From bafa9d95453387814ef25e6b6256ba8db2df612f Mon Sep 17 00:00:00 2001
From: Martin Braun <martin.braun@ettus.com>
Date: Thu, 23 Jan 2020 16:10:22 -0800
Subject: Merge FPGA repository back into UHD repository
MIME-Version: 1.0
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The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
---
 .../lib/white_rabbit/wr_cores_v4_2/Makefile.srcs   |    176 +
 .../bin/sdbfs/sdbfs-empty-i2c-eeprom.bin           |    Bin 0 -> 320 bytes
 .../wr_cores_v4_2/bin/sdbfs/sdbfs-svec-flash.bin   |    Bin 0 -> 6291904 bytes
 .../wr_cores_v4_2/bin/wrpc/wrc_phy16.bram          |  32768 ++++++
 .../wr_cores_v4_2/bin/wrpc/wrc_phy8.bram           |  32768 ++++++
 .../wr_cores_v4_2/bin/wrpc/wrc_phy8.mif            |  32775 ++++++
 .../wr_cores_v4_2/bin/wrpc/wrc_phy8_sim.bram       |  32768 ++++++
 .../wr_cores_v4_2/bin/wrpc/wrc_phy8_sim.mif        |  32775 ++++++
 .../wr_cores_v4_2/board/common/wr_board_pkg.vhd    |    359 +
 .../board/common/xwrc_board_common.vhd             |    552 +
 .../wr_cores_v4_2/board/eeprom/sfp_eeprom.vhd      |    161 +
 .../wr_cores_v4_2/board/eeprom/tb_sfp_eeprom.vhd   |     96 +
 .../wr_cores_v4_2/board/fasec/wr_fasec_pkg.vhd     |    198 +
 .../wr_cores_v4_2/board/fasec/wrc_board_fasec.vhd  |    599 +
 .../wr_cores_v4_2/board/fasec/xwrc_board_fasec.vhd |    623 +
 .../hdl/eb_slave_core/eb_cfg_fifo.vhd              |    177 +
 .../hdl/eb_slave_core/eb_checksum.vhd              |    101 +
 .../hdl/eb_slave_core/eb_commit_fifo.vhd           |    123 +
 .../etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd |    183 +
 .../etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd |    332 +
 .../hdl/eb_slave_core/eb_ethernet_slave.vhd        |    164 +
 .../etherbone-core/hdl/eb_slave_core/eb_fifo.vhd   |    112 +
 .../hdl/eb_slave_core/eb_hdr_pkg.vhd               |    271 +
 .../hdl/eb_slave_core/eb_internals_pkg.vhd         |    418 +
 .../hdl/eb_slave_core/eb_pass_fifo.vhd             |     61 +
 .../hdl/eb_slave_core/eb_slave_fsm.vhd             |    353 +
 .../hdl/eb_slave_core/eb_slave_top.vhd             |    205 +
 .../hdl/eb_slave_core/eb_stream_narrow.vhd         |    150 +
 .../hdl/eb_slave_core/eb_stream_widen.vhd          |    145 +
 .../hdl/eb_slave_core/eb_tag_fifo.vhd              |     61 +
 .../etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd |    170 +
 .../hdl/eb_slave_core/eb_wbm_fifo.vhd              |    171 +
 .../hdl/eb_slave_core/etherbone_pkg.vhd            |    168 +
 .../general-cores/modules/common/gc_crc_gen.vhd    |    280 +
 .../modules/common/gc_extend_pulse.vhd             |     93 +
 .../modules/common/gc_frequency_meter.vhd          |    130 +
 .../modules/common/gc_pulse_synchronizer.vhd       |    134 +
 .../modules/common/gc_pulse_synchronizer2.vhd      |    132 +
 .../general-cores/modules/common/gc_reset.vhd      |     87 +
 .../general-cores/modules/common/gc_sync_ffs.vhd   |    125 +
 .../modules/common/gc_sync_register.vhd            |     88 +
 .../general-cores/modules/common/gencores_pkg.vhd  |    674 +
 .../genrams/common/generic_shiftreg_fifo.vhd       |    168 +
 .../modules/genrams/common/inferred_async_fifo.vhd |    326 +
 .../modules/genrams/common/inferred_sync_fifo.vhd  |    261 +
 .../modules/genrams/generic/generic_async_fifo.vhd |    162 +
 .../modules/genrams/generic/generic_sync_fifo.vhd  |    130 +
 .../general-cores/modules/genrams/genram_pkg.vhd   |    262 +
 .../modules/genrams/memory_loader_pkg.vhd          |    251 +
 .../modules/genrams/xilinx/gc_shiftreg.vhd         |     68 +
 .../modules/genrams/xilinx/generic_dpram.vhd       |    235 +
 .../genrams/xilinx/generic_dpram_dualclock.vhd     |    268 +
 .../genrams/xilinx/generic_dpram_sameclock.vhd     |    304 +
 .../modules/genrams/xilinx/generic_dpram_split.vhd |    233 +
 .../genrams/xilinx/generic_simple_dpram.vhd        |    100 +
 .../wishbone/wb_axi4lite_bridge/axi4_pkg.vhd       |    253 +
 .../wb_axi4lite_bridge/wb_axi4lite_bridge.vhd      |    131 +
 .../wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd     |    196 +
 .../modules/wishbone/wb_crossbar/sdb_rom.vhd       |    160 +
 .../modules/wishbone/wb_crossbar/xwb_crossbar.vhd  |    427 +
 .../wishbone/wb_crossbar/xwb_sdb_crossbar.vhd      |    232 +
 .../modules/wishbone/wb_dpram/xwb_dpram.vhd        |    185 +
 .../wishbone/wb_lm32/generated/lm32_allprofiles.v  | 102181 ++++++++++++++++++
 .../wishbone/wb_lm32/generated/xwb_lm32.vhd        |    825 +
 .../wishbone/wb_lm32/platform/generic/jtag_tap.v   |     20 +
 .../wb_lm32/platform/generic/lm32_multiplier.v     |    119 +
 .../modules/wishbone/wb_lm32/src/jtag_cores.v      |     66 +
 .../modules/wishbone/wb_lm32/src/lm32_adder.v      |    115 +
 .../modules/wishbone/wb_lm32/src/lm32_addsub.v     |     74 +
 .../modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd   |     46 +
 .../modules/wishbone/wb_lm32/src/lm32_include.v    |    320 +
 .../modules/wishbone/wb_lm32/src/lm32_logic_op.v   |     76 +
 .../modules/wishbone/wb_lm32/src/lm32_ram.vhd      |     66 +
 .../modules/wishbone/wb_lm32/src/lm32_shifter.v    |    138 +
 .../wishbone/wb_onewire_master/sockit_owm.v        |    432 +
 .../wb_onewire_master/wb_onewire_master.vhd        |    184 +
 .../wb_onewire_master/xwb_onewire_master.vhd       |    105 +
 .../wishbone/wb_slave_adapter/wb_slave_adapter.vhd |    232 +
 .../modules/wishbone/wb_spi/spi_defines.v          |    167 +
 .../modules/wishbone/wb_spi/timescale.v            |      2 +
 .../modules/wishbone/wb_uart/simple_uart_pkg.vhd   |     99 +
 .../modules/wishbone/wb_uart/simple_uart_wb.vhd    |    315 +
 .../modules/wishbone/wb_uart/uart_async_rx.vhd     |    229 +
 .../modules/wishbone/wb_uart/uart_async_tx.vhd     |    190 +
 .../modules/wishbone/wb_uart/uart_baud_gen.vhd     |     89 +
 .../modules/wishbone/wb_uart/wb_simple_uart.vhd    |    323 +
 .../modules/wishbone/wb_uart/xwb_simple_uart.vhd   |    129 +
 .../modules/wishbone/wbgen2/wbgen2_eic.vhd         |    241 +
 .../modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd   |    144 +
 .../modules/wishbone/wbgen2/wbgen2_pkg.vhd         |    154 +
 .../modules/wishbone/wishbone_pkg.vhd              |   2130 +
 .../wr_cores_v4_2/modules/fabric/wr_fabric_pkg.vhd |    220 +
 .../modules/fabric/xwb_fabric_sink.vhd             |    265 +
 .../modules/fabric/xwb_fabric_source.vhd           |    229 +
 .../wr_cores_v4_2/modules/fabric/xwrf_mux.vhd      |    307 +
 .../modules/timing/dmtd_phase_meas.vhd             |    290 +
 .../modules/timing/dmtd_with_deglitcher.vhd        |    353 +
 .../wr_cores_v4_2/modules/timing/pulse_stamper.vhd |    161 +
 .../modules/wr_dacs/spec_serial_dac.vhd            |    209 +
 .../modules/wr_dacs/spec_serial_dac_arb.vhd        |    187 +
 .../modules/wr_endpoint/endpoint_pkg.vhd           |    469 +
 .../modules/wr_endpoint/endpoint_private_pkg.vhd   |    930 +
 .../modules/wr_endpoint/ep_1000basex_pcs.vhd       |    635 +
 .../modules/wr_endpoint/ep_autonegotiation.vhd     |    281 +
 .../wr_endpoint/ep_clock_alignment_fifo.vhd        |    127 +
 .../modules/wr_endpoint/ep_crc32_pkg.vhd           |    128 +
 .../modules/wr_endpoint/ep_leds_controller.vhd     |    129 +
 .../modules/wr_endpoint/ep_packet_filter.vhd       |    371 +
 .../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd     |    627 +
 .../modules/wr_endpoint/ep_registers_pkg.vhd       |    261 +
 .../modules/wr_endpoint/ep_rtu_header_extract.vhd  |    205 +
 .../modules/wr_endpoint/ep_rx_buffer.vhd           |    321 +
 .../modules/wr_endpoint/ep_rx_crc_size_check.vhd   |    404 +
 .../wr_endpoint/ep_rx_early_address_match.vhd      |    271 +
 .../modules/wr_endpoint/ep_rx_oob_insert.vhd       |    171 +
 .../modules/wr_endpoint/ep_rx_path.vhd             |    515 +
 .../modules/wr_endpoint/ep_rx_pcs_16bit.vhd        |    765 +
 .../modules/wr_endpoint/ep_rx_pcs_8bit.vhd         |    858 +
 .../wr_endpoint/ep_rx_status_reg_insert.vhd        |    153 +
 .../modules/wr_endpoint/ep_rx_vlan_unit.vhd        |    449 +
 .../modules/wr_endpoint/ep_rx_wb_master.vhd        |    226 +
 .../modules/wr_endpoint/ep_sync_detect.vhd         |    280 +
 .../modules/wr_endpoint/ep_sync_detect_16bit.vhd   |    193 +
 .../modules/wr_endpoint/ep_timestamping_unit.vhd   |    424 +
 .../modules/wr_endpoint/ep_ts_counter.vhd          |    152 +
 .../modules/wr_endpoint/ep_tx_crc_inserter.vhd     |    267 +
 .../modules/wr_endpoint/ep_tx_header_processor.vhd |    723 +
 .../modules/wr_endpoint/ep_tx_inject_ctrl.vhd      |    235 +
 .../modules/wr_endpoint/ep_tx_packet_injection.vhd |    251 +
 .../modules/wr_endpoint/ep_tx_path.vhd             |    352 +
 .../modules/wr_endpoint/ep_tx_pcs_16bit.vhd        |    546 +
 .../modules/wr_endpoint/ep_tx_pcs_8bit.vhd         |    514 +
 .../modules/wr_endpoint/ep_tx_vlan_unit.vhd        |    305 +
 .../modules/wr_endpoint/ep_wishbone_controller.vhd |    861 +
 .../modules/wr_endpoint/wr_endpoint.vhd            |   1001 +
 .../modules/wr_endpoint/xwr_endpoint.vhd           |    533 +
 .../modules/wr_mini_nic/minic_wb_slave.vhd         |    602 +
 .../modules/wr_mini_nic/minic_wbgen2_pkg.vhd       |    145 +
 .../modules/wr_mini_nic/wr_mini_nic.vhd            |    817 +
 .../modules/wr_mini_nic/xwr_mini_nic.vhd           |    186 +
 .../modules/wr_pps_gen/pps_gen_wb.vhd              |    820 +
 .../modules/wr_pps_gen/wr_pps_gen.vhd              |    518 +
 .../modules/wr_pps_gen/xwr_pps_gen.vhd             |    162 +
 .../modules/wr_softpll_ng/softpll_pkg.vhd          |     31 +
 .../modules/wr_softpll_ng/spll_aligner.vhd         |    180 +
 .../modules/wr_softpll_ng/spll_wb_slave.vhd        |    939 +
 .../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd      |    207 +
 .../modules/wr_softpll_ng/wr_softpll_ng.vhd        |    809 +
 .../modules/wr_softpll_ng/xwr_softpll_ng.vhd       |    244 +
 .../modules/wr_streamers/dropping_buffer.vhd       |    142 +
 .../modules/wr_streamers/escape_detector.vhd       |    106 +
 .../modules/wr_streamers/escape_inserter.vhd       |    141 +
 .../modules/wr_streamers/streamers_pkg.vhd         |    332 +
 .../modules/wr_streamers/streamers_priv_pkg.vhd    |    201 +
 .../modules/wr_streamers/wr_streamers_wb.vhd       |    706 +
 .../wr_streamers/wr_streamers_wbgen2_pkg.vhd       |    191 +
 .../modules/wr_streamers/xrtx_streamers_stats.vhd  |    362 +
 .../modules/wr_streamers/xrx_streamer.vhd          |    677 +
 .../modules/wr_streamers/xrx_streamers_stats.vhd   |    231 +
 .../modules/wr_streamers/xtx_streamer.vhd          |    597 +
 .../modules/wr_streamers/xtx_streamers_stats.vhd   |    125 +
 .../modules/wr_streamers/xwr_streamers.vhd         |    467 +
 .../modules/wr_tbi_phy/disparity_gen_pkg.vhd       |     90 +
 .../wr_cores_v4_2/modules/wrc_core/wr_core.vhd     |   1157 +
 .../modules/wrc_core/wrc_diags_pkg.vhd             |    134 +
 .../modules/wrc_core/wrc_diags_wb.vhd              |    376 +
 .../wr_cores_v4_2/modules/wrc_core/wrc_periph.vhd  |    520 +
 .../modules/wrc_core/wrc_syscon_pkg.vhd            |    253 +
 .../modules/wrc_core/wrc_syscon_wb.vhd             |    975 +
 .../wr_cores_v4_2/modules/wrc_core/wrcore_pkg.vhd  |    769 +
 .../wr_cores_v4_2/modules/wrc_core/xwr_core.vhd    |    448 +
 .../modules/wrc_core/xwrc_diags_wb.vhd             |    132 +
 .../whiterabbit_gtpe2_channel_wrapper.vhd          |    491 +
 .../whiterabbit_gtpe2_channel_wrapper_gt.vhd       |   1013 +
 ...erabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd |    342 +
 .../wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd  |    521 +
 .../whiterabbit_gtxe2_channel_wrapper_gt.vhd       |    803 +
 .../wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd  |    505 +
 .../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd    |    230 +
 .../xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd |    137 +
 .../whiterabbitgtp_wrapper_tile_spartan6.vhd       |    712 +
 .../wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd    |    816 +
 .../platform/xilinx/wr_xilinx_pkg.vhd              |    192 +
 .../platform/xilinx/xwrc_platform_xilinx.vhd       |   1095 +
 .../lib/white_rabbit/wr_cores_v4_2/source.txt      |      2 +
 185 files changed, 324094 insertions(+)
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/Makefile.srcs
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/sdbfs/sdbfs-empty-i2c-eeprom.bin
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/sdbfs/sdbfs-svec-flash.bin
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy16.bram
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8.bram
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8.mif
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8_sim.bram
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8_sim.mif
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/common/wr_board_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/common/xwrc_board_common.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/eeprom/sfp_eeprom.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/eeprom/tb_sfp_eeprom.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/wr_fasec_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/wrc_board_fasec.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/xwrc_board_fasec.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_crc_gen.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_reset.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_sync_register.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gencores_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/genram_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/wr_fabric_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwb_fabric_sink.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwb_fabric_source.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwrf_mux.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/dmtd_phase_meas.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/dmtd_with_deglitcher.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/pulse_stamper.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_dacs/spec_serial_dac.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_dacs/spec_serial_dac_arb.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/endpoint_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/endpoint_private_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_1000basex_pcs.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_autonegotiation.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_crc32_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_leds_controller.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_packet_filter.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_registers_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rtu_header_extract.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_buffer.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_crc_size_check.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_early_address_match.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_oob_insert.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_path.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_vlan_unit.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_wb_master.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_sync_detect.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_sync_detect_16bit.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_timestamping_unit.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_ts_counter.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_crc_inserter.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_header_processor.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_inject_ctrl.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_packet_injection.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_path.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_vlan_unit.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_wishbone_controller.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/wr_endpoint.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/xwr_endpoint.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/minic_wb_slave.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/wr_mini_nic.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/xwr_mini_nic.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/pps_gen_wb.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/wr_pps_gen.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/xwr_pps_gen.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/softpll_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_aligner.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_wb_slave.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/wr_softpll_ng.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/xwr_softpll_ng.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/dropping_buffer.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/escape_detector.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/escape_inserter.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/streamers_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/streamers_priv_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/wr_streamers_wb.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrtx_streamers_stats.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrx_streamer.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrx_streamers_stats.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xtx_streamer.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xtx_streamers_stats.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xwr_streamers.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_tbi_phy/disparity_gen_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wr_core.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_diags_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_diags_wb.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_periph.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_syscon_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_syscon_wb.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrcore_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/xwr_core.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/xwrc_diags_wb.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_xilinx_pkg.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/xwrc_platform_xilinx.vhd
 create mode 100644 fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/source.txt

(limited to 'fpga/usrp3/lib/white_rabbit')

diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/Makefile.srcs b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/Makefile.srcs
new file mode 100644
index 000000000..fce6adefa
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/Makefile.srcs
@@ -0,0 +1,176 @@
+#
+# Copyright 2018 Ettus Research LLC
+#
+
+##################################################
+# White Rabbit Sources
+##################################################
+WHITE_RABBIT_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/white_rabbit/wr_cores_v4_2/, \
+platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd \
+platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd \
+platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \
+platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd \
+ip_cores/general-cores/modules/common/gc_reset.vhd \
+ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
+ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd \
+modules/fabric/wr_fabric_pkg.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd \
+modules/wr_streamers/escape_detector.vhd \
+modules/wr_streamers/dropping_buffer.vhd \
+modules/wr_streamers/escape_inserter.vhd \
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+modules/wrc_core/wrc_syscon_pkg.vhd \
+modules/wr_endpoint/endpoint_pkg.vhd \
+modules/wrc_core/wrcore_pkg.vhd \
+modules/wr_streamers/streamers_pkg.vhd \
+modules/wr_streamers/xrx_streamers_stats.vhd \
+modules/wr_streamers/xtx_streamers_stats.vhd \
+modules/timing/pulse_stamper.vhd \
+modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd \
+modules/wr_streamers/streamers_priv_pkg.vhd \
+modules/wr_streamers/xrtx_streamers_stats.vhd \
+modules/wr_streamers/wr_streamers_wb.vhd \
+modules/wr_pps_gen/pps_gen_wb.vhd \
+ip_cores/general-cores/modules/common/gencores_pkg.vhd \
+ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
+modules/wr_softpll_ng/spll_aligner.vhd \
+modules/wr_endpoint/ep_registers_pkg.vhd \
+modules/wr_endpoint/endpoint_private_pkg.vhd \
+modules/wr_endpoint/ep_leds_controller.vhd \
+modules/wr_endpoint/ep_sync_detect.vhd \
+modules/wr_endpoint/ep_sync_detect_16bit.vhd \
+ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
+modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd \
+modules/wr_endpoint/ep_autonegotiation.vhd \
+modules/wr_endpoint/ep_tx_packet_injection.vhd \
+modules/wr_endpoint/ep_tx_inject_ctrl.vhd \
+modules/wr_endpoint/ep_tx_header_processor.vhd \
+modules/wr_endpoint/ep_rx_vlan_unit.vhd \
+ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
+ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd \
+ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
+ip_cores/general-cores/modules/common/gc_sync_register.vhd \
+modules/wr_endpoint/ep_rx_oob_insert.vhd \
+ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
+modules/wr_endpoint/ep_crc32_pkg.vhd \
+modules/wr_endpoint/ep_rx_crc_size_check.vhd \
+modules/wr_endpoint/ep_rtu_header_extract.vhd \
+modules/wr_endpoint/ep_rx_status_reg_insert.vhd \
+modules/wr_endpoint/ep_rx_wb_master.vhd \
+modules/wr_endpoint/ep_ts_counter.vhd \
+modules/wr_endpoint/ep_wishbone_controller.vhd \
+ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
+ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
+ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
+modules/wr_mini_nic/minic_wbgen2_pkg.vhd \
+modules/wr_mini_nic/minic_wb_slave.vhd \
+ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
+ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
+ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v \
+ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
+ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
+ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v \
+ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
+ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
+ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd \
+ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
+ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
+ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
+ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
+ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
+ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
+ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
+modules/wrc_core/wrc_syscon_wb.vhd \
+ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd \
+ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
+ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
+ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
+ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
+ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
+ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
+ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
+modules/wrc_core/wrc_diags_wb.vhd \
+ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
+ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
+ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
+ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
+modules/fabric/xwrf_mux.vhd \
+ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd \
+ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd \
+ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd \
+board/eeprom/sfp_eeprom.vhd \
+platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd \
+platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd \
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+ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd \
+ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd \
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+board/common/wr_board_pkg.vhd \
+board/common/xwrc_board_common.vhd \
+))
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/sdbfs/sdbfs-empty-i2c-eeprom.bin b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/sdbfs/sdbfs-empty-i2c-eeprom.bin
new file mode 100644
index 000000000..825733426
Binary files /dev/null and b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/sdbfs/sdbfs-empty-i2c-eeprom.bin differ
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/sdbfs/sdbfs-svec-flash.bin b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/sdbfs/sdbfs-svec-flash.bin
new file mode 100644
index 000000000..0da8a2b8e
Binary files /dev/null and b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/sdbfs/sdbfs-svec-flash.bin differ
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy16.bram b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy16.bram
new file mode 100644
index 000000000..05fabcd35
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy16.bram
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new file mode 100644
index 000000000..d02bac529
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8.bram
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diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8.mif b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8.mif
new file mode 100644
index 000000000..83f979eb6
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8.mif
@@ -0,0 +1,32775 @@
+DEPTH = 32768;
+WIDTH = 32;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT
+BEGIN
+0 : 98000000;
+1 : D0000000;
+2 : D0200000;
+3 : 78010000;
+4 : 38210000;
+5 : D0E10000;
+6 : F800003A;
+7 : 34000000;
+8 : 00000000;
+9 : 00000000;
+a : 00000000;
+b : 00000000;
+c : 00000000;
+d : 00000000;
+e : 00000000;
+f : 00000000;
+10 : 00000000;
+11 : 00000000;
+12 : 00000000;
+13 : 00000000;
+14 : 00000000;
+15 : 00000000;
+16 : 00000000;
+17 : 00000000;
+18 : 00000000;
+19 : 00000000;
+1a : 00000000;
+1b : 00000000;
+1c : 00000000;
+1d : 00000000;
+1e : 00000000;
+1f : 00000000;
+20 : 57525043;
+21 : 2D2D2D2D;
+22 : 01234567;
+23 : 89ABCDEF;
+24 : 0001BFD8;
+25 : 00000000;
+26 : 00019828;
+27 : 0001AD84;
+28 : 00000000;
+29 : 02140000;
+2a : 00000000;
+2b : 00000000;
+2c : 00000000;
+2d : 00000000;
+2e : 00000000;
+2f : 00000000;
+30 : 5B9D0000;
+31 : F800001E;
+32 : 34010002;
+33 : F800519E;
+34 : E000002E;
+35 : 34000000;
+36 : 34000000;
+37 : 34000000;
+38 : 00000000;
+39 : 00000000;
+3a : 00000000;
+3b : 00000000;
+3c : 00000000;
+3d : 00000000;
+3e : 00000000;
+3f : 00000000;
+40 : 98000000;
+41 : 781C0001;
+42 : 3B9CFFFC;
+43 : 78010001;
+44 : 3821B0B0;
+45 : 34020000;
+46 : 78030001;
+47 : 3863C2C8;
+48 : C8611800;
+49 : F800580B;
+4a : 34010000;
+4b : 34020000;
+4c : 34030000;
+4d : F8000109;
+4e : E0000000;
+4f : 379CFFC4;
+50 : 5B810004;
+51 : 5B820008;
+52 : 5B83000C;
+53 : 5B840010;
+54 : 5B850014;
+55 : 5B860018;
+56 : 5B87001C;
+57 : 5B880020;
+58 : 5B890024;
+59 : 5B8A0028;
+5a : 5B9E0034;
+5b : 5B9F0038;
+5c : 2B81003C;
+5d : 5B810030;
+5e : BB800800;
+5f : 3421003C;
+60 : 5B81002C;
+61 : C3A00000;
+62 : 2B810004;
+63 : 2B820008;
+64 : 2B83000C;
+65 : 2B840010;
+66 : 2B850014;
+67 : 2B860018;
+68 : 2B87001C;
+69 : 2B880020;
+6a : 2B890024;
+6b : 2B8A0028;
+6c : 2B9D0030;
+6d : 2B9E0034;
+6e : 2B9F0038;
+6f : 2B9C002C;
+70 : 34000000;
+71 : C3C00000;
+72 : 90001000;
+73 : 3401FFFE;
+74 : A0410800;
+75 : D0010000;
+76 : 90201000;
+77 : 3401FFFE;
+78 : A0410800;
+79 : D0210000;
+7a : C3A00000;
+7b : 90001000;
+7c : 3401FFFE;
+7d : A0410800;
+7e : D0010000;
+7f : 90201000;
+80 : 38420001;
+81 : D0220000;
+82 : 38210001;
+83 : D0010000;
+84 : C3A00000;
+85 : 379CFFFC;
+86 : 5B9D0004;
+87 : F8003D83;
+88 : 78020001;
+89 : 78030001;
+8a : 3863B0C4;
+8b : 3842B0C8;
+8c : 28640000;
+8d : 28450000;
+8e : 58610000;
+8f : 340303E8;
+90 : C8A42000;
+91 : B4812000;
+92 : 58440000;
+93 : 34010000;
+94 : 50640009;
+95 : 78010000;
+96 : 382100A0;
+97 : 3484FC18;
+98 : 58440000;
+99 : 28220000;
+9a : 34420001;
+9b : 58220000;
+9c : 34010001;
+9d : 2B9D0004;
+9e : 379C0004;
+9f : C3A00000;
+a0 : 379CFFFC;
+a1 : 5B9D0004;
+a2 : F8003D68;
+a3 : 78020001;
+a4 : 3842B0C4;
+a5 : 58410000;
+a6 : 2B9D0004;
+a7 : 379C0004;
+a8 : C3A00000;
+a9 : 379CFFF4;
+aa : 5B9D0004;
+ab : F8003EDF;
+ac : F800384D;
+ad : 78010001;
+ae : 38216720;
+af : F800376F;
+b0 : 34010001;
+b1 : F8003D47;
+b2 : 78010001;
+b3 : 3821C284;
+b4 : F8003D29;
+b5 : F8004808;
+b6 : F8004A2D;
+b7 : 78010001;
+b8 : 3821C1F0;
+b9 : 58200000;
+ba : F8004953;
+bb : F8004054;
+bc : 34010000;
+bd : F8003B6C;
+be : 34010000;
+bf : 34020050;
+c0 : F8004403;
+c1 : 37820008;
+c2 : 34010000;
+c3 : F80044CC;
+c4 : 3402FFFF;
+c5 : 5C220006;
+c6 : 78010001;
+c7 : 3821673C;
+c8 : F8003756;
+c9 : 34010022;
+ca : 33810008;
+cb : 4384000A;
+cc : 4385000B;
+cd : 4386000C;
+ce : 4387000D;
+cf : 43830009;
+d0 : 43820008;
+d1 : 78010001;
+d2 : 38216760;
+d3 : F800374B;
+d4 : F8003DB5;
+d5 : 37810008;
+d6 : F8003950;
+d7 : 340100C8;
+d8 : F8003D37;
+d9 : 34020001;
+da : 34010001;
+db : F800389D;
+dc : F8003B80;
+dd : F80041E3;
+de : F800042E;
+df : 78020001;
+e0 : 38429700;
+e1 : 34010002;
+e2 : F8003FB9;
+e3 : F80051B1;
+e4 : F8002B51;
+e5 : F8002322;
+e6 : 78030001;
+e7 : 38638EC4;
+e8 : 78010001;
+e9 : 28620000;
+ea : 3821B0B0;
+eb : 58200000;
+ec : 78010001;
+ed : 3821F800;
+ee : 58220000;
+ef : 34010003;
+f0 : F800047D;
+f1 : F8000430;
+f2 : 78020001;
+f3 : 3842B0B8;
+f4 : 34010000;
+f5 : F800421A;
+f6 : F8003D14;
+f7 : 78020001;
+f8 : 3842B0BC;
+f9 : 58410000;
+fa : 2B9D0004;
+fb : 379C000C;
+fc : C3A00000;
+fd : 379CFFF8;
+fe : 5B8B0008;
+ff : 5B9D0004;
+100 : 34010000;
+101 : F80038A9;
+102 : B8205800;
+103 : 78010001;
+104 : 3821B0C0;
+105 : 28240000;
+106 : 7D620000;
+107 : 64830000;
+108 : A0431800;
+109 : 4460000D;
+10a : 78010001;
+10b : 3821C2AC;
+10c : 28210000;
+10d : 34020002;
+10e : 58220004;
+10f : F8003DDC;
+110 : F8000411;
+111 : 78010001;
+112 : 3821C2A4;
+113 : 34020001;
+114 : 58220000;
+115 : E0000014;
+116 : 65610000;
+117 : 7C840000;
+118 : A0240800;
+119 : 44230012;
+11a : 78010001;
+11b : 3821C2AC;
+11c : 28210000;
+11d : 34020002;
+11e : 58220008;
+11f : 78010001;
+120 : 3821C2A4;
+121 : 58220000;
+122 : F8000425;
+123 : 34010002;
+124 : 34020000;
+125 : 34030001;
+126 : F8005179;
+127 : 34010000;
+128 : F8004217;
+129 : 34010001;
+12a : E0000008;
+12b : FC411000;
+12c : 78010001;
+12d : C8021000;
+12e : 3821C2A4;
+12f : 20420003;
+130 : 58220000;
+131 : 34010000;
+132 : 78020001;
+133 : 3842B0C0;
+134 : 584B0000;
+135 : 2B9D0004;
+136 : 2B8B0008;
+137 : 379C0008;
+138 : C3A00000;
+139 : 379CFFF8;
+13a : 5B8B0008;
+13b : 5B9D0004;
+13c : 78010001;
+13d : 3821B0B0;
+13e : 28220000;
+13f : 34010001;
+140 : 5C41000F;
+141 : F8001FFC;
+142 : B8205800;
+143 : F80037E4;
+144 : 3402001B;
+145 : 44220005;
+146 : 78020001;
+147 : 384296F8;
+148 : 28410000;
+149 : 5C200008;
+14a : F80022BD;
+14b : 78020001;
+14c : 3842B0B0;
+14d : 58400000;
+14e : E0000003;
+14f : F80022C2;
+150 : B8205800;
+151 : B9600800;
+152 : 2B9D0004;
+153 : 2B8B0008;
+154 : 379C0008;
+155 : C3A00000;
+156 : 379CFFC8;
+157 : 5B8B0034;
+158 : 5B8C0030;
+159 : 5B8D002C;
+15a : 5B8E0028;
+15b : 5B8F0024;
+15c : 5B900020;
+15d : 5B91001C;
+15e : 5B920018;
+15f : 5B930014;
+160 : 5B940010;
+161 : 5B95000C;
+162 : 5B960008;
+163 : 5B9D0004;
+164 : 780B0001;
+165 : 780C0001;
+166 : F80053EA;
+167 : 396BAEEC;
+168 : 398CB0AC;
+169 : E0000005;
+16a : 29610008;
+16b : 44200002;
+16c : D8200000;
+16d : 356B0020;
+16e : 558BFFFC;
+16f : 780B0001;
+170 : 78010001;
+171 : 396BAEEC;
+172 : 78140001;
+173 : 78100001;
+174 : 38218EC8;
+175 : 780F0001;
+176 : 780E0001;
+177 : 78120001;
+178 : 78110001;
+179 : 3A94B0AC;
+17a : 3A10B0B8;
+17b : 28330000;
+17c : 39EFB0BC;
+17d : 39CEB0B4;
+17e : 3A5267C8;
+17f : 3A316794;
+180 : B960A800;
+181 : E000003C;
+182 : 2961000C;
+183 : 5C200005;
+184 : 29610010;
+185 : 34210001;
+186 : 59610010;
+187 : E000000B;
+188 : 29620004;
+189 : 44400003;
+18a : 28420000;
+18b : 44400007;
+18c : D8200000;
+18d : 29620010;
+18e : B9606000;
+18f : B4411000;
+190 : 59620010;
+191 : 5C200002;
+192 : BAA06000;
+193 : 37820038;
+194 : 34010000;
+195 : F800417A;
+196 : F8003C74;
+197 : B820B000;
+198 : 2A020000;
+199 : 2B810038;
+19a : C8221000;
+19b : 4C400002;
+19c : B4531000;
+19d : 29830018;
+19e : B4431000;
+19f : 59820018;
+1a0 : 52620006;
+1a1 : C8531000;
+1a2 : 59820018;
+1a3 : 29820014;
+1a4 : 34420001;
+1a5 : 59820014;
+1a6 : 29ED0000;
+1a7 : 5A010000;
+1a8 : CACD6800;
+1a9 : 4DA00002;
+1aa : 35AD03E8;
+1ab : 2983001C;
+1ac : 506D0008;
+1ad : 29C10000;
+1ae : 44200005;
+1af : 29820000;
+1b0 : BA200800;
+1b1 : B9A02000;
+1b2 : F800366C;
+1b3 : 598D001C;
+1b4 : 29C10000;
+1b5 : 44200006;
+1b6 : 502D0005;
+1b7 : 29820000;
+1b8 : BA400800;
+1b9 : B9A01800;
+1ba : F8003664;
+1bb : 59F60000;
+1bc : 356B0020;
+1bd : 568BFFC5;
+1be : F8005391;
+1bf : BAA05800;
+1c0 : E3FFFFFD;
+1c1 : 379CFFC0;
+1c2 : 5B8B0014;
+1c3 : 5B8C0010;
+1c4 : 5B8D000C;
+1c5 : 5B8E0008;
+1c6 : 5B9D0004;
+1c7 : 5B83002C;
+1c8 : 78030001;
+1c9 : 3863B0CC;
+1ca : 5B820028;
+1cb : 5B840030;
+1cc : 5B850034;
+1cd : 5B860038;
+1ce : 5B87003C;
+1cf : 5B880040;
+1d0 : 286D0000;
+1d1 : B8205800;
+1d2 : B8407000;
+1d3 : 34030000;
+1d4 : 44200002;
+1d5 : 2823001C;
+1d6 : B86D1800;
+1d7 : 0063001C;
+1d8 : 4460001E;
+1d9 : 780C0001;
+1da : 398CB0CC;
+1db : 39A10001;
+1dc : 59810000;
+1dd : 29610038;
+1de : 37820018;
+1df : 28230000;
+1e0 : B9600800;
+1e1 : D8600000;
+1e2 : 598D0000;
+1e3 : 2B840020;
+1e4 : 2F830024;
+1e5 : 296B03D4;
+1e6 : 3C840010;
+1e7 : 780C0001;
+1e8 : B8830800;
+1e9 : 78030001;
+1ea : 38638ECC;
+1eb : 28620000;
+1ec : 398C6814;
+1ed : F800553B;
+1ee : 2B83001C;
+1ef : B8202000;
+1f0 : B9601000;
+1f1 : B9800800;
+1f2 : F800362C;
+1f3 : B9C00800;
+1f4 : 3782002C;
+1f5 : F8003607;
+1f6 : 2B9D0004;
+1f7 : 2B8B0014;
+1f8 : 2B8C0010;
+1f9 : 2B8D000C;
+1fa : 2B8E0008;
+1fb : 379C0040;
+1fc : C3A00000;
+1fd : 379CFFFC;
+1fe : 5B9D0004;
+1ff : B8402800;
+200 : 5C600005;
+201 : 78020001;
+202 : 38426830;
+203 : B8A01800;
+204 : E000000C;
+205 : 34020001;
+206 : 5C620006;
+207 : 78020001;
+208 : 3842684C;
+209 : B8A01800;
+20a : 28240008;
+20b : E0000005;
+20c : 28240004;
+20d : 78020001;
+20e : 38426864;
+20f : B8A01800;
+210 : FBFFFFB1;
+211 : 2B9D0004;
+212 : 379C0004;
+213 : C3A00000;
+214 : 379CFFDC;
+215 : 5B8B0024;
+216 : 5B8C0020;
+217 : 5B8D001C;
+218 : 5B8E0018;
+219 : 5B8F0014;
+21a : 5B900010;
+21b : 5B9D000C;
+21c : B8205800;
+21d : B8407000;
+21e : B8606800;
+21f : 4C0300B6;
+220 : 40430000;
+221 : 2828010C;
+222 : 28290108;
+223 : 2063000F;
+224 : 28260104;
+225 : 5B830004;
+226 : 0863000C;
+227 : 78020001;
+228 : 01070010;
+229 : 38429768;
+22a : 2108FFFF;
+22b : B4431000;
+22c : 090803E8;
+22d : 28420000;
+22e : 3D290010;
+22f : 78040001;
+230 : 01080010;
+231 : 5B820008;
+232 : 34030001;
+233 : 34020005;
+234 : 3884687C;
+235 : B9A02800;
+236 : B9273800;
+237 : F80000A2;
+238 : 34010021;
+239 : 4C2D009C;
+23a : 41C10000;
+23b : 3402000D;
+23c : 2021000F;
+23d : 48220010;
+23e : 3C210002;
+23f : 78020001;
+240 : 38428FA0;
+241 : B4411000;
+242 : 28410000;
+243 : 482D000A;
+244 : 41C20001;
+245 : 34010002;
+246 : 2042000F;
+247 : 5C410006;
+248 : B9600800;
+249 : B9C01000;
+24a : B9A01800;
+24b : F80017D2;
+24c : 44200003;
+24d : 340D0000;
+24e : 340E0000;
+24f : 296C0010;
+250 : 5960000C;
+251 : 29610000;
+252 : 45800003;
+253 : 29820000;
+254 : 44410013;
+255 : 34020001;
+256 : 780C0001;
+257 : 5962000C;
+258 : 398C9DA8;
+259 : E0000006;
+25a : 5C410004;
+25b : 596C0010;
+25c : 5D80000B;
+25d : E0000004;
+25e : 358C000C;
+25f : 29820000;
+260 : 5C40FFFA;
+261 : 296203D4;
+262 : 78010001;
+263 : 382168AC;
+264 : F80035BA;
+265 : 34012710;
+266 : E0000066;
+267 : 59610004;
+268 : 2961000C;
+269 : 59600008;
+26a : 44200006;
+26b : 29820004;
+26c : B9600800;
+26d : 34030000;
+26e : B9A02000;
+26f : FBFFFF8E;
+270 : 45C00033;
+271 : 29610030;
+272 : 416503A6;
+273 : 2821000C;
+274 : 4021001E;
+275 : 44250008;
+276 : 78040001;
+277 : B9600800;
+278 : 34020005;
+279 : 34030001;
+27a : 388468CC;
+27b : F800005E;
+27c : E0000025;
+27d : 417003A7;
+27e : 22100001;
+27f : 46000007;
+280 : 78040001;
+281 : B9600800;
+282 : 34020005;
+283 : 34030001;
+284 : 388468E8;
+285 : E000000C;
+286 : 29620358;
+287 : 356F03C0;
+288 : B9E00800;
+289 : 3403000A;
+28a : F800552B;
+28b : 5C300008;
+28c : 78040001;
+28d : B9600800;
+28e : 34020005;
+28f : 34030001;
+290 : 38846904;
+291 : F8000048;
+292 : E000000F;
+293 : 416203A1;
+294 : 3401000B;
+295 : 5C41000E;
+296 : 29620358;
+297 : B9E00800;
+298 : 34030008;
+299 : F800551C;
+29a : 5C200009;
+29b : 29610358;
+29c : 2D6203C8;
+29d : 2C210008;
+29e : 50410003;
+29f : 34010007;
+2a0 : 59610004;
+2a1 : 340D0000;
+2a2 : 340E0000;
+2a3 : 29610004;
+2a4 : 29620000;
+2a5 : 5C410013;
+2a6 : 5DA00003;
+2a7 : 3401000F;
+2a8 : 316103A1;
+2a9 : 29840008;
+2aa : B9A01800;
+2ab : B9600800;
+2ac : B9C01000;
+2ad : D8800000;
+2ae : B8201800;
+2af : 44200006;
+2b0 : 296203D4;
+2b1 : 29840004;
+2b2 : 78010001;
+2b3 : 3821691C;
+2b4 : F800356A;
+2b5 : 29610004;
+2b6 : 29620000;
+2b7 : 4441000F;
+2b8 : 59610000;
+2b9 : B9600800;
+2ba : F80000E6;
+2bb : 41610020;
+2bc : 29620010;
+2bd : 34030002;
+2be : 202100F9;
+2bf : 31610020;
+2c0 : 28420004;
+2c1 : B9600800;
+2c2 : 34040000;
+2c3 : FBFFFF3A;
+2c4 : 34010000;
+2c5 : E0000007;
+2c6 : 29820004;
+2c7 : B9600800;
+2c8 : 34030001;
+2c9 : 34040000;
+2ca : FBFFFF33;
+2cb : 29610008;
+2cc : 2B9D000C;
+2cd : 2B8B0024;
+2ce : 2B8C0020;
+2cf : 2B8D001C;
+2d0 : 2B8E0018;
+2d1 : 2B8F0014;
+2d2 : 2B900010;
+2d3 : 379C0024;
+2d4 : C3A00000;
+2d5 : 34010000;
+2d6 : 340D0000;
+2d7 : 340E0000;
+2d8 : E3FFFF66;
+2d9 : 379CFFE4;
+2da : 5B8B0008;
+2db : 5B9D0004;
+2dc : 5B84000C;
+2dd : 5B850010;
+2de : B8805800;
+2df : 5B860014;
+2e0 : 78040001;
+2e1 : 5B870018;
+2e2 : 5B88001C;
+2e3 : 38846938;
+2e4 : 34050000;
+2e5 : 44200003;
+2e6 : 282403D4;
+2e7 : 2825001C;
+2e8 : 78060001;
+2e9 : 38C6B0CC;
+2ea : 28C10000;
+2eb : 3C420002;
+2ec : B8A12800;
+2ed : 80A22800;
+2ee : 20A5000F;
+2ef : 5465000C;
+2f0 : 78050001;
+2f1 : 38A58FE8;
+2f2 : B4A22800;
+2f3 : 78060001;
+2f4 : 28A20000;
+2f5 : B8C00800;
+2f6 : 38216940;
+2f7 : F8003527;
+2f8 : B9600800;
+2f9 : 37820010;
+2fa : F8003502;
+2fb : 2B9D0004;
+2fc : 2B8B0008;
+2fd : 379C001C;
+2fe : C3A00000;
+2ff : 379CFFF8;
+300 : 5B8B0008;
+301 : 5B9D0004;
+302 : 3402001C;
+303 : B8201800;
+304 : 340B0000;
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diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8_sim.bram b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8_sim.bram
new file mode 100644
index 000000000..8d4e519ba
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/bin/wrpc/wrc_phy8_sim.bram
@@ -0,0 +1,32768 @@
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new file mode 100644
index 000000000..1680114ee
--- /dev/null
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+17a0 : 52455155;
+17a1 : 45535400;
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+7f6b : 00000000;
+7f6c : 00000000;
+7f6d : 00000000;
+7f6e : 00000000;
+7f6f : 00000000;
+7f70 : 00000000;
+7f71 : 00000000;
+7f72 : 00000000;
+7f73 : 00000000;
+7f74 : 00000000;
+7f75 : 00000000;
+7f76 : 00000000;
+7f77 : 00000000;
+7f78 : 00000000;
+7f79 : 00000000;
+7f7a : 00000000;
+7f7b : 00000000;
+7f7c : 00000000;
+7f7d : 00000000;
+7f7e : 00000000;
+7f7f : 00000000;
+7f80 : 00000000;
+7f81 : 00000000;
+7f82 : 00000000;
+7f83 : 00000000;
+7f84 : 00000000;
+7f85 : 00000000;
+7f86 : 00000000;
+7f87 : 00000000;
+7f88 : 00000000;
+7f89 : 00000000;
+7f8a : 00000000;
+7f8b : 00000000;
+7f8c : 00000000;
+7f8d : 00000000;
+7f8e : 00000000;
+7f8f : 00000000;
+7f90 : 00000000;
+7f91 : 00000000;
+7f92 : 00000000;
+7f93 : 00000000;
+7f94 : 00000000;
+7f95 : 00000000;
+7f96 : 00000000;
+7f97 : 00000000;
+7f98 : 00000000;
+7f99 : 00000000;
+7f9a : 00000000;
+7f9b : 00000000;
+7f9c : 00000000;
+7f9d : 00000000;
+7f9e : 00000000;
+7f9f : 00000000;
+7fa0 : 00000000;
+7fa1 : 00000000;
+7fa2 : 00000000;
+7fa3 : 00000000;
+7fa4 : 00000000;
+7fa5 : 00000000;
+7fa6 : 00000000;
+7fa7 : 00000000;
+7fa8 : 00000000;
+7fa9 : 00000000;
+7faa : 00000000;
+7fab : 00000000;
+7fac : 00000000;
+7fad : 00000000;
+7fae : 00000000;
+7faf : 00000000;
+7fb0 : 00000000;
+7fb1 : 00000000;
+7fb2 : 00000000;
+7fb3 : 00000000;
+7fb4 : 00000000;
+7fb5 : 00000000;
+7fb6 : 00000000;
+7fb7 : 00000000;
+7fb8 : 00000000;
+7fb9 : 00000000;
+7fba : 00000000;
+7fbb : 00000000;
+7fbc : 00000000;
+7fbd : 00000000;
+7fbe : 00000000;
+7fbf : 00000000;
+7fc0 : 00000000;
+7fc1 : 00000000;
+7fc2 : 00000000;
+7fc3 : 00000000;
+7fc4 : 00000000;
+7fc5 : 00000000;
+7fc6 : 00000000;
+7fc7 : 00000000;
+7fc8 : 00000000;
+7fc9 : 00000000;
+7fca : 00000000;
+7fcb : 00000000;
+7fcc : 00000000;
+7fcd : 00000000;
+7fce : 00000000;
+7fcf : 00000000;
+7fd0 : 00000000;
+7fd1 : 00000000;
+7fd2 : 00000000;
+7fd3 : 00000000;
+7fd4 : 00000000;
+7fd5 : 00000000;
+7fd6 : 00000000;
+7fd7 : 00000000;
+7fd8 : 00000000;
+7fd9 : 00000000;
+7fda : 00000000;
+7fdb : 00000000;
+7fdc : 00000000;
+7fdd : 00000000;
+7fde : 00000000;
+7fdf : 00000000;
+7fe0 : 00000000;
+7fe1 : 00000000;
+7fe2 : 00000000;
+7fe3 : 00000000;
+7fe4 : 00000000;
+7fe5 : 00000000;
+7fe6 : 00000000;
+7fe7 : 00000000;
+7fe8 : 00000000;
+7fe9 : 00000000;
+7fea : 00000000;
+7feb : 00000000;
+7fec : 00000000;
+7fed : 00000000;
+7fee : 00000000;
+7fef : 00000000;
+7ff0 : 00000000;
+7ff1 : 00000000;
+7ff2 : 00000000;
+7ff3 : 00000000;
+7ff4 : 00000000;
+7ff5 : 00000000;
+7ff6 : 00000000;
+7ff7 : 00000000;
+7ff8 : 00000000;
+7ff9 : 00000000;
+7ffa : 00000000;
+7ffb : 00000000;
+7ffc : 00000000;
+7ffd : 00000000;
+7ffe : 00000000;
+7fff : 00000000;
+END;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/common/wr_board_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/common/wr_board_pkg.vhd
new file mode 100644
index 000000000..81a61a583
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/common/wr_board_pkg.vhd
@@ -0,0 +1,359 @@
+-------------------------------------------------------------------------------
+-- Title      : Common WRPC Wrapper package
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : xwrc_board_common.vhd
+-- Company    : CERN (BE-CO-HT)
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2017 CERN
+--
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.wrcore_pkg.all;
+use work.streamers_pkg.all;
+
+package wr_board_pkg is
+
+  type t_board_fabric_iface is (PLAIN, STREAMERS, ETHERBONE, always_last_invalid);
+
+  -- TODO: using these default paths requires absolute path. If relative path is used,
+  --       they work only for reference designs by chance. Once we figure out how to
+  --       automatically figure out absolute path of <wr-cores location>/bin/wrpc, we
+  --       will be able to use this concept in f_find_default_lm32_firmware()
+  constant dpram_initf_default_altera_phy8     : string := "";
+  constant dpram_initf_default_xilinx_phy8     : string := "";
+  constant dpram_initf_default_altera_phy8_sim : string := "";
+  constant dpram_initf_default_xilinx_phy8_sim : string := "";
+
+  procedure f_check_fabric_iface_type (
+    constant iface_type : in t_board_fabric_iface);
+
+  procedure f_check_diag_id (
+    constant diag_id, diag_ver : in integer);
+
+  function f_str2iface_type (
+    constant iface_str : string(1 to 9))
+    return t_board_fabric_iface;
+
+  function f_pick_diag_val (
+    iface           : t_board_fabric_iface;
+    streamers_val   : integer;
+    application_val : integer
+    ) return integer;
+
+  function f_pick_diag_size (
+    iface            : t_board_fabric_iface;
+    streamers_size   : integer;
+    application_size : integer
+    ) return integer;
+
+  function f_vectorize_diag (
+    diag_in          : t_generic_word_array;
+    diag_vector_size : integer)
+    return std_logic_vector;
+
+  function f_de_vectorize_diag (
+    diag_in          : std_logic_vector;
+    diag_vector_size : integer)
+    return t_generic_word_array;
+
+  function f_find_default_lm32_firmware (
+    dpram_initf : string;
+    simulation  : integer;
+    pcs_16_bit  : boolean)
+    return string;
+
+  component xwrc_board_common is
+    generic (
+      g_simulation                : integer                        := 0;
+      g_with_external_clock_input : boolean                        := TRUE;
+      g_board_name                : string                         := "NA  ";
+      g_flash_secsz_kb            : integer                        := 256;        -- default for M25P128
+      g_flash_sdbfs_baddr         : integer                        := 16#600000#; -- default for M25P128
+      g_phys_uart                 : boolean                        := TRUE;
+      g_virtual_uart              : boolean                        := TRUE;
+      g_aux_clks                  : integer                        := 0;
+      g_ep_rxbuf_size             : integer                        := 1024;
+      g_tx_runt_padding           : boolean                        := TRUE;
+      g_dpram_initf               : string                         := "";
+      g_dpram_size                : integer                        := 131072/4;
+      g_interface_mode            : t_wishbone_interface_mode      := PIPELINED;
+      g_address_granularity       : t_wishbone_address_granularity := BYTE;
+      g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
+      g_softpll_enable_debugger   : boolean                        := FALSE;
+      g_vuart_fifo_size           : integer                        := 1024;
+      g_pcs_16bit                 : boolean                        := FALSE;
+      g_diag_id                   : integer                        := 0;
+      g_diag_ver                  : integer                        := 0;
+      g_diag_ro_size              : integer                        := 0;
+      g_diag_rw_size              : integer                        := 0;
+      g_streamers_op_mode         : t_streamers_op_mode            := TX_AND_RX;
+      g_tx_streamer_params        : t_tx_streamer_params           := c_tx_streamer_params_defaut;
+      g_rx_streamer_params        : t_rx_streamer_params           := c_rx_streamer_params_defaut;
+      g_fabric_iface              : t_board_fabric_iface           := PLAIN);
+    port (
+      clk_sys_i            : in  std_logic;
+      clk_dmtd_i           : in  std_logic;
+      clk_ref_i            : in  std_logic;
+      clk_aux_i            : in  std_logic_vector(g_aux_clks-1 downto 0)          := (others => '0');
+      clk_10m_ext_i        : in  std_logic                                        := '0';
+      clk_ext_mul_i        : in  std_logic                                        := '0';
+      clk_ext_mul_locked_i : in  std_logic                                        := '1';
+      clk_ext_stopped_i    : in  std_logic                                        := '0';
+      clk_ext_rst_o        : out std_logic;
+      pps_ext_i            : in  std_logic                                        := '0';
+      rst_n_i              : in  std_logic;
+      dac_hpll_load_p1_o   : out std_logic;
+      dac_hpll_data_o      : out std_logic_vector(15 downto 0);
+      dac_dpll_load_p1_o   : out std_logic;
+      dac_dpll_data_o      : out std_logic_vector(15 downto 0);
+      phy8_o               : out t_phy_8bits_from_wrc;
+      phy8_i               : in  t_phy_8bits_to_wrc                               := c_dummy_phy8_to_wrc;
+      phy16_o              : out t_phy_16bits_from_wrc;
+      phy16_i              : in  t_phy_16bits_to_wrc                              := c_dummy_phy16_to_wrc;
+      scl_o                : out std_logic;
+      scl_i                : in  std_logic                                        := '1';
+      sda_o                : out std_logic;
+      sda_i                : in  std_logic                                        := '1';
+      sfp_scl_o            : out std_logic;
+      sfp_scl_i            : in  std_logic                                        := '1';
+      sfp_sda_o            : out std_logic;
+      sfp_sda_i            : in  std_logic                                        := '1';
+      sfp_det_i            : in  std_logic;
+      spi_sclk_o           : out std_logic;
+      spi_ncs_o            : out std_logic;
+      spi_mosi_o           : out std_logic;
+      spi_miso_i           : in  std_logic                                        := '0';
+      uart_rxd_i           : in  std_logic                                        := '0';
+      uart_txd_o           : out std_logic;
+      owr_pwren_o          : out std_logic_vector(1 downto 0);
+      owr_en_o             : out std_logic_vector(1 downto 0);
+      owr_i                : in  std_logic_vector(1 downto 0)                     := (others => '1');
+      wb_slave_i           : in  t_wishbone_slave_in                              := cc_dummy_slave_in;
+      wb_slave_o           : out t_wishbone_slave_out;
+      aux_master_o         : out t_wishbone_master_out;
+      aux_master_i         : in  t_wishbone_master_in                             := cc_dummy_master_in;
+      wrf_src_o            : out t_wrf_source_out;
+      wrf_src_i            : in  t_wrf_source_in                                  := c_dummy_src_in;
+      wrf_snk_o            : out t_wrf_sink_out;
+      wrf_snk_i            : in  t_wrf_sink_in                                    := c_dummy_snk_in;
+      wrs_tx_data_i        : in  std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
+      wrs_tx_valid_i       : in  std_logic                                        := '0';
+      wrs_tx_dreq_o        : out std_logic;
+      wrs_tx_last_i        : in  std_logic                                        := '1';
+      wrs_tx_flush_i       : in  std_logic                                        := '0';
+      wrs_rx_first_o       : out std_logic;
+      wrs_rx_last_o        : out std_logic;
+      wrs_rx_data_o        : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+      wrs_rx_valid_o       : out std_logic;
+      wrs_rx_dreq_i        : in  std_logic                                        := '0';
+      wrs_tx_cfg_i         : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
+      wrs_rx_cfg_i         : in t_rx_streamer_cfg := c_rx_streamer_cfg_default;
+      wb_eth_master_o      : out t_wishbone_master_out;
+      wb_eth_master_i      : in  t_wishbone_master_in                             := cc_dummy_master_in;
+      aux_diag_i           : in  t_generic_word_array(g_diag_ro_size-1 downto 0)  := (others => (others => '0'));
+      aux_diag_o           : out t_generic_word_array(g_diag_rw_size-1 downto 0);
+      tm_dac_value_o       : out std_logic_vector(23 downto 0);
+      tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+      tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0)          := (others => '0');
+      tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+      timestamps_o         : out t_txtsu_timestamp;
+      timestamps_ack_i     : in  std_logic                                        := '1';
+      abscal_txts_o        : out std_logic;
+      abscal_rxts_o        : out std_logic;
+      fc_tx_pause_req_i    : in  std_logic                                        := '0';
+      fc_tx_pause_delay_i  : in  std_logic_vector(15 downto 0)                    := x"0000";
+      fc_tx_pause_ready_o  : out std_logic;
+      tm_link_up_o         : out std_logic;
+      tm_time_valid_o      : out std_logic;
+      tm_tai_o             : out std_logic_vector(39 downto 0);
+      tm_cycles_o          : out std_logic_vector(27 downto 0);
+      led_act_o            : out std_logic;
+      led_link_o           : out std_logic;
+      btn1_i               : in  std_logic                                        := '1';
+      btn2_i               : in  std_logic                                        := '1';
+      pps_csync_o          : out std_logic;
+      pps_p_o              : out std_logic;
+      pps_led_o            : out std_logic;
+      link_ok_o            : out std_logic);
+  end component xwrc_board_common;
+
+end wr_board_pkg;
+
+package body wr_board_pkg is
+
+  procedure f_check_fabric_iface_type (
+    constant iface_type : in t_board_fabric_iface) is
+  begin
+    if iface_type >= always_last_invalid then
+      assert FALSE
+        report "WR PTP core fabric interface [" & t_board_fabric_iface'image(iface_type) & "] is not supported"
+        severity FAILURE;
+    end if;
+  end procedure f_check_fabric_iface_type;
+
+  procedure f_check_diag_id (
+    constant diag_id, diag_ver : in integer) is
+  begin
+    assert (diag_id /= 1) report
+      "g_diag_id=1 is reserved for wr_streamers and cannot be set by users"
+      severity FAILURE;
+
+    assert (not (diag_id /= 0 and diag_ver = 0)) report
+      "If diag_id is set by the user (diag_id > 1), g_diag_ver must be at least 1"
+      severity FAILURE;
+  end procedure f_check_diag_id;
+
+  function f_str2iface_type (
+    constant iface_str : string(1 to 9))
+    return t_board_fabric_iface is
+    variable result : t_board_fabric_iface;
+  begin
+    case iface_str is
+      when "PLAINFBRC" => result := PLAIN;
+      when "STREAMERS" => result := STREAMERS;
+      when "ETHERBONE" => result := ETHERBONE;
+      when others      => result := always_last_invalid;
+    end case;
+    return result;
+  end function f_str2iface_type;
+
+  -- this function decides what is the diag_id/ver used in the WRPC and MIB for access
+  -- via SNMP
+  function f_pick_diag_val (
+    iface           : t_board_fabric_iface;
+    streamers_val   : integer;
+    application_val : integer
+    ) return integer is
+  begin
+    -- streamers are enabled and application/user does nto use diags (no vector specified),
+    -- use default streamer's id/ver
+    if(iface = STREAMERS and application_val = 0) then
+      return streamers_val;
+    else  -- otherwise, use id/ver specified by the user/application. This is the case also
+      -- when streamers are used.
+      return application_val;
+    end if;
+  end f_pick_diag_val;
+
+  -- provide the size of the final diag array.
+  function f_pick_diag_size (
+    iface            : t_board_fabric_iface;
+    streamers_size   : integer;
+    application_size : integer
+    ) return integer is
+  begin
+    -- when streamers are used, concatenate the array of streamers and application/user
+    if(iface = STREAMERS) then
+      return (streamers_size+application_size);
+    else  -- otherwise, only the size provided by the application/user
+      return application_size;
+    end if;
+  end f_pick_diag_size;
+
+  function f_vectorize_diag (
+    diag_in          : t_generic_word_array;
+    diag_vector_size : integer)
+    return std_logic_vector is
+    variable result : std_logic_vector(diag_vector_size-1 downto 0);
+  begin
+    assert (diag_vector_size mod 32 = 0) report
+      "g_diag_ro/w_vector_width must have value that is a mutiple of 32"
+      severity FAILURE;
+    for i in 0 to diag_vector_size/32-1 loop
+      result(i*32-31 downto i*32) := diag_in(i);
+    end loop;
+    return result;
+  end function f_vectorize_diag;
+
+  function f_de_vectorize_diag (
+    diag_in          : std_logic_vector;
+    diag_vector_size : integer)
+    return t_generic_word_array is
+    variable result : t_generic_word_array(diag_vector_size/32-1 downto 0);
+  begin
+    assert (diag_vector_size mod 32 = 0) report
+      "g_diag_ro/w_vector_width must have value that is a mutiple of 32"
+      severity FAILURE;
+    for i in 0 to diag_vector_size/32-1 loop
+      result(i) := diag_in(i*32-31 downto i*32);
+    end loop;
+    return result;
+  end function f_de_vectorize_diag;
+
+  function f_find_default_lm32_firmware (
+    dpram_initf : string;
+    simulation  : integer;
+    pcs_16_bit  : boolean)
+    return string is
+  begin
+    if((dpram_initf = "default_altera" or dpram_initf = "default_xilinx") and
+       pcs_16_bit = TRUE) then
+      assert FALSE
+        report "[Board:Software for LM32 in WR Core] No release binary for " &
+        "pcs_16_bit." severity FAILURE;
+      return "";
+    elsif (dpram_initf /= "default_altera" and dpram_initf /= "default_xilinx") then
+      report "[Board:Software for LM32 in WR Core]  Using user-provided LM32 " &
+        "firmware ("&dpram_initf&")." severity NOTE;
+      return dpram_initf;
+    elsif (simulation = 0 and dpram_initf = "default_altera" and pcs_16_bit = FALSE and
+           dpram_initf_default_altera_phy8 /= "") then
+      report "[Board:Software for LM32 in WR Core] Using release LM32 firmware " &
+        "(altera, phy8)." severity NOTE;
+      return dpram_initf_default_altera_phy8;
+    elsif (simulation = 0 and dpram_initf = "default_xilinx" and pcs_16_bit = FALSE and
+           dpram_initf_default_xilinx_phy8 /= "") then
+      report "[Board:Software for LM32 in WR Core] Using release LM32 firmware " &
+        "(xilnix, phy8)" severity NOTE;
+      return dpram_initf_default_xilinx_phy8;
+    elsif (simulation = 1 and dpram_initf = "default_altera" and pcs_16_bit = FALSE and
+           dpram_initf_default_altera_phy8_sim /= "") then
+      report "Board:[Software for LM32 in WR Core] Using release LM32 firmware " &
+        "(altera, phy8, sim)." severity NOTE;
+      return dpram_initf_default_altera_phy8_sim;
+    elsif (simulation = 1 and dpram_initf = "default_xilinx" and pcs_16_bit = FALSE and
+           dpram_initf_default_xilinx_phy8_sim /= "") then
+      report "[Board:Software for LM32 in WR Core] Using release LM32 firmware " &
+        "(xilinx, phy8, sim)." severity NOTE;
+      return dpram_initf_default_xilinx_phy8_sim;
+    else
+      assert FALSE
+        report "[Board:Software for LM32 in WR Core] Default inclussion of LM32" &
+        "binary with software is not supported yet. In your instantiation" &
+        "of the board (xwrc_board_{spec,svec,vfchd} set g_dpram_initf to the" &
+        "correct path, i.e." &
+        "<your wr-cores location>/bin/wrpc/wrc_phy8_sim.{bram, mif} " severity FAILURE;
+      return "";
+    end if;
+  end function;
+
+end package body wr_board_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/common/xwrc_board_common.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/common/xwrc_board_common.vhd
new file mode 100644
index 000000000..1ec195920
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/common/xwrc_board_common.vhd
@@ -0,0 +1,552 @@
+-------------------------------------------------------------------------------
+-- Title      : Common WRPC Wrapper
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : xwrc_board_common.vhd
+-- Company    : CERN (BE-CO-HT)
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Wrapper for WR PTP core with common features shared between
+-- the various supported boards. These include the core itself, as well as
+-- a selection of fabric interfaces between the core and the application.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2017 CERN
+--
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wrcore_pkg.all;
+use work.wishbone_pkg.all;
+use work.etherbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.streamers_pkg.all;
+use work.wr_board_pkg.all;
+
+entity xwrc_board_common is
+  generic(
+    g_simulation                : integer                        := 0;
+    g_with_external_clock_input : boolean                        := TRUE;
+    g_board_name                : string                         := "NA  ";
+    g_flash_secsz_kb            : integer                        := 256;        -- default for M25P128
+    g_flash_sdbfs_baddr         : integer                        := 16#600000#; -- default for M25P128
+    g_phys_uart                 : boolean                        := TRUE;
+    g_virtual_uart              : boolean                        := TRUE;
+    g_aux_clks                  : integer                        := 0;
+    g_ep_rxbuf_size             : integer                        := 1024;
+    g_tx_runt_padding           : boolean                        := TRUE;
+    g_dpram_initf               : string                         := "";
+    g_dpram_size                : integer                        := 131072/4;
+    g_interface_mode            : t_wishbone_interface_mode      := PIPELINED;
+    g_address_granularity       : t_wishbone_address_granularity := BYTE;
+    g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
+    g_softpll_enable_debugger   : boolean                        := FALSE;
+    g_vuart_fifo_size           : integer                        := 1024;
+    g_pcs_16bit                 : boolean                        := FALSE;
+    g_diag_id                   : integer                        := 0;
+    g_diag_ver                  : integer                        := 0;
+    g_diag_ro_size              : integer                        := 0;
+    g_diag_rw_size              : integer                        := 0;
+    g_streamers_op_mode         : t_streamers_op_mode            := TX_AND_RX;
+    g_tx_streamer_params        : t_tx_streamer_params           := c_tx_streamer_params_defaut;
+    g_rx_streamer_params        : t_rx_streamer_params           := c_rx_streamer_params_defaut;
+    g_fabric_iface              : t_board_fabric_iface           := PLAIN);
+  port(
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+    -- system reference clock (any frequency <= f(clk_ref_i))
+    clk_sys_i : in std_logic;
+
+    -- DDMTD offset clock (125.x MHz)
+    clk_dmtd_i : in std_logic;
+
+    -- Timing reference (125 MHz)
+    clk_ref_i : in std_logic;
+
+    -- Aux clock (i.e. the FMC clock), which can be disciplined by the WR Core
+    clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+
+    -- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
+    clk_10m_ext_i : in std_logic := '0';
+
+    clk_ext_mul_i        : in  std_logic := '0';
+    clk_ext_mul_locked_i : in  std_logic := '1';
+    clk_ext_stopped_i    : in  std_logic := '0';
+    clk_ext_rst_o        : out std_logic;
+
+    -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
+    pps_ext_i : in std_logic := '0';
+
+    rst_n_i : in std_logic;
+
+    ---------------------------------------------------------------------------
+    --Timing system
+    ---------------------------------------------------------------------------
+    dac_hpll_load_p1_o : out std_logic;
+    dac_hpll_data_o    : out std_logic_vector(15 downto 0);
+
+    dac_dpll_load_p1_o : out std_logic;
+    dac_dpll_data_o    : out std_logic_vector(15 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- PHY I/f
+    ---------------------------------------------------------------------------
+    phy8_o  : out t_phy_8bits_from_wrc;
+    phy8_i  : in  t_phy_8bits_to_wrc  := c_dummy_phy8_to_wrc;
+    phy16_o : out t_phy_16bits_from_wrc;
+    phy16_i : in  t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
+
+    ---------------------------------------------------------------------------
+    -- I2C EEPROM
+    ---------------------------------------------------------------------------
+    scl_o : out std_logic;
+    scl_i : in  std_logic := '1';
+    sda_o : out std_logic;
+    sda_i : in  std_logic := '1';
+
+    ---------------------------------------------------------------------------
+    -- SFP management info
+    ---------------------------------------------------------------------------
+    sfp_scl_o : out std_logic;
+    sfp_scl_i : in  std_logic := '1';
+    sfp_sda_o : out std_logic;
+    sfp_sda_i : in  std_logic := '1';
+    sfp_det_i : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Flash memory SPI interface
+    ---------------------------------------------------------------------------
+    spi_sclk_o : out std_logic;
+    spi_ncs_o  : out std_logic;
+    spi_mosi_o : out std_logic;
+    spi_miso_i : in  std_logic := '0';
+
+    ---------------------------------------------------------------------------
+    --UART
+    ---------------------------------------------------------------------------
+    uart_rxd_i : in  std_logic := '0';
+    uart_txd_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- 1-wire
+    ---------------------------------------------------------------------------
+    owr_pwren_o : out std_logic_vector(1 downto 0);
+    owr_en_o    : out std_logic_vector(1 downto 0);
+    owr_i       : in  std_logic_vector(1 downto 0) := (others => '1');
+
+    ---------------------------------------------------------------------------
+    --External WB interface
+    ---------------------------------------------------------------------------
+    wb_slave_i : in  t_wishbone_slave_in := cc_dummy_slave_in;
+    wb_slave_o : out t_wishbone_slave_out;
+
+    aux_master_o : out t_wishbone_master_out;
+    aux_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+
+    ---------------------------------------------------------------------------
+    -- External Fabric I/F (when g_fabric_iface = PLAIN)
+    ---------------------------------------------------------------------------
+    wrf_src_o : out t_wrf_source_out;
+    wrf_src_i : in  t_wrf_source_in := c_dummy_src_in;
+    wrf_snk_o : out t_wrf_sink_out;
+    wrf_snk_i : in  t_wrf_sink_in   := c_dummy_snk_in;
+
+    ---------------------------------------------------------------------------
+    -- WR streamers (when g_fabric_iface = STREAMERS)
+    ---------------------------------------------------------------------------
+    wrs_tx_data_i  : in  std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
+    wrs_tx_valid_i : in  std_logic                                        := '0';
+    wrs_tx_dreq_o  : out std_logic;
+    wrs_tx_last_i  : in  std_logic                                        := '1';
+    wrs_tx_flush_i : in  std_logic                                        := '0';
+    wrs_rx_first_o : out std_logic;
+    wrs_rx_last_o  : out std_logic;
+    wrs_rx_data_o  : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+    wrs_rx_valid_o : out std_logic;
+    wrs_rx_dreq_i  : in  std_logic                                        := '0';
+    wrs_tx_cfg_i   : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
+    wrs_rx_cfg_i   : in t_rx_streamer_cfg := c_rx_streamer_cfg_default;
+    ---------------------------------------------------------------------------
+    -- Etherbone WB master interface (when g_fabric_iface = ETHERBONE)
+    ---------------------------------------------------------------------------
+    wb_eth_master_o : out t_wishbone_master_out;
+    wb_eth_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+
+    ---------------------------------------------------------------------------
+    -- Generic diagnostics interface (access from WRPC via SNMP or uart console
+    ---------------------------------------------------------------------------
+    aux_diag_i : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
+    aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- Aux clocks control
+    ---------------------------------------------------------------------------
+    tm_dac_value_o       : out std_logic_vector(23 downto 0);
+    tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+    tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+    tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- External Tx Timestamping I/F
+    ---------------------------------------------------------------------------
+    timestamps_o     : out t_txtsu_timestamp;
+    timestamps_ack_i : in  std_logic := '1';
+
+    -----------------------------------------
+    -- Timestamp helper signals, used for Absolute Calibration
+    -----------------------------------------
+    abscal_txts_o               : out std_logic;
+    abscal_rxts_o               : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Pause Frame Control
+    ---------------------------------------------------------------------------
+    fc_tx_pause_req_i   : in  std_logic                     := '0';
+    fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+    fc_tx_pause_ready_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Timecode I/F
+    ---------------------------------------------------------------------------
+    tm_link_up_o    : out std_logic;
+    tm_time_valid_o : out std_logic;
+    tm_tai_o        : out std_logic_vector(39 downto 0);
+    tm_cycles_o     : out std_logic_vector(27 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- Buttons, LEDs and PPS output
+    ---------------------------------------------------------------------------
+    led_act_o  : out std_logic;
+    led_link_o : out std_logic;
+    btn1_i     : in  std_logic := '1';
+    btn2_i     : in  std_logic := '1';
+    -- 1PPS output
+    pps_csync_o : out std_logic;
+    pps_p_o     : out std_logic;
+    pps_led_o   : out std_logic;
+    -- Link ok indication
+    link_ok_o : out std_logic
+    );
+
+end entity xwrc_board_common;
+
+
+architecture struct of xwrc_board_common is
+
+  -----------------------------------------------------------------------------
+  -- Signals
+  -----------------------------------------------------------------------------
+
+  -- Timecode interface
+  signal tm_time_valid : std_logic;
+  signal tm_tai        : std_logic_vector(39 downto 0);
+  signal tm_cycles     : std_logic_vector(27 downto 0);
+
+  -- WR fabric interface
+  signal wrf_src_out : t_wrf_source_out;
+  signal wrf_src_in  : t_wrf_source_in;
+  signal wrf_snk_out : t_wrf_sink_out;
+  signal wrf_snk_in  : t_wrf_sink_in;
+
+  -- Aux WB interface
+  signal aux_master_out : t_wishbone_master_out;
+  signal aux_master_in  : t_wishbone_master_in;
+  signal aux_rst_n      : std_logic;
+
+  -- Aux diagnostics:
+  -- 1) streamers have their own ID not to be used by the users
+  -- 2) regardless whether streamers are enabled nor not, application can use diagnostics
+  -- 3) if application uses diagnostics, it must specify diag_id > 1, diag_ver should start
+  --    with 1.
+  -- Application diagnostic words are added after streamer's diagnostics in the array that
+  -- goes to/from WRPC
+
+  constant c_streamers_diag_id  : integer := 1;  -- id reserved for streamers
+  constant c_streamers_diag_ver : integer := 2;  -- version that will be probably increased
+  -- when more diagnostics is added to streamers
+
+  -- final values that go to WRPC generics (depend on configuration)
+  constant c_diag_id  : integer := f_pick_diag_val(g_fabric_iface, c_streamers_diag_id, g_diag_id);
+  constant c_diag_ver : integer := f_pick_diag_val(g_fabric_iface, c_streamers_diag_ver, g_diag_id);
+
+  constant c_diag_ro_size : integer := f_pick_diag_size(g_fabric_iface, c_WR_STREAMERS_ARR_SIZE_OUT, g_diag_ro_size);
+  constant c_diag_rw_size : integer := f_pick_diag_size(g_fabric_iface, c_WR_STREAMERS_ARR_SIZE_IN, g_diag_rw_size);
+
+  -- WR SNMP
+  signal aux_diag_in  : t_generic_word_array(c_diag_ro_size-1 downto 0);
+  signal aux_diag_out : t_generic_word_array(c_diag_rw_size-1 downto 0);
+
+  -- link state
+  signal link_ok      : std_logic;
+
+begin  -- architecture struct
+
+  -- Check for unsupported fabric interface type
+  f_check_fabric_iface_type(g_fabric_iface);
+
+  -- check whether diag id and version are correct, i.e.:
+  -- * diag_id =1 is reserved for wr_streamers and cannot be used
+  -- * diag_ver values should start with 1
+  f_check_diag_id(g_diag_id, g_diag_ver);
+
+  -----------------------------------------------------------------------------
+  -- The WR PTP core itself
+  -----------------------------------------------------------------------------
+
+  cmp_xwr_core : xwr_core
+    generic map (
+      g_simulation                => g_simulation,
+      g_with_external_clock_input => g_with_external_clock_input,
+      g_board_name                => g_board_name,
+      g_flash_secsz_kb            => g_flash_secsz_kb,
+      g_flash_sdbfs_baddr         => g_flash_sdbfs_baddr,
+      g_phys_uart                 => g_phys_uart,
+      g_virtual_uart              => g_virtual_uart,
+      g_aux_clks                  => g_aux_clks,
+      g_ep_rxbuf_size             => g_ep_rxbuf_size,
+      g_tx_runt_padding           => g_tx_runt_padding,
+      g_dpram_initf               => f_find_default_lm32_firmware(g_dpram_initf, g_simulation, g_pcs_16bit),
+      g_dpram_size                => g_dpram_size,
+      g_interface_mode            => g_interface_mode,
+      g_address_granularity       => g_address_granularity,
+      g_aux_sdb                   => g_aux_sdb,
+      g_softpll_enable_debugger   => g_softpll_enable_debugger,
+      g_vuart_fifo_size           => g_vuart_fifo_size,
+      g_pcs_16bit                 => g_pcs_16bit,
+      g_records_for_phy           => TRUE,
+      g_diag_id                   => c_diag_id,
+      g_diag_ver                  => c_diag_ver,
+      g_diag_ro_size              => c_diag_ro_size,
+      g_diag_rw_size              => c_diag_rw_size)
+    port map (
+      clk_sys_i            => clk_sys_i,
+      clk_dmtd_i           => clk_dmtd_i,
+      clk_ref_i            => clk_ref_i,
+      clk_aux_i            => clk_aux_i,
+      clk_ext_i            => clk_10m_ext_i,
+      clk_ext_mul_i        => clk_ext_mul_i,
+      clk_ext_mul_locked_i => clk_ext_mul_locked_i,
+      clk_ext_stopped_i    => clk_ext_stopped_i,
+      clk_ext_rst_o        => clk_ext_rst_o,
+      pps_ext_i            => pps_ext_i,
+      rst_n_i              => rst_n_i,
+      dac_hpll_load_p1_o   => dac_hpll_load_p1_o,
+      dac_hpll_data_o      => dac_hpll_data_o,
+      dac_dpll_load_p1_o   => dac_dpll_load_p1_o,
+      dac_dpll_data_o      => dac_dpll_data_o,
+      phy_ref_clk_i        => '0',
+      phy_tx_data_o        => open,
+      phy_tx_k_o           => open,
+      phy_tx_disparity_i   => '0',
+      phy_tx_enc_err_i     => '0',
+      phy_rx_data_i        => (others => '0'),
+      phy_rx_rbclk_i       => '0',
+      phy_rx_k_i           => (others => '0'),
+      phy_rx_enc_err_i     => '0',
+      phy_rx_bitslide_i    => (others => '0'),
+      phy_rst_o            => open,
+      phy_rdy_i            => '1',
+      phy_loopen_o         => open,
+      phy_loopen_vec_o     => open,
+      phy_tx_prbs_sel_o    => open,
+      phy_sfp_tx_fault_i   => '0',
+      phy_sfp_los_i        => '0',
+      phy_sfp_tx_disable_o => open,
+      phy8_o               => phy8_o,
+      phy8_i               => phy8_i,
+      phy16_o              => phy16_o,
+      phy16_i              => phy16_i,
+      led_act_o            => led_act_o,
+      led_link_o           => led_link_o,
+      scl_o                => scl_o,
+      scl_i                => scl_i,
+      sda_o                => sda_o,
+      sda_i                => sda_i,
+      sfp_scl_o            => sfp_scl_o,
+      sfp_scl_i            => sfp_scl_i,
+      sfp_sda_o            => sfp_sda_o,
+      sfp_sda_i            => sfp_sda_i,
+      sfp_det_i            => sfp_det_i,
+      btn1_i               => btn1_i,
+      btn2_i               => btn2_i,
+      spi_sclk_o           => spi_sclk_o,
+      spi_ncs_o            => spi_ncs_o,
+      spi_mosi_o           => spi_mosi_o,
+      spi_miso_i           => spi_miso_i,
+      uart_rxd_i           => uart_rxd_i,
+      uart_txd_o           => uart_txd_o,
+      owr_pwren_o          => owr_pwren_o,
+      owr_en_o             => owr_en_o,
+      owr_i                => owr_i,
+      slave_i              => wb_slave_i,
+      slave_o              => wb_slave_o,
+      aux_master_o         => aux_master_out,
+      aux_master_i         => aux_master_in,
+      wrf_src_o            => wrf_src_out,
+      wrf_src_i            => wrf_src_in,
+      wrf_snk_o            => wrf_snk_out,
+      wrf_snk_i            => wrf_snk_in,
+      timestamps_o         => timestamps_o,
+      timestamps_ack_i     => timestamps_ack_i,
+      abscal_txts_o        => abscal_txts_o,
+      abscal_rxts_o        => abscal_rxts_o,
+      fc_tx_pause_req_i    => fc_tx_pause_req_i,
+      fc_tx_pause_delay_i  => fc_tx_pause_delay_i,
+      fc_tx_pause_ready_o  => fc_tx_pause_ready_o,
+      tm_link_up_o         => tm_link_up_o,
+      tm_dac_value_o       => tm_dac_value_o,
+      tm_dac_wr_o          => tm_dac_wr_o,
+      tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
+      tm_clk_aux_locked_o  => tm_clk_aux_locked_o,
+      tm_time_valid_o      => tm_time_valid,
+      tm_tai_o             => tm_tai,
+      tm_cycles_o          => tm_cycles,
+      pps_csync_o          => pps_csync_o,
+      pps_p_o              => pps_p_o,
+      pps_led_o            => pps_led_o,
+      rst_aux_n_o          => aux_rst_n,
+      aux_diag_i           => aux_diag_in,
+      aux_diag_o           => aux_diag_out,
+      link_ok_o            => link_ok);
+
+  link_ok_o       <= link_ok;
+  tm_time_valid_o <= tm_time_valid;
+  tm_tai_o        <= tm_tai;
+  tm_cycles_o     <= tm_cycles;
+
+  gen_wr_streamers : if (g_fabric_iface = STREAMERS) generate
+
+    cmp_xwr_streamers : xwr_streamers
+      generic map (
+        g_streamers_op_mode  => g_streamers_op_mode,
+        g_tx_streamer_params => g_tx_streamer_params,
+        g_rx_streamer_params => g_rx_streamer_params,
+        g_simulation         => g_simulation)
+      port map (
+        clk_sys_i       => clk_sys_i,
+        rst_n_i         => rst_n_i,
+        src_i           => wrf_snk_out,
+        src_o           => wrf_snk_in,
+        snk_i           => wrf_src_out,
+        snk_o           => wrf_src_in,
+        tx_data_i       => wrs_tx_data_i,
+        tx_valid_i      => wrs_tx_valid_i,
+        tx_dreq_o       => wrs_tx_dreq_o,
+        tx_last_p1_i    => wrs_tx_last_i,
+        tx_flush_p1_i   => wrs_tx_flush_i,
+        rx_first_p1_o   => wrs_rx_first_o,
+        rx_last_p1_o    => wrs_rx_last_o,
+        rx_data_o       => wrs_rx_data_o,
+        rx_valid_o      => wrs_rx_valid_o,
+        rx_dreq_i       => wrs_rx_dreq_i,
+        clk_ref_i       => clk_ref_i,
+        tm_time_valid_i => tm_time_valid,
+        tm_tai_i        => tm_tai,
+        tm_cycles_i     => tm_cycles,
+        link_ok_i       => link_ok,
+        wb_slave_i      => aux_master_out,
+        wb_slave_o      => aux_master_in,
+        snmp_array_o    => aux_diag_in(c_WR_STREAMERS_ARR_SIZE_OUT-1 downto 0),
+        snmp_array_i    => aux_diag_out(c_WR_STREAMERS_ARR_SIZE_IN-1 downto 0),
+        tx_streamer_cfg_i=> wrs_tx_cfg_i,
+        rx_streamer_cfg_i=> wrs_rx_cfg_i);
+
+    -- unused output ports
+    wrf_src_o <= c_dummy_snk_in;
+    wrf_snk_o <= c_dummy_src_in;
+
+    aux_master_o    <= cc_dummy_master_out;
+    wb_eth_master_o <= cc_dummy_master_out;
+
+    aux_diag_in(c_diag_ro_size-1 downto c_WR_STREAMERS_ARR_SIZE_OUT) <= aux_diag_i;
+    aux_diag_o                                                   <= aux_diag_out(c_diag_rw_size-1 downto c_WR_STREAMERS_ARR_SIZE_IN);
+
+  end generate gen_wr_streamers;
+
+  gen_etherbone : if (g_fabric_iface = ETHERBONE) generate
+
+    cmp_eb_ethernet_slave : eb_ethernet_slave
+      generic map (
+        g_sdb_address => x"0000000000030000")
+      port map (
+        clk_i       => clk_sys_i,
+        nRst_i      => aux_rst_n,
+        src_o       => wrf_snk_in,
+        src_i       => wrf_snk_out,
+        snk_o       => wrf_src_in,
+        snk_i       => wrf_src_out,
+        cfg_slave_o => aux_master_in,
+        cfg_slave_i => aux_master_out,
+        master_o    => wb_eth_master_o,
+        master_i    => wb_eth_master_i);
+
+    -- unused output ports
+    wrf_src_o <= c_dummy_snk_in;
+    wrf_snk_o <= c_dummy_src_in;
+
+    wrs_tx_dreq_o  <= '0';
+    wrs_rx_first_o <= '0';
+    wrs_rx_last_o  <= '0';
+    wrs_rx_valid_o <= '0';
+    wrs_rx_data_o  <= (others => '0');
+
+    aux_master_o <= cc_dummy_master_out;
+
+    -- unused inputs to WR PTP core
+    aux_diag_in <= aux_diag_i;
+    aux_diag_o  <= aux_diag_out;
+
+  end generate gen_etherbone;
+
+  gen_wr_fabric : if (g_fabric_iface = PLAIN) generate
+
+    wrf_src_o <= wrf_src_out;
+    wrf_snk_o <= wrf_snk_out;
+
+    wrf_src_in <= wrf_src_i;
+    wrf_snk_in <= wrf_snk_i;
+
+    -- unused output ports
+    wrs_tx_dreq_o  <= '0';
+    wrs_rx_first_o <= '0';
+    wrs_rx_last_o  <= '0';
+    wrs_rx_valid_o <= '0';
+    wrs_rx_data_o  <= (others => '0');
+
+    wb_eth_master_o <= cc_dummy_master_out;
+
+    aux_master_in <= aux_master_i;
+    aux_master_o  <= aux_master_out;
+
+    -- unused inputs to WR PTP core
+    aux_diag_in <= aux_diag_i;
+    aux_diag_o  <= aux_diag_out;
+
+  end generate gen_wr_fabric;
+
+end architecture struct;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/eeprom/sfp_eeprom.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/eeprom/sfp_eeprom.vhd
new file mode 100644
index 000000000..673b361d2
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/eeprom/sfp_eeprom.vhd
@@ -0,0 +1,161 @@
+-------------------------------------------------------------------------------
+--
+-- File: sfp_eeprom.vhd
+-- Author: National Instruments
+-- Original Project: N310
+-- Date: 22 February 2018
+--
+-------------------------------------------------------------------------------
+-- Copyright 2018 Ettus Research, A National Instruments Company
+-- SPDX-License-Identifier: LGPL-3.0
+-------------------------------------------------------------------------------
+--
+-- Purpose:
+--
+-- Responds to I2C reads from the WRC to pretend to be an AXGE SFP module.
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+entity sfp_eeprom is
+
+  port (
+    -- clock & reset
+    clk_i     : in std_logic;
+    sfp_scl   : in std_logic;
+    sfp_sda_i : in std_logic;
+    sfp_sda_o : out std_logic
+  );
+end sfp_eeprom;
+
+
+architecture syn of sfp_eeprom is
+
+  signal SfpSdaIn_ms    : std_logic := '0';
+  signal SfpSdaIn       : std_logic := '0';
+  signal SfpSdaInDel    : std_logic := '0';
+  signal SfpScl_ms      : std_logic := '0';
+  signal SfpScl         : std_logic := '0';
+  signal SfpSclDel      : std_logic := '0';
+  signal SfpSdaOut      : std_logic := '1';
+
+  signal ClockRe        : boolean := false;
+  signal ClockFe        : boolean := false;
+  signal DataFe         : boolean := false;
+  signal DataRe         : boolean := false;
+  signal Running        : boolean := false;
+  signal ReadSel        : boolean := false;
+
+  signal BitCount       : integer range -1 to 7 := 7;
+  signal AddrCount      : unsigned(4 downto 0) := (others=>'0');
+  signal ByteCount      : integer range 0 to 143;
+
+  type   Eeprom_t       is array(0 to 143) of std_logic_vector(7 downto 0);
+  signal Eeprom         : Eeprom_t := (
+  X"03", X"04", X"07", X"00", X"00", X"00", X"40", X"00", X"00", X"00", X"00", X"01", X"0d", X"00", X"0a", X"64",
+  X"00", X"00", X"00", X"00", X"41", X"78", X"63", X"65", X"6e", X"20", X"50", X"68", X"6f", X"74", X"6f", X"6e",
+  X"69", X"63", X"73", X"20", X"00", X"00", X"17", X"2d", X"41", X"58", X"47", X"45", X"2d", X"31", X"32", X"35",
+  X"34", X"2d", X"30", X"35", X"33", X"31", X"20", X"20", X"56", X"31", X"2e", X"31", X"05", X"1e", X"00", X"51",
+  X"00", X"1a", X"00", X"00", X"41", X"58", X"31", X"36", X"35", X"30", X"30", X"30", X"30", X"36", X"37", X"36",
+  X"39", X"20", X"20", X"20", X"31", X"36", X"31", X"32", X"30", X"38", X"20", X"20", X"00", X"00", X"00", X"bd",
+  X"45", X"58", X"54", X"52", X"45", X"4d", X"45", X"4c", X"59", X"20", X"43", X"4f", X"4d", X"50", X"41", X"54",
+  X"49", X"42", X"4c", X"45", X"20", X"20", X"20", X"20", X"20", X"20", X"20", X"20", X"20", X"20", X"20", X"20",
+  X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF");
+
+  -- AXGE Optical
+  --      0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
+  -- 00: 03 04 07 00 00 00 40 00 00 00 00 01 0d 00 0a 64    ???...@....??.?d
+  -- 10: 00 00 00 00 41 78 63 65 6e 20 50 68 6f 74 6f 6e    ....Axcen Photon
+  -- 20: 69 63 73 20 00 00 17 2d 41 58 47 45 2d 31 32 35    ics ..?-AXGE-125
+  -- 30: 34 2d 30 35 33 31 20 20 56 31 2e 31 05 1e 00 51    4-0531  V1.1??.Q
+  -- 40: 00 1a 00 00 41 58 31 36 35 30 30 30 30 36 37 36    .?..AX1650000676
+  -- 50: 39 20 20 20 31 36 31 32 30 38 20 20 00 00 00 bd    9   161208  ...?
+  -- 60: 45 58 54 52 45 4d 45 4c 59 20 43 4f 4d 50 41 54    EXTREMELY COMPAT
+  -- 70: 49 42 4c 45 20 20 20 20 20 20 20 20 20 20 20 20    IBLE
+  -- 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
+
+begin
+
+  sfp_sda_o <= SfpSdaOut;
+
+  -- Double syncs on the I2C lines
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      SfpSdaIn_ms  <= sfp_sda_i;
+      SfpSdaIn     <= SfpSdaIn_ms;
+      SfpSdaInDel  <= SfpSdaIn;
+
+      SfpScl_ms    <= sfp_scl;
+      SfpScl       <= SfpScl_ms;
+      SfpSclDel    <= SfpScl;
+    end if;
+  end process;
+
+  ClockRe <= SfpScl='1' and SfpSclDel='0';
+  ClockFe <= SfpScl='0' and SfpSclDel='1';
+  DataRe  <= SfpSdaIn='1' and SfpSdaInDel='0';
+  DataFe  <= SfpSdaIn='0' and SfpSdaInDel='1';
+
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      SfpSdaOut <= '1';
+      if (DataFe and SfpScl='1') or not Running then   -- detect start condition
+        BitCount <= 7;
+        AddrCount <= (others=>'0');
+        --ByteCount <= 0;
+        Running <= true;
+        ReadSel <= false;
+      else                            -- if running, then start generating data
+        if DataRe and SfpScl='1' then -- detect stop condition
+          Running <= false;
+        elsif AddrCount<9 then
+          if ClockFe then
+            AddrCount <= AddrCOunt + 1;
+            if AddrCount=8 then
+              if SfpSdaIn='0' then      -- reset byte count for write operation
+                ByteCount <= 0;
+              end if;
+              ReadSel <= SfpSdaIn='1';
+            end if;
+          end if;
+        elsif AddrCount=9 then
+          SfpSdaOut <= '0';           -- output ACK and hold it for a clock tick
+          if ClockFe then
+            AddrCount <= AddrCOunt + 1;
+          end if;
+        else
+          if BitCount>=0 then         -- shift out 8 bits if it's a read
+            if ReadSel then
+              SfpSdaOut <= Eeprom(ByteCount)(BitCount);
+            else
+              SfpSdaOut <= '1';
+            end if;
+            if ClockFe then
+              BitCount <= BitCOunt - 1;
+            end if;
+          else                        -- ignore ACK, update byte counter
+            SfpSdaOut <= '0';
+            if ClockFe then
+              if ReadSel then
+                if ByteCount<143 then
+                  ByteCount <= ByteCount + 1;
+                else
+                  ByteCount <= 143;    -- play X"FF" for all remaining bytes
+                end if;
+              end if;
+              BitCount <= 7;
+            end if;
+          end if;
+        end if;
+      end if;                         -- Running
+    end if;
+  end process;
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/eeprom/tb_sfp_eeprom.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/eeprom/tb_sfp_eeprom.vhd
new file mode 100644
index 000000000..4eec0765c
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/eeprom/tb_sfp_eeprom.vhd
@@ -0,0 +1,96 @@
+-------------------------------------------------------------------------------
+--
+-- File: tb_sfp_eeprom.vhd
+-- Author: National Instruments
+-- Original Project: N310
+-- Date: 22 February 2018
+--
+-------------------------------------------------------------------------------
+-- Copyright 2018 Ettus Research, A National Instruments Company
+-- SPDX-License-Identifier: LGPL-3.0
+-------------------------------------------------------------------------------
+--
+-- Purpose:
+--
+-- Testbench for sfp_eeprom.vhd
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+
+entity tb_sfp_eeprom is
+end tb_sfp_eeprom;
+
+architecture test of tb_sfp_eeprom is
+
+  constant kHalfPeriod    : time := 25 ns;
+
+  signal clk_i     : std_logic := '1';
+  signal sfp_scl   : std_logic := '1';
+  signal sfp_sda_i : std_logic := '1';
+  signal sfp_sda_o : std_logic := '1';
+
+
+  signal StopSim : boolean := false;
+
+  -- This procedure waits for X rising edges of Clk
+  procedure ClkWait (X : integer := 1) is
+  begin
+    for i in 1 to X loop
+      wait until rising_edge(clk_i);
+    end loop;
+  end procedure ClkWait;
+
+  component sfp_eeprom
+  port (
+    clk_i     : in std_logic;
+    sfp_scl   : in std_logic;
+    sfp_sda_i : in std_logic;
+    sfp_sda_o : out std_logic);
+  end component;
+
+begin
+
+  -- Set up the clock(s)
+  clk_i <= not clk_i after kHalfPeriod when not StopSim else '0';
+
+
+  DUT: sfp_eeprom
+    port map (
+      clk_i => clk_i,
+      sfp_scl => sfp_scl,
+      sfp_sda_i => sfp_sda_i,
+      sfp_sda_o => sfp_sda_o );
+
+
+  Sim: process
+  begin
+    for K in 0 to 1 loop
+      wait for 210 ns;
+      -- send start condition
+      sfp_sda_i <= '0';
+      wait for 210 ns;
+      sfp_scl <= '0';
+      wait for 210 ns;
+      for I in 0 to 150 loop
+        for J in 0 to 8 loop
+          sfp_scl <= '1';
+          wait for 210 ns;
+          sfp_scl <= '0';
+          wait for 210 ns;
+        end loop;
+        wait for 210 ns;
+      end loop;
+      sfp_scl <= '1';
+      wait for 210 ns;
+      sfp_sda_i <= '1';
+      wait for 210 ns;
+    end loop;
+    StopSim <= true;
+    wait;
+  end process Sim;
+
+
+end test;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/wr_fasec_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/wr_fasec_pkg.vhd
new file mode 100644
index 000000000..eeb3c81b9
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/wr_fasec_pkg.vhd
@@ -0,0 +1,198 @@
+-------------------------------------------------------------------------------
+-- Title      : WRPC Wrapper for FASEC package
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : wr_fasec_pkg.vhd
+-- Author(s)  : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2017-08-02
+-- Last update: 2017-09-07
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2017 CERN
+--
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.wrcore_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_board_pkg.all;
+use work.streamers_pkg.all;
+
+package wr_fasec_pkg is
+
+  component xwrc_board_fasec
+    generic(
+      g_simulation                : integer              := 0;
+      g_with_external_clock_input : boolean              := TRUE;
+      g_aux_clks                  : integer              := 0;
+      g_fabric_iface              : t_board_fabric_iface := plain;
+      g_streamers_op_mode         : t_streamers_op_mode  := TX_AND_RX;
+      g_tx_streamer_params        : t_tx_streamer_params := c_tx_streamer_params_defaut;
+      g_rx_streamer_params        : t_rx_streamer_params := c_rx_streamer_params_defaut;
+      g_dpram_initf               : string               := "default_xilinx";
+      g_diag_id                   : integer              := 0;
+      g_diag_ver                  : integer              := 0;
+      g_diag_ro_size              : integer              := 0;
+      g_diag_rw_size              : integer              := 0);
+    port (
+      areset_n_i          : in  std_logic;
+      areset_edge_n_i     : in  std_logic := '1';
+      clk_20m_vcxo_i      : in  std_logic;
+      clk_125m_pllref_p_i : in  std_logic;
+      clk_125m_pllref_n_i : in  std_logic;
+      clk_125m_gtp_n_i    : in  std_logic;
+      clk_125m_gtp_p_i    : in  std_logic;
+      clk_aux_i           : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+      clk_10m_ext_i       : in  std_logic                               := '0';
+      pps_ext_i           : in  std_logic                               := '0';
+      clk_sys_62m5_o      : out std_logic;
+      clk_ref_125m_o      : out std_logic;
+      rst_sys_62m5_n_o    : out std_logic;
+      rst_ref_125m_n_o    : out std_logic;
+  
+      plldac_sclk_o   : out std_logic;
+      plldac_din_o    : out std_logic;
+      pll25dac_cs_n_o : out std_logic;
+      pll20dac_cs_n_o : out std_logic;
+  
+      sfp_txp_o         : out std_logic;
+      sfp_txn_o         : out std_logic;
+      sfp_rxp_i         : in  std_logic;
+      sfp_rxn_i         : in  std_logic;
+      sfp_det_i         : in  std_logic := '1';
+      sfp_sda_i         : in  std_logic;
+      sfp_sda_o         : out std_logic;
+      sfp_sda_t         : out std_logic;
+      sfp_scl_i         : in  std_logic;
+      sfp_scl_o         : out std_logic;
+      sfp_scl_t         : out std_logic;
+      sfp_rate_select_o : out std_logic;
+      sfp_tx_fault_i    : in  std_logic := '0';
+      sfp_tx_disable_o  : out std_logic;
+      sfp_los_i         : in  std_logic := '0';
+  
+      eeprom_sda_i : in  std_logic;
+      eeprom_sda_o : out std_logic;
+      eeprom_sda_t : out std_logic;
+      eeprom_scl_i : in  std_logic;
+      eeprom_scl_o : out std_logic;
+      eeprom_scl_t : out std_logic;
+    
+      thermo_id_i : in  std_logic;
+      thermo_id_o : out std_logic;
+      thermo_id_t : out std_logic;
+      uart_rxd_i : in  std_logic;
+      uart_txd_o : out std_logic;
+  
+      flash_sclk_o : out std_logic;
+      flash_ncs_o  : out std_logic;
+      flash_mosi_o : out std_logic;
+      flash_miso_i : in  std_logic := '0';
+  
+      aux_master_o : out t_wishbone_master_out;
+      aux_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+  
+      s00_axi_aclk_o  : out std_logic;
+      s00_axi_aresetn : in  std_logic;
+      s00_axi_awaddr  : in std_logic_vector(31 downto 0);
+      s00_axi_awprot  : in  std_logic_vector(2 downto 0);
+      s00_axi_awvalid : in  std_logic;
+      s00_axi_awready : out std_logic;
+      s00_axi_wdata   : in std_logic_vector(31 downto 0);
+      s00_axi_wstrb   : in std_logic_vector(3 downto 0);
+      s00_axi_wvalid  : in  std_logic;
+      s00_axi_wready  : out std_logic;
+      s00_axi_bresp   : out std_logic_vector(1 downto 0);
+      s00_axi_bvalid  : out std_logic;
+      s00_axi_bready  : in std_logic;
+      s00_axi_araddr  : in std_logic_vector(31 downto 0);
+      s00_axi_arprot  : in std_logic_vector(2 downto 0);
+      s00_axi_arvalid : in std_logic;
+      s00_axi_arready : out std_logic;
+      s00_axi_rdata   : out std_logic_vector(31 downto 0);
+      s00_axi_rresp   : out std_logic_vector(1 downto 0);
+      s00_axi_rvalid  : out std_logic;
+      s00_axi_rready  : in std_logic;
+      s00_axi_rlast   : out std_logic;
+      axi_int_o       : out std_logic;
+  
+      wrf_src_o : out t_wrf_source_out;
+      wrf_src_i : in  t_wrf_source_in := c_dummy_src_in;
+      wrf_snk_o : out t_wrf_sink_out;
+      wrf_snk_i : in  t_wrf_sink_in   := c_dummy_snk_in;
+  
+      wrs_tx_data_i  : in  std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
+      wrs_tx_valid_i : in  std_logic                                        := '0';
+      wrs_tx_dreq_o  : out std_logic;
+      wrs_tx_last_i  : in  std_logic                                        := '1';
+      wrs_tx_flush_i : in  std_logic                                        := '0';
+      wrs_tx_cfg_i   : in  t_tx_streamer_cfg                                := c_tx_streamer_cfg_default;
+      wrs_rx_first_o : out std_logic;
+      wrs_rx_last_o  : out std_logic;
+      wrs_rx_data_o  : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+      wrs_rx_valid_o : out std_logic;
+      wrs_rx_dreq_i  : in  std_logic                                        := '0';
+      wrs_rx_cfg_i   : in t_rx_streamer_cfg                                 := c_rx_streamer_cfg_default;
+
+      wb_eth_master_o : out t_wishbone_master_out;
+      wb_eth_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+  
+      aux_diag_i : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
+      aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
+  
+      tm_dac_value_o       : out std_logic_vector(23 downto 0);
+      tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+      tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+      tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+  
+      timestamps_o     : out t_txtsu_timestamp;
+      timestamps_ack_i : in  std_logic := '1';
+  
+      abscal_txts_o       : out std_logic;
+      abscal_rxts_o       : out std_logic;
+  
+      fc_tx_pause_req_i   : in  std_logic                     := '0';
+      fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+      fc_tx_pause_ready_o : out std_logic;
+  
+      tm_link_up_o    : out std_logic;
+      tm_time_valid_o : out std_logic;
+      tm_tai_o        : out std_logic_vector(39 downto 0);
+      tm_cycles_o     : out std_logic_vector(27 downto 0);
+  
+      led_act_o  : out std_logic;
+      led_link_o : out std_logic;
+      btn1_i     : in  std_logic := '1';
+      btn2_i     : in  std_logic := '1';
+      pps_p_o    : out std_logic;
+      pps_led_o  : out std_logic;
+      link_ok_o  : out std_logic);
+  end component xwrc_board_fasec;
+
+end wr_fasec_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/wrc_board_fasec.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/wrc_board_fasec.vhd
new file mode 100644
index 000000000..3aeca64b7
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/wrc_board_fasec.vhd
@@ -0,0 +1,599 @@
+-------------------------------------------------------------------------------
+-- Title      : WRPC Wrapper for FASEC
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : wrc_board_fasec.vhd
+-- Author(s)  : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2017-08-02
+-- Last update: 2017-09-07
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Top-level wrapper for WR PTP core including all the modules
+-- needed to operate the core on the FASEC board.
+-- Version with no VHDL records on the top-level (mainly for Verilog
+-- instantiation).
+-- http://www.ohwr.org/projects/fasec/
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+-------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wrcore_pkg.all;
+use work.wishbone_pkg.all;
+use work.etherbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.streamers_pkg.all;
+use work.wr_xilinx_pkg.all;
+use work.wr_board_pkg.all;
+use work.wr_fasec_pkg.all;
+
+entity wrc_board_fasec is
+  generic(
+    -- set to 1 to speed up some initialization processes during simulation
+    g_simulation                : integer := 0;
+    -- Select whether to include external ref clock input
+    g_with_external_clock_input : integer := 0;
+    -- Number of aux clocks syntonized by WRPC to WR timebase
+    g_aux_clks                  : integer := 0;
+    -- "plainfbrc" = expose WRC fabric interface
+    -- "streamers" = attach WRC streamers to fabric interface
+    -- "etherbone" = attach Etherbone slave to fabric interface
+    g_fabric_iface              : string  := "plainfbrc";
+    -- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
+    --g_streamers_op_mode        : t_streamers_op_mode  := TX_AND_RX;
+    --g_tx_streamer_params       : t_tx_streamer_params := c_tx_streamer_params_defaut;
+    --g_rx_streamer_params       : t_rx_streamer_params := c_rx_streamer_params_defaut;
+    -- memory initialisation file for embedded CPU
+    g_dpram_initf               : string  := "../../../../bin/wrpc/wrc_phy16.bram";
+    -- identification (id and ver) of the layout of words in the generic diag interface
+    g_diag_id                   : integer := 0;
+    g_diag_ver                  : integer := 0;
+    -- size the generic diag interface
+    g_diag_ro_vector_width      : integer := 0;
+    g_diag_rw_vector_width      : integer := 0
+    );
+  port (
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+    -- Reset from system fpga
+    areset_n_i          : in  std_logic;
+    -- Optional reset input active low with rising edge detection. Does not
+    -- reset PLLs.
+    --areset_edge_n_i     : in  std_logic := '1';
+    -- Clock inputs from the board
+    clk_20m_vcxo_i      : in  std_logic;
+    clk_125m_pllref_p_i : in  std_logic;
+    clk_125m_pllref_n_i : in  std_logic;
+    clk_125m_gtp_n_i    : in  std_logic;
+    clk_125m_gtp_p_i    : in  std_logic;
+    -- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
+    clk_10m_ext_i       : in  std_logic := '0';
+    -- External PPS input (g_with_external_clock_input = TRUE)
+    pps_ext_i           : in  std_logic := '0';
+    -- 62.5MHz sys clock output
+    clk_sys_62m5_o      : out std_logic;
+    -- 125MHz ref clock output
+    clk_ref_125m_o      : out std_logic;
+    -- active low reset outputs, synchronous to 62m5 and 125m clocks
+    rst_sys_62m5_n_o    : out std_logic;
+    rst_ref_125m_n_o    : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Shared SPI interface to DACs
+    ---------------------------------------------------------------------------
+    plldac_sclk_o   : out std_logic;
+    plldac_din_o    : out std_logic;
+    pll25dac_cs_n_o : out std_logic;
+    pll20dac_cs_n_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- SFP I/O for transceiver and SFP management info
+    ---------------------------------------------------------------------------
+    sfp_tx_p_o         : out std_logic;
+    sfp_tx_n_o         : out std_logic;
+    sfp_rx_p_i         : in  std_logic;
+    sfp_rx_n_i         : in  std_logic;
+    sfp_det_i         : in  std_logic := '1';
+    sfp_sda_i         : in  std_logic;
+    sfp_sda_o         : out std_logic;
+    sfp_sda_t         : out std_logic;
+    sfp_scl_i         : in  std_logic;
+    sfp_scl_o         : out std_logic;
+    sfp_scl_t         : out std_logic;
+    sfp_rate_select_o : out std_logic;
+    sfp_tx_fault_i    : in  std_logic := '0';
+    sfp_tx_disable_o  : out std_logic;
+    sfp_los_i         : in  std_logic := '0';
+
+    ---------------------------------------------------------------------------
+    -- I2C EEPROM
+    ---------------------------------------------------------------------------
+    eeprom_sda_i : in  std_logic;
+    eeprom_sda_o : out std_logic;
+    eeprom_sda_t : out std_logic;
+    eeprom_scl_i : in  std_logic;
+    eeprom_scl_o : out std_logic;
+    eeprom_scl_t : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Onewire interface
+    ---------------------------------------------------------------------------
+    thermo_id_i : in  std_logic;
+    thermo_id_o : out std_logic;
+    thermo_id_t : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- UART
+    ---------------------------------------------------------------------------
+    uart_rxd_i : in  std_logic;
+    uart_txd_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Flash memory SPI interface
+    ---------------------------------------------------------------------------
+    --flash_sclk_o : out std_logic;
+    --flash_ncs_o  : out std_logic;
+    --flash_mosi_o : out std_logic;
+    --flash_miso_i : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- External WB interface
+    ---------------------------------------------------------------------------
+    --aux_master_adr_o   : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+    --aux_master_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    --aux_master_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
+    --aux_master_sel_o   : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
+    --aux_master_we_o    : out std_logic;
+    --aux_master_cyc_o   : out std_logic;
+    --aux_master_stb_o   : out std_logic;
+    --aux_master_ack_i   : in  std_logic                                          := '0';
+    --aux_master_int_i   : in  std_logic                                          := '0';
+    --aux_master_err_i   : in  std_logic                                          := '0';
+    --aux_master_rty_i   : in  std_logic                                          := '0';
+    --aux_master_stall_i : in  std_logic                                          := '0';
+
+    ------------------------------------------
+    -- Axi Slave Bus Interface S00_AXI
+    ------------------------------------------
+    s00_axi_aclk_o  : out std_logic;
+    s00_axi_aresetn : in  std_logic := '1';
+    s00_axi_awaddr  : in  std_logic_vector(31 downto 0) := (others=>'0');
+    --s00_axi_awprot  : in  std_logic_vector(2 downto 0);
+    s00_axi_awvalid : in  std_logic := '0';
+    s00_axi_awready : out std_logic;
+    s00_axi_wdata   : in  std_logic_vector(31 downto 0) := (others=>'0');
+    s00_axi_wstrb   : in  std_logic_vector(3 downto 0)  := (others=>'0');
+    s00_axi_wvalid  : in  std_logic := '0';
+    s00_axi_wready  : out std_logic;
+    s00_axi_bresp   : out std_logic_vector(1 downto 0);
+    s00_axi_bvalid  : out std_logic;
+    s00_axi_bready  : in  std_logic := '0';
+    s00_axi_araddr  : in  std_logic_vector(31 downto 0) := (others=>'0');
+    --s00_axi_arprot  : in std_logic_vector(2 downto 0);
+    s00_axi_arvalid : in  std_logic := '0';
+    s00_axi_arready : out std_logic;
+    s00_axi_rdata   : out std_logic_vector(31 downto 0);
+    s00_axi_rresp   : out std_logic_vector(1 downto 0);
+    s00_axi_rvalid  : out std_logic;
+    s00_axi_rready  : in  std_logic := '0';
+    s00_axi_rlast   : out std_logic;
+    axi_int_o       : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- WR fabric interface (when g_fabric_iface = "plain")
+    ---------------------------------------------------------------------------
+    --wrf_src_adr_o   : out std_logic_vector(1 downto 0);
+    --wrf_src_dat_o   : out std_logic_vector(15 downto 0);
+    --wrf_src_cyc_o   : out std_logic;
+    --wrf_src_stb_o   : out std_logic;
+    --wrf_src_we_o    : out std_logic;
+    --wrf_src_sel_o   : out std_logic_vector(1 downto 0);
+    --wrf_src_ack_i   : in  std_logic;
+    --wrf_src_stall_i : in  std_logic;
+    --wrf_src_err_i   : in  std_logic;
+    --wrf_src_rty_i   : in  std_logic;
+    --wrf_snk_adr_i   : in  std_logic_vector(1 downto 0);
+    --wrf_snk_dat_i   : in  std_logic_vector(15 downto 0);
+    --wrf_snk_cyc_i   : in  std_logic;
+    --wrf_snk_stb_i   : in  std_logic;
+    --wrf_snk_we_i    : in  std_logic;
+    --wrf_snk_sel_i   : in  std_logic_vector(1 downto 0);
+    --wrf_snk_ack_o   : out std_logic;
+    --wrf_snk_stall_o : out std_logic;
+    --wrf_snk_err_o   : out std_logic;
+    --wrf_snk_rty_o   : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- WR streamers (when g_fabric_iface = "streamers")
+    ---------------------------------------------------------------------------
+    ----wrs_tx_data_i  : in  std_logic_vector(c_tx_streamer_params_defaut.data_width-1 downto 0) := (others => '0');
+    --wrs_tx_data_i  : in  std_logic_vector(31 downto 0) := (others => '0');
+    --wrs_tx_valid_i : in  std_logic                                        := '0';
+    --wrs_tx_dreq_o  : out std_logic;
+    --wrs_tx_last_i  : in  std_logic                                        := '1';
+    --wrs_tx_flush_i : in  std_logic                                        := '0';
+    --wrs_tx_cfg_mac_l_i : in  std_logic_vector(47 downto 0)                := x"000000000000";
+    --wrs_tx_cfg_mac_t_i : in  std_logic_vector(47 downto 0)                := x"ffffffffffff";
+    --wrs_tx_cfg_etype_i : in  std_logic_vector(15 downto 0)                := x"dbff";
+    --wrs_rx_first_o : out std_logic;
+    --wrs_rx_last_o  : out std_logic;
+    ----wrs_rx_data_o  : out std_logic_vector(c_rx_streamer_params_defaut.data_width-1 downto 0);
+    --wrs_rx_data_o  : out std_logic_vector(31 downto 0);
+    --wrs_rx_valid_o : out std_logic;
+    --wrs_rx_dreq_i  : in  std_logic                                        := '0';
+    --wrs_rx_cfg_mac_l_i : in std_logic_vector(47 downto 0)                 := x"000000000000";
+    --wrs_rx_cfg_mac_r_i : in std_logic_vector(47 downto 0)                 := x"000000000000";
+    --wrs_rx_cfg_etype_i : in std_logic_vector(15 downto 0)                 := x"dbff";
+    --wrs_rx_cfg_acc_b_i : in std_logic                                     := '1';
+    --wrs_rx_cfg_flt_r_i : in std_logic                                     := '0';
+    --wrs_rx_cfg_fix_l_i : in std_logic_vector(27 downto 0)                 := x"0000000";
+    ---------------------------------------------------------------------------
+    -- Etherbone WB master interface (when g_fabric_iface = "etherbone")
+    ---------------------------------------------------------------------------
+    --wb_eth_adr_o   : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+    --wb_eth_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    --wb_eth_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
+    --wb_eth_sel_o   : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
+    --wb_eth_we_o    : out std_logic;
+    --wb_eth_cyc_o   : out std_logic;
+    --wb_eth_stb_o   : out std_logic;
+    --wb_eth_ack_i   : in  std_logic                                          := '0';
+    --wb_eth_int_i   : in  std_logic                                          := '0';
+    --wb_eth_err_i   : in  std_logic                                          := '0';
+    --wb_eth_rty_i   : in  std_logic                                          := '0';
+    --wb_eth_stall_i : in  std_logic                                          := '0';
+
+    ---------------------------------------------------------------------------
+    -- Generic diagnostics interface (access from WRPC via SNMP or uart console
+    ---------------------------------------------------------------------------
+    --aux_diag_i : in  std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
+    --aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
+
+    ---------------------------------------------------------------------------
+    -- Aux clocks control
+    ---------------------------------------------------------------------------
+    --tm_dac_value_o       : out std_logic_vector(23 downto 0);
+    --tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+    --tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+    --tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- External Tx Timestamping I/F
+    ---------------------------------------------------------------------------
+    --tstamps_stb_o       : out std_logic;
+    --tstamps_tsval_o     : out std_logic_vector(31 downto 0);
+    --tstamps_port_id_o   : out std_logic_vector(5 downto 0);
+    --tstamps_frame_id_o  : out std_logic_vector(15 downto 0);
+    --tstamps_incorrect_o : out std_logic;
+    --tstamps_ack_i       : in  std_logic := '1';
+
+    -----------------------------------------
+    -- Timestamp helper signals, used for Absolute Calibration
+    -----------------------------------------
+    --abscal_txts_o       : out std_logic;
+    --abscal_rxts_o       : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Pause Frame Control
+    ---------------------------------------------------------------------------
+    --fc_tx_pause_req_i   : in  std_logic                     := '0';
+    --fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+    --fc_tx_pause_ready_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Timecode I/F
+    ---------------------------------------------------------------------------
+    --tm_link_up_o    : out std_logic;
+    --tm_time_valid_o : out std_logic;
+    --tm_tai_o        : out std_logic_vector(39 downto 0);
+    --tm_cycles_o     : out std_logic_vector(27 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- Buttons, LEDs and PPS output
+    ---------------------------------------------------------------------------
+    led_act_o  : out std_logic;
+    led_link_o : out std_logic;
+    --btn1_i     : in  std_logic := '1';
+    --btn2_i     : in  std_logic := '1';
+    -- 1PPS output
+    pps_p_o    : out std_logic;
+    pps_led_o  : out std_logic;
+    -- Link ok indication
+    link_ok_o  : out std_logic
+    );
+
+end entity wrc_board_fasec;
+
+
+architecture std_wrapper of wrc_board_fasec is
+
+  -----------------------------------------------------------------------------
+  -- Signals
+  -----------------------------------------------------------------------------
+
+  -- WR fabric interface
+  signal wrf_src_out : t_wrf_source_out;
+  signal wrf_src_in  : t_wrf_source_in;
+  signal wrf_snk_out : t_wrf_sink_out;
+  signal wrf_snk_in  : t_wrf_sink_in;
+
+  signal aux_master_out : t_wishbone_master_out;
+  signal aux_master_in  : t_wishbone_master_in;
+
+  -- Etherbone interface
+  signal wb_eth_master_out : t_wishbone_master_out;
+  signal wb_eth_master_in  : t_wishbone_master_in;
+
+  -- Aux diagnostics
+  constant c_diag_ro_size : integer := g_diag_ro_vector_width/32;
+  constant c_diag_rw_size : integer := g_diag_rw_vector_width/32;
+
+  signal aux_diag_in  : t_generic_word_array(c_diag_ro_size-1 downto 0);
+  signal aux_diag_out : t_generic_word_array(c_diag_rw_size-1 downto 0);
+
+  -- External Tx Timestamping I/F
+  signal timestamps_out : t_txtsu_timestamp;
+
+  -- streamers config
+  signal wrs_tx_cfg_in  : t_tx_streamer_cfg;
+  signal wrs_rx_cfg_in  : t_rx_streamer_cfg;
+
+  -- axi signals
+  signal s_axi_araddr : std_logic_vector(31 downto 0);
+  signal s_axi_awaddr : std_logic_vector(31 downto 0);
+
+begin  -- architecture struct
+
+  -- Map top-level signals to internal records
+  --aux_master_adr_o <= aux_master_out.adr;
+  --aux_master_dat_o <= aux_master_out.dat;
+  --aux_master_cyc_o <= aux_master_out.cyc;
+  --aux_master_stb_o <= aux_master_out.stb;
+  --aux_master_sel_o <= aux_master_out.sel;
+  --aux_master_we_o  <= aux_master_out.we;
+
+  --aux_master_in.dat   <= aux_master_dat_i;
+  --aux_master_in.ack   <= aux_master_ack_i;
+  --aux_master_in.int   <= aux_master_int_i;
+  --aux_master_in.err   <= aux_master_err_i;
+  --aux_master_in.rty   <= aux_master_rty_i;
+  --aux_master_in.stall <= aux_master_stall_i;
+
+  --wrf_src_adr_o    <= wrf_src_out.adr;
+  --wrf_src_dat_o    <= wrf_src_out.dat;
+  --wrf_src_cyc_o    <= wrf_src_out.cyc;
+  --wrf_src_stb_o    <= wrf_src_out.stb;
+  --wrf_src_we_o     <= wrf_src_out.we;
+  --wrf_src_sel_o    <= wrf_src_out.sel;
+  --wrf_src_in.ack   <= wrf_src_ack_i;
+  --wrf_src_in.stall <= wrf_src_stall_i;
+  --wrf_src_in.err   <= wrf_src_err_i;
+  --wrf_src_in.rty   <= wrf_src_rty_i;
+
+  --wrf_snk_in.adr  <= wrf_snk_adr_i;
+  --wrf_snk_in.dat  <= wrf_snk_dat_i;
+  --wrf_snk_in.cyc  <= wrf_snk_cyc_i;
+  --wrf_snk_in.stb  <= wrf_snk_stb_i;
+  --wrf_snk_in.we   <= wrf_snk_we_i;
+  --wrf_snk_in.sel  <= wrf_snk_sel_i;
+  --wrf_snk_ack_o   <= wrf_snk_out.ack;
+  --wrf_snk_stall_o <= wrf_snk_out.stall;
+  --wrf_snk_err_o   <= wrf_snk_out.err;
+  --wrf_snk_rty_o   <= wrf_snk_out.rty;
+
+
+  --wb_eth_adr_o <= wb_eth_master_out.adr;
+  --wb_eth_dat_o <= wb_eth_master_out.dat;
+  --wb_eth_cyc_o <= wb_eth_master_out.cyc;
+  --wb_eth_stb_o <= wb_eth_master_out.stb;
+  --wb_eth_sel_o <= wb_eth_master_out.sel;
+  --wb_eth_we_o  <= wb_eth_master_out.we;
+
+  --wb_eth_master_in.dat   <= wb_eth_dat_i;
+  --wb_eth_master_in.ack   <= wb_eth_ack_i;
+  --wb_eth_master_in.int   <= wb_eth_int_i;
+  --wb_eth_master_in.err   <= wb_eth_err_i;
+  --wb_eth_master_in.rty   <= wb_eth_rty_i;
+  --wb_eth_master_in.stall <= wb_eth_stall_i;
+
+  --aux_diag_in <= f_de_vectorize_diag(aux_diag_i, g_diag_ro_vector_width);
+  --aux_diag_o  <= f_vectorize_diag(aux_diag_out, g_diag_rw_vector_width);
+
+  --tstamps_stb_o      <= timestamps_out.stb;
+  --tstamps_tsval_o    <= timestamps_out.tsval;
+  --tstamps_port_id_o  <= timestamps_out.port_id;
+  --tstamps_frame_id_o <= timestamps_out.frame_id;
+
+  --wrs_tx_cfg_in.mac_local         <= wrs_tx_cfg_mac_l_i;
+  --wrs_tx_cfg_in.mac_target        <= wrs_tx_cfg_mac_t_i;
+  --wrs_tx_cfg_in.ethertype         <= wrs_tx_cfg_etype_i;
+
+  --wrs_rx_cfg_in.mac_local         <= wrs_rx_cfg_mac_l_i;
+  --wrs_rx_cfg_in.mac_remote        <= wrs_rx_cfg_mac_r_i;
+  --wrs_rx_cfg_in.ethertype         <= wrs_rx_cfg_etype_i;
+  --wrs_rx_cfg_in.accept_broadcasts <= wrs_rx_cfg_acc_b_i;
+  --wrs_rx_cfg_in.filter_remote     <= wrs_rx_cfg_flt_r_i;
+  --wrs_rx_cfg_in.fixed_latency     <= wrs_rx_cfg_fix_l_i;
+
+  -- axi supports word-addressing only, i.e. per 4 bytes; shift for wb-bridge
+  s_axi_araddr  <= "00" & s00_axi_araddr(31 downto 2);
+  s_axi_awaddr  <= "00" & s00_axi_awaddr(31 downto 2);
+  -- Instantiate the records-based module
+  cmp_xwrc_board_fasec : xwrc_board_fasec
+    generic map (
+      g_simulation                => g_simulation,
+      g_with_external_clock_input => f_int2bool(g_with_external_clock_input),
+      g_aux_clks                  => g_aux_clks,
+      g_fabric_iface              => f_str2iface_type(g_fabric_iface),
+      g_streamers_op_mode         => TX_AND_RX,
+      g_tx_streamer_params        => c_tx_streamer_params_defaut,
+      g_rx_streamer_params        => c_rx_streamer_params_defaut,
+      g_dpram_initf               => g_dpram_initf,
+      g_diag_id                   => g_diag_id,
+      g_diag_ver                  => g_diag_ver,
+      g_diag_ro_size              => c_diag_ro_size,
+      g_diag_rw_size              => c_diag_rw_size)
+    port map (
+      areset_n_i           => areset_n_i,
+      --areset_edge_n_i      => areset_edge_n_i,
+      clk_20m_vcxo_i       => clk_20m_vcxo_i,
+      clk_125m_pllref_p_i  => clk_125m_pllref_p_i,
+      clk_125m_pllref_n_i  => clk_125m_pllref_n_i,
+      clk_125m_gtp_n_i     => clk_125m_gtp_n_i,
+      clk_125m_gtp_p_i     => clk_125m_gtp_p_i,
+      clk_10m_ext_i        => clk_10m_ext_i,
+      pps_ext_i            => pps_ext_i,
+      clk_sys_62m5_o       => clk_sys_62m5_o,
+      clk_ref_125m_o       => clk_ref_125m_o,
+      rst_sys_62m5_n_o     => rst_sys_62m5_n_o,
+      rst_ref_125m_n_o     => rst_ref_125m_n_o,
+      --
+      plldac_sclk_o        => plldac_sclk_o,
+      plldac_din_o         => plldac_din_o,
+      pll25dac_cs_n_o      => pll25dac_cs_n_o,
+      pll20dac_cs_n_o      => pll20dac_cs_n_o,
+      --
+      sfp_txp_o            => sfp_tx_p_o,
+      sfp_txn_o            => sfp_tx_n_o,
+      sfp_rxp_i            => sfp_rx_p_i,
+      sfp_rxn_i            => sfp_rx_n_i,
+      sfp_det_i            => sfp_det_i,
+      sfp_sda_i            => sfp_sda_i,
+      sfp_sda_o            => sfp_sda_o,
+      sfp_sda_t            => sfp_sda_t,
+      sfp_scl_i            => sfp_scl_i,
+      sfp_scl_o            => sfp_scl_o,
+      sfp_scl_t            => sfp_scl_t,
+      sfp_rate_select_o    => sfp_rate_select_o,
+      sfp_tx_fault_i       => sfp_tx_fault_i,
+      sfp_tx_disable_o     => sfp_tx_disable_o,
+      sfp_los_i            => sfp_los_i,
+      --
+      eeprom_sda_i => eeprom_sda_i,
+      eeprom_sda_o => eeprom_sda_o,
+      eeprom_sda_t => eeprom_sda_t,
+      eeprom_scl_i => eeprom_scl_i,
+      eeprom_scl_o => eeprom_scl_o,
+      eeprom_scl_t => eeprom_scl_t,
+      --
+      thermo_id_i  => thermo_id_i,
+      thermo_id_o  => thermo_id_o,
+      thermo_id_t  => thermo_id_t,
+      --
+      uart_rxd_i           => uart_rxd_i,
+      uart_txd_o           => uart_txd_o,
+      --
+      --flash_sclk_o         => flash_sclk_o,
+      --flash_ncs_o          => flash_ncs_o,
+      --flash_mosi_o         => flash_mosi_o,
+      --flash_miso_i         => flash_miso_i,
+      --
+      --aux_master_o         => aux_master_out,
+      --aux_master_i         => aux_master_in,
+      --
+      s00_axi_aclk_o       => s00_axi_aclk_o,
+      s00_axi_aresetn      => s00_axi_aresetn,
+      s00_axi_awaddr       => s_axi_awaddr,
+      s00_axi_awprot       => (others=>'0'), --s00_axi_awprot,
+      s00_axi_awvalid      => s00_axi_awvalid,
+      s00_axi_awready      => s00_axi_awready,
+      s00_axi_wdata        => s00_axi_wdata,
+      s00_axi_wstrb        => s00_axi_wstrb,
+      s00_axi_wvalid       => s00_axi_wvalid,
+      s00_axi_wready       => s00_axi_wready,
+      s00_axi_bresp        => s00_axi_bresp,
+      s00_axi_bvalid       => s00_axi_bvalid,
+      s00_axi_bready       => s00_axi_bready,
+      s00_axi_araddr       => s_axi_araddr,
+      s00_axi_arprot       => (others=>'0'), --s00_axi_arprot,
+      s00_axi_arvalid      => s00_axi_arvalid,
+      s00_axi_arready      => s00_axi_arready,
+      s00_axi_rdata        => s00_axi_rdata,
+      s00_axi_rresp        => s00_axi_rresp,
+      s00_axi_rvalid       => s00_axi_rvalid,
+      s00_axi_rready       => s00_axi_rready,
+      s00_axi_rlast        => s00_axi_rlast,
+      axi_int_o            => axi_int_o,
+      --
+      --wrf_src_o            => wrf_src_out,
+      --wrf_src_i            => wrf_src_in,
+      --wrf_snk_o            => wrf_snk_out,
+      --wrf_snk_i            => wrf_snk_in,
+      --
+      --wrs_tx_data_i        => wrs_tx_data_i,
+      --wrs_tx_valid_i       => wrs_tx_valid_i,
+      --wrs_tx_dreq_o        => wrs_tx_dreq_o,
+      --wrs_tx_last_i        => wrs_tx_last_i,
+      --wrs_tx_flush_i       => wrs_tx_flush_i,
+      --wrs_tx_cfg_i         => wrs_tx_cfg_in,
+      --wrs_rx_first_o       => wrs_rx_first_o,
+      --wrs_rx_last_o        => wrs_rx_last_o,
+      --wrs_rx_data_o        => wrs_rx_data_o,
+      --wrs_rx_valid_o       => wrs_rx_valid_o,
+      --wrs_rx_dreq_i        => wrs_rx_dreq_i,
+      --wrs_rx_cfg_i         => wrs_rx_cfg_in,
+      --
+      --wb_eth_master_o      => wb_eth_master_out,
+      --wb_eth_master_i      => wb_eth_master_in,
+      --
+      --aux_diag_i           => aux_diag_in,
+      --aux_diag_o           => aux_diag_out,
+      --
+      --tm_dac_value_o       => tm_dac_value_o,
+      --tm_dac_wr_o          => tm_dac_wr_o,
+      --tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
+      --tm_clk_aux_locked_o  => tm_clk_aux_locked_o,
+      --
+      --timestamps_o         => timestamps_out,
+      --timestamps_ack_i     => tstamps_ack_i,
+      --
+      --abscal_txts_o        => abscal_txts_o,
+      --abscal_rxts_o        => abscal_rxts_o,
+      --
+      --fc_tx_pause_req_i    => fc_tx_pause_req_i,
+      --fc_tx_pause_delay_i  => fc_tx_pause_delay_i,
+      --fc_tx_pause_ready_o  => fc_tx_pause_ready_o,
+      --
+      --tm_link_up_o         => tm_link_up_o,
+      --tm_time_valid_o      => tm_time_valid_o,
+      --tm_tai_o             => tm_tai_o,
+      --tm_cycles_o          => tm_cycles_o,
+      --
+      led_act_o            => led_act_o,
+      led_link_o           => led_link_o,
+      --btn1_i               => btn1_i,
+      --btn2_i               => btn2_i,
+      --
+      pps_p_o              => pps_p_o,
+      pps_led_o            => pps_led_o,
+      --
+      link_ok_o            => link_ok_o);
+
+end architecture std_wrapper;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/xwrc_board_fasec.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/xwrc_board_fasec.vhd
new file mode 100644
index 000000000..30bc6f3ed
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/xwrc_board_fasec.vhd
@@ -0,0 +1,623 @@
+-------------------------------------------------------------------------------
+-- Title      : WRPC Wrapper for FASEC
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : xwrc_board_fasec.vhd
+-- Author(s)  : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2017-08-02
+-- Last update: 2017-08-02
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Top-level wrapper for WR PTP core including all the modules
+-- needed to operate the core on the FASEC board.
+-- http://www.ohwr.org/projects/fasec/
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+-------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wrcore_pkg.all;
+use work.wishbone_pkg.all;
+use work.etherbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.streamers_pkg.all;
+use work.wr_xilinx_pkg.all;
+use work.wr_board_pkg.all;
+use work.wr_fasec_pkg.all;
+use work.axi4_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity xwrc_board_fasec is
+  generic(
+    -- set to 1 to speed up some initialization processes during simulation
+    g_simulation                : integer              := 0;
+    -- Select whether to include external ref clock input
+    g_with_external_clock_input : boolean              := TRUE;
+    -- Number of aux clocks syntonized by WRPC to WR timebase
+    g_aux_clks                  : integer              := 0;
+    -- plain     = expose WRC fabric interface
+    -- streamers = attach WRC streamers to fabric interface
+    -- etherbone = attach Etherbone slave to fabric interface
+    g_fabric_iface              : t_board_fabric_iface := plain;
+    -- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
+    g_streamers_op_mode        : t_streamers_op_mode  := TX_AND_RX;
+    g_tx_streamer_params       : t_tx_streamer_params := c_tx_streamer_params_defaut;
+    g_rx_streamer_params       : t_rx_streamer_params := c_rx_streamer_params_defaut;
+    -- memory initialisation file for embedded CPU
+    g_dpram_initf               : string               := "/home/greg/wr/wr-cores/bin/wrpc/wrc_phy16.bram";
+    -- identification (id and ver) of the layout of words in the generic diag interface
+    g_diag_id                   : integer              := 0;
+    g_diag_ver                  : integer              := 0;
+    -- size the generic diag interface
+    g_diag_ro_size              : integer              := 0;
+    g_diag_rw_size              : integer              := 0
+    );
+  port (
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+    -- Reset input (active low, can be async)
+    areset_n_i          : in  std_logic;
+    -- Optional reset input active low with rising edge detection. Does not
+    -- reset PLLs.
+    areset_edge_n_i     : in  std_logic := '1';
+    -- Clock inputs from the board
+    clk_20m_vcxo_i      : in  std_logic;
+    clk_125m_pllref_p_i : in  std_logic;
+    clk_125m_pllref_n_i : in  std_logic;
+    clk_125m_gtp_n_i    : in  std_logic;
+    clk_125m_gtp_p_i    : in  std_logic;
+    -- Aux clocks, which can be disciplined by the WR Core
+    clk_aux_i           : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+    -- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
+    clk_10m_ext_i       : in  std_logic                               := '0';
+    -- External PPS input (g_with_external_clock_input = TRUE)
+    pps_ext_i           : in  std_logic                               := '0';
+    -- 62.5MHz sys clock output
+    clk_sys_62m5_o      : out std_logic;
+    -- 125MHz ref clock output
+    clk_ref_125m_o      : out std_logic;
+    -- active low reset outputs, synchronous to 62m5 and 125m clocks
+    rst_sys_62m5_n_o    : out std_logic;
+    rst_ref_125m_n_o    : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Shared SPI interface to DACs
+    ---------------------------------------------------------------------------
+    plldac_sclk_o   : out std_logic;
+    plldac_din_o    : out std_logic;
+    pll25dac_cs_n_o : out std_logic;
+    pll20dac_cs_n_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- SFP I/O for transceiver and SFP management info
+    ---------------------------------------------------------------------------
+    sfp_txp_o         : out std_logic;
+    sfp_txn_o         : out std_logic;
+    sfp_rxp_i         : in  std_logic;
+    sfp_rxn_i         : in  std_logic;
+    sfp_det_i         : in  std_logic := '1';
+    sfp_sda_i         : in  std_logic;
+    sfp_sda_o         : out std_logic;
+    sfp_sda_t         : out std_logic;
+    sfp_scl_i         : in  std_logic;
+    sfp_scl_o         : out std_logic;
+    sfp_scl_t         : out std_logic;
+    sfp_rate_select_o : out std_logic;
+    sfp_tx_fault_i    : in  std_logic := '0';
+    sfp_tx_disable_o  : out std_logic;
+    sfp_los_i         : in  std_logic := '0';
+
+    ---------------------------------------------------------------------------
+    -- I2C EEPROM
+    ---------------------------------------------------------------------------
+    eeprom_sda_i : in  std_logic;
+    eeprom_sda_o : out std_logic;
+    eeprom_sda_t : out std_logic;
+    eeprom_scl_i : in  std_logic;
+    eeprom_scl_o : out std_logic;
+    eeprom_scl_t : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Onewire interface
+    ---------------------------------------------------------------------------
+    thermo_id_i : in  std_logic;
+    thermo_id_o : out std_logic;
+    thermo_id_t : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- UART
+    ---------------------------------------------------------------------------
+    uart_rxd_i : in  std_logic;
+    uart_txd_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Flash memory SPI interface
+    ---------------------------------------------------------------------------
+    flash_sclk_o : out std_logic;
+    flash_ncs_o  : out std_logic;
+    flash_mosi_o : out std_logic;
+    flash_miso_i : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- External WB interface
+    ---------------------------------------------------------------------------
+    aux_master_o : out t_wishbone_master_out;
+    aux_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+
+    ------------------------------------------
+    -- Axi Slave Bus Interface S00_AXI
+    ------------------------------------------
+    -- aclk provided by this IP, wire to master!
+    s00_axi_aclk_o  : out std_logic;
+    s00_axi_aresetn : in  std_logic;
+    s00_axi_awaddr  : in std_logic_vector(31 downto 0);
+    s00_axi_awprot  : in  std_logic_vector(2 downto 0);
+    s00_axi_awvalid : in  std_logic;
+    s00_axi_awready : out std_logic;
+    s00_axi_wdata   : in std_logic_vector(31 downto 0);
+    s00_axi_wstrb   : in std_logic_vector(3 downto 0);
+    s00_axi_wvalid  : in  std_logic;
+    s00_axi_wready  : out std_logic;
+    s00_axi_bresp   : out std_logic_vector(1 downto 0);
+    s00_axi_bvalid  : out std_logic;
+    s00_axi_bready  : in std_logic;
+    s00_axi_araddr  : in std_logic_vector(31 downto 0);
+    s00_axi_arprot  : in std_logic_vector(2 downto 0);
+    s00_axi_arvalid : in std_logic;
+    s00_axi_arready : out std_logic;
+    s00_axi_rdata   : out std_logic_vector(31 downto 0);
+    s00_axi_rresp   : out std_logic_vector(1 downto 0);
+    s00_axi_rvalid  : out std_logic;
+    s00_axi_rready  : in std_logic;
+    s00_axi_rlast   : out std_logic;
+    axi_int_o       : out std_logic;  -- axi interrupt signal
+
+    ---------------------------------------------------------------------------
+    -- WR fabric interface (when g_fabric_iface = "plainfbrc")
+    ---------------------------------------------------------------------------
+    wrf_src_o : out t_wrf_source_out;
+    wrf_src_i : in  t_wrf_source_in := c_dummy_src_in;
+    wrf_snk_o : out t_wrf_sink_out;
+    wrf_snk_i : in  t_wrf_sink_in   := c_dummy_snk_in;
+
+    ---------------------------------------------------------------------------
+    -- WR streamers (when g_fabric_iface = "streamers")
+    ---------------------------------------------------------------------------
+    wrs_tx_data_i  : in  std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
+    wrs_tx_valid_i : in  std_logic                                        := '0';
+    wrs_tx_dreq_o  : out std_logic;
+    wrs_tx_last_i  : in  std_logic                                        := '1';
+    wrs_tx_flush_i : in  std_logic                                        := '0';
+    wrs_tx_cfg_i   : in  t_tx_streamer_cfg                                := c_tx_streamer_cfg_default;
+    wrs_rx_first_o : out std_logic;
+    wrs_rx_last_o  : out std_logic;
+    wrs_rx_data_o  : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+    wrs_rx_valid_o : out std_logic;
+    wrs_rx_dreq_i  : in  std_logic                                        := '0';
+    wrs_rx_cfg_i   : in t_rx_streamer_cfg                                 := c_rx_streamer_cfg_default;
+    ---------------------------------------------------------------------------
+    -- Etherbone WB master interface (when g_fabric_iface = "etherbone")
+    ---------------------------------------------------------------------------
+    wb_eth_master_o : out t_wishbone_master_out;
+    wb_eth_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+
+    ---------------------------------------------------------------------------
+    -- Generic diagnostics interface (access from WRPC via SNMP or uart console
+    ---------------------------------------------------------------------------
+    aux_diag_i : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
+    aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- Aux clocks control
+    ---------------------------------------------------------------------------
+    tm_dac_value_o       : out std_logic_vector(23 downto 0);
+    tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+    tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+    tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- External Tx Timestamping I/F
+    ---------------------------------------------------------------------------
+    timestamps_o     : out t_txtsu_timestamp;
+    timestamps_ack_i : in  std_logic := '1';
+
+    -----------------------------------------
+    -- Timestamp helper signals, used for Absolute Calibration
+    -----------------------------------------
+    abscal_txts_o       : out std_logic;
+    abscal_rxts_o       : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Pause Frame Control
+    ---------------------------------------------------------------------------
+    fc_tx_pause_req_i   : in  std_logic                     := '0';
+    fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+    fc_tx_pause_ready_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Timecode I/F
+    ---------------------------------------------------------------------------
+    tm_link_up_o    : out std_logic;
+    tm_time_valid_o : out std_logic;
+    tm_tai_o        : out std_logic_vector(39 downto 0);
+    tm_cycles_o     : out std_logic_vector(27 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- Buttons, LEDs and PPS output
+    ---------------------------------------------------------------------------
+    led_act_o  : out std_logic;
+    led_link_o : out std_logic;
+    btn1_i     : in  std_logic := '1';
+    btn2_i     : in  std_logic := '1';
+    -- 1PPS output
+    pps_p_o    : out std_logic;
+    pps_led_o  : out std_logic;
+    -- Link ok indication
+    link_ok_o  : out std_logic
+    );
+
+end entity xwrc_board_fasec;
+
+
+architecture struct of xwrc_board_fasec is
+
+  -----------------------------------------------------------------------------
+  -- Signals
+  -----------------------------------------------------------------------------
+
+  -- IBUFDS
+  signal clk_125m_pllref_buf : std_logic;
+
+  -- PLLs, clocks
+  signal clk_pll_62m5 : std_logic;
+  signal clk_pll_125m : std_logic;
+  signal clk_pll_dmtd : std_logic;
+  signal pll_locked   : std_logic;
+  signal clk_10m_ext  : std_logic;
+
+  -- Reset logic
+  signal areset_edge_ppulse : std_logic;
+  signal rst_62m5_n         : std_logic;
+  signal rstlogic_arst_n    : std_logic;
+  signal rstlogic_clk_in    : std_logic_vector(1 downto 0);
+  signal rstlogic_rst_out   : std_logic_vector(1 downto 0);
+
+  -- PLL DAC ARB
+  signal dac_hpll_load_p1 : std_logic;
+  signal dac_hpll_data    : std_logic_vector(15 downto 0);
+  signal dac_dpll_load_p1 : std_logic;
+  signal dac_dpll_data    : std_logic_vector(15 downto 0);
+
+  -- OneWire
+  signal onewire_in : std_logic_vector(1 downto 0);
+  signal onewire_en : std_logic_vector(1 downto 0);
+
+  -- PHY
+  signal phy16_to_wrc   : t_phy_16bits_to_wrc;
+  signal phy16_from_wrc : t_phy_16bits_from_wrc;
+
+  -- External reference
+  signal ext_ref_mul         : std_logic;
+  signal ext_ref_mul_locked  : std_logic;
+  signal ext_ref_mul_stopped : std_logic;
+  signal ext_ref_rst         : std_logic;
+
+  -- WRC WB Slave interface
+  signal wb_slave_out : t_wishbone_slave_out;
+  signal wb_slave_in  : t_wishbone_slave_in;
+  signal zero : std_logic;
+
+begin  -- architecture struct
+
+  -----------------------------------------------------------------------------
+  -- Platform-dependent part (PHY, PLLs, buffers, etc)
+  -----------------------------------------------------------------------------
+
+  cmp_ibufgds_pllref : IBUFGDS
+    generic map (
+      DIFF_TERM    => TRUE,
+      IBUF_LOW_PWR => TRUE,
+      IOSTANDARD   => "DEFAULT")
+    port map (
+      O  => clk_125m_pllref_buf,
+      I  => clk_125m_pllref_p_i,
+      IB => clk_125m_pllref_n_i);
+
+  cmp_xwrc_platform : xwrc_platform_xilinx
+    generic map (
+      g_fpga_family               => "kintex7",
+      g_with_external_clock_input => g_with_external_clock_input,
+      g_use_default_plls          => TRUE,
+      g_simulation                => g_simulation)
+    port map (
+      areset_n_i            => areset_n_i,
+      clk_10m_ext_i         => clk_10m_ext_i,
+      clk_20m_vcxo_i        => clk_20m_vcxo_i,
+      clk_125m_pllref_i     => clk_125m_pllref_buf,
+      clk_125m_gtp_p_i      => clk_125m_gtp_p_i,
+      clk_125m_gtp_n_i      => clk_125m_gtp_n_i,
+      sfp_txn_o             => sfp_txn_o,
+      sfp_txp_o             => sfp_txp_o,
+      sfp_rxn_i             => sfp_rxn_i,
+      sfp_rxp_i             => sfp_rxp_i,
+      sfp_tx_fault_i        => sfp_tx_fault_i,
+      sfp_los_i             => sfp_los_i,
+      sfp_tx_disable_o      => sfp_tx_disable_o,
+      clk_62m5_sys_o        => clk_pll_62m5,
+      clk_125m_ref_o        => clk_pll_125m,
+      clk_62m5_dmtd_o       => clk_pll_dmtd,
+      pll_locked_o          => pll_locked,
+      clk_10m_ext_o         => clk_10m_ext,
+      phy16_o               => phy16_to_wrc,
+      phy16_i               => phy16_from_wrc,
+      ext_ref_mul_o         => ext_ref_mul,
+      ext_ref_mul_locked_o  => ext_ref_mul_locked,
+      ext_ref_mul_stopped_o => ext_ref_mul_stopped,
+      ext_ref_rst_i         => ext_ref_rst);
+
+  clk_sys_62m5_o <= clk_pll_62m5;
+  clk_ref_125m_o <= clk_pll_125m;
+
+  -----------------------------------------------------------------------------
+  -- Reset logic
+  -----------------------------------------------------------------------------
+  -- Detect when areset_edge_n_i goes high (end of reset) and use this edge to
+  -- generate rstlogic_arst_n. This is needed to connect optional reset like PCIe
+  -- reset. When baord runs standalone, we need to ignore PCIe reset being
+  -- constantly low.
+  cmp_arst_edge: gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_pll_62m5,
+      rst_n_i  => '1',
+      data_i   => areset_edge_n_i,
+      ppulse_o => areset_edge_ppulse);
+
+  -- logic AND of all async reset sources (active low)
+  rstlogic_arst_n <= pll_locked and areset_n_i and (not areset_edge_ppulse);
+
+  -- concatenation of all clocks required to have synced resets
+  rstlogic_clk_in(0) <= clk_pll_62m5;
+  rstlogic_clk_in(1) <= clk_pll_125m;
+
+  cmp_rstlogic_reset : gc_reset
+    generic map (
+      g_clocks    => 2,                           -- 62.5MHz, 125MHz
+      g_logdelay  => 4,                           -- 16 clock cycles
+      g_syncdepth => 3)                           -- length of sync chains
+    port map (
+      free_clk_i => clk_125m_pllref_buf,
+      locked_i   => rstlogic_arst_n,
+      clks_i     => rstlogic_clk_in,
+      rstn_o     => rstlogic_rst_out);
+
+  -- distribution of resets (already synchronized to their clock domains)
+  rst_62m5_n <= rstlogic_rst_out(0);
+
+  rst_sys_62m5_n_o <= rst_62m5_n;
+  rst_ref_125m_n_o <= rstlogic_rst_out(1);
+
+  -----------------------------------------------------------------------------
+  -- 2x SPI DAC
+  -----------------------------------------------------------------------------
+
+  cmp_dac_arb : spec_serial_dac_arb
+    generic map (
+      g_invert_sclk    => FALSE,
+      g_num_extra_bits => 8)
+    port map (
+      clk_i         => clk_pll_62m5,
+      rst_n_i       => rst_62m5_n,
+      val1_i        => dac_dpll_data,
+      load1_i       => dac_dpll_load_p1,
+      val2_i        => dac_hpll_data,
+      load2_i       => dac_hpll_load_p1,
+      dac_cs_n_o(0) => pll25dac_cs_n_o,
+      dac_cs_n_o(1) => pll20dac_cs_n_o,
+      dac_sclk_o    => plldac_sclk_o,
+      dac_din_o     => plldac_din_o);
+
+  -----------------------------------------------------------------------------
+  -- The WR PTP core with optional fabric interface attached
+  -----------------------------------------------------------------------------
+
+  cmp_board_common : xwrc_board_common
+    generic map (
+      g_simulation                => g_simulation,
+      g_with_external_clock_input => g_with_external_clock_input,
+      g_board_name                => "FSEC",
+      g_phys_uart                 => TRUE,
+      g_virtual_uart              => TRUE,
+      g_aux_clks                  => g_aux_clks,
+      g_ep_rxbuf_size             => 1024,
+      g_tx_runt_padding           => TRUE,
+      g_dpram_initf               => g_dpram_initf,
+      g_dpram_size                => 131072/4,
+      g_interface_mode            => PIPELINED,
+      g_address_granularity       => BYTE,
+      g_aux_sdb                   => c_wrc_periph3_sdb,
+      g_softpll_enable_debugger   => FALSE,
+      g_vuart_fifo_size           => 1024,
+      g_pcs_16bit                 => TRUE,
+      g_diag_id                   => g_diag_id,
+      g_diag_ver                  => g_diag_ver,
+      g_diag_ro_size              => g_diag_ro_size,
+      g_diag_rw_size              => g_diag_rw_size,
+      g_streamers_op_mode         => g_streamers_op_mode,
+      g_tx_streamer_params        => g_tx_streamer_params,
+      g_rx_streamer_params        => g_rx_streamer_params,
+      g_fabric_iface              => g_fabric_iface
+      )
+    port map (
+      clk_sys_i            => clk_pll_62m5,
+      clk_dmtd_i           => clk_pll_dmtd,
+      clk_ref_i            => clk_pll_125m,
+      clk_aux_i            => clk_aux_i,
+      clk_10m_ext_i        => clk_10m_ext,
+      clk_ext_mul_i        => ext_ref_mul,
+      clk_ext_mul_locked_i => ext_ref_mul_locked,
+      clk_ext_stopped_i    => ext_ref_mul_stopped,
+      clk_ext_rst_o        => ext_ref_rst,
+      pps_ext_i            => pps_ext_i,
+      rst_n_i              => rst_62m5_n,
+      dac_hpll_load_p1_o   => dac_hpll_load_p1,
+      dac_hpll_data_o      => dac_hpll_data,
+      dac_dpll_load_p1_o   => dac_dpll_load_p1,
+      dac_dpll_data_o      => dac_dpll_data,
+      phy16_o              => phy16_from_wrc,
+      phy16_i              => phy16_to_wrc,
+      scl_o                => eeprom_scl_t,
+      scl_i                => eeprom_scl_i,
+      sda_o                => eeprom_sda_t,
+      sda_i                => eeprom_sda_i,
+      sfp_scl_o            => sfp_scl_t,
+      sfp_scl_i            => sfp_scl_i,
+      sfp_sda_o            => sfp_sda_t,
+      sfp_sda_i            => sfp_sda_i,
+      sfp_det_i            => sfp_det_i,
+      spi_sclk_o           => flash_sclk_o,
+      spi_ncs_o            => flash_ncs_o,
+      spi_mosi_o           => flash_mosi_o,
+      spi_miso_i           => flash_miso_i,
+      uart_rxd_i           => uart_rxd_i,
+      uart_txd_o           => uart_txd_o,
+      owr_pwren_o          => open,
+      owr_en_o             => onewire_en,
+      owr_i                => onewire_in,
+      wb_slave_i           => wb_slave_in,
+      wb_slave_o           => wb_slave_out,
+      aux_master_o         => aux_master_o,
+      aux_master_i         => aux_master_i,
+      wrf_src_o            => wrf_src_o,
+      wrf_src_i            => wrf_src_i,
+      wrf_snk_o            => wrf_snk_o,
+      wrf_snk_i            => wrf_snk_i,
+      wrs_tx_data_i        => wrs_tx_data_i,
+      wrs_tx_valid_i       => wrs_tx_valid_i,
+      wrs_tx_dreq_o        => wrs_tx_dreq_o,
+      wrs_tx_last_i        => wrs_tx_last_i,
+      wrs_tx_flush_i       => wrs_tx_flush_i,
+      wrs_tx_cfg_i         => wrs_tx_cfg_i,
+      wrs_rx_first_o       => wrs_rx_first_o,
+      wrs_rx_last_o        => wrs_rx_last_o,
+      wrs_rx_data_o        => wrs_rx_data_o,
+      wrs_rx_valid_o       => wrs_rx_valid_o,
+      wrs_rx_dreq_i        => wrs_rx_dreq_i,
+      wrs_rx_cfg_i         => wrs_rx_cfg_i,
+      wb_eth_master_o      => wb_eth_master_o,
+      wb_eth_master_i      => wb_eth_master_i,
+      aux_diag_i           => aux_diag_i,
+      aux_diag_o           => aux_diag_o,
+      tm_dac_value_o       => tm_dac_value_o,
+      tm_dac_wr_o          => tm_dac_wr_o,
+      tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
+      tm_clk_aux_locked_o  => tm_clk_aux_locked_o,
+      timestamps_o         => timestamps_o,
+      timestamps_ack_i     => timestamps_ack_i,
+      abscal_txts_o        => abscal_txts_o,
+      abscal_rxts_o        => abscal_rxts_o,
+      fc_tx_pause_req_i    => fc_tx_pause_req_i,
+      fc_tx_pause_delay_i  => fc_tx_pause_delay_i,
+      fc_tx_pause_ready_o  => fc_tx_pause_ready_o,
+      tm_link_up_o         => tm_link_up_o,
+      tm_time_valid_o      => tm_time_valid_o,
+      tm_tai_o             => tm_tai_o,
+      tm_cycles_o          => tm_cycles_o,
+      led_act_o            => led_act_o,
+      led_link_o           => led_link_o,
+      btn1_i               => btn1_i,
+      btn2_i               => btn2_i,
+      pps_p_o              => pps_p_o,
+      pps_led_o            => pps_led_o,
+      link_ok_o            => link_ok_o);
+
+  sfp_rate_select_o <= '1';
+
+  --onewire_oen_o <= onewire_en(0);
+  --onewire_in(0) <= onewire_i;
+  --onewire_in(1) <= '1';
+
+  thermo_id_t <= '0' when onewire_en(0) = '1' else '1';
+  thermo_id_o <= '0';
+  onewire_in(0) <= thermo_id_i;
+  onewire_in(1) <= '1';
+
+  eeprom_sda_o <= '0';
+  eeprom_scl_o <= '0';
+  sfp_sda_o    <= '0';
+  sfp_scl_o    <= '0';
+
+  s00_axi_aclk_o <= clk_pll_62m5;
+
+  zero <= '0';
+  cmp_axi4lite_wbm: wb_axi4lite_bridge
+    port map (
+      clk_sys_i => clk_pll_62m5,
+      rst_n_i   => s00_axi_aresetn,
+
+      AWADDR  => s00_axi_awaddr, 
+      AWVALID => s00_axi_awvalid,
+      AWREADY => s00_axi_awready,
+      WDATA   => s00_axi_wdata,
+      WSTRB   => s00_axi_wstrb,
+      WVALID  => s00_axi_wvalid,
+      WREADY  => s00_axi_wready,
+      WLAST   => zero,
+      BRESP   => s00_axi_bresp,
+      BVALID  => s00_axi_bvalid,
+      BREADY  => s00_axi_bready,
+      ARADDR  => s00_axi_araddr,
+      ARVALID => s00_axi_arvalid,
+      ARREADY => s00_axi_arready,
+      RDATA   => s00_axi_rdata,
+      RRESP   => s00_axi_rresp,
+      RVALID  => s00_axi_rvalid,
+      RREADY  => s00_axi_rready,
+      RLAST   => s00_axi_rlast,
+
+      wb_adr  => wb_slave_in.adr,
+      wb_dat_m2s => wb_slave_in.dat,
+      wb_sel => wb_slave_in.sel,
+      wb_cyc => wb_slave_in.cyc,
+      wb_stb => wb_slave_in.stb,
+      wb_we  => wb_slave_in.we,
+
+      wb_dat_s2m => wb_slave_out.dat,
+      wb_err     => wb_slave_out.err,
+      wb_rty     => wb_slave_out.rty,
+      wb_ack     => wb_slave_out.ack,
+      wb_stall   => wb_slave_out.stall
+    );
+  
+
+end architecture struct;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd
new file mode 100644
index 000000000..684633eba
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd
@@ -0,0 +1,177 @@
+------------------------------------------------------------------------------
+-- Title      : Etherbone Config Master FIFO
+-- Project    : Etherbone Core
+------------------------------------------------------------------------------
+-- File       : eb_cfg_fifo.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2013-04-08
+-- Last update: 2013-04-08
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Buffers Config space requests
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 GSI
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-04-08  1.0      terpstra        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+
+entity eb_cfg_fifo is
+  generic(
+    g_sdb_address : t_wishbone_address);
+  port(
+    clk_i       : in  std_logic;
+    rstn_i      : in  std_logic;
+    
+    errreg_i    : in  std_logic_vector(63 downto 0);
+    
+    cfg_i       : in  t_wishbone_slave_in;
+    cfg_o       : out t_wishbone_slave_out;
+    
+    fsm_stb_i   : in  std_logic;
+    fsm_adr_i   : in  t_wishbone_address;
+    fsm_full_o  : out std_logic;
+
+    mux_pop_i   : in  std_logic;
+    mux_dat_o   : out t_wishbone_data;
+    mux_empty_o : out std_logic;
+    
+    my_mac_o    : out std_logic_vector(47 downto 0);
+    my_ip_o     : out std_logic_vector(31 downto 0);
+    my_port_o   : out std_logic_vector(15 downto 0));
+end eb_cfg_fifo;
+
+architecture rtl of eb_cfg_fifo is
+  
+  constant c_pad  : std_logic_vector(31 downto 16) := (others => '0');
+  
+  signal r_mac  : std_logic_vector(6*8-1 downto 0);
+  signal r_ip   : std_logic_vector(4*8-1 downto 0);
+  signal r_port : std_logic_vector(2*8-1 downto 0);
+  
+  signal s_fsm_adr     : std_logic_vector(2 downto 0);
+  signal s_fifo_adr    : std_logic_vector(2 downto 0);
+  signal s_fifo_empty  : std_logic;
+  signal s_fifo_pop    : std_logic;
+  signal r_cache_empty : std_logic;
+  signal r_cache_adr   : std_logic_vector(2 downto 0);
+  
+  impure function update(x : std_logic_vector) return std_logic_vector is
+    alias    y : std_logic_vector(x'length-1 downto 0) is x;
+    variable o : std_logic_vector(x'length-1 downto 0);
+  begin
+    for i in (y'length/8)-1 downto 0 loop
+      if cfg_i.sel(i) = '1' then
+        o(i*8+7 downto i*8) := cfg_i.dat(i*8+7 downto i*8);
+      else
+        o(i*8+7 downto i*8) := y(i*8+7 downto i*8);
+      end if;
+    end loop;
+    
+    return o;
+  end update;
+  
+begin
+
+  cfg_o.int <= '0';
+  cfg_o.err <= '0';
+  cfg_o.rty <= '0';
+  cfg_o.stall <= '0';
+
+  cfg_wbs : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_mac  <= x"D15EA5EDBEEF";
+      r_ip   <= x"C0A80064";
+      r_port <= x"EBD0";
+      
+      cfg_o.ack <= '0';
+      cfg_o.dat <= (others => '0');
+    elsif rising_edge(clk_i) then
+      if cfg_i.cyc = '1' and cfg_i.stb = '1' and cfg_i.we = '1' then
+        case to_integer(unsigned(cfg_i.adr(4 downto 2))) is
+          when 4 => r_mac(47 downto 32) <= update(r_mac(47 downto 32));
+          when 5 => r_mac(31 downto  0) <= update(r_mac(31 downto  0));
+          when 6 => r_ip   <= update(r_ip);
+          when 7 => r_port <= update(r_port);
+          when others => null;
+        end case;
+      end if;
+      
+      cfg_o.ack <= cfg_i.cyc and cfg_i.stb;
+      
+      case to_integer(unsigned(cfg_i.adr(4 downto 2))) is
+        when 0 => cfg_o.dat <= errreg_i(63 downto 32);
+        when 1 => cfg_o.dat <= errreg_i(31 downto  0);
+        when 2 => cfg_o.dat <= (others => '0');
+        when 3 => cfg_o.dat <= g_sdb_address;
+        when 4 => cfg_o.dat <= c_pad & r_mac(47 downto 32);
+        when 5 => cfg_o.dat <= r_mac(31 downto 0);
+        when 6 => cfg_o.dat <= r_ip;
+        when others => cfg_o.dat <= c_pad & r_port;
+      end case;
+      
+    end if;
+  end process;
+
+  -- Discard writes.
+  s_fsm_adr  <= fsm_adr_i(4 downto 2);
+  
+  fifo : eb_fifo
+    generic map(
+      g_width => 3,
+      g_size  => c_queue_depth)
+    port map(
+      clk_i     => clk_i,
+      rstn_i    => rstn_i,
+      w_full_o  => fsm_full_o,
+      w_push_i  => fsm_stb_i,
+      w_dat_i   => s_fsm_adr,
+      r_empty_o => s_fifo_empty,
+      r_pop_i   => s_fifo_pop,
+      r_dat_o   => s_fifo_adr);
+      
+  s_fifo_pop <= not s_fifo_empty and (r_cache_empty or mux_pop_i);
+  
+  cache : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_cache_empty <= '1';
+      r_cache_adr   <= (others => '0');
+    elsif rising_edge(clk_i) then
+      if r_cache_empty = '1' or mux_pop_i = '1' then
+        r_cache_empty <= s_fifo_empty;
+        r_cache_adr   <= s_fifo_adr;
+      end if;
+    end if;
+  end process;
+  
+  mux_empty_o <= r_cache_empty;
+  
+  with r_cache_adr select 
+  mux_dat_o <= 
+    errreg_i(63 downto 32)      when "000",
+    errreg_i(31 downto  0)      when "001",
+    x"00000000"                 when "010",
+    g_sdb_address               when "011",
+    c_pad & r_mac(47 downto 32) when "100",
+            r_mac(31 downto  0) when "101",
+    r_ip                        when "110",
+    c_pad & r_port              when others;
+    
+  my_mac_o  <= r_mac;
+  my_ip_o   <= r_ip;
+  my_port_o <= r_port;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd
new file mode 100644
index 000000000..6eb2c9df2
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd
@@ -0,0 +1,101 @@
+--! @file eb_checksum.vhd
+--! @brief IP checksum generator for EtherBone
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH 
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+--! Lesser General Public License for more details.
+--!  
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+---! Standard library
+library IEEE;
+--! Standard packages    
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--! Additional library
+library work;
+--! Additional packages    
+use work.eb_hdr_pkg.all;
+
+entity eb_checksum is 
+  port(
+    clk_i  : in  std_logic;
+    nRst_i : in  std_logic;
+    en_i   : in  std_logic; 
+    data_i : in  std_logic_vector(15 downto 0);
+    done_o : out std_logic;
+    sum_o  : out std_logic_vector(15 downto 0));
+end eb_checksum;
+
+architecture behavioral of eb_checksum is
+  constant c_width : natural := 28;
+  type t_state is (S_IDLE, S_ADDUP);
+
+  signal state : t_state := S_IDLE;
+  signal sum   : unsigned(c_width-1 downto 0);
+
+  function f_wrap(sum : unsigned) return unsigned is
+    variable sum0, sum1 : unsigned(16 downto 0);
+  begin
+    sum0 := resize(sum(15 downto 0), 17) + resize(sum(c_width-1 downto 16), 17);
+    sum1 := resize(sum(15 downto 0), 17) + resize(sum(c_width-1 downto 16), 17) + 1;
+    if sum0(16) = '1' then
+      return sum1(15 downto 0);
+    else
+      return sum0(15 downto 0);
+    end if;
+  end f_wrap;
+  
+begin
+
+  sum_o <= std_logic_vector(sum(15 downto 0));
+  
+  adder: process(clk_i, nRst_i)
+  begin
+    if nRst_i = '0' then
+      done_o <= '0';
+      state  <= S_IDLE;
+      sum    <= (others => '0');
+    elsif rising_edge(clk_i) then
+      case state is
+        
+        when S_IDLE =>
+          done_o <= '0';
+          if en_i = '1' then
+            state <= S_ADDUP;
+            sum <= resize(unsigned(data_i), c_width);
+          end if;
+        
+        when S_ADDUP =>
+          if en_i = '0' then
+            sum <= resize(f_wrap(sum), c_width);
+            done_o <= '1';
+            state <= S_IDLE;
+          else 
+            sum <= sum + resize(unsigned(data_i), c_width);
+          end if;
+        
+      end case;
+    end if;
+  end process;
+  
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd
new file mode 100644
index 000000000..24bab963d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd
@@ -0,0 +1,123 @@
+------------------------------------------------------------------------------
+-- Title      : Etherbone Commit FIFO
+-- Project    : Etherbone Core
+------------------------------------------------------------------------------
+-- File       : eb_fifo.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2013-04-29
+-- Last update: 2013-04-29
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: A FIFO which can commit/abort a sequence of writes
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 GSI
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-04-08  1.0      terpstra        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+use work.genram_pkg.all;
+
+-- r_dat_o is valid when r_empty_o=0 (show ahead)
+-- w_dat_i is valid when w_push_i =1
+-- r_pop_i  affects r_empty_o on the next cycle
+-- w_push_i affects w_full_o  on the next cycle
+entity eb_commit_fifo is
+  generic(
+    g_width : natural;
+    g_size  : natural);
+  port(
+    clk_i      : in  std_logic;
+    rstn_i     : in  std_logic;
+    w_full_o   : out std_logic;
+    w_push_i   : in  std_logic;
+    w_dat_i    : in  std_logic_vector(g_width-1 downto 0);
+    w_commit_i : in  std_logic;
+    w_abort_i  : in  std_logic;
+    r_empty_o  : out std_logic;
+    r_pop_i    : in  std_logic;
+    r_dat_o    : out std_logic_vector(g_width-1 downto 0));
+end eb_commit_fifo;
+
+architecture rtl of eb_commit_fifo is
+  constant c_depth : natural := f_ceil_log2(g_size);
+  
+  signal r_idx  : unsigned(c_depth downto 0);
+  signal w_idx  : unsigned(c_depth downto 0);
+  signal e_idx  : unsigned(c_depth downto 0);
+  signal r_idx1 : unsigned(c_depth downto 0);
+  signal w_idx1 : unsigned(c_depth downto 0);
+  
+  constant c_low  : unsigned(c_depth-1 downto 0) := (others => '0');
+  constant c_high : unsigned(c_depth   downto 0) := '1' & c_low;
+  
+begin
+
+  ram : generic_simple_dpram
+    generic map(
+      g_data_width => g_width,
+      g_size       => 2**c_depth,
+      g_dual_clock => false)
+    port map(
+      rst_n_i => rstn_i,
+      clka_i  => clk_i,
+      bwea_i  => (others => '1'),
+      wea_i   => w_push_i,
+      aa_i    => std_logic_vector(w_idx(c_depth-1 downto 0)),
+      da_i    => w_dat_i,
+      clkb_i  => clk_i,
+      ab_i    => std_logic_vector(r_idx1(c_depth-1 downto 0)),
+      qb_o    => r_dat_o);
+  
+  r_idx1 <= (r_idx+1) when r_pop_i ='1' else r_idx;
+  w_idx1 <= (w_idx+1) when w_push_i='1' else w_idx;
+  
+  main : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_idx     <= (others => '0');
+      e_idx     <= (others => '0');
+      w_idx     <= (others => '0');
+      w_full_o  <= '0';
+      r_empty_o <= '1';
+    elsif rising_edge(clk_i) then
+      r_idx <= r_idx1;
+      
+      if w_commit_i = '1' then
+        e_idx <= w_idx1;
+      end if;
+      
+      if w_abort_i = '1' then
+        w_idx <= e_idx;
+      else
+        w_idx <= w_idx1;
+      end if;
+      
+      -- Compare the newest pointers
+      if (w_idx1 xor c_high) = r_idx1 then
+        w_full_o <= '1';
+      else
+        w_full_o <= '0';
+      end if;
+      
+      -- Use the OLD write pointer to prevent read-during-write
+      if e_idx = r_idx1 then
+        r_empty_o <= '1';
+      else
+        r_empty_o <= '0';
+      end if;
+      
+    end if;
+  end process;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd
new file mode 100644
index 000000000..e4e60e3dd
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd
@@ -0,0 +1,183 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.eb_hdr_pkg.all;
+
+entity eb_eth_rx is
+  generic(
+    g_mtu : natural);
+  port(
+    clk_i     : in  std_logic;
+    rst_n_i   : in  std_logic;
+    snk_i     : in  t_wrf_sink_in;
+    snk_o     : out t_wrf_sink_out;
+    master_o  : out t_wishbone_master_out;
+    master_i  : in  t_wishbone_master_in;
+    stb_o     : out std_logic;
+    stall_i   : in  std_logic;
+    mac_o     : out std_logic_vector(47 downto 0);
+    ip_o      : out std_logic_vector(31 downto 0);
+    port_o    : out std_logic_vector(15 downto 0);
+    length_o  : out unsigned(15 downto 0));
+end eb_eth_rx;
+
+architecture rtl of eb_eth_rx is
+  subtype t_index is unsigned(f_ceil_log2(g_mtu)-1 downto 0);
+  
+  type t_state is (S_DROP, S_WAIT, S_ETHERNET, S_IP, S_UDP, S_STB);
+  
+  -- Two bytes at a time
+  constant c_step : natural := 2;
+  
+  signal r_state      : t_state;
+  signal r_state_next : t_state;
+  signal r_count      : t_index;
+  
+  signal r_ack    : std_logic;
+  signal r_pass   : std_logic;
+  signal r_shift  : std_logic_vector(c_ip_len*8-1 downto 0);
+  signal r_stb    : std_logic;
+  signal r_mac    : std_logic_vector(47 downto 0);
+  signal r_ip     : std_logic_vector(31 downto 0);
+  signal r_port   : std_logic_vector(15 downto 0);
+  signal r_length : unsigned(15 downto 0);
+  
+  signal s_stall   : std_logic;
+  signal s_eth_hdr : t_eth_hdr;
+  signal s_ip_hdr  : t_ip_hdr;
+  signal s_udp_hdr : t_udp_hdr;
+  signal s_optlen  : unsigned(3 downto 0);
+  signal s_shift  : std_logic_vector(c_ip_len*8-1 downto 0);
+  
+  function f_step(x : natural) return t_index is
+  begin
+    return to_unsigned(x/2 - 1, t_index'length);
+  end function;
+begin
+
+  master_o.cyc <= snk_i.cyc;
+  master_o.stb <= (r_pass and snk_i.stb) when snk_i.adr = c_WRF_DATA else '0';
+  master_o.adr <= (others => '0');
+  master_o.sel <= "0011";
+  master_o.we  <= '1';
+  master_o.dat(31 downto 16) <= (others => '0');
+  master_o.dat(15 downto  0) <= snk_i.dat;
+  
+  snk_o.ack <= r_ack;
+  snk_o.err <= '0';
+  snk_o.rty <= '0';
+  snk_o.stall <= s_stall;
+  
+  stb_o    <= r_stb;
+  mac_o    <= r_mac;
+  ip_o     <= r_ip;
+  port_o   <= r_port;
+  length_o <= r_length;
+  
+  s_stall <= r_stb when r_state = S_UDP else (r_pass and master_i.stall);
+  
+  -- These are valid when header is fully shifted in
+  s_shift   <= r_shift(r_shift'left-16 downto 0) & snk_i.dat;
+  s_eth_hdr <= f_parse_eth(s_shift);
+  s_ip_hdr  <= f_parse_ip (s_shift);
+  s_udp_hdr <= f_parse_udp(s_shift);
+  
+  s_optlen <= unsigned(s_ip_hdr.ihl)-5;
+
+  fsm : process(clk_i, rst_n_i) is
+  begin
+    if rst_n_i = '0' then
+      r_state      <= S_WAIT;
+      r_state_next <= S_ETHERNET;
+      r_count      <= f_step(c_eth_len);
+      
+      r_ack    <= '0';
+      r_pass   <= '0';
+      r_shift  <= (others => '0');
+      r_stb    <= '0';
+      r_mac    <= (others => '0');
+      r_ip     <= (others => '0');
+      r_port   <= (others => '0');
+      r_length <= (others => '0');
+    elsif rising_edge(clk_i) then
+      r_ack   <= snk_i.cyc and snk_i.stb and not s_stall;
+      r_stb   <= r_stb and stall_i;
+      
+      if snk_i.cyc = '0' then
+        r_pass       <= '0';
+        r_state      <= S_WAIT;
+        r_state_next <= S_ETHERNET;
+        r_count      <= f_step(c_eth_len);
+      elsif snk_i.stb = '1' and s_stall = '0' and snk_i.adr = c_WRF_DATA then
+      
+        -- defaults
+        r_state      <= S_WAIT;
+        r_state_next <= S_DROP;
+        r_count      <= r_count - 1;
+        r_shift      <= s_shift;
+        
+        case r_state is
+          -- special states
+          when S_DROP => 
+            r_state <= S_DROP;
+            r_pass <= '0';
+            
+          when S_WAIT =>
+            r_state_next <= r_state_next;
+            if r_count = to_unsigned(1, r_count'length) then
+              r_state <= r_state_next;
+            end if;
+          
+          -- payload states
+          when S_ETHERNET =>
+            r_mac <= s_eth_hdr.src;
+            
+            r_count <= f_step(c_ip_len);
+            if s_eth_hdr.typ = c_eth_typ_ip then
+              r_state_next <= S_IP;
+            else
+              r_state <= S_DROP;
+            end if;
+          
+          when S_IP =>
+            r_ip <= s_ip_hdr.src;
+            
+            r_count <= f_step(to_integer(s_optlen)*4 + c_udp_len);
+            if s_ip_hdr.ver = x"4" and unsigned(s_ip_hdr.ihl) >= 5 and s_ip_hdr.pro = c_ip_typ_udp then
+              r_state_next <= S_UDP;
+            else
+              r_state <= S_DROP;
+            end if;
+          
+          when S_UDP =>
+            r_port   <= s_udp_hdr.src;
+            r_length <= unsigned(s_udp_hdr.len);
+            
+            -- Raise stb four bytes after fsm starts (=> fsm will TX)
+            r_count <= f_step(4);
+            
+            -- Enforce MTU and 4-byte alignment
+            if unsigned(s_udp_hdr.len) >= 12 and 
+               unsigned(s_udp_hdr.len) <= g_mtu-c_ip_len and
+               s_udp_hdr.len(1 downto 0) = "00" then
+              r_pass <= '1'; -- Feed future bytes to etherbone fsm
+              r_state_next <= S_STB;
+            else
+              r_state <= S_DROP;
+            end if;
+          
+          when S_STB =>
+            r_stb   <= '1'; -- this must be 4 bytes after r_pass='1'
+            r_count <= f_step(to_integer(r_length)-c_udp_len-4);
+            r_state_next <= S_DROP;
+          
+        end case;
+      end if;
+    end if;
+  end process;
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd
new file mode 100644
index 000000000..661c7712d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd
@@ -0,0 +1,332 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.eb_internals_pkg.all;
+use work.eb_hdr_pkg.all;
+
+entity eb_eth_tx is
+  generic(
+    g_mtu : natural);
+  port(
+    clk_i        : in  std_logic;
+    rst_n_i      : in  std_logic;
+    src_i        : in  t_wrf_source_in;
+    src_o        : out t_wrf_source_out;
+    slave_o      : out t_wishbone_slave_out;
+    slave_i      : in  t_wishbone_slave_in;
+    stb_i        : in  std_logic;
+    stall_o      : out std_logic;
+    mac_i        : in  std_logic_vector(47 downto 0);
+    ip_i         : in  std_logic_vector(31 downto 0);
+    port_i       : in  std_logic_vector(15 downto 0);
+    length_i     : in  unsigned(15 downto 0);
+    skip_stb_i   : in  std_logic;
+    skip_stall_o : out std_logic;
+    my_mac_i     : in  std_logic_vector(47 downto 0);
+    my_ip_i      : in  std_logic_vector(31 downto 0);
+    my_port_i    : in  std_logic_vector(15 downto 0));
+end eb_eth_tx;
+
+architecture rtl of eb_eth_tx is
+  type t_state is (S_WRF_STATUS, S_ETHERNET, S_IP, S_UDP, S_DONE, S_WAIT, S_PAYLOAD, S_RUNT, S_LOWER, S_SKIP, S_PUSH);
+  type t_sum_state is (S_CONST, S_DST_HI, S_DST_LO, S_SRC_HI, S_SRC_LO, S_LENGTH, S_DONE);
+  
+  signal r_state  : t_state;
+  signal r_staten : t_state;
+  signal r_count  : unsigned(4 downto 0);
+  
+  signal r_ready  : std_logic;
+  signal r_mac    : std_logic_vector(47 downto 0);
+  signal r_ip     : std_logic_vector(31 downto 0);
+  signal r_port   : std_logic_vector(15 downto 0);
+  signal r_length : unsigned(15 downto 0);
+
+  signal r_hdr_stb : std_logic;
+  signal r_shift   : std_logic_vector(c_ip_len*8-1 downto 0);
+  signal r_ack     : std_logic;
+  signal s_stall   : std_logic;
+  
+  signal s_buf_stb    : std_logic;
+  signal s_buf_full   : std_logic;
+  signal s_buf_push   : std_logic;
+  signal s_buf_commit : std_logic;
+  signal s_buf_abort  : std_logic;
+  signal s_buf_cyc    : std_logic;
+  signal s_buf_data   : std_logic_vector(15 downto 0);
+  signal r_buf_typ    : std_logic;
+  
+  signal r_tx_cyc   : std_logic;
+  signal s_tx_empty : std_logic;
+  signal s_tx_pop   : std_logic;
+  signal s_tx_cyc   : std_logic;
+  signal s_tx_typ   : std_logic;
+  signal s_tx_dat   : std_logic_vector(15 downto 0);
+  
+  signal r_sum_state : t_sum_state;
+  signal r_sum_en    : std_logic;
+  signal r_sum_data  : std_logic_vector(15 downto 0);
+  signal s_sum_done  : std_logic_vector(15 downto 0);
+  
+  constant c_hdr_len  : natural := c_ip_len;
+  constant c_runt_min : natural := 46 - c_ip_len;
+  
+  function f_send_eth(dst, src : std_logic_vector(47 downto 0)) return std_logic_vector is
+    variable o : std_logic_vector(c_hdr_len*8-1 downto 0) := (others => '-');
+    variable eth : t_eth_hdr := c_eth_init;
+  begin
+    eth.dst := dst;
+    eth.src := src;
+    o(o'left downto (c_hdr_len-c_eth_len)*8) := f_format_eth(eth);
+    return o;
+  end function;
+  
+  function f_send_ip(dst, src : std_logic_vector(31 downto 0); len : unsigned(15 downto 0); sum : std_logic_vector(15 downto 0)) return std_logic_vector is
+    variable o : std_logic_vector(c_hdr_len*8-1 downto 0) := (others => '-');
+    variable ip : t_ip_hdr := c_ip_init;
+  begin
+    ip.tol := std_logic_vector(len+20);
+    ip.dst := dst;
+    ip.src := src;
+    ip.sum := not sum;
+    o(o'left downto (c_hdr_len-c_ip_len)*8) := f_format_ip(ip);
+    return o;
+  end function;
+  
+  function f_send_udp(dst, src : std_logic_vector(15 downto 0); len : unsigned(15 downto 0)) return std_logic_vector is
+    variable o : std_logic_vector(c_hdr_len*8-1 downto 0) := (others => '-');
+    variable udp : t_udp_hdr := c_udp_init;
+  begin
+    udp.src := src;
+    udp.dst := dst;
+    udp.len := std_logic_vector(len);
+    o(o'left downto (c_hdr_len-c_udp_len)*8) := f_format_udp(udp);
+    return o;
+  end function;
+  
+  function f_step(x : natural) return unsigned is
+  begin
+    return to_unsigned(x/2 - 1, 5);
+  end function;
+  
+begin
+
+  tx : eb_commit_fifo
+    generic map(
+      g_width => 18,
+      g_size  => (g_mtu+c_eth_len)/2)
+    port map(
+      clk_i      => clk_i,
+      rstn_i     => rst_n_i,
+      w_full_o   => s_buf_full,
+      w_push_i   => s_buf_push,
+      w_commit_i => s_buf_commit,
+      w_abort_i  => s_buf_abort,
+      r_empty_o  => s_tx_empty,
+      r_pop_i    => s_tx_pop,
+      w_dat_i(17)          => s_buf_cyc,
+      w_dat_i(16)          => r_buf_typ,
+      w_dat_i(15 downto 0) => s_buf_data,
+      r_dat_o(17)          => s_tx_cyc,
+      r_dat_o(16)          => s_tx_typ,
+      r_dat_o(15 downto 0) => s_tx_dat);
+  
+  slave_o.ack <= r_ack;
+  slave_o.int <= '0';
+  slave_o.rty <= '0';
+  slave_o.err <= '0';
+  slave_o.stall <= s_stall;
+  slave_o.dat <= (others => '0');
+  
+  stall_o <= r_ready; -- already have params
+  
+  s_stall      <= s_buf_full when r_state=S_PAYLOAD else '1';
+  skip_stall_o <= '0' when r_state=S_SKIP else '1';
+  s_buf_stb    <= (slave_i.cyc and slave_i.stb) when r_state=S_PAYLOAD else r_hdr_stb;
+  s_buf_push   <= s_buf_stb and not s_buf_full;
+  s_buf_abort  <= '1' when r_state=S_SKIP  else '0';
+  s_buf_commit <= '1' when r_state=S_LOWER else '0';
+  s_buf_cyc    <= '0' when r_state=S_LOWER else '1';
+  s_buf_data   <= slave_i.dat(15 downto 0) when r_state=S_PAYLOAD else r_shift(r_shift'left downto r_shift'left-15);
+  
+  hdr : process(clk_i, rst_n_i) is
+  begin
+    if rst_n_i = '0' then
+      r_state   <= S_WRF_STATUS;
+      r_staten  <= S_WRF_STATUS;
+      r_count   <= (others => '0');
+      r_ready   <= '0';
+      r_mac     <= (others => '0');
+      r_ip      <= (others => '0');
+      r_port    <= (others => '0');
+      r_length  <= (others => '0');
+      r_hdr_stb <= '0';
+      r_ack     <= '0';
+      r_shift   <= (others => '-');
+      r_tx_cyc  <= '0';
+    elsif rising_edge(clk_i) then
+      r_ack <= slave_i.cyc and slave_i.stb and not s_stall;
+      
+      if s_tx_empty = '0' then
+        r_tx_cyc <= s_tx_cyc;
+      end if;
+      
+      if stb_i = '1' and r_ready = '0' then
+        r_mac    <= mac_i;
+        r_ip     <= ip_i;
+        r_port   <= port_i;
+        r_length <= length_i;
+        r_ready  <= '1';
+      end if;
+      
+      case r_state is
+        when S_WRF_STATUS =>
+          if r_ready = '1' then
+            r_hdr_stb <= '1';
+            r_buf_typ <= '1';
+            r_shift   <= (others => '0');
+            r_state   <= S_ETHERNET;
+          end if;
+        
+        when S_ETHERNET =>
+          if s_buf_full = '0' then
+            r_buf_typ <= '0';
+            r_shift   <= f_send_eth(r_mac, my_mac_i);
+            r_count   <= f_step(c_eth_len);
+            r_staten  <= S_IP;
+            r_state   <= S_PUSH;
+          end if;
+          
+        when S_IP =>
+          if s_buf_full = '0' then
+            r_shift  <= f_send_ip(r_ip, my_ip_i, r_length, s_sum_done);
+            r_count  <= f_step(c_ip_len);
+            r_staten <= S_UDP;
+            r_state  <= S_PUSH;
+          end if;
+        
+        when S_UDP =>
+          if s_buf_full = '0' then
+            r_shift  <= f_send_udp(r_port, my_port_i, r_length);
+            r_count  <= f_step(c_udp_len);
+            r_staten <= S_DONE;
+            r_state  <= S_PUSH;
+          end if;
+        
+        when S_DONE =>
+          if s_buf_full = '0' then
+            r_ready   <= '0'; -- can latch next header params
+            r_hdr_stb <= '0'; -- nothing more from the header side of things
+            
+            -- After payload, may need to add runt padding
+            r_shift <= (others => '0');
+            
+            if r_length < c_runt_min then
+              r_staten <= S_RUNT;
+              r_count <= f_step(c_runt_min - to_integer(r_length));
+            else
+              r_staten <= S_LOWER;
+              r_count <= (others => '-');
+            end if;
+            
+            -- Make sure we don't skip the payload!
+            if slave_i.cyc = '1' then
+              r_state <= S_PAYLOAD;
+            elsif skip_stb_i = '1' then
+              r_state <= S_SKIP;
+            else
+              r_state <= S_WAIT;
+            end if;
+          end if;
+          
+        when S_WAIT =>
+          if slave_i.cyc = '1' then
+            r_state <= S_PAYLOAD;
+          elsif skip_stb_i = '1' then
+            r_state <= S_SKIP;
+          end if;
+        
+        when S_PAYLOAD =>
+          if slave_i.cyc = '0' then
+            r_hdr_stb <= '1';
+            r_state <= r_staten;
+          end if;
+        
+        when S_RUNT =>
+          if s_buf_full = '0' then
+            r_state   <= S_PUSH;
+            r_staten  <= S_LOWER;
+          end if;
+        
+        when S_LOWER =>
+          if s_buf_full = '0' then
+            r_hdr_stb <= '0';
+            r_state <= S_WRF_STATUS;
+          end if;
+        
+        when S_SKIP =>
+          r_state <= S_WRF_STATUS;
+        
+        when S_PUSH =>
+          if s_buf_full = '0' then
+            r_count <= r_count - 1;
+            r_shift <= r_shift(r_shift'left-16 downto 0) & x"0000";
+            
+            if r_count = to_unsigned(1, r_count'length) then
+              r_state <= r_staten;
+            end if;
+          end if;
+          
+      end case;
+    end if;
+  end process;
+
+  src_o.cyc <= s_tx_cyc when s_tx_empty='0' else r_tx_cyc;
+  src_o.stb <= not s_tx_empty;
+  src_o.adr <= c_WRF_STATUS when s_tx_typ='1' else c_WRF_DATA;
+  src_o.we  <= '1';
+  src_o.sel <= "11";
+  src_o.dat <= s_tx_dat;
+  
+  s_tx_pop <= not s_tx_empty and not (s_tx_cyc and src_i.stall);
+  
+  sum : eb_checksum
+    port map(
+      clk_i => clk_i,
+      nRst_i => rst_n_i,
+      en_i   => r_sum_en,
+      data_i => r_sum_data,
+      done_o => open,
+      sum_o  => s_sum_done);
+  
+  sum_header : process(clk_i, rst_n_i) is
+  begin
+    if rst_n_i = '0' then
+      r_sum_state <= S_CONST;
+      r_sum_en    <= '0';
+      r_sum_data  <= (others => '0');
+    elsif rising_edge(clk_i) then
+    
+      case r_sum_state is
+        when S_CONST =>
+          r_sum_data <= f_checksum(f_format_ip(c_ip_init));
+          if stb_i = '1' and r_ready = '0' then
+            r_sum_en    <= '1';
+            r_sum_state <= S_DST_HI;
+          end if;
+        
+        when S_DST_HI => r_sum_state <= S_DST_LO; r_sum_data <=    r_ip(31 downto 16);
+        when S_DST_LO => r_sum_state <= S_SRC_HI; r_sum_data <=    r_ip(15 downto  0);
+        when S_SRC_HI => r_sum_state <= S_SRC_LO; r_sum_data <= my_ip_i(31 downto 16);
+        when S_SRC_LO => r_sum_state <= S_LENGTH; r_sum_data <= my_ip_i(15 downto  0);
+        when S_LENGTH => r_sum_state <= S_DONE;   r_sum_data <= std_logic_vector(r_length+20);
+        when S_DONE   => r_sum_state <= S_CONST;  r_sum_en <= '0';
+      end case;
+      
+    end if;
+  end process;
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd
new file mode 100644
index 000000000..304333085
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd
@@ -0,0 +1,164 @@
+--! @file eb_ethernet_slave.vhd
+--! @brief Top file for EtherBone core
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH 
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--! @author Wesley W. Terpstra <w.terpstra@gsi.de>
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+--! Lesser General Public License for more details.
+--!  
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+--! Standard library
+library IEEE;
+--! Standard packages    
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library work;
+use work.etherbone_pkg.all;
+use work.eb_hdr_pkg.all;
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.eb_internals_pkg.all;
+
+entity eb_ethernet_slave is
+  generic(
+    g_sdb_address    : std_logic_vector(63 downto 0);
+    g_timeout_cycles : natural;
+    g_mtu            : natural);
+  port(
+    clk_i       : in  std_logic;
+    nRst_i      : in  std_logic;
+    snk_i       : in  t_wrf_sink_in;
+    snk_o       : out t_wrf_sink_out;
+    src_o       : out t_wrf_source_out;
+    src_i       : in  t_wrf_source_in;
+    cfg_slave_o : out t_wishbone_slave_out;
+    cfg_slave_i : in  t_wishbone_slave_in;
+    master_o    : out t_wishbone_master_out;
+    master_i    : in  t_wishbone_master_in);
+end eb_ethernet_slave;
+
+
+architecture rtl of eb_ethernet_slave is
+  signal s_his_mac,  s_my_mac  : std_logic_vector(47 downto 0);
+  signal s_his_ip,   s_my_ip   : std_logic_vector(31 downto 0);
+  signal s_his_port, s_my_port : std_logic_vector(15 downto 0);
+  
+  signal s_tx_stb     : std_logic;
+  signal s_tx_stall   : std_logic;
+  signal s_skip_stb   : std_logic;
+  signal s_skip_stall : std_logic;
+  signal s_length     : unsigned(15 downto 0); -- of UDP in words
+  
+  signal s_rx2widen   : t_wishbone_master_out;
+  signal s_widen2rx   : t_wishbone_master_in;
+  signal s_widen2fsm  : t_wishbone_master_out;
+  signal s_fsm2widen  : t_wishbone_master_in;
+  signal s_fsm2narrow : t_wishbone_master_out;
+  signal s_narrow2fsm : t_wishbone_master_in;
+  signal s_narrow2tx  : t_wishbone_master_out;
+  signal s_tx2narrow  : t_wishbone_master_in;
+  
+begin
+  rx : eb_eth_rx
+    generic map(
+      g_mtu => g_mtu)
+    port map(
+      clk_i     => clk_i,
+      rst_n_i   => nRst_i,
+      snk_i     => snk_i,
+      snk_o     => snk_o,
+      master_o  => s_rx2widen,
+      master_i  => s_widen2rx,
+      stb_o     => s_tx_stb,
+      stall_i   => s_tx_stall,
+      mac_o     => s_his_mac,
+      ip_o      => s_his_ip,
+      port_o    => s_his_port,
+      length_o  => s_length);
+  
+  widen : eb_stream_widen
+    generic map(
+      g_slave_width  => 16,
+      g_master_width => 32)
+    port map(
+      clk_i    => clk_i,
+      rst_n_i  => nRst_i,
+      slave_i  => s_rx2widen,
+      slave_o  => s_widen2rx,
+      master_i => s_fsm2widen,
+      master_o => s_widen2fsm);
+      
+  eb : eb_slave_top
+    generic map(
+      g_sdb_address    => g_sdb_address(31 downto 0),
+      g_timeout_cycles => g_timeout_cycles)
+    port map(
+      clk_i        => clk_i,
+      nRst_i       => nRst_i,
+      EB_RX_i      => s_widen2fsm,
+      EB_RX_o      => s_fsm2widen,
+      EB_TX_i      => s_narrow2fsm,
+      EB_TX_o      => s_fsm2narrow,
+      skip_stb_o   => s_skip_stb,
+      skip_stall_i => s_skip_stall,
+      WB_config_i  => cfg_slave_i,
+      WB_config_o  => cfg_slave_o,
+      WB_master_i  => master_i,
+      WB_master_o  => master_o,
+      my_mac_o     => s_my_mac,
+      my_ip_o      => s_my_ip,
+      my_port_o    => s_my_port);
+
+  narrow : eb_stream_narrow
+    generic map(
+      g_slave_width  => 32,
+      g_master_width => 16)
+    port map(
+      clk_i    => clk_i,
+      rst_n_i  => nRst_i,
+      slave_i  => s_fsm2narrow,
+      slave_o  => s_narrow2fsm,
+      master_i => s_tx2narrow,
+      master_o => s_narrow2tx);
+
+  tx : eb_eth_tx
+    generic map(
+      g_mtu => g_mtu)
+    port map(
+      clk_i        => clk_i,
+      rst_n_i      => nRst_i,
+      src_i        => src_i,
+      src_o        => src_o,
+      slave_o      => s_tx2narrow,
+      slave_i      => s_narrow2tx,
+      stb_i        => s_tx_stb,
+      stall_o      => s_tx_stall,
+      mac_i        => s_his_mac,
+      ip_i         => s_his_ip,
+      port_i       => s_his_port,
+      length_i     => s_length,
+      skip_stb_i   => s_skip_stb,
+      skip_stall_o => s_skip_stall,
+      my_mac_i     => s_my_mac,
+      my_ip_i      => s_my_ip,
+      my_port_i    => s_my_port);
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd
new file mode 100644
index 000000000..22ac21364
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd
@@ -0,0 +1,112 @@
+------------------------------------------------------------------------------
+-- Title      : Etherbone FIFO
+-- Project    : Etherbone Core
+------------------------------------------------------------------------------
+-- File       : eb_fifo.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2013-04-08
+-- Last update: 2013-04-08
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: A convenience wrapper for FIFOs used in Etherbone
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 GSI
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-04-08  1.0      terpstra        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+use work.genram_pkg.all;
+
+-- r_dat_o is valid when r_empty_o=0 (show ahead)
+-- w_dat_i is valid when w_push_i =1
+-- r_pop_i  affects r_empty_o on the next cycle
+-- w_push_i affects w_full_o  on the next cycle
+entity eb_fifo is
+  generic(
+    g_width : natural;
+    g_size  : natural);
+  port(
+    clk_i     : in  std_logic;
+    rstn_i    : in  std_logic;
+    w_full_o  : out std_logic;
+    w_push_i  : in  std_logic;
+    w_dat_i   : in  std_logic_vector(g_width-1 downto 0);
+    r_empty_o : out std_logic;
+    r_pop_i   : in  std_logic;
+    r_dat_o   : out std_logic_vector(g_width-1 downto 0));
+end eb_fifo;
+
+architecture rtl of eb_fifo is
+  constant c_depth : natural := f_ceil_log2(g_size);
+  
+  signal r_idx  : unsigned(c_depth downto 0);
+  signal w_idx  : unsigned(c_depth downto 0);
+  signal r_idx1 : unsigned(c_depth downto 0);
+  signal w_idx1 : unsigned(c_depth downto 0);
+  
+  constant c_low  : unsigned(c_depth-1 downto 0) := (others => '0');
+  constant c_high : unsigned(c_depth   downto 0) := '1' & c_low;
+  
+begin
+
+  ram : generic_simple_dpram
+    generic map(
+      g_data_width => g_width,
+      g_size       => g_size,
+      g_dual_clock => false)
+    port map(
+      rst_n_i => rstn_i,
+      
+      clka_i  => clk_i,
+      bwea_i  => (others => '1'),
+      wea_i   => w_push_i,
+      aa_i    => std_logic_vector(w_idx(c_depth-1 downto 0)),
+      da_i    => w_dat_i,
+      
+      clkb_i  => clk_i,
+      ab_i    => std_logic_vector(r_idx1(c_depth-1 downto 0)),
+      qb_o    => r_dat_o);
+  
+  r_idx1 <= (r_idx+1) when r_pop_i ='1' else r_idx;
+  w_idx1 <= (w_idx+1) when w_push_i='1' else w_idx;
+  
+  main : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_idx     <= (others => '0');
+      w_idx     <= (others => '0');
+      w_full_o  <= '0';
+      r_empty_o <= '1';
+    elsif rising_edge(clk_i) then
+      r_idx <= r_idx1;
+      w_idx <= w_idx1;
+      
+      -- Compare the newest pointers
+      if (w_idx1 xor c_high) = r_idx1 then
+        w_full_o <= '1';
+      else
+        w_full_o <= '0';
+      end if;
+      
+      -- Use the OLD write pointer to prevent read-during-write
+      if w_idx = r_idx1 then
+        r_empty_o <= '1';
+      else
+        r_empty_o <= '0';
+      end if;
+      
+    end if;
+  end process;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd
new file mode 100644
index 000000000..c7d40aa07
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd
@@ -0,0 +1,271 @@
+--! @file eb_hdr_pkg.vhd
+--! @brief EtherBone Header definitions - Eth, IPV4, UDP, EB
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH 
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--! @author Wesley W. Terpstra <w.terpstra@gsi.de>
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+--! Lesser General Public License for more details.
+--!  
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+
+package eb_hdr_pkg is
+
+  constant c_eth_typ_ip : std_logic_vector((2*8)-1 downto 0) := x"0800";
+  type t_eth_hdr is record
+    dst : std_logic_vector((6*8)-1 downto 0); 
+    src : std_logic_vector((6*8)-1 downto 0);
+    typ : std_logic_vector((2*8)-1 downto 0);
+  end record;
+  constant c_eth_len : natural := 14;
+  constant c_eth_init : t_eth_hdr := (
+    dst => (others => '0'), -- set!
+    src => (others => '0'), -- set!
+    typ => c_eth_typ_ip);
+  
+  constant c_ip_typ_udp : std_logic_vector(7 downto 0) := x"11";
+  type t_ip_hdr is record
+    ver : std_logic_vector(3 downto 0);
+    ihl : std_logic_vector(3 downto 0);
+    tos : std_logic_vector(7 downto 0);
+    tol : std_logic_vector(15 downto 0);
+    id  : std_logic_vector(15 downto 0);
+    flg : std_logic_vector(2 downto 0);
+    fro : std_logic_vector(12 downto 0);
+    ttl : std_logic_vector(7 downto 0);
+    pro : std_logic_vector(7 downto 0);
+    sum : std_logic_vector(15 downto 0);
+    src : std_logic_vector(31 downto 0);
+    dst : std_logic_vector(31 downto 0);
+  end record;
+  constant c_ip_len : natural := 20;
+  constant c_ip_init : t_ip_hdr := (
+    ver => x"4",
+    ihl => x"5",
+    tos => x"00",
+    tol => (others => '0'),  -- set!
+    id  => (others => '0'),
+    flg => "010", -- don't fragment
+    fro => (others => '0'),
+    ttl => x"3f",
+    pro => c_ip_typ_udp,
+    sum => (others => '0'),  -- set!
+    src => (others => '0'),  -- set!
+    dst => (others => '0')); -- set!
+  
+  type t_udp_hdr is record
+    src : std_logic_vector(15 downto 0);
+    dst : std_logic_vector(15 downto 0);
+    len : std_logic_vector(15 downto 0);
+    sum : std_logic_vector(15 downto 0);
+  end record;
+  constant c_udp_len : natural := 8;
+  constant c_udp_init : t_udp_hdr := (
+    src => (others => '0'),  -- set!
+    dst => (others => '0'),  -- set!
+    len => (others => '0'),  -- set!
+    sum => (others => '0'));
+  
+  constant c_eb_magic : std_logic_vector(15 downto 0) := x"4e6f";
+  constant c_eb_ver   : std_logic_vector(3 downto 0) := x"1";
+  type t_eb_hdr is record
+    magic       : std_logic_vector(15 downto 0);
+    ver         : std_logic_vector(3 downto 0);
+    res1        : std_logic;
+    no_response : std_logic;
+    probe_res   : std_logic;
+    probe       : std_logic;
+    addr_size   : std_logic_vector(3 downto 0);
+    data_size   : std_logic_vector(3 downto 0);
+  end record;
+  constant c_eb_len : natural := 4;
+  constant c_eb_init : t_eb_hdr := (
+    magic       => c_eb_magic,
+    ver         => c_eb_ver,
+    res1        => '0',
+    no_response => '1',
+    probe_res   => '0',
+    probe       => '0',
+    addr_size   => x"4", -- 32-bit only
+    data_size   => x"4");
+  
+  type t_rec_hdr is record
+    bca_cfg  : std_logic;
+    rca_cfg  : std_logic;
+    rd_fifo  : std_logic;
+    res1     : std_logic;
+    drop_cyc : std_logic;
+    wca_cfg  : std_logic;
+    wr_fifo  : std_logic;
+    res2     : std_logic;
+    sel      : std_logic_vector(7 downto 0);
+    wr_cnt   : unsigned(7 downto 0);
+    rd_cnt   : unsigned(7 downto 0);
+  end record;
+  constant c_rec_len : natural := 4;
+  constant c_rec_init : t_rec_hdr := (
+    bca_cfg  => '0',
+    rca_cfg  => '0',
+    rd_fifo  => '0',
+    res1     => '0',
+    drop_cyc => '0',
+    wca_cfg  => '0',
+    wr_fifo  => '0',
+    res2     => '0',
+    sel      => (others => '0'),
+    wr_cnt   => (others => '0'),
+    rd_cnt   => (others => '0'));
+  
+  function f_parse_eth(x : std_logic_vector) return t_eth_hdr;
+  function f_parse_ip (x : std_logic_vector) return t_ip_hdr;
+  function f_parse_udp(x : std_logic_vector) return t_udp_hdr;
+  function f_parse_eb (x : std_logic_vector) return t_eb_hdr;
+  function f_parse_rec(x : std_logic_vector) return t_rec_hdr;
+  
+  function f_format_eth(x : t_eth_hdr) return std_logic_vector; --(c_eth_len*8-1 downto 0);
+  function f_format_ip (x : t_ip_hdr)  return std_logic_vector; --(c_ip_len *8-1 downto 0);
+  function f_format_udp(x : t_udp_hdr) return std_logic_vector; --(c_udp_len*8-1 downto 0);
+  function f_format_eb (x : t_eb_hdr)  return std_logic_vector; --(c_eb_len *8-1 downto 0);
+  function f_format_rec(x : t_rec_hdr) return std_logic_vector; --(c_rec_len*8-1 downto 0);
+  
+  -- To be used only on constants!
+  function f_checksum(x : std_logic_vector) return std_logic_vector;
+  
+end package;
+
+package body eb_hdr_pkg is
+
+  function f_parse_eth(x : std_logic_vector) return t_eth_hdr is
+    variable o : t_eth_hdr;
+  begin
+    o.dst := x(111 downto 64);
+    o.src := x( 63 downto 16);
+    o.typ := x( 15 downto  0);
+    return o;
+  end function;
+   
+  function f_parse_ip(x : std_logic_vector) return t_ip_hdr is
+    variable o : t_ip_hdr;
+  begin
+    o.ver := x(159 downto 156);
+    o.ihl := x(155 downto 152);
+    o.tos := x(151 downto 144);
+    o.tol := x(143 downto 128);
+    o.id  := x(127 downto 112);
+    o.flg := x(111 downto 109);
+    o.fro := x(108 downto 96);
+    o.ttl := x(95 downto 88);
+    o.pro := x(87 downto 80);
+    o.sum := x(79 downto 64);
+    o.src := x(63 downto 32);
+    o.dst := x(31 downto 0);
+    return o;
+  end function;
+   
+  function f_parse_udp(x : std_logic_vector) return t_udp_hdr is
+    variable o : t_udp_hdr;
+  begin
+    o.src := x(63 downto 48);
+    o.dst := x(47 downto 32);
+    o.len := x(31 downto 16);
+    o.sum := x(15 downto  0);
+    return o;
+  end function;
+  
+  function f_parse_eb(x : std_logic_vector) return t_eb_hdr is
+    variable o : t_eb_hdr;
+  begin
+    o.magic       := x(31 downto 16);
+    o.ver         := x(15 downto 12);
+    o.res1        := x(11);
+    o.no_response := x(10);
+    o.probe_res   := x(9);
+    o.probe       := x(8);
+    o.addr_size   := x( 7 downto  4);
+    o.data_size   := x( 3 downto  0);
+    return o;
+  end function;
+   
+  function f_parse_rec(x : std_logic_vector) return t_rec_hdr is
+    variable o : t_rec_hdr;
+  begin
+    o.bca_cfg  := x(31);
+    o.rca_cfg  := x(30);
+    o.rd_fifo  := x(29);
+    o.res1     := x(28);
+    o.drop_cyc := x(27);
+    o.wca_cfg  := x(26);
+    o.wr_fifo  := x(25);
+    o.res2     := x(24);
+    o.sel      := x(23 downto 16);
+    o.wr_cnt   := unsigned(x(15 downto 8));
+    o.rd_cnt   := unsigned(x( 7 downto 0));
+    return o;
+  end function;
+   
+  function f_format_eth(x : t_eth_hdr) return std_logic_vector is
+  begin
+    return x.dst & x.src & x.typ;
+  end function;
+  
+  function f_format_ip (x : t_ip_hdr) return std_logic_vector is
+  begin
+    return x.ver & x.ihl & x.tos & x.tol & x.id  & x.flg &
+           x.fro & x.ttl & x.pro & x.sum & x.src & x.dst;
+  end function;
+  
+  function f_format_udp(x : t_udp_hdr) return std_logic_vector is
+  begin
+    return x.src & x.dst & x.len & x.sum;
+  end function;
+  
+  function f_format_eb (x : t_eb_hdr)  return std_logic_vector is
+  begin
+    return x.magic & x.ver & x.res1 & x.no_response & x.probe_res &
+           x.probe & x.addr_size & x.data_size;
+  end function;
+  
+  function f_format_rec(x : t_rec_hdr) return std_logic_vector is
+  begin
+    return x.bca_cfg  & x.rca_cfg & x.rd_fifo & x.res1 & 
+           x.drop_cyc & x.wca_cfg & x.wr_fifo & x.res2 & 
+           x.sel & std_logic_vector(x.wr_cnt) & std_logic_vector(x.rd_cnt);
+  end function;
+  
+  function f_checksum(x : std_logic_vector) return std_logic_vector is
+    alias y : std_logic_vector((x'length/16)*16-1 downto 0) is x;
+    variable o : unsigned(16 downto 0) := (others => '0');
+  begin
+    for i in y'length/16-1 downto 0 loop
+      o := o + ('0' & unsigned(y(i*16+15 downto i*16)));
+      if o(16) = '1' then
+        o := o + 1;
+        o(16) := '0';
+      end if;
+    end loop;
+    return std_logic_vector(o(15 downto 0));
+  end function;
+  
+end package body;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd
new file mode 100644
index 000000000..27fc5a893
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd
@@ -0,0 +1,418 @@
+library IEEE;
+--! Standard packages
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--! Additional library
+library work;
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.eb_hdr_pkg.all;
+
+package eb_internals_pkg is 
+
+  subtype t_tag is std_logic_vector(2 downto 0);
+
+  constant c_tag_drop_tx : t_tag := "000";
+  constant c_tag_skip_tx : t_tag := "001";
+  constant c_tag_pass_tx : t_tag := "010";
+  constant c_tag_pass_on : t_tag := "011";
+  constant c_tag_cfg_req : t_tag := "100";
+  constant c_tag_cfg_ign : t_tag := "101";
+  constant c_tag_wbm_req : t_tag := "110";
+  constant c_tag_wbm_ign : t_tag := "111";
+  
+  constant c_queue_depth : natural := 32;
+
+  component eb_slave_top is
+    generic(
+      g_sdb_address    : t_wishbone_address;
+      g_timeout_cycles : natural);
+    port(
+      clk_i       : in std_logic;  --! System Clk
+      nRst_i      : in std_logic;  --! active low sync reset
+
+      EB_RX_i     : in  t_wishbone_slave_in;   --! Streaming wishbone(record) sink from RX transport protocol block
+      EB_RX_o     : out t_wishbone_slave_out;  --! Streaming WB sink flow control to RX transport protocol block
+      EB_TX_i     : in  t_wishbone_master_in;  --! Streaming WB src flow control from TX transport protocol block
+      EB_TX_o     : out t_wishbone_master_out; --! Streaming WB src to TX transport protocol block
+      
+      skip_stb_o  : out std_logic; --! Does a packet get discarded?
+      skip_stall_i: in  std_logic;
+
+      WB_config_i : in  t_wishbone_slave_in;    --! WB V4 interface to WB interconnect/device(s)
+      WB_config_o : out t_wishbone_slave_out;   --! WB V4 interface to WB interconnect/device(s)
+      WB_master_i : in  t_wishbone_master_in;   --! WB V4 interface to WB interconnect/device(s)
+      WB_master_o : out t_wishbone_master_out;  --! WB V4 interface to WB interconnect/device(s)
+      
+      my_mac_o    : out std_logic_vector(47 downto 0);
+      my_ip_o     : out std_logic_vector(31 downto 0);
+      my_port_o   : out std_logic_vector(15 downto 0));
+  end component;
+
+  component eb_slave_fsm is
+    port(
+      clk_i       : in  std_logic;
+      rstn_i      : in  std_logic;
+      
+      rx_cyc_i    : in  std_logic;
+      rx_stb_i    : in  std_logic;
+      rx_dat_i    : in  t_wishbone_data;
+      rx_stall_o  : out std_logic;
+      
+      tag_stb_o   : out std_logic;
+      tag_dat_o   : out t_tag;
+      tag_full_i  : in  std_logic;
+      
+      pass_stb_o  : out std_logic;
+      pass_dat_o  : out t_wishbone_data;
+      pass_full_i : in  std_logic;
+      
+      cfg_stb_o   : out std_logic;
+      cfg_adr_o   : out t_wishbone_address;
+      cfg_full_i  : in  std_logic;
+      
+      wbm_stb_o   : out std_logic;
+      wbm_full_i  : in  std_logic;
+      wbm_busy_i  : in  std_logic;
+      
+      master_o       : out t_wishbone_master_out;
+      master_stall_i : in  std_logic);
+  end component;
+
+  component eb_fifo is
+    generic(
+      g_width : natural;
+      g_size  : natural);
+    port(
+      clk_i     : in  std_logic;
+      rstn_i    : in  std_logic;
+      w_full_o  : out std_logic;
+      w_push_i  : in  std_logic;
+      w_dat_i   : in  std_logic_vector(g_width-1 downto 0);
+      r_empty_o : out std_logic;
+      r_pop_i   : in  std_logic;
+      r_dat_o   : out std_logic_vector(g_width-1 downto 0));
+  end component;
+
+  component eb_commit_fifo is
+    generic(
+      g_width : natural;
+      g_size  : natural);
+    port(
+      clk_i      : in  std_logic;
+      rstn_i     : in  std_logic;
+      w_full_o   : out std_logic;
+      w_push_i   : in  std_logic;
+      w_dat_i    : in  std_logic_vector(g_width-1 downto 0);
+      w_commit_i : in  std_logic;
+      w_abort_i  : in  std_logic;
+      r_empty_o  : out std_logic;
+      r_pop_i    : in  std_logic;
+      r_dat_o    : out std_logic_vector(g_width-1 downto 0));
+  end component;
+  
+  component eb_tx_mux is
+    port(
+      clk_i       : in  std_logic;
+      rstn_i      : in  std_logic;
+      
+      tag_pop_o   : out std_logic;
+      tag_dat_i   : in  t_tag;
+      tag_empty_i : in  std_logic;
+      
+      pass_pop_o   : out std_logic;
+      pass_dat_i   : in  t_wishbone_data;
+      pass_empty_i : in  std_logic;
+      
+      cfg_pop_o    : out std_logic;
+      cfg_dat_i    : in  t_wishbone_data;
+      cfg_empty_i  : in  std_logic;
+      
+      wbm_pop_o    : out std_logic;
+      wbm_dat_i    : in  t_wishbone_data;
+      wbm_empty_i  : in  std_logic;
+      
+      skip_stb_o   : out std_logic;
+      skip_stall_i : in  std_logic;
+      
+      tx_cyc_o     : out std_logic;
+      tx_stb_o     : out std_logic;
+      tx_dat_o     : out t_wishbone_data;
+      tx_stall_i   : in  std_logic);
+  end component;
+
+  component eb_tag_fifo is
+    port(
+      clk_i       : in  std_logic;
+      rstn_i      : in  std_logic;
+      
+      fsm_stb_i   : in  std_logic;
+      fsm_dat_i   : in  t_tag;
+      fsm_full_o  : out std_logic;
+
+      mux_pop_i   : in  std_logic;
+      mux_dat_o   : out t_tag;
+      mux_empty_o : out std_logic);
+  end component;
+
+  component eb_pass_fifo is
+    port(
+      clk_i       : in  std_logic;
+      rstn_i      : in  std_logic;
+      
+      fsm_stb_i   : in  std_logic;
+      fsm_dat_i   : in  t_wishbone_data;
+      fsm_full_o  : out std_logic;
+
+      mux_pop_i   : in  std_logic;
+      mux_dat_o   : out t_wishbone_data;
+      mux_empty_o : out std_logic);
+  end component;
+
+  component eb_cfg_fifo is
+    generic(
+      g_sdb_address : t_wishbone_address);
+    port(
+      clk_i       : in  std_logic;
+      rstn_i      : in  std_logic;
+      
+      errreg_i    : in  std_logic_vector(63 downto 0);
+      
+      cfg_i       : in  t_wishbone_slave_in;
+      cfg_o       : out t_wishbone_slave_out;
+      
+      fsm_stb_i   : in  std_logic;
+      fsm_adr_i   : in  t_wishbone_address;
+      fsm_full_o  : out std_logic;
+
+      mux_pop_i   : in  std_logic;
+      mux_dat_o   : out t_wishbone_data;
+      mux_empty_o : out std_logic;
+      
+      my_mac_o    : out std_logic_vector(47 downto 0);
+      my_ip_o     : out std_logic_vector(31 downto 0);
+      my_port_o   : out std_logic_vector(15 downto 0));
+  end component;
+
+  component eb_wbm_fifo is
+    generic(
+      g_timeout_cycles : natural);
+    port(
+      clk_i       : in  std_logic;
+      rstn_i      : in  std_logic;
+      
+      errreg_o    : out std_logic_vector(63 downto 0);
+      wb_i        : in  t_wishbone_master_in;
+      
+      fsm_stb_i   : in  std_logic;
+      fsm_full_o  : out std_logic;
+      fsm_busy_o  : out std_logic;
+
+      mux_pop_i   : in  std_logic;
+      mux_dat_o   : out t_wishbone_data;
+      mux_empty_o : out std_logic);
+  end component;
+  
+  component eb_stream_narrow is
+    generic(
+      g_slave_width  : natural;
+      g_master_width : natural);
+    port(
+      clk_i    : in  std_logic;
+      rst_n_i  : in  std_logic;
+      slave_i  : in  t_wishbone_slave_in;
+      slave_o  : out t_wishbone_slave_out;
+      master_i : in  t_wishbone_master_in;
+      master_o : out t_wishbone_master_out);
+  end component;
+
+  component eb_stream_widen is
+    generic(
+      g_slave_width  : natural;
+      g_master_width : natural);
+    port(
+      clk_i    : in  std_logic;
+      rst_n_i  : in  std_logic;
+      slave_i  : in  t_wishbone_slave_in;
+      slave_o  : out t_wishbone_slave_out;
+      master_i : in  t_wishbone_master_in;
+      master_o : out t_wishbone_master_out);
+  end component;
+  
+  component eb_checksum is
+    port(
+      clk_i  : in  std_logic;
+      nRst_i : in  std_logic;
+      en_i   : in  std_logic; 
+      data_i : in  std_logic_vector(15 downto 0);
+      done_o : out std_logic;
+      sum_o  : out std_logic_vector(15 downto 0));
+  end component;
+  
+  component eb_eth_rx is
+    generic(
+      g_mtu : natural);
+    port(
+      clk_i     : in  std_logic;
+      rst_n_i   : in  std_logic;
+      snk_i     : in  t_wrf_sink_in;
+      snk_o     : out t_wrf_sink_out;
+      master_o  : out t_wishbone_master_out;
+      master_i  : in  t_wishbone_master_in;
+      stb_o     : out std_logic;
+      stall_i   : in  std_logic;
+      mac_o     : out std_logic_vector(47 downto 0);
+      ip_o      : out std_logic_vector(31 downto 0);
+      port_o    : out std_logic_vector(15 downto 0);
+      length_o  : out unsigned(15 downto 0));
+  end component;
+  
+  component eb_eth_tx is
+    generic(
+      g_mtu : natural);
+    port(
+      clk_i        : in  std_logic;
+      rst_n_i      : in  std_logic;
+      src_i        : in  t_wrf_source_in;
+      src_o        : out t_wrf_source_out;
+      slave_o      : out t_wishbone_slave_out;
+      slave_i      : in  t_wishbone_slave_in;
+      stb_i        : in  std_logic;
+      stall_o      : out std_logic;
+      mac_i        : in  std_logic_vector(47 downto 0);
+      ip_i         : in  std_logic_vector(31 downto 0);
+      port_i       : in  std_logic_vector(15 downto 0);
+      length_i     : in  unsigned(15 downto 0);
+      skip_stb_i   : in  std_logic;
+      skip_stall_o : out std_logic;
+      my_mac_i     : in  std_logic_vector(47 downto 0);
+      my_ip_i      : in  std_logic_vector(31 downto 0);
+      my_port_i    : in  std_logic_vector(15 downto 0));
+  end component;
+
+----------------------------------------------------------------- 
+-- EB Master Stuff
+----------------------------------------------------------------- 
+ 
+
+ 
+   component eb_master_wb_if is
+    generic(g_adr_bits_hi : natural;
+      g_mtu         : natural);
+    port(
+      clk_i       : in  std_logic;
+      rst_n_i     : in  std_logic;
+      
+      slave_i     : in  t_wishbone_slave_in;
+      slave_o     : out t_wishbone_slave_out;
+      
+      byte_cnt_i  : in std_logic_vector(15 downto 0);
+      error_i     : in std_logic_vector(0 downto 0);
+      
+      
+      clear_o     : out std_logic;
+      flush_o     : out std_logic;
+      
+      my_mac_o    : out std_logic_vector(47 downto 0);
+      my_ip_o     : out std_logic_vector(31 downto 0);
+      my_port_o   : out std_logic_vector(15 downto 0);
+      
+      his_mac_o   : out std_logic_vector(47 downto 0); 
+      his_ip_o    : out std_logic_vector(31 downto 0);
+      his_port_o  : out std_logic_vector(15 downto 0); 
+      length_o    : out unsigned(15 downto 0);
+      max_ops_o   : out unsigned(15 downto 0);
+      adr_hi_o    : out std_logic_vector(g_adr_bits_hi-1 downto 0);
+      eb_opt_o    : out t_rec_hdr;
+      
+      udp_raw_o   : out std_logic;
+      udp_we_o    : out std_logic;
+      udp_valid_i : in  std_logic;   
+      udp_data_o  : out std_logic_vector(31 downto 0));
+   end component;
+  
+  
+   component eb_framer is
+   port(
+    clk_i           : in   std_logic;            -- WB Clock
+    rst_n_i         : in   std_logic;            -- async reset
+
+    slave_i         : in   t_wishbone_slave_in;  -- WB op. -> not WB compliant, but the record format is convenient
+    slave_o         : out  t_wishbone_slave_out;  -- flow control    
+    master_o        : out  t_wishbone_master_out;
+    master_i        : in   t_wishbone_master_in; 
+    
+    byte_cnt_o      : out  std_logic_vector(15 downto 0);
+    ovf_o           : out  std_logic;
+       
+    tx_send_now_i   : in   std_logic;
+    tx_flush_o      : out  std_logic; 
+    max_ops_i       : in   unsigned(15 downto 0);
+    length_i        : in   unsigned(15 downto 0); 
+    cfg_rec_hdr_i   : in   t_rec_hdr -- EB cfg information, eg read from cfg space etc
+   );    
+   end component;
+  
+   component eb_record_gen is
+   port(
+      clk_i           : in  std_logic;            
+      rst_n_i         : in  std_logic;            
+
+      slave_i         : in  t_wishbone_slave_in;  
+      slave_stall_o   : out std_logic;              
+      slave_ack_o     : out std_logic;
+      
+      rec_valid_o     : out std_logic;            
+      rec_hdr_o       : out t_rec_hdr;          
+      rec_adr_rd_o    : out t_wishbone_data; 
+      rec_adr_wr_o    : out t_wishbone_address; 
+      rec_ack_i       : in std_logic;             
+      byte_cnt_o    : out unsigned(15 downto 0); 
+      cfg_rec_hdr_i   : in t_rec_hdr);   
+   end component ;
+  
+  component eb_master_eth_tx is
+  generic(
+    g_mtu : natural);
+  port(
+    clk_i        : in  std_logic;
+    rst_n_i      : in  std_logic;
+    src_i        : in  t_wrf_source_in;
+    src_o        : out t_wrf_source_out;
+    slave_o      : out t_wishbone_slave_out;
+    slave_i      : in  t_wishbone_slave_in;
+    stb_i        : in  std_logic;
+    stall_o      : out std_logic;
+    mac_i        : in  std_logic_vector(47 downto 0);
+    ip_i         : in  std_logic_vector(31 downto 0);
+    port_i       : in  std_logic_vector(15 downto 0);
+    skip_stb_i   : in  std_logic;
+    skip_stall_o : out std_logic;
+    my_mac_i     : in  std_logic_vector(47 downto 0);
+    my_ip_i      : in  std_logic_vector(31 downto 0);
+    my_port_i    : in  std_logic_vector(15 downto 0)
+    );
+   end component;
+   
+   component eb_commit_len_fifo is
+  generic(
+    g_width : natural;
+    g_size  : natural);
+  port(
+    clk_i      : in  std_logic;
+    rstn_i     : in  std_logic;
+    w_cnt_o    : out unsigned(f_ceil_log2(g_size) downto 0);
+    r_cnt_o    : out unsigned(f_ceil_log2(g_size) downto 0);
+    w_full_o   : out std_logic;
+    w_push_i   : in  std_logic;
+    w_dat_i    : in  std_logic_vector(g_width-1 downto 0);
+    w_commit_i : in  std_logic;
+    w_abort_i  : in  std_logic;
+    r_empty_o  : out std_logic;
+    r_pop_i    : in  std_logic;
+    r_dat_o    : out std_logic_vector(g_width-1 downto 0)
+    );
+   end component;
+  
+end package;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd
new file mode 100644
index 000000000..df04798ff
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd
@@ -0,0 +1,61 @@
+------------------------------------------------------------------------------
+-- Title      : Etherbone Pass FIFO
+-- Project    : Etherbone Core
+------------------------------------------------------------------------------
+-- File       : eb_pass_fifo.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2013-04-08
+-- Last update: 2013-04-08
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Records protocol data that should be put into response
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 GSI
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-04-08  1.0      terpstra        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+
+entity eb_pass_fifo is
+  port(
+    clk_i       : in  std_logic;
+    rstn_i      : in  std_logic;
+    
+    fsm_stb_i   : in  std_logic;
+    fsm_dat_i   : in  t_wishbone_data;
+    fsm_full_o  : out std_logic;
+
+    mux_pop_i   : in  std_logic;
+    mux_dat_o   : out t_wishbone_data;
+    mux_empty_o : out std_logic);
+end eb_pass_fifo;
+
+architecture rtl of eb_pass_fifo is
+begin
+
+  fifo : eb_fifo
+    generic map(
+      g_width => c_wishbone_data_width,
+      g_size  => c_queue_depth)
+    port map(
+      clk_i     => clk_i,
+      rstn_i    => rstn_i,
+      w_full_o  => fsm_full_o,
+      w_push_i  => fsm_stb_i,
+      w_dat_i   => fsm_dat_i,
+      r_empty_o => mux_empty_o,
+      r_pop_i   => mux_pop_i,
+      r_dat_o   => mux_dat_o);
+      
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd
new file mode 100644
index 000000000..9eb991a7c
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd
@@ -0,0 +1,353 @@
+library IEEE;
+--! Standard packages
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--! Additional library
+library work;
+--! Additional packages
+use work.eb_internals_pkg.all;
+use work.eb_hdr_pkg.all;
+use work.wishbone_pkg.all;
+
+entity eb_slave_fsm is
+  port(
+    clk_i       : in  std_logic;
+    rstn_i      : in  std_logic;
+    
+    rx_cyc_i    : in  std_logic;
+    rx_stb_i    : in  std_logic;
+    rx_dat_i    : in  t_wishbone_data;
+    rx_stall_o  : out std_logic;
+    
+    tag_stb_o   : out std_logic;
+    tag_dat_o   : out t_tag;
+    tag_full_i  : in  std_logic;
+    
+    pass_stb_o  : out std_logic;
+    pass_dat_o  : out t_wishbone_data;
+    pass_full_i : in  std_logic;
+    
+    cfg_stb_o   : out std_logic;
+    cfg_adr_o   : out t_wishbone_address;
+    cfg_full_i  : in  std_logic;
+    
+    wbm_stb_o   : out std_logic;
+    wbm_full_i  : in  std_logic;
+    wbm_busy_i  : in  std_logic;
+    
+    master_o       : out t_wishbone_master_out;
+    master_stall_i : in  std_logic);
+    
+end entity;
+
+architecture behavioral of eb_slave_fsm is
+
+  type t_state_RX is (S_EB_HDR, S_PROBE_DROP, S_PROBE_ID, S_CYC_HDR, S_WR_ADR, S_WRITE, S_RD_ADR, S_READ, S_DROP);
+  
+  signal r_tag_stb_o    : std_logic;
+  signal r_tag_dat_o    : t_tag;
+  signal r_pass_stb_o   : std_logic;
+  signal r_pass_dat_o   : t_wishbone_data;
+  signal r_cfg_stb_o    : std_logic;
+  signal r_wbm_stb_o    : std_logic;
+  signal r_master_cyc_o : std_logic;
+  signal r_master_stb_o : std_logic;
+  signal r_master_we_o  : std_logic;
+  signal r_master_adr_o : t_wishbone_address;
+  signal r_master_dat_o : t_wishbone_data;
+  signal r_wr_adr       : unsigned(t_wishbone_address'range);
+  signal r_rx_rec_hdr   : t_rec_hdr;
+  signal r_tx_rec_hdr   : t_rec_hdr;
+  signal r_rx_cyc       : std_logic;
+  signal r_state        : t_state_RX;
+  signal s_stall        : std_logic;
+  signal s_wbm_busy     : std_logic;
+  signal s_rx_eb_hdr    : t_eb_hdr;
+  signal s_tx_eb_hdr    : t_eb_hdr;
+  signal s_rx_rec_hdr   : t_rec_hdr;
+  signal s_tx_rec_hdr   : t_rec_hdr;
+  
+  function f_reply_eb(rx_eb_hdr : t_eb_hdr) return t_eb_hdr is
+    variable tx_eb_hdr : t_eb_hdr := c_eb_init;
+  begin
+    tx_eb_hdr.probe_res := rx_eb_hdr.probe;
+    return tx_eb_hdr;
+  end function;
+
+  function f_reply_rec(rx_rec_hdr : t_rec_hdr) return t_rec_hdr is
+    variable tx_rec_hdr : t_rec_hdr := C_rec_init;
+  begin
+    tx_rec_hdr.WCA_CFG  := rx_rec_hdr.BCA_CFG;
+    tx_rec_hdr.RD_FIFO  := '0';
+    tx_rec_hdr.RD_CNT   := (others => '0');
+    tx_rec_hdr.WR_FIFO  := rx_rec_hdr.RD_FIFO;
+    tx_rec_hdr.WR_CNT   := rx_rec_hdr.RD_CNT;
+    tx_rec_hdr.SEL      := rx_rec_hdr.SEL;
+    tx_rec_hdr.DROP_CYC := rx_rec_hdr.DROP_CYC;
+    return tx_rec_hdr;
+  end function;
+
+begin
+              
+  rx_stall_o <= s_stall;
+  tag_stb_o  <= r_tag_stb_o;
+  tag_dat_o  <= r_tag_dat_o;
+  pass_stb_o <= r_pass_stb_o;
+  pass_dat_o <= r_pass_dat_o;
+  cfg_stb_o  <= r_cfg_stb_o;
+  cfg_adr_o  <= r_master_adr_o;
+  wbm_stb_o  <= r_wbm_stb_o;
+  
+  s_wbm_busy   <= wbm_busy_i or r_wbm_stb_o; -- cope with 1 cycle latency
+  master_o.cyc <= r_master_cyc_o or s_wbm_busy;
+  master_o.stb <= r_master_stb_o;
+  master_o.we  <= r_master_we_o;
+  master_o.adr <= r_master_adr_o;
+  master_o.dat <= r_master_dat_o;
+  master_o.sel <= r_rx_rec_hdr.sel(master_o.sel'range);
+  
+  -- Stall the RX path if:
+  --   Any TX FIFO is full
+  --   We are pushing a strobe that is stalled
+  --   We are waiting to lower the cycle line
+  s_stall <= tag_full_i OR pass_full_i OR cfg_full_i OR wbm_full_i OR 
+             (r_master_stb_o and master_stall_i) OR
+             (not r_master_cyc_o and s_wbm_busy);
+  
+  s_rx_eb_hdr <= f_parse_eb(rx_dat_i);
+  s_tx_eb_hdr <= f_reply_eb(s_rx_eb_hdr);
+  
+  s_rx_rec_hdr <= f_parse_rec(rx_dat_i);
+  s_tx_rec_hdr <= f_reply_rec(s_rx_rec_hdr);
+  
+  fsm : process(clk_i, rstn_i) is
+  begin
+    if (rstn_i = '0') then
+      r_tag_stb_o    <= '0';
+      r_tag_dat_o    <= (others => '0');
+      r_pass_stb_o   <= '0';
+      r_pass_dat_o   <= (others => '0');
+      r_cfg_stb_o    <= '0';
+      r_wbm_stb_o    <= '0';
+      r_master_cyc_o <= '0';
+      r_master_stb_o <= '0';
+      r_master_we_o  <= '0';
+      r_master_adr_o <= (others => '0');
+      r_master_dat_o <= (others => '0');
+      r_wr_adr       <= (others => '0');
+      r_rx_rec_hdr   <= c_rec_init;
+      r_tx_rec_hdr   <= c_rec_init;
+      r_rx_cyc       <= '0';
+      r_state        <= S_EB_HDR;
+    elsif rising_edge(clk_i) then
+    
+      -- By default, write nowhere in particular
+      r_tag_stb_o  <= '0';
+      r_pass_stb_o <= '0';
+      r_cfg_stb_o  <= '0';
+      r_wbm_stb_o  <= '0';
+      
+      -- Lower strobe line when it is queued
+      r_master_stb_o <= r_master_stb_o and master_stall_i;
+      
+      -- Register to enable detecting falling edge
+      r_rx_cyc <= rx_cyc_i;
+      
+      if(rx_cyc_i = '0') then
+        -- expect a new negotiation header
+        r_state <= S_EB_HDR; 
+        -- guard against improperly terminated streams
+        r_master_cyc_o <= '0'; 
+        
+        -- On falling edge of RX cycle line, push a tag to drop TX cycle
+        if r_rx_cyc = '1' then
+          r_tag_stb_o <= '1';
+          r_tag_dat_o <= c_tag_drop_tx;
+        end if;
+      elsif(rx_stb_i = '1' and s_stall = '0') then
+        -- Every non-error state must write something
+        
+        case r_state is
+          when s_EB_HDR =>
+            -- supported EB header?
+            if (s_rx_eb_hdr.magic = c_eb_magic and s_rx_eb_hdr.ver = c_eb_ver) then
+              -- Raise TX cycle line if this needs to be sent
+              if s_rx_eb_hdr.no_response = '1' then
+                r_tag_stb_o  <= '1';
+                r_tag_dat_o  <= c_tag_skip_tx;
+              else
+                -- Write the header using pass fifo
+                r_tag_stb_o  <= '1';
+                r_tag_dat_o  <= c_tag_pass_tx;
+                r_pass_stb_o <= '1';
+                r_pass_dat_o <= f_format_eb(s_tx_eb_hdr);
+              end if;
+              
+              if s_rx_eb_hdr.probe = '1' then
+                if s_rx_eb_hdr.addr_size(2) = '1' and
+                   s_rx_eb_hdr.data_size(2) = '1' then
+                  -- Allow follow-up payload for stream channels
+                  r_state <= S_PROBE_ID; 
+                else
+                  -- Does not support 32-bit? drop anything after probe id
+                  r_state <= S_PROBE_DROP;
+                end if;  
+              else -- not a probe
+                if s_rx_eb_hdr.addr_size = x"4" or
+                   s_rx_eb_hdr.data_size = x"4" then
+                  -- Must be the exactly right format if not a probe!
+                  r_state <= S_CYC_HDR;
+                else
+                  -- Do the best we can ... report proper EB header and pad with 0s
+                  r_state <= S_DROP;
+                end if;  
+              end if;
+            else  --bad eb header. drop all til cycle line is lowered again
+              r_tag_stb_o <= '1';
+              r_tag_dat_o <= c_tag_skip_tx;
+              r_state     <= S_DROP;
+            end if;
+          
+          when S_PROBE_DROP =>
+            -- Write the probe-id using pass fifo
+            r_tag_stb_o  <= '1';
+            r_tag_dat_o  <= c_tag_pass_on;
+            r_pass_stb_o <= '1';
+            r_pass_dat_o <= rx_dat_i;
+            
+            r_state <= s_DROP;
+          
+          when S_PROBE_ID =>
+            -- Write the probe-id using pass fifo
+            r_tag_stb_o  <= '1';
+            r_tag_dat_o  <= c_tag_pass_on;
+            r_pass_stb_o <= '1';
+            r_pass_dat_o <= rx_dat_i;
+            
+            r_state <= s_CYC_HDR;
+          
+          when S_CYC_HDR  =>
+            r_tx_rec_hdr  <= s_tx_rec_hdr;
+            r_rx_rec_hdr  <= s_rx_rec_hdr;
+            
+            -- Write padding/header using pass fifo
+            r_tag_stb_o  <= '1';
+            r_tag_dat_o  <= c_tag_pass_on;
+            r_pass_stb_o <= '1';
+            
+            if (s_rx_rec_hdr.WR_CNT /= 0) then
+              --padding logic 1. insert padding instead of the header                                  
+              r_pass_dat_o <= x"00000000";
+              r_state <= S_WR_ADR;  
+            elsif (s_rx_rec_hdr.RD_CNT /= 0) then
+              --no writes, no padding. insert the header
+              r_pass_dat_o <= f_format_rec(s_tx_rec_hdr);
+              r_state <= S_RD_ADR;
+            else
+              --no writes, no padding. insert the header 
+              r_pass_dat_o <= f_format_rec(s_tx_rec_hdr);
+              
+              r_master_cyc_o <= r_master_cyc_o and not s_rx_rec_hdr.DROP_CYC;
+              r_state <= S_CYC_HDR;
+            end if;
+            
+          when S_WR_ADR =>
+            r_wr_adr <= unsigned(rx_dat_i);
+            
+            -- Write padding using pass fifo
+            r_tag_stb_o  <= '1';
+            r_tag_dat_o  <= c_tag_pass_on;
+            r_pass_stb_o <= '1';
+            r_pass_dat_o <= x"00000000";
+            
+            r_state <= S_WRITE;
+          
+          when S_WRITE =>
+            r_master_we_o  <= '1';
+            r_master_adr_o <= std_logic_vector(r_wr_adr);
+            r_master_dat_o <= rx_dat_i;
+            
+            if(r_rx_rec_hdr.WR_FIFO = '0') then
+              r_wr_adr <= r_wr_adr + 4;
+            end if;
+            
+            -- Write padding/header using pass fifo
+            r_tag_stb_o  <= '1';
+            r_pass_stb_o <= '1';
+            
+            -- Writes need their output discarded
+            if r_rx_rec_hdr.WCA_CFG = '1' then
+              r_cfg_stb_o    <= '1';
+              r_tag_dat_o    <= c_tag_cfg_ign;
+            else
+              r_wbm_stb_o    <= '1';
+              r_tag_dat_o    <= c_tag_wbm_ign;
+              r_master_cyc_o <= '1';
+              r_master_stb_o <= '1';
+            end if;
+            
+            if (r_rx_rec_hdr.WR_CNT /= 1) then
+              r_pass_dat_o <= x"00000000";
+            else
+              r_pass_dat_o <= f_format_rec(r_tx_rec_hdr);
+              
+              if (r_rx_rec_hdr.RD_CNT /= 0) then
+                r_state <= S_RD_ADR;
+              else
+                r_master_cyc_o <= r_master_cyc_o and not r_rx_rec_hdr.DROP_CYC;  
+                r_state <= S_CYC_HDR;
+              end if;
+            end if;
+            
+            r_rx_rec_hdr.WR_CNT <= r_rx_rec_hdr.WR_CNT - 1;
+              
+          when S_RD_ADR =>
+            -- Copy address using pass fifo
+            r_tag_stb_o  <= '1';
+            r_tag_dat_o  <= c_tag_pass_on;
+            r_pass_stb_o <= '1';
+            r_pass_dat_o <= rx_dat_i; --pass the rx readback address as base write address to tx
+            
+            r_state <= S_READ;
+            
+          when S_READ =>
+            r_master_we_o  <= '0';
+            r_master_adr_o <= rx_dat_i;
+            
+            -- Get data from either cfg or wbm fifos
+            r_tag_stb_o <= '1';
+            
+            if r_rx_rec_hdr.RCA_CFG = '1' then
+              r_cfg_stb_o <= '1';
+              r_tag_dat_o <= c_tag_cfg_req;
+            else
+              r_wbm_stb_o <= '1';
+              r_tag_dat_o <= c_tag_wbm_req;
+              r_master_cyc_o <= '1';
+              r_master_stb_o <= '1';
+            end if;
+            
+            if(r_rx_rec_hdr.RD_CNT = 1) then
+              r_master_cyc_o <= r_master_cyc_o and not r_rx_rec_hdr.DROP_CYC;  
+              r_state <= S_CYC_HDR;
+            end if;
+            
+            r_rx_rec_hdr.RD_CNT <= r_rx_rec_hdr.RD_CNT - 1;
+            
+          when S_DROP =>
+            -- preserve packet length
+            r_tag_stb_o  <= '1';
+            r_tag_dat_o  <= c_tag_pass_on;
+            r_pass_stb_o <= '1';
+            r_pass_dat_o <= (others => '0');
+
+          when others =>
+            r_state <= S_DROP;
+        
+        end case;
+      end if; --rx_stb_i
+    end if; --clk edge  
+  end process;
+
+end architecture;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd
new file mode 100644
index 000000000..4003d37b5
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd
@@ -0,0 +1,205 @@
+------------------------------------------------------------------------------
+-- Title      : Etherbone Slave
+-- Project    : Etherbone Core
+------------------------------------------------------------------------------
+-- File       : eb_slave.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2013-04-08
+-- Last update: 2013-04-08
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Connect all the components of an Etherbone slave
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 GSI
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-04-08  1.0      terpstra        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+
+entity eb_slave_top is
+  generic(
+    g_sdb_address    : t_wishbone_address;
+    g_timeout_cycles : natural);
+  port(
+    clk_i       : in std_logic;  --! System Clk
+    nRst_i      : in std_logic;  --! active low sync reset
+
+    EB_RX_i     : in  t_wishbone_slave_in;   --! Streaming wishbone(record) sink from RX transport protocol block
+    EB_RX_o     : out t_wishbone_slave_out;  --! Streaming WB sink flow control to RX transport protocol block
+    EB_TX_i     : in  t_wishbone_master_in;  --! Streaming WB src flow control from TX transport protocol block
+    EB_TX_o     : out t_wishbone_master_out; --! Streaming WB src to TX transport protocol block
+    
+    skip_stb_o  : out std_logic; --! Does a packet get discarded?
+    skip_stall_i: in  std_logic;
+
+    WB_config_i : in  t_wishbone_slave_in;    --! WB V4 interface to WB interconnect/device(s)
+    WB_config_o : out t_wishbone_slave_out;   --! WB V4 interface to WB interconnect/device(s)
+    WB_master_i : in  t_wishbone_master_in;   --! WB V4 interface to WB interconnect/device(s)
+    WB_master_o : out t_wishbone_master_out;  --! WB V4 interface to WB interconnect/device(s)
+    
+    my_mac_o    : out std_logic_vector(47 downto 0);
+    my_ip_o     : out std_logic_vector(31 downto 0);
+    my_port_o   : out std_logic_vector(15 downto 0));
+end eb_slave_top;
+
+architecture rtl of eb_slave_top is
+  signal rstn_i : std_logic;
+  
+  signal errreg         : std_logic_vector(63 downto 0);
+  signal rx_stall       : std_logic;
+  
+  signal fsm_tag_stb    : std_logic;
+  signal fsm_tag_dat    : t_tag;
+  signal tag_fsm_full   : std_logic;
+  signal fsm_pass_stb   : std_logic;
+  signal fsm_pass_dat   : t_wishbone_data;
+  signal pass_fsm_full  : std_logic;
+  signal fsm_cfg_stb    : std_logic;
+  signal fsm_cfg_adr    : t_wishbone_address;
+  signal cfg_fsm_full   : std_logic;
+  signal fsm_wbm_stb    : std_logic;
+  signal wbm_fsm_full   : std_logic;
+  signal wbm_fsm_busy   : std_logic;
+  
+  signal mux_tag_pop    : std_logic;
+  signal tag_mux_dat    : t_tag;
+  signal tag_mux_empty  : std_logic;
+  signal mux_pass_pop   : std_logic;
+  signal pass_mux_dat   : t_wishbone_data;
+  signal pass_mux_empty : std_logic;
+  signal mux_cfg_pop    : std_logic;
+  signal cfg_mux_dat    : t_wishbone_data;
+  signal cfg_mux_empty  : std_logic;
+  signal mux_wbm_pop    : std_logic;
+  signal wbm_mux_dat    : t_wishbone_data;
+  signal wbm_mux_empty  : std_logic;
+  
+begin
+
+  rstn_i <= nRst_i;
+  
+  EB_RX_o.ack <= EB_RX_i.cyc and EB_RX_i.stb and not rx_stall;
+  EB_RX_o.err <= '0';
+  EB_RX_o.rty <= '0';
+  EB_RX_o.int <= '0';
+  EB_RX_o.stall <= rx_stall;
+  EB_RX_o.dat <= (others => '0');
+  
+  fsm : eb_slave_fsm 
+    port map(
+      clk_i       => clk_i,
+      rstn_i      => rstn_i,
+      rx_cyc_i    => EB_RX_i.cyc,
+      rx_stb_i    => EB_RX_i.stb,
+      rx_dat_i    => EB_RX_i.dat,
+      rx_stall_o  => rx_stall,
+      tag_stb_o   => fsm_tag_stb,
+      tag_dat_o   => fsm_tag_dat,
+      tag_full_i  => tag_fsm_full,
+      pass_stb_o  => fsm_pass_stb,
+      pass_dat_o  => fsm_pass_dat,
+      pass_full_i => pass_fsm_full,
+      cfg_stb_o   => fsm_cfg_stb,
+      cfg_adr_o   => fsm_cfg_adr,
+      cfg_full_i  => cfg_fsm_full,
+      wbm_stb_o   => fsm_wbm_stb,
+      wbm_full_i  => wbm_fsm_full,
+      wbm_busy_i  => wbm_fsm_busy,
+      master_o    => WB_master_o,
+      master_stall_i => WB_master_i.stall);
+
+  EB_TX_o.we  <= '1';
+  EB_TX_o.sel <= (others => '1');
+  EB_TX_o.adr <= (others => '0');
+  
+  mux : eb_tx_mux
+    port map (
+      clk_i        => clk_i,
+      rstn_i       => rstn_i,
+      tag_pop_o    => mux_tag_pop,
+      tag_dat_i    => tag_mux_dat,
+      tag_empty_i  => tag_mux_empty,
+      pass_pop_o   => mux_pass_pop,
+      pass_dat_i   => pass_mux_dat,
+      pass_empty_i => pass_mux_empty,
+      cfg_pop_o    => mux_cfg_pop,
+      cfg_dat_i    => cfg_mux_dat,
+      cfg_empty_i  => cfg_mux_empty,
+      wbm_pop_o    => mux_wbm_pop,
+      wbm_dat_i    => wbm_mux_dat,
+      wbm_empty_i  => wbm_mux_empty,
+      skip_stb_o   => skip_stb_o,
+      skip_stall_i => skip_stall_i,
+      tx_cyc_o     => EB_TX_o.cyc,
+      tx_stb_o     => EB_TX_o.stb,
+      tx_dat_o     => EB_TX_o.dat,
+      tx_stall_i   => EB_TX_i.stall);
+
+  tag : eb_tag_fifo
+    port map(
+      clk_i       => clk_i,
+      rstn_i      => rstn_i,
+      fsm_stb_i   => fsm_tag_stb,
+      fsm_dat_i   => fsm_tag_dat,
+      fsm_full_o  => tag_fsm_full,
+      mux_pop_i   => mux_tag_pop,
+      mux_dat_o   => tag_mux_dat,
+      mux_empty_o => tag_mux_empty);
+
+  pass : eb_pass_fifo
+    port map(
+      clk_i       => clk_i,
+      rstn_i      => rstn_i,
+      fsm_stb_i   => fsm_pass_stb,
+      fsm_dat_i   => fsm_pass_dat,
+      fsm_full_o  => pass_fsm_full,
+      mux_pop_i   => mux_pass_pop,
+      mux_dat_o   => pass_mux_dat,
+      mux_empty_o => pass_mux_empty);
+
+  cfg : eb_cfg_fifo
+    generic map(
+      g_sdb_address => g_sdb_address)
+    port map(
+      clk_i       => clk_i,
+      rstn_i      => rstn_i,
+      errreg_i    => errreg,
+      cfg_i       => WB_config_i,
+      cfg_o       => WB_config_o,
+      fsm_stb_i   => fsm_cfg_stb,
+      fsm_adr_i   => fsm_cfg_adr,
+      fsm_full_o  => cfg_fsm_full,
+      mux_pop_i   => mux_cfg_pop,
+      mux_dat_o   => cfg_mux_dat,
+      mux_empty_o => cfg_mux_empty,
+      my_mac_o    => my_mac_o,
+      my_ip_o     => my_ip_o,
+      my_port_o   => my_port_o);
+
+  wbm : eb_wbm_fifo
+    generic map(
+      g_timeout_cycles => g_timeout_cycles)
+    port map(
+      clk_i       => clk_i,
+      rstn_i      => rstn_i,
+      errreg_o    => errreg,
+      wb_i        => WB_master_i,
+      fsm_stb_i   => fsm_wbm_stb,
+      fsm_full_o  => wbm_fsm_full,
+      fsm_busy_o  => wbm_fsm_busy,
+      mux_pop_i   => mux_wbm_pop,
+      mux_dat_o   => wbm_mux_dat,
+      mux_empty_o => wbm_mux_empty);
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd
new file mode 100644
index 000000000..268c13ed1
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd
@@ -0,0 +1,150 @@
+--! @file eb_stream_narrow.vhd
+--! @brief Adapts the width of a wishbone data stream.
+--!
+--! Copyright (C) 2013 GSI Helmholtz Centre for Heavy Ion Research GmbH 
+--!
+--! Fairly simple state-machine
+--!
+--! @author Wesley W. Terpstra <w.terpstra@gsi.de>
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+--! Lesser General Public License for more details.
+--!  
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+use work.genram_pkg.all;
+
+-- Completely breaks/ignores: adr, sel, we, ack, err
+entity eb_stream_narrow is
+  generic(
+    g_slave_width  : natural;
+    g_master_width : natural);
+  port(
+    clk_i    : in  std_logic;
+    rst_n_i  : in  std_logic;
+    slave_i  : in  t_wishbone_slave_in;
+    slave_o  : out t_wishbone_slave_out;
+    master_i : in  t_wishbone_master_in;
+    master_o : out t_wishbone_master_out);
+end eb_stream_narrow;
+
+architecture rtl of eb_stream_narrow is
+  
+  subtype t_index is unsigned(f_ceil_log2(g_slave_width/g_master_width)-1 downto 0);
+  constant c_max  : t_index := to_unsigned(g_slave_width/g_master_width-1, t_index'length);
+  constant c_one  : t_index := to_unsigned(1, t_index'length);
+  constant c_zero : t_index := (others => '0');
+
+  signal r_ack       : std_logic;
+  signal r_cyc       : std_logic;
+  signal r_drop      : std_logic; -- need to report any cycle line drops
+  signal r_stb       : std_logic;
+  signal r_last      : std_logic; -- '1' when r_idx = 0
+  signal r_idx       : t_index;
+  signal r_dat       : std_logic_vector(g_master_width-1 downto 0);
+  signal s_stall     : std_logic;
+  signal s_cyc_cases : std_logic_vector(2 downto 0);
+  
+begin
+
+  assert (g_slave_width <= c_wishbone_data_width)
+  report "g_master_width can not exceed wishbone data width"
+  severity error;
+
+  assert (g_slave_width mod g_master_width = 0)
+  report "g_master_width must divide g_slave_width"
+  severity error;
+
+  assert (g_master_width < g_slave_width)
+  report "g_master_width must be < g_slave_width"
+  severity error;
+
+  -- Outputs
+  slave_o.ack   <= r_ack;
+  slave_o.err   <= '0';
+  slave_o.stall <= s_stall;
+  slave_o.dat   <= (others => '0');
+  
+  master_o.cyc <= r_cyc;
+  master_o.stb <= r_stb;
+  master_o.we  <= '1';
+  master_o.adr <= (others => '0');
+  master_o.dat(c_wishbone_data_width-1 downto g_master_width) <= (others => '0');
+  master_o.dat(g_master_width-1 downto 0) <= r_dat;
+  
+  output_sel : for i in t_wishbone_byte_select'range generate
+    master_o.sel(i) <= '1' when (i*8 < g_master_width) else '0';
+  end generate;
+  
+  -- Actual logic
+  s_stall <= not r_last or master_i.stall or r_drop;
+  s_cyc_cases(2) <= r_drop;
+  s_cyc_cases(1) <= r_stb;
+  s_cyc_cases(0) <= slave_i.cyc;
+  
+  main : process(clk_i, rst_n_i) is
+  begin
+    if rst_n_i = '0' then
+      r_ack   <= '0';
+      r_cyc   <= '0';
+      r_drop  <= '0';
+      r_stb   <= '0';
+      r_last  <= '0';
+      r_idx   <= c_max;
+      r_dat   <= (others => '0');
+    elsif rising_edge(clk_i) then
+      r_ack <= slave_i.cyc and slave_i.stb and not s_stall;
+      
+      -- Make sure we always report cycle line changes
+      case s_cyc_cases is
+        when "000"  => r_cyc <= '0'; r_drop <= '0'; -- can end cycle immediately
+        when "001"  => r_cyc <= '1'; r_drop <= '0'; -- start new cycle
+        when "010"  => r_cyc <= '1'; r_drop <= '1'; -- report this!
+        when "011"  => r_cyc <= '1'; r_drop <= '0'; -- operation in progress
+        when "100"  => r_cyc <= '0'; r_drop <= '0'; -- reported!
+        when "101"  => r_cyc <= '0'; r_drop <= '0'; -- reported!
+        when others => r_cyc <= '1'; r_drop <= '1'; -- wait for r_stb to fall
+      end case;
+
+      -- When strobing and stalled the process is blocked
+      if (r_stb and master_i.stall) = '0' then
+        -- Steal data from the stalled request
+        r_dat <= slave_i.dat((to_integer(r_idx)+1)*g_master_width-1 downto to_integer(r_idx)*g_master_width);
+        -- If the slave has no new data for us, stop strobing
+        if r_idx = c_max and (slave_i.cyc and slave_i.stb and not r_drop) = '0' then
+          r_stb <= '0';
+        else
+          r_stb <= '1';
+          if r_idx = c_one then
+            r_last <= '1';
+          else
+            r_last <= '0';
+          end if;
+          if r_idx = c_zero then
+            r_idx <= c_max;
+          else
+            r_idx <= r_idx - 1;
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd
new file mode 100644
index 000000000..049646600
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd
@@ -0,0 +1,145 @@
+--! @file eb_stream_adapt.vhd
+--! @brief Adapts the width of a wishbone data stream.
+--!
+--! Copyright (C) 2013 GSI Helmholtz Centre for Heavy Ion Research GmbH 
+--!
+--! Fairly simple state-machine
+--!
+--! @author Wesley W. Terpstra <w.terpstra@gsi.de>
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+--! Lesser General Public License for more details.
+--!  
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+use work.genram_pkg.all;
+
+-- Completely breaks/ignores: adr, sel, we, ack, err
+entity eb_stream_widen is
+  generic(
+    g_slave_width  : natural;
+    g_master_width : natural);
+  port(
+    clk_i    : in  std_logic;
+    rst_n_i  : in  std_logic;
+    slave_i  : in  t_wishbone_slave_in;
+    slave_o  : out t_wishbone_slave_out;
+    master_i : in  t_wishbone_master_in;
+    master_o : out t_wishbone_master_out);
+end eb_stream_widen;
+
+architecture rtl of eb_stream_widen is
+  
+  subtype t_index is unsigned(f_ceil_log2(g_master_width/g_slave_width)-1 downto 0);
+  constant c_max  : t_index := to_unsigned(g_master_width/g_slave_width-1, t_index'length);
+  constant c_zero : t_index := (others => '0');
+
+  signal r_ack       : std_logic;
+  signal r_cyc       : std_logic;
+  signal r_drop      : std_logic; -- need to report any cycle line drops
+  signal r_stb       : std_logic;
+  signal r_idx       : t_index;
+  signal r_dat       : t_wishbone_data;
+  signal s_stall     : std_logic;
+  signal s_cyc_cases : std_logic_vector(2 downto 0);
+  
+begin
+
+  assert (g_master_width <= c_wishbone_data_width)
+  report "g_master_width can not exceed wishbone data width"
+  severity error;
+
+  assert (g_master_width mod g_slave_width = 0)
+  report "g_slave_width must divide g_master_width"
+  severity error;
+
+  assert (g_master_width > g_slave_width)
+  report "g_slave_width must be < g_master_width"
+  severity error;
+
+  -- Outputs
+  slave_o.ack   <= r_ack;
+  slave_o.err   <= '0';
+  slave_o.stall <= s_stall;
+  slave_o.dat   <= (others => '0');
+  
+  master_o.cyc <= r_cyc;
+  master_o.stb <= r_stb;
+  master_o.we  <= '1';
+  master_o.adr <= (others => '0');
+  master_o.dat <= r_dat;
+  
+  output_sel : for i in t_wishbone_byte_select'range generate
+    master_o.sel(i) <= '1' when (i*8 < g_master_width) else '0';
+  end generate;
+
+  -- Actual logic
+  s_stall <= (r_stb and master_i.stall) or r_drop;
+  s_cyc_cases(2) <= r_drop;
+  s_cyc_cases(1) <= r_stb;
+  s_cyc_cases(0) <= slave_i.cyc;
+  
+  main : process(clk_i, rst_n_i) is
+  begin
+    if rst_n_i = '0' then
+      r_ack  <= '0';
+      r_cyc  <= '0';
+      r_drop <= '0';
+      r_stb  <= '0';
+      r_idx  <= c_max;
+      r_dat  <= (others => '0');
+    elsif rising_edge(clk_i) then
+      r_ack <= slave_i.cyc and slave_i.stb and not s_stall;
+      
+      -- Make sure we always report cycle line changes
+      case s_cyc_cases is
+        when "000"  => r_cyc <= '0'; r_drop <= '0'; -- can end cycle immediately
+        when "001"  => r_cyc <= '1'; r_drop <= '0'; -- start new cycle
+        when "010"  => r_cyc <= '1'; r_drop <= '1'; -- report this!
+        when "011"  => r_cyc <= '1'; r_drop <= '0'; -- operation in progress
+        when "100"  => r_cyc <= '0'; r_drop <= '0'; -- reported!
+        when "101"  => r_cyc <= '0'; r_drop <= '0'; -- reported!
+        when others => r_cyc <= '1'; r_drop <= '1'; -- wait for r_stb to fall
+      end case;
+      
+      -- Transfer done?
+      if (r_stb and not master_i.stall) = '1' then
+        r_stb <= '0';
+      end if;
+      
+      -- Did the slave push us data?
+      if slave_i.cyc = '0' then
+        r_idx <= c_max; -- reset counter to restore alignment
+        -- leave r_stb/r_dat unchanged!
+      elsif (slave_i.stb and not s_stall) = '1' then
+        r_dat(((to_integer(r_idx)+1)*g_slave_width)-1 downto to_integer(r_idx)*g_slave_width) <= 
+          slave_i.dat(g_slave_width-1 downto 0);
+        if r_idx = c_zero then
+          r_idx <= c_max;
+          r_stb <= '1';
+        else
+          r_idx <= r_idx - 1;
+        end if;
+      end if;
+      
+    end if;
+  end process;
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd
new file mode 100644
index 000000000..015e32bb0
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd
@@ -0,0 +1,61 @@
+------------------------------------------------------------------------------
+-- Title      : Etherbone Tag FIFO
+-- Project    : Etherbone Core
+------------------------------------------------------------------------------
+-- File       : eb_tag_fifo.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2013-04-08
+-- Last update: 2013-04-08
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Tracks which channel the MUX should pop next
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 GSI
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-04-08  1.0      terpstra        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+
+entity eb_tag_fifo is
+  port(
+    clk_i       : in  std_logic;
+    rstn_i      : in  std_logic;
+    
+    fsm_stb_i   : in  std_logic;
+    fsm_dat_i   : in  t_tag;
+    fsm_full_o  : out std_logic;
+
+    mux_pop_i   : in  std_logic;
+    mux_dat_o   : out t_tag;
+    mux_empty_o : out std_logic);
+end eb_tag_fifo;
+
+architecture rtl of eb_tag_fifo is
+begin
+
+  fifo : eb_fifo
+    generic map(
+      g_width => t_tag'length,
+      g_size  => c_queue_depth)
+    port map(
+      clk_i     => clk_i,
+      rstn_i    => rstn_i,
+      w_full_o  => fsm_full_o,
+      w_push_i  => fsm_stb_i,
+      w_dat_i   => fsm_dat_i,
+      r_empty_o => mux_empty_o,
+      r_pop_i   => mux_pop_i,
+      r_dat_o   => mux_dat_o);
+      
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd
new file mode 100644
index 000000000..2c2c4c345
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd
@@ -0,0 +1,170 @@
+------------------------------------------------------------------------------
+-- Title      : Etherbone TX MUX
+-- Project    : Etherbone Core
+------------------------------------------------------------------------------
+-- File       : eb_tux_mux.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2013-04-08
+-- Last update: 2013-04-08
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Combines output streams into a packet
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 GSI
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-04-08  1.0      terpstra        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+
+entity eb_tx_mux is
+  port(
+    clk_i       : in  std_logic;
+    rstn_i      : in  std_logic;
+    
+    tag_pop_o   : out std_logic;
+    tag_dat_i   : in  t_tag;
+    tag_empty_i : in  std_logic;
+    
+    pass_pop_o   : out std_logic;
+    pass_dat_i   : in  t_wishbone_data;
+    pass_empty_i : in  std_logic;
+    
+    cfg_pop_o    : out std_logic;
+    cfg_dat_i    : in  t_wishbone_data;
+    cfg_empty_i  : in  std_logic;
+    
+    wbm_pop_o    : out std_logic;
+    wbm_dat_i    : in  t_wishbone_data;
+    wbm_empty_i  : in  std_logic;
+    
+    skip_stb_o   : out std_logic;
+    skip_stall_i : in  std_logic;
+    
+    tx_cyc_o     : out std_logic;
+    tx_stb_o     : out std_logic;
+    tx_dat_o     : out t_wishbone_data;
+    tx_stall_i   : in  std_logic);
+end eb_tx_mux;
+
+architecture rtl of eb_tx_mux is
+
+  signal r_skip      : std_logic;
+  signal r_tx_cyc    : std_logic;
+  signal r_tx_stb    : std_logic;
+  signal s_can_tx    : std_logic;
+  signal s_dat_mux   : t_wishbone_data;
+  signal s_tag_mux   : std_logic;
+  signal s_pass_mux  : std_logic;
+  signal s_cfg_mux   : std_logic;
+  signal s_wbm_mux   : std_logic;
+  signal s_tag_pop   : std_logic;
+  signal r_tag_valid : std_logic;
+  signal r_tag_value : t_tag;
+  
+begin
+
+  -- We can write whenever TX is unstalled and/or not full
+  s_can_tx <= not ((r_tx_cyc and r_tx_stb and tx_stall_i) or (r_skip and skip_stall_i));
+  
+  skip_stb_o <= r_skip;
+  tx_cyc_o   <= r_tx_cyc;
+  tx_stb_o   <= r_tx_stb;
+  
+  tx_out : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_skip   <= '0';
+      r_tx_cyc <= '0';
+      r_tx_stb <= '0';
+      tx_dat_o <= (others => '0');
+    elsif rising_edge(clk_i) then
+      if s_can_tx = '1' then -- is prior operation complete?
+        r_tx_stb <= not s_tag_mux and r_tag_valid;
+        r_skip <= '0';
+        tx_dat_o <= s_dat_mux;
+        -- Control the TX cycle line
+        if r_tag_valid = '1' then
+          case r_tag_value is
+            when c_tag_drop_tx => r_tx_cyc <= '0';
+            when c_tag_pass_tx => r_tx_cyc <= '1';
+            when c_tag_skip_tx => r_skip   <= '1';
+            when others        => null;
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  with r_tag_value select
+  s_dat_mux <= 
+    pass_dat_i      when c_tag_pass_tx,
+    pass_dat_i      when c_tag_pass_on,
+    cfg_dat_i       when c_tag_cfg_req,
+    pass_dat_i      when c_tag_cfg_ign,
+    wbm_dat_i       when c_tag_wbm_req,
+    pass_dat_i      when c_tag_wbm_ign,
+    (others => '-') when others; -- c_tag_skip_tx, c_tag_drop_tx
+  
+  with r_tag_value select
+  s_tag_mux <=
+    pass_empty_i                  when c_tag_pass_tx,
+    pass_empty_i                  when c_tag_pass_on,
+    cfg_empty_i                   when c_tag_cfg_req,
+    (pass_empty_i or cfg_empty_i) when c_tag_cfg_ign,
+    wbm_empty_i                   when c_tag_wbm_req,
+    (pass_empty_i or wbm_empty_i) when c_tag_wbm_ign,
+    '0'                           when others; -- c_tag_skip_tx, c_tag_drop_tx
+  
+  with r_tag_value select
+  s_pass_mux <=
+    pass_empty_i                  when c_tag_pass_tx,
+    pass_empty_i                  when c_tag_pass_on,
+    (pass_empty_i or cfg_empty_i) when c_tag_cfg_ign,
+    (pass_empty_i or wbm_empty_i) when c_tag_wbm_ign,
+    '1'                           when others; -- c_tag_skip_tx, c_tag_drop_tx, c_tag_cfg_req, c_tag_wbm_req
+  
+  with r_tag_value select
+  s_cfg_mux <=
+    cfg_empty_i                   when c_tag_cfg_req,
+    (pass_empty_i or cfg_empty_i) when c_tag_cfg_ign,
+    '1'                           when others;
+  
+  with r_tag_value select
+  s_wbm_mux <=
+    wbm_empty_i                   when c_tag_wbm_req,
+    (pass_empty_i or wbm_empty_i) when c_tag_wbm_ign,
+    '1'                           when others;
+  
+  -- Pop the queue we fed into TX
+  pass_pop_o <= s_can_tx and r_tag_valid and not s_pass_mux;
+  cfg_pop_o  <= s_can_tx and r_tag_valid and not s_cfg_mux;
+  wbm_pop_o  <= s_can_tx and r_tag_valid and not s_wbm_mux;
+  s_tag_pop  <= s_can_tx and r_tag_valid and not s_tag_mux;
+  
+  -- Pop the tag FIFO if the register is empty/emptied
+  tag_pop_o <= not tag_empty_i and (s_tag_pop or not r_tag_valid);
+  tag_in : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_tag_valid <= '0';
+      r_tag_value <= c_tag_drop_tx;
+    elsif rising_edge(clk_i) then
+      if s_tag_pop = '1' or r_tag_valid = '0' then
+        r_tag_valid <= not tag_empty_i;
+        r_tag_value <= tag_dat_i;
+      end if;
+    end if;
+  end process;
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd
new file mode 100644
index 000000000..245863e42
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd
@@ -0,0 +1,171 @@
+------------------------------------------------------------------------------
+-- Title      : Etherbone Wishbone Master FIFO
+-- Project    : Etherbone Core
+------------------------------------------------------------------------------
+-- File       : eb_wbm_fifo.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2013-04-08
+-- Last update: 2013-04-08
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Buffers Wishbone requests to resulting data
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 GSI
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-04-08  1.0      terpstra        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.eb_internals_pkg.all;
+
+entity eb_wbm_fifo is
+  generic(
+    g_timeout_cycles : natural);
+  port(
+    clk_i       : in  std_logic;
+    rstn_i      : in  std_logic;
+    
+    errreg_o    : out std_logic_vector(63 downto 0);
+    wb_i        : in  t_wishbone_master_in;
+    
+    fsm_stb_i   : in  std_logic;
+    fsm_busy_o  : out std_logic;
+    fsm_full_o  : out std_logic;
+
+    mux_pop_i   : in  std_logic;
+    mux_dat_o   : out t_wishbone_data;
+    mux_empty_o : out std_logic);
+end eb_wbm_fifo;
+
+architecture rtl of eb_wbm_fifo is
+  
+  constant c_size  : natural := c_queue_depth;
+  constant c_sbits : natural := f_ceil_log2(c_size);
+  constant c_tbits : natural := f_ceil_log2(g_timeout_cycles);
+  
+  signal s_wb_i_rdy    : std_logic;                     -- 1 when a strobe ackd
+  signal r_inflight    : unsigned(c_sbits-1 downto 0);  -- # unacked strobes
+  signal r_busy        : std_logic;                     -- 1 when r_inflight > 0
+  signal r_queued      : unsigned(c_sbits-1 downto 0);  -- # unpoped strobes (>= r_inflight)
+  signal r_full        : std_logic;                     -- 1 when r_queued > 0
+  signal r_timeout     : unsigned(c_tbits-1 downto 0);  -- counts downto 0 between acks
+  signal r_kill_ack    : std_logic;                     -- 1 when r_timeout expires
+  signal r_errreg      : std_logic_vector(63 downto 0); -- shifts in ack when data pops
+  signal s_ack         : std_logic;                     -- ack of ready data
+  
+begin
+
+  s_wb_i_rdy <= wb_i.ack or wb_i.err or wb_i.rty or r_kill_ack;
+  
+  fsm_busy_o <= r_busy;
+  busy : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_busy <= '0';
+      r_inflight <= (others => '0');
+    elsif rising_edge(clk_i) then
+      if fsm_stb_i = '1' then
+        if s_wb_i_rdy = '1' then         -- push+pop
+          r_inflight <= r_inflight;
+        else                             -- push
+          r_busy <= '1';
+          r_inflight <= r_inflight + 1;
+        end if;
+      else
+        if s_wb_i_rdy = '1' then         -- pop
+          if r_inflight = 1 then
+            r_busy <= '0';
+          end if;
+          r_inflight <= r_inflight - 1;
+        else                             -- noop
+          r_inflight <= r_inflight;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  fsm_full_o <= r_full;
+  full : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_full <= '0';
+      r_queued <= (others => '0');
+    elsif rising_edge(clk_i) then
+      if fsm_stb_i = '1' then
+        if mux_pop_i = '1' then          -- push+pop
+          r_queued <= r_queued;
+        else                             -- push
+          if r_queued = c_size-1 then
+            r_full <= '1';
+          end if;
+          r_queued <= r_queued + 1;
+        end if;
+      else
+        if mux_pop_i = '1' then          -- pop
+          r_full <= '0';
+          r_queued <= r_queued - 1;
+        else                             -- noop
+          r_queued <= r_queued;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  kill_ack : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_kill_ack <= '0';
+      r_timeout  <= to_unsigned(g_timeout_cycles, r_timeout'length);
+    elsif rising_edge(clk_i) then
+      if s_wb_i_rdy = '1' or r_busy = '0' then -- ackd?
+        r_kill_ack <= '0';
+        r_timeout  <= to_unsigned(g_timeout_cycles, r_timeout'length);
+      else
+        if r_timeout = 1 then
+          r_kill_ack <= '1'; -- causes s_wb_i_rdy next cycle
+        end if;
+        r_timeout <= r_timeout - 1;
+      end if;
+    end if;
+  end process;
+  
+  datfifo : eb_fifo
+    generic map(
+      g_width => c_wishbone_data_width+1,
+      g_size  => c_size)
+    port map(
+      clk_i                           => clk_i,
+      rstn_i                          => rstn_i,
+      w_full_o                        => open,
+      w_push_i                        => s_wb_i_rdy,
+      w_dat_i(t_wishbone_data'range)  => wb_i.dat,
+      w_dat_i(t_wishbone_data'length) => wb_i.ack,
+      r_empty_o                       => mux_empty_o,
+      r_pop_i                         => mux_pop_i,
+      r_dat_o(t_wishbone_data'range)  => mux_dat_o,
+      r_dat_o(t_wishbone_data'length) => s_ack);
+  
+  -- Shift the error register during data pop
+  -- This ensures that it reflects state synchronous to the TX path
+  errreg_o <= r_errreg;
+  errreg : process(rstn_i, clk_i) is
+  begin
+    if rstn_i = '0' then
+      r_errreg <= (others => '0');
+    elsif rising_edge(clk_i) then
+      if mux_pop_i = '1' then
+        r_errreg <= r_errreg(r_errreg'left-1 downto 0) & (not s_ack);
+      end if;
+    end if;
+  end process;
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd
new file mode 100644
index 000000000..394b1e878
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd
@@ -0,0 +1,168 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+
+package etherbone_pkg is
+  constant c_etherbone_sdb : t_sdb_device := (
+    abi_class     => x"0000", -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"4", --32-bit port granularity
+    sdb_component => (
+    addr_first    => x"0000000000000000",
+    addr_last     => x"00000000000000ff",
+    product => (
+    vendor_id     => x"0000000000000651", -- GSI
+    device_id     => x"68202b22",
+    version       => x"00000001",
+    date          => x"20130211",
+    name          => "Etherbone-Config   ")));
+  
+  constant c_ebm_sdb : t_sdb_device := (
+    abi_class     => x"0000", -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7", -- 8/16/32-bit port granularity
+    sdb_component => (
+    addr_first    => x"0000000000000000",
+    addr_last     => x"0000000000ffffff",
+    product => (
+    vendor_id     => x"0000000000000651", -- GSI
+    device_id     => x"00000815",
+    version       => x"00000002",
+    date          => x"20140615",
+    name          => "Etherbone_Master   ")));
+  
+  function f_hi_adr_bits(ebm : t_sdb_device) return natural;
+  
+  
+  component eb_raw_slave is
+    generic(
+      g_sdb_address    : std_logic_vector(63 downto 0);
+      g_timeout_cycles : natural := 6250000; -- 100 ms at 62.5MHz
+      g_bus_width      : natural);
+    port(
+      clk_i       : in  std_logic;
+      nRst_i      : in  std_logic;
+      snk_i       : in  t_wishbone_slave_in;
+      snk_o       : out t_wishbone_slave_out;
+      src_o       : out t_wishbone_master_out;
+      src_i       : in  t_wishbone_master_in;
+      cfg_slave_o : out t_wishbone_slave_out;
+      cfg_slave_i : in  t_wishbone_slave_in;
+      master_o    : out t_wishbone_master_out;
+      master_i    : in  t_wishbone_master_in);
+  end component;
+
+  component eb_master_slave_wrapper is
+  generic(
+    g_with_master         : boolean := false;
+    
+    g_ebs_sdb_address     : std_logic_vector(63 downto 0);
+    g_ebs_timeout_cycles  : natural := 6250000;
+    g_ebs_mtu             : natural := 1500;
+    
+    g_ebm_adr_bits_hi     : natural := f_hi_adr_bits(c_ebm_sdb)
+    
+    );
+  port(
+    clk_i           : in  std_logic;
+    nRst_i          : in  std_logic;
+    
+    --to wr core, ext wrf if 
+    snk_i           : in  t_wrf_sink_in;
+    snk_o           : out t_wrf_sink_out;
+    src_o           : out t_wrf_source_out;
+    src_i           : in  t_wrf_source_in;
+  
+    --ebs
+    ebs_cfg_slave_o : out t_wishbone_slave_out;
+    ebs_cfg_slave_i : in  t_wishbone_slave_in;
+    ebs_wb_master_o : out t_wishbone_master_out;
+    ebs_wb_master_i : in  t_wishbone_master_in;
+    
+    --ebm (optional)
+    ebm_wb_slave_i  : in  t_wishbone_slave_in;
+    ebm_wb_slave_o  : out t_wishbone_slave_out 
+     
+  );
+  end component;
+  
+  component eb_ethernet_slave is
+    generic(
+      g_sdb_address    : std_logic_vector(63 downto 0);
+      g_timeout_cycles : natural := 6250000; -- 100 ms at 62.5MHz
+      g_mtu            : natural := 1500);
+    port(
+      clk_i       : in  std_logic;
+      nRst_i      : in  std_logic;
+      snk_i       : in  t_wrf_sink_in;
+      snk_o       : out t_wrf_sink_out;
+      src_o       : out t_wrf_source_out;
+      src_i       : in  t_wrf_source_in;
+      cfg_slave_o : out t_wishbone_slave_out;
+      cfg_slave_i : in  t_wishbone_slave_in;
+      master_o    : out t_wishbone_master_out;
+      master_i    : in  t_wishbone_master_in);
+  end component;
+
+  -- Backwards compatability component; use eb_ethernet_slave
+  component eb_slave_core is
+    generic(
+      g_sdb_address    : std_logic_vector(63 downto 0);
+      g_timeout_cycles : natural := 6250000; -- 100 ms at 62.5MHz
+      g_mtu            : natural := 1500);
+    port(
+      clk_i       : in  std_logic;
+      nRst_i      : in  std_logic;
+      snk_i       : in  t_wrf_sink_in;
+      snk_o       : out t_wrf_sink_out;
+      src_o       : out t_wrf_source_out;
+      src_i       : in  t_wrf_source_in;
+      cfg_slave_o : out t_wishbone_slave_out;
+      cfg_slave_i : in  t_wishbone_slave_in;
+      master_o    : out t_wishbone_master_out;
+      master_i    : in  t_wishbone_master_in);
+  end component;
+  
+  component eb_master_top is
+generic(g_adr_bits_hi : natural := 8;
+        g_mtu : natural := 32);
+port(
+  clk_i         : in  std_logic;
+  rst_n_i       : in  std_logic;
+
+  slave_i       : in  t_wishbone_slave_in;
+  slave_o       : out t_wishbone_slave_out;
+  
+  framer_in   : out t_wishbone_slave_in;
+  framer_out  : out t_wishbone_slave_out;
+  
+  src_i         : in  t_wrf_source_in;
+  src_o         : out t_wrf_source_out
+);
+end component;
+
+
+
+end etherbone_pkg;
+
+package body etherbone_pkg is
+
+   -- gets correct number of high address bits from ebm sdb
+   function f_hi_adr_bits(ebm : t_sdb_device) return natural is
+      variable ret : natural := 2;
+      variable len : natural;
+   begin
+     len := f_hot_to_bin(ebm.sdb_component.addr_last);
+     ret := c_wishbone_address_width - (len - 2);
+     return ret;
+   end f_hi_adr_bits;
+
+end etherbone_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_crc_gen.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_crc_gen.vhd
new file mode 100644
index 000000000..e7d6b6665
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_crc_gen.vhd
@@ -0,0 +1,280 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- Ultimate CRC.                                                ----
+----                                                              ----
+---- This file is part of the ultimate CRC projectt               ----
+---- http://www.opencores.org/cores/ultimate_crc/                 ----
+----                                                              ----
+---- Description                                                  ----
+---- CRC generator/checker, parallel implementation.              ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Geir Drange, gedra@opencores.org                           ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2005 Authors and OPENCORES.ORG                 ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU General          ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.0 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU General Public License for more details.----
+----                                                              ----
+---- You should have received a copy of the GNU General           ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/gpl.txt                     ----
+----                                                              ----
+----------------------------------------------------------------------
+--
+-- CVS Revision History
+--
+-- $Log: ucrc_par.vhd,v $
+-- Revision 1.1  2005/05/09 15:58:38  gedra
+-- Parallel implementation
+--
+-- Modified by T.W. for use in GenCores library
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.gencores_pkg.all;
+
+entity gc_crc_gen is
+  generic (
+-- polynomial of our CRC generator
+    g_polynomial              : std_logic_vector       := x"04C11DB7";
+-- initial (after-reset) value of CRC
+    g_init_value              : std_logic_vector       := x"ffffffff";
+-- residual value of CRC when matched
+    g_residue                 : std_logic_vector       := x"38fb2284";
+-- width of full data input word 
+    g_data_width              : integer range 2 to 256 := 16;
+-- width of smaller-than-full data input word
+    g_half_width              : integer range 2 to 256 := 8;
+-- use synchronous reset when 1
+    g_sync_reset              : integer range 0 to 1   := 0;
+-- dual-width mode (g_data_width - wide input word when 1 and g_half_width input
+-- word when 0)
+    g_dual_width              : integer range 0 to 1   := 0;
+-- if true, match_o output is registered, otherwise it's driven combinatorially
+    g_registered_match_output : boolean                := true;
+    g_registered_crc_output   : boolean                := true); 
+  port (
+    clk_i  : in std_logic;              -- clock
+    rst_i  : in std_logic;              -- reset, active high
+    en_i   : in std_logic;              -- enable input, active high
+    half_i : in std_logic;              -- 1: input word has g_half_width bits
+                                        -- 0: input word has g_data_width bits
+
+    data_i    : in std_logic_vector(g_data_width - 1 downto 0);  -- data input
+    restart_i : in std_logic := '0';
+
+    match_o : out std_logic;            -- CRC match flag: 1 - CRC matches
+
+    crc_o : out std_logic_vector(g_polynomial'length - 1 downto 0));  -- CRC
+                                                                      -- output value
+end gc_crc_gen;
+
+architecture rtl of gc_crc_gen is
+
+  function f_reverse_vector (a : in std_logic_vector)
+    return std_logic_vector is
+    variable v_result : std_logic_vector(a'reverse_range);
+  begin
+    for i in a'range loop
+      v_result(i) := a(i);
+    end loop;
+    return v_result;
+  end;
+
+  function f_reverse_bytes (a : in std_logic_vector)
+    return std_logic_vector is
+    variable tmp      : std_logic_vector(a'length-1 downto 0);
+    variable v_result : std_logic_vector(a'length-1 downto 0);
+  begin
+    tmp := a;
+    for i in tmp'range loop
+      v_result(i) := tmp(((tmp'length/8-1) - i/8)*8 + (i mod 8));
+    end loop;
+    return v_result;
+  end;
+
+
+  constant msb        : integer                        := g_polynomial'length - 1;
+  constant init_msb   : integer                        := g_init_value'length - 1;
+  constant p          : std_logic_vector(msb downto 0) := g_polynomial;
+  constant dw         : integer                        := g_data_width;
+  constant pw         : integer                        := g_polynomial'length;
+  type     fb_array is array (dw downto 1) of std_logic_vector(msb downto 0);
+  type     dmsb_array is array (dw downto 1) of std_logic_vector(msb downto 1);
+  signal   crca       : fb_array;
+  signal   da, ma     : dmsb_array;
+  signal   crc        : std_logic_vector(msb downto 0);
+  signal   arst, srst : std_logic;
+
+
+  signal data_i2           : std_logic_vector(g_data_width-1 downto 0);
+  signal en_d0             : std_logic;
+  signal crc_cur, crc_next : std_logic_vector(g_polynomial'length-1 downto 0);
+
+  
+begin
+
+-- Parameter checking: Invalid generics will abort simulation/synthesis
+  PCHK1 : if msb /= init_msb generate
+    process
+    begin
+      report "g_polynomial and g_init_value vectors must be equal length!"
+        severity failure;
+      wait;
+    end process;
+  end generate PCHK1;
+
+  PCHK2 : if (msb < 3) or (msb > 31) generate
+    process
+    begin
+      report "g_polynomial must be of order 4 to 32!"
+        severity failure;
+      wait;
+    end process;
+  end generate PCHK2;
+
+  PCHK3 : if p(0) /= '1' generate       -- LSB must be 1
+    process
+    begin
+      report "g_polynomial must have lsb set to 1!"
+        severity failure;
+      wait;
+    end process;
+  end generate PCHK3;
+
+  data_i2 <= f_reverse_bytes(data_i);
+
+  crc_cur <= g_init_value when restart_i = '1' else crc;
+
+-- Generate vector of each data bit
+  CA : for i in 1 to dw generate        -- data bits
+    DAT : for j in 1 to msb generate
+      da(i)(j) <= data_i2(i - 1);
+    end generate DAT;
+  end generate CA;
+
+-- Generate vector of each CRC MSB
+  MS0 : for i in 1 to msb generate
+    ma(1)(i) <= crc_cur(msb);
+  end generate MS0;
+  MSP : for i in 2 to dw generate
+    MSU : for j in 1 to msb generate
+      ma(i)(j) <= crca(i - 1)(msb);
+    end generate MSU;
+  end generate MSP;
+
+-- Generate feedback matrix
+  crca(1)(0)            <= da(1)(1) xor crc_cur(msb);
+  crca(1)(msb downto 1) <= crc_cur(msb - 1 downto 0) xor ((da(1) xor ma(1)) and p(msb downto 1));
+  FB : for i in 2 to dw generate
+    crca(i)(0)            <= da(i)(1) xor crca(i - 1)(msb);
+    crca(i)(msb downto 1) <= crca(i - 1)(msb - 1 downto 0) xor
+                             ((da(i) xor ma(i)) and p(msb downto 1));
+  end generate FB;
+
+-- Reset signal
+  SR : if g_sync_reset = 1 generate
+    srst <= rst_i;
+    arst <= '0';
+  end generate SR;
+  AR : if g_sync_reset = 0 generate
+    srst <= '0';
+    arst <= rst_i;
+  end generate AR;
+
+
+  CRCP : process (clk_i, arst)
+  begin
+    if arst = '1' then                  -- async. reset
+      crc     <= g_init_value;
+    elsif rising_edge(clk_i) then
+      if srst = '1' then                -- sync. reset
+        crc <= g_init_value;
+      elsif en_i = '1' then
+        
+        if(half_i = '1' and g_dual_width = 1) then
+          crc <= crca(g_half_width);
+        else
+          crc <= crca(g_data_width);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_crc_next : process(crc, half_i, crca)
+  begin
+    if(g_registered_crc_output) then
+      crc_next <= f_reverse_bytes(f_reverse_vector(not crc));
+    else
+      if(half_i = '1' and g_dual_width = 1) then
+        crc_next <= f_reverse_bytes(f_reverse_vector(not crca(g_half_width)));
+      else
+        crc_next <= f_reverse_bytes(f_reverse_vector(not crca(g_data_width)));
+      end if;
+    end if;
+  end process;
+
+  p_crc_output : process(crc_next, crc, en_i)
+  begin
+    if(g_registered_crc_output) then
+      crc_o <= crc_next;
+    elsif(en_i = '1') then
+      crc_o <= crc_next;
+    else
+      crc_o <= f_reverse_bytes(f_reverse_vector(not crc));
+    end if;
+  end process;
+
+  gen_reg_match_output : if(g_registered_match_output) generate
+    
+    match_gen : process (clk_i, arst)
+    begin
+      if arst = '1' then                -- async. reset
+        match_o <= '0';
+        en_d0   <= '0';
+      elsif rising_edge(clk_i) then
+        if srst = '1' then              -- sync. reset
+          match_o <= '0';
+          en_d0   <= '0';
+        else
+          en_d0 <= en_i;
+
+          if(en_d0 = '1') then
+            if crc_next = g_residue then
+              match_o <= '1';
+            else
+              match_o <= '0';
+            end if;
+          end if;
+        end if;
+      end if;
+    end process;
+    
+  end generate gen_reg_match_output;
+
+  gen_comb_match_output : if (not g_registered_match_output) generate
+    match_o <= '1' when crc_next = g_residue else '0';
+  end generate gen_comb_match_output;
+end rtl;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
new file mode 100644
index 000000000..939d516a4
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
@@ -0,0 +1,93 @@
+-------------------------------------------------------------------------------
+-- Title      : Pulse width extender
+-- Project    : General Cores library
+-------------------------------------------------------------------------------
+-- File       : gc_extend_pulse.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Created    : 2009-09-01
+-- Last update: 2012-06-19
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description:
+-- Synchronous pulse extender. Generates a pulse of programmable width upon
+-- detection of a rising edge in the input.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2011 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2009-09-01  0.9      twlostow        Created
+-- 2011-04-18  1.0      twlostow        Added comments & header
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.NUMERIC_STD.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+
+entity gc_extend_pulse is
+  
+  generic (
+    -- output pulse width in clk_i cycles
+    g_width : natural := 1000
+    );
+  port (
+    clk_i      : in  std_logic;
+    rst_n_i    : in  std_logic;
+    -- input pulse (synchronou to clk_i)
+    pulse_i    : in  std_logic;
+    -- extended output pulse
+    extended_o : out std_logic := '0');
+end gc_extend_pulse;
+
+architecture rtl of gc_extend_pulse is
+
+  signal cntr : unsigned(f_log2_size(g_width)-1 downto 0);
+  signal extended_int : std_logic;
+  
+begin  -- rtl
+
+  extend : process (clk_i, rst_n_i)
+  begin  -- process extend
+    if rst_n_i = '0' then                   -- asynchronous reset (active low)
+      extended_int <= '0';
+      cntr       <= (others => '0');
+    elsif clk_i'event and clk_i = '1' then  -- rising clock edge
+      if(pulse_i = '1') then
+        extended_int <= '1';
+        cntr       <= to_unsigned(g_width - 2, cntr'length);
+      elsif cntr /= to_unsigned(0, cntr'length) then
+        cntr <= cntr - 1;
+      else
+        extended_int <= '0';
+      end if;
+    end if;
+  end process extend;
+
+  extended_o <= pulse_i or extended_int;
+
+end rtl;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
new file mode 100644
index 000000000..39b15afc7
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
@@ -0,0 +1,130 @@
+-------------------------------------------------------------------------------
+-- Title      : Frequency meter
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_frequency_meter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012-2015 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+
+entity gc_frequency_meter is
+  generic(
+    g_with_internal_timebase : boolean := true;
+    g_clk_sys_freq           : integer;
+    g_counter_bits           : integer := 32);
+
+  port(
+    clk_sys_i    : in  std_logic;
+    clk_in_i     : in  std_logic;
+    rst_n_i      : in  std_logic;
+    pps_p1_i     : in  std_logic;
+    freq_o       : out std_logic_vector(g_counter_bits-1 downto 0);
+    freq_valid_o : out std_logic
+    );
+
+end gc_frequency_meter;
+
+
+architecture behavioral of gc_frequency_meter is
+
+  signal gate_pulse, gate_pulse_synced : std_logic;
+
+  signal cntr_gate : unsigned(g_counter_bits-1 downto 0);
+  signal cntr_meas : unsigned(g_counter_bits-1 downto 0);
+  signal freq_reg  : std_logic_vector(g_counter_bits-1 downto 0);
+
+begin
+
+  gen_internal_timebase : if(g_with_internal_timebase = true) generate
+
+    p_gate_counter : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_n_i = '0' then
+          cntr_gate  <= (others => '0');
+          gate_pulse <= '0';
+        else
+          if(cntr_gate = g_clk_sys_freq-1) then
+            cntr_gate  <= (others => '0');
+            gate_pulse <= '1';
+          else
+            cntr_gate  <= cntr_gate + 1;
+            gate_pulse <= '0';
+          end if;
+        end if;
+      end if;
+    end process;
+
+  U_Sync_Gate : gc_pulse_synchronizer
+    port map (
+      clk_in_i  => clk_sys_i,
+      clk_out_i => clk_in_i,
+      rst_n_i   => rst_n_i,
+      d_ready_o => freq_valid_o,
+      d_p_i     => gate_pulse,
+      q_p_o     => gate_pulse_synced);
+
+  end generate gen_internal_timebase;
+
+  gen_external_timebase : if(g_with_internal_timebase = false) generate
+
+    U_Sync_Gate : gc_pulse_synchronizer
+    port map (
+      clk_in_i  => clk_sys_i,
+      clk_out_i => clk_in_i,
+      rst_n_i   => rst_n_i,
+      d_ready_o => freq_valid_o,
+      d_p_i     => pps_p1_i,
+      q_p_o     => gate_pulse_synced);
+
+  end generate gen_external_timebase;
+
+
+  p_freq_counter : process (clk_in_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then               -- asynchronous reset (active low)
+      cntr_meas <= (others => '0');
+      freq_reg  <= (others => '0');
+    elsif rising_edge(clk_in_i) then
+      
+      if(gate_pulse_synced = '1') then
+        freq_reg  <= std_logic_vector(cntr_meas);
+        cntr_meas <= (others => '0');
+      else
+        cntr_meas <= cntr_meas + 1;
+      end if;
+    end if;
+  end process p_freq_counter;
+
+  freq_o <= freq_reg;
+end behavioral;
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
new file mode 100644
index 000000000..1707450d1
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
@@ -0,0 +1,134 @@
+-------------------------------------------------------------------------------
+-- Title      : Pulse synchronizer
+-- Project    : General Cores Library 
+-------------------------------------------------------------------------------
+-- File       : gc_pulse_synchronizer.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-01-10
+-- Last update: 2012-08-29
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Full feedback pulse synchronizer (works independently of the
+-- input/output clock domain frequency ratio)
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2012-01-12  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.gencores_pkg.all;
+
+entity gc_pulse_synchronizer is
+  
+  port (
+    -- pulse input clock
+    clk_in_i  : in  std_logic;
+    -- pulse output clock
+    clk_out_i : in  std_logic;
+    -- system reset (clk_in_i domain)
+    rst_n_i   : in  std_logic;
+    -- pulse input ready (clk_in_i domain). When HI, a pulse coming to d_p_i will be
+    -- correctly transferred to q_p_o.
+    d_ready_o : out std_logic;
+    -- pulse input (clk_in_i domain)
+    d_p_i     : in  std_logic;
+    -- pulse output (clk_out_i domain)
+    q_p_o     : out std_logic);
+
+end gc_pulse_synchronizer;
+
+architecture rtl of gc_pulse_synchronizer is
+
+  constant c_sync_stages : integer := 3;
+
+  signal ready, d_p_d0 : std_logic;
+
+  signal in_ext, out_ext : std_logic;
+  signal out_feedback    : std_logic;
+
+  signal d_in2out : std_logic_vector(c_sync_stages-1 downto 0);
+  signal d_out2in : std_logic_vector(c_sync_stages-1 downto 0);
+
+begin  -- rtl
+
+  process(clk_out_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      d_in2out <= (others => '0');
+      out_ext <= '0';
+    elsif rising_edge(clk_out_i) then
+      d_in2out <= d_in2out(c_sync_stages-2 downto 0) & in_ext;
+      out_ext <= d_in2out(c_sync_stages-1);
+    end if;
+  end process;
+
+
+  process(clk_in_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      d_out2in <= (others => '0');
+    elsif rising_edge(clk_in_i) then
+      d_out2in <= d_out2in(c_sync_stages-2 downto 0) & out_ext;
+    end if;
+  end process;
+
+  out_feedback <= d_out2in(c_sync_stages-1);
+
+  p_input_ack : process(clk_in_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      ready  <= '1';
+      in_ext <= '0';
+      d_p_d0 <= '0';
+    elsif rising_edge(clk_in_i) then
+
+      d_p_d0 <= d_p_i;
+      
+      if(ready = '1' and d_p_i = '1' and d_p_d0 = '0') then
+        in_ext <= '1';
+        ready  <= '0';
+      elsif(in_ext = '1' and out_feedback = '1') then
+        in_ext <= '0';
+      elsif(in_ext = '0' and out_feedback = '0') then
+        ready <= '1';
+      end if;
+    end if;
+  end process;
+
+  p_drive_output : process(clk_out_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      q_p_o <= '0';
+    elsif rising_edge(clk_out_i) then
+      q_p_o <= not out_ext and d_in2out(c_sync_stages-1);
+    end if;
+  end process;
+
+  d_ready_o <= ready;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
new file mode 100644
index 000000000..280c72bd8
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
@@ -0,0 +1,132 @@
+-------------------------------------------------------------------------------
+-- Title      : Pulse synchronizer
+-- Project    : General Cores Library 
+-------------------------------------------------------------------------------
+-- File       : gc_pulse_synchronizer2.vhd
+-- Author     : Tomasz Wlostowski, Wesley Terpstra
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-01-10
+-- Last update: 2012-08-29
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Full feedback pulse synchronizer (works independently of the
+-- input/output clock domain frequency ratio)
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2012-01-12  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.gencores_pkg.all;
+
+entity gc_pulse_synchronizer2 is
+  port (
+    -- pulse input clock
+    clk_in_i    : in  std_logic;
+    rst_in_n_i  : in  std_logic;
+    -- pulse output clock
+    clk_out_i   : in  std_logic;
+    rst_out_n_i : in  std_logic;
+    
+    -- pulse input ready (clk_in_i domain). When HI, a pulse coming to d_p_i will be
+    -- correctly transferred to q_p_o.
+    d_ready_o : out std_logic;
+    -- pulse input (clk_in_i domain)
+    d_p_i     : in  std_logic;
+    -- pulse output (clk_out_i domain)
+    q_p_o     : out std_logic);
+
+end gc_pulse_synchronizer2;
+
+architecture rtl of gc_pulse_synchronizer2 is
+
+  constant c_sync_stages : integer := 3;
+
+  signal ready, d_p_d0 : std_logic;
+
+  signal in_ext, out_ext : std_logic;
+  signal out_feedback    : std_logic;
+
+  signal d_in2out : std_logic_vector(c_sync_stages-1 downto 0);
+  signal d_out2in : std_logic_vector(c_sync_stages-1 downto 0);
+
+begin  -- rtl
+
+  process(clk_out_i, rst_out_n_i)
+  begin
+    if rst_out_n_i = '0' then
+      d_in2out <= (others => '0');
+      out_ext <= '0';
+    elsif rising_edge(clk_out_i) then
+      d_in2out <= d_in2out(c_sync_stages-2 downto 0) & in_ext;
+      out_ext <= d_in2out(c_sync_stages-1);
+    end if;
+  end process;
+
+
+  process(clk_in_i, rst_in_n_i)
+  begin
+    if rst_in_n_i = '0' then
+      d_out2in <= (others => '0');
+    elsif rising_edge(clk_in_i) then
+      d_out2in <= d_out2in(c_sync_stages-2 downto 0) & out_ext;
+    end if;
+  end process;
+
+  out_feedback <= d_out2in(c_sync_stages-1);
+
+  p_input_ack : process(clk_in_i, rst_in_n_i)
+  begin
+    if rst_in_n_i = '0' then
+      ready  <= '1';
+      in_ext <= '0';
+      d_p_d0 <= '0';
+    elsif rising_edge(clk_in_i) then
+
+      d_p_d0 <= d_p_i;
+      
+      if(ready = '1' and d_p_i = '1' and d_p_d0 = '0') then
+        in_ext <= not in_ext;
+        ready  <= '0';
+      elsif(in_ext = out_feedback) then
+        ready <= '1';
+      end if;
+    end if;
+  end process;
+
+  p_drive_output : process(clk_out_i, rst_out_n_i)
+  begin
+    if rst_out_n_i = '0' then
+      q_p_o <= '0';
+    elsif rising_edge(clk_out_i) then
+      q_p_o <= out_ext xor d_in2out(c_sync_stages-1);
+    end if;
+  end process;
+
+  d_ready_o <= ready;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_reset.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_reset.vhd
new file mode 100644
index 000000000..e4fa0a493
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_reset.vhd
@@ -0,0 +1,87 @@
+-------------------------------------------------------------------------------
+-- Title      : Reset synchronizer and generator
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_reset.vhd
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity gc_reset is
+  generic(
+    g_clocks    : natural := 1;
+    g_logdelay  : natural := 10;
+    g_syncdepth : natural := 3);
+  port(
+    free_clk_i : in  std_logic;
+    locked_i   : in  std_logic := '1'; -- All the PLL locked signals ANDed together
+    clks_i     : in  std_logic_vector(g_clocks-1 downto 0);
+    rstn_o     : out std_logic_vector(g_clocks-1 downto 0));
+end gc_reset;
+
+architecture rtl of gc_reset is
+  subtype t_shifter is std_logic_vector(g_syncdepth-1 downto 0);
+  type t_shifters is array(natural range <>) of t_shifter;
+  
+  signal shifters : t_shifters(g_clocks-1 downto 0) := (others => (others => '0')); -- start reset
+  signal locked_count : unsigned(g_logdelay-1 downto 0) := (others => '0');
+  signal master_rstn : std_logic := '0';
+begin
+  lock : process(free_clk_i, locked_i)
+    constant locked_done : unsigned(g_logdelay-1 downto 0) := (others => '1');
+  begin
+    -- Asynchronous reset
+    if locked_i = '0' then
+      master_rstn <= '0';
+      locked_count <= (others => '0');
+    else
+      if rising_edge(free_clk_i) then
+        if locked_count = locked_done then
+          master_rstn <= '1';
+        else
+          master_rstn <= '0';
+          locked_count <= locked_count + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  -- Generate the sync chains for each clock domain
+  syncs : for i in g_clocks-1 downto 0 generate
+    sync : process(clks_i(i))
+    begin
+      if rising_edge(clks_i(i)) then
+        shifters(i) <= master_rstn & shifters(i)(g_syncdepth-1 downto 1);
+      end if;
+    end process;
+  end generate;
+
+  -- Output the synchronized reset
+  rstn : for i in g_clocks-1 downto 0 generate
+    rstn_o(i) <= shifters(i)(0);
+  end generate;
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
new file mode 100644
index 000000000..6603c0297
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
@@ -0,0 +1,125 @@
+-------------------------------------------------------------------------------
+-- Title      : Synchronizer chain
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : gc_sync_ffs.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-06-14
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: Synchronizer chain and edge detector.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009 - 2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2010-06-14  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity gc_sync_ffs is
+  generic(
+    g_sync_edge : string := "positive"
+    );
+  port(
+    clk_i    : in  std_logic;  -- clock from the destination clock domain
+    rst_n_i  : in  std_logic;           -- reset
+    data_i   : in  std_logic;           -- async input
+    synced_o : out std_logic;           -- synchronized output
+    npulse_o : out std_logic;  -- negative edge detect output (single-clock
+    -- pulse)
+    ppulse_o : out std_logic   -- positive edge detect output (single-clock
+   -- pulse)
+    );
+end gc_sync_ffs;
+
+-- make Altera Quartus quiet regarding unknown attributes:
+-- altera message_off 10335
+
+architecture behavioral of gc_sync_ffs is
+  signal sync0, sync1, sync2 : std_logic;
+
+  attribute shreg_extract : string;
+  attribute shreg_extract of sync0  : signal is "no";
+  attribute shreg_extract of sync1  : signal is "no";
+  attribute shreg_extract of sync2  : signal is "no";
+
+  attribute keep : string;
+  attribute keep of sync0  : signal is "true";
+  attribute keep of sync1  : signal is "true";
+
+  -- synchronizer attribute for Vivado
+  attribute ASYNC_REG : string;
+  attribute ASYNC_REG of sync0 : signal is "true";
+  attribute ASYNC_REG of sync1 : signal is "true";
+  attribute ASYNC_REG of sync2 : signal is "true";
+
+begin
+
+
+  sync_posedge : if (g_sync_edge = "positive") generate
+    process(clk_i, rst_n_i)
+    begin
+      if(rst_n_i = '0') then
+        sync0    <= '0';
+        sync1    <= '0';
+        sync2    <= '0';
+        synced_o <= '0';
+        npulse_o <= '0';
+        ppulse_o <= '0';
+      elsif rising_edge(clk_i) then
+        sync0    <= data_i;
+        sync1    <= sync0;
+        sync2    <= sync1;
+        synced_o <= sync1;
+        npulse_o <= sync2 and not sync1;
+        ppulse_o <= not sync2 and sync1;
+      end if;
+    end process;
+  end generate sync_posedge;
+
+  sync_negedge : if(g_sync_edge = "negative") generate
+    process(clk_i, rst_n_i)
+    begin
+      if(rst_n_i = '0') then
+        sync0    <= '0';
+        sync1    <= '0';
+        sync2    <= '0';
+        synced_o <= '0';
+        npulse_o <= '0';
+        ppulse_o <= '0';
+      elsif falling_edge(clk_i) then
+        sync0    <= data_i;
+        sync1    <= sync0;
+        sync2    <= sync1;
+        synced_o <= sync1;
+        npulse_o <= sync2 and not sync1;
+        ppulse_o <= not sync2 and sync1;
+      end if;
+    end process;
+  end generate sync_negedge;
+  
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_sync_register.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_sync_register.vhd
new file mode 100644
index 000000000..8d43ef443
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gc_sync_register.vhd
@@ -0,0 +1,88 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrized synchronizer
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_sync_register.vhd
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2014-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+--  Modifications:
+--      2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
+--          * added ASYNC_REG attribute for better timing analysis/simulation
+--            in Xilinx tools
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity gc_sync_register is
+  generic (
+    g_width : integer);
+  port (
+    clk_i     : in  std_logic;
+    rst_n_a_i : in  std_logic;
+    d_i       : in  std_logic_vector(g_width-1 downto 0);
+    q_o       : out std_logic_vector(g_width-1 downto 0));
+
+end gc_sync_register;
+
+-- make Altera Quartus quiet regarding unknown attributes:
+-- altera message_off 10335
+
+architecture rtl of gc_sync_register is
+
+  signal gc_sync_register_in : std_logic_vector(g_width-1 downto 0);
+  signal sync0, sync1        : std_logic_vector(g_width-1 downto 0);
+
+  attribute shreg_extract                        : string;
+  attribute shreg_extract of gc_sync_register_in : signal is "no";
+  attribute shreg_extract of sync0               : signal is "no";
+  attribute shreg_extract of sync1               : signal is "no";
+
+  attribute keep                        : string;
+  attribute keep of gc_sync_register_in : signal is "true";
+  attribute keep of sync0               : signal is "true";
+  attribute keep of sync1               : signal is "true";
+  
+  attribute async_reg                        : string;
+  attribute async_reg of gc_sync_register_in : signal is "true";
+  attribute async_reg of sync0               : signal is "true";
+  attribute async_reg of sync1               : signal is "true";
+
+begin
+
+  process(clk_i, rst_n_a_i)
+  begin
+    if(rst_n_a_i = '0') then
+      sync1 <= (others => '0');
+      sync0 <= (others => '0');
+    elsif rising_edge(clk_i) then
+      sync0 <= gc_sync_register_in;
+      sync1 <= sync0;
+    end if;
+  end process;
+
+  gc_sync_register_in <= d_i;
+  q_o                 <= sync1;
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gencores_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gencores_pkg.vhd
new file mode 100644
index 000000000..4e6d39fe7
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/gencores_pkg.vhd
@@ -0,0 +1,674 @@
+-------------------------------------------------------------------------------
+-- Title      : General cores VHDL package
+-- Project    : General Cores library
+-------------------------------------------------------------------------------
+-- File       : gencores_pkg.vhd
+-- Author     : Tomasz Wlostowski
+--              Theodor-Adrian Stana
+--              Matthieu Cattin
+--              Dimitrios Lampridis
+-- Company    : CERN
+-- Created    : 2009-09-01
+-- Last update: 2017-10-11
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description:
+-- Package incorporating simple VHDL modules and functions, which are used
+-- in the WR and other OHWR projects.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2016 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.genram_pkg.all;
+
+package gencores_pkg is
+
+  --============================================================================
+  -- Component instantiations
+  --============================================================================
+
+  ------------------------------------------------------------------------------
+  -- Pulse extender
+  ------------------------------------------------------------------------------
+  component gc_extend_pulse
+    generic (
+      g_width : natural);
+    port (
+      clk_i      : in  std_logic;
+      rst_n_i    : in  std_logic;
+      pulse_i    : in  std_logic;
+      extended_o : out std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- CRC generator
+  ------------------------------------------------------------------------------
+  component gc_crc_gen
+    generic (
+      g_polynomial              : std_logic_vector       := x"04C11DB7";
+      g_init_value              : std_logic_vector       := x"ffffffff";
+      g_residue                 : std_logic_vector       := x"38fb2284";
+      g_data_width              : integer range 2 to 256 := 16;
+      g_half_width              : integer range 2 to 256 := 8;
+      g_sync_reset              : integer range 0 to 1   := 1;
+      g_dual_width              : integer range 0 to 1   := 0;
+      g_registered_match_output : boolean                := true;
+      g_registered_crc_output   : boolean                := true);
+    port (
+      clk_i     : in  std_logic;
+      rst_i     : in  std_logic;
+      en_i      : in  std_logic;
+      half_i    : in  std_logic;
+      restart_i : in  std_logic := '0';
+      data_i    : in  std_logic_vector(g_data_width - 1 downto 0);
+      match_o   : out std_logic;
+      crc_o     : out std_logic_vector(g_polynomial'length - 1 downto 0));
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Moving average
+  ------------------------------------------------------------------------------
+  component gc_moving_average
+    generic (
+      g_data_width : natural;
+      g_avg_log2   : natural range 1 to 8);
+    port (
+      rst_n_i    : in  std_logic;
+      clk_i      : in  std_logic;
+      din_i      : in  std_logic_vector(g_data_width-1 downto 0);
+      dout_o     : out std_logic_vector(g_data_width+g_avg_log2-1 downto 0);
+      dout_stb_o : out std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Delay line
+  ------------------------------------------------------------------------------
+  component gc_delay_line
+    generic (
+      g_delay : integer;
+      g_width : integer);
+    port (
+      clk_i   : in  std_logic;
+      rst_n_i : in  std_logic;
+      d_i     : in  std_logic_vector(g_width -1 downto 0);
+      q_o     : out std_logic_vector(g_width -1 downto 0);
+      ready_o : out std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- PI controller
+  ------------------------------------------------------------------------------
+  component gc_dual_pi_controller
+    generic (
+      g_error_bits          : integer;
+      g_dacval_bits         : integer;
+      g_output_bias         : integer;
+      g_integrator_fracbits : integer;
+      g_integrator_overbits : integer;
+      g_coef_bits           : integer);
+    port (
+      clk_sys_i         : in  std_logic;
+      rst_n_sysclk_i    : in  std_logic;
+      phase_err_i       : in  std_logic_vector(g_error_bits-1 downto 0);
+      phase_err_stb_p_i : in  std_logic;
+      freq_err_i        : in  std_logic_vector(g_error_bits-1 downto 0);
+      freq_err_stb_p_i  : in  std_logic;
+      mode_sel_i        : in  std_logic;
+      dac_val_o         : out std_logic_vector(g_dacval_bits-1 downto 0);
+      dac_val_stb_p_o   : out std_logic;
+      pll_pcr_enable_i  : in  std_logic;
+      pll_pcr_force_f_i : in  std_logic;
+      pll_fbgr_f_kp_i   : in  std_logic_vector(g_coef_bits-1 downto 0);
+      pll_fbgr_f_ki_i   : in  std_logic_vector(g_coef_bits-1 downto 0);
+      pll_pbgr_p_kp_i   : in  std_logic_vector(g_coef_bits-1 downto 0);
+      pll_pbgr_p_ki_i   : in  std_logic_vector(g_coef_bits-1 downto 0));
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Serial 16-bit DAC interface (SPI/QSPI/MICROWIRE compatible)
+  ------------------------------------------------------------------------------
+  component gc_serial_dac
+    generic (
+      g_num_data_bits  : integer;
+      g_num_extra_bits : integer;
+      g_num_cs_select  : integer;
+      g_sclk_polarity  : integer);
+    port (
+      clk_i         : in  std_logic;
+      rst_n_i       : in  std_logic;
+      value_i       : in  std_logic_vector(g_num_data_bits-1 downto 0);
+      cs_sel_i      : in  std_logic_vector(g_num_cs_select-1 downto 0);
+      load_i        : in  std_logic;
+      sclk_divsel_i : in  std_logic_vector(2 downto 0);
+      dac_cs_n_o    : out std_logic_vector(g_num_cs_select-1 downto 0);
+      dac_sclk_o    : out std_logic;
+      dac_sdata_o   : out std_logic;
+      busy_o        : out std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Synchronisation FF chain
+  ------------------------------------------------------------------------------
+  component gc_sync_ffs
+    generic (
+      g_sync_edge : string := "positive");
+    port (
+      clk_i    : in  std_logic;
+      rst_n_i  : in  std_logic;
+      data_i   : in  std_logic;
+      synced_o : out std_logic;
+      npulse_o : out std_logic;
+      ppulse_o : out std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Pulse synchroniser
+  ------------------------------------------------------------------------------
+  component gc_pulse_synchronizer
+    port (
+      clk_in_i  : in  std_logic;
+      clk_out_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+      d_ready_o : out std_logic;
+      d_p_i     : in  std_logic;
+      q_p_o     : out std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Pulse synchroniser (with reset from both clock domains)
+  ------------------------------------------------------------------------------
+  component gc_pulse_synchronizer2 is
+    port (
+      clk_in_i    : in  std_logic;
+      rst_in_n_i  : in  std_logic;
+      clk_out_i   : in  std_logic;
+      rst_out_n_i : in  std_logic;
+      d_ready_o   : out std_logic;
+      d_p_i       : in  std_logic;
+      q_p_o       : out std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Frequency meter
+  ------------------------------------------------------------------------------
+  component gc_frequency_meter
+    generic (
+      g_with_internal_timebase : boolean;
+      g_clk_sys_freq           : integer;
+      g_counter_bits           : integer);
+    port (
+      clk_sys_i    : in  std_logic;
+      clk_in_i     : in  std_logic;
+      rst_n_i      : in  std_logic;
+      pps_p1_i     : in  std_logic;
+      freq_o       : out std_logic_vector(g_counter_bits-1 downto 0);
+      freq_valid_o : out std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Time-division multiplexer with round robin arbitration
+  ------------------------------------------------------------------------------
+  component gc_arbitrated_mux
+    generic (
+      g_num_inputs : integer;
+      g_width      : integer);
+    port (
+      clk_i        : in  std_logic;
+      rst_n_i      : in  std_logic;
+      d_i          : in  std_logic_vector(g_num_inputs * g_width-1 downto 0);
+      d_valid_i    : in  std_logic_vector(g_num_inputs-1 downto 0);
+      d_req_o      : out std_logic_vector(g_num_inputs-1 downto 0);
+      q_o          : out std_logic_vector(g_width-1 downto 0);
+      q_valid_o    : out std_logic;
+      q_input_id_o : out std_logic_vector(f_log2_size(g_num_inputs)-1 downto 0));
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Power-On reset generator
+  ------------------------------------------------------------------------------
+  component gc_reset is
+    generic(
+      g_clocks    : natural := 1;
+      g_logdelay  : natural := 10;
+      g_syncdepth : natural := 3);
+    port(
+      free_clk_i : in  std_logic;
+      locked_i   : in  std_logic := '1';  -- All the PLL locked signals ANDed together
+      clks_i     : in  std_logic_vector(g_clocks-1 downto 0);
+      rstn_o     : out std_logic_vector(g_clocks-1 downto 0));
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Power-On reset generator of synchronous single reset from multiple
+  -- asynchronous input reset signals
+  ------------------------------------------------------------------------------
+  component gc_single_reset_gen is
+    generic(
+      g_out_reg_depth     : natural :=2;
+      g_rst_in_num        : natural :=2);
+    port (
+      clk_i               : in std_logic;
+      rst_signals_n_a_i   : in std_logic_vector(g_rst_in_num-1 downto 0);
+      rst_n_o             : out std_logic
+    );
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Round robin arbiter
+  ------------------------------------------------------------------------------
+  component gc_rr_arbiter
+    generic (
+      g_size : integer);
+    port (
+      clk_i        : in  std_logic;
+      rst_n_i      : in  std_logic;
+      req_i        : in  std_logic_vector(g_size-1 downto 0);
+      grant_o      : out std_logic_vector(g_size-1 downto 0);
+      grant_comb_o : out std_logic_vector(g_size-1 downto 0));
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Pack or unpack words
+  ------------------------------------------------------------------------------
+  component gc_word_packer
+    generic (
+      g_input_width  : integer;
+      g_output_width : integer);
+    port (
+      clk_i     : in  std_logic;
+      rst_n_i   : in  std_logic;
+      d_i       : in  std_logic_vector(g_input_width-1 downto 0);
+      d_valid_i : in  std_logic;
+      d_req_o   : out std_logic;
+      flush_i   : in  std_logic := '0';
+      q_o       : out std_logic_vector(g_output_width-1 downto 0);
+      q_valid_o : out std_logic;
+      q_req_i   : in  std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Adder
+  ------------------------------------------------------------------------------
+  component gc_big_adder is
+    generic(
+      g_data_bits : natural := 64;
+      g_parts     : natural := 4);
+    port(
+      clk_i   : in  std_logic;
+      stall_i : in  std_logic := '0';
+      a_i     : in  std_logic_vector(g_data_bits-1 downto 0);
+      b_i     : in  std_logic_vector(g_data_bits-1 downto 0);
+      c_i     : in  std_logic := '0';
+      c1_o    : out std_logic;
+      x2_o    : out std_logic_vector(g_data_bits-1 downto 0);
+      c2_o    : out std_logic);
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- I2C slave
+  ------------------------------------------------------------------------------
+  constant c_i2cs_idle      : std_logic_vector(1 downto 0) := "00";
+  constant c_i2cs_addr_good : std_logic_vector(1 downto 0) := "01";
+  constant c_i2cs_rd_done   : std_logic_vector(1 downto 0) := "10";
+  constant c_i2cs_wr_done   : std_logic_vector(1 downto 0) := "11";
+
+  component gc_i2c_slave is
+    generic
+      (
+        -- Length of glitch filter
+        -- 0 - SCL and SDA lines are passed only through synchronizer
+        -- 1 - one clk_i glitches filtered
+        -- 2 - two clk_i glitches filtered
+        g_gf_len        : natural := 0;
+        g_auto_addr_ack : boolean := FALSE
+        );
+    port
+      (
+        -- Clock, reset ports
+        clk_i   : in std_logic;
+        rst_n_i : in std_logic;
+
+        -- I2C lines
+        scl_i    : in  std_logic;
+        scl_o    : out std_logic;
+        scl_en_o : out std_logic;
+        sda_i    : in  std_logic;
+        sda_o    : out std_logic;
+        sda_en_o : out std_logic;
+
+        -- Slave address
+        i2c_addr_i : in std_logic_vector(6 downto 0);
+
+        -- ACK input, should be set after done_p_o = '1'
+        -- (note that the bit is reversed wrt I2C ACK bit)
+        -- '1' - ACK
+        -- '0' - NACK
+        ack_i : in std_logic;
+
+        -- Byte to send, should be loaded while done_p_o = '1'
+        tx_byte_i : in std_logic_vector(7 downto 0);
+
+        -- Received byte, valid after done_p_o = '1'
+        rx_byte_o : out std_logic_vector(7 downto 0);
+
+        -- Pulse outputs signaling various I2C actions
+        -- Start and stop conditions
+        i2c_sta_p_o   : out std_logic;
+        i2c_sto_p_o   : out std_logic;
+        -- Received address corresponds addr_i
+        addr_good_p_o : out std_logic;
+        -- Read and write done
+        r_done_p_o    : out std_logic;
+        w_done_p_o    : out std_logic;
+
+        -- I2C bus operation, set after address detection
+        -- '0' - write
+        -- '1' - read
+        op_o : out std_logic
+        );
+  end component gc_i2c_slave;
+
+  ------------------------------------------------------------------------------
+  -- Glitch filter
+  ------------------------------------------------------------------------------
+  component gc_glitch_filt is
+    generic
+      (
+        -- Length of glitch filter:
+        -- g_len = 1 => data width should be > 1 clk_i cycle
+        -- g_len = 2 => data width should be > 2 clk_i cycle
+        -- etc.
+        g_len : natural := 4
+        );
+    port
+      (
+        clk_i   : in std_logic;
+        rst_n_i : in std_logic;
+
+        -- Data input
+        dat_i : in std_logic;
+
+        -- Data output
+        -- latency: g_len+1 clk_i cycles
+        dat_o : out std_logic
+        );
+  end component gc_glitch_filt;
+
+  ------------------------------------------------------------------------------
+  -- Dynamic glitch filter
+  ------------------------------------------------------------------------------
+  component gc_dyn_glitch_filt is
+    generic
+      (
+        -- Number of bit of the glitch filter length input
+        g_len_width : natural := 8
+        );
+    port
+      (
+        clk_i   : in std_logic;
+        rst_n_i : in std_logic;
+
+        -- Glitch filter length
+        len_i : in std_logic_vector(g_len_width-1 downto 0);
+
+        -- Data input
+        dat_i : in std_logic;
+
+        -- Data output
+        -- latency: g_len+1 clk_i cycles
+        dat_o : out std_logic
+        );
+  end component gc_dyn_glitch_filt;
+
+  ------------------------------------------------------------------------------
+  -- FSM Watchdog Timer
+  ------------------------------------------------------------------------------
+  component gc_fsm_watchdog is
+    generic
+      (
+        -- Maximum value of watchdog timer in clk_i cycles
+        g_wdt_max : positive := 65535
+        );
+    port
+      (
+        -- Clock and active-low reset line
+        clk_i   : in std_logic;
+        rst_n_i : in std_logic;
+
+        -- Active-high watchdog timer reset line, synchronous to clk_i
+        wdt_rst_i : in std_logic;
+
+        -- Active-high reset output, synchronous to clk_i
+        fsm_rst_o : out std_logic
+        );
+  end component gc_fsm_watchdog;
+
+  ------------------------------------------------------------------------------
+  -- Bicolor LED controller
+  ------------------------------------------------------------------------------
+  constant c_led_red       : std_logic_vector(1 downto 0) := "10";
+  constant c_led_green     : std_logic_vector(1 downto 0) := "01";
+  constant c_led_red_green : std_logic_vector(1 downto 0) := "11";
+  constant c_led_off       : std_logic_vector(1 downto 0) := "00";
+
+  component gc_bicolor_led_ctrl
+    generic(
+      g_nb_column    : natural := 4;
+      g_nb_line      : natural := 2;
+      g_clk_freq     : natural := 125000000;  -- in Hz
+      g_refresh_rate : natural := 250         -- in Hz
+      );
+    port
+      (
+        rst_n_i         : in  std_logic;
+        clk_i           : in  std_logic;
+        led_intensity_i : in  std_logic_vector(6 downto 0);
+        led_state_i     : in  std_logic_vector((g_nb_line * g_nb_column * 2) - 1 downto 0);
+        column_o        : out std_logic_vector(g_nb_column - 1 downto 0);
+        line_o          : out std_logic_vector(g_nb_line - 1 downto 0);
+        line_oen_o      : out std_logic_vector(g_nb_line - 1 downto 0)
+        );
+  end component;
+
+  component gc_sync_register is
+    generic (
+      g_width : integer);
+    port (
+      clk_i     : in  std_logic;
+      rst_n_a_i : in  std_logic;
+      d_i       : in  std_logic_vector(g_width-1 downto 0);
+      q_o       : out std_logic_vector(g_width-1 downto 0));
+  end component gc_sync_register;
+
+  component gc_async_signals_input_stage is
+    generic (
+      g_signal_num                 : integer;
+      g_extended_pulse_width       : integer;
+      g_dglitch_filter_len         : integer);
+    port (
+      clk_i                        : in std_logic;
+      rst_n_i                      : in std_logic;
+      signals_a_i                  : in  std_logic_vector(g_signal_num-1 downto 0);
+      config_active_i              : in  std_logic_vector(g_signal_num-1 downto 0);
+      signals_o                    : out std_logic_vector(g_signal_num-1 downto 0);
+      signals_p1_o                 : out std_logic_vector(g_signal_num-1 downto 0);
+      signals_pN_o                 : out std_logic_vector(g_signal_num-1 downto 0));
+  end component;
+
+  --============================================================================
+  -- Procedures and functions
+  --============================================================================
+  procedure f_rr_arbitrate (
+    signal req       : in  std_logic_vector;
+    signal pre_grant : in  std_logic_vector;
+    signal grant     : out std_logic_vector);
+  function f_onehot_decode(x : std_logic_vector; size : integer) return std_logic_vector;
+
+  function f_big_ripple(a, b : std_logic_vector; c : std_logic) return std_logic_vector;
+  function f_gray_encode(x   : std_logic_vector) return std_logic_vector;
+  function f_gray_decode(x   : std_logic_vector; step : natural) return std_logic_vector;
+  function log2_ceil(N       : natural) return positive;
+
+  function f_bool2int (b : boolean) return natural;
+  function f_int2bool (n : natural) return boolean;
+
+end package;
+
+package body gencores_pkg is
+
+  ------------------------------------------------------------------------------
+  -- Simple round-robin arbiter:
+  --  req = requests (1 = pending request),
+  --  pre_grant = previous grant vector (1 cycle delay)
+  --  grant = new grant vector
+  ------------------------------------------------------------------------------
+  procedure f_rr_arbitrate (
+    signal req       : in  std_logic_vector;
+    signal pre_grant : in  std_logic_vector;
+    signal grant     : out std_logic_vector)is
+
+    variable reqs  : std_logic_vector(req'length - 1 downto 0);
+    variable gnts  : std_logic_vector(req'length - 1 downto 0);
+    variable gnt   : std_logic_vector(req'length - 1 downto 0);
+    variable gntM  : std_logic_vector(req'length - 1 downto 0);
+    variable zeros : std_logic_vector(req'length - 1 downto 0);
+
+  begin
+    zeros := (others => '0');
+
+    -- bit twiddling magic :
+    gnt  := req and std_logic_vector(unsigned(not req) + 1);
+    reqs := req and not (std_logic_vector(unsigned(pre_grant) - 1) or pre_grant);
+    gnts := reqs and std_logic_vector(unsigned(not reqs)+1);
+
+    if(reqs = zeros) then
+      gntM := gnt;
+    else
+      gntM := gnts;
+    end if;
+
+    if((req and pre_grant) = zeros) then
+      grant <= gntM;
+    else
+      grant <= pre_grant;
+    end if;
+
+  end f_rr_arbitrate;
+
+  function f_onehot_decode(x : std_logic_vector; size : integer) return std_logic_vector is
+  begin
+    for j in 0 to x'left loop
+      if x(j) /= '0' then
+        return std_logic_vector(to_unsigned(j, size));
+      end if;
+    end loop;  -- i
+    return std_logic_vector(to_unsigned(0, size));
+  end f_onehot_decode;
+
+
+
+  ------------------------------------------------------------------------------
+  -- Carry ripple
+  ------------------------------------------------------------------------------
+  function f_big_ripple(a, b : std_logic_vector; c : std_logic) return std_logic_vector is
+    constant len        : natural := a'length;
+    variable aw, bw, rw : std_logic_vector(len+1 downto 0);
+    variable x          : std_logic_vector(len downto 0);
+  begin
+    aw := "0" & a & c;
+    bw := "0" & b & c;
+    rw := std_logic_vector(unsigned(aw) + unsigned(bw));
+    x  := rw(len+1 downto 1);
+    return x;
+  end f_big_ripple;
+
+
+  ------------------------------------------------------------------------------
+  -- Gray encoder
+  ------------------------------------------------------------------------------
+  function f_gray_encode(x : std_logic_vector) return std_logic_vector is
+    variable o : std_logic_vector(x'length downto 0);
+  begin
+    o := (x & '0') xor ('0' & x);
+    return o(x'length downto 1);
+  end f_gray_encode;
+
+  ------------------------------------------------------------------------------
+  -- Gray decoder
+  --  call with step=1
+  ------------------------------------------------------------------------------
+  function f_gray_decode(x : std_logic_vector; step : natural) return std_logic_vector is
+    constant len : natural                          := x'length;
+    alias y      : std_logic_vector(len-1 downto 0) is x;
+    variable z   : std_logic_vector(len-1 downto 0) := (others => '0');
+  begin
+    if step >= len then
+      return y;
+    else
+      z(len-step-1 downto 0) := y(len-1 downto step);
+      return f_gray_decode(y xor z, step+step);
+    end if;
+  end f_gray_decode;
+
+  ------------------------------------------------------------------------------
+  -- Returns log of 2 of a natural number
+  ------------------------------------------------------------------------------
+  function log2_ceil(N : natural) return positive is
+  begin
+    if N <= 2 then
+      return 1;
+    elsif N mod 2 = 0 then
+      return 1 + log2_ceil(N/2);
+    else
+      return 1 + log2_ceil((N+1)/2);
+    end if;
+  end;
+
+  ------------------------------------------------------------------------------
+  -- Converts a boolean to natural integer (false -> 0, true -> 1)
+  ------------------------------------------------------------------------------
+  function f_bool2int (b : boolean) return natural is
+  begin
+    if b then
+      return 1;
+    else
+      return 0;
+    end if;
+  end;
+
+  ------------------------------------------------------------------------------
+  -- Converts a natural integer to boolean (0 -> false, any positive -> true)
+  ------------------------------------------------------------------------------
+  function f_int2bool (n : natural) return boolean is
+  begin
+    if n = 0 then
+      return false;
+    else
+      return true;
+    end if;
+  end;
+
+end gencores_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd
new file mode 100644
index 000000000..9158a4fdb
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd
@@ -0,0 +1,168 @@
+----------------------------------------------------------------------------
+----                                                                    ----
+----                                                                    ----
+---- This file is part of the srl_fifo project                          ----
+---- http://www.opencores.org/cores/srl_fifo                            ----
+----                                                                    ----
+---- Description                                                        ----
+---- Implementation of srl_fifo IP core according to                    ----
+---- srl_fifo IP core specification document.                           ----
+----                                                                    ----
+---- To Do:                                                             ----
+----    NA                                                              ----
+----                                                                    ----
+---- Author(s):                                                         ----
+----   Andrew Mulcock, amulcock@opencores.org                           ----
+----                                                                    ----
+---- Modified for WR Project by Tomasz Wlostowski                       ----
+----------------------------------------------------------------------------
+----                                                                    ----
+---- Copyright (C) 2008 Authors and OPENCORES.ORG                       ----
+----                                                                    ----
+---- This source file may be used and distributed without               ----
+---- restriction provided that this copyright statement is not          ----
+---- removed from the file and that any derivative work contains        ----
+---- the original copyright notice and the associated disclaimer.       ----
+----                                                                    ----
+---- This source file is free software; you can redistribute it         ----
+---- and/or modify it under the terms of the GNU Lesser General         ----
+---- Public License as published by the Free Software Foundation;       ----
+---- either version 2.1 of the License, or (at your option) any         ----
+---- later version.                                                     ----
+----                                                                    ----
+---- This source is distributed in the hope that it will be             ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied         ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ----
+---- PURPOSE. See the GNU Lesser General Public License for more        ----
+---- details.                                                           ----
+----                                                                    ----
+---- You should have received a copy of the GNU Lesser General          ----
+---- Public License along with this source; if not, download it         ----
+---- from http://www.opencores.org/lgpl.shtml                           ----
+----                                                                    ----
+----------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.NUMERIC_STD.all;
+
+use work.genram_pkg.all;
+
+entity generic_shiftreg_fifo is
+  generic (
+    g_data_width : integer := 128;
+    g_size       : integer := 32
+    );          
+  port (
+    rst_n_i : in std_logic := '1';
+    clk_i   : in std_logic;
+
+    d_i  : in  std_logic_vector(g_data_width-1 downto 0);
+    we_i : in  std_logic;
+    q_o  : out std_logic_vector(g_data_width-1 downto 0);
+    rd_i : in  std_logic;
+
+    full_o        : out std_logic;
+    almost_full_o : out std_logic;
+    q_valid_o     : out std_logic
+    );
+
+end generic_shiftreg_fifo;
+
+architecture rtl of generic_shiftreg_fifo is
+
+  component gc_shiftreg
+    generic (
+      g_size : integer);
+    port (
+      clk_i : in  std_logic;
+      en_i  : in  std_logic;
+      d_i   : in  std_logic;
+      q_o   : out std_logic;
+      a_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0));
+  end component;
+
+  signal pointer : integer range 0 to g_size-1 := 0;
+
+  signal srl_addr            : std_logic_vector(f_log2_size(g_size)-1 downto 0) := (others => '0');
+  signal pointer_zero        : std_logic;
+  signal pointer_full        : std_logic;
+  signal pointer_almost_full : std_logic;
+  signal empty               : std_logic := '1';
+  signal valid_count         : std_logic;
+  signal do_write            : std_logic;
+begin
+
+-- Valid write, high when valid to write data to the store.
+
+  do_write <= '1' when (rd_i = '1' and we_i = '1')
+              or (we_i = '1' and pointer_full = '0') else '0';
+
+
+  gen_sregs : for i in 0 to g_data_width-1 generate
+    U_SRLx : gc_shiftreg
+      generic map (
+        g_size => g_size)
+      port map (
+        clk_i => clk_i,
+        en_i  => do_write,
+        d_i   => d_i(i),
+        q_o   => q_o(i),
+        a_i   => srl_addr);
+  end generate gen_sregs;
+
+  srl_addr <= std_logic_vector(to_unsigned(pointer, srl_addr'length));
+
+  p_empty_logic : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        empty <= '1';
+      elsif empty = '1' and we_i = '1' then
+        empty <= '0';
+      elsif pointer_zero = '1' and rd_i = '1' and we_i = '0' then
+        empty <= '1';
+      end if;
+    end if;
+  end process;
+
+--      W       R       Action
+--      0       0       pointer <= pointer
+--      0       1       pointer <= pointer - 1  Read, but no write, so less data in counter
+--      1       0       pointer <= pointer + 1  Write, but no read, so more data in fifo
+--      1       1       pointer <= pointer              Read and write, so same number of words in fifo
+--
+  
+  valid_count <= '1' when (
+    (we_i = '1' and rd_i = '0' and pointer_full = '0' and empty = '0')
+    or
+    (we_i = '0' and rd_i = '1' and pointer_zero = '0')
+    ) else '0';
+
+  p_gen_address : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        pointer <= 0;
+      elsif valid_count = '1' then
+        if we_i = '1' then
+          pointer <= pointer + 1;
+        else
+          pointer <= pointer - 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -- Detect when pointer is zero and maximum
+  pointer_zero        <= '1' when pointer = 0                                else '0';
+  pointer_full        <= '1' when pointer = g_size - 1                       else '0';
+  pointer_almost_full <= '1' when pointer_full = '1' or pointer = g_size -3 or pointer = g_size - 2 else '0';
+
+
+  -- assign internal signals to outputs
+  full_o        <= pointer_full;
+  almost_full_o <= pointer_almost_full;
+  q_valid_o     <= not empty;
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd
new file mode 100644
index 000000000..bf24ea561
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd
@@ -0,0 +1,326 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable asynchronous FIFO (Generic version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_async_fifo.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2014-07-31
+-- Platform   :
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Dual-clock asynchronous FIFO.
+-- - configurable data width and size
+-- - configurable full/empty/almost full/almost empty/word count signals
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.genram_pkg.all;
+use work.gencores_pkg.all;
+
+entity inferred_async_fifo is
+
+  generic (
+    g_data_width : natural;
+    g_size       : natural;
+    g_show_ahead : boolean := false;
+
+    -- Read-side flag selection
+    g_with_rd_empty        : boolean := true;   -- with empty flag
+    g_with_rd_full         : boolean := false;  -- with full flag
+    g_with_rd_almost_empty : boolean := false;
+    g_with_rd_almost_full  : boolean := false;
+    g_with_rd_count        : boolean := false;  -- with words counter
+
+    g_with_wr_empty        : boolean := false;
+    g_with_wr_full         : boolean := true;
+    g_with_wr_almost_empty : boolean := false;
+    g_with_wr_almost_full  : boolean := false;
+    g_with_wr_count        : boolean := false;
+
+    g_almost_empty_threshold : integer;  -- threshold for almost empty flag
+    g_almost_full_threshold  : integer   -- threshold for almost full flag
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';
+
+
+    -- write port
+    clk_wr_i : in std_logic;
+    d_i      : in std_logic_vector(g_data_width-1 downto 0);
+    we_i     : in std_logic;
+
+    wr_empty_o        : out std_logic;
+    wr_full_o         : out std_logic;
+    wr_almost_empty_o : out std_logic; -- TODO: assign
+    wr_almost_full_o  : out std_logic;
+    wr_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
+
+    -- read port
+    clk_rd_i : in  std_logic;
+    q_o      : out std_logic_vector(g_data_width-1 downto 0);
+    rd_i     : in  std_logic;
+
+    rd_empty_o        : out std_logic;
+    rd_full_o         : out std_logic;
+    rd_almost_empty_o : out std_logic;
+    rd_almost_full_o  : out std_logic; -- TODO: assign
+    rd_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
+    );
+
+end inferred_async_fifo;
+
+
+architecture syn of inferred_async_fifo is
+
+  function f_bin2gray(bin : std_logic_vector) return std_logic_vector is
+  begin
+    return bin(bin'left) & (bin(bin'left-1 downto 0) xor bin(bin'left downto 1));
+  end f_bin2gray;
+
+  function f_gray2bin(gray : std_logic_vector) return std_logic_vector is
+    variable bin : std_logic_vector(gray'left downto 0);
+  begin
+    -- gray to binary
+    for i in 0 to gray'left loop
+      bin(i) := '0';
+      for j in i to gray'left loop
+        bin(i) := bin(i) xor gray(j);
+      end loop;  -- j
+    end loop;  -- i
+    return bin;
+  end f_gray2bin;
+
+  constant c_counter_bits : integer := f_log2_size(g_size) + 1;
+  subtype t_counter is std_logic_vector(c_counter_bits-1 downto 0);
+
+  type t_counter_block is record
+    bin, bin_next, gray, gray_next : t_counter;
+    bin_x, gray_x, gray_xm         : t_counter;
+  end record;
+
+  type   t_mem_type is array (0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
+  signal mem : t_mem_type;
+
+  signal rcb, wcb                          : t_counter_block;
+
+  
+  signal full_int, empty_int               : std_logic;
+  signal almost_full_int, almost_empty_int : std_logic;
+  signal going_full                        : std_logic;
+
+  signal wr_count, rd_count : t_counter;
+  signal rd_int, we_int : std_logic;
+
+  signal wr_empty_xm, wr_empty_x : std_logic;
+  signal rd_full_xm, rd_full_x   : std_logic;
+
+  signal almost_full_x, almost_full_xm   : std_logic;
+  signal almost_empty_x, almost_empty_xm : std_logic;
+
+begin  -- syn
+
+  rd_int <= rd_i and not empty_int;
+  we_int <= we_i and not full_int;
+
+  p_mem_write : process(clk_wr_i)
+  begin
+    if rising_edge(clk_wr_i) then
+      if(we_int = '1') then
+        mem(to_integer(unsigned(wcb.bin(wcb.bin'left-1 downto 0)))) <= d_i;
+      end if;
+    end if;
+  end process;
+
+  p_mem_read : process(clk_rd_i)
+  begin
+    if rising_edge(clk_rd_i) then
+      if(rd_int = '1') then
+        q_o <= mem(to_integer(unsigned(rcb.bin(rcb.bin'left-1 downto 0))));
+      end if;
+    end if;
+  end process;
+
+  wcb.bin_next  <= std_logic_vector(unsigned(wcb.bin) + 1);
+  wcb.gray_next <= f_bin2gray(wcb.bin_next);
+
+  p_write_ptr : process(clk_wr_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      wcb.bin  <= (others => '0');
+      wcb.gray <= (others => '0');
+    elsif rising_edge(clk_wr_i) then
+      if(we_int = '1') then
+        wcb.bin  <= wcb.bin_next;
+        wcb.gray <= wcb.gray_next;
+      end if;
+    end if;
+  end process;
+
+  rcb.bin_next  <= std_logic_vector(unsigned(rcb.bin) + 1);
+  rcb.gray_next <= f_bin2gray(rcb.bin_next);
+
+  p_read_ptr : process(clk_rd_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      rcb.bin  <= (others => '0');
+      rcb.gray <= (others => '0');
+    elsif rising_edge(clk_rd_i) then
+      if(rd_int = '1') then
+        rcb.bin  <= rcb.bin_next;
+        rcb.gray <= rcb.gray_next;
+      end if;
+    end if;
+  end process;
+
+    U_Sync1: gc_sync_register
+    generic map (
+      g_width => c_counter_bits)
+    port map (
+      clk_i    => clk_wr_i,
+      rst_n_a_i  => rst_n_i,
+      d_i  => rcb.gray,
+      q_o => rcb.gray_x);
+
+    U_Sync2: gc_sync_register
+    generic map (
+      g_width => c_counter_bits)
+    port map (
+      clk_i    => clk_rd_i,
+      rst_n_a_i  => rst_n_i,
+      d_i   => wcb.gray,
+      q_o => wcb.gray_x);
+
+  wcb.bin_x <= f_gray2bin(wcb.gray_x);
+  rcb.bin_x <= f_gray2bin(rcb.gray_x);
+
+  p_gen_empty : process(clk_rd_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      empty_int <= '1';
+    elsif rising_edge (clk_rd_i) then
+      if(rcb.gray = wcb.gray_x or (rd_int = '1' and (wcb.gray_x = rcb.gray_next))) then
+        empty_int <= '1';
+      else
+        empty_int <= '0';
+      end if;
+    end if;
+  end process;
+
+  U_Sync_Empty: gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_wr_i,
+      rst_n_i  => rst_n_i,
+      data_i   => empty_int,
+      synced_o => wr_empty_x);
+
+  U_Sync_Full: gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_rd_i,
+      rst_n_i  => rst_n_i,
+      data_i   => full_int,
+      synced_o => rd_full_x);
+ 
+  
+
+  rd_empty_o <= empty_int;
+  wr_empty_o <= wr_empty_x;
+
+  p_gen_going_full : process(we_int, wcb, rcb)
+  begin
+    if ((wcb.bin (wcb.bin'left-1 downto 0) = rcb.bin_x(rcb.bin_x'left-1 downto 0))
+        and (wcb.bin(wcb.bin'left) /= rcb.bin_x(wcb.bin_x'left))) then
+      going_full <= '1';
+    elsif (we_int = '1'
+           and (wcb.bin_next(wcb.bin'left-1 downto 0) = rcb.bin_x(rcb.bin_x'left-1 downto 0))
+           and (wcb.bin_next(wcb.bin'left) /= rcb.bin_x(rcb.bin_x'left))) then
+      going_full <= '1';
+    else
+      going_full <= '0';
+    end if;
+  end process;
+
+  p_register_full : process(clk_wr_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      full_int <= '0';
+    elsif rising_edge (clk_wr_i) then
+      full_int <= going_full;
+    end if;
+  end process;
+
+  wr_full_o <= full_int;
+  rd_full_o <= rd_full_x;
+
+  p_reg_almost_full : process(clk_wr_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      almost_full_int <= '0';
+    elsif rising_edge(clk_wr_i) then
+      wr_count <= std_logic_vector(unsigned(wcb.bin) - unsigned(rcb.bin_x));
+      if (unsigned(wr_count) >= g_almost_full_threshold) then
+        almost_full_int <= '1';
+      else
+        almost_full_int <= '0';
+      end if;
+    end if;
+  end process;
+
+  U_Sync_AlmostFull: gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_rd_i,
+      rst_n_i  => rst_n_i,
+      data_i   => almost_full_int,
+      synced_o => almost_full_x);
+
+  wr_almost_full_o  <= almost_full_int;
+  rd_almost_full_o  <= almost_full_x;
+
+  p_reg_almost_empty : process(clk_rd_i, rst_n_i)
+  begin
+    if rst_n_i = '0' then
+      almost_empty_int <= '1';
+    elsif rising_edge(clk_rd_i) then
+      rd_count     <= std_logic_vector(unsigned(wcb.bin_x) - unsigned(rcb.bin));
+      if (unsigned(rd_count) <= g_almost_empty_threshold) then
+        almost_empty_int <= '1';
+      else
+        almost_empty_int <= '0';
+      end if;
+    end if;
+  end process;
+
+  U_Sync_AlmostEmpty: gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_wr_i,
+      rst_n_i  => rst_n_i,
+      data_i   => almost_empty_int,
+      synced_o => almost_empty_x);
+
+  rd_almost_empty_o <= almost_empty_int;
+  wr_almost_empty_o <= almost_empty_x;
+
+  wr_count_o <= std_logic_vector(wr_count(f_log2_size(g_size)-1 downto 0));
+  rd_count_o <= std_logic_vector(rd_count(f_log2_size(g_size)-1 downto 0));
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd
new file mode 100644
index 000000000..c70a83003
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd
@@ -0,0 +1,261 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable synchronous FIFO (Generic version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_sync_fifo_std.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2017-02-03
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Single-clock FIFO. 
+-- - configurable data width and size
+-- - configurable full/empty/almost full/almost empty/word count signals
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.genram_pkg.all;
+
+entity inferred_sync_fifo is
+
+  generic (
+    g_data_width : natural;
+    g_size       : natural;
+    g_show_ahead : boolean := false;
+
+    -- Read-side flag selection
+    g_with_empty        : boolean := true;   -- with empty flag
+    g_with_full         : boolean := true;   -- with full flag
+    g_with_almost_empty : boolean := false;
+    g_with_almost_full  : boolean := false;
+    g_with_count        : boolean := false;  -- with words counter
+
+    g_almost_empty_threshold : integer := 0;  -- threshold for almost empty flag
+    g_almost_full_threshold  : integer := 0;  -- threshold for almost full flag
+
+    g_register_flag_outputs : boolean := true
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';
+
+    clk_i : in std_logic;
+    d_i   : in std_logic_vector(g_data_width-1 downto 0);
+    we_i  : in std_logic;
+
+    q_o  : out std_logic_vector(g_data_width-1 downto 0);
+    rd_i : in  std_logic;
+
+    empty_o        : out std_logic;
+    full_o         : out std_logic;
+    almost_empty_o : out std_logic;
+    almost_full_o  : out std_logic;
+    count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
+    );
+
+end inferred_sync_fifo;
+
+architecture syn of inferred_sync_fifo is
+
+  constant c_pointer_width                         : integer := f_log2_size(g_size);
+  signal   rd_ptr, wr_ptr, wr_ptr_d0, rd_ptr_muxed : unsigned(c_pointer_width-1 downto 0);
+  signal   usedw                                   : unsigned(c_pointer_width downto 0);
+  signal   full, empty                             : std_logic;
+  signal   q_int                                   : std_logic_vector(g_data_width-1 downto 0);
+  signal   we_int, rd_int                          : std_logic;
+  signal   guard_bit                               : std_logic;
+
+  signal q_comb : std_logic_vector(g_data_width-1 downto 0);
+  
+begin  -- syn
+
+  we_int <= we_i and not full;
+  rd_int <= rd_i and not empty;
+  
+  U_FIFO_Ram : generic_dpram
+    generic map (
+      g_data_width               => g_data_width,
+      g_size                     => g_size,
+      g_with_byte_enable         => false,
+      g_addr_conflict_resolution => "dont_care",
+      g_dual_clock               => false)
+    port map (
+      rst_n_i => rst_n_i,
+      clka_i  => clk_i,
+      wea_i   => we_int,
+      aa_i    => std_logic_vector(wr_ptr(c_pointer_width-1 downto 0)),
+      da_i    => d_i,
+      clkb_i  => '0',
+      ab_i    => std_logic_vector(rd_ptr_muxed(c_pointer_width-1 downto 0)),
+      qb_o    => q_comb);
+
+  process(rd_ptr, rd_i, rd_int)
+  begin
+    if(rd_int = '1' and g_show_ahead) then
+      rd_ptr_muxed <= rd_ptr + 1;
+    elsif((rd_int = '1' and not g_show_ahead) or (g_show_ahead)) then
+      rd_ptr_muxed <= rd_ptr;
+    else
+      rd_ptr_muxed <= rd_ptr - 1;
+    end if;
+  end process;
+
+  q_o <= q_comb;
+
+  p_pointers : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        wr_ptr <= (others => '0');
+        rd_ptr <= (others => '0');
+      else
+        if(we_int = '1') then
+          wr_ptr <= wr_ptr + 1;
+        end if;
+
+        if(rd_int = '1') then
+          rd_ptr <= rd_ptr + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  gen_comb_flags_showahead : if(g_show_ahead = true) generate
+
+    process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if ((rd_ptr + 1 = wr_ptr and rd_int = '1') or (rd_ptr = wr_ptr)) then
+          empty <= '1';
+        else
+          empty <= '0';
+        end if;
+      end if;
+    end process;
+    full <= '1' when (wr_ptr + 1 = rd_ptr) else '0';
+
+  end generate gen_comb_flags_showahead;
+
+  gen_comb_flags : if(g_register_flag_outputs = false and g_show_ahead = false) generate
+    empty <= '1' when (wr_ptr = rd_ptr and guard_bit = '0') else '0';
+    full  <= '1' when (wr_ptr = rd_ptr and guard_bit = '1') else '0';
+
+    p_guard_bit : process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if rst_n_i = '0' then
+          guard_bit <= '0';
+        elsif(wr_ptr + 1 = rd_ptr and we_int = '1') then
+          guard_bit <= '1';
+        elsif(rd_i = '1') then
+          guard_bit <= '0';
+        end if;
+      end if;
+    end process;
+  end generate gen_comb_flags;
+
+  gen_registered_flags : if(g_register_flag_outputs = true and g_show_ahead = false) generate
+    p_reg_flags : process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        
+        if(rst_n_i = '0') then
+          full  <= '0';
+          empty <= '1';
+        else
+          if(usedw = 1 and rd_int = '1' and we_int = '0') then
+            empty <= '1';
+          elsif(we_int = '1' and rd_int = '0') then
+            empty <= '0';
+          end if;
+
+          if(usedw = g_size-2 and we_int = '1' and rd_int = '0') then
+            full <= '1';
+          elsif(usedw = g_size-1 and rd_int = '1' and we_int = '0') then
+            full <= '0';
+          end if;
+        end if;
+        
+      end if;
+    end process;
+  end generate gen_registered_flags;
+
+
+  gen_with_word_counter : if(g_with_count or g_with_almost_empty or g_with_almost_full or g_register_flag_outputs) generate
+    p_usedw_counter : process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if rst_n_i = '0' then
+          usedw <= (others => '0');
+        else
+          if(we_int = '1' and rd_int = '0') then
+            usedw <= usedw + 1;
+          elsif(we_int = '0' and rd_int = '1') then
+            usedw <= usedw - 1;
+          end if;
+        end if;
+      end if;
+    end process;
+
+    count_o <= std_logic_vector(usedw(c_pointer_width-1 downto 0));
+
+  end generate gen_with_word_counter;
+
+  gen_with_almost_full : if(g_with_almost_full) generate
+    process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if rst_n_i = '0' then
+          almost_full_o <= '0';
+        else
+          if(usedw = g_almost_full_threshold-1) and (we_int = '1' and rd_int = '0') then
+            almost_full_o <= '1';
+          elsif (usedw = g_almost_full_threshold) and (rd_int = '1' and we_int = '0') then
+            almost_full_o <= '0';
+          end if;
+        end if;
+      end if;
+    end process;
+  end generate gen_with_almost_full;
+
+  gen_without_almost_full : if(not g_with_almost_full) generate
+    almost_full_o <= '0';
+  end generate gen_without_almost_full;
+
+  gen_with_almost_empty : if(g_with_almost_empty) generate
+    process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if rst_n_i = '0' then
+          almost_empty_o <= '1';
+        else
+          if(usedw = g_almost_empty_threshold+1) and (rd_int = '1' and we_int = '0') then
+            almost_empty_o <= '1';
+          elsif (usedw = g_almost_empty_threshold) and (we_int = '1' and rd_int = '0') then
+            almost_empty_o <= '0';
+          end if;
+        end if;
+      end if;
+    end process;
+  end generate gen_with_almost_empty;
+
+  gen_without_almost_empty : if(not g_with_almost_empty) generate
+    almost_empty_o <= '0';
+  end generate gen_without_almost_empty;
+
+  full_o  <= full;
+  empty_o <= empty;
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
new file mode 100644
index 000000000..66fce2fe0
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
@@ -0,0 +1,162 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable asynchronous FIFO (Generic version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_async_fifo.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2012-07-03
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Dual-clock asynchronous FIFO. 
+-- - configurable data width and size
+-- - configurable full/empty/almost full/almost empty/word count signals
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.genram_pkg.all;
+
+entity generic_async_fifo is
+
+  generic (
+    g_data_width : natural;
+    g_size       : natural;
+    g_show_ahead : boolean := false;
+
+    -- Read-side flag selection
+    g_with_rd_empty        : boolean := true;   -- with empty flag
+    g_with_rd_full         : boolean := false;  -- with full flag
+    g_with_rd_almost_empty : boolean := false;
+    g_with_rd_almost_full  : boolean := false;
+    g_with_rd_count        : boolean := false;  -- with words counter
+
+    g_with_wr_empty        : boolean := false;
+    g_with_wr_full         : boolean := true;
+    g_with_wr_almost_empty : boolean := false;
+    g_with_wr_almost_full  : boolean := false;
+    g_with_wr_count        : boolean := false;
+
+    g_almost_empty_threshold : integer;  -- threshold for almost empty flag
+    g_almost_full_threshold  : integer   -- threshold for almost full flag
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';
+
+
+    -- write port
+    clk_wr_i : in std_logic;
+    d_i      : in std_logic_vector(g_data_width-1 downto 0);
+    we_i     : in std_logic;
+
+    wr_empty_o        : out std_logic;
+    wr_full_o         : out std_logic;
+    wr_almost_empty_o : out std_logic;
+    wr_almost_full_o  : out std_logic;
+    wr_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
+
+    -- read port
+    clk_rd_i : in  std_logic;
+    q_o      : out std_logic_vector(g_data_width-1 downto 0);
+    rd_i     : in  std_logic;
+
+    rd_empty_o        : out std_logic;
+    rd_full_o         : out std_logic;
+    rd_almost_empty_o : out std_logic;
+    rd_almost_full_o  : out std_logic;
+    rd_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
+    );
+
+end generic_async_fifo;
+
+
+architecture syn of generic_async_fifo is
+  
+  component inferred_async_fifo
+    generic (
+      g_data_width             : natural;
+      g_size                   : natural;
+      g_show_ahead             : boolean;
+      g_with_rd_empty          : boolean;
+      g_with_rd_full           : boolean;
+      g_with_rd_almost_empty   : boolean;
+      g_with_rd_almost_full    : boolean;
+      g_with_rd_count          : boolean;
+      g_with_wr_empty          : boolean;
+      g_with_wr_full           : boolean;
+      g_with_wr_almost_empty   : boolean;
+      g_with_wr_almost_full    : boolean;
+      g_with_wr_count          : boolean;
+      g_almost_empty_threshold : integer;
+      g_almost_full_threshold  : integer);
+    port (
+      rst_n_i           : in  std_logic := '1';
+      clk_wr_i          : in  std_logic;
+      d_i               : in  std_logic_vector(g_data_width-1 downto 0);
+      we_i              : in  std_logic;
+      wr_empty_o        : out std_logic;
+      wr_full_o         : out std_logic;
+      wr_almost_empty_o : out std_logic;
+      wr_almost_full_o  : out std_logic;
+      wr_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      clk_rd_i          : in  std_logic;
+      q_o               : out std_logic_vector(g_data_width-1 downto 0);
+      rd_i              : in  std_logic;
+      rd_empty_o        : out std_logic;
+      rd_full_o         : out std_logic;
+      rd_almost_empty_o : out std_logic;
+      rd_almost_full_o  : out std_logic;
+      rd_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
+  end component;
+
+
+begin  -- syn
+
+  U_Inferred_FIFO : inferred_async_fifo
+    generic map (
+      g_data_width             => g_data_width,
+      g_size                   => g_size,
+      g_show_ahead             => g_show_ahead,
+      g_with_rd_empty          => g_with_rd_empty,
+      g_with_rd_full           => g_with_rd_full,
+      g_with_rd_almost_empty   => g_with_rd_almost_empty,
+      g_with_rd_almost_full    => g_with_rd_almost_full,
+      g_with_rd_count          => g_with_rd_count,
+      g_with_wr_empty          => g_with_wr_empty,
+      g_with_wr_full           => g_with_wr_full,
+      g_with_wr_almost_empty   => g_with_wr_almost_empty,
+      g_with_wr_almost_full    => g_with_wr_almost_full,
+      g_with_wr_count          => g_with_wr_count,
+      g_almost_empty_threshold => g_almost_empty_threshold,
+      g_almost_full_threshold  => g_almost_full_threshold)
+    port map (
+      rst_n_i           => rst_n_i,
+      clk_wr_i          => clk_wr_i,
+      d_i               => d_i,
+      we_i              => we_i,
+      wr_empty_o        => wr_empty_o,
+      wr_full_o         => wr_full_o,
+      wr_almost_empty_o => wr_almost_empty_o,
+      wr_almost_full_o  => wr_almost_full_o,
+      wr_count_o        => wr_count_o,
+      clk_rd_i          => clk_rd_i,
+      q_o               => q_o,
+      rd_i              => rd_i,
+      rd_empty_o        => rd_empty_o,
+      rd_full_o         => rd_full_o,
+      rd_almost_empty_o => rd_almost_empty_o,
+      rd_almost_full_o  => rd_almost_full_o,
+      rd_count_o        => rd_count_o);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
new file mode 100644
index 000000000..fecd0882d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
@@ -0,0 +1,130 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable synchronous FIFO (Xilinx version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_sync_fifo.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2012-07-03
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Single-clock FIFO. 
+-- - configurable data width and size
+-- - "show ahead" mode
+-- - configurable full/empty/almost full/almost empty/word count signals
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.genram_pkg.all;
+
+entity generic_sync_fifo is
+
+  generic (
+    g_data_width : natural;
+    g_size       : natural;
+    g_show_ahead : boolean := false;
+
+    -- Read-side flag selection
+    g_with_empty        : boolean := true;   -- with empty flag
+    g_with_full         : boolean := true;   -- with full flag
+    g_with_almost_empty : boolean := false;
+    g_with_almost_full  : boolean := false;
+    g_with_count        : boolean := false;  -- with words counter
+
+    g_almost_empty_threshold : integer;  -- threshold for almost empty flag
+    g_almost_full_threshold  : integer;  -- threshold for almost full flag
+    g_register_flag_outputs  : boolean := true
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';
+
+    clk_i : in std_logic;
+    d_i   : in std_logic_vector(g_data_width-1 downto 0);
+    we_i  : in std_logic;
+
+    q_o  : out std_logic_vector(g_data_width-1 downto 0);
+    rd_i : in  std_logic;
+
+    empty_o        : out std_logic;
+    full_o         : out std_logic;
+    almost_empty_o : out std_logic;
+    almost_full_o  : out std_logic;
+    count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
+    );
+
+end generic_sync_fifo;
+
+architecture syn of generic_sync_fifo is
+
+  component inferred_sync_fifo
+    generic (
+      g_data_width             : natural;
+      g_size                   : natural;
+      g_show_ahead             : boolean;
+      g_with_empty             : boolean;
+      g_with_full              : boolean;
+      g_with_almost_empty      : boolean;
+      g_with_almost_full       : boolean;
+      g_with_count             : boolean;
+      g_almost_empty_threshold : integer;
+      g_almost_full_threshold  : integer;
+      g_register_flag_outputs  : boolean);
+    port (
+      rst_n_i        : in  std_logic := '1';
+      clk_i          : in  std_logic;
+      d_i            : in  std_logic_vector(g_data_width-1 downto 0);
+      we_i           : in  std_logic;
+      q_o            : out std_logic_vector(g_data_width-1 downto 0);
+      rd_i           : in  std_logic;
+      empty_o        : out std_logic;
+      full_o         : out std_logic;
+      almost_empty_o : out std_logic;
+      almost_full_o  : out std_logic;
+      count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
+  end component;
+
+begin  -- syn
+
+  U_Inferred_FIFO : inferred_sync_fifo
+      generic map (
+        g_data_width             => g_data_width,
+        g_size                   => g_size,
+        g_show_ahead             => g_show_ahead,
+        g_with_empty             => g_with_empty,
+        g_with_full              => g_with_full,
+        g_with_almost_empty      => g_with_almost_empty,
+        g_with_almost_full       => g_with_almost_full,
+        g_with_count             => g_with_count,
+        g_almost_empty_threshold => g_almost_empty_threshold,
+        g_almost_full_threshold  => g_almost_full_threshold,
+        g_register_flag_outputs  => g_register_flag_outputs)
+
+      port map (
+        rst_n_i        => rst_n_i,
+        clk_i          => clk_i,
+        d_i            => d_i,
+        we_i           => we_i,
+        q_o            => q_o,
+        rd_i           => rd_i,
+        empty_o        => empty_o,
+        full_o         => full_o,
+        almost_empty_o => almost_empty_o,
+        almost_full_o  => almost_full_o,
+        count_o        => count_o);
+
+ 
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/genram_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/genram_pkg.vhd
new file mode 100644
index 000000000..c212bbf32
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/genram_pkg.vhd
@@ -0,0 +1,262 @@
+-------------------------------------------------------------------------------
+-- Title      : Main package file
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : genram_pkg.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2013-10-30
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package genram_pkg is
+
+  function f_log2_size (A       : natural) return natural;
+  function f_gen_dummy_vec (val : std_logic; size : natural) return std_logic_vector;
+  function f_zeros (size : integer) return std_logic_vector;
+  function f_check_bounds(x : integer; minx : integer; maxx : integer) return integer;
+
+  type t_generic_ram_init is array (integer range <>, integer range <>) of std_logic;
+  type t_ram8_type  is array (integer range <>) of std_logic_vector(7 downto 0);
+  type t_ram16_type is array (integer range <>) of std_logic_vector(15 downto 0);
+  type t_ram32_type is array (integer range <>) of std_logic_vector(31 downto 0);
+  
+  -- Single-port synchronous RAM
+  component generic_spram
+    generic (
+      g_data_width               : natural;
+      g_size                     : natural;
+      g_with_byte_enable         : boolean := false;
+      g_init_file                : string  := "none";
+      g_addr_conflict_resolution : string  := "dont_care") ;
+    port (
+      rst_n_i : in  std_logic;
+      clk_i   : in  std_logic;
+      bwe_i   : in  std_logic_vector((g_data_width+7)/8-1 downto 0):= f_gen_dummy_vec('1', (g_data_width+7)/8);
+      we_i    : in  std_logic;
+      a_i     : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      d_i     : in  std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
+      q_o     : out std_logic_vector(g_data_width-1 downto 0));
+  end component;
+
+  component generic_simple_dpram
+    generic (
+      g_data_width               : natural;
+      g_size                     : natural;
+      g_with_byte_enable         : boolean := false;
+      g_addr_conflict_resolution : string  := "dont_care";
+      g_init_file                : string  := "none";
+      g_dual_clock               : boolean := true);
+    port (
+      rst_n_i : in  std_logic := '1';
+      clka_i  : in  std_logic;
+      bwea_i  : in  std_logic_vector((g_data_width+7)/8 -1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
+      wea_i   : in  std_logic;
+      aa_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      da_i    : in  std_logic_vector(g_data_width       -1 downto 0);
+      clkb_i  : in  std_logic;
+      ab_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      qb_o    : out std_logic_vector(g_data_width       -1 downto 0));
+  end component;
+
+  component generic_dpram
+    generic (
+      g_data_width               : natural;
+      g_size                     : natural;
+      g_with_byte_enable         : boolean := false;
+      g_addr_conflict_resolution : string  := "dont_care";
+      g_init_file                : string  := "none";
+      g_dual_clock               : boolean := true);
+    port (
+      rst_n_i : in  std_logic := '1';
+      clka_i  : in  std_logic;
+      bwea_i  : in  std_logic_vector((g_data_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
+      wea_i   : in  std_logic := '0';
+      aa_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      da_i    : in  std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
+      qa_o    : out std_logic_vector(g_data_width-1 downto 0);
+      clkb_i  : in  std_logic;
+      bweb_i  : in  std_logic_vector((g_data_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
+      web_i   : in  std_logic := '0';
+      ab_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      db_i    : in  std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
+      qb_o    : out std_logic_vector(g_data_width-1 downto 0));
+  end component;
+
+  component generic_dpram_mixed
+    generic (
+      g_data_a_width             : natural;
+      g_data_b_width             : natural;
+      g_size                     : natural;
+      g_addr_conflict_resolution : string := "dont_care";
+      g_init_file                : string := "none";
+      g_dual_clock               : boolean := true);
+    port (
+      rst_n_i : in  std_logic := '1';
+      clka_i  : in  std_logic;
+      bwea_i  : in  std_logic_vector((g_data_a_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_a_width+7)/8);
+      wea_i   : in  std_logic := '0';
+      aa_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      da_i    : in  std_logic_vector(g_data_a_width-1 downto 0) := f_gen_dummy_vec('0', g_data_a_width);
+      qa_o    : out std_logic_vector(g_data_a_width-1 downto 0);
+      clkb_i  : in  std_logic;
+      bweb_i  : in  std_logic_vector((g_data_b_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_b_width+7)/8);
+      web_i   : in  std_logic := '0';
+      ab_i    : in  std_logic_vector(f_log2_size(g_data_a_width*g_size/g_data_b_width)-1 downto 0);
+      db_i    : in  std_logic_vector(g_data_b_width-1 downto 0) := f_gen_dummy_vec('0', g_data_b_width);
+      qb_o    : out std_logic_vector(g_data_b_width-1 downto 0));
+  end component;
+
+  component generic_async_fifo
+    generic (
+      g_data_width             : natural;
+      g_size                   : natural;
+      g_show_ahead             : boolean := false;
+      g_with_rd_empty          : boolean := true;
+      g_with_rd_full           : boolean := false;
+      g_with_rd_almost_empty   : boolean := false;
+      g_with_rd_almost_full    : boolean := false;
+      g_with_rd_count          : boolean := false;
+      g_with_wr_empty          : boolean := false;
+      g_with_wr_full           : boolean := true;
+      g_with_wr_almost_empty   : boolean := false;
+      g_with_wr_almost_full    : boolean := false;
+      g_with_wr_count          : boolean := false;
+      g_almost_empty_threshold : integer := 0;
+      g_almost_full_threshold  : integer := 0);
+    port (
+      rst_n_i           : in  std_logic := '1';
+      clk_wr_i          : in  std_logic;
+      d_i               : in  std_logic_vector(g_data_width-1 downto 0);
+      we_i              : in  std_logic;
+      wr_empty_o        : out std_logic;
+      wr_full_o         : out std_logic;
+      wr_almost_empty_o : out std_logic;
+      wr_almost_full_o  : out std_logic;
+      wr_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      clk_rd_i          : in  std_logic;
+      q_o               : out std_logic_vector(g_data_width-1 downto 0);
+      rd_i              : in  std_logic;
+      rd_empty_o        : out std_logic;
+      rd_full_o         : out std_logic;
+      rd_almost_empty_o : out std_logic;
+      rd_almost_full_o  : out std_logic;
+      rd_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
+  end component;
+
+
+  component generic_sync_fifo
+    generic (
+      g_data_width             : natural;
+      g_size                   : natural;
+      g_show_ahead             : boolean := false;
+      g_with_empty             : boolean := true;
+      g_with_full              : boolean := true;
+      g_with_almost_empty      : boolean := false;
+      g_with_almost_full       : boolean := false;
+      g_with_count             : boolean := false;
+      g_almost_empty_threshold : integer := 0;
+      g_almost_full_threshold  : integer := 0);
+    port (
+      rst_n_i        : in  std_logic := '1';
+      clk_i          : in  std_logic;
+      d_i            : in  std_logic_vector(g_data_width-1 downto 0);
+      we_i           : in  std_logic;
+      q_o            : out std_logic_vector(g_data_width-1 downto 0);
+      rd_i           : in  std_logic;
+      empty_o        : out std_logic;
+      full_o         : out std_logic;
+      almost_empty_o : out std_logic;
+      almost_full_o  : out std_logic;
+      count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
+  end component;
+
+  component generic_shiftreg_fifo
+    generic (
+      g_data_width : integer;
+      g_size       : integer);
+    port (
+      rst_n_i       : in  std_logic := '1';
+      clk_i         : in  std_logic;
+      d_i           : in  std_logic_vector(g_data_width-1 downto 0);
+      we_i          : in  std_logic;
+      q_o           : out std_logic_vector(g_data_width-1 downto 0);
+      rd_i          : in  std_logic;
+      full_o        : out std_logic;
+      almost_full_o : out std_logic;
+      q_valid_o     : out std_logic
+      );
+  end component;
+  
+end genram_pkg;
+
+package body genram_pkg is
+
+  function f_log2_size (A : natural) return natural is
+  begin
+    for I in 1 to 64 loop               -- Works for up to 64 bits
+      if (2**I >= A) then
+        return(I);
+      end if;
+    end loop;
+    return(63);
+  end function f_log2_size;
+
+  function f_gen_dummy_vec (val : std_logic; size : natural) return std_logic_vector is
+    variable tmp : std_logic_vector(size-1 downto 0);
+  begin
+    for i in 0 to size-1 loop
+      tmp(i) := val;
+    end loop;  -- i
+    return tmp;
+  end f_gen_dummy_vec;
+
+  function f_zeros(size : integer)
+    return std_logic_vector is
+  begin
+    return std_logic_vector(to_unsigned(0, size));
+  end f_zeros;
+
+  function f_check_bounds(x : integer; minx : integer; maxx : integer) return integer is
+  begin
+    if(x < minx) then
+      return minx;
+    elsif(x > maxx) then
+      return maxx;
+    else
+      return x;
+    end if;
+  end f_check_bounds;
+
+end genram_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
new file mode 100644
index 000000000..5bb1da6d3
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
@@ -0,0 +1,251 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library std;
+use std.textio.all;
+
+library work;
+use work.genram_pkg.all;
+
+package memory_loader_pkg is
+
+  subtype t_meminit_array is t_generic_ram_init;
+
+  impure function f_load_mem_from_file
+    (file_name : in string;
+     mem_size  : in integer;
+     mem_width : in integer;
+     fail_if_notfound : boolean)
+    return t_meminit_array;
+
+  impure function f_load_mem32_from_file
+    (file_name : in string; mem_size  : in integer; fail_if_notfound : boolean)
+    return t_ram32_type;
+
+  impure function f_load_mem16_from_file
+    (file_name : in string; mem_size  : in integer; fail_if_notfound : boolean)
+    return t_ram16_type;
+
+  impure function f_load_mem8_from_file
+    (file_name : in string; mem_size  : in integer; fail_if_notfound : boolean)
+    return t_ram8_type;
+
+  impure function f_load_mem32_from_file_split
+    (file_name        : in string; mem_size : in integer;
+     fail_if_notfound : boolean; byte_idx : in integer)
+    return t_ram8_type;
+
+end memory_loader_pkg;
+
+package body memory_loader_pkg is
+
+  impure function f_load_mem_from_file
+    (file_name        : in string;
+     mem_size         : in integer;
+     mem_width        : in integer;
+     fail_if_notfound : boolean)
+    return t_meminit_array is
+
+    FILE f_in  : text;
+    variable l : line;
+    variable tmp_bv : bit_vector(mem_width-1 downto 0);
+    variable tmp_sv : std_logic_vector(mem_width-1 downto 0);
+    variable mem: t_meminit_array(0 to mem_size-1, mem_width-1 downto 0);
+    variable status   : file_open_status;
+  begin
+    if(file_name = "" or file_name = "none") then
+      mem:= (others => (others => '0'));
+      return mem;
+    end if;
+
+    file_open(status, f_in, file_name, read_mode);
+
+    if(status /= open_ok) then
+      if(fail_if_notfound) then
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity failure;
+      else
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity warning;
+      end if;
+    end if;
+
+    for I in 0 to mem_size-1 loop
+      readline (f_in, l);
+      -- read function gives us bit_vector
+      read (l, tmp_bv);
+      tmp_sv := to_stdlogicvector(tmp_bv);
+      for J in 0 to mem_width-1 loop
+        mem(i, j) := tmp_sv(j);
+      end loop;
+    end loop;
+
+    file_close(f_in);
+    return mem;
+  end f_load_mem_from_file;
+
+  -------------------------------------------------------------------
+  -- RAM initialization for most common sizes to speed-up synthesis
+  -------------------------------------------------------------------
+
+  impure function f_load_mem32_from_file
+    (file_name        : in string;
+     mem_size         : in integer;
+     fail_if_notfound : boolean)
+    return t_ram32_type is
+
+    FILE f_in  : text;
+    variable l : line;
+    variable tmp_bv : bit_vector(31 downto 0);
+    variable mem: t_ram32_type(0 to mem_size-1);
+    variable status   : file_open_status;
+  begin
+    if(file_name = "" or file_name = "none") then
+      mem:= (others => (others => '0'));
+      return mem;
+    end if;
+
+    file_open(status, f_in, file_name, read_mode);
+
+    if(status /= open_ok) then
+      if(fail_if_notfound) then
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity failure;
+      else
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity warning;
+      end if;
+    end if;
+
+    for I in 0 to mem_size-1 loop
+      readline (f_in, l);
+      -- read function gives us bit_vector
+      read (l, tmp_bv);
+      mem(I) := to_stdlogicvector(tmp_bv);
+    end loop;
+
+    file_close(f_in);
+    return mem;
+  end f_load_mem32_from_file;
+
+  -------------------------------------------------------------------
+
+  impure function f_load_mem16_from_file
+    (file_name        : in string;
+     mem_size         : in integer;
+     fail_if_notfound : boolean)
+    return t_ram16_type is
+
+    FILE f_in  : text;
+    variable l : line;
+    variable tmp_bv : bit_vector(15 downto 0);
+    variable mem: t_ram16_type(0 to mem_size-1);
+    variable status   : file_open_status;
+  begin
+    if(file_name = "" or file_name = "none") then
+      mem:= (others => (others => '0'));
+      return mem;
+    end if;
+
+    file_open(status, f_in, file_name, read_mode);
+
+    if(status /= open_ok) then
+      if(fail_if_notfound) then
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity failure;
+      else
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity warning;
+      end if;
+    end if;
+
+    for I in 0 to mem_size-1 loop
+      readline (f_in, l);
+      -- read function gives us bit_vector
+      read (l, tmp_bv);
+      mem(I) := to_stdlogicvector(tmp_bv);
+    end loop;
+
+    file_close(f_in);
+    return mem;
+  end f_load_mem16_from_file;
+
+  -------------------------------------------------------------------
+
+  impure function f_load_mem8_from_file
+    (file_name        : in string;
+     mem_size         : in integer;
+     fail_if_notfound : boolean)
+    return t_ram8_type is
+
+    FILE f_in  : text;
+    variable l : line;
+    variable tmp_bv : bit_vector(7 downto 0);
+    variable mem: t_ram8_type(0 to mem_size-1);
+    variable status   : file_open_status;
+  begin
+    if(file_name = "" or file_name = "none") then
+      mem:= (others => (others => '0'));
+      return mem;
+    end if;
+
+    file_open(status, f_in, file_name, read_mode);
+
+    if(status /= open_ok) then
+      if(fail_if_notfound) then
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity failure;
+      else
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity warning;
+      end if;
+    end if;
+
+    for I in 0 to mem_size-1 loop
+      readline (f_in, l);
+      -- read function gives us bit_vector
+      read (l, tmp_bv);
+      mem(I) := to_stdlogicvector(tmp_bv);
+    end loop;
+
+    file_close(f_in);
+    return mem;
+  end f_load_mem8_from_file;
+
+  -------------------------------------------------------------------
+  -- initialization for 32-bit RAM split into 4x 8-bit BRAM
+  -------------------------------------------------------------------
+
+  impure function f_load_mem32_from_file_split
+    (file_name        : in string;
+     mem_size         : in integer;
+     fail_if_notfound : boolean;
+     byte_idx         : in integer)
+    return t_ram8_type is
+
+    FILE f_in  : text;
+    variable l : line;
+    variable tmp_bv : bit_vector(31 downto 0);
+    variable mem: t_ram8_type(0 to mem_size-1);
+    variable status   : file_open_status;
+  begin
+    if(file_name = "" or file_name = "none") then
+      mem:= (others => (others => '0'));
+      return mem;
+    end if;
+
+    file_open(status, f_in, file_name, read_mode);
+
+    if(status /= open_ok) then
+      if(fail_if_notfound) then
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity failure;
+      else
+        report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity warning;
+      end if;
+    end if;
+
+    for I in 0 to mem_size-1 loop
+      readline (f_in, l);
+      -- read function gives us bit_vector
+      read (l, tmp_bv);
+      mem(I) := to_stdlogicvector( tmp_bv((byte_idx+1)*8-1 downto byte_idx*8) );
+    end loop;
+
+    file_close(f_in);
+    return mem;
+  end f_load_mem32_from_file_split;
+
+end memory_loader_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
new file mode 100644
index 000000000..87a4eee97
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
@@ -0,0 +1,68 @@
+library ieee;
+
+use ieee.STD_LOGIC_1164.all;
+use ieee.NUMERIC_STD.all;
+
+use work.genram_pkg.all;
+
+entity gc_shiftreg is
+  
+  generic (
+    g_size : integer);
+
+  port (
+    clk_i : in  std_logic;
+    en_i  : in  std_logic;
+    d_i   : in  std_logic;
+    q_o   : out std_logic;
+    a_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0));
+
+end gc_shiftreg;
+
+
+architecture wrapper of gc_shiftreg is
+
+  component SRLC32E
+    port (
+      Q   : out std_ulogic;
+      A   : in  std_logic_vector (4 downto 0);
+      CE  : in  std_ulogic;
+      CLK : in  std_ulogic;
+      D   : in  std_ulogic);
+  end component;
+
+  signal a  : std_logic_vector(4 downto 0);
+  signal sr : std_logic_vector(g_size-1 downto 0);
+  
+begin  -- wrapper
+
+  assert (g_size <= 32) report "gc_shiftreg[xilinx]: forced SRL32 implementation can be done only for 32-bit or smaller shift registers" severity warning;
+
+  a <= std_logic_vector(resize(unsigned(a_i), 5));
+
+  gen_srl32 : if(g_size <= 32) generate
+    U_SRLC32 : SRLC32E
+      port map (
+        Q   => q_o,
+        A   => a,
+        CE  => en_i,
+        CLK => clk_i,
+        D   => d_i);
+  end generate gen_srl32;
+
+  gen_inferred : if(g_size > 32) generate
+
+    p_srl : process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if en_i = '1' then
+          sr <= sr(sr'left - 1 downto 0) & d_i;
+        end if;
+      end if;
+    end process;
+
+    q_o <= sr(TO_INTEGER(unsigned(a_i)));
+  end generate gen_inferred;
+  
+
+end wrapper;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
new file mode 100644
index 000000000..db5a42b04
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
@@ -0,0 +1,235 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable dual-port synchronous RAM (Xilinx version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_dpram.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2012-03-16
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
+-- - configurable address and data bus width
+-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
+-- Todo:
+-- - loading initial contents from file
+-- - add support for read-first/write-first address conflict resulution (only
+--   supported by Xilinx in VHDL templates)
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-- 2012-03-13  1.1      wterpstra       Added initial value as array
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.genram_pkg.all;
+use work.memory_loader_pkg.all;
+
+entity generic_dpram is
+
+  generic (
+    -- standard parameters
+    g_data_width : natural := 32;
+    g_size       : natural := 16384;
+
+    g_with_byte_enable         : boolean := false;
+    g_addr_conflict_resolution : string  := "read_first";
+    g_init_file                : string  := "";
+    g_dual_clock               : boolean := true;
+    g_fail_if_file_not_found   : boolean := true
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';      -- synchronous reset, active LO
+
+    -- Port A
+    clka_i : in  std_logic;
+    bwea_i : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+    wea_i  : in  std_logic;
+    aa_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    da_i   : in  std_logic_vector(g_data_width-1 downto 0);
+    qa_o   : out std_logic_vector(g_data_width-1 downto 0);
+    -- Port B
+
+    clkb_i : in  std_logic;
+    bweb_i : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+    web_i  : in  std_logic;
+    ab_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    db_i   : in  std_logic_vector(g_data_width-1 downto 0);
+    qb_o   : out std_logic_vector(g_data_width-1 downto 0)
+    );
+
+end generic_dpram;
+
+
+
+architecture syn of generic_dpram is
+
+  constant c_gen_split :boolean := (g_dual_clock = false and g_data_width=32 and
+      g_with_byte_enable=true and (g_addr_conflict_resolution="dont_care" or
+      g_addr_conflict_resolution="read_first"));
+  constant c_gen_sc    :boolean := (not c_gen_split) and (not g_dual_clock);
+  constant c_gen_dc    :boolean := g_dual_clock;
+
+  component generic_dpram_split
+    generic (
+      g_size                     : natural;
+      g_addr_conflict_resolution : string  := "dont_care";
+      g_init_file                : string  := "none";
+      g_fail_if_file_not_found   : boolean := true);
+    port (
+      rst_n_i : in  std_logic := '1';
+      clk_i   : in  std_logic;
+      bwea_i : in  std_logic_vector(3 downto 0);
+      wea_i  : in  std_logic;
+      aa_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      da_i   : in  std_logic_vector(31 downto 0);
+      qa_o   : out std_logic_vector(31 downto 0);
+      bweb_i : in  std_logic_vector(3 downto 0);
+      web_i  : in  std_logic;
+      ab_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      db_i   : in  std_logic_vector(31 downto 0);
+      qb_o   : out std_logic_vector(31 downto 0));
+  end component;
+
+  component generic_dpram_sameclock
+    generic (
+      g_data_width               : natural;
+      g_size                     : natural;
+      g_with_byte_enable         : boolean;
+      g_addr_conflict_resolution : string;
+      g_init_file                : string;
+      g_fail_if_file_not_found   : boolean);
+    port (
+      rst_n_i : in  std_logic := '1';
+      clk_i   : in  std_logic;
+      bwea_i  : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+      wea_i   : in  std_logic;
+      aa_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      da_i    : in  std_logic_vector(g_data_width-1 downto 0);
+      qa_o    : out std_logic_vector(g_data_width-1 downto 0);
+      bweb_i  : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+      web_i   : in  std_logic;
+      ab_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      db_i    : in  std_logic_vector(g_data_width-1 downto 0);
+      qb_o    : out std_logic_vector(g_data_width-1 downto 0));
+  end component;  
+
+  component generic_dpram_dualclock
+    generic (
+      g_data_width               : natural;
+      g_size                     : natural;
+      g_with_byte_enable         : boolean;
+      g_addr_conflict_resolution : string;
+      g_init_file                : string;
+      g_fail_if_file_not_found   : boolean);
+    port (
+      rst_n_i : in  std_logic := '1';
+      clka_i  : in  std_logic;
+      bwea_i  : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+      wea_i   : in  std_logic;
+      aa_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      da_i    : in  std_logic_vector(g_data_width-1 downto 0);
+      qa_o    : out std_logic_vector(g_data_width-1 downto 0);
+      clkb_i  : in  std_logic;
+      bweb_i  : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+      web_i   : in  std_logic;
+      ab_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      db_i    : in  std_logic_vector(g_data_width-1 downto 0);
+      qb_o    : out std_logic_vector(g_data_width-1 downto 0));
+  end component;
+
+begin
+
+  -- generic_dpram_split is like generic_dpram_sameclock, but hardcoded to
+  -- 32-bit data width and split into 4 BRAMs, each of them 8-bit wide. It's
+  -- better for Xilinx ISE, because it's unable to infer DPRAM with byte-write
+  -- enables without using huge number of LUTs.
+  -- Since it's hardcoded to 32-bits data width, we need to keep
+  -- generic_dpram_sameclock as well. For reasons why generic_dpram_split is
+  -- hardcoded to 32-bits please check the Note in generic_dpram_split.vhd.
+  gen_splitram: if c_gen_split generate
+    U_RAM_SPLIT: generic_dpram_split
+      generic map(
+        g_size                     => g_size,
+        g_addr_conflict_resolution => g_addr_conflict_resolution,
+        g_init_file                => g_init_file,
+        g_fail_if_file_not_found   => g_fail_if_file_not_found)
+      port map(
+        rst_n_i => rst_n_i,
+        clk_i   => clka_i,
+        bwea_i  => bwea_i,
+        wea_i   => wea_i,
+        aa_i    => aa_i,
+        da_i    => da_i,
+        qa_o    => qa_o,
+        bweb_i  => bweb_i,
+        web_i   => web_i,
+        ab_i    => ab_i,
+        db_i    => db_i,
+        qb_o    => qb_o);
+  end generate gen_splitram;
+
+  gen_single_clk : if c_gen_sc generate
+  U_RAM_SC: generic_dpram_sameclock
+    generic map (
+      g_data_width               => g_data_width,
+      g_size                     => g_size,
+      g_with_byte_enable         => g_with_byte_enable,
+      g_addr_conflict_resolution => g_addr_conflict_resolution,
+      g_init_file                => g_init_file,
+      g_fail_if_file_not_found   => g_fail_if_file_not_found)
+    port map (
+      rst_n_i => rst_n_i,
+      clk_i   => clka_i,
+      bwea_i  => bwea_i,
+      wea_i   => wea_i,
+      aa_i    => aa_i,
+      da_i    => da_i,
+      qa_o    => qa_o,
+      bweb_i  => bweb_i,
+      web_i   => web_i,
+      ab_i    => ab_i,
+      db_i    => db_i,
+      qb_o    => qb_o); 
+
+    
+  end generate gen_single_clk;
+
+  gen_dual_clk : if c_gen_dc generate
+    U_RAM_DC: generic_dpram_dualclock
+      generic map (
+        g_data_width               => g_data_width,
+        g_size                     => g_size,
+        g_with_byte_enable         => g_with_byte_enable,
+        g_addr_conflict_resolution => g_addr_conflict_resolution,
+        g_init_file                => g_init_file,
+        g_fail_if_file_not_found   => g_fail_if_file_not_found)
+      port map (
+        rst_n_i => rst_n_i,
+        clka_i  => clka_i,
+        bwea_i  => bwea_i,
+        wea_i   => wea_i,
+        aa_i    => aa_i,
+        da_i    => da_i,
+        qa_o    => qa_o,
+        clkb_i  => clkb_i,
+        bweb_i  => bweb_i,
+        web_i   => web_i,
+        ab_i    => ab_i,
+        db_i    => db_i,
+        qb_o    => qb_o);
+  end generate gen_dual_clk;
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
new file mode 100644
index 000000000..9f3318d42
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
@@ -0,0 +1,268 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable dual-port synchronous RAM (Xilinx version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_dpram.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2012-03-28
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
+-- - configurable address and data bus width
+-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
+-- Todo:
+-- - loading initial contents from file
+-- - add support for read-first/write-first address conflict resulution (only
+--   supported by Xilinx in VHDL templates)
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.genram_pkg.all;
+use work.memory_loader_pkg.all;
+
+entity generic_dpram_dualclock is
+
+  generic (
+    -- standard parameters
+    g_data_width : natural := 32;
+    g_size       : natural := 16384;
+
+    g_with_byte_enable         : boolean := false;
+    g_addr_conflict_resolution : string  := "read_first";
+    g_init_file                : string  := "";
+    g_fail_if_file_not_found   : boolean := true
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';      -- synchronous reset, active LO
+
+    -- Port A
+    clka_i : in  std_logic;
+    bwea_i : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+    wea_i  : in  std_logic;
+    aa_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    da_i   : in  std_logic_vector(g_data_width-1 downto 0);
+    qa_o   : out std_logic_vector(g_data_width-1 downto 0);
+    -- Port B
+
+    clkb_i : in  std_logic;
+    bweb_i : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+    web_i  : in  std_logic;
+    ab_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    db_i   : in  std_logic_vector(g_data_width-1 downto 0);
+    qb_o   : out std_logic_vector(g_data_width-1 downto 0)
+    );
+
+end generic_dpram_dualclock;
+
+
+
+architecture syn of generic_dpram_dualclock is
+
+  constant c_num_bytes : integer := (g_data_width+7)/8;
+
+
+  type t_ram_type is array(0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
+
+  impure function f_file_to_ramtype return t_ram_type is
+    variable tmp    : t_ram_type;
+    variable n, pos : integer;
+    variable mem32  : t_ram32_type(0 to g_size-1);
+    variable mem16  : t_ram16_type(0 to g_size-1);
+    variable mem8   : t_ram8_type(0 to g_size-1);
+    variable arr    : t_meminit_array(0 to g_size-1, g_data_width-1 downto 0);
+  begin
+    -- If no file was given, there is nothing to convert, just return
+    if (g_init_file = "" or g_init_file = "none") then
+      tmp := (others=>(others=>'0'));
+      return tmp;
+    end if;
+
+    arr := f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
+    pos := 0;
+    while(pos < g_size)loop
+      n := 0;
+      -- avoid ISE loop iteration limit
+      while (pos < g_size and n < 4096) loop
+        for i in 0 to g_data_width-1 loop
+          tmp(pos)(i) := arr(pos, i);
+        end loop;  -- i
+        n   := n+1;
+        pos := pos + 1;
+      end loop;
+    end loop;
+    return tmp;
+  end f_file_to_ramtype;
+
+  function f_is_synthesis return boolean is
+  begin
+    -- synthesis translate_off
+    return false;
+    -- synthesis translate_on
+    return true;
+  end f_is_synthesis; 
+
+  shared variable ram : t_ram_type := f_file_to_ramtype;
+
+  signal s_we_a     : std_logic_vector(c_num_bytes-1 downto 0);
+  signal s_ram_in_a : std_logic_vector(g_data_width-1 downto 0);
+  signal s_we_b     : std_logic_vector(c_num_bytes-1 downto 0);
+  signal s_ram_in_b : std_logic_vector(g_data_width-1 downto 0);
+
+  signal clka_int : std_logic;
+  signal clkb_int : std_logic;
+
+  signal wea_rep, web_rep : std_logic_vector(c_num_bytes-1 downto 0);
+
+begin
+
+  wea_rep <= (others => wea_i);
+  web_rep <= (others => web_i);
+
+  s_we_a <= bwea_i and wea_rep;
+  s_we_b <= bweb_i and web_rep;
+
+  gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
+                                                                     g_addr_conflict_resolution = "dont_care")) generate
+
+
+    process (clka_i)
+    begin
+      if rising_edge(clka_i) then
+        if f_is_synthesis then
+          qa_o <= ram(to_integer(unsigned(aa_i)));
+        else
+          qa_o <= ram(to_integer(unsigned(aa_i)) mod g_size);
+        end if;
+        for i in 0 to c_num_bytes-1 loop
+          if s_we_a(i) = '1' then
+            ram(to_integer(unsigned(aa_i)))((i+1)*8-1 downto i*8) := da_i((i+1)*8-1 downto i*8);
+          end if;
+        end loop;
+      end if;
+    end process;
+
+
+    process (clkb_i)
+    begin
+      if rising_edge(clkb_i) then
+        if f_is_synthesis then
+          qb_o <= ram(to_integer(unsigned(ab_i)));
+        else
+          qb_o <= ram(to_integer(unsigned(ab_i)) mod g_size);
+        end if;
+        for i in 0 to c_num_bytes-1 loop
+          if s_we_b(i) = '1' then
+            ram(to_integer(unsigned(ab_i)))((i+1)*8-1 downto i*8)
+              := db_i((i+1)*8-1 downto i*8);
+          end if;
+        end loop;
+      end if;
+    end process;
+    
+
+
+
+  end generate gen_with_byte_enable_readfirst;
+
+
+
+  gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
+                                                                         g_addr_conflict_resolution = "dont_care")) generate
+
+    process(clka_i)
+    begin
+      if rising_edge(clka_i) then
+        qa_o <= ram(to_integer(unsigned(aa_i)));
+        if(wea_i = '1') then
+          ram(to_integer(unsigned(aa_i))) := da_i;
+        end if;
+      end if;
+    end process;
+
+
+    process(clkb_i)
+    begin
+      if rising_edge(clkb_i) then
+        qb_o <= ram(to_integer(unsigned(ab_i)));
+        if(web_i = '1') then
+          ram(to_integer(unsigned(ab_i))) := db_i;
+        end if;
+      end if;
+    end process;
+
+  end generate gen_without_byte_enable_readfirst;
+
+
+  gen_without_byte_enable_writefirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "write_first") generate
+
+    process(clka_i)
+    begin
+      if rising_edge(clka_i) then
+        if(wea_i = '1') then
+          ram(to_integer(unsigned(aa_i))) := da_i;
+          qa_o                            <= da_i;
+        else
+          qa_o <= ram(to_integer(unsigned(aa_i)));
+        end if;
+      end if;
+    end process;
+
+
+    process(clkb_i)
+    begin
+      if rising_edge(clkb_i) then
+        if(web_i = '1') then
+          ram(to_integer(unsigned(ab_i))) := db_i;
+          qb_o                            <= db_i;
+        else
+          qb_o <= ram(to_integer(unsigned(ab_i)));
+        end if;
+      end if;
+    end process;
+  end generate gen_without_byte_enable_writefirst;
+
+
+    gen_without_byte_enable_nochange : if(g_with_byte_enable = false and g_addr_conflict_resolution = "no_change") generate
+
+    process(clka_i)
+    begin
+      if rising_edge(clka_i) then
+        if(wea_i = '1') then
+          ram(to_integer(unsigned(aa_i))) := da_i;
+        else
+          qa_o <= ram(to_integer(unsigned(aa_i)));
+        end if;
+      end if;
+    end process;
+
+
+    process(clkb_i)
+    begin
+      if rising_edge(clkb_i) then
+        if(web_i = '1') then
+          ram(to_integer(unsigned(ab_i))) := db_i;
+        else
+          qb_o <= ram(to_integer(unsigned(ab_i)));
+        end if;
+      end if;
+    end process;
+  end generate gen_without_byte_enable_nochange;
+  
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
new file mode 100644
index 000000000..49151486d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
@@ -0,0 +1,304 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable dual-port synchronous RAM (Xilinx version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_dpram_sameclock.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2015-03-30
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
+-- - configurable address and data bus width
+-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
+-- Todo:
+-- - loading initial contents from file
+-- - add support for read-first/write-first address conflict resulution (only
+--   supported by Xilinx in VHDL templates)
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.genram_pkg.all;
+use work.memory_loader_pkg.all;
+
+entity generic_dpram_sameclock is
+
+  generic (
+    g_data_width : natural := 32;
+    g_size       : natural := 16384;
+
+    g_with_byte_enable         : boolean := false;
+    g_addr_conflict_resolution : string  := "read_first";
+    g_init_file                : string  := "";
+    g_fail_if_file_not_found   : boolean := true
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';      -- synchronous reset, active LO
+
+    -- Port A
+    clk_i : in std_logic;
+
+    bwea_i : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+    wea_i  : in  std_logic;
+    aa_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    da_i   : in  std_logic_vector(g_data_width-1 downto 0);
+    qa_o   : out std_logic_vector(g_data_width-1 downto 0);
+
+    -- Port B
+    bweb_i : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+    web_i  : in  std_logic;
+    ab_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    db_i   : in  std_logic_vector(g_data_width-1 downto 0);
+    qb_o   : out std_logic_vector(g_data_width-1 downto 0)
+    );
+
+end generic_dpram_sameclock;
+
+
+
+architecture syn of generic_dpram_sameclock is
+
+  constant c_num_bytes : integer := (g_data_width + 7)/8;
+
+
+  type t_ram_type is array(0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
+
+  impure function f_file_to_ramtype return t_ram_type is
+    variable tmp    : t_ram_type;
+    variable n, pos : integer;
+    variable mem32  : t_ram32_type(0 to g_size-1);
+    variable mem16  : t_ram16_type(0 to g_size-1);
+    variable mem8   : t_ram8_type(0 to g_size-1);
+    variable arr    : t_meminit_array(0 to g_size-1, g_data_width-1 downto 0);
+  begin
+    -- If no file was given, there is nothing to convert, just return
+    if (g_init_file = "" or g_init_file = "none") then
+      tmp := (others=>(others=>'0'));
+      return tmp;
+    end if;
+
+    arr := f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
+    pos := 0;
+    while(pos < g_size)loop
+      n := 0;
+      -- avoid ISE loop iteration limit
+      while (pos < g_size and n < 4096) loop
+        for i in 0 to g_data_width-1 loop
+          tmp(pos)(i) := arr(pos, i);
+        end loop;  -- i
+        n   := n+1;
+        pos := pos + 1;
+      end loop;
+    end loop;
+    return tmp;
+  end f_file_to_ramtype;
+
+  function f_is_synthesis return boolean is
+  begin
+    -- synthesis translate_off
+    return false;
+    -- synthesis translate_on
+    return true;
+  end f_is_synthesis; 
+
+
+  shared variable ram : t_ram_type := f_file_to_ramtype;
+
+  signal s_we_a     : std_logic_vector(c_num_bytes-1 downto 0);
+  signal s_ram_in_a : std_logic_vector(g_data_width-1 downto 0);
+  signal s_we_b     : std_logic_vector(c_num_bytes-1 downto 0);
+  signal s_ram_in_b : std_logic_vector(g_data_width-1 downto 0);
+
+  signal wea_rep, web_rep : std_logic_vector(c_num_bytes-1 downto 0);
+
+begin
+
+  wea_rep <= (others => wea_i);
+  web_rep <= (others => web_i);
+
+  s_we_a <= bwea_i and wea_rep;
+  s_we_b <= bweb_i and web_rep;
+
+  gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
+                                                                     g_addr_conflict_resolution = "dont_care")) generate
+
+    Port_A: process (clk_i)
+    begin
+      if rising_edge(clk_i) then
+        qa_o <= ram(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1));
+        for i in 0 to c_num_bytes-1 loop
+          if s_we_a(i) = '1' then
+            ram(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1))((i+1)*8-1 downto i*8) := da_i((i+1)*8-1 downto i*8);
+          end if;
+        end loop;
+      end if;
+    end process;
+
+    Port_B: process (clk_i)
+    begin
+      if rising_edge(clk_i) then
+        qb_o <= ram(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1));
+        for i in 0 to c_num_bytes-1 loop
+          if(s_we_b(i) = '1') then
+            ram(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1))((i+1)*8-1 downto i*8) := db_i((i+1)*8-1 downto i*8);
+          end if;
+        end loop;
+      end if;
+    end process;
+
+  end generate gen_with_byte_enable_readfirst;
+
+
+
+  gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
+                                                                         g_addr_conflict_resolution = "dont_care")) generate
+
+    Port_A: process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if f_is_synthesis then
+          qa_o <= ram(to_integer(unsigned(aa_i)));
+        else
+          qa_o <= ram(to_integer(unsigned(aa_i)) mod g_size);
+        end if;
+        if(wea_i = '1') then
+          ram(to_integer(unsigned(aa_i))) := da_i;
+        end if;
+      end if;
+    end process;
+
+    Port_B: process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if f_is_synthesis then
+          qb_o <= ram(to_integer(unsigned(ab_i)));
+        else
+          qb_o <= ram(to_integer(unsigned(ab_i)) mod g_size);
+        end if;
+        if(web_i = '1') then
+          ram(to_integer(unsigned(ab_i))) := db_i;
+        end if;
+      end if;
+    end process;
+  end generate gen_without_byte_enable_readfirst;
+
+  gen_without_byte_enable_writefirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "write_first") generate
+
+    Port_A: process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if(wea_i = '1') then
+          ram(to_integer(unsigned(aa_i))) := da_i;
+          qa_o                            <= da_i;
+        else
+          if f_is_synthesis then
+            qa_o <= ram(to_integer(unsigned(aa_i)));
+          else
+            qa_o <= ram(to_integer(unsigned(aa_i)) mod g_size);
+          end if;
+        end if;
+      end if;
+    end process;
+
+    Port_B: process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if(web_i = '1') then
+          ram(to_integer(unsigned(ab_i))) := db_i;
+          qb_o                            <= db_i;
+        else
+          if f_is_synthesis then
+            qb_o <= ram(to_integer(unsigned(ab_i)));
+          else
+            qb_o <= ram(to_integer(unsigned(ab_i)) mod g_size);
+          end if;
+        end if;
+      end if;
+    end process;
+
+  end generate gen_without_byte_enable_writefirst;
+
+
+  gen_without_byte_enable_nochange : if(g_with_byte_enable = false and g_addr_conflict_resolution = "no_change") generate
+
+    Port_A: process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if(wea_i = '1') then
+          ram(to_integer(unsigned(aa_i))) := da_i;
+        else
+          if f_is_synthesis then
+            qa_o <= ram(to_integer(unsigned(aa_i)));
+          else
+            qa_o <= ram(to_integer(unsigned(aa_i)) mod g_size);
+          end if;
+        end if;
+      end if;
+    end process;
+
+    Port_B: process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if(web_i = '1') then
+          ram(to_integer(unsigned(ab_i))) := db_i;
+        else
+          if f_is_synthesis then
+            qb_o <= ram(to_integer(unsigned(ab_i)));
+          else
+            qb_o <= ram(to_integer(unsigned(ab_i)) mod g_size);
+          end if;
+        end if;
+      end if;
+    end process;
+
+    
+  end generate gen_without_byte_enable_nochange;
+
+   gen_with_byte_enable_writefirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "write_first")) generate
+
+    Port_A: process (clk_i)
+    begin
+      if rising_edge(clk_i) then
+        for i in 0 to c_num_bytes-1 loop
+          if s_we_a(i) = '1' then
+            ram(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1))((i+1)*8-1 downto i*8) := da_i((i+1)*8-1 downto i*8);
+            qa_o((i+1)*8-1 downto i*8)                                                         <= da_i((i+1)*8-1 downto i*8);
+          else
+            qa_o((i+1)*8-1 downto i*8) <= ram(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1))((i+1)*8-1 downto i*8);
+          end if;
+        end loop;
+      end if;
+    end process;
+
+    Port_B: process (clk_i)
+    begin
+      if rising_edge(clk_i) then
+        for i in 0 to c_num_bytes-1 loop
+          if s_we_b(i) = '1' then
+            ram(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1))((i+1)*8-1 downto i*8) := db_i((i+1)*8-1 downto i*8);
+            qb_o((i+1)*8-1 downto i*8)                                                         <= db_i((i+1)*8-1 downto i*8);
+          else
+            qb_o((i+1)*8-1 downto i*8) <= ram(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1))((i+1)*8-1 downto i*8);
+          end if;
+        end loop;
+      end if;
+    end process;
+
+  end generate gen_with_byte_enable_writefirst;
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd
new file mode 100644
index 000000000..b6d692bb8
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd
@@ -0,0 +1,233 @@
+-------------------------------------------------------------------------------
+-- Title      : Dual-port synchronous RAM with byte-write for Xilinx
+-------------------------------------------------------------------------------
+-- File       : generic_dpram_split.vhd
+-- Author     : Grzegorz Daniluk
+-- Company    : CERN BE-CO-HT
+-- Created    : 2017-02-13
+-- Last update: 2017-02-13
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: 
+-- This module is 32-bit RAM with byte-write enables. It was created for Xilinx
+-- FPGAs, since Xilinx ISE is unable to infer dual-port block-RAM with
+-- byte-writes (e.g. based on generic_dpram_sameclock.vhd module). When
+-- synthesizing generic_dpram_sameclock with g_with_byte_enable, ISE uses a lot
+-- of LUTs to get the byte-write behavior (instead of using the features of BRAM
+-- blocks).
+--
+-- Note:
+-- This module is hardcoded to 32-bits and 4 ram modules (ram0-3). It would be
+-- much cleaner to have a generic code and using ram(0 to g_data_width/8-1).
+-- However, it looks that ISE is not able to initialize 3-d array that would be
+-- needed in this case.
+-- I.e. this works:
+-- shared variable ram0 : t_split_ram := f_file_to_ramtype(0);
+-- shared variable ram1 : t_split_ram := f_file_to_ramtype(1);
+-- shared variable ram2 : t_split_ram := f_file_to_ramtype(2);
+-- shared variable ram3 : t_split_ram := f_file_to_ramtype(3);
+--
+-- but this doesn't:
+-- type t_split_ram_array is array(0 to 3) of t_split_ram;
+-- shared variable ram : t_split_ram_array := (f_file_to_ramtype(0),
+-- f_file_to_ramtype(1),f_file_to_ramtype(2),
+-- f_file_to_ramtype(3));
+-- 
+-- By "doesn't work" I mean that ISE does not fail during the synthesis, but RAM
+-- does not get initialized.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.genram_pkg.all;
+use work.memory_loader_pkg.all;
+
+entity generic_dpram_split is
+  generic (
+    g_size                     : natural := 16384;
+    g_addr_conflict_resolution : string  := "read_first";
+    g_init_file                : string  := "";
+    g_fail_if_file_not_found   : boolean := true);
+  port (
+    rst_n_i : in std_logic := '1';
+    clk_i   : in std_logic;
+
+    -- Port A
+    bwea_i : in  std_logic_vector(3 downto 0);
+    wea_i  : in  std_logic;
+    aa_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    da_i   : in  std_logic_vector(31 downto 0);
+    qa_o   : out std_logic_vector(31 downto 0);
+
+    -- Port B
+    bweb_i : in  std_logic_vector(3 downto 0);
+    web_i  : in  std_logic;
+    ab_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    db_i   : in  std_logic_vector(31 downto 0);
+    qb_o   : out std_logic_vector(31 downto 0));
+end generic_dpram_split;
+
+architecture syn of generic_dpram_split is
+
+  constant c_data_width : integer := 32;
+  constant c_num_bytes  : integer := (c_data_width+7)/8;
+
+  type t_split_ram is array(0 to g_size-1) of std_logic_vector(7 downto 0);
+
+  impure function f_file_to_ramtype(idx : integer) return t_split_ram is
+    variable tmp    : t_split_ram;
+    variable mem8   : t_ram8_type(0 to g_size-1);
+  begin
+    -- If no file was given, there is nothing to convert, just return
+    if (g_init_file = "" or g_init_file = "none") then
+      tmp := (others=>(others=>'0'));
+      return tmp;
+    end if;
+
+    mem8 := f_load_mem32_from_file_split(g_init_file, g_size, g_fail_if_file_not_found, idx);
+    return t_split_ram(mem8);
+  end f_file_to_ramtype;
+
+  impure function f_file_contents return t_meminit_array is
+  begin
+    return f_load_mem_from_file(g_init_file, g_size, c_data_width, g_fail_if_file_not_found);
+  end f_file_contents;
+
+  shared variable ram0 : t_split_ram := f_file_to_ramtype(0);
+  shared variable ram1 : t_split_ram := f_file_to_ramtype(1);
+  shared variable ram2 : t_split_ram := f_file_to_ramtype(2);
+  shared variable ram3 : t_split_ram := f_file_to_ramtype(3);
+
+  signal s_we_a  : std_logic_vector(c_num_bytes-1 downto 0);
+  signal s_we_b  : std_logic_vector(c_num_bytes-1 downto 0);
+  signal wea_rep : std_logic_vector(c_num_bytes-1 downto 0);
+  signal web_rep : std_logic_vector(c_num_bytes-1 downto 0);
+
+begin
+
+  assert (g_addr_conflict_resolution = "read_first" or g_addr_conflict_resolution = "dont_care") 
+  report "generic_dpram_split: only read_first and dont_care supported for now" severity failure;
+
+  -- combine byte-write enable with write signals
+  wea_rep <= (others => wea_i);
+  web_rep <= (others => web_i);
+  s_we_a <= bwea_i and wea_rep;
+  s_we_b <= bweb_i and web_rep;
+
+  --------------------------------------------------
+  -- yes, I know this is 4 times exactly the same code for ram0,1,2,3,
+  -- but ISE fails to initialize BRAM when ram is an array (check Note
+  -- in the header of this file).
+  GEN_RAM0_Port_A: process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      qa_o(7 downto 0) <= ram0(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1));
+      if s_we_a(0) = '1' then
+        ram0(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1)) := da_i(7 downto 0);
+      end if;
+    end if;
+  end process;
+
+  GEN_RAM0_Port_B: process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      qb_o(7 downto 0) <= ram0(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1));
+      if s_we_b(0) = '1' then
+        ram0(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1)) := db_i(7 downto 0);
+      end if;
+    end if;
+  end process;
+
+  --------------------------------------------------
+
+  GEN_RAM1_Port_A: process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      qa_o(15 downto 8) <= ram1(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1));
+      if s_we_a(1) = '1' then
+        ram1(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1)) := da_i(15 downto 8);
+      end if;
+    end if;
+  end process;
+
+  GEN_RAM1_Port_B: process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      qb_o(15 downto 8) <= ram1(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1));
+      if s_we_b(1) = '1' then
+        ram1(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1)) := db_i(15 downto 8);
+      end if;
+    end if;
+  end process;
+
+  --------------------------------------------------
+
+  GEN_RAM2_Port_A: process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      qa_o(23 downto 16) <= ram2(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1));
+      if s_we_a(2) = '1' then
+        ram2(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1)) := da_i(23 downto 16);
+      end if;
+    end if;
+  end process;
+
+  GEN_RAM2_Port_B: process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      qb_o(23 downto 16) <= ram2(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1));
+      if s_we_b(2) = '1' then
+        ram2(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1)) := db_i(23 downto 16);
+      end if;
+    end if;
+  end process;
+
+  --------------------------------------------------
+
+  GEN_RAM3_Port_A: process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      qa_o(31 downto 24) <= ram3(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1));
+      if s_we_a(3) = '1' then
+        ram3(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1)) := da_i(31 downto 24);
+      end if;
+    end if;
+  end process;
+
+  GEN_RAM3_Port_B: process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      qb_o(31 downto 24) <= ram3(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1));
+      if s_we_b(3) = '1' then
+        ram3(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1)) := db_i(31 downto 24);
+      end if;
+    end if;
+  end process;
+
+  --------------------------------------------------
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
new file mode 100644
index 000000000..5eb14729a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
@@ -0,0 +1,100 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable dual-port synchronous RAM (Xilinx version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_simple_dpram.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2013-03-04
+-- Last update: 2013-10-30
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
+-- - configurable address and data bus width
+-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
+-- Todo:
+-- - loading initial contents from file
+-- - add support for read-first/write-first address conflict resulution (only
+--   supported by Xilinx in VHDL templates)
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-03-04  1.0      wterpstra       Initial version: wrapper to generic_dpram
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.genram_pkg.all;
+use work.memory_loader_pkg.all;
+
+entity generic_simple_dpram is
+
+  generic (
+    -- standard parameters
+    g_data_width : natural := 32;
+    g_size       : natural := 16384;
+
+    g_with_byte_enable         : boolean := false;
+    g_addr_conflict_resolution : string  := "read_first";
+    g_init_file                : string  := "";
+    g_dual_clock               : boolean := true;
+    g_fail_if_file_not_found   : boolean := true
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';      -- synchronous reset, active LO
+
+    -- Port A
+    clka_i : in  std_logic;
+    bwea_i : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+    wea_i  : in  std_logic;
+    aa_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    da_i   : in  std_logic_vector(g_data_width-1 downto 0);
+    
+    -- Port B
+    clkb_i : in  std_logic;
+    ab_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    qb_o   : out std_logic_vector(g_data_width-1 downto 0)
+    );
+
+end generic_simple_dpram;
+
+
+
+architecture syn of generic_simple_dpram is
+
+begin
+
+  -- Works well enough until a Xilinx guru can optimize it.
+  true_dp : generic_dpram
+    generic map(
+      g_data_width               => g_data_width,
+      g_size                     => g_size,
+      g_with_byte_enable         => g_with_byte_enable,
+      g_addr_conflict_resolution => g_addr_conflict_resolution,
+      g_init_file                => g_init_file,
+      g_dual_clock               => g_dual_clock)
+    port map(
+      rst_n_i => rst_n_i,
+      clka_i  => clka_i,
+      bwea_i  => bwea_i,
+      wea_i   => wea_i,
+      aa_i    => aa_i,
+      da_i    => da_i,
+      qa_o    => open,
+      clkb_i  => clkb_i,
+      bweb_i  => f_zeros((g_data_width+7)/8),
+      web_i   => '0',
+      ab_i    => ab_i,
+      db_i    => f_zeros(g_data_width),
+      qb_o    => qb_o);
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
new file mode 100644
index 000000000..cde1f31bb
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
@@ -0,0 +1,253 @@
+-------------------------------------------------------------------------------
+-- Title      : AXI4Lite-to-WB bridge package
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : axi4_pkg.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.wishbone_pkg.all;
+
+package axi4_pkg is
+
+  -- AXI4-Full interface, master output ports, 32 bits
+  type t_axi4_full_master_out_32 is record
+    ARVALID : std_logic;
+    AWVALID : std_logic;
+    BREADY  : std_logic;
+    RREADY  : std_logic;
+    WLAST   : std_logic;
+    WVALID  : std_logic;
+    ARID    : std_logic_vector (11 downto 0);
+    AWID    : std_logic_vector (11 downto 0);
+    WID     : std_logic_vector (11 downto 0);
+    ARBURST : std_logic_vector (1 downto 0);
+    ARLOCK  : std_logic_vector (1 downto 0);
+    ARSIZE  : std_logic_vector (2 downto 0);
+    AWBURST : std_logic_vector (1 downto 0);
+    AWLOCK  : std_logic_vector (1 downto 0);
+    AWSIZE  : std_logic_vector (2 downto 0);
+    ARPROT  : std_logic_vector (2 downto 0);
+    AWPROT  : std_logic_vector (2 downto 0);
+    ARADDR  : std_logic_vector (31 downto 0);
+    AWADDR  : std_logic_vector (31 downto 0);
+    WDATA   : std_logic_vector (31 downto 0);
+    ARCACHE : std_logic_vector (3 downto 0);
+    ARLEN   : std_logic_vector (3 downto 0);
+    ARQOS   : std_logic_vector (3 downto 0);
+    AWCACHE : std_logic_vector (3 downto 0);
+    AWLEN   : std_logic_vector (3 downto 0);
+    AWQOS   : std_logic_vector (3 downto 0);
+    WSTRB   : std_logic_vector (3 downto 0);
+  end record;
+
+  -- AXI4-Full interface, master input ports, 32 bits
+  type t_axi4_full_master_in_32 is record
+    ARREADY : std_logic;
+    AWREADY : std_logic;
+    BVALID  : std_logic;
+    RLAST   : std_logic;
+    RVALID  : std_logic;
+    WREADY  : std_logic;
+    BID     : std_logic_vector (11 downto 0);
+    RID     : std_logic_vector (11 downto 0);
+    BRESP   : std_logic_vector (1 downto 0);
+    RRESP   : std_logic_vector (1 downto 0);
+    RDATA   : std_logic_vector (31 downto 0);
+  end record;
+
+  -- AXI4-Lite interface, master output ports, 32 bits
+  type t_axi4_lite_master_out_32 is record
+    ARVALID : std_logic;
+    AWVALID : std_logic;
+    BREADY  : std_logic;
+    RREADY  : std_logic;
+    WLAST   : std_logic;
+    WVALID  : std_logic;
+    ARADDR  : std_logic_vector (31 downto 0);
+    AWADDR  : std_logic_vector (31 downto 0);
+    WDATA   : std_logic_vector (31 downto 0);
+    WSTRB   : std_logic_vector (3 downto 0);
+  end record;
+
+  -- AXI4-Lite interface, master input ports, 32 bits
+  type t_axi4_lite_master_in_32 is record
+    ARREADY : std_logic;
+    AWREADY : std_logic;
+    BVALID  : std_logic;
+    RLAST   : std_logic;
+    RVALID  : std_logic;
+    WREADY  : std_logic;
+    BRESP   : std_logic_vector (1 downto 0);
+    RRESP   : std_logic_vector (1 downto 0);
+    RDATA   : std_logic_vector (31 downto 0);
+  end record;
+
+  constant c_axi4_lite_default_master_in_32 : t_axi4_lite_master_in_32 :=
+    (
+      AWREADY => '0',
+      ARREADY => '0',
+      BVALID  => '0',
+      RLAST   => '0',
+      RVALID  => '0',
+      WREADY  => '0',
+      BRESP   => "00",
+      RRESP   => "00",
+      RDATA   => (others => '0')
+      );
+
+
+  constant c_axi4_lite_default_master_out_32 : t_axi4_lite_master_out_32 :=
+    (
+      ARVALID => '0',
+      AWVALID => '0',
+      BREADY  => '0',
+      RREADY  => '0',
+      WLAST   => '0',
+      WVALID  => '0',
+      ARADDR  => (others => '0'),
+      AWADDR  => (others => '0'),
+      WDATA   => (others => '0'),
+      WSTRB   => (others => '0')
+      );
+
+
+
+  subtype t_axi4_lite_slave_in_32 is t_axi4_lite_master_out_32;
+  subtype t_axi4_lite_slave_out_32 is t_axi4_lite_master_in_32;
+
+  constant c_AXI4_RESP_OKAY   : std_logic_vector(1 downto 0) := "00";
+  constant c_AXI4_RESP_EXOKAY : std_logic_vector(1 downto 0) := "01";
+  constant c_AXI4_RESP_SLVERR : std_logic_vector(1 downto 0) := "10";
+  constant c_AXI4_RESP_DECERR : std_logic_vector(1 downto 0) := "11";
+
+    function f_axi4_full_to_lite (
+    f : t_axi4_full_master_out_32
+    )  return t_axi4_lite_master_out_32;
+  
+  function f_axi4_lite_to_full (
+    l : t_axi4_lite_master_in_32
+    )  return t_axi4_full_master_in_32;
+
+  component xwb_axi4lite_bridge is
+    port (
+      clk_sys_i    : in  std_logic;
+      rst_n_i      : in  std_logic;
+      axi4_slave_i : in  t_axi4_lite_slave_in_32;
+      axi4_slave_o : out t_axi4_lite_slave_out_32;
+      wb_master_o  : out t_wishbone_master_out;
+      wb_master_i  : in  t_wishbone_master_in);
+  end component xwb_axi4lite_bridge;
+
+  component wb_axi4lite_bridge is
+    port (
+      clk_sys_i : in std_logic;
+      rst_n_i   : in std_logic;
+  
+      ARVALID : in  std_logic;
+      AWVALID : in  std_logic;
+      BREADY  : in  std_logic;
+      RREADY  : in  std_logic;
+      WLAST   : in  std_logic;
+      WVALID  : in  std_logic;
+      ARADDR  : in  std_logic_vector (31 downto 0);
+      AWADDR  : in  std_logic_vector (31 downto 0);
+      WDATA   : in  std_logic_vector (31 downto 0);
+      WSTRB   : in  std_logic_vector (3 downto 0);
+      ARREADY : out std_logic;
+      AWREADY : out std_logic;
+      BVALID  : out std_logic;
+      RLAST   : out std_logic;
+      RVALID  : out std_logic;
+      WREADY  : out std_logic;
+      BRESP   : out std_logic_vector (1 downto 0);
+      RRESP   : out std_logic_vector (1 downto 0);
+      RDATA   : out std_logic_vector (31 downto 0);
+  
+      wb_adr : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+      wb_dat_m2s : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_sel : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+      wb_cyc : out std_logic;
+      wb_stb : out std_logic;
+      wb_we  : out std_logic;
+  
+      wb_dat_s2m   : in std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_err   : in std_logic := '0';
+      wb_rty   : in std_logic := '0';
+      wb_ack   : in std_logic;
+      wb_stall : in std_logic
+      );
+  end component;
+  
+end package;
+
+package body axi4_pkg is
+
+    function f_axi4_full_to_lite (
+    f : t_axi4_full_master_out_32
+    )  return t_axi4_lite_master_out_32 is
+    variable l : t_axi4_lite_master_out_32;
+  begin
+
+    l.ARVALID := f.ARVALID;
+    l.AWVALID := f.AWVALID;
+    l.BREADY  := f.BREADY;
+    l.RREADY  := f.RREADY;
+    l.WLAST   := f.WLAST;
+    l.WVALID  := f.WVALID;
+    l.ARADDR  := f.ARADDR;
+    l.AWADDR  := f.AWADDR;
+    l.WDATA   := f.WDATA;
+    l.WSTRB   := f.WSTRB;
+
+    return l;
+    
+  end f_axi4_full_to_lite;
+
+  function f_axi4_lite_to_full (
+    l : t_axi4_lite_master_in_32
+    )  return t_axi4_full_master_in_32 is
+    variable f : t_axi4_full_master_in_32;
+  begin
+    f.ARREADY := l.ARREADY;
+    f.AWREADY := l.AWREADY;
+    f.BVALID  := l.BVALID;
+    f.RLAST   := l.RLAST;
+    f.RVALID  := l.RVALID;
+    f.WREADY  := l.WREADY;
+    f.BID     := (others => '0');
+    f.RID     := (others => '0');
+    f.BRESP   := l.BRESP;
+    f.RRESP   := l.RRESP;
+    f.RDATA   := l.RDATA;
+
+    return f;
+    
+  end f_axi4_lite_to_full;
+
+
+end package body;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
new file mode 100644
index 000000000..b8e63eca3
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
@@ -0,0 +1,131 @@
+-------------------------------------------------------------------------------
+-- Title      : AXI4Lite-to-WB bridge
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wb_axi4lite_bridge.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.axi4_pkg.all;
+use work.wishbone_pkg.all;
+
+entity wb_axi4lite_bridge is
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    ARVALID : in  std_logic;
+    AWVALID : in  std_logic;
+    BREADY  : in  std_logic;
+    RREADY  : in  std_logic;
+    WLAST   : in  std_logic;
+    WVALID  : in  std_logic;
+    ARADDR  : in  std_logic_vector (31 downto 0);
+    AWADDR  : in  std_logic_vector (31 downto 0);
+    WDATA   : in  std_logic_vector (31 downto 0);
+    WSTRB   : in  std_logic_vector (3 downto 0);
+    ARREADY : out std_logic;
+    AWREADY : out std_logic;
+    BVALID  : out std_logic;
+    RLAST   : out std_logic;
+    RVALID  : out std_logic;
+    WREADY  : out std_logic;
+    BRESP   : out std_logic_vector (1 downto 0);
+    RRESP   : out std_logic_vector (1 downto 0);
+    RDATA   : out std_logic_vector (31 downto 0);
+
+    wb_adr : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+    wb_dat_m2s : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_sel : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+    wb_cyc : out std_logic;
+    wb_stb : out std_logic;
+    wb_we  : out std_logic;
+
+    wb_dat_s2m   : in std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_err   : in std_logic := '0';
+    wb_rty   : in std_logic := '0';
+    wb_ack   : in std_logic;
+    wb_stall : in std_logic
+    );
+
+end wb_axi4lite_bridge;
+
+architecture rtl of wb_axi4lite_bridge is
+
+  signal axi_in  : t_axi4_lite_master_out_32;
+  signal axi_out : t_axi4_lite_master_in_32;
+  signal wb_in   : t_wishbone_master_in;
+  signal wb_out  : t_wishbone_master_out;
+  
+begin
+
+  axi_in.ARVALID  <= ARVALID;
+  axi_in.AWVALID <= AWVALID;
+  axi_in.BREADY  <= BREADY;
+  axi_in.RREADY  <= RREADY;
+  axi_in.WLAST   <= WLAST;
+  axi_in.WVALID  <= WVALID;
+  axi_in.ARADDR  <= ARADDR;
+  axi_in.AWADDR  <= AWADDR;
+  axi_in.WDATA   <= WDATA;
+  axi_in.WSTRB   <= WSTRB;
+  ARREADY         <= axi_out.ARREADY;
+  AWREADY         <= axi_out.AWREADY;
+  BVALID          <= axi_out.BVALID;
+  RLAST           <= axi_out.RLAST;
+  RVALID          <= axi_out.RVALID;
+  WREADY          <= axi_out.WREADY;
+  BRESP           <= axi_out.BRESP;
+  RRESP           <= axi_out.RRESP;
+  RDATA           <= axi_out.RDATA;
+
+  wb_adr <= wb_out.adr;
+  wb_dat_m2s <= wb_out.dat;
+  wb_stb <= wb_out.stb;
+  wb_sel <= wb_out.sel;
+  wb_cyc <= wb_out.cyc;
+  wb_we <= wb_out.we;
+
+  wb_in.err <= wb_err;
+  wb_in.rty <= wb_rty;
+  wb_in.ack <= wb_ack;
+  wb_in.int <= '0';
+  wb_in.stall <= wb_stall;
+  wb_in.dat <= wb_dat_s2m;
+
+  U_Wrapped_Bridge : xwb_axi4lite_bridge
+    port map (
+      clk_sys_i    => clk_sys_i,
+      rst_n_i      => rst_n_i,
+      axi4_slave_i => axi_in,
+      axi4_slave_o => axi_out,
+      wb_master_o  => wb_out,
+      wb_master_i  => wb_in);
+  
+end rtl;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
new file mode 100644
index 000000000..51838931a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
@@ -0,0 +1,196 @@
+-------------------------------------------------------------------------------
+-- Title      : AXI4Lite-to-WB bridge wrapper
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : xwb_axi4lite_bridge.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.axi4_pkg.all;
+use work.wishbone_pkg.all;
+
+entity xwb_axi4lite_bridge is
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    axi4_slave_i : in  t_axi4_lite_slave_in_32;
+    axi4_slave_o : out t_axi4_lite_slave_out_32;
+
+    wb_master_o : out t_wishbone_master_out;
+    wb_master_i : in  t_wishbone_master_in
+
+    );
+
+end xwb_axi4lite_bridge;
+
+architecture rtl of xwb_axi4lite_bridge is
+
+  constant c_timeout : integer := 256;
+
+  type t_state is
+    (IDLE, ISSUE_WRITE, ISSUE_READ, COMPLETE_WRITE, COMPLETE_READ, WAIT_ACK_READ, WAIT_ACK_WRITE, RESPONSE_READ, RESPONSE_WRITE);
+
+  signal state : t_state;
+
+  signal count : unsigned(10 downto 0);
+  
+begin
+
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        axi4_slave_o    <= c_axi4_lite_default_master_in_32;
+        wb_master_o.cyc <= '0';
+        state           <= IDLE;
+      else
+        case state is
+          when IDLE =>
+            wb_master_o.cyc      <= '0';
+            axi4_slave_o.ARREADY <= '1';
+            axi4_slave_o.AWREADY <= '1';
+            axi4_slave_o.WREADY  <= '0';
+            axi4_slave_o.BVALID  <= '0';
+            axi4_slave_o.BRESP   <= (others => 'X');
+            axi4_slave_o.RDATA  <= (others => 'X');
+            axi4_slave_o.RRESP  <= (others => 'X');
+            axi4_slave_o.RVALID <= '0';
+            axi4_slave_o.RLAST <= '0';
+            
+            if(axi4_slave_i.AWVALID = '1') then
+              state           <= ISSUE_WRITE;
+              wb_master_o.adr <= axi4_slave_i.AWADDR;
+            elsif (axi4_slave_i.ARVALID = '1') then
+              state           <= ISSUE_READ;
+              wb_master_o.adr <= axi4_slave_i.ARADDR;
+            end if;
+
+          when ISSUE_WRITE =>
+            axi4_slave_o.WREADY <= '1';
+
+            wb_master_o.cyc <= '1';
+            wb_master_o.we  <= '1';
+
+            if(axi4_slave_i.WVALID = '1') then
+              wb_master_o.stb <= '1';
+              wb_master_o.sel <= axi4_slave_i.WSTRB;
+              wb_master_o.dat <= axi4_slave_i.WDATA;
+              state           <= COMPLETE_WRITE;
+            end if;
+
+          when ISSUE_READ =>
+
+            wb_master_o.cyc <= '1';
+            wb_master_o.stb <= '1';
+            wb_master_o.we  <= '0';
+            axi4_slave_o.RVALID <= '0';
+            axi4_slave_o.RLAST <= '0';
+            state <= COMPLETE_READ;
+
+          when COMPLETE_READ =>
+            if(wb_master_i.stall = '0') then
+              wb_master_o.stb <= '0';
+              if(wb_master_i.ack = '1') then
+                state <= IDLE;
+                axi4_slave_o.RRESP <= c_AXI4_RESP_EXOKAY;
+                axi4_slave_o.RDATA <= wb_master_i.dat;
+                axi4_slave_o.RVALID <= '1';
+                axi4_slave_o.RLAST <= '1';
+                wb_master_o.cyc    <= '0';
+              else
+                state <= WAIT_ACK_READ;
+                count <= (others => '0');
+              end if;
+            end if;
+
+            
+          when COMPLETE_WRITE =>
+            if(wb_master_i.stall = '0') then
+              wb_master_o.stb <= '0';
+              if(wb_master_i.ack = '1') then
+                state <= RESPONSE_WRITE;
+                axi4_slave_o.BRESP <= c_AXI4_RESP_EXOKAY;
+                wb_master_o.cyc    <= '0';
+              else
+                state <= WAIT_ACK_WRITE;
+                count <= (others => '0');
+              end if;
+            end if;
+
+
+          when WAIT_ACK_WRITE =>
+            if(wb_master_i.ack = '1') then
+              state              <= RESPONSE_WRITE;
+              axi4_slave_o.BRESP <= c_AXI4_RESP_EXOKAY;
+              wb_master_o.cyc    <= '0';
+            elsif count = c_timeout then
+              state              <= RESPONSE_WRITE;
+              axi4_slave_o.BRESP <= c_AXI4_RESP_SLVERR;
+              wb_master_o.cyc    <= '0';
+            end if;
+            count <= count + 1;
+
+          when WAIT_ACK_READ =>
+            if(wb_master_i.ack = '1') then
+              state              <= IDLE;
+              axi4_slave_o.RRESP <= c_AXI4_RESP_EXOKAY;
+              axi4_slave_o.RVALID <= '1';
+              axi4_slave_o.RLAST <= '1';
+              axi4_slave_o.RDATA <= wb_master_i.dat;
+              wb_master_o.cyc    <= '0';
+            elsif count = c_timeout then
+              state              <= IDLE;
+              axi4_slave_o.RRESP <= c_AXI4_RESP_SLVERR;
+              axi4_slave_o.RVALID <= '1';
+              axi4_slave_o.RLAST <= '1';
+              axi4_slave_o.RDATA <= (others => 'X');
+              wb_master_o.cyc    <= '0';
+            end if;
+            count <= count + 1;
+
+            
+          when RESPONSE_WRITE =>
+            if (axi4_slave_i.BREADY = '1') then
+              axi4_slave_o.BVALID <= '1';
+              state               <= IDLE;
+            end if;
+
+          when RESPONSE_READ => null;
+            
+            
+        end case;
+
+
+
+      end if;
+    end if;
+  end process;
+
+end rtl;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
new file mode 100644
index 000000000..9ca049b71
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
@@ -0,0 +1,160 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wishbone_pkg.all;
+
+entity sdb_rom is
+  generic(
+    g_layout   : t_sdb_record_array;
+    g_masters  : natural;
+    g_bus_end  : unsigned(63 downto 0);
+    g_sdb_name : string := "WB4-Crossbar-GSI   ");
+  port(
+    clk_sys_i  : in  std_logic;
+    master_i   : in  std_logic_vector(g_masters-1 downto 0);
+    slave_i    : in  t_wishbone_slave_in;
+    slave_o    : out t_wishbone_slave_out);
+end sdb_rom;
+
+architecture rtl of sdb_rom is
+  alias c_layout : t_sdb_record_array(g_layout'length downto 1) is g_layout;
+
+  -- The ROM must describe all slaves, the crossbar itself and the optional information records
+  constant c_used_entries   : natural := c_layout'high + 1;
+  constant c_rom_entries    : natural := 2**f_ceil_log2(c_used_entries); -- next power of 2
+  constant c_sdb_words      : natural := c_sdb_device_length / c_wishbone_data_width;
+  constant c_rom_words      : natural := c_rom_entries * c_sdb_words;
+  constant c_rom_depth      : natural := f_ceil_log2(c_rom_words);
+  constant c_rom_lowbits    : natural := f_ceil_log2(c_wishbone_data_width / 8);
+  constant c_sdb_name       : string  := f_string_fix_len(g_sdb_name , 19, ' ', false);
+  
+  -- Index of the MSI entry in SDB
+  type t_nat_array is array(g_masters-1 downto 0) of natural;
+  function f_master_positions return t_nat_array is
+    variable typ    : std_logic_vector(7 downto 0);
+    variable result : t_nat_array;
+    variable master : natural := 0;
+  begin
+    for rec in c_layout'low to c_layout'high loop
+      typ := c_layout(rec)(7 downto 0);
+      case typ is
+        when x"03" | x"f3" =>
+          assert master < g_masters
+          report "Too many msi records found"
+          severity failure;
+        
+          result(master) := rec;
+          master := master + 1;
+        
+        when others => null;
+      end case;
+    end loop;
+    
+    if master = 0 then
+      result := (others => 0);
+    else
+      assert master = g_masters
+      report "Insufficient msi records found (" & Integer'image(master) & "/" & Integer'image(g_masters) & ")"
+      severity failure;
+    end if;
+    return result;
+  end f_master_positions;
+  
+  constant c_master_positions : t_nat_array := f_master_positions;
+  constant c_msi              : boolean     := c_master_positions(0) /= 0;
+  
+  function f_msi_flag_index(y : std_logic_vector) return std_logic_vector is
+    variable offset : unsigned(c_rom_depth-1 downto 0) := (others => '0');
+    variable result : std_logic_vector(c_rom_depth-1 downto 0) := (others => '0');
+  begin
+    for i in c_master_positions'range loop
+      if c_msi then
+        offset := to_unsigned(c_master_positions(i)*16, offset'length);
+      end if;
+      for b in result'range loop
+        result(b) := result(b) or (offset(b) and y(i));
+      end loop;
+    end loop;
+    return result;
+  end f_msi_flag_index;
+  
+  type t_rom is array(c_rom_words-1 downto 0) of t_wishbone_data;
+
+  function f_build_rom
+    return t_rom 
+  is
+    variable res : t_rom := (others => (others => '0'));
+    variable sdb_record : t_sdb_record;
+    variable sdb_component : t_sdb_component;
+  begin
+    sdb_record(511 downto 480) := x"5344422D"  ;                                     -- sdb_magic
+    sdb_record(479 downto 464) := std_logic_vector(to_unsigned(c_used_entries, 16)); -- sdb_records
+    sdb_record(463 downto 456) := x"01";                                             -- sdb_version
+    sdb_record(455 downto 448) := x"00";                                             -- sdb_bus_type = sdb_wishbone
+    sdb_record(  7 downto   0) := x"00";                                             -- record_type  = sdb_interconnect
+    
+    sdb_component.addr_first := (others => '0');
+    sdb_component.addr_last  := std_logic_vector(g_bus_end);
+    sdb_component.product.vendor_id := x"0000000000000651"; -- GSI
+    sdb_component.product.device_id := x"e6a542c9";
+    sdb_component.product.version   := x"00000003";
+    sdb_component.product.date      := x"20120511";
+    sdb_component.product.name      := c_sdb_name;
+    sdb_record(447 downto   8) := f_sdb_embed_component(sdb_component, (others => '0'));
+    
+    for i in 0 to c_sdb_words-1 loop
+      res(c_sdb_words-1-i) := 
+        sdb_record((i+1)*c_wishbone_data_width-1 downto i*c_wishbone_data_width);
+    end loop;
+    
+    for idx in c_layout'range loop
+      sdb_record := c_layout(idx);
+      
+      -- All local/temporary types => empty record
+      if sdb_record(7 downto 4) = x"f" then
+        sdb_record(3 downto 0) := x"f";
+      end if;
+      
+      for i in 0 to c_sdb_words-1 loop
+        res((idx+1)*c_sdb_words-1-i) := 
+          sdb_record((i+1)*c_wishbone_data_width-1 downto i*c_wishbone_data_width);
+      end loop;
+    end loop;
+    
+    return res;
+  end f_build_rom;
+  
+  signal rom : t_rom := f_build_rom;
+
+  signal s_adr : unsigned(c_rom_depth-1 downto 0);
+  signal s_sel : unsigned(c_rom_depth-1 downto 0);
+  
+  signal r_rom  : t_wishbone_data;
+  signal r_flag : t_wishbone_data;
+  signal r_ack  : std_logic;
+
+begin
+
+  slave_o.dat <= r_rom or r_flag;
+  slave_o.ack <= r_ack;
+  slave_o.err   <= '0';
+  slave_o.rty   <= '0';
+  slave_o.stall <= '0';
+  slave_o.int   <= '0'; -- Tom sucks! This should not be here.
+
+  s_adr <= unsigned(slave_i.adr(c_rom_depth+c_rom_lowbits-1 downto c_rom_lowbits));
+  s_sel <= unsigned(f_msi_flag_index(master_i));
+  
+  slave_clk : process(clk_sys_i)
+  begin
+    if (rising_edge(clk_sys_i)) then
+      r_ack <= slave_i.cyc and slave_i.stb;
+      r_rom  <= rom(to_integer(s_adr));
+      r_flag <= (others => '0');
+      if s_adr = s_sel and c_msi then
+        r_flag(r_flag'high) <= '1';
+      end if;
+    end if;
+  end process;
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
new file mode 100644
index 000000000..265e3495b
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
@@ -0,0 +1,427 @@
+-------------------------------------------------------------------------------
+-- Title      : An MxS Wishbone crossbar switch
+-- Project    : General Cores Library (gencores)
+-------------------------------------------------------------------------------
+-- File       : xwb_crossbar.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2011-06-08
+-- Last update: 2011-09-22
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- An MxS Wishbone crossbar switch
+-- 
+-- All masters, slaves, and the crossbar itself must share the same WB clock.
+-- All participants must support the same data bus width. 
+-- 
+-- If a master raises STB_O with an address not mapped by the crossbar,
+-- ERR_I will be raised. If two masters address the same slave
+-- simultaneously, the lowest numbered master is granted access.
+-- 
+-- The implementation of this crossbar locks a master to a slave so long as
+-- CYC_O is held high. 
+-- 
+-- Synthesis/timing relevant facts:
+--   (m)asters, (s)laves, masked (a)ddress bits
+--   
+--   Area required       = O(ms log(ma))
+--   Arbitration depth   = O(log(msa))
+--   Master->Slave depth = O(log(m))
+--   Slave->Master depth = O(log(s))
+-- 
+--   If g_registered = false, arbitration depth is added to M->S and S->M.
+--
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 GSI / Wesley W. Terpstra
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2012-03-05  3.0      wterpstra       made address generic and check overlap
+-- 2011-11-04  2.0      wterpstra       timing improvements
+-- 2011-06-08  1.0      wterpstra       import from SVN
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wishbone_pkg.all;
+
+entity xwb_crossbar is
+  generic(
+    g_num_masters : integer := 2;
+    g_num_slaves  : integer := 1;
+    g_registered  : boolean := false;
+    -- Address of the slaves connected
+    g_address     : t_wishbone_address_array;
+    g_mask        : t_wishbone_address_array);
+  port(
+    clk_sys_i     : in  std_logic;
+    rst_n_i       : in  std_logic;
+    -- Master connections (INTERCON is a slave)
+    slave_i       : in  t_wishbone_slave_in_array(g_num_masters-1 downto 0);
+    slave_o       : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
+    -- Slave connections (INTERCON is a master)
+    master_i      : in  t_wishbone_master_in_array(g_num_slaves-1 downto 0);
+    master_o      : out t_wishbone_master_out_array(g_num_slaves-1 downto 0);
+    -- Master granted access to SDB for use by MSI crossbar (please ignore it)
+    sdb_sel_o     : out std_logic_vector(g_num_masters-1 downto 0));
+end xwb_crossbar;
+
+architecture rtl of xwb_crossbar is
+  alias c_address : t_wishbone_address_array(g_num_slaves-1 downto 0) is g_address;
+  alias c_mask    : t_wishbone_address_array(g_num_slaves-1 downto 0) is g_mask;
+
+  -- Confirm that no address ranges overlap
+  function f_ranges_ok
+    return boolean
+  is
+    constant zero  : t_wishbone_address := (others => '0');
+    constant align : std_logic_vector(f_ceil_log2(c_wishbone_data_width)-4 downto 0) := (others => '0');
+  begin
+    -- all (i,j) with 0 <= i < j < n
+    if g_num_slaves > 1 then
+      for i in 0 to g_num_slaves-2 loop
+        for j in i+1 to g_num_slaves-1 loop
+          assert not (((c_mask(i) and c_mask(j)) and (c_address(i) xor c_address(j))) = zero) or
+                 ((c_mask(i) or not c_address(i)) = zero) or -- disconnected slave?
+                 ((c_mask(j) or not c_address(j)) = zero)    -- disconnected slave?
+          report "Address ranges must be distinct (slaves " & 
+                 Integer'image(i) & "[" & f_bits2string(c_address(i)) & "/" &
+                                          f_bits2string(c_mask(i)) & "] & " & 
+                 Integer'image(j) & "[" & f_bits2string(c_address(j)) & "/" &
+                                          f_bits2string(c_mask(j)) & "])"
+          severity Failure;
+        end loop;
+      end loop;
+    end if;
+    for i in 0 to g_num_slaves-1 loop
+      assert (c_address(i) and not c_mask(i)) = zero or -- at least 1 bit outside mask
+             (not c_address(i) or c_mask(i))  = zero    -- all bits outside mask (= disconnected)
+      report "Address bits not in mask; slave #" & 
+             Integer'image(i) & "[" & f_bits2string(c_address(i)) & "/" &
+                                      f_bits2string(c_mask(i)) & "]"
+      severity Failure;
+      
+      assert c_mask(i)(align'range) = align
+      report "Address space smaller than a wishbone register; slave #" & 
+             Integer'image(i) & "[" & f_bits2string(c_address(i)) & "/" &
+                                      f_bits2string(c_mask(i)) & "]"
+      severity Failure;
+      
+      -- Working case
+      report "Mapping slave #" & 
+             Integer'image(i) & "[" & f_bits2string(c_address(i)) & "/" &
+                                      f_bits2string(c_mask(i)) & "]"
+      severity Note;
+    end loop;
+    return true;
+  end f_ranges_ok;
+  constant c_ok : boolean := f_ranges_ok;
+
+  -- Crossbar connection matrix
+  type matrix is array (g_num_masters-1 downto 0, g_num_slaves downto 0) of std_logic;
+  
+  -- Add an 'error' device to the list of slaves
+  signal master_ie : t_wishbone_master_in_array(g_num_slaves downto 0);
+  signal master_oe : t_wishbone_master_out_array(g_num_slaves downto 0);
+  signal virtual_ERR : std_logic;
+  
+  signal matrix_old : matrix; -- Registered connection matrix
+  signal matrix_new : matrix; -- The new values of the matrix
+
+  -- Either matrix_old or matrix_new, depending on g_registered
+  signal granted : matrix;
+  
+  -- 1 => 0    2 => 1    3..4 => 2     5..8 => 3
+  function log2(i : natural) return natural is
+  begin
+    if i <= 1
+    then return 0;
+    else return log2((i+1)/2) + 1;
+    end if;
+  end log2;
+  
+  -- 0 => 1    1 => 2      2 => 4      3 => 8
+  function pow2(i : natural) return natural is
+  begin
+    if i = 0
+    then return 1;
+    else return pow2(i-1)*2;
+    end if;
+  end pow2;
+  
+  -- If any of the bits are '1', the whole thing is '1'
+  -- This function makes the check explicitly have logarithmic depth.
+  function vector_OR(x : std_logic_vector)
+    return std_logic 
+  is
+    constant len : integer := x'length;
+    constant mid : integer := len / 2;
+    alias y : std_logic_vector(len-1 downto 0) is x;
+  begin
+    if len = 1 
+    then return y(0);
+    else return vector_OR(y(len-1 downto mid)) or
+                vector_OR(y(mid-1 downto 0));
+    end if;
+  end vector_OR;
+  
+  -- Kogge-Stone network of ORs.
+  -- A log(n) deep, n-wide circuit where:
+  --   output(i) = OR_{j<=i} input(j)
+  function ks_OR(input : std_logic_vector)
+    return std_logic_vector
+  is
+    constant width  : natural := input'length;
+    constant stages : natural := log2(width);
+    variable prev   : std_logic_vector(width-1 downto 0);
+    variable output : std_logic_vector(width-1 downto 0);
+  begin
+    prev := input;
+    if stages = 0 then
+      output := prev;
+    else
+      for l in 0 to stages-1 loop
+        for i in 0 to width-1 loop
+          if i >= pow2(l)
+          then output(i) := prev(i) or prev(i-pow2(l));
+          else output(i) := prev(i);
+          end if;
+        end loop;
+        prev := output;
+      end loop;
+    end if;
+    return output;
+  end ks_OR;
+  
+  -- Impure because it accesses c_{address, mask}
+  function matrix_logic(
+    matrix_old : matrix;
+    slave_i    : t_wishbone_slave_in_array(g_num_masters-1 downto 0))
+    return matrix
+  is
+    subtype row    is std_logic_vector(g_num_masters-1 downto 0);
+    subtype column is std_logic_vector(g_num_slaves    downto 0);
+    
+    variable tmp        : std_logic;
+    variable tmp_column : column;
+    variable tmp_row    : row;
+    
+    variable request    : matrix;  -- Which slaves do the masters address log(S) 
+    variable selected   : matrix;  -- Which master wins arbitration  log(M) request
+    variable sbusy      : column;  -- Does the slave's  previous connection persist?
+    variable mbusy      : row;     -- Does the master's previous connection persist?
+    variable matrix_new : matrix;
+  begin
+    -- A slave is busy iff it services an in-progress cycle
+    for slave in g_num_slaves downto 0 loop
+      for master in g_num_masters-1 downto 0 loop
+        tmp_row(master) := matrix_old(master, slave) and slave_i(master).CYC;
+      end loop;
+      sbusy(slave) := vector_OR(tmp_row);
+    end loop;
+    
+    -- A master is busy iff it services an in-progress cycle
+    for master in g_num_masters-1 downto 0 loop
+      for slave in g_num_slaves downto 0 loop
+        tmp_column(slave) := matrix_old(master, slave);
+      end loop;
+      mbusy(master) := vector_OR(tmp_column) and slave_i(master).CYC;
+    end loop;
+
+    -- Decode the request address to see if master wants access
+    for master in g_num_masters-1 downto 0 loop
+      for slave in g_num_slaves-1 downto 0 loop
+        tmp := not vector_OR((slave_i(master).ADR and c_mask(slave)) xor c_address(slave));
+        tmp_column(slave) := tmp;
+        request(master, slave) := slave_i(master).CYC and slave_i(master).STB and tmp;
+      end loop;
+      tmp_column(g_num_slaves) := '0';
+      -- If no slaves match request, bind to 'error device'
+      request(master, g_num_slaves) := slave_i(master).CYC and slave_i(master).STB and not vector_OR(tmp_column);
+    end loop;
+
+    -- Arbitrate among the requesting masters
+    -- Policy: lowest numbered master first
+    for slave in g_num_slaves downto 0 loop
+      -- OR together all the requests by higher priority masters
+      for master in 0 to g_num_masters-1 loop
+        tmp_row(master) := request(master, slave);
+      end loop;
+      tmp_row := ks_OR(tmp_row);
+      
+      -- Grant to highest priority master
+      selected(0, slave) := request(0, slave); -- master 0 always wins
+      if g_num_masters > 1 then
+        for master in 1 to g_num_masters-1 loop
+          selected(master, slave) := -- only if requested and no lower requests
+            not tmp_row(master-1) and request(master, slave);
+        end loop;
+      end if;
+    end loop;
+
+    -- Determine the master granted access
+    -- Policy: if cycle still in progress, preserve the previous choice
+    for slave in g_num_slaves downto 0 loop
+      for master in g_num_masters-1 downto 0 loop
+        if sbusy(slave) = '1' or mbusy(master) = '1' then
+          matrix_new(master, slave) := matrix_old(master, slave);
+        else
+          matrix_new(master, slave) := selected(master, slave);
+        end if;
+      end loop;
+    end loop;
+    
+    return matrix_new;
+  end matrix_logic;
+
+  subtype slave_row is std_logic_vector(g_num_masters-1 downto 0);
+  type slave_matrix is array (natural range <>) of slave_row;
+  
+  function slave_matrix_OR(x : slave_matrix)
+    return std_logic_vector is
+    variable result : std_logic_vector(x'LENGTH-1 downto 0);
+  begin
+    for i in x'LENGTH-1 downto 0 loop
+      result(i) := vector_OR(x(i));
+    end loop;
+    return result;
+  end slave_matrix_OR;
+  
+  -- Select the master pins the slave will receive
+  function slave_logic(slave   : integer;
+                       granted : matrix;
+                       slave_i : t_wishbone_slave_in_array(g_num_masters-1 downto 0))
+    return t_wishbone_master_out
+  is
+    variable CYC_row    : slave_row;
+    variable STB_row    : slave_row;
+    variable ADR_matrix : slave_matrix(c_wishbone_address_width-1 downto 0);
+    variable SEL_matrix : slave_matrix((c_wishbone_address_width/8)-1 downto 0);
+    variable WE_row     : slave_row;
+    variable DAT_matrix : slave_matrix(c_wishbone_data_width-1 downto 0);
+  begin
+    -- Rename all the signals ready for big_or
+    for master in g_num_masters-1 downto 0 loop
+      CYC_row(master) := slave_i(master).CYC and granted(master, slave);
+      STB_row(master) := slave_i(master).STB and granted(master, slave);
+      for bit in c_wishbone_address_width-1 downto 0 loop
+        ADR_matrix(bit)(master) := slave_i(master).ADR(bit) and granted(master, slave);
+      end loop;
+      for bit in (c_wishbone_address_width/8)-1 downto 0 loop
+        SEL_matrix(bit)(master) := slave_i(master).SEL(bit) and granted(master, slave);
+      end loop;
+      WE_row(master) := slave_i(master).WE and granted(master, slave);
+      for bit in c_wishbone_data_width-1 downto 0 loop
+        DAT_matrix(bit)(master) := slave_i(master).DAT(bit) and granted(master, slave);
+      end loop;
+    end loop;
+    
+    return (
+       CYC => vector_OR(CYC_row),
+       STB => vector_OR(STB_row),
+       ADR => slave_matrix_OR(ADR_matrix),
+       SEL => slave_matrix_OR(SEL_matrix),
+       WE  => vector_OR(WE_row),
+       DAT => slave_matrix_OR(DAT_matrix));
+  end slave_logic;
+
+  subtype master_row is std_logic_vector(g_num_slaves downto 0);
+  type master_matrix is array (natural range <>) of master_row;
+  
+  function master_matrix_OR(x : master_matrix)
+    return std_logic_vector is
+    variable result : std_logic_vector(x'LENGTH-1 downto 0);
+  begin
+    for i in x'LENGTH-1 downto 0 loop
+      result(i) := vector_OR(x(i));
+    end loop;
+    return result;
+  end master_matrix_OR;
+  
+  -- Select the slave pins the master will receive
+  function master_logic(master    : integer;
+                        granted   : matrix;
+                        master_ie : t_wishbone_master_in_array(g_num_slaves downto 0))
+    return t_wishbone_slave_out
+  is
+    variable ACK_row    : master_row;
+    variable ERR_row    : master_row;
+    variable RTY_row    : master_row;
+    variable STALL_row  : master_row;
+    variable DAT_matrix : master_matrix(c_wishbone_data_width-1 downto 0);
+  begin
+    -- We use inverted logic on STALL so that if no slave granted => stall
+    for slave in g_num_slaves downto 0 loop
+      ACK_row(slave) := master_ie(slave).ACK and granted(master, slave);
+      ERR_row(slave) := master_ie(slave).ERR and granted(master, slave);
+      RTY_row(slave) := master_ie(slave).RTY and granted(master, slave);
+      STALL_row(slave) := not master_ie(slave).STALL and granted(master, slave);
+      for bit in c_wishbone_data_width-1 downto 0 loop
+        DAT_matrix(bit)(slave) := master_ie(slave).DAT(bit) and granted(master, slave);
+      end loop;
+    end loop;
+    
+    return (
+      ACK => vector_OR(ACK_row),
+      ERR => vector_OR(ERR_row),
+      RTY => vector_OR(RTY_row),
+      STALL => not vector_OR(STALL_row),
+      DAT => master_matrix_OR(DAT_matrix),
+      INT => '0');
+  end master_logic;
+begin
+  -- The virtual error slave is pretty straight-forward:
+  master_o <= master_oe(g_num_slaves-1 downto 0);
+  master_ie(g_num_slaves-1 downto 0) <= master_i;
+  
+  master_ie(g_num_slaves) <= (
+    ACK   => '0', 
+    ERR   => virtual_ERR,
+    RTY   => '0', 
+    STALL => '0',
+    DAT   => (others => '0'),
+    INT   => '0');
+  virtual_error_slave : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      virtual_ERR <= master_oe(g_num_slaves).CYC and master_oe(g_num_slaves).STB;
+    end if;
+  end process virtual_error_slave;
+  
+  -- Copy the matrix to a register:
+  matrix_new <= matrix_logic(matrix_old, slave_i);
+  main : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        matrix_old <= (others => (others => '0'));
+      else
+        matrix_old <= matrix_new;
+      end if;
+    end if;
+  end process main;
+  
+  -- Is the crossbar combinatorial or registered
+  granted <= matrix_old when g_registered else matrix_new;
+
+  -- Make the slave connections
+  slave_matrixs : for slave in g_num_slaves downto 0 generate
+    master_oe(slave) <= slave_logic(slave, granted, slave_i);
+  end generate;
+
+  -- Make the master connections
+  master_matrixs : for master in g_num_masters-1 downto 0 generate
+    slave_o(master) <= master_logic(master, granted, master_ie);
+  end generate;
+  
+  -- Tell SDB which master is accessing it (SDB is last slave)
+  sdb_masters : for master in g_num_masters-1 downto 0 generate
+    sdb_sel_o(master) <= granted(master, g_num_slaves-1);
+  end generate;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
new file mode 100644
index 000000000..010fe078a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
@@ -0,0 +1,232 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wishbone_pkg.all;
+
+entity xwb_sdb_crossbar is
+  generic(
+    g_num_masters : natural := 1;
+    g_num_slaves  : natural := 1;
+    g_registered  : boolean := false;
+    g_wraparound  : boolean := true;
+    g_layout      : t_sdb_record_array;
+    g_sdb_addr    : t_wishbone_address;
+    g_sdb_name    : string := "WB4-Crossbar-GSI   ");
+  port(
+    clk_sys_i     : in  std_logic;
+    rst_n_i       : in  std_logic;
+    -- Master connections (INTERCON is a slave)
+    slave_i       : in  t_wishbone_slave_in_array  (g_num_masters-1 downto 0);
+    slave_o       : out t_wishbone_slave_out_array (g_num_masters-1 downto 0);
+    msi_master_i  : in  t_wishbone_master_in_array (g_num_masters-1 downto 0) := (others => cc_dummy_master_in);
+    msi_master_o  : out t_wishbone_master_out_array(g_num_masters-1 downto 0);
+    -- Slave connections (INTERCON is a master)
+    master_i      : in  t_wishbone_master_in_array (g_num_slaves -1 downto 0);
+    master_o      : out t_wishbone_master_out_array(g_num_slaves -1 downto 0);
+    msi_slave_i   : in  t_wishbone_slave_in_array  (g_num_slaves -1 downto 0) := (others => cc_dummy_slave_in);
+    msi_slave_o   : out t_wishbone_slave_out_array (g_num_slaves -1 downto 0));
+end xwb_sdb_crossbar;
+
+architecture rtl of xwb_sdb_crossbar is
+  alias c_layout : t_sdb_record_array(g_layout'length-1 downto 0) is g_layout;
+  
+  -- Pretty print device name
+  function f_trim(s : string) return string is
+    variable cut : natural;
+  begin
+    byte : for i in s'length downto 1 loop
+      cut := i;
+      exit byte when s(i) /= ' ';
+    end loop;
+    return s(1 to cut);
+  end f_trim;
+
+  -- Step 1. Place the SDB ROM on the bus
+  -- How much space does the ROM need?
+  constant c_used_entries   : natural := c_layout'length + 1;
+  constant c_rom_entries    : natural := 2**f_ceil_log2(c_used_entries); -- next power of 2
+  constant c_sdb_bytes      : natural := c_sdb_device_length / 8;
+  constant c_rom_bytes      : natural := c_rom_entries * c_sdb_bytes;
+  
+  constant c_bus_last : unsigned := f_sdb_bus_end(g_wraparound, g_layout, g_sdb_addr, false);
+  constant c_msi_last : unsigned := f_sdb_bus_end(g_wraparound, g_layout, g_sdb_addr, true);
+
+  type t_addresses is record
+    bus_address : t_wishbone_address_array(g_num_slaves -1 downto 0);
+    bus_mask    : t_wishbone_address_array(g_num_slaves -1 downto 0);
+    msi_address : t_wishbone_address_array(g_num_masters-1 downto 0);
+    msi_mask    : t_wishbone_address_array(g_num_masters-1 downto 0);
+  end record t_addresses;
+
+  -- Step 3. Map device address begin values
+  function f_addresses return t_addresses is
+    variable result : t_addresses;
+    
+    variable typ     : std_logic_vector(7 downto 0);
+    variable sdb_component : t_sdb_component;
+    
+    variable address : t_wishbone_address;
+    variable extend  : std_logic_vector(63 downto 0) := (others => '0');
+    variable size    : unsigned(63 downto 0);
+    
+    variable bus_index : natural := 0;
+    variable msi_index : natural := 0;
+  begin
+    for i in c_layout'low to c_layout'high loop
+      typ := c_layout(i)(7 downto 0);
+      sdb_component := f_sdb_extract_component(c_layout(i)(447 downto 8));
+
+      if (typ(7) = '0') then --only do address checks on non-meta record types (typ >= 0x80)
+        -- Range must be valid
+        assert unsigned(sdb_component.addr_first) <= unsigned(sdb_component.addr_last)
+        report "Wishbone slave device #" & Integer'image(i) & " (" & f_trim(sdb_component.product.name) & ") sdb_component.addr_first (" & f_bits2string(sdb_component.addr_first) & ") must precede sdb_component.addr_last address (" & f_bits2string(sdb_component.addr_last) & ")."
+        severity Failure;
+
+        -- Address must fit within Wishbone address width
+        address := sdb_component.addr_first(address'range);
+        extend(address'range) := address;
+        assert sdb_component.addr_first = extend
+        report "Wishbone slave device #" & Integer'image(i) & " (" & f_trim(sdb_component.product.name) & ") sdb_component.addr_first (" & f_bits2string(sdb_component.addr_first) & " does not fit in t_wishbone_address."
+        severity Failure;
+        
+        size := unsigned(sdb_component.addr_last) - unsigned(sdb_component.addr_first);
+        -- size must be of the form 000000...00001111...1
+        assert (size and (size + 1)) = 0
+        report "Wishbone slave device #" & Integer'image(i) & " (" & f_trim(sdb_component.product.name) & ") has an address range that is not a power of 2 minus one (" & f_bits2string(std_logic_vector(size)) & "). This is not supported by the crossbar."
+        severity Warning;
+        
+        -- fix the size up to the form 000...0001111...11
+        for j in c_wishbone_address_width-2 downto 0 loop
+          size(j) := size(j) or size(j+1);
+        end loop;
+        
+        -- the base address must be aligned to the size
+        assert (unsigned(sdb_component.addr_first) and size) = 0
+        report "Wishbone slave device #" & Integer'image(i) & " (" & f_trim(sdb_component.product.name) & ") sdb_component.addr_first (" & f_bits2string(sdb_component.addr_first) & ") is not aligned. This is not supported by the crossbar."
+        severity Failure;
+
+      end if;
+
+      -- Record the address for posterity
+      case typ is
+        when x"01" | x"02" =>
+          assert bus_index < g_num_slaves
+          report "Too many device and bridge records found in g_layout"
+          severity Failure;
+          
+          size := c_bus_last - size;
+          result.bus_address(bus_index) := address;
+          result.bus_mask   (bus_index) := std_logic_vector(size(address'range));
+          bus_index := bus_index + 1;
+          
+        when x"03" =>
+          assert msi_index < g_num_masters
+          report "Too many msi records found in g_layout"
+          severity Failure;
+          
+          size := c_msi_last - size;
+          result.msi_address(msi_index) := address;
+          result.msi_mask   (msi_index) := std_logic_vector(size(address'range));
+          msi_index := msi_index + 1;
+
+        when x"f1" | x"f2" =>
+          result.bus_address(bus_index) := (others => '1');
+          result.bus_mask   (bus_index) := (others => '0');
+          bus_index := bus_index + 1;
+
+        when x"f3" =>
+          result.msi_address(msi_index) := (others => '1');
+          result.msi_mask   (msi_index) := (others => '0');
+          msi_index := msi_index + 1;
+        
+        when others => null;
+      end case;
+    end loop;
+    
+    -- There must be exactly the right number of slave SDB records
+    assert bus_index = g_num_slaves
+    report "Too few device and bridge records found in g_layout. Did you accidentally include meta records in the supplied number of slaves?"
+    severity Failure;
+    
+    -- It is OK to have no master records (backwards compat)
+    if msi_index = 0 then
+      result.msi_address := (others => (others => '1'));
+      result.msi_mask    := (others => (others => '0'));
+    else
+      assert msi_index = g_num_masters
+      report "Too few msi records found in g_layout"
+      severity Failure;
+    end if;
+    
+    return result;
+  end f_addresses;
+  
+  constant c_addresses : t_addresses := f_addresses;
+
+  -- Figure out the mask for the SDB slave
+  constant c_rom_mask : unsigned(63 downto 0) := 
+    c_bus_last - to_unsigned(c_rom_bytes-1, 64);
+  constant c_sdb_mask : t_wishbone_address := 
+    std_logic_vector(c_rom_mask(c_wishbone_address_width-1 downto 0));
+  
+  -- Fill bus crossbar parameters
+  constant c_address : t_wishbone_address_array(g_num_slaves downto 0) :=
+    g_sdb_addr & c_addresses.bus_address;
+  constant c_mask : t_wishbone_address_array(g_num_slaves downto 0) :=
+    c_sdb_mask & c_addresses.bus_mask;
+  
+  signal master_i_1 :  t_wishbone_master_in_array(g_num_slaves downto 0);
+  signal master_o_1 : t_wishbone_master_out_array(g_num_slaves downto 0);
+  signal sdb_sel    : std_logic_vector(g_num_masters-1 downto 0);
+
+begin
+
+  -- Pass-through all slave ports except SDB
+  master_i_1(g_num_slaves-1 downto 0) <=  master_i;
+  master_o <= master_o_1(g_num_slaves-1 downto 0);
+  
+  rom : sdb_rom
+    generic map(
+      g_layout   => c_layout,
+      g_masters  => g_num_masters,
+      g_bus_end  => c_bus_last,
+      g_sdb_name => g_sdb_name)
+    port map(
+      clk_sys_i => clk_sys_i,
+      master_i  => sdb_sel,
+      slave_i   => master_o_1(g_num_slaves),
+      slave_o   => master_i_1(g_num_slaves));
+  
+  crossbar : xwb_crossbar
+    generic map(
+      g_num_masters => g_num_masters,
+      g_num_slaves  => g_num_slaves + 1,
+      g_registered  => g_registered,
+      g_address     => c_address,
+      g_mask        => c_mask)
+    port map(
+      clk_sys_i     => clk_sys_i,
+      rst_n_i       => rst_n_i,
+      slave_i       => slave_i, 
+      slave_o       => slave_o, 
+      master_i      => master_i_1, 
+      master_o      => master_o_1,
+      sdb_sel_o     => sdb_sel);
+
+  msi : xwb_crossbar
+    generic map(
+      g_num_masters => g_num_slaves,
+      g_num_slaves  => g_num_masters,
+      g_registered  => g_registered,
+      g_address     => c_addresses.msi_address,
+      g_mask        => c_addresses.msi_mask)
+    port map(
+      clk_sys_i     => clk_sys_i,
+      rst_n_i       => rst_n_i,
+      slave_i       => msi_slave_i,
+      slave_o       => msi_slave_o,
+      master_i      => msi_master_i,
+      master_o      => msi_master_o,
+      sdb_sel_o     => open);
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
new file mode 100644
index 000000000..71c3f3840
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
@@ -0,0 +1,185 @@
+-------------------------------------------------------------------------------
+-- Title      : Dual-port RAM for WR core
+-- Project    : WhiteRabbit
+-------------------------------------------------------------------------------
+-- File       : wrc_dpram.vhd
+-- Author     : Grzegorz Daniluk
+-- Company    : CERN
+-- Created    : 2011-02-15
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- Dual port RAM with wishbone interface
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-02-15  1.0      greg.d          Created
+-- 2011-06-09  1.01     twlostow        Removed unnecessary generics
+-- 2011-21-09  1.02     twlostow        Struct-ized version
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.genram_pkg.all;
+use work.wishbone_pkg.all;
+
+entity xwb_dpram is
+  generic(
+    g_size                  : natural := 16384;
+    g_init_file             : string  := "";
+    g_must_have_init_file   : boolean := true;
+    g_slave1_interface_mode : t_wishbone_interface_mode;
+    g_slave2_interface_mode : t_wishbone_interface_mode;
+    g_slave1_granularity    : t_wishbone_address_granularity;
+    g_slave2_granularity    : t_wishbone_address_granularity
+    );
+  port(
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    slave1_i : in  t_wishbone_slave_in;
+    slave1_o : out t_wishbone_slave_out;
+    slave2_i : in  t_wishbone_slave_in;
+    slave2_o : out t_wishbone_slave_out
+    );
+end xwb_dpram;
+
+architecture struct of xwb_dpram is
+
+  signal s_wea  : std_logic;
+  signal s_web  : std_logic;
+  signal s_bwea : std_logic_vector(3 downto 0);
+  signal s_bweb : std_logic_vector(3 downto 0);
+
+  signal slave1_in  : t_wishbone_slave_in;
+  signal slave1_out : t_wishbone_slave_out;
+  signal slave2_in  : t_wishbone_slave_in;
+  signal slave2_out : t_wishbone_slave_out;
+  
+begin
+  U_Adapter1 : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => g_slave1_interface_mode,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => true,
+      g_slave_mode         => g_slave1_interface_mode,
+      g_slave_granularity  => g_slave1_granularity)
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      slave_i   => slave1_i,
+      slave_o   => slave1_o,
+      master_i  => slave1_out,
+      master_o  => slave1_in);
+
+  U_Adapter2 : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => g_slave2_interface_mode,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => true,
+      g_slave_mode         => g_slave2_interface_mode,
+      g_slave_granularity  => g_slave2_granularity)
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      slave_i   => slave2_i,
+      slave_o   => slave2_o,
+      master_i  => slave2_out,
+      master_o  => slave2_in);
+
+    U_DPRAM : generic_dpram
+      generic map(
+        -- standard parameters
+        g_data_width               => 32,
+        g_size                     => g_size,
+        g_with_byte_enable         => true,
+        g_addr_conflict_resolution => "dont_care",
+        g_init_file                => g_init_file,
+        g_dual_clock               => false
+        )
+      port map(
+        rst_n_i => rst_n_i,
+        -- Port A
+        clka_i  => clk_sys_i,
+        bwea_i  => s_bwea,
+        wea_i   => s_wea,
+        aa_i    => slave1_in.adr(f_log2_size(g_size)-1 downto 0),
+        da_i    => slave1_in.dat,
+        qa_o    => slave1_out.dat,
+        -- Port B
+        clkb_i  => clk_sys_i,
+        bweb_i  => s_bweb,
+        web_i   => s_web,
+        ab_i    => slave2_in.adr(f_log2_size(g_size)-1 downto 0),
+        db_i    => slave2_in.dat,
+        qb_o    => slave2_out.dat
+        );
+
+  -- I know this looks weird, but otherwise ISE generates distributed RAM instead of block
+  -- RAM
+  s_bwea <= slave1_in.sel when s_wea = '1' else f_zeros(c_wishbone_data_width/8);
+  s_bweb <= slave2_in.sel when s_web = '1' else f_zeros(c_wishbone_data_width/8);
+
+  s_wea <= slave1_in.we and slave1_in.stb and slave1_in.cyc;
+  s_web <= slave2_in.we and slave2_in.stb and slave2_in.cyc;
+
+  process(clk_sys_i)
+  begin
+    if(rising_edge(clk_sys_i)) then
+      if(rst_n_i = '0') then
+        slave1_out.ack <= '0';
+        slave2_out.ack <= '0';
+      else
+        if(slave1_out.ack = '1' and g_slave1_interface_mode = CLASSIC) then
+          slave1_out.ack <= '0';
+        else
+          slave1_out.ack <= slave1_in.cyc and slave1_in.stb;
+        end if;
+
+        if(slave2_out.ack = '1' and g_slave2_interface_mode = CLASSIC) then
+          slave2_out.ack <= '0';
+        else
+          slave2_out.ack <= slave2_in.cyc and slave2_in.stb;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  slave1_out.stall <= '0';
+  slave2_out.stall <= '0';
+  slave1_out.err   <= '0';
+  slave2_out.err   <= '0';
+  slave1_out.rty   <= '0';
+  slave2_out.rty   <= '0';
+  slave1_out.int   <= '0';
+  slave2_out.int   <= '0';
+  
+end struct;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
new file mode 100644
index 000000000..af57302c2
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
@@ -0,0 +1,102181 @@
+
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+
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+
+
+
+module lm32_top_full (
+    
+    clk_i,
+    rst_i,
+    
+
+    interrupt,
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+    );
+
+parameter eba_reset = 32'h00000000;
+parameter sdb_address = 32'h00000000;
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+
+input [ (32-1):0] interrupt;          
+
+
+  
+               
+                             
+
+    
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+  
+
+
+
+ 
+  
+
+  
+  
+ 
+  
+  
+ 
+ 
+
+
+
+
+  
+
+                     
+                             
+                            
+                   
+                                 
+ 
+                                 
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+   
+
+lm32_cpu_full 
+	#(
+		.eba_reset(eba_reset),
+    .sdb_address(sdb_address)
+	) cpu (
+    
+    .clk_i                 (clk_i),
+  
+                   
+
+
+    .rst_i                 (rst_i),
+    
+  
+
+    .interrupt             (interrupt),
+ 
+
+    
+  
+               
+             
+
+     
+  
+    
+                  
+               
+                
+           
+
+
+  
+
+     
+    .I_DAT_I               (I_DAT_I),
+    .I_ACK_I               (I_ACK_I),
+    .I_ERR_I               (I_ERR_I),
+    .I_RTY_I               (I_RTY_I),
+ 
+
+    
+    .D_DAT_I               (D_DAT_I),
+    .D_ACK_I               (D_ACK_I),
+    .D_ERR_I               (D_ERR_I),
+    .D_RTY_I               (D_RTY_I),
+    
+  
+                  
+            
+           
+                 
+                
+ 
+                
+
+
+
+  
+                
+           
+
+
+      
+                
+               
+            
+            
+
+    
+  
+
+    
+    .I_DAT_O               (I_DAT_O),
+    .I_ADR_O               (I_ADR_O),
+    .I_CYC_O               (I_CYC_O),
+    .I_SEL_O               (I_SEL_O),
+    .I_STB_O               (I_STB_O),
+    .I_WE_O                (I_WE_O),
+    .I_CTI_O               (I_CTI_O),
+    .I_LOCK_O              (I_LOCK_O),
+    .I_BTE_O               (I_BTE_O),
+     
+
+    
+    .D_DAT_O               (D_DAT_O),
+    .D_ADR_O               (D_ADR_O),
+    .D_CYC_O               (D_CYC_O),
+    .D_SEL_O               (D_SEL_O),
+    .D_STB_O               (D_STB_O),
+    .D_WE_O                (D_WE_O),
+    .D_CTI_O               (D_CTI_O),
+    .D_LOCK_O              (D_LOCK_O),
+    .D_BTE_O               (D_BTE_O)
+    );
+   
+  		   
+
+  
+    
+                     
+                
+    
+                
+                     
+                
+                      
+                     
+    
+
+        
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+           
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_mc_arithmetic_full (
+    
+    clk_i,
+    rst_i,
+    stall_d,
+    kill_x,
+  
+
+    divide_d,
+    modulus_d,
+ 
+
+  
+    
+
+
+  
+    
+    
+    
+
+
+    operand_0_d,
+    operand_1_d,
+    
+    result_x,
+  
+
+    divide_by_zero_x,
+ 
+
+    stall_request_x
+    );
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+input stall_d;                                  
+input kill_x;                                   
+  
+
+input divide_d;                                 
+input modulus_d;                                
+ 
+
+  
+                                
+
+
+  
+                              
+                             
+                             
+
+
+input [ (32-1):0] operand_0_d;
+input [ (32-1):0] operand_1_d;
+
+
+
+
+
+output [ (32-1):0] result_x;               
+reg    [ (32-1):0] result_x;
+  
+
+output divide_by_zero_x;                        
+reg    divide_by_zero_x;
+ 
+
+output stall_request_x;                         
+wire   stall_request_x;
+
+
+
+
+
+reg [ (32-1):0] p;                         
+reg [ (32-1):0] a;
+reg [ (32-1):0] b;
+  
+
+wire [32:0] t;
+ 
+
+
+reg [ 2:0] state;                 
+reg [5:0] cycles;                               
+
+  
+                               
+                                 
+
+
+
+
+
+
+
+
+assign stall_request_x = state !=  3'b000;
+
+  
+
+
+assign t = {p[ 32-2:0], a[ 32-1]} - b;
+ 
+
+
+  
+
+       
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        cycles <= {6{1'b0}};
+        p <= { 32{1'b0}};
+        a <= { 32{1'b0}};
+        b <= { 32{1'b0}};
+  
+          
+
+
+  
+
+        divide_by_zero_x <=  1'b0;
+ 
+
+        result_x <= { 32{1'b0}};
+        state <=  3'b000;
+    end
+    else
+    begin
+  
+
+        divide_by_zero_x <=  1'b0;
+ 
+
+        case (state)
+         3'b000:
+        begin
+            if (stall_d ==  1'b0)                 
+            begin          
+                cycles <=  32;
+                p <= 32'b0;
+                a <= operand_0_d;
+                b <= operand_1_d;                    
+  
+
+                if (divide_d ==  1'b1)
+                    state <=  3'b011 ;
+                if (modulus_d ==  1'b1)
+                    state <=  3'b010   ;
+ 
+                    
+  
+                   
+                      
+
+
+  
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+
+
+            end            
+        end
+  
+
+         3'b011 :
+        begin
+            if (t[32] == 1'b0)
+            begin
+                p <= t[31:0];
+                a <= {a[ 32-2:0], 1'b1};
+            end
+            else 
+            begin
+                p <= {p[ 32-2:0], a[ 32-1]};
+                a <= {a[ 32-2:0], 1'b0};
+            end
+            result_x <= a;
+            if ((cycles ==  32'd0) || (kill_x ==  1'b1))
+            begin
+                
+                divide_by_zero_x <= b == { 32{1'b0}};
+                state <=  3'b000;
+            end
+            cycles <= cycles - 1'b1;
+        end
+         3'b010   :
+        begin
+            if (t[32] == 1'b0)
+            begin
+                p <= t[31:0];
+                a <= {a[ 32-2:0], 1'b1};
+            end
+            else 
+            begin
+                p <= {p[ 32-2:0], a[ 32-1]};
+                a <= {a[ 32-2:0], 1'b0};
+            end
+            result_x <= p;
+            if ((cycles ==  32'd0) || (kill_x ==  1'b1))
+            begin
+                
+                divide_by_zero_x <= b == { 32{1'b0}};
+                state <=  3'b000;
+            end
+            cycles <= cycles - 1'b1;
+        end
+ 
+        
+  
+        
+        
+               
+                    
+               
+               
+              
+                   
+                  
+                
+        
+
+     
+  
+        
+               
+               
+              
+                   
+                  
+                
+        
+        
+               
+               
+              
+                   
+                  
+                
+        
+
+   
+        endcase
+    end
+end 
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_cpu_full (
+    
+    clk_i,
+  
+    
+
+
+    rst_i,
+  
+    
+
+
+  
+   
+   
+   
+   
+   
+   
+
+
+
+    
+  
+
+    interrupt,
+ 
+
+    
+  
+    
+    
+
+     
+  
+    
+    
+     
+    
+    
+
+
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+  
+    
+    
+    
+    
+    
+ 
+    
+
+
+
+  
+    
+    
+
+
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+ 
+  
+    
+    
+    
+    
+    
+    
+    
+    
+           
+
+
+		 
+		 
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+
+		 
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                           
+  
+                            
+
+
+parameter sdb_address =   32'h00000000;
+
+  
+
+parameter icache_associativity =  1;     
+parameter icache_sets =  256;                       
+parameter icache_bytes_per_line =  16;   
+parameter icache_base_address =  32'h0;       
+parameter icache_limit =  32'h7fffffff;                     
+ 
+       
+                         
+     
+         
+                       
+
+
+
+  
+
+parameter dcache_associativity =  1;     
+parameter dcache_sets =  256;                       
+parameter dcache_bytes_per_line =  16;   
+parameter dcache_base_address =  32'h0;       
+parameter dcache_limit =  32'h7fffffff;                     
+ 
+       
+                         
+     
+         
+                       
+
+
+
+  
+                          
+
+
+parameter watchpoints = 0;
+ 
+
+  
+                          
+
+
+parameter breakpoints = 0;
+ 
+
+
+  
+
+parameter interrupts =  32;                         
+ 
+   
+
+
+
+
+
+
+
+input clk_i;                                    
+  
+                                   
+
+    
+input rst_i;                                    
+
+  
+
+input [ (32-1):0] interrupt;          
+ 
+
+
+  
+               
+                             
+
+    
+
+   
+                                  
+                               
+                
+  
+
+
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+    
+     
+
+
+   
+   
+  
+                   
+     
+                           
+    
+                          
+    
+                 
+     
+                               
+    
+ 
+                               
+    
+
+
+
+
+  
+  
+    
+  
+    
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+
+  
+      
+     
+       
+      
+             
+
+
+   
+
+
+
+
+
+
+  
+
+reg valid_a;                                    
+ 
+
+reg valid_f;                                    
+reg valid_d;                                    
+reg valid_x;                                    
+reg valid_m;                                    
+reg valid_w;                                    
+   
+wire q_x;
+wire [ (32-1):0] immediate_d;              
+wire load_d;                                    
+reg load_x;                                     
+reg load_m;
+wire load_q_x;
+wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
+wire store_d;                                   
+reg store_x;
+reg store_m;
+wire [ 1:0] size_d;                   
+reg [ 1:0] size_x;
+wire branch_d;                                  
+wire branch_predict_d;                          
+wire branch_predict_taken_d;                    
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;   
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
+wire bi_unconditional;
+wire bi_conditional;
+reg branch_x;                                   
+reg branch_predict_x;
+reg branch_predict_taken_x;
+reg branch_m;
+reg branch_predict_m;
+reg branch_predict_taken_m;
+wire branch_mispredict_taken_m;                 
+wire branch_flushX_m;                           
+wire branch_reg_d;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;            
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;             
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+wire [ 0:0] d_result_sel_0_d; 
+wire [ 1:0] d_result_sel_1_d; 
+
+wire x_result_sel_csr_d;                        
+reg x_result_sel_csr_x;
+  
+
+wire q_d;
+wire x_result_sel_mc_arith_d;                   
+reg x_result_sel_mc_arith_x;
+ 
+
+      
+                       
+ 
+
+
+  
+
+wire x_result_sel_sext_d;                       
+reg x_result_sel_sext_x;
+ 
+
+wire x_result_sel_logic_d;                      
+  
+                        
+ 
+
+
+wire x_result_sel_add_d;                        
+reg x_result_sel_add_x;
+wire m_result_sel_compare_d;                    
+reg m_result_sel_compare_x;
+reg m_result_sel_compare_m;
+  
+
+wire m_result_sel_shift_d;                      
+reg m_result_sel_shift_x;
+reg m_result_sel_shift_m;
+ 
+
+wire w_result_sel_load_d;                       
+reg w_result_sel_load_x;
+reg w_result_sel_load_m;
+reg w_result_sel_load_w;
+  
+
+wire w_result_sel_mul_d;                        
+reg w_result_sel_mul_x;
+reg w_result_sel_mul_m;
+reg w_result_sel_mul_w;
+ 
+
+wire x_bypass_enable_d;                         
+reg x_bypass_enable_x;                          
+wire m_bypass_enable_d;                         
+reg m_bypass_enable_x;                          
+reg m_bypass_enable_m;
+wire sign_extend_d;                             
+reg sign_extend_x;
+wire write_enable_d;                            
+reg write_enable_x;
+wire write_enable_q_x;
+reg write_enable_m;
+wire write_enable_q_m;
+reg write_enable_w;
+wire write_enable_q_w;
+wire read_enable_0_d;                           
+wire [ (5-1):0] read_idx_0_d;          
+wire read_enable_1_d;                           
+wire [ (5-1):0] read_idx_1_d;          
+wire [ (5-1):0] write_idx_d;           
+reg [ (5-1):0] write_idx_x;            
+reg [ (5-1):0] write_idx_m;
+reg [ (5-1):0] write_idx_w;
+wire [ (4 -1):0] csr_d;                     
+reg  [ (4 -1):0] csr_x;                  
+wire [ (3-1):0] condition_d;         
+reg [ (3-1):0] condition_x;          
+  
+                                    
+                                     
+
+
+wire scall_d;                                   
+reg scall_x;    
+wire eret_d;                                    
+reg eret_x;
+wire eret_q_x;
+  
+ 
+ 
+
+
+  
+                                     
+ 
+ 
+ 
+ 
+ 
+
+
+
+wire csr_write_enable_d;                        
+reg csr_write_enable_x;
+wire csr_write_enable_q_x;
+  
+       
+
+
+
+  
+
+wire bus_error_d;                               
+reg bus_error_x;
+reg data_bus_error_exception_m;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] memop_pc_w;
+ 
+
+
+reg [ (32-1):0] d_result_0;                
+reg [ (32-1):0] d_result_1;                
+reg [ (32-1):0] x_result;                  
+reg [ (32-1):0] m_result;                  
+reg [ (32-1):0] w_result;                  
+
+reg [ (32-1):0] operand_0_x;               
+reg [ (32-1):0] operand_1_x;               
+reg [ (32-1):0] store_operand_x;           
+reg [ (32-1):0] operand_m;                 
+reg [ (32-1):0] operand_w;                 
+
+
+  
+
+reg [ (32-1):0] reg_data_live_0;          
+reg [ (32-1):0] reg_data_live_1;  
+reg use_buf;                                    
+reg [ (32-1):0] reg_data_buf_0;
+reg [ (32-1):0] reg_data_buf_1;
+ 
+
+  
+
+ 
+     
+
+
+wire [ (32-1):0] reg_data_0;               
+wire [ (32-1):0] reg_data_1;               
+reg [ (32-1):0] bypass_data_0;             
+reg [ (32-1):0] bypass_data_1;             
+wire reg_write_enable_q_w;
+
+reg interlock;                                  
+
+wire stall_a;                                   
+wire stall_f;                                   
+wire stall_d;                                   
+wire stall_x;                                   
+wire stall_m;                                   
+
+
+wire adder_op_d;                                
+reg adder_op_x;                                 
+reg adder_op_x_n;                               
+wire [ (32-1):0] adder_result_x;           
+wire adder_overflow_x;                          
+wire adder_carry_n_x;                           
+
+
+wire [ 3:0] logic_op_d;           
+reg [ 3:0] logic_op_x;            
+wire [ (32-1):0] logic_result_x;           
+
+  
+
+
+wire [ (32-1):0] sextb_result_x;           
+wire [ (32-1):0] sexth_result_x;           
+wire [ (32-1):0] sext_result_x;            
+ 
+
+
+
+  
+
+  
+                                   
+                                     
+
+
+wire direction_d;                               
+reg direction_x;                                        
+wire [ (32-1):0] shifter_result_m;         
+ 
+
+  
+                               
+ 
+                              
+ 
+
+
+  
+           
+
+
+
+
+  
+
+wire [ (32-1):0] multiplier_result_w;      
+ 
+
+  
+                                 
+ 
+
+
+
+
+  
+
+wire divide_d;                                  
+wire divide_q_d;
+wire modulus_d;
+wire modulus_q_d;
+wire divide_by_zero_x;                          
+ 
+
+
+
+  
+
+wire mc_stall_request_x;                        
+wire [ (32-1):0] mc_result_x;
+ 
+
+
+
+  
+
+wire [ (32-1):0] interrupt_csr_read_data_x;
+ 
+
+wire [ (32-1):0] cfg;                      
+wire [ (32-1):0] cfg2;                     
+  
+                          
+
+
+reg [ (32-1):0] csr_read_data_x;           
+
+
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                       
+  
+                          
+
+
+  
+
+wire [ (32-1):0] instruction_f;     
+ 
+
+
+
+wire [ (32-1):0] instruction_d;     
+  
+
+wire iflush;                                    
+wire icache_stall_request;                      
+wire icache_restart_request;                    
+wire icache_refill_request;                     
+wire icache_refilling;                          
+ 
+
+
+
+  
+
+wire dflush_x;                                  
+reg dflush_m;                                    
+wire dcache_stall_request;                      
+wire dcache_restart_request;                    
+wire dcache_refill_request;                     
+wire dcache_refilling;                          
+ 
+
+wire [ (32-1):0] load_data_w;              
+wire stall_wb_load;                             
+
+
+  
+ 
+          
+          
+
+ 
+                      
+        
+                    
+                           
+  
+ 
+  
+  
+ 
+
+ 
+                                 
+
+
+
+
+
+wire raw_x_0;                                   
+wire raw_x_1;                                   
+wire raw_m_0;                                   
+wire raw_m_1;                                   
+wire raw_w_0;                                   
+wire raw_w_1;                                   
+
+
+wire cmp_zero;                                  
+wire cmp_negative;                              
+wire cmp_overflow;                              
+wire cmp_carry_n;                               
+reg condition_met_x;                            
+reg condition_met_m;
+  
+    
+wire branch_taken_x;                            
+ 
+
+wire branch_taken_m;                            
+
+wire kill_f;                                    
+wire kill_d;                                    
+wire kill_x;                                    
+wire kill_m;                                    
+wire kill_w;                                    
+
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;                 
+  
+                  
+
+
+reg [ (3-1):0] eid_x;                      
+  
+                        
+                        
+
+
+
+  
+ 
+                                      
+
+                                      
+ 
+ 
+                                
+                                 
+                          
+ 
+ 
+ 
+                      
+ 
+ 
+ 
+
+
+wire exception_x;                               
+reg exception_m;
+reg exception_w;
+wire exception_q_w;
+ 
+
+
+  
+  
+                            
+
+ 
+                            
+
+
+
+  
+
+wire interrupt_exception;                       
+ 
+
+  
+                       
+                       
+
+
+  
+
+   reg [ (32-1):0] data_bus_error_addr;
+   
+wire instruction_bus_error_exception;           
+wire data_bus_error_exception;                  
+ 
+
+  
+
+wire divide_by_zero_exception;                  
+ 
+
+wire system_call_exception;                     
+
+  
+
+reg data_bus_error_seen;                        
+ 
+
+
+   
+    
+
+
+     
+  
+                          
+   
+            
+   
+                          
+   
+
+    	      
+    	      
+    	      
+    	      
+    	      
+    	      
+   
+   
+
+
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+lm32_instruction_unit_full #(
+    .eba_reset              (eba_reset),
+    .associativity          (icache_associativity),
+    .sets                   (icache_sets),
+    .bytes_per_line         (icache_bytes_per_line),
+    .base_address           (icache_base_address),
+    .limit                  (icache_limit)
+  ) instruction_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .stall_d                (stall_d),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .valid_f                (valid_f),
+    .valid_d                (valid_d),
+    .kill_f                 (kill_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .branch_predict_address_d (branch_predict_address_d),
+  
+    
+    .branch_taken_x         (branch_taken_x),
+    .branch_target_x        (branch_target_x),
+ 
+
+    .exception_m            (exception_m),
+    .branch_taken_m         (branch_taken_m),
+    .branch_mispredict_taken_m (branch_mispredict_taken_m),
+    .branch_target_m        (branch_target_m),
+  
+
+    .iflush                 (iflush),
+ 
+
+  
+
+    .dcache_restart_request (dcache_restart_request),
+    .dcache_refill_request  (dcache_refill_request),
+    .dcache_refilling       (dcache_refilling),
+ 
+        
+  
+
+    
+    .i_dat_i                (I_DAT_I),
+    .i_ack_i                (I_ACK_I),
+    .i_err_i                (I_ERR_I),
+    .i_rty_i                (I_RTY_I),
+ 
+
+  
+           
+          
+            
+               
+
+
+    
+    
+    .pc_f                   (pc_f),
+    .pc_d                   (pc_d),
+    .pc_x                   (pc_x),
+    .pc_m                   (pc_m),
+    .pc_w                   (pc_w),
+  
+
+    .icache_stall_request   (icache_stall_request),
+    .icache_restart_request (icache_restart_request),
+    .icache_refill_request  (icache_refill_request),
+    .icache_refilling       (icache_refilling),
+ 
+
+  
+
+    
+    .i_dat_o                (I_DAT_O),
+    .i_adr_o                (I_ADR_O),
+    .i_cyc_o                (I_CYC_O),
+    .i_sel_o                (I_SEL_O),
+    .i_stb_o                (I_STB_O),
+    .i_we_o                 (I_WE_O),
+    .i_cti_o                (I_CTI_O),
+    .i_lock_o               (I_LOCK_O),
+    .i_bte_o                (I_BTE_O),
+ 
+ 
+
+  
+    
+    
+    
+
+
+		      	      
+  
+             
+       
+
+
+  
+
+    .bus_error_d            (bus_error_d),
+ 
+
+  
+
+    .instruction_f          (instruction_f),
+ 
+
+
+		      
+    .instruction_d          (instruction_d)
+
+
+		      
+    );
+
+
+lm32_decoder_full decoder (
+    
+    .instruction            (instruction_d),
+    
+    .d_result_sel_0         (d_result_sel_0_d),
+    .d_result_sel_1         (d_result_sel_1_d),
+    .x_result_sel_csr       (x_result_sel_csr_d),
+  
+
+    .x_result_sel_mc_arith  (x_result_sel_mc_arith_d),
+ 
+
+      
+         
+
+
+  
+
+    .x_result_sel_sext      (x_result_sel_sext_d),
+ 
+    
+    .x_result_sel_logic     (x_result_sel_logic_d),
+  
+          
+
+
+    .x_result_sel_add       (x_result_sel_add_d),
+    .m_result_sel_compare   (m_result_sel_compare_d),
+  
+
+    .m_result_sel_shift     (m_result_sel_shift_d),  
+ 
+    
+    .w_result_sel_load      (w_result_sel_load_d),
+  
+
+    .w_result_sel_mul       (w_result_sel_mul_d),
+ 
+
+    .x_bypass_enable        (x_bypass_enable_d),
+    .m_bypass_enable        (m_bypass_enable_d),
+    .read_enable_0          (read_enable_0_d),
+    .read_idx_0             (read_idx_0_d),
+    .read_enable_1          (read_enable_1_d),
+    .read_idx_1             (read_idx_1_d),
+    .write_enable           (write_enable_d),
+    .write_idx              (write_idx_d),
+    .immediate              (immediate_d),
+    .branch_offset          (branch_offset_d),
+    .load                   (load_d),
+    .store                  (store_d),
+    .size                   (size_d),
+    .sign_extend            (sign_extend_d),
+    .adder_op               (adder_op_d),
+    .logic_op               (logic_op_d),
+  
+
+    .direction              (direction_d),
+ 
+
+  
+                 
+                
+
+
+  
+                   
+
+
+  
+
+    .divide                 (divide_d),
+    .modulus                (modulus_d),
+ 
+
+    .branch                 (branch_d),
+    .bi_unconditional       (bi_unconditional),
+    .bi_conditional         (bi_conditional),
+    .branch_reg             (branch_reg_d),
+    .condition              (condition_d),
+  
+               
+
+
+    .scall                  (scall_d),
+    .eret                   (eret_d),
+  
+                       
+
+
+  
+                
+
+
+    .csr_write_enable       (csr_write_enable_d)
+    ); 
+
+
+lm32_load_store_unit_full #(
+    .associativity          (dcache_associativity),
+    .sets                   (dcache_sets),
+    .bytes_per_line         (dcache_bytes_per_line),
+    .base_address           (dcache_base_address),
+    .limit                  (dcache_limit)
+  ) load_store_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .kill_x                 (kill_x),
+    .kill_m                 (kill_m),
+    .exception_m            (exception_m),
+    .store_operand_x        (store_operand_x),
+    .load_store_address_x   (adder_result_x),
+    .load_store_address_m   (operand_m),
+    .load_store_address_w   (operand_w[1:0]),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_q_x               (load_q_x),
+    .store_q_x              (store_q_x),
+    .load_q_m               (load_q_m),
+    .store_q_m              (store_q_m),
+    .sign_extend_x          (sign_extend_x),
+    .size_x                 (size_x),
+  
+
+    .dflush                 (dflush_m),
+ 
+
+
+  
+    
+    
+    
+    
+    
+    
+    
+
+
+		     
+    
+    .d_dat_i                (D_DAT_I),
+    .d_ack_i                (D_ACK_I),
+    .d_err_i                (D_ERR_I),
+    .d_rty_i                (D_RTY_I),
+    
+    
+  
+
+    .dcache_refill_request  (dcache_refill_request),
+    .dcache_restart_request (dcache_restart_request),
+    .dcache_stall_request   (dcache_stall_request),
+    .dcache_refilling       (dcache_refilling),
+ 
+    
+    .load_data_w            (load_data_w),
+    .stall_wb_load          (stall_wb_load),
+    
+    .d_dat_o                (D_DAT_O),
+    .d_adr_o                (D_ADR_O),
+    .d_cyc_o                (D_CYC_O),
+    .d_sel_o                (D_SEL_O),
+    .d_stb_o                (D_STB_O),
+    .d_we_o                 (D_WE_O),
+    .d_cti_o                (D_CTI_O),
+    .d_lock_o               (D_LOCK_O),
+    .d_bte_o                (D_BTE_O)
+    );      
+       
+
+lm32_adder adder (
+    
+    .adder_op_x             (adder_op_x),
+    .adder_op_x_n           (adder_op_x_n),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .adder_result_x         (adder_result_x),
+    .adder_carry_n_x        (adder_carry_n_x),
+    .adder_overflow_x       (adder_overflow_x)
+    );
+
+
+lm32_logic_op logic_op (
+    
+    .logic_op_x             (logic_op_x),
+    .operand_0_x            (operand_0_x),
+
+    .operand_1_x            (operand_1_x),
+    
+    .logic_result_x         (logic_result_x)
+    );
+              
+  
+
+
+lm32_shifter shifter (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .direction_x            (direction_x),
+    .sign_extend_x          (sign_extend_x),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .shifter_result_m       (shifter_result_m)
+    );
+ 
+
+
+  
+
+
+lm32_multiplier multiplier (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .operand_0              (d_result_0),
+    .operand_1              (d_result_1),
+    
+    .result                 (multiplier_result_w)    
+    );
+ 
+
+
+  
+
+
+lm32_mc_arithmetic_full mc_arithmetic (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_d                (stall_d),
+    .kill_x                 (kill_x),
+  
+                  
+    .divide_d               (divide_q_d),
+    .modulus_d              (modulus_q_d),
+ 
+
+          
+                 
+
+
+  
+               
+              
+              
+
+    
+    .operand_0_d            (d_result_0),
+    .operand_1_d            (d_result_1),
+    
+    .result_x               (mc_result_x),
+  
+                  
+    .divide_by_zero_x       (divide_by_zero_x),
+ 
+
+    .stall_request_x        (mc_stall_request_x)
+    );
+ 
+
+              
+  
+
+
+lm32_interrupt_full interrupt_unit (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    
+    .interrupt              (interrupt),
+    
+    .stall_x                (stall_x),
+  
+         
+            
+
+
+    .exception              (exception_q_w), 
+ 
+
+    .eret_q_x               (eret_q_x),
+  
+                   
+
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    
+    .interrupt_exception    (interrupt_exception),
+    
+    .csr_read_data          (interrupt_csr_read_data_x)
+    );
+ 
+
+
+  
+      
+      
+        
+   
+
+
+
+
+  
+
+  
+    
+                      
+                      
+    
+                   
+                
+                 
+            
+    
+ 
+                        
+             
+           
+                    
+
+ 
+             
+       
+
+ 
+                
+    
+    
+    
+ 
+          
+          
+
+ 
+      
+        
+                   
+           
+          
+            
+               
+
+ 
+                 
+                 
+
+    
+                 
+            
+    
+
+
+
+  
+
+ 
+                
+                
+    
+    
+                       
+                      
+                       
+                     
+                    
+       
+         
+             
+                      
+  
+	       
+      
+        
+                   
+	      
+	       
+      
+        
+                   
+	      
+
+ 
+                   
+                   
+                    
+                
+                        
+ 
+      
+
+
+    
+ 
+                      
+
+                      
+                   
+                   
+    
+
+
+
+
+
+  
+
+   
+           
+            
+          
+            
+
+
+             
+              
+    
+
+   wire [31:0] regfile_data_0, regfile_data_1;
+   reg [31:0]  w_result_d;
+   reg 	       regfile_raw_0, regfile_raw_0_nxt;
+   reg 	       regfile_raw_1, regfile_raw_1_nxt;
+   
+   
+             
+          
+
+   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
+     begin
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[25:21]))
+	  regfile_raw_0_nxt = 1'b1;
+	else
+	  regfile_raw_0_nxt = 1'b0;
+	
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[20:16]))
+	  regfile_raw_1_nxt = 1'b1;
+	else
+	  regfile_raw_1_nxt = 1'b0;
+     end
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_0 or w_result_d or regfile_data_0)
+     if (regfile_raw_0)
+       reg_data_live_0 = w_result_d;
+     else
+       reg_data_live_0 = regfile_data_0;
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_1 or w_result_d or regfile_data_1)
+     if (regfile_raw_1)
+       reg_data_live_1 = w_result_d;
+     else
+       reg_data_live_1 = regfile_data_1;
+   
+   
+     
+
+   always @(posedge clk_i  )
+     if (rst_i ==  1'b1)
+       begin
+	  regfile_raw_0 <= 1'b0;
+	  regfile_raw_1 <= 1'b0;
+	  w_result_d <= 32'b0;
+       end
+     else
+       begin
+	  regfile_raw_0 <= regfile_raw_0_nxt;
+	  regfile_raw_1 <= regfile_raw_1_nxt;
+	  w_result_d <= w_result;
+       end
+   
+   
+      
+
+   
+   lm32_dp_ram
+     #(
+       
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_0
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[25:21]),
+      
+      .rdata_o	(regfile_data_0)
+      );
+
+   lm32_dp_ram
+     #(
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_1
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[20:16]),
+      
+      .rdata_o	(regfile_data_1)
+      );
+ 
+
+
+  
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+   
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+
+
+
+
+
+
+
+
+  
+
+
+assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
+assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
+ 
+
+  
+
+ 
+
+   
+   
+
+
+
+
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w ==  1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w ==  1'b1);
+
+
+always @(*)
+begin
+    if (   (   (x_bypass_enable_x ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_x_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_x_1 ==  1'b1))
+               )
+           )
+        || (   (m_bypass_enable_m ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_m_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_m_1 ==  1'b1))
+               )
+           )
+       )
+        interlock =  1'b1;
+    else
+        interlock =  1'b0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_0 ==  1'b1)        
+        bypass_data_0 = x_result;
+    else if (raw_m_0 ==  1'b1)
+        bypass_data_0 = m_result;
+    else if (raw_w_0 ==  1'b1)
+        bypass_data_0 = w_result;
+    else
+        bypass_data_0 = reg_data_0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_1 ==  1'b1)
+        bypass_data_1 = x_result;
+    else if (raw_m_1 ==  1'b1)
+        bypass_data_1 = m_result;
+    else if (raw_w_1 ==  1'b1)
+        bypass_data_1 = w_result;
+    else
+        bypass_data_1 = reg_data_1;
+end
+
+   
+          
+       
+       
+     
+
+   assign branch_predict_d = bi_unconditional | bi_conditional;
+   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
+   
+   
+   assign branch_target_d = pc_d + branch_offset_d;
+
+   
+   
+   
+   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
+
+
+always @(*)
+begin
+    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
+    case (d_result_sel_1_d)
+     2'b00:      d_result_1 = { 32{1'b0}};
+     2'b01:     d_result_1 = bypass_data_1;
+     2'b10: d_result_1 = immediate_d;
+    default:                        d_result_1 = { 32{1'bx}};
+    endcase
+end
+
+      
+
+   
+   
+
+
+
+  
+
+
+assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
+assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
+assign sext_result_x = size_x ==  2'b00 ? sextb_result_x : sexth_result_x;
+ 
+
+
+  
+
+      
+
+
+
+
+assign cmp_zero = operand_0_x == operand_1_x;
+assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_overflow = adder_overflow_x;
+assign cmp_carry_n = adder_carry_n_x;
+always @(*)
+begin
+    case (condition_x)
+     3'b000:   condition_met_x =  1'b1;
+     3'b110:   condition_met_x =  1'b1;
+     3'b001:    condition_met_x = cmp_zero;
+     3'b111:   condition_met_x = !cmp_zero;
+     3'b010:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+     3'b101:   condition_met_x = cmp_carry_n && !cmp_zero;
+     3'b011:   condition_met_x = cmp_negative == cmp_overflow;
+     3'b100:  condition_met_x = cmp_carry_n;
+    default:              condition_met_x = 1'bx;
+    endcase 
+end
+
+
+always @(*)
+begin
+    x_result =   x_result_sel_add_x ? adder_result_x 
+               : x_result_sel_csr_x ? csr_read_data_x
+  
+
+               : x_result_sel_sext_x ? sext_result_x
+ 
+
+  
+                  
+
+
+  
+                  
+
+
+  
+
+               : x_result_sel_mc_arith_x ? mc_result_x
+ 
+
+               : logic_result_x;
+end
+
+
+always @(*)
+begin
+    m_result =   m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
+  
+
+               : m_result_sel_shift_m ? shifter_result_m
+ 
+
+               : operand_m; 
+end
+
+
+always @(*)
+begin
+    w_result =    w_result_sel_load_w ? load_data_w
+  
+
+                : w_result_sel_mul_w ? multiplier_result_w
+ 
+
+                : operand_w;
+end
+
+  
+    
+
+assign branch_taken_x =      (stall_x ==  1'b0)
+                          && (   (branch_x ==  1'b1)
+                              && ((condition_x ==  3'b000) || (condition_x ==  3'b110))
+                              && (valid_x ==  1'b1)
+                              && (branch_predict_x ==  1'b0)
+                             ); 
+ 
+
+
+
+assign branch_taken_m =      (stall_m ==  1'b0) 
+                          && (   (   (branch_m ==  1'b1) 
+                                  && (valid_m ==  1'b1)
+                                  && (   (   (condition_met_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b0)
+					 )
+				      || (   (condition_met_m ==  1'b0)
+					  && (branch_predict_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b1)
+					 )
+				     )
+                                 ) 
+                              || (exception_m ==  1'b1)
+                             );
+
+
+assign branch_mispredict_taken_m =    (condition_met_m ==  1'b0)
+                                   && (branch_predict_m ==  1'b1)
+	   			   && (branch_predict_taken_m ==  1'b1);
+   
+
+assign branch_flushX_m =    (stall_m ==  1'b0)
+                         && (   (   (branch_m ==  1'b1) 
+                                 && (valid_m ==  1'b1)
+			         && (   (condition_met_m ==  1'b1)
+				     || (   (condition_met_m ==  1'b0)
+					 && (branch_predict_m ==  1'b1)
+					 && (branch_predict_taken_m ==  1'b1)
+					)
+				    )
+			        )
+			     || (exception_m ==  1'b1)
+			    );
+
+
+assign kill_f =    (   (valid_d ==  1'b1)
+                    && (branch_predict_taken_d ==  1'b1)
+		   )
+                || (branch_taken_m ==  1'b1) 
+  
+    
+                || (branch_taken_x ==  1'b1)
+ 
+
+  
+
+                || (icache_refill_request ==  1'b1) 
+ 
+
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+
+                ;
+assign kill_d =    (branch_taken_m ==  1'b1) 
+  
+    
+                || (branch_taken_x ==  1'b1)
+ 
+
+  
+
+                || (icache_refill_request ==  1'b1)     
+ 
+                
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+
+                ;
+assign kill_x =    (branch_flushX_m ==  1'b1) 
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+
+                ;
+assign kill_m =     1'b0
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+
+                ;                
+assign kill_w =     1'b0
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+                
+                ;
+
+
+
+  
+              
+				         
+				     
+				     
+				 
+ 
+                                 
+
+                              
+
+
+
+  
+     
+
+
+
+  
+
+assign instruction_bus_error_exception = (   (bus_error_x ==  1'b1)
+                                          && (valid_x ==  1'b1)
+                                         );
+assign data_bus_error_exception = data_bus_error_seen ==  1'b1;
+ 
+
+
+  
+
+assign divide_by_zero_exception = divide_by_zero_x ==  1'b1;
+ 
+
+
+assign system_call_exception = (   (scall_x ==  1'b1)
+  
+
+                                && (valid_x ==  1'b1)
+ 
+
+			       );
+
+  
+      
+                            
+                         
+
+     
+ 
+                               
+
+ 
+                               
+                               
+
+ 
+                               
+
+ 
+                                  
+ 
+                                   
+                            
+ 
+ 				   
+				   
+
+                               
+
+                            
+
+         
+
+
+assign exception_x =           (system_call_exception ==  1'b1)
+  
+
+                            || (instruction_bus_error_exception ==  1'b1)
+                            || (data_bus_error_exception ==  1'b1)
+ 
+
+  
+
+                            || (divide_by_zero_exception ==  1'b1)
+ 
+
+  
+
+                            || (   (interrupt_exception ==  1'b1)
+  
+                                   
+
+                            
+  
+
+ 				&& (store_q_m ==  1'b0)
+				&& (D_CYC_O ==  1'b0)
+ 
+
+                               )
+ 
+
+                            ;
+ 
+
+
+  
+ 
+
+ 
+  
+      
+   
+      
+
+
+
+
+always @(*)
+begin
+  
+ 
+       
+          
+    
+     
+ 
+            
+          
+    
+
+            
+          
+    
+
+
+  
+
+         if (data_bus_error_exception ==  1'b1)
+        eid_x =  3'h4;
+    else
+         if (instruction_bus_error_exception ==  1'b1)
+        eid_x =  3'h2;
+    else
+ 
+
+  
+            
+          
+     
+
+
+  
+
+         if (divide_by_zero_exception ==  1'b1)
+        eid_x =  3'h5;
+    else
+ 
+
+  
+
+         if (   (interrupt_exception ==  1'b1)
+  
+                
+
+                            
+            )
+        eid_x =  3'h6;
+    else
+ 
+
+        eid_x =  3'h7;
+end
+
+
+
+assign stall_a = (stall_f ==  1'b1);
+                
+assign stall_f = (stall_d ==  1'b1);
+                
+assign stall_d =   (stall_x ==  1'b1) 
+                || (   (interlock ==  1'b1)
+                    && (kill_d ==  1'b0)
+                   ) 
+		|| (   (   (eret_d ==  1'b1)
+			|| (scall_d ==  1'b1)
+  
+
+			|| (bus_error_d ==  1'b1)
+ 
+
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+  
+		         
+			   
+		       
+		          
+			   
+			   
+			   
+			   
+		       
+                       
+		   
+
+                   
+                || (   (csr_write_enable_d ==  1'b1)
+                    && (load_q_x ==  1'b1)
+                   )                      
+  
+                 
+                 
+                       
+		           
+			 
+			
+		    
+
+	
+                ;
+                
+assign stall_x =    (stall_m ==  1'b1)
+  
+
+                 || (   (mc_stall_request_x ==  1'b1)
+                     && (kill_x ==  1'b0)
+                    ) 
+ 
+
+
+	    
+                 ;
+
+assign stall_m =    (stall_wb_load ==  1'b1)
+  
+                    
+
+
+                 || (   (D_CYC_O ==  1'b1)
+                     && (   (store_m ==  1'b1)
+		         
+          
+          
+
+		  
+	 
+	
+
+          
+           
+          
+       
+
+  
+
+		         || ((store_x ==  1'b1) && (interrupt_exception ==  1'b1))
+ 
+
+                         || (load_m ==  1'b1)
+                         || (load_x ==  1'b1)
+                        ) 
+                    ) 
+ 
+                 
+  
+
+                 || (dcache_stall_request ==  1'b1)     
+ 
+                                    
+  
+
+                 || (icache_stall_request ==  1'b1)     
+                 || ((I_CYC_O ==  1'b1) && ((branch_m ==  1'b1) || (exception_m ==  1'b1))) 
+ 
+ 
+                                
+
+
+                               
+  
+                                  
+                        
+                    
+
+
+  
+                  
+   
+
+                 ;      
+
+
+
+
+  
+
+assign q_d = (valid_d ==  1'b1) && (kill_d ==  1'b0);
+ 
+
+  
+         
+         
+
+
+  
+         
+
+
+  
+
+assign divide_q_d = (divide_d ==  1'b1) && (q_d ==  1'b1);
+assign modulus_q_d = (modulus_d ==  1'b1) && (q_d ==  1'b1);
+ 
+
+assign q_x = (valid_x ==  1'b1) && (kill_x ==  1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x ==  1'b1) && (q_x ==  1'b1);
+assign eret_q_x = (eret_x ==  1'b1) && (q_x ==  1'b1);
+  
+         
+
+
+assign load_q_x = (load_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+                  
+
+
+                  ;
+assign store_q_x = (store_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+                  
+
+
+                  ;
+  
+         
+
+                              
+assign q_m = (valid_m ==  1'b1) && (kill_m ==  1'b0) && (exception_m ==  1'b0);
+assign load_q_m = (load_m ==  1'b1) && (q_m ==  1'b1);
+assign store_q_m = (store_m ==  1'b1) && (q_m ==  1'b1);
+  
+         
+                 
+
+
+assign exception_q_w = ((exception_w ==  1'b1) && (valid_w ==  1'b1));        
+ 
+
+
+assign write_enable_q_x = (write_enable_x ==  1'b1) && (valid_x ==  1'b1) && (branch_flushX_m ==  1'b0);
+assign write_enable_q_m = (write_enable_m ==  1'b1) && (valid_m ==  1'b1);
+assign write_enable_q_w = (write_enable_w ==  1'b1) && (valid_w ==  1'b1);
+
+assign reg_write_enable_q_w = (write_enable_w ==  1'b1) && (kill_w ==  1'b0) && (valid_w ==  1'b1);
+
+
+assign cfg = {
+               6'h02,
+              watchpoints[3:0],
+              breakpoints[3:0],
+              interrupts[5:0],
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+ 
+               1'b1
+ 
+              
+
+
+              };
+
+assign cfg2 = {
+		     30'b0,
+  
+		     
+
+
+		      1'b0,
+ 
+
+  
+		     
+
+
+		      1'b0
+ 
+
+		     };
+   
+
+  
+
+assign iflush = (   (csr_write_enable_d ==  1'b1) 
+                 && (csr_d ==  4 'h3)
+                 && (stall_d ==  1'b0)
+                 && (kill_d ==  1'b0)
+                 && (valid_d ==  1'b1))
+
+  
+             
+                     
+		    
+
+
+		 ;
+ 
+ 
+  
+
+assign dflush_x = (   (csr_write_enable_q_x ==  1'b1) 
+                   && (csr_x ==  4 'h4))
+
+  
+               
+                       
+		      
+
+
+		   ;
+ 
+ 
+
+
+assign csr_d = read_idx_0_d[ (4 -1):0];
+
+
+always @(*)
+begin
+    case (csr_x)
+  
+
+     4 'h0,
+     4 'h1,
+     4 'h2:   csr_read_data_x = interrupt_csr_read_data_x;  
+ 
+
+  
+         
+
+
+     4 'h6:  csr_read_data_x = cfg;
+     4 'h7:  csr_read_data_x = {eba, 8'h00};
+  
+        
+
+
+  
+          
+        
+
+
+     4 'ha: csr_read_data_x = cfg2;
+     4 'hb:  csr_read_data_x = sdb_address;
+  
+
+     4 'hc:  csr_read_data_x = data_bus_error_addr;
+ 
+
+      
+      
+    default:        csr_read_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  4 'h7) && (stall_x ==  1'b0))
+            eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+  
+  
+              
+           
+ 
+  
+              
+           
+ 	 
+
+
+    end
+end
+
+  
+
+   
+
+       
+          
+    
+    
+                   
+              
+  
+   
+              
+           
+  
+   
+              
+           
+         
+ 
+    
+
+
+
+
+
+  
+   
+
+       
+          
+    
+            
+
+
+
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        data_bus_error_seen <=  1'b0;
+    else
+    begin
+        
+        if ((D_ERR_I ==  1'b1) && (D_CYC_O ==  1'b1)) begin
+           data_bus_error_seen <=  1'b1;
+	   data_bus_error_addr <= D_ADR_O;
+	end
+        
+        if ((exception_m ==  1'b1) && (kill_m ==  1'b0))
+            data_bus_error_seen <=  1'b0;
+    end
+end
+ 
+
+ 
+
+
+  
+
+  
+
+always @(*)
+begin
+    if (   (icache_refill_request ==  1'b1) 
+        || (dcache_refill_request ==  1'b1)
+       )
+        valid_a =  1'b0;
+    else if (   (icache_restart_request ==  1'b1) 
+             || (dcache_restart_request ==  1'b1) 
+            ) 
+        valid_a =  1'b1;
+    else 
+        valid_a = !icache_refilling && !dcache_refilling;
+end 
+ 
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+ 
+ 
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        valid_f <=  1'b0;
+        valid_d <=  1'b0;
+        valid_x <=  1'b0;
+        valid_m <=  1'b0;
+        valid_w <=  1'b0;
+    end
+    else
+    begin    
+        if ((kill_f ==  1'b1) || (stall_a ==  1'b0))
+  
+
+            valid_f <= valid_a;    
+ 
+              
+
+            
+        else if (stall_f ==  1'b0)
+            valid_f <=  1'b0;            
+
+        if (kill_d ==  1'b1)
+            valid_d <=  1'b0;
+        else if (stall_f ==  1'b0)
+            valid_d <= valid_f & !kill_f;
+        else if (stall_d ==  1'b0)
+            valid_d <=  1'b0;
+       
+        if (stall_d ==  1'b0)
+            valid_x <= valid_d & !kill_d;
+        else if (kill_x ==  1'b1)
+            valid_x <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_x <=  1'b0;
+
+        if (kill_m ==  1'b1)
+            valid_m <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_m <= valid_x & !kill_x;
+        else if (stall_m ==  1'b0)
+            valid_m <=  1'b0;
+
+        if (stall_m ==  1'b0)
+            valid_w <= valid_m & !kill_m;
+        else 
+            valid_w <=  1'b0;        
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+  
+                 
+
+        
+        operand_0_x <= { 32{1'b0}};
+        operand_1_x <= { 32{1'b0}};
+        store_operand_x <= { 32{1'b0}};
+        branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};        
+        x_result_sel_csr_x <=  1'b0;
+  
+
+        x_result_sel_mc_arith_x <=  1'b0;
+ 
+
+      
+          
+
+
+  
+
+        x_result_sel_sext_x <=  1'b0;
+ 
+    
+  
+          
+
+
+        x_result_sel_add_x <=  1'b0;
+        m_result_sel_compare_x <=  1'b0;
+  
+
+        m_result_sel_shift_x <=  1'b0;
+ 
+    
+        w_result_sel_load_x <=  1'b0;
+  
+
+        w_result_sel_mul_x <=  1'b0;
+ 
+
+        x_bypass_enable_x <=  1'b0;
+        m_bypass_enable_x <=  1'b0;
+        write_enable_x <=  1'b0;
+        write_idx_x <= { 5{1'b0}};
+        csr_x <= { 4 {1'b0}};
+        load_x <=  1'b0;
+        store_x <=  1'b0;
+        size_x <= { 2{1'b0}};
+        sign_extend_x <=  1'b0;
+        adder_op_x <=  1'b0;
+        adder_op_x_n <=  1'b0;
+        logic_op_x <= 4'h0;
+  
+
+        direction_x <=  1'b0;
+ 
+
+  
+          
+
+
+
+        branch_x <=  1'b0;
+        branch_predict_x <=  1'b0;
+        branch_predict_taken_x <=  1'b0;
+        condition_x <=  3'b000;
+  
+          
+
+
+        scall_x <=  1'b0;
+        eret_x <=  1'b0;
+  
+          
+
+
+  
+
+        bus_error_x <=  1'b0;
+        data_bus_error_exception_m <=  1'b0;
+ 
+
+        csr_write_enable_x <=  1'b0;
+        operand_m <= { 32{1'b0}};
+        branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        m_result_sel_compare_m <=  1'b0;
+  
+
+        m_result_sel_shift_m <=  1'b0;
+ 
+    
+        w_result_sel_load_m <=  1'b0;
+  
+
+        w_result_sel_mul_m <=  1'b0;
+ 
+
+        m_bypass_enable_m <=  1'b0;
+        branch_m <=  1'b0;
+        branch_predict_m <=  1'b0;
+	branch_predict_taken_m <=  1'b0;
+        exception_m <=  1'b0;
+        load_m <=  1'b0;
+        store_m <=  1'b0;
+        write_enable_m <=  1'b0;            
+        write_idx_m <= { 5{1'b0}};
+        condition_met_m <=  1'b0;
+  
+
+        dflush_m <=  1'b0;
+ 
+
+  
+          
+                  
+
+
+        operand_w <= { 32{1'b0}};        
+        w_result_sel_load_w <=  1'b0;
+  
+
+        w_result_sel_mul_w <=  1'b0;
+ 
+
+        write_idx_w <= { 5{1'b0}};        
+        write_enable_w <=  1'b0;
+  
+          
+                  
+
+
+        exception_w <=  1'b0;
+ 
+
+  
+
+        memop_pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ 
+
+    end
+    else
+    begin
+        
+       
+        if (stall_x ==  1'b0)
+        begin
+  
+                     
+
+        
+            operand_0_x <= d_result_0;
+            operand_1_x <= d_result_1;
+            store_operand_x <= bypass_data_1;
+            branch_target_x <= branch_reg_d ==  1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;            
+            x_result_sel_csr_x <= x_result_sel_csr_d;
+  
+
+            x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
+ 
+
+      
+              
+
+
+  
+
+            x_result_sel_sext_x <= x_result_sel_sext_d;
+ 
+    
+  
+              
+
+
+            x_result_sel_add_x <= x_result_sel_add_d;
+            m_result_sel_compare_x <= m_result_sel_compare_d;
+  
+
+            m_result_sel_shift_x <= m_result_sel_shift_d;
+ 
+    
+            w_result_sel_load_x <= w_result_sel_load_d;
+  
+
+            w_result_sel_mul_x <= w_result_sel_mul_d;
+ 
+
+            x_bypass_enable_x <= x_bypass_enable_d;
+            m_bypass_enable_x <= m_bypass_enable_d;
+            load_x <= load_d;
+            store_x <= store_d;
+            branch_x <= branch_d;
+	    branch_predict_x <= branch_predict_d;
+	    branch_predict_taken_x <= branch_predict_taken_d;
+	    write_idx_x <= write_idx_d;
+            csr_x <= csr_d;
+            size_x <= size_d;
+            sign_extend_x <= sign_extend_d;
+            adder_op_x <= adder_op_d;
+            adder_op_x_n <= ~adder_op_d;
+            logic_op_x <= logic_op_d;
+  
+
+            direction_x <= direction_d;
+ 
+
+  
+              
+
+
+            condition_x <= condition_d;
+            csr_write_enable_x <= csr_write_enable_d;
+  
+              
+
+
+            scall_x <= scall_d;
+  
+
+            bus_error_x <= bus_error_d;
+ 
+
+            eret_x <= eret_d;
+  
+               
+
+
+            write_enable_x <= write_enable_d;
+        end
+        
+        
+
+        if (stall_m ==  1'b0)
+        begin
+            operand_m <= x_result;
+            m_result_sel_compare_m <= m_result_sel_compare_x;
+  
+
+            m_result_sel_shift_m <= m_result_sel_shift_x;
+ 
+    
+            if (exception_x ==  1'b1)
+            begin
+                w_result_sel_load_m <=  1'b0;
+  
+
+                w_result_sel_mul_m <=  1'b0;
+ 
+
+            end
+            else
+            begin
+                w_result_sel_load_m <= w_result_sel_load_x;
+  
+
+                w_result_sel_mul_m <= w_result_sel_mul_x;
+ 
+
+            end
+            m_bypass_enable_m <= m_bypass_enable_x;
+            load_m <= load_x;
+            store_m <= store_x;
+  
+    
+            branch_m <= branch_x && !branch_taken_x;
+ 
+              
+	      
+	      
+
+
+  
+	   
+	   
+	   
+	   
+	   
+                
+                  
+                
+                  
+             
+                  
+
+
+            if (exception_x ==  1'b1)
+                write_idx_m <=  5'd30;
+            else 
+                write_idx_m <= write_idx_x;
+ 
+
+            condition_met_m <= condition_met_x;
+  
+	      
+	        
+		     
+		        
+	           
+	     
+	           
+	   
+	       
+
+
+            branch_target_m <= exception_x ==  1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
+ 
+
+  
+              
+              
+
+
+  
+
+            dflush_m <= dflush_x;
+ 
+
+  
+ 
+               
+
+
+
+            write_enable_m <= exception_x ==  1'b1 ?  1'b1 : write_enable_x;            
+  
+              
+                      
+
+
+        end
+        
+        
+        if (stall_m ==  1'b0)
+        begin
+            if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+                exception_m <=  1'b1;
+            else 
+                exception_m <=  1'b0;
+  
+
+	   data_bus_error_exception_m <=    (data_bus_error_exception ==  1'b1) 
+  
+					    
+
+
+					 ;
+ 
+
+	end
+                
+        
+  
+
+        operand_w <= exception_m ==  1'b1 ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
+ 
+                 
+
+
+        w_result_sel_load_w <= w_result_sel_load_m;
+  
+
+        w_result_sel_mul_w <= w_result_sel_mul_m;
+ 
+
+        write_idx_w <= write_idx_m;
+  
+          
+          
+ 
+           
+
+
+
+        write_enable_w <= write_enable_m;
+  
+          
+          
+
+
+        exception_w <= exception_m;
+ 
+
+  
+
+        if (   (stall_m ==  1'b0)
+            && (   (load_q_m ==  1'b1) 
+                || (store_q_m ==  1'b1)
+               )
+	   )
+          memop_pc_w <= pc_m;
+ 
+
+    end
+end
+
+  
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        use_buf <=  1'b0;
+        reg_data_buf_0 <= { 32{1'b0}};
+        reg_data_buf_1 <= { 32{1'b0}};
+    end
+    else
+    begin
+        if (stall_d ==  1'b0)
+            use_buf <=  1'b0;
+        else if (use_buf ==  1'b0)
+        begin        
+            reg_data_buf_0 <= reg_data_live_0;
+            reg_data_buf_1 <= reg_data_live_1;
+            use_buf <=  1'b1;
+        end        
+        if (reg_write_enable_q_w ==  1'b1)
+        begin
+            if (write_idx_w == read_idx_0_d)
+                reg_data_buf_0 <= w_result;
+            if (write_idx_w == read_idx_1_d)
+                reg_data_buf_1 <= w_result;
+        end
+    end
+end
+ 
+
+
+  
+
+ 
+
+   
+
+        
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+     
+           
+            
+        
+
+
+
+
+  
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+ 
+          
+
+          
+    
+    
+    
+          
+        
+ 
+               
+
+           
+
+                
+              
+              
+              
+              
+        
+        
+              
+        
+             
+        
+            
+                 
+            
+                
+                  
+                  
+            
+            
+              
+            
+              
+ 
+              
+
+        
+        
+        
+              
+ 
+              
+
+        
+    
+
+
+
+      
+
+
+
+
+
+        
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_load_store_unit_full 
+(
+    
+    clk_i,
+    rst_i,
+ 
+    stall_a,
+    stall_x,
+    stall_m,
+    kill_x,
+    kill_m,
+    exception_m,
+    store_operand_x,
+    load_store_address_x,
+    load_store_address_m,
+    load_store_address_w,
+    load_x,
+    store_x,
+    load_q_x,
+    store_q_x,
+    load_q_m,
+    store_q_m,
+    sign_extend_x,
+    size_x,
+  
+
+    dflush,
+ 
+
+    
+    d_dat_i,
+    d_ack_i,
+    d_err_i,
+    d_rty_i,
+    
+    
+  
+
+    dcache_refill_request,
+    dcache_restart_request,
+    dcache_stall_request,
+    dcache_refilling,
+ 
+    
+  
+    
+    
+    
+    
+    
+    
+    
+
+			     
+    load_data_w,
+    stall_wb_load,
+    
+    d_dat_o,
+    d_adr_o,
+    d_cyc_o,
+    d_sel_o,
+    d_stb_o,
+    d_we_o,
+    d_cti_o,
+    d_lock_o,
+    d_bte_o
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+
+   input clk_i;                                            
+   
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+input kill_x;                                           
+input kill_m;                                           
+input exception_m;                                      
+
+input [ (32-1):0] store_operand_x;                 
+input [ (32-1):0] load_store_address_x;            
+input [ (32-1):0] load_store_address_m;            
+input [1:0] load_store_address_w;                       
+input load_x;                                           
+input store_x;                                          
+input load_q_x;                                         
+input store_q_x;                                        
+input load_q_m;                                         
+input store_q_m;                                        
+input sign_extend_x;                                    
+input [ 1:0] size_x;                          
+
+  
+
+input dflush;                                           
+ 
+
+
+     
+     
+     
+      
+      
+            
+    	 
+   
+
+
+
+   reg 		 [31:0] iram_dat_d0;
+   reg 		 iram_en_d0;
+   wire 	 iram_en;
+   wire [31:0] 	 iram_data;
+   
+   
+   
+input [ (32-1):0] d_dat_i;                         
+input d_ack_i;                                          
+input d_err_i;                                          
+input d_rty_i;                                          
+
+
+
+
+
+  
+
+output dcache_refill_request;                           
+wire   dcache_refill_request;
+output dcache_restart_request;                          
+wire   dcache_restart_request;
+output dcache_stall_request;                            
+wire   dcache_stall_request;
+output dcache_refilling;
+wire   dcache_refilling;
+ 
+
+
+   
+output [ (32-1):0] load_data_w;                    
+reg    [ (32-1):0] load_data_w;
+output stall_wb_load;                                   
+reg    stall_wb_load;
+
+output [ (32-1):0] d_dat_o;                        
+reg    [ (32-1):0] d_dat_o;
+output [ (32-1):0] d_adr_o;                        
+reg    [ (32-1):0] d_adr_o;
+output d_cyc_o;                                         
+reg    d_cyc_o;
+output [ (4-1):0] d_sel_o;                 
+reg    [ (4-1):0] d_sel_o;
+output d_stb_o;                                         
+reg    d_stb_o; 
+output d_we_o;                                          
+reg    d_we_o;
+output [ (3-1):0] d_cti_o;                       
+reg    [ (3-1):0] d_cti_o;
+output d_lock_o;                                        
+reg    d_lock_o;
+output [ (2-1):0] d_bte_o;                       
+wire   [ (2-1):0] d_bte_o;
+
+
+
+
+
+
+reg [ 1:0] size_m;
+reg [ 1:0] size_w;
+reg sign_extend_m;
+reg sign_extend_w;
+reg [ (32-1):0] store_data_x;       
+reg [ (32-1):0] store_data_m;       
+reg [ (4-1):0] byte_enable_x;
+reg [ (4-1):0] byte_enable_m;
+wire [ (32-1):0] data_m;
+reg [ (32-1):0] data_w;
+
+   
+
+  
+
+wire dcache_select_x;                                   
+reg dcache_select_m;
+wire [ (32-1):0] dcache_data_m;                    
+wire [ (32-1):0] dcache_refill_address;            
+reg dcache_refill_ready;                                
+wire [ (3-1):0] first_cycle_type;                
+wire [ (3-1):0] next_cycle_type;                 
+wire last_word;                                         
+wire [ (32-1):0] first_address;                    
+ 
+
+  
+                                      
+ 
+                                      
+                    
+                      
+                        
+                  
+
+
+wire wb_select_x;                                       
+  
+                                      
+
+  
+    
+    
+   
+
+
+
+reg wb_select_m;
+reg [ (32-1):0] wb_data_m;                         
+reg wb_load_complete;                                   
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+
+lm32_dcache_full #(
+    .associativity          (associativity),
+    .sets                   (sets),
+    .bytes_per_line         (bytes_per_line),
+    .base_address           (base_address),
+    .limit                  (limit)
+    ) dcache ( 
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),      
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .address_x              (load_store_address_x),
+    .address_m              (load_store_address_m),
+    .load_q_m               (load_q_m & dcache_select_m),
+    .store_q_m              (store_q_m & dcache_select_m),
+    .store_data             (store_data_m),
+    .store_byte_select      (byte_enable_m & {4{dcache_select_m}}),
+    .refill_ready           (dcache_refill_ready),
+    .refill_data            (wb_data_m),
+    .dflush                 (dflush),
+    
+    .stall_request          (dcache_stall_request),
+    .restart_request        (dcache_restart_request),
+    .refill_request         (dcache_refill_request),
+    .refill_address         (dcache_refill_address),
+    .refilling              (dcache_refilling),
+    .load_data              (dcache_data_m)
+    );
+ 
+
+
+
+
+
+
+
+  
+            
+                             
+
+
+
+  
+            
+                             
+
+      
+        
+
+    
+       
+
+   
+
+    
+     
+       
+     
+         
+     
+
+          
+    
+   
+   
+
+
+   
+  
+
+   assign dcache_select_x =    (load_store_address_x >=  32'h0) 
+                            && (load_store_address_x <=  32'h7fffffff)
+  
+                               
+
+
+  
+                               
+
+
+                     ;
+ 
+
+	  
+   assign wb_select_x =     1'b1
+  
+
+                        && !dcache_select_x 
+ 
+
+  
+                         
+
+
+  
+                         
+
+
+                     ;
+
+
+always @(*)
+begin
+    case (size_x)
+     2'b00:  store_data_x = {4{store_operand_x[7:0]}};
+     2'b11: store_data_x = {2{store_operand_x[15:0]}};
+     2'b10:  store_data_x = store_operand_x;    
+    default:          store_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+always @(*)
+begin
+    casez ({size_x, load_store_address_x[1:0]})
+    { 2'b00, 2'b11}:  byte_enable_x = 4'b0001;
+    { 2'b00, 2'b10}:  byte_enable_x = 4'b0010;
+    { 2'b00, 2'b01}:  byte_enable_x = 4'b0100;
+    { 2'b00, 2'b00}:  byte_enable_x = 4'b1000;
+    { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+    { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+    { 2'b10, 2'b??}:  byte_enable_x = 4'b1111;
+    default:                   byte_enable_x = 4'bxxxx;
+    endcase
+end
+
+  
+      
+            
+
+           
+	                            
+   
+   
+               
+        
+
+
+   
+  
+
+   
+   
+   
+         
+                    
+                       
+                      
+                        
+                     
+                        
+  
+   
+         
+                    
+                       
+                      
+                      
+  
+ 
+
+    
+   
+         
+                    
+                       
+                      
+                      
+  
+
+   
+   assign data_m = wb_select_m ==  1'b1 
+                   ? wb_data_m 
+                   : dcache_data_m;
+   
+
+  
+
+ 
+  
+   
+   
+         
+                     
+                      
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+   
+   
+         
+                     
+                    
+
+  
+   
+      
+  
+ 
+
+
+
+
+always @(*)
+begin
+    casez ({size_w, load_store_address_w[1:0]})
+    { 2'b00, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+    { 2'b00, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+    { 2'b00, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+    { 2'b00, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+    { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+    { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+    { 2'b10, 2'b??}:  load_data_w = data_w;
+    default:                   load_data_w = { 32{1'bx}};
+    endcase
+end
+
+
+assign d_bte_o =  2'b00;
+
+  
+                
+
+generate 
+    case (bytes_per_line)
+    4:
+    begin
+assign first_cycle_type =  3'b111;
+assign next_cycle_type =  3'b111;
+assign last_word =  1'b1;
+assign first_address = {dcache_refill_address[ 32-1:2], 2'b00};
+    end
+    8:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type =  3'b111;
+assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
+assign first_address = {dcache_refill_address[ 32-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
+    end
+    16:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ?  3'b111 :  3'b010;
+assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
+assign first_address = {dcache_refill_address[ 32-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
+    end
+    endcase
+endgenerate
+ 
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        d_cyc_o <=  1'b0;
+        d_stb_o <=  1'b0;
+        d_dat_o <= { 32{1'b0}};
+        d_adr_o <= { 32{1'b0}};
+        d_sel_o <= { 4{ 1'b0}};
+        d_we_o <=  1'b0;
+        d_cti_o <=  3'b111;
+        d_lock_o <=  1'b0;
+        wb_data_m <= { 32{1'b0}};
+        wb_load_complete <=  1'b0;
+        stall_wb_load <=  1'b0;
+  
+                
+        dcache_refill_ready <=  1'b0;
+ 
+                
+    end
+    else 
+    begin
+  
+ 
+        
+        dcache_refill_ready <=  1'b0;
+ 
+                
+        
+        if (d_cyc_o ==  1'b1)
+        begin
+            
+            if ((d_ack_i ==  1'b1) || (d_err_i ==  1'b1))
+            begin
+  
+                
+                if ((dcache_refilling ==  1'b1) && (!last_word))
+                begin
+                    
+                    d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
+                end
+                else
+ 
+                
+                begin
+                    
+                    d_cyc_o <=  1'b0;
+                    d_stb_o <=  1'b0;
+                    d_lock_o <=  1'b0;
+                end
+  
+    
+                d_cti_o <= next_cycle_type;
+                
+                dcache_refill_ready <= dcache_refilling;
+ 
+
+                
+                wb_data_m <= d_dat_i;
+                
+                wb_load_complete <= !d_we_o;
+            end
+            
+        end
+        else 
+        begin
+  
+                
+            if (dcache_refill_request ==  1'b1)
+            begin
+                
+                d_adr_o <= first_address;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= { 32/8{ 1'b1}};
+                d_stb_o <=  1'b1;                
+                d_we_o <=  1'b0;
+                d_cti_o <= first_cycle_type;
+                
+            end
+            else 
+ 
+            
+                 if (   (store_q_m ==  1'b1)
+                     && (stall_m ==  1'b0)
+  
+                        
+
+
+  
+		        
+
+			
+                    )
+            begin
+                
+                d_dat_o <= store_data_m;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b1;
+                d_cti_o <=  3'b111;
+            end        
+            else if (   (load_q_m ==  1'b1) 
+                     && (wb_select_m ==  1'b1) 
+                     && (wb_load_complete ==  1'b0)
+                     
+                    )
+            begin
+                
+                stall_wb_load <=  1'b0;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b0;
+                d_cti_o <=  3'b111;
+            end
+        end
+        
+        if (stall_m ==  1'b0)
+            wb_load_complete <=  1'b0;
+        
+        if ((load_q_x ==  1'b1) && (wb_select_x ==  1'b1) && (stall_x ==  1'b0))
+            stall_wb_load <=  1'b1;
+        
+        if ((kill_m ==  1'b1) || (exception_m ==  1'b1))
+            stall_wb_load <=  1'b0;
+    end
+end
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        sign_extend_m <=  1'b0;
+        size_m <= 2'b00;
+        byte_enable_m <=  1'b0;
+        store_data_m <= { 32{1'b0}};
+  
+
+        dcache_select_m <=  1'b0;
+ 
+
+  
+          
+
+
+  
+          
+			    
+
+
+        wb_select_m <=  1'b0;        
+    end
+    else
+    begin
+        if (stall_m ==  1'b0)
+        begin
+            sign_extend_m <= sign_extend_x;
+            size_m <= size_x;
+            byte_enable_m <= byte_enable_x;    
+            store_data_m <= store_data_x;
+  
+
+            dcache_select_m <= dcache_select_x;
+ 
+
+  
+              
+
+
+  
+              
+			    
+
+
+            wb_select_m <= wb_select_x;
+        end
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        size_w <= 2'b00;
+        data_w <= { 32{1'b0}};
+        sign_extend_w <=  1'b0;
+    end
+    else
+    begin
+        size_w <= size_m;
+
+  
+         
+
+
+        data_w <= data_m;
+
+        sign_extend_w <= sign_extend_m;
+    end
+end
+
+
+
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_decoder_full (
+    
+    instruction,
+    
+    d_result_sel_0,
+    d_result_sel_1,        
+    x_result_sel_csr,
+  
+
+    x_result_sel_mc_arith,
+ 
+    
+      
+    
+
+
+  
+
+    x_result_sel_sext,
+ 
+    
+    x_result_sel_logic,
+  
+    
+
+
+    x_result_sel_add,
+    m_result_sel_compare,
+  
+
+    m_result_sel_shift,  
+ 
+    
+    w_result_sel_load,
+  
+
+    w_result_sel_mul,
+ 
+
+    x_bypass_enable,
+    m_bypass_enable,
+    read_enable_0,
+    read_idx_0,
+    read_enable_1,
+    read_idx_1,
+    write_enable,
+    write_idx,
+    immediate,
+    branch_offset,
+    load,
+    store,
+    size,
+    sign_extend,
+    adder_op,
+    logic_op,
+  
+
+    direction,
+ 
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+
+    divide,
+    modulus,
+ 
+
+    branch,
+    branch_reg,
+    condition,
+    bi_conditional,
+    bi_unconditional,
+  
+    
+
+
+    scall,
+    eret,
+  
+    
+
+
+  
+    
+
+
+    csr_write_enable
+    );
+
+
+
+
+
+input [ (32-1):0] instruction;       
+
+
+
+
+
+output [ 0:0] d_result_sel_0;
+reg    [ 0:0] d_result_sel_0;
+output [ 1:0] d_result_sel_1;
+reg    [ 1:0] d_result_sel_1;
+output x_result_sel_csr;
+reg    x_result_sel_csr;
+  
+
+output x_result_sel_mc_arith;
+reg    x_result_sel_mc_arith;
+ 
+
+      
+ 
+    
+
+
+  
+
+output x_result_sel_sext;
+reg    x_result_sel_sext;
+ 
+
+output x_result_sel_logic;
+reg    x_result_sel_logic;
+  
+ 
+    
+
+
+output x_result_sel_add;
+reg    x_result_sel_add;
+output m_result_sel_compare;
+reg    m_result_sel_compare;
+  
+
+output m_result_sel_shift;
+reg    m_result_sel_shift;
+ 
+
+output w_result_sel_load;
+reg    w_result_sel_load;
+  
+
+output w_result_sel_mul;
+reg    w_result_sel_mul;
+ 
+
+output x_bypass_enable;
+wire   x_bypass_enable;
+output m_bypass_enable;
+wire   m_bypass_enable;
+output read_enable_0;
+wire   read_enable_0;
+output [ (5-1):0] read_idx_0;
+wire   [ (5-1):0] read_idx_0;
+output read_enable_1;
+wire   read_enable_1;
+output [ (5-1):0] read_idx_1;
+wire   [ (5-1):0] read_idx_1;
+output write_enable;
+wire   write_enable;
+output [ (5-1):0] write_idx;
+wire   [ (5-1):0] write_idx;
+output [ (32-1):0] immediate;
+wire   [ (32-1):0] immediate;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+wire   [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+output load;
+wire   load;
+output store;
+wire   store;
+output [ 1:0] size;
+wire   [ 1:0] size;
+output sign_extend;
+wire   sign_extend;
+output adder_op;
+wire   adder_op;
+output [ 3:0] logic_op;
+wire   [ 3:0] logic_op;
+  
+
+output direction;
+wire   direction;
+ 
+
+  
+ 
+   
+ 
+   
+
+
+  
+ 
+   
+
+
+  
+
+output divide;
+wire   divide;
+output modulus;
+wire   modulus;
+ 
+
+output branch;
+wire   branch;
+output branch_reg;
+wire   branch_reg;
+output [ (3-1):0] condition;
+wire   [ (3-1):0] condition;
+output bi_conditional;
+wire bi_conditional;
+output bi_unconditional;
+wire bi_unconditional;
+  
+ 
+   
+
+
+output scall;
+wire   scall;
+output eret;
+wire   eret;
+  
+ 
+   
+
+
+  
+  
+    
+
+
+output csr_write_enable;
+wire   csr_write_enable;
+
+
+
+
+
+wire [ (32-1):0] extended_immediate;       
+wire [ (32-1):0] high_immediate;           
+wire [ (32-1):0] call_immediate;           
+wire [ (32-1):0] branch_immediate;         
+wire sign_extend_immediate;                     
+wire select_high_immediate;                     
+wire select_call_immediate;                     
+
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+  
+
+wire op_divu;
+ 
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+  
+
+wire op_modu;
+ 
+
+  
+
+wire op_mul;
+ 
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+  
+
+wire op_sextb;
+wire op_sexth;
+ 
+
+wire op_sh;
+  
+
+wire op_sl;
+ 
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+  
+ 
+
+
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+  
+
+wire shift;
+ 
+
+  
+ 
+
+
+  
+
+wire sext;
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+assign op_add    = instruction[ 30:26] ==  5'b01101;
+assign op_and    = instruction[ 30:26] ==  5'b01000;
+assign op_andhi  = instruction[ 31:26] ==  6'b011000;
+assign op_b      = instruction[ 31:26] ==  6'b110000;
+assign op_bi     = instruction[ 31:26] ==  6'b111000;
+assign op_be     = instruction[ 31:26] ==  6'b010001;
+assign op_bg     = instruction[ 31:26] ==  6'b010010;
+assign op_bge    = instruction[ 31:26] ==  6'b010011;
+assign op_bgeu   = instruction[ 31:26] ==  6'b010100;
+assign op_bgu    = instruction[ 31:26] ==  6'b010101;
+assign op_bne    = instruction[ 31:26] ==  6'b010111;
+assign op_call   = instruction[ 31:26] ==  6'b110110;
+assign op_calli  = instruction[ 31:26] ==  6'b111110;
+assign op_cmpe   = instruction[ 30:26] ==  5'b11001;
+assign op_cmpg   = instruction[ 30:26] ==  5'b11010;
+assign op_cmpge  = instruction[ 30:26] ==  5'b11011;
+assign op_cmpgeu = instruction[ 30:26] ==  5'b11100;
+assign op_cmpgu  = instruction[ 30:26] ==  5'b11101;
+assign op_cmpne  = instruction[ 30:26] ==  5'b11111;
+  
+
+assign op_divu   = instruction[ 31:26] ==  6'b100011;
+ 
+
+assign op_lb     = instruction[ 31:26] ==  6'b000100;
+assign op_lbu    = instruction[ 31:26] ==  6'b010000;
+assign op_lh     = instruction[ 31:26] ==  6'b000111;
+assign op_lhu    = instruction[ 31:26] ==  6'b001011;
+assign op_lw     = instruction[ 31:26] ==  6'b001010;
+  
+
+assign op_modu   = instruction[ 31:26] ==  6'b110001;
+ 
+
+  
+
+assign op_mul    = instruction[ 30:26] ==  5'b00010;
+ 
+
+assign op_nor    = instruction[ 30:26] ==  5'b00001;
+assign op_or     = instruction[ 30:26] ==  5'b01110;
+assign op_orhi   = instruction[ 31:26] ==  6'b011110;
+assign op_raise  = instruction[ 31:26] ==  6'b101011;
+assign op_rcsr   = instruction[ 31:26] ==  6'b100100;
+assign op_sb     = instruction[ 31:26] ==  6'b001100;
+  
+
+assign op_sextb  = instruction[ 31:26] ==  6'b101100;
+assign op_sexth  = instruction[ 31:26] ==  6'b110111;
+ 
+
+assign op_sh     = instruction[ 31:26] ==  6'b000011;
+  
+
+assign op_sl     = instruction[ 30:26] ==  5'b01111;      
+ 
+
+assign op_sr     = instruction[ 30:26] ==  5'b00101;
+assign op_sru    = instruction[ 30:26] ==  5'b00000;
+assign op_sub    = instruction[ 31:26] ==  6'b110010;
+assign op_sw     = instruction[ 31:26] ==  6'b010110;
+  
+       
+
+
+assign op_wcsr   = instruction[ 31:26] ==  6'b110100;
+assign op_xnor   = instruction[ 30:26] ==  5'b01001;
+assign op_xor    = instruction[ 30:26] ==  5'b00110;
+
+
+assign arith = op_add | op_sub;
+assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
+assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
+assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
+assign bi_unconditional = op_bi;
+assign bra = op_b | bi_unconditional | bi_conditional;
+assign call = op_call | op_calli;
+  
+
+assign shift = op_sl | op_sr | op_sru;
+ 
+
+  
+     
+
+
+  
+   
+     
+
+
+  
+
+assign sext = op_sextb | op_sexth;
+ 
+
+  
+   
+
+
+  
+
+assign divide = op_divu; 
+assign modulus = op_modu;
+ 
+
+assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
+assign store = op_sb | op_sh | op_sw;
+
+
+always @(*)
+begin
+    
+    if (call) 
+        d_result_sel_0 =  1'b1;
+    else 
+        d_result_sel_0 =  1'b0;
+    if (call) 
+        d_result_sel_1 =  2'b00;         
+    else if ((instruction[31] == 1'b0) && !bra) 
+        d_result_sel_1 =  2'b10;
+    else
+        d_result_sel_1 =  2'b01; 
+    
+    x_result_sel_csr =  1'b0;
+  
+
+    x_result_sel_mc_arith =  1'b0;
+ 
+
+  
+      
+
+
+  
+
+    x_result_sel_sext =  1'b0;
+ 
+
+    x_result_sel_logic =  1'b0;
+          
+      
+
+
+    x_result_sel_add =  1'b0;
+    if (op_rcsr)
+        x_result_sel_csr =  1'b1;
+  
+    
+  
+         
+          
+
+
+  
+
+    else if (divide | modulus)
+        x_result_sel_mc_arith =  1'b1;        
+ 
+
+  
+      
+                      
+
+
+ 
+
+  
+      
+                  
+
+
+  
+
+    else if (sext)
+        x_result_sel_sext =  1'b1;
+ 
+        
+    else if (logical) 
+        x_result_sel_logic =  1'b1;
+          
+      
+          
+
+
+    else 
+        x_result_sel_add =  1'b1;        
+    
+    
+
+    m_result_sel_compare = cmp;
+  
+
+    m_result_sel_shift = shift;
+ 
+
+
+    
+    w_result_sel_load = load;
+  
+
+    w_result_sel_mul = op_mul; 
+ 
+
+end
+
+
+assign x_bypass_enable =  arith 
+                        | logical
+  
+                         
+                         
+
+                        
+  
+                         
+
+
+  
+
+                        | divide
+                        | modulus
+ 
+
+  
+                         
+
+                  
+  
+
+                        | sext 
+ 
+                        
+  
+                         
+
+
+                        | op_rcsr
+                        ;
+
+assign m_bypass_enable = x_bypass_enable 
+  
+
+                        | shift
+ 
+
+                        | cmp
+                        ;
+
+assign read_enable_0 = ~(op_bi | op_calli);
+assign read_idx_0 = instruction[25:21];
+
+assign read_enable_1 = ~(op_bi | op_calli | load);
+assign read_idx_1 = instruction[20:16];
+
+assign write_enable = ~(bra | op_raise | store | op_wcsr);
+assign write_idx = call
+                    ? 5'd29
+                    : instruction[31] == 1'b0 
+                        ? instruction[20:16] 
+                        : instruction[15:11];
+                        
+
+assign size = instruction[27:26];
+
+assign sign_extend = instruction[28];                      
+
+assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
+
+assign logic_op = instruction[29:26];
+  
+
+
+assign direction = instruction[29];
+ 
+
+
+assign branch = bra | call;
+assign branch_reg = op_call | op_b;
+assign condition = instruction[28:26];      
+  
+     
+
+
+assign scall = op_raise & instruction[2];
+assign eret = op_b & (instruction[25:21] == 5'd30);
+  
+       
+
+
+  
+
+   
+
+
+
+assign csr_write_enable = op_wcsr;
+
+
+
+assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
+assign select_high_immediate = op_andhi | op_orhi;
+assign select_call_immediate = instruction[31];
+
+assign high_immediate = {instruction[15:0], 16'h0000};
+assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
+assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
+assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
+
+assign immediate = select_high_immediate ==  1'b1 
+                        ? high_immediate 
+                        : extended_immediate;
+   
+assign branch_offset = select_call_immediate ==  1'b1   
+                        ? (call_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0])
+                        : (branch_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0]);
+    
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_icache_full ( 
+    
+    clk_i,
+    rst_i,    
+    stall_a,
+    stall_f,
+    address_a,
+    address_f,
+    read_enable_f,
+    refill_ready,
+    refill_data,
+    iflush,
+  
+    
+
+
+    valid_d,
+    branch_predict_taken_d,
+    
+    stall_request,
+    restart_request,
+    refill_request,
+    refill_address,
+    refilling,
+    inst
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
+localparam addr_set_width = clogb2(sets)-1;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+localparam addr_set_lsb = (addr_offset_msb+1);
+localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
+localparam addr_tag_lsb = (addr_set_msb+1);
+localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
+
+
+
+
+
+input clk_i;                                        
+input rst_i;                                        
+
+input stall_a;                                      
+input stall_f;                                      
+
+input valid_d;                                      
+input branch_predict_taken_d;                       
+   
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;                     
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;                     
+input read_enable_f;                                
+
+input refill_ready;                                 
+input [ (32-1):0] refill_data;          
+
+input iflush;                                       
+  
+                                      
+
+
+   
+
+
+
+
+output stall_request;                               
+wire   stall_request;
+output restart_request;                             
+reg    restart_request;
+output refill_request;                              
+wire   refill_request;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+output refilling;                                   
+reg    refilling;
+output [ (32-1):0] inst;                
+wire   [ (32-1):0] inst;
+
+
+
+
+
+wire enable;
+wire [0:associativity-1] way_mem_we;
+wire [ (32-1):0] way_data[0:associativity-1];
+wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [0:associativity-1] way_valid;
+wire [0:associativity-1] way_match;
+wire miss;
+
+wire [ (addr_set_width-1):0] tmem_read_address;
+wire [ (addr_set_width-1):0] tmem_write_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
+wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
+
+reg [ 3:0] state;
+wire flushing;
+wire check;
+wire refill;
+
+reg [associativity-1:0] refill_way_select;
+reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
+wire last_refill;
+reg [ (addr_set_width-1):0] flush_set;
+
+genvar i;
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+   generate
+      for (i = 0; i < associativity; i = i + 1)
+	begin : memories
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 (32),
+	       .address_width              ( (addr_offset_width+addr_set_width))
+
+) 
+	   way_0_data_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (dmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (dmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i]),
+	      .write_data                 (refill_data),    
+	      
+	      .read_data                  (way_data[i])
+	      );
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 ( (addr_tag_width+1)),
+	       .address_width              ( addr_set_width)
+
+	       ) 
+	   way_0_tag_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (tmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (tmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i] | flushing),
+	      .write_data                 (tmem_write_data),
+	      
+	      .read_data                  ({way_tag[i], way_valid[i]})
+	      );
+	   
+	end
+endgenerate
+
+
+
+
+
+
+generate
+    for (i = 0; i < associativity; i = i + 1)
+    begin : match
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[ addr_tag_msb:addr_tag_lsb],  1'b1});
+    end
+endgenerate
+
+
+generate
+    if (associativity == 1)
+    begin : inst_1
+assign inst = way_match[0] ? way_data[0] : 32'b0;
+    end
+    else if (associativity == 2)
+	 begin : inst_2
+assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
+    end
+endgenerate
+
+
+generate 
+    if (bytes_per_line > 4)
+assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset};
+    else
+assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb];
+endgenerate
+    
+assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb];
+
+
+assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb];
+assign tmem_write_address = flushing 
+                                ? flush_set
+                                : refill_address[ addr_set_msb:addr_set_lsb];
+
+
+generate 
+    if (bytes_per_line > 4)                            
+assign last_refill = refill_offset == {addr_offset_width{1'b1}};
+    else
+assign last_refill =  1'b1;
+endgenerate
+
+
+assign enable = (stall_a ==  1'b0);
+
+
+generate
+    if (associativity == 1) 
+    begin : we_1     
+assign way_mem_we[0] = (refill_ready ==  1'b1);
+    end
+    else
+    begin : we_2
+assign way_mem_we[0] = (refill_ready ==  1'b1) && (refill_way_select[0] ==  1'b1);
+assign way_mem_we[1] = (refill_ready ==  1'b1) && (refill_way_select[1] ==  1'b1);
+    end
+endgenerate                     
+
+
+assign tmem_write_data[ 0] = last_refill & !flushing;
+assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+
+
+assign flushing = |state[1:0];
+assign check = state[2];
+assign refill = state[3];
+
+assign miss = (~(|way_match)) && (read_enable_f ==  1'b1) && (stall_f ==  1'b0) && !(valid_d && branch_predict_taken_d);
+assign stall_request = (check ==  1'b0);
+assign refill_request = (refill ==  1'b1);
+                      
+
+
+
+
+
+generate
+    if (associativity >= 2) 
+    begin : way_select      
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
+    else
+    begin        
+        if (miss ==  1'b1)
+            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
+    end
+end
+    end
+endgenerate
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refilling <=  1'b0;
+    else
+        refilling <= refill;
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  4'b0001;
+        flush_set <= { addr_set_width{1'b1}};
+        refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+        restart_request <=  1'b0;
+    end
+    else 
+    begin
+        case (state)
+
+        
+         4'b0001:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+                state <=  4'b0100;
+            flush_set <= flush_set - 1'b1;
+        end
+
+        
+         4'b0010:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+  
+	       
+                  
+	      
+
+
+		state <=  4'b0100;
+	   
+            flush_set <= flush_set - 1'b1;
+        end
+        
+        
+         4'b0100:
+        begin            
+            if (stall_a ==  1'b0)
+                restart_request <=  1'b0;
+            if (iflush ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b0010;
+            end
+            else if (miss ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b1000;
+            end
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+            begin
+                if (last_refill ==  1'b1)
+                begin
+                    restart_request <=  1'b1;
+                    state <=  4'b0100;
+                end
+            end
+        end
+
+        endcase        
+    end
+end
+
+generate 
+    if (bytes_per_line > 4)
+    begin
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_offset <= {addr_offset_width{1'b0}};
+    else 
+    begin
+        case (state)
+        
+        
+         4'b0100:
+        begin            
+            if (iflush ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+            else if (miss ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+                refill_offset <= refill_offset + 1'b1;
+        end
+
+        endcase        
+    end
+end
+    end
+endgenerate
+   
+endmodule
+
+ 
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+
+
+module lm32_dcache_full ( 
+    
+    clk_i,
+    rst_i,    
+    stall_a,
+    stall_x,
+    stall_m,
+    address_x,
+    address_m,
+    load_q_m,
+    store_q_m,
+    store_data,
+    store_byte_select,
+    refill_ready,
+    refill_data,
+    dflush,
+    
+    stall_request,
+    restart_request,
+    refill_request,
+    refill_address,
+    refilling,
+    load_data
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
+localparam addr_set_width = clogb2(sets)-1;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+localparam addr_set_lsb = (addr_offset_msb+1);
+localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
+localparam addr_tag_lsb = (addr_set_msb+1);
+localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
+
+
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+
+input [ (32-1):0] address_x;                       
+input [ (32-1):0] address_m;                       
+input load_q_m;                                         
+input store_q_m;                                        
+input [ (32-1):0] store_data;                      
+input [ (4-1):0] store_byte_select;        
+
+input refill_ready;                                     
+input [ (32-1):0] refill_data;                     
+
+input dflush;                                           
+
+
+
+
+
+output stall_request;                                   
+wire   stall_request;
+output restart_request;                                 
+reg    restart_request;
+output refill_request;                                  
+reg    refill_request;
+output [ (32-1):0] refill_address;                 
+reg    [ (32-1):0] refill_address;
+output refilling;                                       
+reg    refilling;
+output [ (32-1):0] load_data;                      
+wire   [ (32-1):0] load_data;
+
+
+
+
+
+wire read_port_enable;                                  
+wire write_port_enable;                                 
+wire [0:associativity-1] way_tmem_we;                   
+wire [0:associativity-1] way_dmem_we;                   
+wire [ (32-1):0] way_data[0:associativity-1];      
+wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [0:associativity-1] way_valid;                     
+wire [0:associativity-1] way_match;                     
+wire miss;                                              
+
+wire [ (addr_set_width-1):0] tmem_read_address;        
+wire [ (addr_set_width-1):0] tmem_write_address;       
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;        
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;       
+wire [ ((addr_tag_width+1)-1):0] tmem_write_data;               
+reg [ (32-1):0] dmem_write_data;                   
+
+reg [ 2:0] state;                         
+wire flushing;                                          
+wire check;                                             
+wire refill;                                            
+
+wire valid_store;                                       
+reg [associativity-1:0] refill_way_select;              
+reg [ addr_offset_msb:addr_offset_lsb] refill_offset;           
+wire last_refill;                                       
+reg [ (addr_set_width-1):0] flush_set;                 
+
+genvar i, j;
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+   generate
+      for (i = 0; i < associativity; i = i + 1)    
+	begin : memories
+	   
+           if ( (addr_offset_width+addr_set_width) < 11)
+             begin : data_memories
+		lm32_ram 
+		  #(
+		    
+		    .data_width (32),
+		    .address_width ( (addr_offset_width+addr_set_width))
+
+		    ) way_0_data_ram 
+		    (
+		     
+		     .read_clk (clk_i),
+		     .write_clk (clk_i),
+		     .reset (rst_i),
+		     .read_address (dmem_read_address),
+		     .enable_read (read_port_enable),
+		     .write_address (dmem_write_address),
+		     .enable_write (write_port_enable),
+		     .write_enable (way_dmem_we[i]),
+		     .write_data (dmem_write_data),    
+		     
+		     .read_data (way_data[i])
+		     );    
+             end
+           else
+             begin
+		for (j = 0; j < 4; j = j + 1)    
+		  begin : byte_memories
+		     lm32_ram 
+		       #(
+			 
+			 .data_width (8),
+			 .address_width ( (addr_offset_width+addr_set_width))
+
+			 ) way_0_data_ram 
+			 (
+			  
+			  .read_clk (clk_i),
+			  .write_clk (clk_i),
+			  .reset (rst_i),
+			  .read_address (dmem_read_address),
+			  .enable_read (read_port_enable),
+			  .write_address (dmem_write_address),
+			  .enable_write (write_port_enable),
+			  .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
+			  .write_data (dmem_write_data[(j+1)*8-1:j*8]),    
+			  
+			  .read_data (way_data[i][(j+1)*8-1:j*8])
+			  );
+		  end
+             end
+	   
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width ( (addr_tag_width+1)),
+	       .address_width ( addr_set_width)
+
+	       ) way_0_tag_ram 
+	       (
+		
+		.read_clk (clk_i),
+		.write_clk (clk_i),
+		.reset (rst_i),
+		.read_address (tmem_read_address),
+		.enable_read (read_port_enable),
+		.write_address (tmem_write_address),
+		.enable_write ( 1'b1),
+		.write_enable (way_tmem_we[i]),
+		.write_data (tmem_write_data),
+		
+		.read_data ({way_tag[i], way_valid[i]})
+		);
+	end
+      
+   endgenerate
+
+
+
+
+
+
+generate
+    for (i = 0; i < associativity; i = i + 1)
+    begin : match
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[ addr_tag_msb:addr_tag_lsb],  1'b1});
+    end
+endgenerate
+
+
+generate
+    if (associativity == 1)    
+	 begin : data_1
+assign load_data = way_data[0];
+    end
+    else if (associativity == 2)
+	 begin : data_2
+assign load_data = way_match[0] ? way_data[0] : way_data[1]; 
+    end
+endgenerate
+
+generate
+    if ( (addr_offset_width+addr_set_width) < 11)
+    begin
+
+always @(*)
+begin
+    if (refill ==  1'b1)
+        dmem_write_data = refill_data;
+    else
+    begin
+        dmem_write_data[ 7:0] = store_byte_select[0] ? store_data[ 7:0] : load_data[ 7:0];
+        dmem_write_data[ 15:8] = store_byte_select[1] ? store_data[ 15:8] : load_data[ 15:8];
+        dmem_write_data[ 23:16] = store_byte_select[2] ? store_data[ 23:16] : load_data[ 23:16];
+        dmem_write_data[ 31:24] = store_byte_select[3] ? store_data[ 31:24] : load_data[ 31:24];
+    end
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    if (refill ==  1'b1)
+        dmem_write_data = refill_data;
+    else
+        dmem_write_data = store_data;
+end
+    end
+endgenerate
+
+
+generate 
+     if (bytes_per_line > 4)
+assign dmem_write_address = (refill ==  1'b1) 
+                            ? {refill_address[ addr_set_msb:addr_set_lsb], refill_offset}
+                            : address_m[ addr_set_msb:addr_offset_lsb];
+    else
+assign dmem_write_address = (refill ==  1'b1) 
+                            ? refill_address[ addr_set_msb:addr_set_lsb]
+                            : address_m[ addr_set_msb:addr_offset_lsb];
+endgenerate
+assign dmem_read_address = address_x[ addr_set_msb:addr_offset_lsb];
+
+assign tmem_write_address = (flushing ==  1'b1)
+                            ? flush_set
+                            : refill_address[ addr_set_msb:addr_set_lsb];
+assign tmem_read_address = address_x[ addr_set_msb:addr_set_lsb];
+
+
+generate 
+    if (bytes_per_line > 4)                            
+assign last_refill = refill_offset == {addr_offset_width{1'b1}};
+    else
+assign last_refill =  1'b1;
+endgenerate
+
+
+assign read_port_enable = (stall_x ==  1'b0);
+assign write_port_enable = (refill_ready ==  1'b1) || !stall_m;
+
+
+assign valid_store = (store_q_m ==  1'b1) && (check ==  1'b1);
+
+
+generate
+    if (associativity == 1) 
+    begin : we_1     
+assign way_dmem_we[0] = (refill_ready ==  1'b1) || ((valid_store ==  1'b1) && (way_match[0] ==  1'b1));
+assign way_tmem_we[0] = (refill_ready ==  1'b1) || (flushing ==  1'b1);
+    end 
+    else 
+    begin : we_2
+assign way_dmem_we[0] = ((refill_ready ==  1'b1) && (refill_way_select[0] ==  1'b1)) || ((valid_store ==  1'b1) && (way_match[0] ==  1'b1));
+assign way_dmem_we[1] = ((refill_ready ==  1'b1) && (refill_way_select[1] ==  1'b1)) || ((valid_store ==  1'b1) && (way_match[1] ==  1'b1));
+assign way_tmem_we[0] = ((refill_ready ==  1'b1) && (refill_way_select[0] ==  1'b1)) || (flushing ==  1'b1);
+assign way_tmem_we[1] = ((refill_ready ==  1'b1) && (refill_way_select[1] ==  1'b1)) || (flushing ==  1'b1);
+    end
+endgenerate
+
+
+assign tmem_write_data[ 0] = ((last_refill ==  1'b1) || (valid_store ==  1'b1)) && (flushing ==  1'b0);
+assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+
+
+assign flushing = state[0];
+assign check = state[1];
+assign refill = state[2];
+
+assign miss = (~(|way_match)) && (load_q_m ==  1'b1) && (stall_m ==  1'b0);
+assign stall_request = (check ==  1'b0);
+                      
+
+
+
+
+
+generate
+    if (associativity >= 2) 
+    begin : way_select      
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
+    else
+    begin        
+        if (refill_request ==  1'b1)
+            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
+    end
+end
+    end 
+endgenerate   
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refilling <=  1'b0;
+    else 
+        refilling <= refill;
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  3'b001;
+        flush_set <= { addr_set_width{1'b1}};
+        refill_request <=  1'b0;
+        refill_address <= { 32{1'bx}};
+        restart_request <=  1'b0;
+    end
+    else 
+    begin
+        case (state)
+
+        
+         3'b001:
+        begin
+            if (flush_set == { addr_set_width{1'b0}})
+                state <=  3'b010;
+            flush_set <= flush_set - 1'b1;
+        end
+        
+        
+         3'b010:
+        begin
+            if (stall_a ==  1'b0)
+                restart_request <=  1'b0;
+            if (miss ==  1'b1)
+            begin
+                refill_request <=  1'b1;
+                refill_address <= address_m;
+                state <=  3'b100;
+            end
+            else if (dflush ==  1'b1)
+                state <=  3'b001;
+        end
+
+        
+         3'b100:
+        begin
+            refill_request <=  1'b0;
+            if (refill_ready ==  1'b1)
+            begin
+                if (last_refill ==  1'b1)
+                begin
+                    restart_request <=  1'b1;
+                    state <=  3'b010;
+                end
+            end
+        end
+        
+        endcase        
+    end
+end
+
+generate
+    if (bytes_per_line > 4)
+    begin
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_offset <= {addr_offset_width{1'b0}};
+    else 
+    begin
+        case (state)
+        
+        
+         3'b010:
+        begin
+            if (miss ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+        end
+
+        
+         3'b100:
+        begin
+            if (refill_ready ==  1'b1)
+                refill_offset <= refill_offset + 1'b1;
+        end
+        
+        endcase        
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+ 
+
+
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+                  
+                    
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+               
+                 
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+                    
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+                    
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+                      
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+                  
+                    
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+                   
+              
+                  
+                 
+            
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+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
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+           
+         
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+          
+         
+     
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+            
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+                  
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+                 
+                   
+               
+              
+          
+                   
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+                 
+                   
+                
+                
+                
+               
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+  
+
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+                  
+                 
+         
+     
+     
+              
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+    
+     
+    
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+                                     
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+                                    
+                                   
+      
+                        
+            
+                      
+ 
+ 
+                     
+       
+                   
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+    
+                          
+            
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+                                  
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+                               
+                                       
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+                                    
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+                                        
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+         
+                       
+                
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+     
+         
+                
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+                     
+       
+                   
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+               
+      
+         
+    
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+        
+       
+    
+     
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+        
+   
+    
+   
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+    
+               
+
+ 
+               
+      
+             
+                   
+
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+        
+                   
+    
+   
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+                
+                 
+
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+         
+         
+         
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+               
+      
+   
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+       
+    
+          
+          
+    
+    
+    
+                 
+        
+              
+              
+        
+    
+    
+    
+
+
+
+
+               
+      
+   
+
+       
+    
+          
+          
+    
+    
+    
+           
+        
+               
+                  
+                 
+                  
+        
+      
+
+    
+
+
+
+   
+
+       
+          
+    
+    
+               
+              
+    
+    
+
+ 
+
+   
+
+       
+    
+          
+          
+    
+    
+    
+               
+        
+              
+                
+                  
+             
+                  
+        
+         
+        
+        
+            
+                     
+                       
+                    
+                   
+               
+                   
+        
+        
+        
+            
+                   
+                  
+        
+        
+        
+            
+ 
+               
+                  
+             
+
+                            
+            
+                  
+                  
+            
+        
+        
+        
+            
+ 
+               
+                  
+             
+
+                  
+        
+        
+    
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+     
+    
+   
+  
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+ 
+
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+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
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+ 
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+ 
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+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_instruction_unit_full (
+    
+    clk_i,
+    rst_i,
+    
+    stall_a,
+    stall_f,
+    stall_d,
+    stall_x,
+    stall_m,
+    valid_f,
+    valid_d,
+    kill_f,
+    branch_predict_taken_d,
+    branch_predict_address_d,
+  
+    
+    branch_taken_x,
+    branch_target_x,
+ 
+
+    exception_m,
+    branch_taken_m,
+    branch_mispredict_taken_m,
+    branch_target_m,
+  
+
+    iflush,
+ 
+
+  
+
+    dcache_restart_request,
+    dcache_refill_request,
+    dcache_refilling,
+ 
+        
+  
+
+    
+    i_dat_i,
+    i_ack_i,
+    i_err_i,
+    i_rty_i,
+ 
+
+  
+    
+    
+    
+    
+
+
+    
+    
+    pc_f,
+    pc_d,
+    pc_x,
+    pc_m,
+    pc_w,
+  
+
+    icache_stall_request,
+    icache_restart_request,
+    icache_refill_request,
+    icache_refilling,
+ 
+
+  
+
+    
+    i_dat_o,
+    i_adr_o,
+    i_cyc_o,
+    i_sel_o,
+    i_stb_o,
+    i_we_o,
+    i_cti_o,
+    i_lock_o,
+    i_bte_o,
+ 
+
+  
+    
+    
+    
+
+
+  
+    
+    
+
+
+  
+
+    bus_error_d,
+ 
+
+  
+
+    instruction_f,
+ 
+    
+    instruction_d
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                   
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam eba_reset_minus_4 = eba_reset - 4;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+  
+  
+   
+        
+   
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_f;                                          
+input stall_d;                                          
+input stall_x;                                          
+input stall_m;                                          
+input valid_f;                                          
+input valid_d;                                          
+input kill_f;                                           
+
+input branch_predict_taken_d;                           
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;          
+   
+  
+    
+input branch_taken_x;                                   
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;                   
+ 
+
+input exception_m;
+input branch_taken_m;                                   
+input branch_mispredict_taken_m;                        
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;                   
+
+  
+
+input iflush;                                           
+ 
+
+  
+
+input dcache_restart_request;                           
+input dcache_refill_request;                            
+input dcache_refilling;
+ 
+        
+
+
+  
+
+input [ (32-1):0] i_dat_i;                         
+input i_ack_i;                                          
+input i_err_i;                                          
+input i_rty_i;                                          
+ 
+
+
+  
+                                  
+                                 
+                   
+                      
+
+
+
+
+
+
+        
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
+  
+
+output icache_stall_request;                            
+wire   icache_stall_request;
+output icache_restart_request;                          
+wire   icache_restart_request;
+output icache_refill_request;                           
+wire   icache_refill_request;
+output icache_refilling;                                
+wire   icache_refilling;
+ 
+
+
+  
+
+output [ (32-1):0] i_dat_o;                        
+  
+     
+
+
+wire   [ (32-1):0] i_dat_o;
+ 
+
+output [ (32-1):0] i_adr_o;                        
+reg    [ (32-1):0] i_adr_o;
+output i_cyc_o;                                         
+reg    i_cyc_o; 
+output [ (4-1):0] i_sel_o;                 
+  
+     
+
+
+wire   [ (4-1):0] i_sel_o;
+ 
+
+output i_stb_o;                                         
+reg    i_stb_o;
+output i_we_o;                                          
+  
+    
+
+
+wire   i_we_o;
+ 
+
+output [ (3-1):0] i_cti_o;                       
+reg    [ (3-1):0] i_cti_o;
+output i_lock_o;                                        
+reg    i_lock_o;
+output [ (2-1):0] i_bte_o;                       
+wire   [ (2-1):0] i_bte_o;
+ 
+
+
+  
+                   
+     
+                             
+   
+
+
+
+  
+
+output bus_error_d;                                     
+reg    bus_error_d;
+ 
+
+  
+
+output [ (32-1):0] instruction_f;           
+wire   [ (32-1):0] instruction_f;
+ 
+
+output [ (32-1):0] instruction_d;           
+reg    [ (32-1):0] instruction_d;
+
+
+
+
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;                                
+
+  
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;                     
+ 
+
+
+  
+
+wire icache_read_enable_f;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;              
+reg icache_refill_ready;                                
+reg [ (32-1):0] icache_refill_data;         
+wire [ (32-1):0] icache_data_f;             
+wire [ (3-1):0] first_cycle_type;                
+wire [ (3-1):0] next_cycle_type;                 
+wire last_word;                                         
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;                      
+ 
+ 
+                    
+
+
+
+  
+                                      
+    			     
+   
+
+
+  
+
+ 
+               
+
+
+
+  
+ 
+   
+
+   
+   reg 			     bus_error_f;          
+  
+
+ 
+
+  
+    		       
+
+
+   
+  
+                                         
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+
+lm32_icache_full #(
+    .associativity          (associativity),
+    .sets                   (sets),
+    .bytes_per_line         (bytes_per_line),
+    .base_address           (base_address),
+    .limit                  (limit)
+    ) icache ( 
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),      
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .valid_d                (valid_d),
+    .address_a              (pc_a),
+    .address_f              (pc_f),
+    .read_enable_f          (icache_read_enable_f),
+    .refill_ready           (icache_refill_ready),
+    .refill_data            (icache_refill_data),
+    .iflush                 (iflush),
+    
+    .stall_request          (icache_stall_request),
+    .restart_request        (icache_restart_request),
+    .refill_request         (icache_refill_request),
+    .refill_address         (icache_refill_address),
+    .refilling              (icache_refilling),
+    .inst                   (icache_data_f)
+    );
+ 
+
+
+
+
+
+
+  
+
+   
+   assign icache_read_enable_f =    (valid_f ==  1'b1)
+     && (kill_f ==  1'b0)
+   
+
+   && (dcache_restart_request ==  1'b0)
+  
+                         
+    
+				       
+ 
+       
+				    ;
+ 
+ 
+
+
+always @(*)
+begin
+    
+  
+
+    if (dcache_restart_request ==  1'b1)
+        pc_a = restart_address;
+    else 
+ 
+    
+      if (branch_taken_m ==  1'b1)
+	if ((branch_mispredict_taken_m ==  1'b1) && (exception_m ==  1'b0))
+	  pc_a = pc_x;
+	else
+          pc_a = branch_target_m;
+  
+    
+      else if (branch_taken_x ==  1'b1)
+        pc_a = branch_target_x;
+ 
+
+      else
+	if ( (valid_d ==  1'b1) && (branch_predict_taken_d ==  1'b1) )
+	  pc_a = branch_predict_address_d;
+	else
+  
+
+          if (icache_restart_request ==  1'b1)
+            pc_a = restart_address;
+	  else 
+ 
+        
+            pc_a = pc_f + 1'b1;
+end
+
+
+  
+      
+      
+        
+
+
+
+  
+
+     
+    	      
+
+     
+      
+	  
+       
+	  
+	
+	    
+     
+   
+   
+          
+
+
+  
+   
+
+
+                     
+
+  
+
+assign instruction_f = icache_data_f;
+ 
+   
+
+
+
+ 
+ 
+   
+
+  
+
+  
+
+
+assign i_dat_o = 32'd0;
+assign i_we_o =  1'b0;
+assign i_sel_o = 4'b1111;
+ 
+
+assign i_bte_o =  2'b00;
+ 
+
+
+  
+
+
+generate
+    case (bytes_per_line)
+    4:
+    begin
+assign first_cycle_type =  3'b111;
+assign next_cycle_type =  3'b111;
+assign last_word =  1'b1;
+assign first_address = icache_refill_address;
+    end
+    8:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type =  3'b111;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    16:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ?  3'b111 :  3'b010;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    endcase
+endgenerate
+ 
+
+                     
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        pc_f <= eba_reset_minus_4[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+        pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    end
+    else
+    begin
+        if (stall_f ==  1'b0)
+            pc_f <= pc_a;
+        if (stall_d ==  1'b0)
+            pc_d <= pc_f;
+        if (stall_x ==  1'b0)
+            pc_x <= pc_d;
+        if (stall_m ==  1'b0)
+            pc_m <= pc_x;
+        pc_w <= pc_m;
+    end
+end
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    else
+    begin
+  
+
+  
+        
+            
+            if (dcache_refill_request ==  1'b1)
+                restart_address <= pc_w;
+            else if ((icache_refill_request ==  1'b1) && (!dcache_refilling) && (!dcache_restart_request))
+                restart_address <= icache_refill_address;
+ 
+               
+                  
+
+
+ 
+         
+               
+                  
+
+
+
+    end
+end
+ 
+
+
+
+  
+   
+
+       
+          
+    
+    
+           
+              
+    
+
+
+
+
+  
+    
+                 
+ 
+
+     
+       
+       
+       
+       
+     
+
+   
+
+
+
+  
+
+   
+   
+                
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             i_cyc_o <=  1'b0;
+             i_stb_o <=  1'b0;
+             i_adr_o <= { 32{1'b0}};
+             i_cti_o <=  3'b111;
+             i_lock_o <=  1'b0;
+             icache_refill_data <= { 32{1'b0}};
+             icache_refill_ready <=  1'b0;
+    
+
+             bus_error_f <=  1'b0;
+   
+
+    
+               
+               
+               
+  
+
+	  end
+	else
+	  begin   
+             icache_refill_ready <=  1'b0;
+             
+             if (i_cyc_o ==  1'b1)
+               begin
+		  
+		  if ((i_ack_i ==  1'b1) || (i_err_i ==  1'b1))
+		    begin
+    
+                          
+			 
+			      
+			             
+			        
+			          
+			 
+                       
+  
+
+			 begin
+			    if (last_word ==  1'b1)
+			      begin
+				 
+				 i_cyc_o <=  1'b0;
+				 i_stb_o <=  1'b0;
+				 i_lock_o <=  1'b0;
+			      end
+			    
+			    i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
+			    i_cti_o <= next_cycle_type;
+			    
+			    icache_refill_ready <=  1'b1;
+			    icache_refill_data <= i_dat_i;
+			 end
+		    end
+    
+
+		    
+
+		  if (i_err_i ==  1'b1)
+		    begin
+                       bus_error_f <=  1'b1;
+                       $display ("Instruction bus error. Address: %x", i_adr_o);
+		    end
+		   
+
+   
+
+               end
+             else
+               begin
+		  if ((icache_refill_request ==  1'b1) && (icache_refill_ready ==  1'b0))
+		    begin
+                       
+         
+                         
+  
+
+                       i_adr_o <= {first_address, 2'b00};
+                       i_cyc_o <=  1'b1;
+                       i_stb_o <=  1'b1;                
+                       i_cti_o <= first_cycle_type;
+                       
+    
+
+                       bus_error_f <=  1'b0;
+   
+
+		    end
+    
+		  
+		    
+                              
+			 
+			     
+			         
+			         
+			         
+			         
+			    
+			      
+			      
+			      
+			      
+			      
+			      
+			      
+			 
+		     
+  
+                    
+    
+
+		  
+		  
+     
+    
+		  if (branch_taken_x ==  1'b1)
+                    bus_error_f <=  1'b0;
+    
+
+		  if (branch_taken_m ==  1'b1)
+                    bus_error_f <=  1'b0;
+   
+
+               end
+	  end
+     end
+  
+      
+     
+	   
+	  
+               
+               
+               
+               
+               
+               
+   
+               
+  
+	  
+	
+	     
+             
+                
+               
+		  
+		        
+		    
+                       
+                         
+                         
+                       
+                         
+		    
+   
+		   
+		     
+		    
+                         
+                         
+		       
+		    
+		  
+  
+               
+             
+               
+		  
+		         
+    
+			    
+         
+			 
+		    
+                       
+        
+                         
+  
+                          
+                         
+                         
+   
+                         
+  
+		    
+		  
+		    
+	                      
+    
+			         
+         
+			      
+			 
+   
+			      
+  
+			 
+		    
+               
+	  
+     
+ 
+
+ 
+ 
+
+   
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             instruction_d <= { 32{1'b0}};
+  
+
+             bus_error_d <=  1'b0;
+ 
+
+	  end
+	else
+	  begin
+             if (stall_d ==  1'b0)
+               begin
+		  instruction_d <= instruction_f;
+  
+
+		  bus_error_d <= bus_error_f;
+ 
+
+               end
+	  end
+     end  
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+                              
+                              
+                              
+
+
+                          
+                  
+                 
+              
+             
+                    
+                        
+                        
+
+
+                  
+         
+          
+          
+          
+          
+          
+      
+      
+         
+
+
+
+
+
+  
+    
+    
+    
+     
+    
+    
+    
+ 
+    
+    
+    
+    
+
+ 
+    
+    
+
+ 
+    
+
+    
+ 
+    
+    
+
+ 
+    
+    
+    
+    
+    
+    
+    
+
+ 
+    
+    
+
+    
+    
+    
+
+
+
+
+
+                                             
+                                             
+
+                                          
+                                       
+                        
+                              
+
+ 
+                                
+                                  
+                    
+                                           
+
+ 
+                    
+                              
+
+ 
+                                     
+
+
+
+
+
+       
+ 
+                
+    
+                
+    
+
+ 
+                            
+    
+              
+    
+                          
+    
+                                 
+    
+                                
+    
+                  
+            
+                     
+    
+
+ 
+                                       
+    
+                                       
+    
+
+  
+     
+  
+    
+             
+
+
+
+
+                           
+                         
+                       
+                     
+
+
+
+     
+  
+
+                  
+        
+                       
+        
+                       
+
+
+               
+ 
+         
+  
+  
+  
+  
+                          
+
+
+         
+
+
+
+
+
+ 
+      
+   
+      
+   
+
+                 
+
+                  
+             
+
+   
+
+ 
+   
+
+   
+
+
+                  
+     
+     
+         
+                 
+
+
+
+
+   
+   
+
+
+
+   
+
+       
+    
+          
+          
+          
+          
+    
+    
+    
+          
+          
+          
+          
+    
+
+
+
+   
+
+       
+    
+          
+          
+          
+ 
+          
+          
+          
+          
+
+ 
+          
+          
+
+                  
+          
+          
+          
+          
+
+    
+    
+    
+                  
+               
+        
+             
+            
+            
+                
+                  
+                  
+            
+            
+            
+                
+                  
+            
+            
+        
+
+ 
+        
+           
+        
+              
+              
+        
+
+         
+        
+        
+            
+                 
+            
+                                  
+                 
+ 
+                
+                
+                     
+ 
+                    
+                          
+                    
+                    
+                              
+                          
+                    
+                    
+                          
+                    
+                    
+                              
+                          
+                    
+                    
+                          
+                    
+                    
+                    
+      
+                              
+                                   
+
+                          
+                    
+                    
+                    
+      
+                              
+                                   
+
+                          
+                    
+                                                   
+                
+
+                  
+                
+                
+                      
+                      
+                                    
+                
+                
+                      
+                      
+                
+
+                
+                    
+                                
+            
+        
+ 
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                   
+                      
+                 
+                      
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+             
+            
+            
+            
+                  
+                  
+                  
+            
+            
+            
+            
+                  
+                  
+                  
+            
+            
+            
+                  
+                  
+                  
+            
+            
+        
+        
+        
+               
+                      
+                  
+                  
+                    
+                  
+                  
+            
+            
+        
+        
+              
+              
+              
+            
+
+        
+    
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_interrupt_full (
+    
+    clk_i, 
+    rst_i,
+    
+    interrupt,
+    
+    stall_x,
+  
+    
+    
+
+
+    exception,
+ 
+
+    eret_q_x,
+  
+    
+
+
+    csr,
+    csr_write_data,
+    csr_write_enable,
+    
+    interrupt_exception,
+    
+    csr_read_data
+    );
+
+
+
+
+
+parameter interrupts =  32;         
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [interrupts-1:0] interrupt;               
+
+input stall_x;                                  
+
+  
+                       
+                           
+
+
+input exception;                                
+ 
+
+input eret_q_x;                                 
+  
+                                  
+
+
+
+input [ (4 -1):0] csr;                      
+input [ (32-1):0] csr_write_data;          
+input csr_write_enable;                         
+
+
+
+
+
+output interrupt_exception;                     
+wire   interrupt_exception;
+
+output [ (32-1):0] csr_read_data;          
+reg    [ (32-1):0] csr_read_data;
+
+
+
+
+
+wire [interrupts-1:0] asserted;                 
+
+wire [interrupts-1:0] interrupt_n_exception;
+
+
+
+reg ie;                                         
+reg eie;                                        
+  
+                                         
+
+
+reg [interrupts-1:0] ip;                        
+reg [interrupts-1:0] im;                        
+
+
+
+
+
+
+assign interrupt_n_exception = ip & im;
+
+
+assign interrupt_exception = (|interrupt_n_exception) & ie;
+
+
+assign asserted = ip | interrupt;
+       
+generate
+    if (interrupts > 1) 
+    begin
+
+always @(*)
+begin
+    case (csr)
+     4 'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+                                    
+
+
+                                    1'b0,                                     
+ 
+
+                                    eie, 
+                                    ie
+                                   };
+     4 'h2:  csr_read_data = ip;
+     4 'h1:  csr_read_data = im;
+    default:       csr_read_data = { 32{1'bx}};
+    endcase
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    case (csr)
+     4 'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+                                     
+
+
+                                    1'b0,                                    
+ 
+
+                                    eie, 
+                                    ie
+                                   };
+     4 'h2:  csr_read_data = ip;
+    default:       csr_read_data = { 32{1'bx}};
+      endcase
+end
+    end
+endgenerate
+    
+
+
+
+
+  
+
+   reg [ 10:0] eie_delay  = 0;
+
+   
+generate
+
+   
+    if (interrupts > 1)
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie                   <=  1'b0;
+        eie                  <=  1'b0;
+  
+                           
+
+
+        im                   <= {interrupts{1'b0}};
+        ip                   <= {interrupts{1'b0}};
+       eie_delay             <= 0;
+       
+    end
+    else
+    begin
+        
+        ip                   <= asserted;
+  
+           
+        
+            
+                           
+                            
+        
+            
+        
+            
+                           
+                            
+        
+
+
+        if (exception ==  1'b1)
+        begin
+            
+            eie              <= ie;
+            ie               <=  1'b0;
+        end
+ 
+
+        else if (stall_x ==  1'b0)
+        begin
+
+           if(eie_delay[0])
+             ie              <= eie;
+           
+           eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+            if (eret_q_x ==  1'b1) begin
+                
+               eie_delay[ 10] <=  1'b1;
+               eie_delay[ 10-1:0] <= 0;
+            end
+           
+                      
+           
+  
+                
+                
+                       
+
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  4 'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+                      
+
+
+                end
+                if (csr ==  4 'h1)
+                    im  <= csr_write_data[interrupts-1:0];
+                if (csr ==  4 'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+else
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie              <=  1'b0;
+        eie             <=  1'b0;
+  
+                      
+
+
+        ip              <= {interrupts{1'b0}};
+       eie_delay        <= 0;
+    end
+    else
+    begin
+        
+        ip              <= asserted;
+  
+           
+        
+            
+                      
+                       
+        
+            
+        
+            
+                      
+                       
+        
+
+
+        if (exception ==  1'b1)
+        begin
+            
+            eie         <= ie;
+            ie          <=  1'b0;
+        end
+ 
+
+        else if (stall_x ==  1'b0)
+          begin
+
+             if(eie_delay[0])
+               ie              <= eie;
+           
+             eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+             if (eret_q_x ==  1'b1) begin
+                
+                eie_delay[ 10] <=  1'b1;
+                eie_delay[ 10-1:0] <= 0;
+             end
+           
+  
+                
+                
+                       
+
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  4 'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+                      
+
+
+                end
+                if (csr ==  4 'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	 
+
+ 
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+  
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+
+
+  
+
+  
+
+ 
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+ 
+ 
+                    
+
+  
+                    
+
+
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+ 
+
+
+  
+
+  
+
+ 
+
+ 
+
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+
+  
+
+  
+
+  
+ 
+ 
+
+ 
+
+
+ 
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+  
+
+  
+
+ 
+
+  
+ 
+
+
+  
+ 
+
+
+
+
+  
+
+  
+
+ 
+
+  
+ 
+
+
+
+
+  
+
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+ 
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+ 
+ 
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+ 
+
+
+
+
+
+
+
+
+module lm32_top_full_debug (
+    
+    clk_i,
+    rst_i,
+    
+
+    interrupt,
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+    );
+
+parameter eba_reset = 32'h00000000;
+parameter sdb_address = 32'h00000000;
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+
+input [ (32-1):0] interrupt;          
+
+
+  
+               
+                             
+
+    
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+  
+
+
+
+ 
+  
+
+
+wire [ 7:0] jtag_reg_d;
+wire [ 7:0] jtag_reg_q;
+wire jtag_update;
+wire [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_q;
+wire jtck;
+wire jrstn;
+ 
+
+
+
+  
+
+                     
+                             
+                            
+                   
+                                 
+ 
+                                 
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+   
+
+lm32_cpu_full_debug 
+	#(
+		.eba_reset(eba_reset),
+    .sdb_address(sdb_address)
+	) cpu (
+    
+    .clk_i                 (clk_i),
+  
+                   
+
+
+    .rst_i                 (rst_i),
+    
+  
+
+    .interrupt             (interrupt),
+ 
+
+    
+  
+               
+             
+
+     
+  
+
+    
+    .jtag_clk              (jtck),
+    .jtag_update           (jtag_update),
+    .jtag_reg_q            (jtag_reg_q),
+    .jtag_reg_addr_q       (jtag_reg_addr_q),
+ 
+
+  
+
+     
+    .I_DAT_I               (I_DAT_I),
+    .I_ACK_I               (I_ACK_I),
+    .I_ERR_I               (I_ERR_I),
+    .I_RTY_I               (I_RTY_I),
+ 
+
+    
+    .D_DAT_I               (D_DAT_I),
+    .D_ACK_I               (D_ACK_I),
+    .D_ERR_I               (D_ERR_I),
+    .D_RTY_I               (D_RTY_I),
+    
+  
+                  
+            
+           
+                 
+                
+ 
+                
+
+
+
+  
+
+    .jtag_reg_d            (jtag_reg_d),
+    .jtag_reg_addr_d       (jtag_reg_addr_d),
+ 
+
+      
+                
+               
+            
+            
+
+    
+  
+
+    
+    .I_DAT_O               (I_DAT_O),
+    .I_ADR_O               (I_ADR_O),
+    .I_CYC_O               (I_CYC_O),
+    .I_SEL_O               (I_SEL_O),
+    .I_STB_O               (I_STB_O),
+    .I_WE_O                (I_WE_O),
+    .I_CTI_O               (I_CTI_O),
+    .I_LOCK_O              (I_LOCK_O),
+    .I_BTE_O               (I_BTE_O),
+     
+
+    
+    .D_DAT_O               (D_DAT_O),
+    .D_ADR_O               (D_ADR_O),
+    .D_CYC_O               (D_CYC_O),
+    .D_SEL_O               (D_SEL_O),
+    .D_STB_O               (D_STB_O),
+    .D_WE_O                (D_WE_O),
+    .D_CTI_O               (D_CTI_O),
+    .D_LOCK_O              (D_LOCK_O),
+    .D_BTE_O               (D_BTE_O)
+    );
+   
+  
+		   
+
+jtag_cores jtag_cores (
+    
+    .reg_d                 (jtag_reg_d),
+    .reg_addr_d            (jtag_reg_addr_d),
+    
+    .reg_update            (jtag_update),
+    .reg_q                 (jtag_reg_q),
+    .reg_addr_q            (jtag_reg_addr_q),
+    .jtck                  (jtck),
+    .jrstn                 (jrstn)
+    );
+ 
+        
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+           
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_mc_arithmetic_full_debug (
+    
+    clk_i,
+    rst_i,
+    stall_d,
+    kill_x,
+  
+
+    divide_d,
+    modulus_d,
+ 
+
+  
+    
+
+
+  
+    
+    
+    
+
+
+    operand_0_d,
+    operand_1_d,
+    
+    result_x,
+  
+
+    divide_by_zero_x,
+ 
+
+    stall_request_x
+    );
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+input stall_d;                                  
+input kill_x;                                   
+  
+
+input divide_d;                                 
+input modulus_d;                                
+ 
+
+  
+                                
+
+
+  
+                              
+                             
+                             
+
+
+input [ (32-1):0] operand_0_d;
+input [ (32-1):0] operand_1_d;
+
+
+
+
+
+output [ (32-1):0] result_x;               
+reg    [ (32-1):0] result_x;
+  
+
+output divide_by_zero_x;                        
+reg    divide_by_zero_x;
+ 
+
+output stall_request_x;                         
+wire   stall_request_x;
+
+
+
+
+
+reg [ (32-1):0] p;                         
+reg [ (32-1):0] a;
+reg [ (32-1):0] b;
+  
+
+wire [32:0] t;
+ 
+
+
+reg [ 2:0] state;                 
+reg [5:0] cycles;                               
+
+  
+                               
+                                 
+
+
+
+
+
+
+
+
+assign stall_request_x = state !=  3'b000;
+
+  
+
+
+assign t = {p[ 32-2:0], a[ 32-1]} - b;
+ 
+
+
+  
+
+       
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        cycles <= {6{1'b0}};
+        p <= { 32{1'b0}};
+        a <= { 32{1'b0}};
+        b <= { 32{1'b0}};
+  
+          
+
+
+  
+
+        divide_by_zero_x <=  1'b0;
+ 
+
+        result_x <= { 32{1'b0}};
+        state <=  3'b000;
+    end
+    else
+    begin
+  
+
+        divide_by_zero_x <=  1'b0;
+ 
+
+        case (state)
+         3'b000:
+        begin
+            if (stall_d ==  1'b0)                 
+            begin          
+                cycles <=  32;
+                p <= 32'b0;
+                a <= operand_0_d;
+                b <= operand_1_d;                    
+  
+
+                if (divide_d ==  1'b1)
+                    state <=  3'b011 ;
+                if (modulus_d ==  1'b1)
+                    state <=  3'b010   ;
+ 
+                    
+  
+                   
+                      
+
+
+  
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+
+
+            end            
+        end
+  
+
+         3'b011 :
+        begin
+            if (t[32] == 1'b0)
+            begin
+                p <= t[31:0];
+                a <= {a[ 32-2:0], 1'b1};
+            end
+            else 
+            begin
+                p <= {p[ 32-2:0], a[ 32-1]};
+                a <= {a[ 32-2:0], 1'b0};
+            end
+            result_x <= a;
+            if ((cycles ==  32'd0) || (kill_x ==  1'b1))
+            begin
+                
+                divide_by_zero_x <= b == { 32{1'b0}};
+                state <=  3'b000;
+            end
+            cycles <= cycles - 1'b1;
+        end
+         3'b010   :
+        begin
+            if (t[32] == 1'b0)
+            begin
+                p <= t[31:0];
+                a <= {a[ 32-2:0], 1'b1};
+            end
+            else 
+            begin
+                p <= {p[ 32-2:0], a[ 32-1]};
+                a <= {a[ 32-2:0], 1'b0};
+            end
+            result_x <= p;
+            if ((cycles ==  32'd0) || (kill_x ==  1'b1))
+            begin
+                
+                divide_by_zero_x <= b == { 32{1'b0}};
+                state <=  3'b000;
+            end
+            cycles <= cycles - 1'b1;
+        end
+ 
+        
+  
+        
+        
+               
+                    
+               
+               
+              
+                   
+                  
+                
+        
+
+     
+  
+        
+               
+               
+              
+                   
+                  
+                
+        
+        
+               
+               
+              
+                   
+                  
+                
+        
+
+   
+        endcase
+    end
+end 
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_cpu_full_debug (
+    
+    clk_i,
+  
+    
+
+
+    rst_i,
+  
+    
+
+
+  
+   
+   
+   
+   
+   
+   
+
+
+
+    
+  
+
+    interrupt,
+ 
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    jtag_clk,
+    jtag_update, 
+    jtag_reg_q,
+    jtag_reg_addr_q,
+ 
+
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+  
+    
+    
+    
+    
+    
+ 
+    
+
+
+
+  
+
+    jtag_reg_d,
+    jtag_reg_addr_d,
+ 
+
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+ 
+  
+    
+    
+    
+    
+    
+    
+    
+    
+           
+
+
+		 
+		 
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+
+		 
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                           
+  
+
+parameter deba_reset =  32'h10000000;                         
+ 
+
+parameter sdb_address =   32'h00000000;
+
+  
+
+parameter icache_associativity =  1;     
+parameter icache_sets =  256;                       
+parameter icache_bytes_per_line =  16;   
+parameter icache_base_address =  32'h0;       
+parameter icache_limit =  32'h7fffffff;                     
+ 
+       
+                         
+     
+         
+                       
+
+
+
+  
+
+parameter dcache_associativity =  1;     
+parameter dcache_sets =  256;                       
+parameter dcache_bytes_per_line =  16;   
+parameter dcache_base_address =  32'h0;       
+parameter dcache_limit =  32'h7fffffff;                     
+ 
+       
+                         
+     
+         
+                       
+
+
+
+  
+
+parameter watchpoints =  32'h4;                       
+ 
+   
+
+
+  
+                          
+
+
+parameter breakpoints = 0;
+ 
+
+
+  
+
+parameter interrupts =  32;                         
+ 
+   
+
+
+
+
+
+
+
+input clk_i;                                    
+  
+                                   
+
+    
+input rst_i;                                    
+
+  
+
+input [ (32-1):0] interrupt;          
+ 
+
+
+  
+               
+                             
+
+    
+
+  
+ 
+input jtag_clk;                                 
+input jtag_update;                              
+input [ 7:0] jtag_reg_q;              
+input [2:0] jtag_reg_addr_q;
+ 
+
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+    
+     
+
+
+   
+   
+  
+                   
+     
+                           
+    
+                          
+    
+                 
+     
+                               
+    
+ 
+                               
+    
+
+
+
+
+  
+
+output [ 7:0] jtag_reg_d;
+wire   [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire   [2:0] jtag_reg_addr_d;
+ 
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+
+  
+      
+     
+       
+      
+             
+
+
+   
+
+
+
+
+
+
+  
+
+reg valid_a;                                    
+ 
+
+reg valid_f;                                    
+reg valid_d;                                    
+reg valid_x;                                    
+reg valid_m;                                    
+reg valid_w;                                    
+   
+wire q_x;
+wire [ (32-1):0] immediate_d;              
+wire load_d;                                    
+reg load_x;                                     
+reg load_m;
+wire load_q_x;
+wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
+wire store_d;                                   
+reg store_x;
+reg store_m;
+wire [ 1:0] size_d;                   
+reg [ 1:0] size_x;
+wire branch_d;                                  
+wire branch_predict_d;                          
+wire branch_predict_taken_d;                    
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;   
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
+wire bi_unconditional;
+wire bi_conditional;
+reg branch_x;                                   
+reg branch_predict_x;
+reg branch_predict_taken_x;
+reg branch_m;
+reg branch_predict_m;
+reg branch_predict_taken_m;
+wire branch_mispredict_taken_m;                 
+wire branch_flushX_m;                           
+wire branch_reg_d;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;            
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;             
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+wire [ 0:0] d_result_sel_0_d; 
+wire [ 1:0] d_result_sel_1_d; 
+
+wire x_result_sel_csr_d;                        
+reg x_result_sel_csr_x;
+  
+
+wire q_d;
+wire x_result_sel_mc_arith_d;                   
+reg x_result_sel_mc_arith_x;
+ 
+
+      
+                       
+ 
+
+
+  
+
+wire x_result_sel_sext_d;                       
+reg x_result_sel_sext_x;
+ 
+
+wire x_result_sel_logic_d;                      
+  
+                        
+ 
+
+
+wire x_result_sel_add_d;                        
+reg x_result_sel_add_x;
+wire m_result_sel_compare_d;                    
+reg m_result_sel_compare_x;
+reg m_result_sel_compare_m;
+  
+
+wire m_result_sel_shift_d;                      
+reg m_result_sel_shift_x;
+reg m_result_sel_shift_m;
+ 
+
+wire w_result_sel_load_d;                       
+reg w_result_sel_load_x;
+reg w_result_sel_load_m;
+reg w_result_sel_load_w;
+  
+
+wire w_result_sel_mul_d;                        
+reg w_result_sel_mul_x;
+reg w_result_sel_mul_m;
+reg w_result_sel_mul_w;
+ 
+
+wire x_bypass_enable_d;                         
+reg x_bypass_enable_x;                          
+wire m_bypass_enable_d;                         
+reg m_bypass_enable_x;                          
+reg m_bypass_enable_m;
+wire sign_extend_d;                             
+reg sign_extend_x;
+wire write_enable_d;                            
+reg write_enable_x;
+wire write_enable_q_x;
+reg write_enable_m;
+wire write_enable_q_m;
+reg write_enable_w;
+wire write_enable_q_w;
+wire read_enable_0_d;                           
+wire [ (5-1):0] read_idx_0_d;          
+wire read_enable_1_d;                           
+wire [ (5-1):0] read_idx_1_d;          
+wire [ (5-1):0] write_idx_d;           
+reg [ (5-1):0] write_idx_x;            
+reg [ (5-1):0] write_idx_m;
+reg [ (5-1):0] write_idx_w;
+wire [ (5-1):0] csr_d;                     
+reg  [ (5-1):0] csr_x;                  
+wire [ (3-1):0] condition_d;         
+reg [ (3-1):0] condition_x;          
+  
+
+wire break_d;                                   
+reg break_x;                                    
+ 
+
+wire scall_d;                                   
+reg scall_x;    
+wire eret_d;                                    
+reg eret_x;
+wire eret_q_x;
+  
+ 
+ 
+
+
+  
+
+wire bret_d;                                    
+reg bret_x;
+wire bret_q_x;
+  
+ 
+ 
+
+
+ 
+
+wire csr_write_enable_d;                        
+reg csr_write_enable_x;
+wire csr_write_enable_q_x;
+  
+       
+
+
+
+  
+
+wire bus_error_d;                               
+reg bus_error_x;
+reg data_bus_error_exception_m;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] memop_pc_w;
+ 
+
+
+reg [ (32-1):0] d_result_0;                
+reg [ (32-1):0] d_result_1;                
+reg [ (32-1):0] x_result;                  
+reg [ (32-1):0] m_result;                  
+reg [ (32-1):0] w_result;                  
+
+reg [ (32-1):0] operand_0_x;               
+reg [ (32-1):0] operand_1_x;               
+reg [ (32-1):0] store_operand_x;           
+reg [ (32-1):0] operand_m;                 
+reg [ (32-1):0] operand_w;                 
+
+
+  
+
+reg [ (32-1):0] reg_data_live_0;          
+reg [ (32-1):0] reg_data_live_1;  
+reg use_buf;                                    
+reg [ (32-1):0] reg_data_buf_0;
+reg [ (32-1):0] reg_data_buf_1;
+ 
+
+  
+
+ 
+     
+
+
+wire [ (32-1):0] reg_data_0;               
+wire [ (32-1):0] reg_data_1;               
+reg [ (32-1):0] bypass_data_0;             
+reg [ (32-1):0] bypass_data_1;             
+wire reg_write_enable_q_w;
+
+reg interlock;                                  
+
+wire stall_a;                                   
+wire stall_f;                                   
+wire stall_d;                                   
+wire stall_x;                                   
+wire stall_m;                                   
+
+
+wire adder_op_d;                                
+reg adder_op_x;                                 
+reg adder_op_x_n;                               
+wire [ (32-1):0] adder_result_x;           
+wire adder_overflow_x;                          
+wire adder_carry_n_x;                           
+
+
+wire [ 3:0] logic_op_d;           
+reg [ 3:0] logic_op_x;            
+wire [ (32-1):0] logic_result_x;           
+
+  
+
+
+wire [ (32-1):0] sextb_result_x;           
+wire [ (32-1):0] sexth_result_x;           
+wire [ (32-1):0] sext_result_x;            
+ 
+
+
+
+  
+
+  
+                                   
+                                     
+
+
+wire direction_d;                               
+reg direction_x;                                        
+wire [ (32-1):0] shifter_result_m;         
+ 
+
+  
+                               
+ 
+                              
+ 
+
+
+  
+           
+
+
+
+
+  
+
+wire [ (32-1):0] multiplier_result_w;      
+ 
+
+  
+                                 
+ 
+
+
+
+
+  
+
+wire divide_d;                                  
+wire divide_q_d;
+wire modulus_d;
+wire modulus_q_d;
+wire divide_by_zero_x;                          
+ 
+
+
+
+  
+
+wire mc_stall_request_x;                        
+wire [ (32-1):0] mc_result_x;
+ 
+
+
+
+  
+
+wire [ (32-1):0] interrupt_csr_read_data_x;
+ 
+
+wire [ (32-1):0] cfg;                      
+wire [ (32-1):0] cfg2;                     
+  
+                          
+
+
+reg [ (32-1):0] csr_read_data_x;           
+
+
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                       
+  
+                          
+
+
+  
+
+wire [ (32-1):0] instruction_f;     
+ 
+
+
+
+wire [ (32-1):0] instruction_d;     
+  
+
+wire iflush;                                    
+wire icache_stall_request;                      
+wire icache_restart_request;                    
+wire icache_refill_request;                     
+wire icache_refilling;                          
+ 
+
+
+
+  
+
+wire dflush_x;                                  
+reg dflush_m;                                    
+wire dcache_stall_request;                      
+wire dcache_restart_request;                    
+wire dcache_refill_request;                     
+wire dcache_refilling;                          
+ 
+
+wire [ (32-1):0] load_data_w;              
+wire stall_wb_load;                             
+
+
+  
+
+  
+
+wire [ (32-1):0] jtx_csr_read_data;        
+wire [ (32-1):0] jrx_csr_read_data;        
+ 
+
+  
+
+wire jtag_csr_write_enable;                     
+wire [ (32-1):0] jtag_csr_write_data;      
+wire [ (5-1):0] jtag_csr;                  
+wire jtag_read_enable;                          
+wire [ 7:0] jtag_read_data;
+wire jtag_write_enable;
+wire [ 7:0] jtag_write_data;
+wire [ (32-1):0] jtag_address;
+wire jtag_access_complete;
+ 
+
+  
+
+wire jtag_break;                                
+ 
+
+ 
+
+
+
+wire raw_x_0;                                   
+wire raw_x_1;                                   
+wire raw_m_0;                                   
+wire raw_m_1;                                   
+wire raw_w_0;                                   
+wire raw_w_1;                                   
+
+
+wire cmp_zero;                                  
+wire cmp_negative;                              
+wire cmp_overflow;                              
+wire cmp_carry_n;                               
+reg condition_met_x;                            
+reg condition_met_m;
+  
+    
+wire branch_taken_x;                            
+ 
+
+wire branch_taken_m;                            
+
+wire kill_f;                                    
+wire kill_d;                                    
+wire kill_x;                                    
+wire kill_m;                                    
+wire kill_w;                                    
+
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;                 
+  
+
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;                
+ 
+
+reg [ (3-1):0] eid_x;                      
+  
+                        
+                        
+
+
+
+  
+
+  
+
+wire dc_ss;                                     
+ 
+
+wire dc_re;                                     
+wire bp_match;
+wire wp_match;
+wire exception_x;                               
+reg exception_m;                                
+wire debug_exception_x;                         
+reg debug_exception_m;
+reg debug_exception_w;
+wire debug_exception_q_w;
+wire non_debug_exception_x;                     
+reg non_debug_exception_m;
+reg non_debug_exception_w;
+wire non_debug_exception_q_w;
+ 
+                                
+ 
+ 
+ 
+
+
+
+  
+
+  
+ 
+wire reset_exception;                           
+ 
+
+  
+                            
+
+
+ 
+
+  
+
+wire interrupt_exception;                       
+ 
+
+  
+
+wire breakpoint_exception;                      
+wire watchpoint_exception;                      
+ 
+
+  
+
+   reg [ (32-1):0] data_bus_error_addr;
+   
+wire instruction_bus_error_exception;           
+wire data_bus_error_exception;                  
+ 
+
+  
+
+wire divide_by_zero_exception;                  
+ 
+
+wire system_call_exception;                     
+
+  
+
+reg data_bus_error_seen;                        
+ 
+
+
+   
+    
+
+
+     
+  
+                          
+   
+            
+   
+                          
+   
+
+    	      
+    	      
+    	      
+    	      
+    	      
+    	      
+   
+   
+
+
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+lm32_instruction_unit_full_debug #(
+    .eba_reset              (eba_reset),
+    .associativity          (icache_associativity),
+    .sets                   (icache_sets),
+    .bytes_per_line         (icache_bytes_per_line),
+    .base_address           (icache_base_address),
+    .limit                  (icache_limit)
+  ) instruction_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .stall_d                (stall_d),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .valid_f                (valid_f),
+    .valid_d                (valid_d),
+    .kill_f                 (kill_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .branch_predict_address_d (branch_predict_address_d),
+  
+    
+    .branch_taken_x         (branch_taken_x),
+    .branch_target_x        (branch_target_x),
+ 
+
+    .exception_m            (exception_m),
+    .branch_taken_m         (branch_taken_m),
+    .branch_mispredict_taken_m (branch_mispredict_taken_m),
+    .branch_target_m        (branch_target_m),
+  
+
+    .iflush                 (iflush),
+ 
+
+  
+
+    .dcache_restart_request (dcache_restart_request),
+    .dcache_refill_request  (dcache_refill_request),
+    .dcache_refilling       (dcache_refilling),
+ 
+        
+  
+
+    
+    .i_dat_i                (I_DAT_I),
+    .i_ack_i                (I_ACK_I),
+    .i_err_i                (I_ERR_I),
+    .i_rty_i                (I_RTY_I),
+ 
+
+  
+
+    .jtag_read_enable       (jtag_read_enable),
+    .jtag_write_enable      (jtag_write_enable),
+    .jtag_write_data        (jtag_write_data),
+    .jtag_address           (jtag_address),
+ 
+
+    
+    
+    .pc_f                   (pc_f),
+    .pc_d                   (pc_d),
+    .pc_x                   (pc_x),
+    .pc_m                   (pc_m),
+    .pc_w                   (pc_w),
+  
+
+    .icache_stall_request   (icache_stall_request),
+    .icache_restart_request (icache_restart_request),
+    .icache_refill_request  (icache_refill_request),
+    .icache_refilling       (icache_refilling),
+ 
+
+  
+
+    
+    .i_dat_o                (I_DAT_O),
+    .i_adr_o                (I_ADR_O),
+    .i_cyc_o                (I_CYC_O),
+    .i_sel_o                (I_SEL_O),
+    .i_stb_o                (I_STB_O),
+    .i_we_o                 (I_WE_O),
+    .i_cti_o                (I_CTI_O),
+    .i_lock_o               (I_LOCK_O),
+    .i_bte_o                (I_BTE_O),
+ 
+ 
+
+  
+    
+    
+    
+
+
+		      	      
+  
+
+    .jtag_read_data         (jtag_read_data),
+    .jtag_access_complete   (jtag_access_complete),
+ 
+
+  
+
+    .bus_error_d            (bus_error_d),
+ 
+
+  
+
+    .instruction_f          (instruction_f),
+ 
+
+
+		      
+    .instruction_d          (instruction_d)
+
+
+		      
+    );
+
+
+lm32_decoder_full_debug decoder (
+    
+    .instruction            (instruction_d),
+    
+    .d_result_sel_0         (d_result_sel_0_d),
+    .d_result_sel_1         (d_result_sel_1_d),
+    .x_result_sel_csr       (x_result_sel_csr_d),
+  
+
+    .x_result_sel_mc_arith  (x_result_sel_mc_arith_d),
+ 
+
+      
+         
+
+
+  
+
+    .x_result_sel_sext      (x_result_sel_sext_d),
+ 
+    
+    .x_result_sel_logic     (x_result_sel_logic_d),
+  
+          
+
+
+    .x_result_sel_add       (x_result_sel_add_d),
+    .m_result_sel_compare   (m_result_sel_compare_d),
+  
+
+    .m_result_sel_shift     (m_result_sel_shift_d),  
+ 
+    
+    .w_result_sel_load      (w_result_sel_load_d),
+  
+
+    .w_result_sel_mul       (w_result_sel_mul_d),
+ 
+
+    .x_bypass_enable        (x_bypass_enable_d),
+    .m_bypass_enable        (m_bypass_enable_d),
+    .read_enable_0          (read_enable_0_d),
+    .read_idx_0             (read_idx_0_d),
+    .read_enable_1          (read_enable_1_d),
+    .read_idx_1             (read_idx_1_d),
+    .write_enable           (write_enable_d),
+    .write_idx              (write_idx_d),
+    .immediate              (immediate_d),
+    .branch_offset          (branch_offset_d),
+    .load                   (load_d),
+    .store                  (store_d),
+    .size                   (size_d),
+    .sign_extend            (sign_extend_d),
+    .adder_op               (adder_op_d),
+    .logic_op               (logic_op_d),
+  
+
+    .direction              (direction_d),
+ 
+
+  
+                 
+                
+
+
+  
+                   
+
+
+  
+
+    .divide                 (divide_d),
+    .modulus                (modulus_d),
+ 
+
+    .branch                 (branch_d),
+    .bi_unconditional       (bi_unconditional),
+    .bi_conditional         (bi_conditional),
+    .branch_reg             (branch_reg_d),
+    .condition              (condition_d),
+  
+
+    .break_opcode           (break_d),
+ 
+
+    .scall                  (scall_d),
+    .eret                   (eret_d),
+  
+
+    .bret                   (bret_d),
+ 
+
+  
+                
+
+
+    .csr_write_enable       (csr_write_enable_d)
+    ); 
+
+
+lm32_load_store_unit_full_debug #(
+    .associativity          (dcache_associativity),
+    .sets                   (dcache_sets),
+    .bytes_per_line         (dcache_bytes_per_line),
+    .base_address           (dcache_base_address),
+    .limit                  (dcache_limit)
+  ) load_store_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .kill_x                 (kill_x),
+    .kill_m                 (kill_m),
+    .exception_m            (exception_m),
+    .store_operand_x        (store_operand_x),
+    .load_store_address_x   (adder_result_x),
+    .load_store_address_m   (operand_m),
+    .load_store_address_w   (operand_w[1:0]),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_q_x               (load_q_x),
+    .store_q_x              (store_q_x),
+    .load_q_m               (load_q_m),
+    .store_q_m              (store_q_m),
+    .sign_extend_x          (sign_extend_x),
+    .size_x                 (size_x),
+  
+
+    .dflush                 (dflush_m),
+ 
+
+
+  
+    
+    
+    
+    
+    
+    
+    
+
+
+		     
+    
+    .d_dat_i                (D_DAT_I),
+    .d_ack_i                (D_ACK_I),
+    .d_err_i                (D_ERR_I),
+    .d_rty_i                (D_RTY_I),
+    
+    
+  
+
+    .dcache_refill_request  (dcache_refill_request),
+    .dcache_restart_request (dcache_restart_request),
+    .dcache_stall_request   (dcache_stall_request),
+    .dcache_refilling       (dcache_refilling),
+ 
+    
+    .load_data_w            (load_data_w),
+    .stall_wb_load          (stall_wb_load),
+    
+    .d_dat_o                (D_DAT_O),
+    .d_adr_o                (D_ADR_O),
+    .d_cyc_o                (D_CYC_O),
+    .d_sel_o                (D_SEL_O),
+    .d_stb_o                (D_STB_O),
+    .d_we_o                 (D_WE_O),
+    .d_cti_o                (D_CTI_O),
+    .d_lock_o               (D_LOCK_O),
+    .d_bte_o                (D_BTE_O)
+    );      
+       
+
+lm32_adder adder (
+    
+    .adder_op_x             (adder_op_x),
+    .adder_op_x_n           (adder_op_x_n),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .adder_result_x         (adder_result_x),
+    .adder_carry_n_x        (adder_carry_n_x),
+    .adder_overflow_x       (adder_overflow_x)
+    );
+
+
+lm32_logic_op logic_op (
+    
+    .logic_op_x             (logic_op_x),
+    .operand_0_x            (operand_0_x),
+
+    .operand_1_x            (operand_1_x),
+    
+    .logic_result_x         (logic_result_x)
+    );
+              
+  
+
+
+lm32_shifter shifter (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .direction_x            (direction_x),
+    .sign_extend_x          (sign_extend_x),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .shifter_result_m       (shifter_result_m)
+    );
+ 
+
+
+  
+
+
+lm32_multiplier multiplier (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .operand_0              (d_result_0),
+    .operand_1              (d_result_1),
+    
+    .result                 (multiplier_result_w)    
+    );
+ 
+
+
+  
+
+
+lm32_mc_arithmetic_full_debug mc_arithmetic (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_d                (stall_d),
+    .kill_x                 (kill_x),
+  
+                  
+    .divide_d               (divide_q_d),
+    .modulus_d              (modulus_q_d),
+ 
+
+          
+                 
+
+
+  
+               
+              
+              
+
+    
+    .operand_0_d            (d_result_0),
+    .operand_1_d            (d_result_1),
+    
+    .result_x               (mc_result_x),
+  
+                  
+    .divide_by_zero_x       (divide_by_zero_x),
+ 
+
+    .stall_request_x        (mc_stall_request_x)
+    );
+ 
+
+              
+  
+
+
+lm32_interrupt_full_debug interrupt_unit (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    
+    .interrupt              (interrupt),
+    
+    .stall_x                (stall_x),
+  
+
+    .non_debug_exception    (non_debug_exception_q_w), 
+    .debug_exception        (debug_exception_q_w),
+ 
+                   
+
+
+    .eret_q_x               (eret_q_x),
+  
+
+    .bret_q_x               (bret_q_x),
+ 
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    
+    .interrupt_exception    (interrupt_exception),
+    
+    .csr_read_data          (interrupt_csr_read_data_x)
+    );
+ 
+
+
+  
+      
+      
+        
+   
+
+
+
+
+  
+
+
+lm32_jtag_full_debug jtag (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .jtag_clk               (jtag_clk),
+    .jtag_update            (jtag_update),
+    .jtag_reg_q             (jtag_reg_q),
+    .jtag_reg_addr_q        (jtag_reg_addr_q),
+    
+  
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    .stall_x                (stall_x),
+ 
+
+  
+
+    .jtag_read_data         (jtag_read_data),
+    .jtag_access_complete   (jtag_access_complete),
+ 
+
+  
+
+    .exception_q_w          (debug_exception_q_w || non_debug_exception_q_w),
+ 
+    
+    
+    
+  
+
+    .jtx_csr_read_data      (jtx_csr_read_data),
+    .jrx_csr_read_data      (jrx_csr_read_data),
+ 
+
+  
+
+    .jtag_csr_write_enable  (jtag_csr_write_enable),
+    .jtag_csr_write_data    (jtag_csr_write_data),
+    .jtag_csr               (jtag_csr),
+    .jtag_read_enable       (jtag_read_enable),
+    .jtag_write_enable      (jtag_write_enable),
+    .jtag_write_data        (jtag_write_data),
+    .jtag_address           (jtag_address),
+ 
+
+  
+
+    .jtag_break             (jtag_break),
+    .jtag_reset             (reset_exception),
+ 
+
+    
+    .jtag_reg_d             (jtag_reg_d),
+    .jtag_reg_addr_d        (jtag_reg_addr_d)
+    );
+ 
+
+
+  
+
+
+lm32_debug_full_debug #(
+    .breakpoints            (breakpoints),
+    .watchpoints            (watchpoints)
+  ) hw_debug (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    .pc_x                   (pc_x),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_store_address_x   (adder_result_x),
+    .csr_write_enable_x     (csr_write_enable_q_x),
+    .csr_write_data         (operand_1_x),
+    .csr_x                  (csr_x),
+   
+
+	        
+
+    .jtag_csr_write_enable  (jtag_csr_write_enable),
+    .jtag_csr_write_data    (jtag_csr_write_data),
+    .jtag_csr               (jtag_csr),
+	       
+
+	        
+      
+        
+                   
+	      
+
+ 
+
+  
+
+    .eret_q_x               (eret_q_x),
+    .bret_q_x               (bret_q_x),
+    .stall_x                (stall_x),
+    .exception_x            (exception_x),
+    .q_x                    (q_x),
+  
+
+    .dcache_refill_request  (dcache_refill_request),
+ 
+
+ 
+
+    
+  
+
+    .dc_ss                  (dc_ss),
+ 
+
+    .dc_re                  (dc_re),
+    .bp_match               (bp_match),
+    .wp_match               (wp_match)
+    );
+ 
+
+
+
+
+  
+
+   
+           
+            
+          
+            
+
+
+             
+              
+    
+
+   wire [31:0] regfile_data_0, regfile_data_1;
+   reg [31:0]  w_result_d;
+   reg 	       regfile_raw_0, regfile_raw_0_nxt;
+   reg 	       regfile_raw_1, regfile_raw_1_nxt;
+   
+   
+             
+          
+
+   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
+     begin
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[25:21]))
+	  regfile_raw_0_nxt = 1'b1;
+	else
+	  regfile_raw_0_nxt = 1'b0;
+	
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[20:16]))
+	  regfile_raw_1_nxt = 1'b1;
+	else
+	  regfile_raw_1_nxt = 1'b0;
+     end
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_0 or w_result_d or regfile_data_0)
+     if (regfile_raw_0)
+       reg_data_live_0 = w_result_d;
+     else
+       reg_data_live_0 = regfile_data_0;
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_1 or w_result_d or regfile_data_1)
+     if (regfile_raw_1)
+       reg_data_live_1 = w_result_d;
+     else
+       reg_data_live_1 = regfile_data_1;
+   
+   
+     
+
+   always @(posedge clk_i  )
+     if (rst_i ==  1'b1)
+       begin
+	  regfile_raw_0 <= 1'b0;
+	  regfile_raw_1 <= 1'b0;
+	  w_result_d <= 32'b0;
+       end
+     else
+       begin
+	  regfile_raw_0 <= regfile_raw_0_nxt;
+	  regfile_raw_1 <= regfile_raw_1_nxt;
+	  w_result_d <= w_result;
+       end
+   
+   
+      
+
+   
+   lm32_dp_ram
+     #(
+       
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_0
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[25:21]),
+      
+      .rdata_o	(regfile_data_0)
+      );
+
+   lm32_dp_ram
+     #(
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_1
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[20:16]),
+      
+      .rdata_o	(regfile_data_1)
+      );
+ 
+
+
+  
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+   
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+
+
+
+
+
+
+
+
+  
+
+
+assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
+assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
+ 
+
+  
+
+ 
+
+   
+   
+
+
+
+
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w ==  1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w ==  1'b1);
+
+
+always @(*)
+begin
+    if (   (   (x_bypass_enable_x ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_x_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_x_1 ==  1'b1))
+               )
+           )
+        || (   (m_bypass_enable_m ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_m_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_m_1 ==  1'b1))
+               )
+           )
+       )
+        interlock =  1'b1;
+    else
+        interlock =  1'b0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_0 ==  1'b1)        
+        bypass_data_0 = x_result;
+    else if (raw_m_0 ==  1'b1)
+        bypass_data_0 = m_result;
+    else if (raw_w_0 ==  1'b1)
+        bypass_data_0 = w_result;
+    else
+        bypass_data_0 = reg_data_0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_1 ==  1'b1)
+        bypass_data_1 = x_result;
+    else if (raw_m_1 ==  1'b1)
+        bypass_data_1 = m_result;
+    else if (raw_w_1 ==  1'b1)
+        bypass_data_1 = w_result;
+    else
+        bypass_data_1 = reg_data_1;
+end
+
+   
+          
+       
+       
+     
+
+   assign branch_predict_d = bi_unconditional | bi_conditional;
+   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
+   
+   
+   assign branch_target_d = pc_d + branch_offset_d;
+
+   
+   
+   
+   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
+
+
+always @(*)
+begin
+    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
+    case (d_result_sel_1_d)
+     2'b00:      d_result_1 = { 32{1'b0}};
+     2'b01:     d_result_1 = bypass_data_1;
+     2'b10: d_result_1 = immediate_d;
+    default:                        d_result_1 = { 32{1'bx}};
+    endcase
+end
+
+      
+
+   
+   
+
+
+
+  
+
+
+assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
+assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
+assign sext_result_x = size_x ==  2'b00 ? sextb_result_x : sexth_result_x;
+ 
+
+
+  
+
+      
+
+
+
+
+assign cmp_zero = operand_0_x == operand_1_x;
+assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_overflow = adder_overflow_x;
+assign cmp_carry_n = adder_carry_n_x;
+always @(*)
+begin
+    case (condition_x)
+     3'b000:   condition_met_x =  1'b1;
+     3'b110:   condition_met_x =  1'b1;
+     3'b001:    condition_met_x = cmp_zero;
+     3'b111:   condition_met_x = !cmp_zero;
+     3'b010:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+     3'b101:   condition_met_x = cmp_carry_n && !cmp_zero;
+     3'b011:   condition_met_x = cmp_negative == cmp_overflow;
+     3'b100:  condition_met_x = cmp_carry_n;
+    default:              condition_met_x = 1'bx;
+    endcase 
+end
+
+
+always @(*)
+begin
+    x_result =   x_result_sel_add_x ? adder_result_x 
+               : x_result_sel_csr_x ? csr_read_data_x
+  
+
+               : x_result_sel_sext_x ? sext_result_x
+ 
+
+  
+                  
+
+
+  
+                  
+
+
+  
+
+               : x_result_sel_mc_arith_x ? mc_result_x
+ 
+
+               : logic_result_x;
+end
+
+
+always @(*)
+begin
+    m_result =   m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
+  
+
+               : m_result_sel_shift_m ? shifter_result_m
+ 
+
+               : operand_m; 
+end
+
+
+always @(*)
+begin
+    w_result =    w_result_sel_load_w ? load_data_w
+  
+
+                : w_result_sel_mul_w ? multiplier_result_w
+ 
+
+                : operand_w;
+end
+
+  
+    
+
+assign branch_taken_x =      (stall_x ==  1'b0)
+                          && (   (branch_x ==  1'b1)
+                              && ((condition_x ==  3'b000) || (condition_x ==  3'b110))
+                              && (valid_x ==  1'b1)
+                              && (branch_predict_x ==  1'b0)
+                             ); 
+ 
+
+
+
+assign branch_taken_m =      (stall_m ==  1'b0) 
+                          && (   (   (branch_m ==  1'b1) 
+                                  && (valid_m ==  1'b1)
+                                  && (   (   (condition_met_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b0)
+					 )
+				      || (   (condition_met_m ==  1'b0)
+					  && (branch_predict_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b1)
+					 )
+				     )
+                                 ) 
+                              || (exception_m ==  1'b1)
+                             );
+
+
+assign branch_mispredict_taken_m =    (condition_met_m ==  1'b0)
+                                   && (branch_predict_m ==  1'b1)
+	   			   && (branch_predict_taken_m ==  1'b1);
+   
+
+assign branch_flushX_m =    (stall_m ==  1'b0)
+                         && (   (   (branch_m ==  1'b1) 
+                                 && (valid_m ==  1'b1)
+			         && (   (condition_met_m ==  1'b1)
+				     || (   (condition_met_m ==  1'b0)
+					 && (branch_predict_m ==  1'b1)
+					 && (branch_predict_taken_m ==  1'b1)
+					)
+				    )
+			        )
+			     || (exception_m ==  1'b1)
+			    );
+
+
+assign kill_f =    (   (valid_d ==  1'b1)
+                    && (branch_predict_taken_d ==  1'b1)
+		   )
+                || (branch_taken_m ==  1'b1) 
+  
+    
+                || (branch_taken_x ==  1'b1)
+ 
+
+  
+
+                || (icache_refill_request ==  1'b1) 
+ 
+
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+
+                ;
+assign kill_d =    (branch_taken_m ==  1'b1) 
+  
+    
+                || (branch_taken_x ==  1'b1)
+ 
+
+  
+
+                || (icache_refill_request ==  1'b1)     
+ 
+                
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+
+                ;
+assign kill_x =    (branch_flushX_m ==  1'b1) 
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+
+                ;
+assign kill_m =     1'b0
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+
+                ;                
+assign kill_w =     1'b0
+  
+                
+                || (dcache_refill_request ==  1'b1)
+ 
+                
+                ;
+
+
+
+  
+
+assign breakpoint_exception =    (   (   (break_x ==  1'b1)
+				      || (bp_match ==  1'b1)
+				     )
+				  && (valid_x ==  1'b1)
+				 )
+  
+
+                              || (jtag_break ==  1'b1)
+ 
+
+                              ;
+ 
+
+
+  
+
+assign watchpoint_exception = wp_match ==  1'b1;
+ 
+
+
+  
+
+assign instruction_bus_error_exception = (   (bus_error_x ==  1'b1)
+                                          && (valid_x ==  1'b1)
+                                         );
+assign data_bus_error_exception = data_bus_error_seen ==  1'b1;
+ 
+
+
+  
+
+assign divide_by_zero_exception = divide_by_zero_x ==  1'b1;
+ 
+
+
+assign system_call_exception = (   (scall_x ==  1'b1)
+  
+
+                                && (valid_x ==  1'b1)
+ 
+
+			       );
+
+  
+
+assign debug_exception_x =  (breakpoint_exception ==  1'b1)
+                         || (watchpoint_exception ==  1'b1)
+                         ;
+
+assign non_debug_exception_x = (system_call_exception ==  1'b1)
+  
+
+                            || (reset_exception ==  1'b1)
+ 
+
+  
+
+                            || (instruction_bus_error_exception ==  1'b1)
+                            || (data_bus_error_exception ==  1'b1)
+ 
+
+  
+
+                            || (divide_by_zero_exception ==  1'b1)
+ 
+
+  
+
+                            || (   (interrupt_exception ==  1'b1)
+  
+
+                                && (dc_ss ==  1'b0)
+ 
+                            
+  
+
+ 				&& (store_q_m ==  1'b0)
+				&& (D_CYC_O ==  1'b0)
+ 
+
+                               )
+ 
+
+                            ;
+
+assign exception_x = (debug_exception_x ==  1'b1) || (non_debug_exception_x ==  1'b1);
+ 
+               
+ 
+                               
+                               
+
+ 
+                               
+
+ 
+                                  
+ 
+                                   
+                            
+ 
+ 				   
+				   
+
+                               
+
+                            
+
+
+
+  
+ 
+
+ 
+  
+      
+   
+      
+
+
+
+
+always @(*)
+begin
+  
+
+  
+
+    if (reset_exception ==  1'b1)
+        eid_x =  3'h0;
+    else
+ 
+     
+  
+
+         if (data_bus_error_exception ==  1'b1)
+        eid_x =  3'h4;
+    else
+ 
+
+         if (breakpoint_exception ==  1'b1)
+        eid_x =  3'd1;
+    else
+ 
+
+  
+
+         if (data_bus_error_exception ==  1'b1)
+        eid_x =  3'h4;
+    else
+         if (instruction_bus_error_exception ==  1'b1)
+        eid_x =  3'h2;
+    else
+ 
+
+  
+
+         if (watchpoint_exception ==  1'b1)
+        eid_x =  3'd3;
+    else 
+ 
+
+  
+
+         if (divide_by_zero_exception ==  1'b1)
+        eid_x =  3'h5;
+    else
+ 
+
+  
+
+         if (   (interrupt_exception ==  1'b1)
+  
+
+             && (dc_ss ==  1'b0)
+ 
+                            
+            )
+        eid_x =  3'h6;
+    else
+ 
+
+        eid_x =  3'h7;
+end
+
+
+
+assign stall_a = (stall_f ==  1'b1);
+                
+assign stall_f = (stall_d ==  1'b1);
+                
+assign stall_d =   (stall_x ==  1'b1) 
+                || (   (interlock ==  1'b1)
+                    && (kill_d ==  1'b0)
+                   ) 
+		|| (   (   (eret_d ==  1'b1)
+			|| (scall_d ==  1'b1)
+  
+
+			|| (bus_error_d ==  1'b1)
+ 
+
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+  
+
+		|| (   (   (break_d ==  1'b1)
+			|| (bret_d ==  1'b1)
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+ 
+                   
+                || (   (csr_write_enable_d ==  1'b1)
+                    && (load_q_x ==  1'b1)
+                   )                      
+  
+                 
+                 
+                       
+		           
+			 
+			
+		    
+
+	
+                ;
+                
+assign stall_x =    (stall_m ==  1'b1)
+  
+
+                 || (   (mc_stall_request_x ==  1'b1)
+                     && (kill_x ==  1'b0)
+                    ) 
+ 
+
+
+	    
+                 ;
+
+assign stall_m =    (stall_wb_load ==  1'b1)
+  
+                    
+
+
+                 || (   (D_CYC_O ==  1'b1)
+                     && (   (store_m ==  1'b1)
+		         
+          
+          
+
+		  
+	 
+	
+
+          
+           
+          
+       
+
+  
+
+		         || ((store_x ==  1'b1) && (interrupt_exception ==  1'b1))
+ 
+
+                         || (load_m ==  1'b1)
+                         || (load_x ==  1'b1)
+                        ) 
+                    ) 
+ 
+                 
+  
+
+                 || (dcache_stall_request ==  1'b1)     
+ 
+                                    
+  
+
+                 || (icache_stall_request ==  1'b1)     
+                 || ((I_CYC_O ==  1'b1) && ((branch_m ==  1'b1) || (exception_m ==  1'b1))) 
+ 
+ 
+                                
+
+
+                               
+  
+                                  
+                        
+                    
+
+
+  
+                  
+   
+
+                 ;      
+
+
+
+
+  
+
+assign q_d = (valid_d ==  1'b1) && (kill_d ==  1'b0);
+ 
+
+  
+         
+         
+
+
+  
+         
+
+
+  
+
+assign divide_q_d = (divide_d ==  1'b1) && (q_d ==  1'b1);
+assign modulus_q_d = (modulus_d ==  1'b1) && (q_d ==  1'b1);
+ 
+
+assign q_x = (valid_x ==  1'b1) && (kill_x ==  1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x ==  1'b1) && (q_x ==  1'b1);
+assign eret_q_x = (eret_x ==  1'b1) && (q_x ==  1'b1);
+  
+
+assign bret_q_x = (bret_x ==  1'b1) && (q_x ==  1'b1);
+ 
+
+assign load_q_x = (load_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+
+               && (bp_match ==  1'b0)
+ 
+
+                  ;
+assign store_q_x = (store_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+
+               && (bp_match ==  1'b0)
+ 
+
+                  ;
+  
+         
+
+                              
+assign q_m = (valid_m ==  1'b1) && (kill_m ==  1'b0) && (exception_m ==  1'b0);
+assign load_q_m = (load_m ==  1'b1) && (q_m ==  1'b1);
+assign store_q_m = (store_m ==  1'b1) && (q_m ==  1'b1);
+  
+
+assign debug_exception_q_w = ((debug_exception_w ==  1'b1) && (valid_w ==  1'b1));
+assign non_debug_exception_q_w = ((non_debug_exception_w ==  1'b1) && (valid_w ==  1'b1));        
+ 
+                 
+
+
+
+assign write_enable_q_x = (write_enable_x ==  1'b1) && (valid_x ==  1'b1) && (branch_flushX_m ==  1'b0);
+assign write_enable_q_m = (write_enable_m ==  1'b1) && (valid_m ==  1'b1);
+assign write_enable_q_w = (write_enable_w ==  1'b1) && (valid_w ==  1'b1);
+
+assign reg_write_enable_q_w = (write_enable_w ==  1'b1) && (kill_w ==  1'b0) && (valid_w ==  1'b1);
+
+
+assign cfg = {
+               6'h02,
+              watchpoints[3:0],
+              breakpoints[3:0],
+              interrupts[5:0],
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+ 
+               1'b1
+ 
+              
+
+
+              };
+
+assign cfg2 = {
+		     30'b0,
+  
+		     
+
+
+		      1'b0,
+ 
+
+  
+		     
+
+
+		      1'b0
+ 
+
+		     };
+   
+
+  
+
+assign iflush = (   (csr_write_enable_d ==  1'b1) 
+                 && (csr_d ==  5'h3)
+                 && (stall_d ==  1'b0)
+                 && (kill_d ==  1'b0)
+                 && (valid_d ==  1'b1))
+
+  
+
+             ||
+                (   (jtag_csr_write_enable ==  1'b1)
+		 && (jtag_csr ==  5'h3))
+ 
+
+		 ;
+ 
+ 
+  
+
+assign dflush_x = (   (csr_write_enable_q_x ==  1'b1) 
+                   && (csr_x ==  5'h4))
+
+  
+
+               ||
+                  (   (jtag_csr_write_enable ==  1'b1)
+		   && (jtag_csr ==  5'h4))
+ 
+
+		   ;
+ 
+ 
+
+
+assign csr_d = read_idx_0_d[ (5-1):0];
+
+
+always @(*)
+begin
+    case (csr_x)
+  
+
+     5'h0,
+     5'h1,
+     5'h2:   csr_read_data_x = interrupt_csr_read_data_x;  
+ 
+
+  
+         
+
+
+     5'h6:  csr_read_data_x = cfg;
+     5'h7:  csr_read_data_x = {eba, 8'h00};
+  
+
+     5'h9: csr_read_data_x = {deba, 8'h00};
+ 
+
+  
+
+     5'he:  csr_read_data_x = jtx_csr_read_data;  
+     5'hf:  csr_read_data_x = jrx_csr_read_data;
+ 
+
+     5'ha: csr_read_data_x = cfg2;
+     5'hb:  csr_read_data_x = sdb_address;
+  
+
+     5'hc:  csr_read_data_x = data_bus_error_addr;
+ 
+
+      
+      
+    default:        csr_read_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  5'h7) && (stall_x ==  1'b0))
+            eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+  
+
+   
+
+       if ((jtag_csr_write_enable ==  1'b1) && (jtag_csr ==  5'h7))
+         eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+  
+
+   
+              
+           
+ 
+	 
+ 
+
+    end
+end
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  5'h9) && (stall_x ==  1'b0))
+            deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+   
+
+    
+
+       if ((jtag_csr_write_enable ==  1'b1) && (jtag_csr ==  5'h9))
+         deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+   
+
+    
+              
+           
+  
+       
+  
+
+    end
+end
+ 
+
+
+
+  
+   
+
+       
+          
+    
+            
+
+
+
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        data_bus_error_seen <=  1'b0;
+    else
+    begin
+        
+        if ((D_ERR_I ==  1'b1) && (D_CYC_O ==  1'b1)) begin
+           data_bus_error_seen <=  1'b1;
+	   data_bus_error_addr <= D_ADR_O;
+	end
+        
+        if ((exception_m ==  1'b1) && (kill_m ==  1'b0))
+            data_bus_error_seen <=  1'b0;
+    end
+end
+ 
+
+ 
+
+
+  
+
+  
+
+always @(*)
+begin
+    if (   (icache_refill_request ==  1'b1) 
+        || (dcache_refill_request ==  1'b1)
+       )
+        valid_a =  1'b0;
+    else if (   (icache_restart_request ==  1'b1) 
+             || (dcache_restart_request ==  1'b1) 
+            ) 
+        valid_a =  1'b1;
+    else 
+        valid_a = !icache_refilling && !dcache_refilling;
+end 
+ 
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+ 
+ 
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        valid_f <=  1'b0;
+        valid_d <=  1'b0;
+        valid_x <=  1'b0;
+        valid_m <=  1'b0;
+        valid_w <=  1'b0;
+    end
+    else
+    begin    
+        if ((kill_f ==  1'b1) || (stall_a ==  1'b0))
+  
+
+            valid_f <= valid_a;    
+ 
+              
+
+            
+        else if (stall_f ==  1'b0)
+            valid_f <=  1'b0;            
+
+        if (kill_d ==  1'b1)
+            valid_d <=  1'b0;
+        else if (stall_f ==  1'b0)
+            valid_d <= valid_f & !kill_f;
+        else if (stall_d ==  1'b0)
+            valid_d <=  1'b0;
+       
+        if (stall_d ==  1'b0)
+            valid_x <= valid_d & !kill_d;
+        else if (kill_x ==  1'b1)
+            valid_x <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_x <=  1'b0;
+
+        if (kill_m ==  1'b1)
+            valid_m <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_m <= valid_x & !kill_x;
+        else if (stall_m ==  1'b0)
+            valid_m <=  1'b0;
+
+        if (stall_m ==  1'b0)
+            valid_w <= valid_m & !kill_m;
+        else 
+            valid_w <=  1'b0;        
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+  
+                 
+
+        
+        operand_0_x <= { 32{1'b0}};
+        operand_1_x <= { 32{1'b0}};
+        store_operand_x <= { 32{1'b0}};
+        branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};        
+        x_result_sel_csr_x <=  1'b0;
+  
+
+        x_result_sel_mc_arith_x <=  1'b0;
+ 
+
+      
+          
+
+
+  
+
+        x_result_sel_sext_x <=  1'b0;
+ 
+    
+  
+          
+
+
+        x_result_sel_add_x <=  1'b0;
+        m_result_sel_compare_x <=  1'b0;
+  
+
+        m_result_sel_shift_x <=  1'b0;
+ 
+    
+        w_result_sel_load_x <=  1'b0;
+  
+
+        w_result_sel_mul_x <=  1'b0;
+ 
+
+        x_bypass_enable_x <=  1'b0;
+        m_bypass_enable_x <=  1'b0;
+        write_enable_x <=  1'b0;
+        write_idx_x <= { 5{1'b0}};
+        csr_x <= { 5{1'b0}};
+        load_x <=  1'b0;
+        store_x <=  1'b0;
+        size_x <= { 2{1'b0}};
+        sign_extend_x <=  1'b0;
+        adder_op_x <=  1'b0;
+        adder_op_x_n <=  1'b0;
+        logic_op_x <= 4'h0;
+  
+
+        direction_x <=  1'b0;
+ 
+
+  
+          
+
+
+
+        branch_x <=  1'b0;
+        branch_predict_x <=  1'b0;
+        branch_predict_taken_x <=  1'b0;
+        condition_x <=  3'b000;
+  
+
+        break_x <=  1'b0;
+ 
+
+        scall_x <=  1'b0;
+        eret_x <=  1'b0;
+  
+
+        bret_x <=  1'b0;
+ 
+
+  
+
+        bus_error_x <=  1'b0;
+        data_bus_error_exception_m <=  1'b0;
+ 
+
+        csr_write_enable_x <=  1'b0;
+        operand_m <= { 32{1'b0}};
+        branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        m_result_sel_compare_m <=  1'b0;
+  
+
+        m_result_sel_shift_m <=  1'b0;
+ 
+    
+        w_result_sel_load_m <=  1'b0;
+  
+
+        w_result_sel_mul_m <=  1'b0;
+ 
+
+        m_bypass_enable_m <=  1'b0;
+        branch_m <=  1'b0;
+        branch_predict_m <=  1'b0;
+	branch_predict_taken_m <=  1'b0;
+        exception_m <=  1'b0;
+        load_m <=  1'b0;
+        store_m <=  1'b0;
+        write_enable_m <=  1'b0;            
+        write_idx_m <= { 5{1'b0}};
+        condition_met_m <=  1'b0;
+  
+
+        dflush_m <=  1'b0;
+ 
+
+  
+
+        debug_exception_m <=  1'b0;
+        non_debug_exception_m <=  1'b0;        
+ 
+
+        operand_w <= { 32{1'b0}};        
+        w_result_sel_load_w <=  1'b0;
+  
+
+        w_result_sel_mul_w <=  1'b0;
+ 
+
+        write_idx_w <= { 5{1'b0}};        
+        write_enable_w <=  1'b0;
+  
+
+        debug_exception_w <=  1'b0;
+        non_debug_exception_w <=  1'b0;        
+ 
+          
+
+
+  
+
+        memop_pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ 
+
+    end
+    else
+    begin
+        
+       
+        if (stall_x ==  1'b0)
+        begin
+  
+                     
+
+        
+            operand_0_x <= d_result_0;
+            operand_1_x <= d_result_1;
+            store_operand_x <= bypass_data_1;
+            branch_target_x <= branch_reg_d ==  1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;            
+            x_result_sel_csr_x <= x_result_sel_csr_d;
+  
+
+            x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
+ 
+
+      
+              
+
+
+  
+
+            x_result_sel_sext_x <= x_result_sel_sext_d;
+ 
+    
+  
+              
+
+
+            x_result_sel_add_x <= x_result_sel_add_d;
+            m_result_sel_compare_x <= m_result_sel_compare_d;
+  
+
+            m_result_sel_shift_x <= m_result_sel_shift_d;
+ 
+    
+            w_result_sel_load_x <= w_result_sel_load_d;
+  
+
+            w_result_sel_mul_x <= w_result_sel_mul_d;
+ 
+
+            x_bypass_enable_x <= x_bypass_enable_d;
+            m_bypass_enable_x <= m_bypass_enable_d;
+            load_x <= load_d;
+            store_x <= store_d;
+            branch_x <= branch_d;
+	    branch_predict_x <= branch_predict_d;
+	    branch_predict_taken_x <= branch_predict_taken_d;
+	    write_idx_x <= write_idx_d;
+            csr_x <= csr_d;
+            size_x <= size_d;
+            sign_extend_x <= sign_extend_d;
+            adder_op_x <= adder_op_d;
+            adder_op_x_n <= ~adder_op_d;
+            logic_op_x <= logic_op_d;
+  
+
+            direction_x <= direction_d;
+ 
+
+  
+              
+
+
+            condition_x <= condition_d;
+            csr_write_enable_x <= csr_write_enable_d;
+  
+
+            break_x <= break_d;
+ 
+
+            scall_x <= scall_d;
+  
+
+            bus_error_x <= bus_error_d;
+ 
+
+            eret_x <= eret_d;
+  
+
+            bret_x <= bret_d; 
+ 
+
+            write_enable_x <= write_enable_d;
+        end
+        
+        
+
+        if (stall_m ==  1'b0)
+        begin
+            operand_m <= x_result;
+            m_result_sel_compare_m <= m_result_sel_compare_x;
+  
+
+            m_result_sel_shift_m <= m_result_sel_shift_x;
+ 
+    
+            if (exception_x ==  1'b1)
+            begin
+                w_result_sel_load_m <=  1'b0;
+  
+
+                w_result_sel_mul_m <=  1'b0;
+ 
+
+            end
+            else
+            begin
+                w_result_sel_load_m <= w_result_sel_load_x;
+  
+
+                w_result_sel_mul_m <= w_result_sel_mul_x;
+ 
+
+            end
+            m_bypass_enable_m <= m_bypass_enable_x;
+            load_m <= load_x;
+            store_m <= store_x;
+  
+    
+            branch_m <= branch_x && !branch_taken_x;
+ 
+              
+	      
+	      
+
+
+  
+
+	   
+	   
+	   
+	   
+	   
+            if (non_debug_exception_x ==  1'b1) 
+                write_idx_m <=  5'd30;
+            else if (debug_exception_x ==  1'b1)
+                write_idx_m <=  5'd31;
+            else 
+                write_idx_m <= write_idx_x;
+ 
+               
+                  
+             
+                  
+
+
+            condition_met_m <= condition_met_x;
+  
+
+	   if (exception_x ==  1'b1)
+	     if ((dc_re ==  1'b1)
+		 || ((debug_exception_x ==  1'b1) 
+		     && (non_debug_exception_x ==  1'b0)))
+	       branch_target_m <= {deba, eid_x, {3{1'b0}}};
+	     else
+	       branch_target_m <= {eba, eid_x, {3{1'b0}}};
+	   else
+	     branch_target_m <= branch_target_x;
+ 
+                      
+
+
+  
+              
+              
+
+
+  
+
+            dflush_m <= dflush_x;
+ 
+
+  
+ 
+               
+
+
+
+            write_enable_m <= exception_x ==  1'b1 ?  1'b1 : write_enable_x;            
+  
+
+            debug_exception_m <= debug_exception_x;
+            non_debug_exception_m <= non_debug_exception_x;        
+ 
+
+        end
+        
+        
+        if (stall_m ==  1'b0)
+        begin
+            if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+                exception_m <=  1'b1;
+            else 
+                exception_m <=  1'b0;
+  
+
+	   data_bus_error_exception_m <=    (data_bus_error_exception ==  1'b1) 
+  
+
+					 && (reset_exception ==  1'b0)
+ 
+
+					 ;
+ 
+
+	end
+                
+        
+  
+
+        operand_w <= exception_m ==  1'b1 ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
+ 
+                 
+
+
+        w_result_sel_load_w <= w_result_sel_load_m;
+  
+
+        w_result_sel_mul_w <= w_result_sel_mul_m;
+ 
+
+        write_idx_w <= write_idx_m;
+  
+          
+          
+ 
+           
+
+
+
+        write_enable_w <= write_enable_m;
+  
+
+        debug_exception_w <= debug_exception_m;
+        non_debug_exception_w <= non_debug_exception_m;
+ 
+          
+
+
+  
+
+        if (   (stall_m ==  1'b0)
+            && (   (load_q_m ==  1'b1) 
+                || (store_q_m ==  1'b1)
+               )
+	   )
+          memop_pc_w <= pc_m;
+ 
+
+    end
+end
+
+  
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        use_buf <=  1'b0;
+        reg_data_buf_0 <= { 32{1'b0}};
+        reg_data_buf_1 <= { 32{1'b0}};
+    end
+    else
+    begin
+        if (stall_d ==  1'b0)
+            use_buf <=  1'b0;
+        else if (use_buf ==  1'b0)
+        begin        
+            reg_data_buf_0 <= reg_data_live_0;
+            reg_data_buf_1 <= reg_data_live_1;
+            use_buf <=  1'b1;
+        end        
+        if (reg_write_enable_q_w ==  1'b1)
+        begin
+            if (write_idx_w == read_idx_0_d)
+                reg_data_buf_0 <= w_result;
+            if (write_idx_w == read_idx_1_d)
+                reg_data_buf_1 <= w_result;
+        end
+    end
+end
+ 
+
+
+  
+
+ 
+
+   
+
+        
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+     
+           
+            
+        
+
+
+
+
+  
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+ 
+          
+
+          
+    
+    
+    
+          
+        
+ 
+               
+
+           
+
+                
+              
+              
+              
+              
+        
+        
+              
+        
+             
+        
+            
+                 
+            
+                
+                  
+                  
+            
+            
+              
+            
+              
+ 
+              
+
+        
+        
+        
+              
+ 
+              
+
+        
+    
+
+
+
+      
+
+
+
+
+
+        
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_load_store_unit_full_debug 
+(
+    
+    clk_i,
+    rst_i,
+ 
+    stall_a,
+    stall_x,
+    stall_m,
+    kill_x,
+    kill_m,
+    exception_m,
+    store_operand_x,
+    load_store_address_x,
+    load_store_address_m,
+    load_store_address_w,
+    load_x,
+    store_x,
+    load_q_x,
+    store_q_x,
+    load_q_m,
+    store_q_m,
+    sign_extend_x,
+    size_x,
+  
+
+    dflush,
+ 
+
+    
+    d_dat_i,
+    d_ack_i,
+    d_err_i,
+    d_rty_i,
+    
+    
+  
+
+    dcache_refill_request,
+    dcache_restart_request,
+    dcache_stall_request,
+    dcache_refilling,
+ 
+    
+  
+    
+    
+    
+    
+    
+    
+    
+
+			     
+    load_data_w,
+    stall_wb_load,
+    
+    d_dat_o,
+    d_adr_o,
+    d_cyc_o,
+    d_sel_o,
+    d_stb_o,
+    d_we_o,
+    d_cti_o,
+    d_lock_o,
+    d_bte_o
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+
+   input clk_i;                                            
+   
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+input kill_x;                                           
+input kill_m;                                           
+input exception_m;                                      
+
+input [ (32-1):0] store_operand_x;                 
+input [ (32-1):0] load_store_address_x;            
+input [ (32-1):0] load_store_address_m;            
+input [1:0] load_store_address_w;                       
+input load_x;                                           
+input store_x;                                          
+input load_q_x;                                         
+input store_q_x;                                        
+input load_q_m;                                         
+input store_q_m;                                        
+input sign_extend_x;                                    
+input [ 1:0] size_x;                          
+
+  
+
+input dflush;                                           
+ 
+
+
+     
+     
+     
+      
+      
+            
+    	 
+   
+
+
+
+   reg 		 [31:0] iram_dat_d0;
+   reg 		 iram_en_d0;
+   wire 	 iram_en;
+   wire [31:0] 	 iram_data;
+   
+   
+   
+input [ (32-1):0] d_dat_i;                         
+input d_ack_i;                                          
+input d_err_i;                                          
+input d_rty_i;                                          
+
+
+
+
+
+  
+
+output dcache_refill_request;                           
+wire   dcache_refill_request;
+output dcache_restart_request;                          
+wire   dcache_restart_request;
+output dcache_stall_request;                            
+wire   dcache_stall_request;
+output dcache_refilling;
+wire   dcache_refilling;
+ 
+
+
+   
+output [ (32-1):0] load_data_w;                    
+reg    [ (32-1):0] load_data_w;
+output stall_wb_load;                                   
+reg    stall_wb_load;
+
+output [ (32-1):0] d_dat_o;                        
+reg    [ (32-1):0] d_dat_o;
+output [ (32-1):0] d_adr_o;                        
+reg    [ (32-1):0] d_adr_o;
+output d_cyc_o;                                         
+reg    d_cyc_o;
+output [ (4-1):0] d_sel_o;                 
+reg    [ (4-1):0] d_sel_o;
+output d_stb_o;                                         
+reg    d_stb_o; 
+output d_we_o;                                          
+reg    d_we_o;
+output [ (3-1):0] d_cti_o;                       
+reg    [ (3-1):0] d_cti_o;
+output d_lock_o;                                        
+reg    d_lock_o;
+output [ (2-1):0] d_bte_o;                       
+wire   [ (2-1):0] d_bte_o;
+
+
+
+
+
+
+reg [ 1:0] size_m;
+reg [ 1:0] size_w;
+reg sign_extend_m;
+reg sign_extend_w;
+reg [ (32-1):0] store_data_x;       
+reg [ (32-1):0] store_data_m;       
+reg [ (4-1):0] byte_enable_x;
+reg [ (4-1):0] byte_enable_m;
+wire [ (32-1):0] data_m;
+reg [ (32-1):0] data_w;
+
+   
+
+  
+
+wire dcache_select_x;                                   
+reg dcache_select_m;
+wire [ (32-1):0] dcache_data_m;                    
+wire [ (32-1):0] dcache_refill_address;            
+reg dcache_refill_ready;                                
+wire [ (3-1):0] first_cycle_type;                
+wire [ (3-1):0] next_cycle_type;                 
+wire last_word;                                         
+wire [ (32-1):0] first_address;                    
+ 
+
+  
+                                      
+ 
+                                      
+                    
+                      
+                        
+                  
+
+
+wire wb_select_x;                                       
+  
+                                      
+
+  
+    
+    
+   
+
+
+
+reg wb_select_m;
+reg [ (32-1):0] wb_data_m;                         
+reg wb_load_complete;                                   
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+
+lm32_dcache_full_debug #(
+    .associativity          (associativity),
+    .sets                   (sets),
+    .bytes_per_line         (bytes_per_line),
+    .base_address           (base_address),
+    .limit                  (limit)
+    ) dcache ( 
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),      
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .address_x              (load_store_address_x),
+    .address_m              (load_store_address_m),
+    .load_q_m               (load_q_m & dcache_select_m),
+    .store_q_m              (store_q_m & dcache_select_m),
+    .store_data             (store_data_m),
+    .store_byte_select      (byte_enable_m & {4{dcache_select_m}}),
+    .refill_ready           (dcache_refill_ready),
+    .refill_data            (wb_data_m),
+    .dflush                 (dflush),
+    
+    .stall_request          (dcache_stall_request),
+    .restart_request        (dcache_restart_request),
+    .refill_request         (dcache_refill_request),
+    .refill_address         (dcache_refill_address),
+    .refilling              (dcache_refilling),
+    .load_data              (dcache_data_m)
+    );
+ 
+
+
+
+
+
+
+
+  
+            
+                             
+
+
+
+  
+            
+                             
+
+      
+        
+
+    
+       
+
+   
+
+    
+     
+       
+     
+         
+     
+
+          
+    
+   
+   
+
+
+   
+  
+
+   assign dcache_select_x =    (load_store_address_x >=  32'h0) 
+                            && (load_store_address_x <=  32'h7fffffff)
+  
+                               
+
+
+  
+                               
+
+
+                     ;
+ 
+
+	  
+   assign wb_select_x =     1'b1
+  
+
+                        && !dcache_select_x 
+ 
+
+  
+                         
+
+
+  
+                         
+
+
+                     ;
+
+
+always @(*)
+begin
+    case (size_x)
+     2'b00:  store_data_x = {4{store_operand_x[7:0]}};
+     2'b11: store_data_x = {2{store_operand_x[15:0]}};
+     2'b10:  store_data_x = store_operand_x;    
+    default:          store_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+always @(*)
+begin
+    casez ({size_x, load_store_address_x[1:0]})
+    { 2'b00, 2'b11}:  byte_enable_x = 4'b0001;
+    { 2'b00, 2'b10}:  byte_enable_x = 4'b0010;
+    { 2'b00, 2'b01}:  byte_enable_x = 4'b0100;
+    { 2'b00, 2'b00}:  byte_enable_x = 4'b1000;
+    { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+    { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+    { 2'b10, 2'b??}:  byte_enable_x = 4'b1111;
+    default:                   byte_enable_x = 4'bxxxx;
+    endcase
+end
+
+  
+      
+            
+
+           
+	                            
+   
+   
+               
+        
+
+
+   
+  
+
+   
+   
+   
+         
+                    
+                       
+                      
+                        
+                     
+                        
+  
+   
+         
+                    
+                       
+                      
+                      
+  
+ 
+
+    
+   
+         
+                    
+                       
+                      
+                      
+  
+
+   
+   assign data_m = wb_select_m ==  1'b1 
+                   ? wb_data_m 
+                   : dcache_data_m;
+   
+
+  
+
+ 
+  
+   
+   
+         
+                     
+                      
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+   
+   
+         
+                     
+                    
+
+  
+   
+      
+  
+ 
+
+
+
+
+always @(*)
+begin
+    casez ({size_w, load_store_address_w[1:0]})
+    { 2'b00, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+    { 2'b00, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+    { 2'b00, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+    { 2'b00, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+    { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+    { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+    { 2'b10, 2'b??}:  load_data_w = data_w;
+    default:                   load_data_w = { 32{1'bx}};
+    endcase
+end
+
+
+assign d_bte_o =  2'b00;
+
+  
+                
+
+generate 
+    case (bytes_per_line)
+    4:
+    begin
+assign first_cycle_type =  3'b111;
+assign next_cycle_type =  3'b111;
+assign last_word =  1'b1;
+assign first_address = {dcache_refill_address[ 32-1:2], 2'b00};
+    end
+    8:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type =  3'b111;
+assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
+assign first_address = {dcache_refill_address[ 32-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
+    end
+    16:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ?  3'b111 :  3'b010;
+assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
+assign first_address = {dcache_refill_address[ 32-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
+    end
+    endcase
+endgenerate
+ 
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        d_cyc_o <=  1'b0;
+        d_stb_o <=  1'b0;
+        d_dat_o <= { 32{1'b0}};
+        d_adr_o <= { 32{1'b0}};
+        d_sel_o <= { 4{ 1'b0}};
+        d_we_o <=  1'b0;
+        d_cti_o <=  3'b111;
+        d_lock_o <=  1'b0;
+        wb_data_m <= { 32{1'b0}};
+        wb_load_complete <=  1'b0;
+        stall_wb_load <=  1'b0;
+  
+                
+        dcache_refill_ready <=  1'b0;
+ 
+                
+    end
+    else 
+    begin
+  
+ 
+        
+        dcache_refill_ready <=  1'b0;
+ 
+                
+        
+        if (d_cyc_o ==  1'b1)
+        begin
+            
+            if ((d_ack_i ==  1'b1) || (d_err_i ==  1'b1))
+            begin
+  
+                
+                if ((dcache_refilling ==  1'b1) && (!last_word))
+                begin
+                    
+                    d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
+                end
+                else
+ 
+                
+                begin
+                    
+                    d_cyc_o <=  1'b0;
+                    d_stb_o <=  1'b0;
+                    d_lock_o <=  1'b0;
+                end
+  
+    
+                d_cti_o <= next_cycle_type;
+                
+                dcache_refill_ready <= dcache_refilling;
+ 
+
+                
+                wb_data_m <= d_dat_i;
+                
+                wb_load_complete <= !d_we_o;
+            end
+            
+        end
+        else 
+        begin
+  
+                
+            if (dcache_refill_request ==  1'b1)
+            begin
+                
+                d_adr_o <= first_address;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= { 32/8{ 1'b1}};
+                d_stb_o <=  1'b1;                
+                d_we_o <=  1'b0;
+                d_cti_o <= first_cycle_type;
+                
+            end
+            else 
+ 
+            
+                 if (   (store_q_m ==  1'b1)
+                     && (stall_m ==  1'b0)
+  
+                        
+
+
+  
+		        
+
+			
+                    )
+            begin
+                
+                d_dat_o <= store_data_m;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b1;
+                d_cti_o <=  3'b111;
+            end        
+            else if (   (load_q_m ==  1'b1) 
+                     && (wb_select_m ==  1'b1) 
+                     && (wb_load_complete ==  1'b0)
+                     
+                    )
+            begin
+                
+                stall_wb_load <=  1'b0;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b0;
+                d_cti_o <=  3'b111;
+            end
+        end
+        
+        if (stall_m ==  1'b0)
+            wb_load_complete <=  1'b0;
+        
+        if ((load_q_x ==  1'b1) && (wb_select_x ==  1'b1) && (stall_x ==  1'b0))
+            stall_wb_load <=  1'b1;
+        
+        if ((kill_m ==  1'b1) || (exception_m ==  1'b1))
+            stall_wb_load <=  1'b0;
+    end
+end
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        sign_extend_m <=  1'b0;
+        size_m <= 2'b00;
+        byte_enable_m <=  1'b0;
+        store_data_m <= { 32{1'b0}};
+  
+
+        dcache_select_m <=  1'b0;
+ 
+
+  
+          
+
+
+  
+          
+			    
+
+
+        wb_select_m <=  1'b0;        
+    end
+    else
+    begin
+        if (stall_m ==  1'b0)
+        begin
+            sign_extend_m <= sign_extend_x;
+            size_m <= size_x;
+            byte_enable_m <= byte_enable_x;    
+            store_data_m <= store_data_x;
+  
+
+            dcache_select_m <= dcache_select_x;
+ 
+
+  
+              
+
+
+  
+              
+			    
+
+
+            wb_select_m <= wb_select_x;
+        end
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        size_w <= 2'b00;
+        data_w <= { 32{1'b0}};
+        sign_extend_w <=  1'b0;
+    end
+    else
+    begin
+        size_w <= size_m;
+
+  
+         
+
+
+        data_w <= data_m;
+
+        sign_extend_w <= sign_extend_m;
+    end
+end
+
+
+
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
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+ 
+ 
+ 
+ 
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+ 
+
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+ 
+
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+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+  
+
+  
+
+
+
+  
+
+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
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+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_decoder_full_debug (
+    
+    instruction,
+    
+    d_result_sel_0,
+    d_result_sel_1,        
+    x_result_sel_csr,
+  
+
+    x_result_sel_mc_arith,
+ 
+    
+      
+    
+
+
+  
+
+    x_result_sel_sext,
+ 
+    
+    x_result_sel_logic,
+  
+    
+
+
+    x_result_sel_add,
+    m_result_sel_compare,
+  
+
+    m_result_sel_shift,  
+ 
+    
+    w_result_sel_load,
+  
+
+    w_result_sel_mul,
+ 
+
+    x_bypass_enable,
+    m_bypass_enable,
+    read_enable_0,
+    read_idx_0,
+    read_enable_1,
+    read_idx_1,
+    write_enable,
+    write_idx,
+    immediate,
+    branch_offset,
+    load,
+    store,
+    size,
+    sign_extend,
+    adder_op,
+    logic_op,
+  
+
+    direction,
+ 
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+
+    divide,
+    modulus,
+ 
+
+    branch,
+    branch_reg,
+    condition,
+    bi_conditional,
+    bi_unconditional,
+  
+
+    break_opcode,
+ 
+
+    scall,
+    eret,
+  
+
+    bret,
+ 
+
+  
+    
+
+
+    csr_write_enable
+    );
+
+
+
+
+
+input [ (32-1):0] instruction;       
+
+
+
+
+
+output [ 0:0] d_result_sel_0;
+reg    [ 0:0] d_result_sel_0;
+output [ 1:0] d_result_sel_1;
+reg    [ 1:0] d_result_sel_1;
+output x_result_sel_csr;
+reg    x_result_sel_csr;
+  
+
+output x_result_sel_mc_arith;
+reg    x_result_sel_mc_arith;
+ 
+
+      
+ 
+    
+
+
+  
+
+output x_result_sel_sext;
+reg    x_result_sel_sext;
+ 
+
+output x_result_sel_logic;
+reg    x_result_sel_logic;
+  
+ 
+    
+
+
+output x_result_sel_add;
+reg    x_result_sel_add;
+output m_result_sel_compare;
+reg    m_result_sel_compare;
+  
+
+output m_result_sel_shift;
+reg    m_result_sel_shift;
+ 
+
+output w_result_sel_load;
+reg    w_result_sel_load;
+  
+
+output w_result_sel_mul;
+reg    w_result_sel_mul;
+ 
+
+output x_bypass_enable;
+wire   x_bypass_enable;
+output m_bypass_enable;
+wire   m_bypass_enable;
+output read_enable_0;
+wire   read_enable_0;
+output [ (5-1):0] read_idx_0;
+wire   [ (5-1):0] read_idx_0;
+output read_enable_1;
+wire   read_enable_1;
+output [ (5-1):0] read_idx_1;
+wire   [ (5-1):0] read_idx_1;
+output write_enable;
+wire   write_enable;
+output [ (5-1):0] write_idx;
+wire   [ (5-1):0] write_idx;
+output [ (32-1):0] immediate;
+wire   [ (32-1):0] immediate;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+wire   [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+output load;
+wire   load;
+output store;
+wire   store;
+output [ 1:0] size;
+wire   [ 1:0] size;
+output sign_extend;
+wire   sign_extend;
+output adder_op;
+wire   adder_op;
+output [ 3:0] logic_op;
+wire   [ 3:0] logic_op;
+  
+
+output direction;
+wire   direction;
+ 
+
+  
+ 
+   
+ 
+   
+
+
+  
+ 
+   
+
+
+  
+
+output divide;
+wire   divide;
+output modulus;
+wire   modulus;
+ 
+
+output branch;
+wire   branch;
+output branch_reg;
+wire   branch_reg;
+output [ (3-1):0] condition;
+wire   [ (3-1):0] condition;
+output bi_conditional;
+wire bi_conditional;
+output bi_unconditional;
+wire bi_unconditional;
+  
+
+output break_opcode;
+wire   break_opcode;
+ 
+
+output scall;
+wire   scall;
+output eret;
+wire   eret;
+  
+
+output bret;
+wire   bret;
+ 
+
+  
+  
+    
+
+
+output csr_write_enable;
+wire   csr_write_enable;
+
+
+
+
+
+wire [ (32-1):0] extended_immediate;       
+wire [ (32-1):0] high_immediate;           
+wire [ (32-1):0] call_immediate;           
+wire [ (32-1):0] branch_immediate;         
+wire sign_extend_immediate;                     
+wire select_high_immediate;                     
+wire select_call_immediate;                     
+
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+  
+
+wire op_divu;
+ 
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+  
+
+wire op_modu;
+ 
+
+  
+
+wire op_mul;
+ 
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+  
+
+wire op_sextb;
+wire op_sexth;
+ 
+
+wire op_sh;
+  
+
+wire op_sl;
+ 
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+  
+ 
+
+
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+  
+
+wire shift;
+ 
+
+  
+ 
+
+
+  
+
+wire sext;
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+assign op_add    = instruction[ 30:26] ==  5'b01101;
+assign op_and    = instruction[ 30:26] ==  5'b01000;
+assign op_andhi  = instruction[ 31:26] ==  6'b011000;
+assign op_b      = instruction[ 31:26] ==  6'b110000;
+assign op_bi     = instruction[ 31:26] ==  6'b111000;
+assign op_be     = instruction[ 31:26] ==  6'b010001;
+assign op_bg     = instruction[ 31:26] ==  6'b010010;
+assign op_bge    = instruction[ 31:26] ==  6'b010011;
+assign op_bgeu   = instruction[ 31:26] ==  6'b010100;
+assign op_bgu    = instruction[ 31:26] ==  6'b010101;
+assign op_bne    = instruction[ 31:26] ==  6'b010111;
+assign op_call   = instruction[ 31:26] ==  6'b110110;
+assign op_calli  = instruction[ 31:26] ==  6'b111110;
+assign op_cmpe   = instruction[ 30:26] ==  5'b11001;
+assign op_cmpg   = instruction[ 30:26] ==  5'b11010;
+assign op_cmpge  = instruction[ 30:26] ==  5'b11011;
+assign op_cmpgeu = instruction[ 30:26] ==  5'b11100;
+assign op_cmpgu  = instruction[ 30:26] ==  5'b11101;
+assign op_cmpne  = instruction[ 30:26] ==  5'b11111;
+  
+
+assign op_divu   = instruction[ 31:26] ==  6'b100011;
+ 
+
+assign op_lb     = instruction[ 31:26] ==  6'b000100;
+assign op_lbu    = instruction[ 31:26] ==  6'b010000;
+assign op_lh     = instruction[ 31:26] ==  6'b000111;
+assign op_lhu    = instruction[ 31:26] ==  6'b001011;
+assign op_lw     = instruction[ 31:26] ==  6'b001010;
+  
+
+assign op_modu   = instruction[ 31:26] ==  6'b110001;
+ 
+
+  
+
+assign op_mul    = instruction[ 30:26] ==  5'b00010;
+ 
+
+assign op_nor    = instruction[ 30:26] ==  5'b00001;
+assign op_or     = instruction[ 30:26] ==  5'b01110;
+assign op_orhi   = instruction[ 31:26] ==  6'b011110;
+assign op_raise  = instruction[ 31:26] ==  6'b101011;
+assign op_rcsr   = instruction[ 31:26] ==  6'b100100;
+assign op_sb     = instruction[ 31:26] ==  6'b001100;
+  
+
+assign op_sextb  = instruction[ 31:26] ==  6'b101100;
+assign op_sexth  = instruction[ 31:26] ==  6'b110111;
+ 
+
+assign op_sh     = instruction[ 31:26] ==  6'b000011;
+  
+
+assign op_sl     = instruction[ 30:26] ==  5'b01111;      
+ 
+
+assign op_sr     = instruction[ 30:26] ==  5'b00101;
+assign op_sru    = instruction[ 30:26] ==  5'b00000;
+assign op_sub    = instruction[ 31:26] ==  6'b110010;
+assign op_sw     = instruction[ 31:26] ==  6'b010110;
+  
+       
+
+
+assign op_wcsr   = instruction[ 31:26] ==  6'b110100;
+assign op_xnor   = instruction[ 30:26] ==  5'b01001;
+assign op_xor    = instruction[ 30:26] ==  5'b00110;
+
+
+assign arith = op_add | op_sub;
+assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
+assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
+assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
+assign bi_unconditional = op_bi;
+assign bra = op_b | bi_unconditional | bi_conditional;
+assign call = op_call | op_calli;
+  
+
+assign shift = op_sl | op_sr | op_sru;
+ 
+
+  
+     
+
+
+  
+   
+     
+
+
+  
+
+assign sext = op_sextb | op_sexth;
+ 
+
+  
+   
+
+
+  
+
+assign divide = op_divu; 
+assign modulus = op_modu;
+ 
+
+assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
+assign store = op_sb | op_sh | op_sw;
+
+
+always @(*)
+begin
+    
+    if (call) 
+        d_result_sel_0 =  1'b1;
+    else 
+        d_result_sel_0 =  1'b0;
+    if (call) 
+        d_result_sel_1 =  2'b00;         
+    else if ((instruction[31] == 1'b0) && !bra) 
+        d_result_sel_1 =  2'b10;
+    else
+        d_result_sel_1 =  2'b01; 
+    
+    x_result_sel_csr =  1'b0;
+  
+
+    x_result_sel_mc_arith =  1'b0;
+ 
+
+  
+      
+
+
+  
+
+    x_result_sel_sext =  1'b0;
+ 
+
+    x_result_sel_logic =  1'b0;
+          
+      
+
+
+    x_result_sel_add =  1'b0;
+    if (op_rcsr)
+        x_result_sel_csr =  1'b1;
+  
+    
+  
+         
+          
+
+
+  
+
+    else if (divide | modulus)
+        x_result_sel_mc_arith =  1'b1;        
+ 
+
+  
+      
+                      
+
+
+ 
+
+  
+      
+                  
+
+
+  
+
+    else if (sext)
+        x_result_sel_sext =  1'b1;
+ 
+        
+    else if (logical) 
+        x_result_sel_logic =  1'b1;
+          
+      
+          
+
+
+    else 
+        x_result_sel_add =  1'b1;        
+    
+    
+
+    m_result_sel_compare = cmp;
+  
+
+    m_result_sel_shift = shift;
+ 
+
+
+    
+    w_result_sel_load = load;
+  
+
+    w_result_sel_mul = op_mul; 
+ 
+
+end
+
+
+assign x_bypass_enable =  arith 
+                        | logical
+  
+                         
+                         
+
+                        
+  
+                         
+
+
+  
+
+                        | divide
+                        | modulus
+ 
+
+  
+                         
+
+                  
+  
+
+                        | sext 
+ 
+                        
+  
+                         
+
+
+                        | op_rcsr
+                        ;
+
+assign m_bypass_enable = x_bypass_enable 
+  
+
+                        | shift
+ 
+
+                        | cmp
+                        ;
+
+assign read_enable_0 = ~(op_bi | op_calli);
+assign read_idx_0 = instruction[25:21];
+
+assign read_enable_1 = ~(op_bi | op_calli | load);
+assign read_idx_1 = instruction[20:16];
+
+assign write_enable = ~(bra | op_raise | store | op_wcsr);
+assign write_idx = call
+                    ? 5'd29
+                    : instruction[31] == 1'b0 
+                        ? instruction[20:16] 
+                        : instruction[15:11];
+                        
+
+assign size = instruction[27:26];
+
+assign sign_extend = instruction[28];                      
+
+assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
+
+assign logic_op = instruction[29:26];
+  
+
+
+assign direction = instruction[29];
+ 
+
+
+assign branch = bra | call;
+assign branch_reg = op_call | op_b;
+assign condition = instruction[28:26];      
+  
+
+assign break_opcode = op_raise & ~instruction[2];
+ 
+
+assign scall = op_raise & instruction[2];
+assign eret = op_b & (instruction[25:21] == 5'd30);
+  
+
+assign bret = op_b & (instruction[25:21] == 5'd31);
+ 
+
+  
+
+   
+
+
+
+assign csr_write_enable = op_wcsr;
+
+
+
+assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
+assign select_high_immediate = op_andhi | op_orhi;
+assign select_call_immediate = instruction[31];
+
+assign high_immediate = {instruction[15:0], 16'h0000};
+assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
+assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
+assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
+
+assign immediate = select_high_immediate ==  1'b1 
+                        ? high_immediate 
+                        : extended_immediate;
+   
+assign branch_offset = select_call_immediate ==  1'b1   
+                        ? (call_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0])
+                        : (branch_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0]);
+    
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_icache_full_debug ( 
+    
+    clk_i,
+    rst_i,    
+    stall_a,
+    stall_f,
+    address_a,
+    address_f,
+    read_enable_f,
+    refill_ready,
+    refill_data,
+    iflush,
+  
+    
+
+
+    valid_d,
+    branch_predict_taken_d,
+    
+    stall_request,
+    restart_request,
+    refill_request,
+    refill_address,
+    refilling,
+    inst
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
+localparam addr_set_width = clogb2(sets)-1;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+localparam addr_set_lsb = (addr_offset_msb+1);
+localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
+localparam addr_tag_lsb = (addr_set_msb+1);
+localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
+
+
+
+
+
+input clk_i;                                        
+input rst_i;                                        
+
+input stall_a;                                      
+input stall_f;                                      
+
+input valid_d;                                      
+input branch_predict_taken_d;                       
+   
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;                     
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;                     
+input read_enable_f;                                
+
+input refill_ready;                                 
+input [ (32-1):0] refill_data;          
+
+input iflush;                                       
+  
+                                      
+
+
+   
+
+
+
+
+output stall_request;                               
+wire   stall_request;
+output restart_request;                             
+reg    restart_request;
+output refill_request;                              
+wire   refill_request;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+output refilling;                                   
+reg    refilling;
+output [ (32-1):0] inst;                
+wire   [ (32-1):0] inst;
+
+
+
+
+
+wire enable;
+wire [0:associativity-1] way_mem_we;
+wire [ (32-1):0] way_data[0:associativity-1];
+wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [0:associativity-1] way_valid;
+wire [0:associativity-1] way_match;
+wire miss;
+
+wire [ (addr_set_width-1):0] tmem_read_address;
+wire [ (addr_set_width-1):0] tmem_write_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
+wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
+
+reg [ 3:0] state;
+wire flushing;
+wire check;
+wire refill;
+
+reg [associativity-1:0] refill_way_select;
+reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
+wire last_refill;
+reg [ (addr_set_width-1):0] flush_set;
+
+genvar i;
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+   generate
+      for (i = 0; i < associativity; i = i + 1)
+	begin : memories
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 (32),
+	       .address_width              ( (addr_offset_width+addr_set_width))
+
+) 
+	   way_0_data_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (dmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (dmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i]),
+	      .write_data                 (refill_data),    
+	      
+	      .read_data                  (way_data[i])
+	      );
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 ( (addr_tag_width+1)),
+	       .address_width              ( addr_set_width)
+
+	       ) 
+	   way_0_tag_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (tmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (tmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i] | flushing),
+	      .write_data                 (tmem_write_data),
+	      
+	      .read_data                  ({way_tag[i], way_valid[i]})
+	      );
+	   
+	end
+endgenerate
+
+
+
+
+
+
+generate
+    for (i = 0; i < associativity; i = i + 1)
+    begin : match
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[ addr_tag_msb:addr_tag_lsb],  1'b1});
+    end
+endgenerate
+
+
+generate
+    if (associativity == 1)
+    begin : inst_1
+assign inst = way_match[0] ? way_data[0] : 32'b0;
+    end
+    else if (associativity == 2)
+	 begin : inst_2
+assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
+    end
+endgenerate
+
+
+generate 
+    if (bytes_per_line > 4)
+assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset};
+    else
+assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb];
+endgenerate
+    
+assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb];
+
+
+assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb];
+assign tmem_write_address = flushing 
+                                ? flush_set
+                                : refill_address[ addr_set_msb:addr_set_lsb];
+
+
+generate 
+    if (bytes_per_line > 4)                            
+assign last_refill = refill_offset == {addr_offset_width{1'b1}};
+    else
+assign last_refill =  1'b1;
+endgenerate
+
+
+assign enable = (stall_a ==  1'b0);
+
+
+generate
+    if (associativity == 1) 
+    begin : we_1     
+assign way_mem_we[0] = (refill_ready ==  1'b1);
+    end
+    else
+    begin : we_2
+assign way_mem_we[0] = (refill_ready ==  1'b1) && (refill_way_select[0] ==  1'b1);
+assign way_mem_we[1] = (refill_ready ==  1'b1) && (refill_way_select[1] ==  1'b1);
+    end
+endgenerate                     
+
+
+assign tmem_write_data[ 0] = last_refill & !flushing;
+assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+
+
+assign flushing = |state[1:0];
+assign check = state[2];
+assign refill = state[3];
+
+assign miss = (~(|way_match)) && (read_enable_f ==  1'b1) && (stall_f ==  1'b0) && !(valid_d && branch_predict_taken_d);
+assign stall_request = (check ==  1'b0);
+assign refill_request = (refill ==  1'b1);
+                      
+
+
+
+
+
+generate
+    if (associativity >= 2) 
+    begin : way_select      
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
+    else
+    begin        
+        if (miss ==  1'b1)
+            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
+    end
+end
+    end
+endgenerate
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refilling <=  1'b0;
+    else
+        refilling <= refill;
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  4'b0001;
+        flush_set <= { addr_set_width{1'b1}};
+        refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+        restart_request <=  1'b0;
+    end
+    else 
+    begin
+        case (state)
+
+        
+         4'b0001:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+                state <=  4'b0100;
+            flush_set <= flush_set - 1'b1;
+        end
+
+        
+         4'b0010:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+  
+	       
+                  
+	      
+
+
+		state <=  4'b0100;
+	   
+            flush_set <= flush_set - 1'b1;
+        end
+        
+        
+         4'b0100:
+        begin            
+            if (stall_a ==  1'b0)
+                restart_request <=  1'b0;
+            if (iflush ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b0010;
+            end
+            else if (miss ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b1000;
+            end
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+            begin
+                if (last_refill ==  1'b1)
+                begin
+                    restart_request <=  1'b1;
+                    state <=  4'b0100;
+                end
+            end
+        end
+
+        endcase        
+    end
+end
+
+generate 
+    if (bytes_per_line > 4)
+    begin
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_offset <= {addr_offset_width{1'b0}};
+    else 
+    begin
+        case (state)
+        
+        
+         4'b0100:
+        begin            
+            if (iflush ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+            else if (miss ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+                refill_offset <= refill_offset + 1'b1;
+        end
+
+        endcase        
+    end
+end
+    end
+endgenerate
+   
+endmodule
+
+ 
+
+
+
+
+
+
+
+
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+								 
+  
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+  
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+ 
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+     
+    
+   
+  
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+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
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+ 
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+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
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+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
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+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
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+ 
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+ 
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+
+
+                   
+             
+               
+
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+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
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+
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+  
+
+
+  
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+  
+
+  
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+  
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+  
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+  
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+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_dcache_full_debug ( 
+    
+    clk_i,
+    rst_i,    
+    stall_a,
+    stall_x,
+    stall_m,
+    address_x,
+    address_m,
+    load_q_m,
+    store_q_m,
+    store_data,
+    store_byte_select,
+    refill_ready,
+    refill_data,
+    dflush,
+    
+    stall_request,
+    restart_request,
+    refill_request,
+    refill_address,
+    refilling,
+    load_data
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
+localparam addr_set_width = clogb2(sets)-1;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+localparam addr_set_lsb = (addr_offset_msb+1);
+localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
+localparam addr_tag_lsb = (addr_set_msb+1);
+localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
+
+
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+
+input [ (32-1):0] address_x;                       
+input [ (32-1):0] address_m;                       
+input load_q_m;                                         
+input store_q_m;                                        
+input [ (32-1):0] store_data;                      
+input [ (4-1):0] store_byte_select;        
+
+input refill_ready;                                     
+input [ (32-1):0] refill_data;                     
+
+input dflush;                                           
+
+
+
+
+
+output stall_request;                                   
+wire   stall_request;
+output restart_request;                                 
+reg    restart_request;
+output refill_request;                                  
+reg    refill_request;
+output [ (32-1):0] refill_address;                 
+reg    [ (32-1):0] refill_address;
+output refilling;                                       
+reg    refilling;
+output [ (32-1):0] load_data;                      
+wire   [ (32-1):0] load_data;
+
+
+
+
+
+wire read_port_enable;                                  
+wire write_port_enable;                                 
+wire [0:associativity-1] way_tmem_we;                   
+wire [0:associativity-1] way_dmem_we;                   
+wire [ (32-1):0] way_data[0:associativity-1];      
+wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [0:associativity-1] way_valid;                     
+wire [0:associativity-1] way_match;                     
+wire miss;                                              
+
+wire [ (addr_set_width-1):0] tmem_read_address;        
+wire [ (addr_set_width-1):0] tmem_write_address;       
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;        
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;       
+wire [ ((addr_tag_width+1)-1):0] tmem_write_data;               
+reg [ (32-1):0] dmem_write_data;                   
+
+reg [ 2:0] state;                         
+wire flushing;                                          
+wire check;                                             
+wire refill;                                            
+
+wire valid_store;                                       
+reg [associativity-1:0] refill_way_select;              
+reg [ addr_offset_msb:addr_offset_lsb] refill_offset;           
+wire last_refill;                                       
+reg [ (addr_set_width-1):0] flush_set;                 
+
+genvar i, j;
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+   generate
+      for (i = 0; i < associativity; i = i + 1)    
+	begin : memories
+	   
+           if ( (addr_offset_width+addr_set_width) < 11)
+             begin : data_memories
+		lm32_ram 
+		  #(
+		    
+		    .data_width (32),
+		    .address_width ( (addr_offset_width+addr_set_width))
+
+		    ) way_0_data_ram 
+		    (
+		     
+		     .read_clk (clk_i),
+		     .write_clk (clk_i),
+		     .reset (rst_i),
+		     .read_address (dmem_read_address),
+		     .enable_read (read_port_enable),
+		     .write_address (dmem_write_address),
+		     .enable_write (write_port_enable),
+		     .write_enable (way_dmem_we[i]),
+		     .write_data (dmem_write_data),    
+		     
+		     .read_data (way_data[i])
+		     );    
+             end
+           else
+             begin
+		for (j = 0; j < 4; j = j + 1)    
+		  begin : byte_memories
+		     lm32_ram 
+		       #(
+			 
+			 .data_width (8),
+			 .address_width ( (addr_offset_width+addr_set_width))
+
+			 ) way_0_data_ram 
+			 (
+			  
+			  .read_clk (clk_i),
+			  .write_clk (clk_i),
+			  .reset (rst_i),
+			  .read_address (dmem_read_address),
+			  .enable_read (read_port_enable),
+			  .write_address (dmem_write_address),
+			  .enable_write (write_port_enable),
+			  .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
+			  .write_data (dmem_write_data[(j+1)*8-1:j*8]),    
+			  
+			  .read_data (way_data[i][(j+1)*8-1:j*8])
+			  );
+		  end
+             end
+	   
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width ( (addr_tag_width+1)),
+	       .address_width ( addr_set_width)
+
+	       ) way_0_tag_ram 
+	       (
+		
+		.read_clk (clk_i),
+		.write_clk (clk_i),
+		.reset (rst_i),
+		.read_address (tmem_read_address),
+		.enable_read (read_port_enable),
+		.write_address (tmem_write_address),
+		.enable_write ( 1'b1),
+		.write_enable (way_tmem_we[i]),
+		.write_data (tmem_write_data),
+		
+		.read_data ({way_tag[i], way_valid[i]})
+		);
+	end
+      
+   endgenerate
+
+
+
+
+
+
+generate
+    for (i = 0; i < associativity; i = i + 1)
+    begin : match
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[ addr_tag_msb:addr_tag_lsb],  1'b1});
+    end
+endgenerate
+
+
+generate
+    if (associativity == 1)    
+	 begin : data_1
+assign load_data = way_data[0];
+    end
+    else if (associativity == 2)
+	 begin : data_2
+assign load_data = way_match[0] ? way_data[0] : way_data[1]; 
+    end
+endgenerate
+
+generate
+    if ( (addr_offset_width+addr_set_width) < 11)
+    begin
+
+always @(*)
+begin
+    if (refill ==  1'b1)
+        dmem_write_data = refill_data;
+    else
+    begin
+        dmem_write_data[ 7:0] = store_byte_select[0] ? store_data[ 7:0] : load_data[ 7:0];
+        dmem_write_data[ 15:8] = store_byte_select[1] ? store_data[ 15:8] : load_data[ 15:8];
+        dmem_write_data[ 23:16] = store_byte_select[2] ? store_data[ 23:16] : load_data[ 23:16];
+        dmem_write_data[ 31:24] = store_byte_select[3] ? store_data[ 31:24] : load_data[ 31:24];
+    end
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    if (refill ==  1'b1)
+        dmem_write_data = refill_data;
+    else
+        dmem_write_data = store_data;
+end
+    end
+endgenerate
+
+
+generate 
+     if (bytes_per_line > 4)
+assign dmem_write_address = (refill ==  1'b1) 
+                            ? {refill_address[ addr_set_msb:addr_set_lsb], refill_offset}
+                            : address_m[ addr_set_msb:addr_offset_lsb];
+    else
+assign dmem_write_address = (refill ==  1'b1) 
+                            ? refill_address[ addr_set_msb:addr_set_lsb]
+                            : address_m[ addr_set_msb:addr_offset_lsb];
+endgenerate
+assign dmem_read_address = address_x[ addr_set_msb:addr_offset_lsb];
+
+assign tmem_write_address = (flushing ==  1'b1)
+                            ? flush_set
+                            : refill_address[ addr_set_msb:addr_set_lsb];
+assign tmem_read_address = address_x[ addr_set_msb:addr_set_lsb];
+
+
+generate 
+    if (bytes_per_line > 4)                            
+assign last_refill = refill_offset == {addr_offset_width{1'b1}};
+    else
+assign last_refill =  1'b1;
+endgenerate
+
+
+assign read_port_enable = (stall_x ==  1'b0);
+assign write_port_enable = (refill_ready ==  1'b1) || !stall_m;
+
+
+assign valid_store = (store_q_m ==  1'b1) && (check ==  1'b1);
+
+
+generate
+    if (associativity == 1) 
+    begin : we_1     
+assign way_dmem_we[0] = (refill_ready ==  1'b1) || ((valid_store ==  1'b1) && (way_match[0] ==  1'b1));
+assign way_tmem_we[0] = (refill_ready ==  1'b1) || (flushing ==  1'b1);
+    end 
+    else 
+    begin : we_2
+assign way_dmem_we[0] = ((refill_ready ==  1'b1) && (refill_way_select[0] ==  1'b1)) || ((valid_store ==  1'b1) && (way_match[0] ==  1'b1));
+assign way_dmem_we[1] = ((refill_ready ==  1'b1) && (refill_way_select[1] ==  1'b1)) || ((valid_store ==  1'b1) && (way_match[1] ==  1'b1));
+assign way_tmem_we[0] = ((refill_ready ==  1'b1) && (refill_way_select[0] ==  1'b1)) || (flushing ==  1'b1);
+assign way_tmem_we[1] = ((refill_ready ==  1'b1) && (refill_way_select[1] ==  1'b1)) || (flushing ==  1'b1);
+    end
+endgenerate
+
+
+assign tmem_write_data[ 0] = ((last_refill ==  1'b1) || (valid_store ==  1'b1)) && (flushing ==  1'b0);
+assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+
+
+assign flushing = state[0];
+assign check = state[1];
+assign refill = state[2];
+
+assign miss = (~(|way_match)) && (load_q_m ==  1'b1) && (stall_m ==  1'b0);
+assign stall_request = (check ==  1'b0);
+                      
+
+
+
+
+
+generate
+    if (associativity >= 2) 
+    begin : way_select      
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
+    else
+    begin        
+        if (refill_request ==  1'b1)
+            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
+    end
+end
+    end 
+endgenerate   
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refilling <=  1'b0;
+    else 
+        refilling <= refill;
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  3'b001;
+        flush_set <= { addr_set_width{1'b1}};
+        refill_request <=  1'b0;
+        refill_address <= { 32{1'bx}};
+        restart_request <=  1'b0;
+    end
+    else 
+    begin
+        case (state)
+
+        
+         3'b001:
+        begin
+            if (flush_set == { addr_set_width{1'b0}})
+                state <=  3'b010;
+            flush_set <= flush_set - 1'b1;
+        end
+        
+        
+         3'b010:
+        begin
+            if (stall_a ==  1'b0)
+                restart_request <=  1'b0;
+            if (miss ==  1'b1)
+            begin
+                refill_request <=  1'b1;
+                refill_address <= address_m;
+                state <=  3'b100;
+            end
+            else if (dflush ==  1'b1)
+                state <=  3'b001;
+        end
+
+        
+         3'b100:
+        begin
+            refill_request <=  1'b0;
+            if (refill_ready ==  1'b1)
+            begin
+                if (last_refill ==  1'b1)
+                begin
+                    restart_request <=  1'b1;
+                    state <=  3'b010;
+                end
+            end
+        end
+        
+        endcase        
+    end
+end
+
+generate
+    if (bytes_per_line > 4)
+    begin
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_offset <= {addr_offset_width{1'b0}};
+    else 
+    begin
+        case (state)
+        
+        
+         3'b010:
+        begin
+            if (miss ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+        end
+
+        
+         3'b100:
+        begin
+            if (refill_ready ==  1'b1)
+                refill_offset <= refill_offset + 1'b1;
+        end
+        
+        endcase        
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+ 
+
+
+
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+                  
+                    
+                 
+                   
+           
+             
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+                   
+               
+                 
+
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+                      
+                      
+                      
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+ 
+                    
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+                    
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+  
+                    
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+                      
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+           
+             
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+                
+           
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+              
+               
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+                    
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+                
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+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
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+                      
+                      
+                      
+                     
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+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
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+ 
+
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+ 
+
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+
+
+
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+                   
+             
+               
+
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+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
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+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
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+
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+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_debug_full_debug (
+    
+    clk_i, 
+    rst_i,
+    pc_x,
+    load_x,
+    store_x,
+    load_store_address_x,
+    csr_write_enable_x,
+    csr_write_data,
+    csr_x,
+  
+
+  
+
+    jtag_csr_write_enable,
+    jtag_csr_write_data,
+    jtag_csr,
+ 
+
+  
+   
+   
+   
+
+
+  
+
+
+		   
+  
+
+    eret_q_x,
+    bret_q_x,
+    stall_x,
+    exception_x,
+    q_x,
+  
+
+    dcache_refill_request,
+ 
+
+ 
+
+
+    
+  
+
+    dc_ss,
+ 
+
+    dc_re,
+    bp_match,
+    wp_match
+    );
+    
+
+
+
+
+parameter breakpoints = 0;                      
+parameter watchpoints = 0;                      
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                      
+input load_x;                                   
+input store_x;                                  
+input [ (32-1):0] load_store_address_x;    
+input csr_write_enable_x;                       
+input [ (32-1):0] csr_write_data;          
+input [ (5-1):0] csr_x;                    
+  
+
+  
+
+input jtag_csr_write_enable;                    
+input [ (32-1):0] jtag_csr_write_data;     
+input [ (5-1):0] jtag_csr;                 
+ 
+
+     
+                          
+            
+                          
+
+
+ 
+
+
+
+  
+
+input eret_q_x;                                 
+input bret_q_x;                                 
+input stall_x;                                  
+input exception_x;                              
+input q_x;                                      
+  
+
+input dcache_refill_request;                    
+ 
+
+ 
+
+
+
+
+
+
+  
+
+output dc_ss;                                   
+reg    dc_ss;
+ 
+
+output dc_re;                                   
+reg    dc_re;
+output bp_match;                                
+wire   bp_match;        
+output wp_match;                                
+wire   wp_match;
+
+
+
+
+
+genvar i;                                       
+
+
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];       
+reg bp_e[0:breakpoints-1];                      
+wire [0:breakpoints-1]bp_match_n;               
+
+reg [ 1:0] wpc_c[0:watchpoints-1];   
+reg [ (32-1):0] wp[0:watchpoints-1];       
+wire [0:watchpoints-1]wp_match_n;               
+
+wire debug_csr_write_enable;                    
+wire [ (32-1):0] debug_csr_write_data;     
+wire [ (5-1):0] debug_csr;                 
+
+  
+
+
+reg [ 2:0] state;           
+
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+generate
+    for (i = 0; i < breakpoints; i = i + 1)
+    begin : bp_comb
+assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] ==  1'b1));
+    end
+endgenerate
+generate 
+  
+
+    if (breakpoints > 0) 
+assign bp_match = (|bp_match_n) || (state ==  3'b011);
+    else
+assign bp_match = state ==  3'b011;
+ 
+        
+   
+    
+   
+
+
+endgenerate    
+               
+
+generate 
+    for (i = 0; i < watchpoints; i = i + 1)
+    begin : wp_comb
+assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
+    end               
+endgenerate
+generate
+    if (watchpoints > 0) 
+assign wp_match = |wp_match_n;                
+    else
+assign wp_match =  1'b0;
+endgenerate
+                
+  
+                
+
+  
+
+assign debug_csr_write_enable = (csr_write_enable_x ==  1'b1) || (jtag_csr_write_enable ==  1'b1);
+assign debug_csr_write_data = jtag_csr_write_enable ==  1'b1 ? jtag_csr_write_data : csr_write_data;
+assign debug_csr = jtag_csr_write_enable ==  1'b1 ? jtag_csr : csr_x;
+ 
+
+   
+  
+         
+         
+         
+
+
+
+   
+ 
+   
+   
+   
+
+
+
+
+
+
+
+
+generate
+    for (i = 0; i < breakpoints; i = i + 1)
+    begin : bp_seq
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+        bp_e[i] <=  1'b0;
+    end
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h10 + i))
+        begin
+            bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+            bp_e[i] <= debug_csr_write_data[0];
+        end
+    end
+end    
+    end
+endgenerate
+
+
+generate
+    for (i = 0; i < watchpoints; i = i + 1)
+    begin : wp_seq
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        wp[i] <= { 32{1'bx}};
+        wpc_c[i] <=  2'b00;
+    end
+    else
+    begin
+        if (debug_csr_write_enable ==  1'b1)
+        begin
+            if (debug_csr ==  5'h8)
+                wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
+            if (debug_csr ==  5'h18 + i)
+                wp[i] <= debug_csr_write_data;
+        end
+    end  
+end
+    end
+endgenerate
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        dc_re <=  1'b0;
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h8))
+            dc_re <= debug_csr_write_data[1];
+    end
+end    
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  3'b000;
+        dc_ss <=  1'b0;
+    end
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h8))
+        begin
+            dc_ss <= debug_csr_write_data[0];
+            if (debug_csr_write_data[0] ==  1'b0) 
+                state <=  3'b000;
+            else 
+                state <=  3'b001;
+        end
+        case (state)
+         3'b001:
+        begin
+            
+            if (   (   (eret_q_x ==  1'b1)
+                    || (bret_q_x ==  1'b1)
+                    )
+                && (stall_x ==  1'b0)
+               )
+                state <=  3'b010; 
+        end
+         3'b010:
+        begin
+            
+            if ((q_x ==  1'b1) && (stall_x ==  1'b0))
+                state <=  3'b011;
+        end
+         3'b011:
+        begin
+            
+  
+
+            if (dcache_refill_request ==  1'b1)
+                state <=  3'b010;
+            else 
+ 
+
+                 if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+            begin
+                dc_ss <=  1'b0;
+                state <=  3'b100;
+            end
+        end
+         3'b100:
+        begin
+            
+  
+
+            if (dcache_refill_request ==  1'b1)
+                state <=  3'b010;
+            else 
+ 
+
+                state <=  3'b000;
+        end
+        endcase
+    end
+end
+ 
+
+
+endmodule
+
+ 
+
+
+
+
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+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
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+ 
+ 
+ 
+ 
+ 
+
+ 
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+ 
+
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+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_instruction_unit_full_debug (
+    
+    clk_i,
+    rst_i,
+    
+    stall_a,
+    stall_f,
+    stall_d,
+    stall_x,
+    stall_m,
+    valid_f,
+    valid_d,
+    kill_f,
+    branch_predict_taken_d,
+    branch_predict_address_d,
+  
+    
+    branch_taken_x,
+    branch_target_x,
+ 
+
+    exception_m,
+    branch_taken_m,
+    branch_mispredict_taken_m,
+    branch_target_m,
+  
+
+    iflush,
+ 
+
+  
+
+    dcache_restart_request,
+    dcache_refill_request,
+    dcache_refilling,
+ 
+        
+  
+
+    
+    i_dat_i,
+    i_ack_i,
+    i_err_i,
+    i_rty_i,
+ 
+
+  
+
+    jtag_read_enable,
+    jtag_write_enable,
+    jtag_write_data,
+    jtag_address,
+ 
+
+    
+    
+    pc_f,
+    pc_d,
+    pc_x,
+    pc_m,
+    pc_w,
+  
+
+    icache_stall_request,
+    icache_restart_request,
+    icache_refill_request,
+    icache_refilling,
+ 
+
+  
+
+    
+    i_dat_o,
+    i_adr_o,
+    i_cyc_o,
+    i_sel_o,
+    i_stb_o,
+    i_we_o,
+    i_cti_o,
+    i_lock_o,
+    i_bte_o,
+ 
+
+  
+    
+    
+    
+
+
+  
+
+    jtag_read_data,
+    jtag_access_complete,
+ 
+
+  
+
+    bus_error_d,
+ 
+
+  
+
+    instruction_f,
+ 
+    
+    instruction_d
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                   
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam eba_reset_minus_4 = eba_reset - 4;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+  
+  
+   
+        
+   
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_f;                                          
+input stall_d;                                          
+input stall_x;                                          
+input stall_m;                                          
+input valid_f;                                          
+input valid_d;                                          
+input kill_f;                                           
+
+input branch_predict_taken_d;                           
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;          
+   
+  
+    
+input branch_taken_x;                                   
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;                   
+ 
+
+input exception_m;
+input branch_taken_m;                                   
+input branch_mispredict_taken_m;                        
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;                   
+
+  
+
+input iflush;                                           
+ 
+
+  
+
+input dcache_restart_request;                           
+input dcache_refill_request;                            
+input dcache_refilling;
+ 
+        
+
+
+  
+
+input [ (32-1):0] i_dat_i;                         
+input i_ack_i;                                          
+input i_err_i;                                          
+input i_rty_i;                                          
+ 
+
+
+  
+
+input jtag_read_enable;                                 
+input jtag_write_enable;                                
+input [ 7:0] jtag_write_data;                 
+input [ (32-1):0] jtag_address;                    
+ 
+
+
+
+
+
+        
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
+  
+
+output icache_stall_request;                            
+wire   icache_stall_request;
+output icache_restart_request;                          
+wire   icache_restart_request;
+output icache_refill_request;                           
+wire   icache_refill_request;
+output icache_refilling;                                
+wire   icache_refilling;
+ 
+
+
+  
+
+output [ (32-1):0] i_dat_o;                        
+  
+
+reg    [ (32-1):0] i_dat_o;
+ 
+    
+
+
+output [ (32-1):0] i_adr_o;                        
+reg    [ (32-1):0] i_adr_o;
+output i_cyc_o;                                         
+reg    i_cyc_o; 
+output [ (4-1):0] i_sel_o;                 
+  
+
+reg    [ (4-1):0] i_sel_o;
+ 
+    
+
+
+output i_stb_o;                                         
+reg    i_stb_o;
+output i_we_o;                                          
+  
+
+reg    i_we_o;
+ 
+   
+
+
+output [ (3-1):0] i_cti_o;                       
+reg    [ (3-1):0] i_cti_o;
+output i_lock_o;                                        
+reg    i_lock_o;
+output [ (2-1):0] i_bte_o;                       
+wire   [ (2-1):0] i_bte_o;
+ 
+
+
+  
+
+output [ 7:0] jtag_read_data;                 
+reg    [ 7:0] jtag_read_data;
+output jtag_access_complete;                            
+wire   jtag_access_complete;
+ 
+
+
+  
+
+output bus_error_d;                                     
+reg    bus_error_d;
+ 
+
+  
+
+output [ (32-1):0] instruction_f;           
+wire   [ (32-1):0] instruction_f;
+ 
+
+output [ (32-1):0] instruction_d;           
+reg    [ (32-1):0] instruction_d;
+
+
+
+
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;                                
+
+  
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;                     
+ 
+
+
+  
+
+wire icache_read_enable_f;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;              
+reg icache_refill_ready;                                
+reg [ (32-1):0] icache_refill_data;         
+wire [ (32-1):0] icache_data_f;             
+wire [ (3-1):0] first_cycle_type;                
+wire [ (3-1):0] next_cycle_type;                 
+wire last_word;                                         
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;                      
+ 
+ 
+                    
+
+
+
+  
+                                      
+    			     
+   
+
+
+  
+
+ 
+               
+
+
+
+  
+ 
+   
+
+   
+   reg 			     bus_error_f;          
+  
+
+ 
+
+  
+    		       
+
+
+   
+  
+
+reg jtag_access;                                        
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+
+lm32_icache_full_debug #(
+    .associativity          (associativity),
+    .sets                   (sets),
+    .bytes_per_line         (bytes_per_line),
+    .base_address           (base_address),
+    .limit                  (limit)
+    ) icache ( 
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),      
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .valid_d                (valid_d),
+    .address_a              (pc_a),
+    .address_f              (pc_f),
+    .read_enable_f          (icache_read_enable_f),
+    .refill_ready           (icache_refill_ready),
+    .refill_data            (icache_refill_data),
+    .iflush                 (iflush),
+    
+    .stall_request          (icache_stall_request),
+    .restart_request        (icache_restart_request),
+    .refill_request         (icache_refill_request),
+    .refill_address         (icache_refill_address),
+    .refilling              (icache_refilling),
+    .inst                   (icache_data_f)
+    );
+ 
+
+
+
+
+
+
+  
+
+   
+   assign icache_read_enable_f =    (valid_f ==  1'b1)
+     && (kill_f ==  1'b0)
+   
+
+   && (dcache_restart_request ==  1'b0)
+  
+                         
+    
+				       
+ 
+       
+				    ;
+ 
+ 
+
+
+always @(*)
+begin
+    
+  
+
+    if (dcache_restart_request ==  1'b1)
+        pc_a = restart_address;
+    else 
+ 
+    
+      if (branch_taken_m ==  1'b1)
+	if ((branch_mispredict_taken_m ==  1'b1) && (exception_m ==  1'b0))
+	  pc_a = pc_x;
+	else
+          pc_a = branch_target_m;
+  
+    
+      else if (branch_taken_x ==  1'b1)
+        pc_a = branch_target_x;
+ 
+
+      else
+	if ( (valid_d ==  1'b1) && (branch_predict_taken_d ==  1'b1) )
+	  pc_a = branch_predict_address_d;
+	else
+  
+
+          if (icache_restart_request ==  1'b1)
+            pc_a = restart_address;
+	  else 
+ 
+        
+            pc_a = pc_f + 1'b1;
+end
+
+
+  
+      
+      
+        
+
+
+
+  
+
+     
+    	      
+
+     
+      
+	  
+       
+	  
+	
+	    
+     
+   
+   
+          
+
+
+  
+   
+
+
+                     
+
+  
+
+assign instruction_f = icache_data_f;
+ 
+   
+
+
+
+ 
+ 
+   
+
+  
+
+  
+
+ 
+   
+   
+   
+
+
+assign i_bte_o =  2'b00;
+ 
+
+
+  
+
+
+generate
+    case (bytes_per_line)
+    4:
+    begin
+assign first_cycle_type =  3'b111;
+assign next_cycle_type =  3'b111;
+assign last_word =  1'b1;
+assign first_address = icache_refill_address;
+    end
+    8:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type =  3'b111;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    16:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ?  3'b111 :  3'b010;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    endcase
+endgenerate
+ 
+
+                     
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        pc_f <= eba_reset_minus_4[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+        pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    end
+    else
+    begin
+        if (stall_f ==  1'b0)
+            pc_f <= pc_a;
+        if (stall_d ==  1'b0)
+            pc_d <= pc_f;
+        if (stall_x ==  1'b0)
+            pc_x <= pc_d;
+        if (stall_m ==  1'b0)
+            pc_m <= pc_x;
+        pc_w <= pc_m;
+    end
+end
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    else
+    begin
+  
+
+  
+        
+            
+            if (dcache_refill_request ==  1'b1)
+                restart_address <= pc_w;
+            else if ((icache_refill_request ==  1'b1) && (!dcache_refilling) && (!dcache_restart_request))
+                restart_address <= icache_refill_address;
+ 
+               
+                  
+
+
+ 
+         
+               
+                  
+
+
+
+    end
+end
+ 
+
+
+
+  
+   
+
+       
+          
+    
+    
+           
+              
+    
+
+
+
+
+  
+
+     
+
+assign jtag_access_complete = (i_cyc_o ==  1'b1) && ((i_ack_i ==  1'b1) || (i_err_i ==  1'b1)) && (jtag_access ==  1'b1);
+always @(*)
+begin
+    case (jtag_address[1:0])
+    2'b00: jtag_read_data = i_dat_i[ 31:24];
+    2'b01: jtag_read_data = i_dat_i[ 23:16];
+    2'b10: jtag_read_data = i_dat_i[ 15:8];
+    2'b11: jtag_read_data = i_dat_i[ 7:0];
+    endcase 
+end
+    
+
+ 
+
+
+  
+
+   
+   
+                
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             i_cyc_o <=  1'b0;
+             i_stb_o <=  1'b0;
+             i_adr_o <= { 32{1'b0}};
+             i_cti_o <=  3'b111;
+             i_lock_o <=  1'b0;
+             icache_refill_data <= { 32{1'b0}};
+             icache_refill_ready <=  1'b0;
+    
+
+             bus_error_f <=  1'b0;
+   
+
+    
+
+             i_we_o <=  1'b0;
+             i_sel_o <= 4'b1111;
+             jtag_access <=  1'b0;
+   
+
+	  end
+	else
+	  begin   
+             icache_refill_ready <=  1'b0;
+             
+             if (i_cyc_o ==  1'b1)
+               begin
+		  
+		  if ((i_ack_i ==  1'b1) || (i_err_i ==  1'b1))
+		    begin
+    
+
+                       if (jtag_access ==  1'b1)
+			 begin
+			    i_cyc_o <=  1'b0;
+			    i_stb_o <=  1'b0;       
+			    i_we_o <=  1'b0;  
+			    jtag_access <=  1'b0;    
+			 end
+                       else
+   
+
+			 begin
+			    if (last_word ==  1'b1)
+			      begin
+				 
+				 i_cyc_o <=  1'b0;
+				 i_stb_o <=  1'b0;
+				 i_lock_o <=  1'b0;
+			      end
+			    
+			    i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
+			    i_cti_o <= next_cycle_type;
+			    
+			    icache_refill_ready <=  1'b1;
+			    icache_refill_data <= i_dat_i;
+			 end
+		    end
+    
+
+		    
+
+		  if (i_err_i ==  1'b1)
+		    begin
+                       bus_error_f <=  1'b1;
+                       $display ("Instruction bus error. Address: %x", i_adr_o);
+		    end
+		   
+
+   
+
+               end
+             else
+               begin
+		  if ((icache_refill_request ==  1'b1) && (icache_refill_ready ==  1'b0))
+		    begin
+                       
+    
+     
+                       i_sel_o <= 4'b1111;
+   
+
+                       i_adr_o <= {first_address, 2'b00};
+                       i_cyc_o <=  1'b1;
+                       i_stb_o <=  1'b1;                
+                       i_cti_o <= first_cycle_type;
+                       
+    
+
+                       bus_error_f <=  1'b0;
+   
+
+		    end
+    
+
+		  else
+		    begin
+                       if ((jtag_read_enable ==  1'b1) || (jtag_write_enable ==  1'b1))
+			 begin
+			    case (jtag_address[1:0])
+			      2'b00: i_sel_o <= 4'b1000;
+			      2'b01: i_sel_o <= 4'b0100;
+			      2'b10: i_sel_o <= 4'b0010;
+			      2'b11: i_sel_o <= 4'b0001;
+			    endcase
+			    i_adr_o <= jtag_address;
+			    i_dat_o <= {4{jtag_write_data}};
+			    i_cyc_o <=  1'b1;
+			    i_stb_o <=  1'b1;
+			    i_we_o <= jtag_write_enable;
+			    i_cti_o <=  3'b111;
+			    jtag_access <=  1'b1;
+			 end
+		    end 
+   
+                    
+    
+
+		  
+		  
+     
+    
+		  if (branch_taken_x ==  1'b1)
+                    bus_error_f <=  1'b0;
+    
+
+		  if (branch_taken_m ==  1'b1)
+                    bus_error_f <=  1'b0;
+   
+
+               end
+	  end
+     end
+  
+      
+     
+	   
+	  
+               
+               
+               
+               
+               
+               
+   
+               
+  
+	  
+	
+	     
+             
+                
+               
+		  
+		        
+		    
+                       
+                         
+                         
+                       
+                         
+		    
+   
+		   
+		     
+		    
+                         
+                         
+		       
+		    
+		  
+  
+               
+             
+               
+		  
+		         
+    
+			    
+         
+			 
+		    
+                       
+        
+                         
+  
+                          
+                         
+                         
+   
+                         
+  
+		    
+		  
+		    
+	                      
+    
+			         
+         
+			      
+			 
+   
+			      
+  
+			 
+		    
+               
+	  
+     
+ 
+
+ 
+ 
+
+   
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             instruction_d <= { 32{1'b0}};
+  
+
+             bus_error_d <=  1'b0;
+ 
+
+	  end
+	else
+	  begin
+             if (stall_d ==  1'b0)
+               begin
+		  instruction_d <= instruction_f;
+  
+
+		  bus_error_d <= bus_error_f;
+ 
+
+               end
+	  end
+     end  
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
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+ 
+
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+ 
+
+ 
+ 
+
+
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+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_jtag_full_debug (
+    
+    clk_i,
+    rst_i,
+    jtag_clk, 
+    jtag_update,
+    jtag_reg_q,
+    jtag_reg_addr_q,
+  
+
+    csr,
+    csr_write_enable,
+    csr_write_data,
+    stall_x,
+ 
+
+  
+
+    jtag_read_data,
+    jtag_access_complete,
+ 
+
+  
+
+    exception_q_w,
+ 
+
+    
+  
+
+    jtx_csr_read_data,
+    jrx_csr_read_data,
+ 
+
+  
+
+    jtag_csr_write_enable,
+    jtag_csr_write_data,
+    jtag_csr,
+    jtag_read_enable,
+    jtag_write_enable,
+    jtag_write_data,
+    jtag_address,
+ 
+
+  
+
+    jtag_break,
+    jtag_reset,
+ 
+
+    jtag_reg_d,
+    jtag_reg_addr_d
+    );
+
+
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input jtag_clk;                                         
+input jtag_update;                                      
+input [ 7:0] jtag_reg_q;                      
+input [2:0] jtag_reg_addr_q;                            
+
+  
+
+input [ (5-1):0] csr;                              
+input csr_write_enable;                                 
+input [ (32-1):0] csr_write_data;                  
+input stall_x;                                          
+ 
+
+  
+
+input [ 7:0] jtag_read_data;                  
+input jtag_access_complete;                             
+ 
+
+  
+
+input exception_q_w;                                    
+ 
+
+
+
+
+
+       
+  
+
+output [ (32-1):0] jtx_csr_read_data;              
+wire   [ (32-1):0] jtx_csr_read_data;
+output [ (32-1):0] jrx_csr_read_data;              
+wire   [ (32-1):0] jrx_csr_read_data;
+ 
+
+  
+
+output jtag_csr_write_enable;                           
+reg    jtag_csr_write_enable;
+output [ (32-1):0] jtag_csr_write_data;            
+wire   [ (32-1):0] jtag_csr_write_data;
+output [ (5-1):0] jtag_csr;                        
+wire   [ (5-1):0] jtag_csr;
+output jtag_read_enable;                                
+reg    jtag_read_enable;
+output jtag_write_enable;                               
+reg    jtag_write_enable;
+output [ 7:0] jtag_write_data;                
+wire   [ 7:0] jtag_write_data;        
+output [ (32-1):0] jtag_address;                   
+wire   [ (32-1):0] jtag_address;
+ 
+
+  
+
+output jtag_break;                                      
+reg    jtag_break;
+output jtag_reset;                                      
+reg    jtag_reset;
+ 
+
+output [ 7:0] jtag_reg_d;
+reg    [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire   [2:0] jtag_reg_addr_d;
+             
+
+
+
+
+reg rx_update;                          
+reg rx_update_r;                        
+reg rx_update_r_r;                      
+reg rx_update_r_r_r;                    
+
+
+
+wire [ 7:0] rx_byte;   
+wire [2:0] rx_addr;
+
+  
+                 
+reg [ 7:0] uart_tx_byte;      
+reg uart_tx_valid;                      
+reg [ 7:0] uart_rx_byte;      
+reg uart_rx_valid;                      
+ 
+
+
+reg [ 3:0] command;             
+  
+
+reg [ 7:0] jtag_byte_0;       
+reg [ 7:0] jtag_byte_1;
+reg [ 7:0] jtag_byte_2;
+reg [ 7:0] jtag_byte_3;
+reg [ 7:0] jtag_byte_4;
+reg processing;                         
+ 
+
+
+reg [ 3:0] state;       
+
+
+
+
+
+  
+
+assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_csr = jtag_byte_4[ (5-1):0];
+assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_write_data = jtag_byte_4;
+ 
+
+                 
+
+  
+                 
+assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};         
+ 
+   
+
+
+  
+
+assign jtag_reg_addr_d[2] = processing;
+ 
+   
+
+
+
+  
+                 
+assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00};
+assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
+ 
+         
+                 
+
+
+
+
+assign rx_byte = jtag_reg_q;
+assign rx_addr = jtag_reg_addr_q;
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        rx_update <= 1'b0;
+        rx_update_r <= 1'b0;
+        rx_update_r_r <= 1'b0;
+        rx_update_r_r_r <= 1'b0;
+    end
+    else
+    begin
+        rx_update <= jtag_update;
+        rx_update_r <= rx_update;
+        rx_update_r_r <= rx_update_r;
+        rx_update_r_r_r <= rx_update_r_r;
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  4'h0;
+        command <= 4'b0000;
+        jtag_reg_d <= 8'h00;
+  
+
+        processing <=  1'b0;
+        jtag_csr_write_enable <=  1'b0;
+        jtag_read_enable <=  1'b0;
+        jtag_write_enable <=  1'b0;
+ 
+
+  
+
+        jtag_break <=  1'b0;
+        jtag_reset <=  1'b0;
+ 
+
+  
+                 
+        uart_tx_byte <= 8'h00;
+        uart_tx_valid <=  1'b0;
+        uart_rx_byte <= 8'h00;
+        uart_rx_valid <=  1'b0;
+ 
+
+    end
+    else
+    begin
+  
+                 
+        if ((csr_write_enable ==  1'b1) && (stall_x ==  1'b0))
+        begin
+            case (csr)
+             5'he:
+            begin
+                
+                uart_tx_byte <= csr_write_data[ 7:0];
+                uart_tx_valid <=  1'b1;
+            end
+             5'hf:
+            begin
+                
+                uart_rx_valid <=  1'b0;
+            end
+            endcase
+        end
+ 
+
+  
+
+        
+        if (exception_q_w ==  1'b1)
+        begin
+            jtag_break <=  1'b0;
+            jtag_reset <=  1'b0;
+        end
+ 
+
+        case (state)
+         4'h0:
+        begin
+            
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                command <= rx_byte[7:4];                
+                case (rx_addr)
+  
+
+                 3'b000:
+                begin
+                    case (rx_byte[7:4])
+  
+
+                     4'b0001:
+                        state <=  4'h1;
+                     4'b0011:
+                    begin
+                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+                        state <=  4'h6;
+                    end
+                     4'b0010:
+                        state <=  4'h1;
+                     4'b0100:
+                    begin
+                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+                        state <= 5;
+                    end
+                     4'b0101:
+                        state <=  4'h1;
+ 
+                    
+                     4'b0110:
+                    begin
+  
+     
+                        uart_rx_valid <=  1'b0;    
+                        uart_tx_valid <=  1'b0;         
+ 
+
+                        jtag_break <=  1'b1;
+                    end
+                     4'b0111:
+                    begin
+  
+     
+                        uart_rx_valid <=  1'b0;    
+                        uart_tx_valid <=  1'b0;         
+ 
+
+                        jtag_reset <=  1'b1;
+                    end
+                    endcase                               
+                end
+ 
+
+  
+                 
+                 3'b001:
+                begin
+                    uart_rx_byte <= rx_byte;
+                    uart_rx_valid <=  1'b1;
+                end                    
+                 3'b010:
+                begin
+                    jtag_reg_d <= uart_tx_byte;
+                    uart_tx_valid <=  1'b0;
+                end
+ 
+
+                default:
+                    ;
+                endcase                
+            end
+        end
+  
+
+         4'h1:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_0 <= rx_byte;
+                state <=  4'h2;
+            end
+        end
+         4'h2:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_1 <= rx_byte;
+                state <=  4'h3;
+            end
+        end
+         4'h3:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_2 <= rx_byte;
+                state <=  4'h4;
+            end
+        end
+         4'h4:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_3 <= rx_byte;
+                if (command ==  4'b0001)
+                    state <=  4'h6;
+                else 
+                    state <=  4'h5;
+            end
+        end
+         4'h5:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_4 <= rx_byte;
+                state <=  4'h6;
+            end
+        end
+         4'h6:
+        begin
+            case (command)
+             4'b0001,
+             4'b0011:
+            begin
+                jtag_read_enable <=  1'b1;
+                processing <=  1'b1;
+                state <=  4'h7;
+            end
+             4'b0010,
+             4'b0100:
+            begin
+                jtag_write_enable <=  1'b1;
+                processing <=  1'b1;
+                state <=  4'h7;
+            end
+             4'b0101:
+            begin
+                jtag_csr_write_enable <=  1'b1;
+                processing <=  1'b1;
+                state <=  4'h8;
+            end
+            endcase
+        end
+         4'h7:
+        begin
+            if (jtag_access_complete ==  1'b1)
+            begin          
+                jtag_read_enable <=  1'b0;
+                jtag_reg_d <= jtag_read_data;
+                jtag_write_enable <=  1'b0;  
+                processing <=  1'b0;
+                state <=  4'h0;
+            end
+        end    
+         4'h8:
+        begin
+            jtag_csr_write_enable <=  1'b0;
+            processing <=  1'b0;
+            state <=  4'h0;
+        end    
+ 
+
+        endcase
+    end
+end
+  
+endmodule
+
+ 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_interrupt_full_debug (
+    
+    clk_i, 
+    rst_i,
+    
+    interrupt,
+    
+    stall_x,
+  
+
+    non_debug_exception,
+    debug_exception,
+ 
+    
+
+
+    eret_q_x,
+  
+
+    bret_q_x,
+ 
+
+    csr,
+    csr_write_data,
+    csr_write_enable,
+    
+    interrupt_exception,
+    
+    csr_read_data
+    );
+
+
+
+
+
+parameter interrupts =  32;         
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [interrupts-1:0] interrupt;               
+
+input stall_x;                                  
+
+  
+
+input non_debug_exception;                      
+input debug_exception;                          
+ 
+                                 
+
+
+input eret_q_x;                                 
+  
+
+input bret_q_x;                                 
+ 
+
+
+input [ (5-1):0] csr;                      
+input [ (32-1):0] csr_write_data;          
+input csr_write_enable;                         
+
+
+
+
+
+output interrupt_exception;                     
+wire   interrupt_exception;
+
+output [ (32-1):0] csr_read_data;          
+reg    [ (32-1):0] csr_read_data;
+
+
+
+
+
+wire [interrupts-1:0] asserted;                 
+
+wire [interrupts-1:0] interrupt_n_exception;
+
+
+
+reg ie;                                         
+reg eie;                                        
+  
+
+reg bie;                                        
+ 
+
+reg [interrupts-1:0] ip;                        
+reg [interrupts-1:0] im;                        
+
+
+
+
+
+
+assign interrupt_n_exception = ip & im;
+
+
+assign interrupt_exception = (|interrupt_n_exception) & ie;
+
+
+assign asserted = ip | interrupt;
+       
+generate
+    if (interrupts > 1) 
+    begin
+
+always @(*)
+begin
+    case (csr)
+     5'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+
+                                    bie,
+ 
+                                                                         
+
+
+                                    eie, 
+                                    ie
+                                   };
+     5'h2:  csr_read_data = ip;
+     5'h1:  csr_read_data = im;
+    default:       csr_read_data = { 32{1'bx}};
+    endcase
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    case (csr)
+     5'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+
+                                    bie, 
+ 
+                                                                        
+
+
+                                    eie, 
+                                    ie
+                                   };
+     5'h2:  csr_read_data = ip;
+    default:       csr_read_data = { 32{1'bx}};
+      endcase
+end
+    end
+endgenerate
+    
+
+
+
+
+  
+
+   reg [ 10:0] eie_delay  = 0;
+
+   
+generate
+
+   
+    if (interrupts > 1)
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie                   <=  1'b0;
+        eie                  <=  1'b0;
+  
+
+        bie                  <=  1'b0;
+ 
+
+        im                   <= {interrupts{1'b0}};
+        ip                   <= {interrupts{1'b0}};
+       eie_delay             <= 0;
+       
+    end
+    else
+    begin
+        
+        ip                   <= asserted;
+  
+
+        if (non_debug_exception ==  1'b1)
+        begin
+            
+            eie              <= ie;
+            ie               <=  1'b0;
+        end
+        else if (debug_exception ==  1'b1)
+        begin
+            
+            bie              <= ie;
+            ie               <=  1'b0;
+        end
+ 
+           
+        
+            
+                           
+                            
+        
+
+
+        else if (stall_x ==  1'b0)
+        begin
+
+           if(eie_delay[0])
+             ie              <= eie;
+           
+           eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+            if (eret_q_x ==  1'b1) begin
+                
+               eie_delay[ 10] <=  1'b1;
+               eie_delay[ 10-1:0] <= 0;
+            end
+           
+                      
+           
+  
+
+            else if (bret_q_x ==  1'b1)
+                
+                ie      <= bie;
+ 
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  5'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+
+                    bie <= csr_write_data[2];
+ 
+
+                end
+                if (csr ==  5'h1)
+                    im  <= csr_write_data[interrupts-1:0];
+                if (csr ==  5'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+else
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie              <=  1'b0;
+        eie             <=  1'b0;
+  
+
+        bie             <=  1'b0;
+ 
+
+        ip              <= {interrupts{1'b0}};
+       eie_delay        <= 0;
+    end
+    else
+    begin
+        
+        ip              <= asserted;
+  
+
+        if (non_debug_exception ==  1'b1)
+        begin
+            
+            eie         <= ie;
+            ie          <=  1'b0;
+        end
+        else if (debug_exception ==  1'b1)
+        begin
+            
+            bie         <= ie;
+            ie          <=  1'b0;
+        end
+ 
+           
+        
+            
+                      
+                       
+        
+
+
+        else if (stall_x ==  1'b0)
+          begin
+
+             if(eie_delay[0])
+               ie              <= eie;
+           
+             eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+             if (eret_q_x ==  1'b1) begin
+                
+                eie_delay[ 10] <=  1'b1;
+                eie_delay[ 10-1:0] <= 0;
+             end
+           
+  
+
+            else if (bret_q_x ==  1'b1)
+                
+                ie      <= bie;
+ 
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  5'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+
+                    bie <= csr_write_data[2];
+ 
+
+                end
+                if (csr ==  5'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+	 
+	 
+	 
+	 
+	
+
+ 
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+  
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+
+
+  
+
+  
+
+ 
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+                    
+
+
+  
+
+  
+
+ 
+  
+                    
+
+
+ 
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+ 
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+ 
+
+ 
+
+
+
+  
+
+  
+
+  
+ 
+ 
+
+ 
+
+
+ 
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+  
+ 
+
+
+
+
+  
+
+  
+
+ 
+
+  
+ 
+
+
+
+
+  
+
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+                   
+                     
+
+
+  
+                   
+                     
+
+
+  
+
+  
+
+ 
+
+ 
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+                      
+                    
+
+
+  
+
+  
+
+  
+
+  
+                     
+                     
+
+
+  
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+
+ 
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+ 
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+ 
+
+
+
+
+
+
+
+
+module lm32_top_medium (
+    
+    clk_i,
+    rst_i,
+    
+
+    interrupt,
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+    );
+
+parameter eba_reset = 32'h00000000;
+parameter sdb_address = 32'h00000000;
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+
+input [ (32-1):0] interrupt;          
+
+
+  
+               
+                             
+
+    
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+  
+
+
+
+ 
+  
+
+  
+  
+ 
+  
+  
+ 
+ 
+
+
+
+
+  
+
+                     
+                             
+                            
+                   
+                                 
+ 
+                                 
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+   
+
+lm32_cpu_medium 
+	#(
+		.eba_reset(eba_reset),
+    .sdb_address(sdb_address)
+	) cpu (
+    
+    .clk_i                 (clk_i),
+  
+                   
+
+
+    .rst_i                 (rst_i),
+    
+  
+
+    .interrupt             (interrupt),
+ 
+
+    
+  
+               
+             
+
+     
+  
+    
+                  
+               
+                
+           
+
+
+  
+
+     
+    .I_DAT_I               (I_DAT_I),
+    .I_ACK_I               (I_ACK_I),
+    .I_ERR_I               (I_ERR_I),
+    .I_RTY_I               (I_RTY_I),
+ 
+
+    
+    .D_DAT_I               (D_DAT_I),
+    .D_ACK_I               (D_ACK_I),
+    .D_ERR_I               (D_ERR_I),
+    .D_RTY_I               (D_RTY_I),
+    
+  
+                  
+            
+           
+                 
+                
+ 
+                
+
+
+
+  
+                
+           
+
+
+      
+                
+               
+            
+            
+
+    
+  
+
+    
+    .I_DAT_O               (I_DAT_O),
+    .I_ADR_O               (I_ADR_O),
+    .I_CYC_O               (I_CYC_O),
+    .I_SEL_O               (I_SEL_O),
+    .I_STB_O               (I_STB_O),
+    .I_WE_O                (I_WE_O),
+    .I_CTI_O               (I_CTI_O),
+    .I_LOCK_O              (I_LOCK_O),
+    .I_BTE_O               (I_BTE_O),
+     
+
+    
+    .D_DAT_O               (D_DAT_O),
+    .D_ADR_O               (D_ADR_O),
+    .D_CYC_O               (D_CYC_O),
+    .D_SEL_O               (D_SEL_O),
+    .D_STB_O               (D_STB_O),
+    .D_WE_O                (D_WE_O),
+    .D_CTI_O               (D_CTI_O),
+    .D_LOCK_O              (D_LOCK_O),
+    .D_BTE_O               (D_BTE_O)
+    );
+   
+  		   
+
+  
+    
+                     
+                
+    
+                
+                     
+                
+                      
+                     
+    
+
+        
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+           
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_mc_arithmetic_medium (
+    
+    clk_i,
+    rst_i,
+    stall_d,
+    kill_x,
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+    
+
+
+    operand_0_d,
+    operand_1_d,
+    
+    result_x,
+  
+    
+
+
+    stall_request_x
+    );
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+input stall_d;                                  
+input kill_x;                                   
+  
+                                  
+                                 
+
+
+  
+                                
+
+
+  
+                              
+                             
+                             
+
+
+input [ (32-1):0] operand_0_d;
+input [ (32-1):0] operand_1_d;
+
+
+
+
+
+output [ (32-1):0] result_x;               
+reg    [ (32-1):0] result_x;
+  
+                         
+    
+
+
+output stall_request_x;                         
+wire   stall_request_x;
+
+
+
+
+
+reg [ (32-1):0] p;                         
+reg [ (32-1):0] a;
+reg [ (32-1):0] b;
+  
+  
+
+
+
+reg [ 2:0] state;                 
+reg [5:0] cycles;                               
+
+  
+                               
+                                 
+
+
+
+
+
+
+
+
+assign stall_request_x = state !=  3'b000;
+
+  
+
+      
+
+
+
+  
+
+       
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        cycles <= {6{1'b0}};
+        p <= { 32{1'b0}};
+        a <= { 32{1'b0}};
+        b <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+        result_x <= { 32{1'b0}};
+        state <=  3'b000;
+    end
+    else
+    begin
+  
+          
+
+
+        case (state)
+         3'b000:
+        begin
+            if (stall_d ==  1'b0)                 
+            begin          
+                cycles <=  32;
+                p <= 32'b0;
+                a <= operand_0_d;
+                b <= operand_1_d;                    
+  
+                   
+                      
+                   
+                      
+
+                    
+  
+                   
+                      
+
+
+  
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+
+
+            end            
+        end
+  
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+
+        
+  
+        
+        
+               
+                    
+               
+               
+              
+                   
+                  
+                
+        
+
+     
+  
+        
+               
+               
+              
+                   
+                  
+                
+        
+        
+               
+               
+              
+                   
+                  
+                
+        
+
+   
+        endcase
+    end
+end 
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_cpu_medium (
+    
+    clk_i,
+  
+    
+
+
+    rst_i,
+  
+    
+
+
+  
+   
+   
+   
+   
+   
+   
+
+
+
+    
+  
+
+    interrupt,
+ 
+
+    
+  
+    
+    
+
+     
+  
+    
+    
+     
+    
+    
+
+
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+  
+    
+    
+    
+    
+    
+ 
+    
+
+
+
+  
+    
+    
+
+
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+ 
+  
+    
+    
+    
+    
+    
+    
+    
+    
+           
+
+
+		 
+		 
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+
+		 
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                           
+  
+                            
+
+
+parameter sdb_address =   32'h00000000;
+
+  
+        
+                          
+      
+          
+                        
+
+
+parameter icache_associativity = 1;    
+parameter icache_sets = 512;                      
+parameter icache_bytes_per_line = 16;  
+parameter icache_base_address = 0;      
+parameter icache_limit = 0;                    
+ 
+
+
+  
+        
+                          
+      
+          
+                        
+
+
+parameter dcache_associativity = 1;    
+parameter dcache_sets = 512;                      
+parameter dcache_bytes_per_line = 16;  
+parameter dcache_base_address = 0;      
+parameter dcache_limit = 0;                    
+ 
+
+
+  
+                          
+
+
+parameter watchpoints = 0;
+ 
+
+  
+                          
+
+
+parameter breakpoints = 0;
+ 
+
+
+  
+
+parameter interrupts =  32;                         
+ 
+   
+
+
+
+
+
+
+
+input clk_i;                                    
+  
+                                   
+
+    
+input rst_i;                                    
+
+  
+
+input [ (32-1):0] interrupt;          
+ 
+
+
+  
+               
+                             
+
+    
+
+   
+                                  
+                               
+                
+  
+
+
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+    
+     
+
+
+   
+   
+  
+                   
+     
+                           
+    
+                          
+    
+                 
+     
+                               
+    
+ 
+                               
+    
+
+
+
+
+  
+  
+    
+  
+    
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+
+  
+      
+     
+       
+      
+             
+
+
+   
+
+
+
+
+
+
+  
+                                     
+
+
+reg valid_f;                                    
+reg valid_d;                                    
+reg valid_x;                                    
+reg valid_m;                                    
+reg valid_w;                                    
+   
+wire q_x;
+wire [ (32-1):0] immediate_d;              
+wire load_d;                                    
+reg load_x;                                     
+reg load_m;
+wire load_q_x;
+wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
+wire store_d;                                   
+reg store_x;
+reg store_m;
+wire [ 1:0] size_d;                   
+reg [ 1:0] size_x;
+wire branch_d;                                  
+wire branch_predict_d;                          
+wire branch_predict_taken_d;                    
+wire [ ((32-2)+2-1):2] branch_predict_address_d;   
+wire [ ((32-2)+2-1):2] branch_target_d;
+wire bi_unconditional;
+wire bi_conditional;
+reg branch_x;                                   
+reg branch_predict_x;
+reg branch_predict_taken_x;
+reg branch_m;
+reg branch_predict_m;
+reg branch_predict_taken_m;
+wire branch_mispredict_taken_m;                 
+wire branch_flushX_m;                           
+wire branch_reg_d;                              
+wire [ ((32-2)+2-1):2] branch_offset_d;            
+reg [ ((32-2)+2-1):2] branch_target_x;             
+reg [ ((32-2)+2-1):2] branch_target_m;
+wire [ 0:0] d_result_sel_0_d; 
+wire [ 1:0] d_result_sel_1_d; 
+
+wire x_result_sel_csr_d;                        
+reg x_result_sel_csr_x;
+  
+ 
+                    
+ 
+
+
+      
+                       
+ 
+
+
+  
+
+wire x_result_sel_sext_d;                       
+reg x_result_sel_sext_x;
+ 
+
+wire x_result_sel_logic_d;                      
+  
+                        
+ 
+
+
+wire x_result_sel_add_d;                        
+reg x_result_sel_add_x;
+wire m_result_sel_compare_d;                    
+reg m_result_sel_compare_x;
+reg m_result_sel_compare_m;
+  
+
+wire m_result_sel_shift_d;                      
+reg m_result_sel_shift_x;
+reg m_result_sel_shift_m;
+ 
+
+wire w_result_sel_load_d;                       
+reg w_result_sel_load_x;
+reg w_result_sel_load_m;
+reg w_result_sel_load_w;
+  
+
+wire w_result_sel_mul_d;                        
+reg w_result_sel_mul_x;
+reg w_result_sel_mul_m;
+reg w_result_sel_mul_w;
+ 
+
+wire x_bypass_enable_d;                         
+reg x_bypass_enable_x;                          
+wire m_bypass_enable_d;                         
+reg m_bypass_enable_x;                          
+reg m_bypass_enable_m;
+wire sign_extend_d;                             
+reg sign_extend_x;
+wire write_enable_d;                            
+reg write_enable_x;
+wire write_enable_q_x;
+reg write_enable_m;
+wire write_enable_q_m;
+reg write_enable_w;
+wire write_enable_q_w;
+wire read_enable_0_d;                           
+wire [ (5-1):0] read_idx_0_d;          
+wire read_enable_1_d;                           
+wire [ (5-1):0] read_idx_1_d;          
+wire [ (5-1):0] write_idx_d;           
+reg [ (5-1):0] write_idx_x;            
+reg [ (5-1):0] write_idx_m;
+reg [ (5-1):0] write_idx_w;
+wire [ (4 -1):0] csr_d;                     
+reg  [ (4 -1):0] csr_x;                  
+wire [ (3-1):0] condition_d;         
+reg [ (3-1):0] condition_x;          
+  
+                                    
+                                     
+
+
+wire scall_d;                                   
+reg scall_x;    
+wire eret_d;                                    
+reg eret_x;
+wire eret_q_x;
+  
+ 
+ 
+
+
+  
+                                     
+ 
+ 
+ 
+ 
+ 
+
+
+
+wire csr_write_enable_d;                        
+reg csr_write_enable_x;
+wire csr_write_enable_q_x;
+  
+       
+
+
+
+  
+                                
+ 
+ 
+  
+
+
+
+reg [ (32-1):0] d_result_0;                
+reg [ (32-1):0] d_result_1;                
+reg [ (32-1):0] x_result;                  
+reg [ (32-1):0] m_result;                  
+reg [ (32-1):0] w_result;                  
+
+reg [ (32-1):0] operand_0_x;               
+reg [ (32-1):0] operand_1_x;               
+reg [ (32-1):0] store_operand_x;           
+reg [ (32-1):0] operand_m;                 
+reg [ (32-1):0] operand_w;                 
+
+
+  
+
+reg [ (32-1):0] reg_data_live_0;          
+reg [ (32-1):0] reg_data_live_1;  
+reg use_buf;                                    
+reg [ (32-1):0] reg_data_buf_0;
+reg [ (32-1):0] reg_data_buf_1;
+ 
+
+  
+
+ 
+     
+
+
+wire [ (32-1):0] reg_data_0;               
+wire [ (32-1):0] reg_data_1;               
+reg [ (32-1):0] bypass_data_0;             
+reg [ (32-1):0] bypass_data_1;             
+wire reg_write_enable_q_w;
+
+reg interlock;                                  
+
+wire stall_a;                                   
+wire stall_f;                                   
+wire stall_d;                                   
+wire stall_x;                                   
+wire stall_m;                                   
+
+
+wire adder_op_d;                                
+reg adder_op_x;                                 
+reg adder_op_x_n;                               
+wire [ (32-1):0] adder_result_x;           
+wire adder_overflow_x;                          
+wire adder_carry_n_x;                           
+
+
+wire [ 3:0] logic_op_d;           
+reg [ 3:0] logic_op_x;            
+wire [ (32-1):0] logic_result_x;           
+
+  
+
+
+wire [ (32-1):0] sextb_result_x;           
+wire [ (32-1):0] sexth_result_x;           
+wire [ (32-1):0] sext_result_x;            
+ 
+
+
+
+  
+
+  
+                                   
+                                     
+
+
+wire direction_d;                               
+reg direction_x;                                        
+wire [ (32-1):0] shifter_result_m;         
+ 
+
+  
+                               
+ 
+                              
+ 
+
+
+  
+           
+
+
+
+
+  
+
+wire [ (32-1):0] multiplier_result_w;      
+ 
+
+  
+                                 
+ 
+
+
+
+
+  
+                                   
+ 
+ 
+ 
+                           
+
+
+
+
+  
+                         
+  
+
+
+
+
+  
+
+wire [ (32-1):0] interrupt_csr_read_data_x;
+ 
+
+wire [ (32-1):0] cfg;                      
+wire [ (32-1):0] cfg2;                     
+  
+                          
+
+
+reg [ (32-1):0] csr_read_data_x;           
+
+
+wire [ ((32-2)+2-1):2] pc_f;                       
+wire [ ((32-2)+2-1):2] pc_d;                       
+wire [ ((32-2)+2-1):2] pc_x;                       
+wire [ ((32-2)+2-1):2] pc_m;                       
+wire [ ((32-2)+2-1):2] pc_w;                       
+  
+                          
+
+
+  
+
+wire [ (32-1):0] instruction_f;     
+ 
+
+
+
+wire [ (32-1):0] instruction_d;     
+  
+                                     
+                       
+                     
+                      
+                           
+
+
+
+
+  
+                                   
+                                     
+                       
+                     
+                      
+                           
+
+
+wire [ (32-1):0] load_data_w;              
+wire stall_wb_load;                             
+
+
+  
+ 
+          
+          
+
+ 
+                      
+        
+                    
+                           
+  
+ 
+  
+  
+ 
+
+ 
+                                 
+
+
+
+
+
+wire raw_x_0;                                   
+wire raw_x_1;                                   
+wire raw_m_0;                                   
+wire raw_m_1;                                   
+wire raw_w_0;                                   
+wire raw_w_1;                                   
+
+
+wire cmp_zero;                                  
+wire cmp_negative;                              
+wire cmp_overflow;                              
+wire cmp_carry_n;                               
+reg condition_met_x;                            
+reg condition_met_m;
+      
+                             
+
+
+wire branch_taken_m;                            
+
+wire kill_f;                                    
+wire kill_d;                                    
+wire kill_x;                                    
+wire kill_m;                                    
+wire kill_w;                                    
+
+reg [ (32-2)+2-1:8] eba;                 
+  
+                  
+
+
+reg [ (3-1):0] eid_x;                      
+  
+                        
+                        
+
+
+
+  
+ 
+                                      
+
+                                      
+ 
+ 
+                                
+                                 
+                          
+ 
+ 
+ 
+                      
+ 
+ 
+ 
+
+
+wire exception_x;                               
+reg exception_m;
+reg exception_w;
+wire exception_q_w;
+ 
+
+
+  
+  
+                            
+
+ 
+                            
+
+
+
+  
+
+wire interrupt_exception;                       
+ 
+
+  
+                       
+                       
+
+
+  
+     
+   
+            
+                   
+
+
+  
+                   
+
+
+wire system_call_exception;                     
+
+  
+                         
+
+
+
+   
+    
+
+
+     
+  
+                          
+   
+            
+   
+                          
+   
+
+    	      
+    	      
+    	      
+    	      
+    	      
+    	      
+   
+   
+
+
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+lm32_instruction_unit_medium #(
+    .eba_reset              (eba_reset),
+    .associativity          (icache_associativity),
+    .sets                   (icache_sets),
+    .bytes_per_line         (icache_bytes_per_line),
+    .base_address           (icache_base_address),
+    .limit                  (icache_limit)
+  ) instruction_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .stall_d                (stall_d),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .valid_f                (valid_f),
+    .valid_d                (valid_d),
+    .kill_f                 (kill_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .branch_predict_address_d (branch_predict_address_d),
+      
+             
+            
+
+
+    .exception_m            (exception_m),
+    .branch_taken_m         (branch_taken_m),
+    .branch_mispredict_taken_m (branch_mispredict_taken_m),
+    .branch_target_m        (branch_target_m),
+  
+                     
+
+
+  
+     
+      
+           
+
+        
+  
+
+    
+    .i_dat_i                (I_DAT_I),
+    .i_ack_i                (I_ACK_I),
+    .i_err_i                (I_ERR_I),
+    .i_rty_i                (I_RTY_I),
+ 
+
+  
+           
+          
+            
+               
+
+
+    
+    
+    .pc_f                   (pc_f),
+    .pc_d                   (pc_d),
+    .pc_x                   (pc_x),
+    .pc_m                   (pc_m),
+    .pc_w                   (pc_w),
+  
+       
+     
+      
+           
+
+
+  
+
+    
+    .i_dat_o                (I_DAT_O),
+    .i_adr_o                (I_ADR_O),
+    .i_cyc_o                (I_CYC_O),
+    .i_sel_o                (I_SEL_O),
+    .i_stb_o                (I_STB_O),
+    .i_we_o                 (I_WE_O),
+    .i_cti_o                (I_CTI_O),
+    .i_lock_o               (I_LOCK_O),
+    .i_bte_o                (I_BTE_O),
+ 
+ 
+
+  
+    
+    
+    
+
+
+		      	      
+  
+             
+       
+
+
+  
+                
+
+
+  
+
+    .instruction_f          (instruction_f),
+ 
+
+
+		      
+    .instruction_d          (instruction_d)
+
+
+		      
+    );
+
+
+lm32_decoder_medium decoder (
+    
+    .instruction            (instruction_d),
+    
+    .d_result_sel_0         (d_result_sel_0_d),
+    .d_result_sel_1         (d_result_sel_1_d),
+    .x_result_sel_csr       (x_result_sel_csr_d),
+  
+      
+
+
+      
+         
+
+
+  
+
+    .x_result_sel_sext      (x_result_sel_sext_d),
+ 
+    
+    .x_result_sel_logic     (x_result_sel_logic_d),
+  
+          
+
+
+    .x_result_sel_add       (x_result_sel_add_d),
+    .m_result_sel_compare   (m_result_sel_compare_d),
+  
+
+    .m_result_sel_shift     (m_result_sel_shift_d),  
+ 
+    
+    .w_result_sel_load      (w_result_sel_load_d),
+  
+
+    .w_result_sel_mul       (w_result_sel_mul_d),
+ 
+
+    .x_bypass_enable        (x_bypass_enable_d),
+    .m_bypass_enable        (m_bypass_enable_d),
+    .read_enable_0          (read_enable_0_d),
+    .read_idx_0             (read_idx_0_d),
+    .read_enable_1          (read_enable_1_d),
+    .read_idx_1             (read_idx_1_d),
+    .write_enable           (write_enable_d),
+    .write_idx              (write_idx_d),
+    .immediate              (immediate_d),
+    .branch_offset          (branch_offset_d),
+    .load                   (load_d),
+    .store                  (store_d),
+    .size                   (size_d),
+    .sign_extend            (sign_extend_d),
+    .adder_op               (adder_op_d),
+    .logic_op               (logic_op_d),
+  
+
+    .direction              (direction_d),
+ 
+
+  
+                 
+                
+
+
+  
+                   
+
+
+  
+                     
+                    
+
+
+    .branch                 (branch_d),
+    .bi_unconditional       (bi_unconditional),
+    .bi_conditional         (bi_conditional),
+    .branch_reg             (branch_reg_d),
+    .condition              (condition_d),
+  
+               
+
+
+    .scall                  (scall_d),
+    .eret                   (eret_d),
+  
+                       
+
+
+  
+                
+
+
+    .csr_write_enable       (csr_write_enable_d)
+    ); 
+
+
+lm32_load_store_unit_medium #(
+    .associativity          (dcache_associativity),
+    .sets                   (dcache_sets),
+    .bytes_per_line         (dcache_bytes_per_line),
+    .base_address           (dcache_base_address),
+    .limit                  (dcache_limit)
+  ) load_store_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .kill_x                 (kill_x),
+    .kill_m                 (kill_m),
+    .exception_m            (exception_m),
+    .store_operand_x        (store_operand_x),
+    .load_store_address_x   (adder_result_x),
+    .load_store_address_m   (operand_m),
+    .load_store_address_w   (operand_w[1:0]),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_q_x               (load_q_x),
+    .store_q_x              (store_q_x),
+    .load_q_m               (load_q_m),
+    .store_q_m              (store_q_m),
+    .sign_extend_x          (sign_extend_x),
+    .size_x                 (size_x),
+  
+                     
+
+
+
+  
+    
+    
+    
+    
+    
+    
+    
+
+
+		     
+    
+    .d_dat_i                (D_DAT_I),
+    .d_ack_i                (D_ACK_I),
+    .d_err_i                (D_ERR_I),
+    .d_rty_i                (D_RTY_I),
+    
+    
+  
+      
+     
+       
+           
+
+    
+    .load_data_w            (load_data_w),
+    .stall_wb_load          (stall_wb_load),
+    
+    .d_dat_o                (D_DAT_O),
+    .d_adr_o                (D_ADR_O),
+    .d_cyc_o                (D_CYC_O),
+    .d_sel_o                (D_SEL_O),
+    .d_stb_o                (D_STB_O),
+    .d_we_o                 (D_WE_O),
+    .d_cti_o                (D_CTI_O),
+    .d_lock_o               (D_LOCK_O),
+    .d_bte_o                (D_BTE_O)
+    );      
+       
+
+lm32_adder adder (
+    
+    .adder_op_x             (adder_op_x),
+    .adder_op_x_n           (adder_op_x_n),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .adder_result_x         (adder_result_x),
+    .adder_carry_n_x        (adder_carry_n_x),
+    .adder_overflow_x       (adder_overflow_x)
+    );
+
+
+lm32_logic_op logic_op (
+    
+    .logic_op_x             (logic_op_x),
+    .operand_0_x            (operand_0_x),
+
+    .operand_1_x            (operand_1_x),
+    
+    .logic_result_x         (logic_result_x)
+    );
+              
+  
+
+
+lm32_shifter shifter (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .direction_x            (direction_x),
+    .sign_extend_x          (sign_extend_x),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .shifter_result_m       (shifter_result_m)
+    );
+ 
+
+
+  
+
+
+lm32_multiplier multiplier (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .operand_0              (d_result_0),
+    .operand_1              (d_result_1),
+    
+    .result                 (multiplier_result_w)    
+    );
+ 
+
+
+  
+
+  
+    
+                      
+                      
+                    
+                     
+                   
+                   
+                  
+
+         
+                 
+
+ 
+               
+              
+              
+    
+                
+                
+    
+                   
+                   
+           
+
+            
+    
+
+
+              
+  
+
+
+lm32_interrupt_medium interrupt_unit (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    
+    .interrupt              (interrupt),
+    
+    .stall_x                (stall_x),
+  
+         
+            
+
+
+    .exception              (exception_q_w), 
+ 
+
+    .eret_q_x               (eret_q_x),
+  
+                   
+
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    
+    .interrupt_exception    (interrupt_exception),
+    
+    .csr_read_data          (interrupt_csr_read_data_x)
+    );
+ 
+
+
+  
+      
+      
+        
+   
+
+
+
+
+  
+
+  
+    
+                      
+                      
+    
+                   
+                
+                 
+            
+    
+ 
+                        
+             
+           
+                    
+
+ 
+             
+       
+
+ 
+                
+    
+    
+    
+ 
+          
+          
+
+ 
+      
+        
+                   
+           
+          
+            
+               
+
+ 
+                 
+                 
+
+    
+                 
+            
+    
+
+
+
+  
+
+ 
+                
+                
+    
+    
+                       
+                      
+                       
+                     
+                    
+       
+         
+             
+                      
+  
+	       
+      
+        
+                   
+	      
+	       
+      
+        
+                   
+	      
+
+ 
+                   
+                   
+                    
+                
+                        
+ 
+      
+
+
+    
+ 
+                      
+
+                      
+                   
+                   
+    
+
+
+
+
+
+  
+
+   
+           
+            
+          
+            
+
+
+             
+              
+    
+
+   wire [31:0] regfile_data_0, regfile_data_1;
+   reg [31:0]  w_result_d;
+   reg 	       regfile_raw_0, regfile_raw_0_nxt;
+   reg 	       regfile_raw_1, regfile_raw_1_nxt;
+   
+   
+             
+          
+
+   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
+     begin
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[25:21]))
+	  regfile_raw_0_nxt = 1'b1;
+	else
+	  regfile_raw_0_nxt = 1'b0;
+	
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[20:16]))
+	  regfile_raw_1_nxt = 1'b1;
+	else
+	  regfile_raw_1_nxt = 1'b0;
+     end
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_0 or w_result_d or regfile_data_0)
+     if (regfile_raw_0)
+       reg_data_live_0 = w_result_d;
+     else
+       reg_data_live_0 = regfile_data_0;
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_1 or w_result_d or regfile_data_1)
+     if (regfile_raw_1)
+       reg_data_live_1 = w_result_d;
+     else
+       reg_data_live_1 = regfile_data_1;
+   
+   
+     
+
+   always @(posedge clk_i  )
+     if (rst_i ==  1'b1)
+       begin
+	  regfile_raw_0 <= 1'b0;
+	  regfile_raw_1 <= 1'b0;
+	  w_result_d <= 32'b0;
+       end
+     else
+       begin
+	  regfile_raw_0 <= regfile_raw_0_nxt;
+	  regfile_raw_1 <= regfile_raw_1_nxt;
+	  w_result_d <= w_result;
+       end
+   
+   
+      
+
+   
+   lm32_dp_ram
+     #(
+       
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_0
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[25:21]),
+      
+      .rdata_o	(regfile_data_0)
+      );
+
+   lm32_dp_ram
+     #(
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_1
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[20:16]),
+      
+      .rdata_o	(regfile_data_1)
+      );
+ 
+
+
+  
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+   
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+
+
+
+
+
+
+
+
+  
+
+
+assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
+assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
+ 
+
+  
+
+ 
+
+   
+   
+
+
+
+
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w ==  1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w ==  1'b1);
+
+
+always @(*)
+begin
+    if (   (   (x_bypass_enable_x ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_x_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_x_1 ==  1'b1))
+               )
+           )
+        || (   (m_bypass_enable_m ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_m_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_m_1 ==  1'b1))
+               )
+           )
+       )
+        interlock =  1'b1;
+    else
+        interlock =  1'b0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_0 ==  1'b1)        
+        bypass_data_0 = x_result;
+    else if (raw_m_0 ==  1'b1)
+        bypass_data_0 = m_result;
+    else if (raw_w_0 ==  1'b1)
+        bypass_data_0 = w_result;
+    else
+        bypass_data_0 = reg_data_0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_1 ==  1'b1)
+        bypass_data_1 = x_result;
+    else if (raw_m_1 ==  1'b1)
+        bypass_data_1 = m_result;
+    else if (raw_w_1 ==  1'b1)
+        bypass_data_1 = w_result;
+    else
+        bypass_data_1 = reg_data_1;
+end
+
+   
+          
+       
+       
+     
+
+   assign branch_predict_d = bi_unconditional | bi_conditional;
+   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
+   
+   
+   assign branch_target_d = pc_d + branch_offset_d;
+
+   
+   
+   
+   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
+
+
+always @(*)
+begin
+    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
+    case (d_result_sel_1_d)
+     2'b00:      d_result_1 = { 32{1'b0}};
+     2'b01:     d_result_1 = bypass_data_1;
+     2'b10: d_result_1 = immediate_d;
+    default:                        d_result_1 = { 32{1'bx}};
+    endcase
+end
+
+      
+
+   
+   
+
+
+
+  
+
+
+assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
+assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
+assign sext_result_x = size_x ==  2'b00 ? sextb_result_x : sexth_result_x;
+ 
+
+
+  
+
+      
+
+
+
+
+assign cmp_zero = operand_0_x == operand_1_x;
+assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_overflow = adder_overflow_x;
+assign cmp_carry_n = adder_carry_n_x;
+always @(*)
+begin
+    case (condition_x)
+     3'b000:   condition_met_x =  1'b1;
+     3'b110:   condition_met_x =  1'b1;
+     3'b001:    condition_met_x = cmp_zero;
+     3'b111:   condition_met_x = !cmp_zero;
+     3'b010:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+     3'b101:   condition_met_x = cmp_carry_n && !cmp_zero;
+     3'b011:   condition_met_x = cmp_negative == cmp_overflow;
+     3'b100:  condition_met_x = cmp_carry_n;
+    default:              condition_met_x = 1'bx;
+    endcase 
+end
+
+
+always @(*)
+begin
+    x_result =   x_result_sel_add_x ? adder_result_x 
+               : x_result_sel_csr_x ? csr_read_data_x
+  
+
+               : x_result_sel_sext_x ? sext_result_x
+ 
+
+  
+                  
+
+
+  
+                  
+
+
+  
+                  
+
+
+               : logic_result_x;
+end
+
+
+always @(*)
+begin
+    m_result =   m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
+  
+
+               : m_result_sel_shift_m ? shifter_result_m
+ 
+
+               : operand_m; 
+end
+
+
+always @(*)
+begin
+    w_result =    w_result_sel_load_w ? load_data_w
+  
+
+                : w_result_sel_mul_w ? multiplier_result_w
+ 
+
+                : operand_w;
+end
+
+      
+
+          
+                                
+                                     
+                                 
+                                 
+                              
+
+
+
+
+assign branch_taken_m =      (stall_m ==  1'b0) 
+                          && (   (   (branch_m ==  1'b1) 
+                                  && (valid_m ==  1'b1)
+                                  && (   (   (condition_met_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b0)
+					 )
+				      || (   (condition_met_m ==  1'b0)
+					  && (branch_predict_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b1)
+					 )
+				     )
+                                 ) 
+                              || (exception_m ==  1'b1)
+                             );
+
+
+assign branch_mispredict_taken_m =    (condition_met_m ==  1'b0)
+                                   && (branch_predict_m ==  1'b1)
+	   			   && (branch_predict_taken_m ==  1'b1);
+   
+
+assign branch_flushX_m =    (stall_m ==  1'b0)
+                         && (   (   (branch_m ==  1'b1) 
+                                 && (valid_m ==  1'b1)
+			         && (   (condition_met_m ==  1'b1)
+				     || (   (condition_met_m ==  1'b0)
+					 && (branch_predict_m ==  1'b1)
+					 && (branch_predict_taken_m ==  1'b1)
+					)
+				    )
+			        )
+			     || (exception_m ==  1'b1)
+			    );
+
+
+assign kill_f =    (   (valid_d ==  1'b1)
+                    && (branch_predict_taken_d ==  1'b1)
+		   )
+                || (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+                    
+
+
+                  
+                   
+
+
+                ;
+assign kill_d =    (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+                        
+
+                
+                  
+                   
+
+
+                ;
+assign kill_x =    (branch_flushX_m ==  1'b1) 
+                  
+                   
+
+
+                ;
+assign kill_m =     1'b0
+                  
+                   
+
+
+                ;                
+assign kill_w =     1'b0
+                  
+                   
+
+                
+                ;
+
+
+
+  
+              
+				         
+				     
+				     
+				 
+ 
+                                 
+
+                              
+
+
+
+  
+     
+
+
+
+  
+        
+                                             
+                                         
+     
+
+
+
+  
+     
+
+
+
+assign system_call_exception = (   (scall_x ==  1'b1)
+  
+                                   
+
+
+			       );
+
+  
+      
+                            
+                         
+
+     
+ 
+                               
+
+ 
+                               
+                               
+
+ 
+                               
+
+ 
+                                  
+ 
+                                   
+                            
+ 
+ 				   
+				   
+
+                               
+
+                            
+
+         
+
+
+assign exception_x =           (system_call_exception ==  1'b1)
+  
+                               
+                               
+
+
+  
+                               
+
+
+  
+
+                            || (   (interrupt_exception ==  1'b1)
+  
+                                   
+
+                            
+  
+ 				   
+				   
+
+
+                               )
+ 
+
+                            ;
+ 
+
+
+  
+ 
+
+ 
+  
+      
+   
+      
+
+
+
+
+always @(*)
+begin
+  
+ 
+       
+          
+    
+     
+ 
+            
+          
+    
+
+            
+          
+    
+
+
+  
+            
+          
+    
+            
+          
+    
+
+
+  
+            
+          
+     
+
+
+  
+            
+          
+    
+
+
+  
+
+         if (   (interrupt_exception ==  1'b1)
+  
+                
+
+                            
+            )
+        eid_x =  3'h6;
+    else
+ 
+
+        eid_x =  3'h7;
+end
+
+
+
+assign stall_a = (stall_f ==  1'b1);
+                
+assign stall_f = (stall_d ==  1'b1);
+                
+assign stall_d =   (stall_x ==  1'b1) 
+                || (   (interlock ==  1'b1)
+                    && (kill_d ==  1'b0)
+                   ) 
+		|| (   (   (eret_d ==  1'b1)
+			|| (scall_d ==  1'b1)
+  
+			   
+
+
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+  
+		         
+			   
+		       
+		          
+			   
+			   
+			   
+			   
+		       
+                       
+		   
+
+                   
+                || (   (csr_write_enable_d ==  1'b1)
+                    && (load_q_x ==  1'b1)
+                   )                      
+  
+                 
+                 
+                       
+		           
+			 
+			
+		    
+
+	
+                ;
+                
+assign stall_x =    (stall_m ==  1'b1)
+  
+                       
+                        
+                     
+
+
+
+	    
+                 ;
+
+assign stall_m =    (stall_wb_load ==  1'b1)
+  
+                    
+
+
+                 || (   (D_CYC_O ==  1'b1)
+                     && (   (store_m ==  1'b1)
+		         
+          
+          
+
+		  
+	 
+	
+
+          
+           
+          
+       
+
+  
+
+		         || ((store_x ==  1'b1) && (interrupt_exception ==  1'b1))
+ 
+
+                         || (load_m ==  1'b1)
+                         || (load_x ==  1'b1)
+                        ) 
+                    ) 
+ 
+                 
+  
+                         
+
+                                    
+  
+                         
+                             
+
+
+  
+
+                 || (I_CYC_O ==  1'b1)            
+ 
+
+ 
+                               
+  
+                                  
+                        
+                    
+
+
+  
+                  
+   
+
+                 ;      
+
+
+
+
+  
+         
+
+
+  
+         
+         
+
+
+  
+         
+
+
+  
+         
+         
+
+
+assign q_x = (valid_x ==  1'b1) && (kill_x ==  1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x ==  1'b1) && (q_x ==  1'b1);
+assign eret_q_x = (eret_x ==  1'b1) && (q_x ==  1'b1);
+  
+         
+
+
+assign load_q_x = (load_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+                  
+
+
+                  ;
+assign store_q_x = (store_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+                  
+
+
+                  ;
+  
+         
+
+                              
+assign q_m = (valid_m ==  1'b1) && (kill_m ==  1'b0) && (exception_m ==  1'b0);
+assign load_q_m = (load_m ==  1'b1) && (q_m ==  1'b1);
+assign store_q_m = (store_m ==  1'b1) && (q_m ==  1'b1);
+  
+         
+                 
+
+
+assign exception_q_w = ((exception_w ==  1'b1) && (valid_w ==  1'b1));        
+ 
+
+
+assign write_enable_q_x = (write_enable_x ==  1'b1) && (valid_x ==  1'b1) && (branch_flushX_m ==  1'b0);
+assign write_enable_q_m = (write_enable_m ==  1'b1) && (valid_m ==  1'b1);
+assign write_enable_q_w = (write_enable_w ==  1'b1) && (valid_w ==  1'b1);
+
+assign reg_write_enable_q_w = (write_enable_w ==  1'b1) && (kill_w ==  1'b0) && (valid_w ==  1'b1);
+
+
+assign cfg = {
+               6'h02,
+              watchpoints[3:0],
+              breakpoints[3:0],
+              interrupts[5:0],
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+ 
+               1'b1
+ 
+              
+
+
+              };
+
+assign cfg2 = {
+		     30'b0,
+  
+		     
+
+
+		      1'b0,
+ 
+
+  
+		     
+
+
+		      1'b0
+ 
+
+		     };
+   
+
+  
+         
+                    
+                    
+                    
+                    
+
+ 
+             
+                     
+		    
+
+		 
+
+ 
+  
+         
+                      
+
+ 
+               
+                       
+		      
+
+		   
+
+ 
+
+
+assign csr_d = read_idx_0_d[ (4 -1):0];
+
+
+always @(*)
+begin
+    case (csr_x)
+  
+
+     4 'h0,
+     4 'h1,
+     4 'h2:   csr_read_data_x = interrupt_csr_read_data_x;  
+ 
+
+  
+         
+
+
+     4 'h6:  csr_read_data_x = cfg;
+     4 'h7:  csr_read_data_x = {eba, 8'h00};
+  
+        
+
+
+  
+          
+        
+
+
+     4 'ha: csr_read_data_x = cfg2;
+     4 'hb:  csr_read_data_x = sdb_address;
+  
+        
+
+
+      
+      
+    default:        csr_read_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        eba <= eba_reset[ (32-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  4 'h7) && (stall_x ==  1'b0))
+            eba <= operand_1_x[ (32-2)+2-1:8];
+  
+  
+              
+           
+ 
+  
+              
+           
+ 	 
+
+
+    end
+end
+
+  
+
+   
+
+       
+          
+    
+    
+                   
+              
+  
+   
+              
+           
+  
+   
+              
+           
+         
+ 
+    
+
+
+
+
+
+  
+   
+
+       
+          
+    
+            
+
+
+
+
+  
+
+   
+
+       
+          
+    
+    
+        
+                
+             
+	     
+	
+        
+               
+              
+    
+
+
+
+ 
+
+
+  
+ 
+ 
+
+           
+           
+       
+          
+            
+                 
+             
+          
+     
+            
+ 
+
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+
+  
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+ 
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        valid_f <=  1'b0;
+        valid_d <=  1'b0;
+        valid_x <=  1'b0;
+        valid_m <=  1'b0;
+        valid_w <=  1'b0;
+    end
+    else
+    begin    
+        if ((kill_f ==  1'b1) || (stall_a ==  1'b0))
+  
+                  
+
+
+            valid_f <=  1'b1;
+ 
+            
+        else if (stall_f ==  1'b0)
+            valid_f <=  1'b0;            
+
+        if (kill_d ==  1'b1)
+            valid_d <=  1'b0;
+        else if (stall_f ==  1'b0)
+            valid_d <= valid_f & !kill_f;
+        else if (stall_d ==  1'b0)
+            valid_d <=  1'b0;
+       
+        if (stall_d ==  1'b0)
+            valid_x <= valid_d & !kill_d;
+        else if (kill_x ==  1'b1)
+            valid_x <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_x <=  1'b0;
+
+        if (kill_m ==  1'b1)
+            valid_m <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_m <= valid_x & !kill_x;
+        else if (stall_m ==  1'b0)
+            valid_m <=  1'b0;
+
+        if (stall_m ==  1'b0)
+            valid_w <= valid_m & !kill_m;
+        else 
+            valid_w <=  1'b0;        
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+  
+                 
+
+        
+        operand_0_x <= { 32{1'b0}};
+        operand_1_x <= { 32{1'b0}};
+        store_operand_x <= { 32{1'b0}};
+        branch_target_x <= { (32-2){1'b0}};        
+        x_result_sel_csr_x <=  1'b0;
+  
+          
+
+
+      
+          
+
+
+  
+
+        x_result_sel_sext_x <=  1'b0;
+ 
+    
+  
+          
+
+
+        x_result_sel_add_x <=  1'b0;
+        m_result_sel_compare_x <=  1'b0;
+  
+
+        m_result_sel_shift_x <=  1'b0;
+ 
+    
+        w_result_sel_load_x <=  1'b0;
+  
+
+        w_result_sel_mul_x <=  1'b0;
+ 
+
+        x_bypass_enable_x <=  1'b0;
+        m_bypass_enable_x <=  1'b0;
+        write_enable_x <=  1'b0;
+        write_idx_x <= { 5{1'b0}};
+        csr_x <= { 4 {1'b0}};
+        load_x <=  1'b0;
+        store_x <=  1'b0;
+        size_x <= { 2{1'b0}};
+        sign_extend_x <=  1'b0;
+        adder_op_x <=  1'b0;
+        adder_op_x_n <=  1'b0;
+        logic_op_x <= 4'h0;
+  
+
+        direction_x <=  1'b0;
+ 
+
+  
+          
+
+
+
+        branch_x <=  1'b0;
+        branch_predict_x <=  1'b0;
+        branch_predict_taken_x <=  1'b0;
+        condition_x <=  3'b000;
+  
+          
+
+
+        scall_x <=  1'b0;
+        eret_x <=  1'b0;
+  
+          
+
+
+  
+          
+          
+
+
+        csr_write_enable_x <=  1'b0;
+        operand_m <= { 32{1'b0}};
+        branch_target_m <= { (32-2){1'b0}};
+        m_result_sel_compare_m <=  1'b0;
+  
+
+        m_result_sel_shift_m <=  1'b0;
+ 
+    
+        w_result_sel_load_m <=  1'b0;
+  
+
+        w_result_sel_mul_m <=  1'b0;
+ 
+
+        m_bypass_enable_m <=  1'b0;
+        branch_m <=  1'b0;
+        branch_predict_m <=  1'b0;
+	branch_predict_taken_m <=  1'b0;
+        exception_m <=  1'b0;
+        load_m <=  1'b0;
+        store_m <=  1'b0;
+        write_enable_m <=  1'b0;            
+        write_idx_m <= { 5{1'b0}};
+        condition_met_m <=  1'b0;
+  
+          
+
+
+  
+          
+                  
+
+
+        operand_w <= { 32{1'b0}};        
+        w_result_sel_load_w <=  1'b0;
+  
+
+        w_result_sel_mul_w <=  1'b0;
+ 
+
+        write_idx_w <= { 5{1'b0}};        
+        write_enable_w <=  1'b0;
+  
+          
+                  
+
+
+        exception_w <=  1'b0;
+ 
+
+  
+          
+
+
+    end
+    else
+    begin
+        
+       
+        if (stall_x ==  1'b0)
+        begin
+  
+                     
+
+        
+            operand_0_x <= d_result_0;
+            operand_1_x <= d_result_1;
+            store_operand_x <= bypass_data_1;
+            branch_target_x <= branch_reg_d ==  1'b1 ? bypass_data_0[ ((32-2)+2-1):2] : branch_target_d;            
+            x_result_sel_csr_x <= x_result_sel_csr_d;
+  
+              
+
+
+      
+              
+
+
+  
+
+            x_result_sel_sext_x <= x_result_sel_sext_d;
+ 
+    
+  
+              
+
+
+            x_result_sel_add_x <= x_result_sel_add_d;
+            m_result_sel_compare_x <= m_result_sel_compare_d;
+  
+
+            m_result_sel_shift_x <= m_result_sel_shift_d;
+ 
+    
+            w_result_sel_load_x <= w_result_sel_load_d;
+  
+
+            w_result_sel_mul_x <= w_result_sel_mul_d;
+ 
+
+            x_bypass_enable_x <= x_bypass_enable_d;
+            m_bypass_enable_x <= m_bypass_enable_d;
+            load_x <= load_d;
+            store_x <= store_d;
+            branch_x <= branch_d;
+	    branch_predict_x <= branch_predict_d;
+	    branch_predict_taken_x <= branch_predict_taken_d;
+	    write_idx_x <= write_idx_d;
+            csr_x <= csr_d;
+            size_x <= size_d;
+            sign_extend_x <= sign_extend_d;
+            adder_op_x <= adder_op_d;
+            adder_op_x_n <= ~adder_op_d;
+            logic_op_x <= logic_op_d;
+  
+
+            direction_x <= direction_d;
+ 
+
+  
+              
+
+
+            condition_x <= condition_d;
+            csr_write_enable_x <= csr_write_enable_d;
+  
+              
+
+
+            scall_x <= scall_d;
+  
+              
+
+
+            eret_x <= eret_d;
+  
+               
+
+
+            write_enable_x <= write_enable_d;
+        end
+        
+        
+
+        if (stall_m ==  1'b0)
+        begin
+            operand_m <= x_result;
+            m_result_sel_compare_m <= m_result_sel_compare_x;
+  
+
+            m_result_sel_shift_m <= m_result_sel_shift_x;
+ 
+    
+            if (exception_x ==  1'b1)
+            begin
+                w_result_sel_load_m <=  1'b0;
+  
+
+                w_result_sel_mul_m <=  1'b0;
+ 
+
+            end
+            else
+            begin
+                w_result_sel_load_m <= w_result_sel_load_x;
+  
+
+                w_result_sel_mul_m <= w_result_sel_mul_x;
+ 
+
+            end
+            m_bypass_enable_m <= m_bypass_enable_x;
+            load_m <= load_x;
+            store_m <= store_x;
+      
+                
+
+
+            branch_m <= branch_x;
+	    branch_predict_m <= branch_predict_x;
+	    branch_predict_taken_m <= branch_predict_taken_x;
+ 
+
+  
+	   
+	   
+	   
+	   
+	   
+                
+                  
+                
+                  
+             
+                  
+
+
+            if (exception_x ==  1'b1)
+                write_idx_m <=  5'd30;
+            else 
+                write_idx_m <= write_idx_x;
+ 
+
+            condition_met_m <= condition_met_x;
+  
+	      
+	        
+		     
+		        
+	           
+	     
+	           
+	   
+	       
+
+
+            branch_target_m <= exception_x ==  1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
+ 
+
+  
+              
+              
+
+
+  
+              
+
+
+  
+ 
+               
+
+
+
+            write_enable_m <= exception_x ==  1'b1 ?  1'b1 : write_enable_x;            
+  
+              
+                      
+
+
+        end
+        
+        
+        if (stall_m ==  1'b0)
+        begin
+            if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+                exception_m <=  1'b1;
+            else 
+                exception_m <=  1'b0;
+  
+	           
+ 
+					    
+
+					 
+
+
+	end
+                
+        
+  
+                      
+
+
+        operand_w <= exception_m ==  1'b1 ? {pc_m, 2'b00} : m_result;
+ 
+
+        w_result_sel_load_w <= w_result_sel_load_m;
+  
+
+        w_result_sel_mul_w <= w_result_sel_mul_m;
+ 
+
+        write_idx_w <= write_idx_m;
+  
+          
+          
+ 
+           
+
+
+
+        write_enable_w <= write_enable_m;
+  
+          
+          
+
+
+        exception_w <= exception_m;
+ 
+
+  
+              
+                   
+                   
+               
+	   
+            
+
+
+    end
+end
+
+  
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        use_buf <=  1'b0;
+        reg_data_buf_0 <= { 32{1'b0}};
+        reg_data_buf_1 <= { 32{1'b0}};
+    end
+    else
+    begin
+        if (stall_d ==  1'b0)
+            use_buf <=  1'b0;
+        else if (use_buf ==  1'b0)
+        begin        
+            reg_data_buf_0 <= reg_data_live_0;
+            reg_data_buf_1 <= reg_data_live_1;
+            use_buf <=  1'b1;
+        end        
+        if (reg_write_enable_q_w ==  1'b1)
+        begin
+            if (write_idx_w == read_idx_0_d)
+                reg_data_buf_0 <= w_result;
+            if (write_idx_w == read_idx_1_d)
+                reg_data_buf_1 <= w_result;
+        end
+    end
+end
+ 
+
+
+  
+
+ 
+
+   
+
+        
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+     
+           
+            
+        
+
+
+
+
+  
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+ 
+          
+
+          
+    
+    
+    
+          
+        
+ 
+               
+
+           
+
+                
+              
+              
+              
+              
+        
+        
+              
+        
+             
+        
+            
+                 
+            
+                
+                  
+                  
+            
+            
+              
+            
+              
+ 
+              
+
+        
+        
+        
+              
+ 
+              
+
+        
+    
+
+
+
+      
+
+
+
+
+
+        
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_load_store_unit_medium 
+(
+    
+    clk_i,
+    rst_i,
+ 
+    stall_a,
+    stall_x,
+    stall_m,
+    kill_x,
+    kill_m,
+    exception_m,
+    store_operand_x,
+    load_store_address_x,
+    load_store_address_m,
+    load_store_address_w,
+    load_x,
+    store_x,
+    load_q_x,
+    store_q_x,
+    load_q_m,
+    store_q_m,
+    sign_extend_x,
+    size_x,
+  
+    
+
+
+    
+    d_dat_i,
+    d_ack_i,
+    d_err_i,
+    d_rty_i,
+    
+    
+  
+    
+    
+    
+    
+
+    
+  
+    
+    
+    
+    
+    
+    
+    
+
+			     
+    load_data_w,
+    stall_wb_load,
+    
+    d_dat_o,
+    d_adr_o,
+    d_cyc_o,
+    d_sel_o,
+    d_stb_o,
+    d_we_o,
+    d_cti_o,
+    d_lock_o,
+    d_bte_o
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+
+   input clk_i;                                            
+   
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+input kill_x;                                           
+input kill_m;                                           
+input exception_m;                                      
+
+input [ (32-1):0] store_operand_x;                 
+input [ (32-1):0] load_store_address_x;            
+input [ (32-1):0] load_store_address_m;            
+input [1:0] load_store_address_w;                       
+input load_x;                                           
+input store_x;                                          
+input load_q_x;                                         
+input store_q_x;                                        
+input load_q_m;                                         
+input store_q_m;                                        
+input sign_extend_x;                                    
+input [ 1:0] size_x;                          
+
+  
+                                            
+
+
+
+     
+     
+     
+      
+      
+            
+    	 
+   
+
+
+
+   reg 		 [31:0] iram_dat_d0;
+   reg 		 iram_en_d0;
+   wire 	 iram_en;
+   wire [31:0] 	 iram_data;
+   
+   
+   
+input [ (32-1):0] d_dat_i;                         
+input d_ack_i;                                          
+input d_err_i;                                          
+input d_rty_i;                                          
+
+
+
+
+
+  
+                            
+   
+                           
+   
+                             
+   
+ 
+   
+
+
+
+   
+output [ (32-1):0] load_data_w;                    
+reg    [ (32-1):0] load_data_w;
+output stall_wb_load;                                   
+reg    stall_wb_load;
+
+output [ (32-1):0] d_dat_o;                        
+reg    [ (32-1):0] d_dat_o;
+output [ (32-1):0] d_adr_o;                        
+reg    [ (32-1):0] d_adr_o;
+output d_cyc_o;                                         
+reg    d_cyc_o;
+output [ (4-1):0] d_sel_o;                 
+reg    [ (4-1):0] d_sel_o;
+output d_stb_o;                                         
+reg    d_stb_o; 
+output d_we_o;                                          
+reg    d_we_o;
+output [ (3-1):0] d_cti_o;                       
+reg    [ (3-1):0] d_cti_o;
+output d_lock_o;                                        
+reg    d_lock_o;
+output [ (2-1):0] d_bte_o;                       
+wire   [ (2-1):0] d_bte_o;
+
+
+
+
+
+
+reg [ 1:0] size_m;
+reg [ 1:0] size_w;
+reg sign_extend_m;
+reg sign_extend_w;
+reg [ (32-1):0] store_data_x;       
+reg [ (32-1):0] store_data_m;       
+reg [ (4-1):0] byte_enable_x;
+reg [ (4-1):0] byte_enable_m;
+wire [ (32-1):0] data_m;
+reg [ (32-1):0] data_w;
+
+   
+
+  
+                                    
+ 
+                      
+              
+                                 
+                  
+                   
+                                          
+                      
+
+
+  
+                                      
+ 
+                                      
+                    
+                      
+                        
+                  
+
+
+wire wb_select_x;                                       
+  
+                                      
+
+  
+    
+    
+   
+
+
+
+reg wb_select_m;
+reg [ (32-1):0] wb_data_m;                         
+reg wb_load_complete;                                   
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+ 
+              
+                       
+             
+               
+                      
+       
+    
+                      
+                            
+                    
+                    
+                    
+                  
+                  
+                     
+                    
+                 
+            
+               
+                
+                     
+    
+              
+            
+             
+             
+                  
+                  
+    
+
+
+
+
+
+
+
+
+  
+            
+                             
+
+
+
+  
+            
+                             
+
+      
+        
+
+    
+       
+
+   
+
+    
+     
+       
+     
+         
+     
+
+          
+    
+   
+   
+
+
+   
+  
+            
+                               
+ 
+                               
+
+ 
+                               
+
+                     
+
+
+	  
+   assign wb_select_x =     1'b1
+  
+                          
+
+
+  
+                         
+
+
+  
+                         
+
+
+                     ;
+
+
+always @(*)
+begin
+    case (size_x)
+     2'b00:  store_data_x = {4{store_operand_x[7:0]}};
+     2'b11: store_data_x = {2{store_operand_x[15:0]}};
+     2'b10:  store_data_x = store_operand_x;    
+    default:          store_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+always @(*)
+begin
+    casez ({size_x, load_store_address_x[1:0]})
+    { 2'b00, 2'b11}:  byte_enable_x = 4'b0001;
+    { 2'b00, 2'b10}:  byte_enable_x = 4'b0010;
+    { 2'b00, 2'b01}:  byte_enable_x = 4'b0100;
+    { 2'b00, 2'b00}:  byte_enable_x = 4'b1000;
+    { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+    { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+    { 2'b10, 2'b??}:  byte_enable_x = 4'b1111;
+    default:                   byte_enable_x = 4'bxxxx;
+    endcase
+end
+
+  
+      
+            
+
+           
+	                            
+   
+   
+               
+        
+
+
+   
+  
+  
+   
+   
+         
+                    
+                       
+                      
+                        
+                     
+                        
+  
+   
+         
+                    
+                       
+                      
+                      
+  
+ 
+   
+   
+         
+                    
+                       
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+
+   
+   
+   
+         
+                     
+                      
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+    
+   
+         
+                     
+                    
+
+  
+
+   
+   assign data_m = wb_data_m;
+   
+
+  
+
+ 
+
+
+
+always @(*)
+begin
+    casez ({size_w, load_store_address_w[1:0]})
+    { 2'b00, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+    { 2'b00, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+    { 2'b00, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+    { 2'b00, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+    { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+    { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+    { 2'b10, 2'b??}:  load_data_w = data_w;
+    default:                   load_data_w = { 32{1'bx}};
+    endcase
+end
+
+
+assign d_bte_o =  2'b00;
+
+                  
+
+ 
+     
+    
+    
+   
+   
+   
+    
+    
+    
+    
+   
+   
+     
+     
+    
+    
+    
+   
+         
+     
+     
+    
+    
+
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        d_cyc_o <=  1'b0;
+        d_stb_o <=  1'b0;
+        d_dat_o <= { 32{1'b0}};
+        d_adr_o <= { 32{1'b0}};
+        d_sel_o <= { 4{ 1'b0}};
+        d_we_o <=  1'b0;
+        d_cti_o <=  3'b111;
+        d_lock_o <=  1'b0;
+        wb_data_m <= { 32{1'b0}};
+        wb_load_complete <=  1'b0;
+        stall_wb_load <=  1'b0;
+                  
+          
+
+                
+    end
+    else 
+    begin
+   
+        
+          
+
+                
+        
+        if (d_cyc_o ==  1'b1)
+        begin
+            
+            if ((d_ack_i ==  1'b1) || (d_err_i ==  1'b1))
+            begin
+                  
+                     
+                
+                    
+                        
+                
+                
+
+                
+                begin
+                    
+                    d_cyc_o <=  1'b0;
+                    d_stb_o <=  1'b0;
+                    d_lock_o <=  1'b0;
+                end
+      
+                  
+                
+                  
+
+
+                
+                wb_data_m <= d_dat_i;
+                
+                wb_load_complete <= !d_we_o;
+            end
+            
+        end
+        else 
+        begin
+                  
+               
+            
+                
+                  
+                  
+                  
+                                  
+                  
+                  
+                
+            
+             
+
+            
+                 if (   (store_q_m ==  1'b1)
+                     && (stall_m ==  1'b0)
+  
+                        
+
+
+  
+		        
+
+			
+                    )
+            begin
+                
+                d_dat_o <= store_data_m;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b1;
+                d_cti_o <=  3'b111;
+            end        
+            else if (   (load_q_m ==  1'b1) 
+                     && (wb_select_m ==  1'b1) 
+                     && (wb_load_complete ==  1'b0)
+                     
+                    )
+            begin
+                
+                stall_wb_load <=  1'b0;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b0;
+                d_cti_o <=  3'b111;
+            end
+        end
+        
+        if (stall_m ==  1'b0)
+            wb_load_complete <=  1'b0;
+        
+        if ((load_q_x ==  1'b1) && (wb_select_x ==  1'b1) && (stall_x ==  1'b0))
+            stall_wb_load <=  1'b1;
+        
+        if ((kill_m ==  1'b1) || (exception_m ==  1'b1))
+            stall_wb_load <=  1'b0;
+    end
+end
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        sign_extend_m <=  1'b0;
+        size_m <= 2'b00;
+        byte_enable_m <=  1'b0;
+        store_data_m <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+  
+          
+			    
+
+
+        wb_select_m <=  1'b0;        
+    end
+    else
+    begin
+        if (stall_m ==  1'b0)
+        begin
+            sign_extend_m <= sign_extend_x;
+            size_m <= size_x;
+            byte_enable_m <= byte_enable_x;    
+            store_data_m <= store_data_x;
+  
+              
+
+
+  
+              
+
+
+  
+              
+			    
+
+
+            wb_select_m <= wb_select_x;
+        end
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        size_w <= 2'b00;
+        data_w <= { 32{1'b0}};
+        sign_extend_w <=  1'b0;
+    end
+    else
+    begin
+        size_w <= size_m;
+
+  
+         
+
+
+        data_w <= data_m;
+
+        sign_extend_w <= sign_extend_m;
+    end
+end
+
+
+
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_decoder_medium (
+    
+    instruction,
+    
+    d_result_sel_0,
+    d_result_sel_1,        
+    x_result_sel_csr,
+  
+    
+
+    
+      
+    
+
+
+  
+
+    x_result_sel_sext,
+ 
+    
+    x_result_sel_logic,
+  
+    
+
+
+    x_result_sel_add,
+    m_result_sel_compare,
+  
+
+    m_result_sel_shift,  
+ 
+    
+    w_result_sel_load,
+  
+
+    w_result_sel_mul,
+ 
+
+    x_bypass_enable,
+    m_bypass_enable,
+    read_enable_0,
+    read_idx_0,
+    read_enable_1,
+    read_idx_1,
+    write_enable,
+    write_idx,
+    immediate,
+    branch_offset,
+    load,
+    store,
+    size,
+    sign_extend,
+    adder_op,
+    logic_op,
+  
+
+    direction,
+ 
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+
+
+    branch,
+    branch_reg,
+    condition,
+    bi_conditional,
+    bi_unconditional,
+  
+    
+
+
+    scall,
+    eret,
+  
+    
+
+
+  
+    
+
+
+    csr_write_enable
+    );
+
+
+
+
+
+input [ (32-1):0] instruction;       
+
+
+
+
+
+output [ 0:0] d_result_sel_0;
+reg    [ 0:0] d_result_sel_0;
+output [ 1:0] d_result_sel_1;
+reg    [ 1:0] d_result_sel_1;
+output x_result_sel_csr;
+reg    x_result_sel_csr;
+  
+ 
+    
+
+
+      
+ 
+    
+
+
+  
+
+output x_result_sel_sext;
+reg    x_result_sel_sext;
+ 
+
+output x_result_sel_logic;
+reg    x_result_sel_logic;
+  
+ 
+    
+
+
+output x_result_sel_add;
+reg    x_result_sel_add;
+output m_result_sel_compare;
+reg    m_result_sel_compare;
+  
+
+output m_result_sel_shift;
+reg    m_result_sel_shift;
+ 
+
+output w_result_sel_load;
+reg    w_result_sel_load;
+  
+
+output w_result_sel_mul;
+reg    w_result_sel_mul;
+ 
+
+output x_bypass_enable;
+wire   x_bypass_enable;
+output m_bypass_enable;
+wire   m_bypass_enable;
+output read_enable_0;
+wire   read_enable_0;
+output [ (5-1):0] read_idx_0;
+wire   [ (5-1):0] read_idx_0;
+output read_enable_1;
+wire   read_enable_1;
+output [ (5-1):0] read_idx_1;
+wire   [ (5-1):0] read_idx_1;
+output write_enable;
+wire   write_enable;
+output [ (5-1):0] write_idx;
+wire   [ (5-1):0] write_idx;
+output [ (32-1):0] immediate;
+wire   [ (32-1):0] immediate;
+output [ ((32-2)+2-1):2] branch_offset;
+wire   [ ((32-2)+2-1):2] branch_offset;
+output load;
+wire   load;
+output store;
+wire   store;
+output [ 1:0] size;
+wire   [ 1:0] size;
+output sign_extend;
+wire   sign_extend;
+output adder_op;
+wire   adder_op;
+output [ 3:0] logic_op;
+wire   [ 3:0] logic_op;
+  
+
+output direction;
+wire   direction;
+ 
+
+  
+ 
+   
+ 
+   
+
+
+  
+ 
+   
+
+
+  
+ 
+   
+ 
+   
+
+
+output branch;
+wire   branch;
+output branch_reg;
+wire   branch_reg;
+output [ (3-1):0] condition;
+wire   [ (3-1):0] condition;
+output bi_conditional;
+wire bi_conditional;
+output bi_unconditional;
+wire bi_unconditional;
+  
+ 
+   
+
+
+output scall;
+wire   scall;
+output eret;
+wire   eret;
+  
+ 
+   
+
+
+  
+  
+    
+
+
+output csr_write_enable;
+wire   csr_write_enable;
+
+
+
+
+
+wire [ (32-1):0] extended_immediate;       
+wire [ (32-1):0] high_immediate;           
+wire [ (32-1):0] call_immediate;           
+wire [ (32-1):0] branch_immediate;         
+wire sign_extend_immediate;                     
+wire select_high_immediate;                     
+wire select_call_immediate;                     
+
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+  
+ 
+
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+  
+ 
+
+
+  
+
+wire op_mul;
+ 
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+  
+
+wire op_sextb;
+wire op_sexth;
+ 
+
+wire op_sh;
+  
+
+wire op_sl;
+ 
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+  
+ 
+
+
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+  
+
+wire shift;
+ 
+
+  
+ 
+
+
+  
+
+wire sext;
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+assign op_add    = instruction[ 30:26] ==  5'b01101;
+assign op_and    = instruction[ 30:26] ==  5'b01000;
+assign op_andhi  = instruction[ 31:26] ==  6'b011000;
+assign op_b      = instruction[ 31:26] ==  6'b110000;
+assign op_bi     = instruction[ 31:26] ==  6'b111000;
+assign op_be     = instruction[ 31:26] ==  6'b010001;
+assign op_bg     = instruction[ 31:26] ==  6'b010010;
+assign op_bge    = instruction[ 31:26] ==  6'b010011;
+assign op_bgeu   = instruction[ 31:26] ==  6'b010100;
+assign op_bgu    = instruction[ 31:26] ==  6'b010101;
+assign op_bne    = instruction[ 31:26] ==  6'b010111;
+assign op_call   = instruction[ 31:26] ==  6'b110110;
+assign op_calli  = instruction[ 31:26] ==  6'b111110;
+assign op_cmpe   = instruction[ 30:26] ==  5'b11001;
+assign op_cmpg   = instruction[ 30:26] ==  5'b11010;
+assign op_cmpge  = instruction[ 30:26] ==  5'b11011;
+assign op_cmpgeu = instruction[ 30:26] ==  5'b11100;
+assign op_cmpgu  = instruction[ 30:26] ==  5'b11101;
+assign op_cmpne  = instruction[ 30:26] ==  5'b11111;
+  
+       
+
+
+assign op_lb     = instruction[ 31:26] ==  6'b000100;
+assign op_lbu    = instruction[ 31:26] ==  6'b010000;
+assign op_lh     = instruction[ 31:26] ==  6'b000111;
+assign op_lhu    = instruction[ 31:26] ==  6'b001011;
+assign op_lw     = instruction[ 31:26] ==  6'b001010;
+  
+       
+
+
+  
+
+assign op_mul    = instruction[ 30:26] ==  5'b00010;
+ 
+
+assign op_nor    = instruction[ 30:26] ==  5'b00001;
+assign op_or     = instruction[ 30:26] ==  5'b01110;
+assign op_orhi   = instruction[ 31:26] ==  6'b011110;
+assign op_raise  = instruction[ 31:26] ==  6'b101011;
+assign op_rcsr   = instruction[ 31:26] ==  6'b100100;
+assign op_sb     = instruction[ 31:26] ==  6'b001100;
+  
+
+assign op_sextb  = instruction[ 31:26] ==  6'b101100;
+assign op_sexth  = instruction[ 31:26] ==  6'b110111;
+ 
+
+assign op_sh     = instruction[ 31:26] ==  6'b000011;
+  
+
+assign op_sl     = instruction[ 30:26] ==  5'b01111;      
+ 
+
+assign op_sr     = instruction[ 30:26] ==  5'b00101;
+assign op_sru    = instruction[ 30:26] ==  5'b00000;
+assign op_sub    = instruction[ 31:26] ==  6'b110010;
+assign op_sw     = instruction[ 31:26] ==  6'b010110;
+  
+       
+
+
+assign op_wcsr   = instruction[ 31:26] ==  6'b110100;
+assign op_xnor   = instruction[ 30:26] ==  5'b01001;
+assign op_xor    = instruction[ 30:26] ==  5'b00110;
+
+
+assign arith = op_add | op_sub;
+assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
+assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
+assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
+assign bi_unconditional = op_bi;
+assign bra = op_b | bi_unconditional | bi_conditional;
+assign call = op_call | op_calli;
+  
+
+assign shift = op_sl | op_sr | op_sru;
+ 
+
+  
+     
+
+
+  
+   
+     
+
+
+  
+
+assign sext = op_sextb | op_sexth;
+ 
+
+  
+   
+
+
+  
+    
+   
+
+
+assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
+assign store = op_sb | op_sh | op_sw;
+
+
+always @(*)
+begin
+    
+    if (call) 
+        d_result_sel_0 =  1'b1;
+    else 
+        d_result_sel_0 =  1'b0;
+    if (call) 
+        d_result_sel_1 =  2'b00;         
+    else if ((instruction[31] == 1'b0) && !bra) 
+        d_result_sel_1 =  2'b10;
+    else
+        d_result_sel_1 =  2'b01; 
+    
+    x_result_sel_csr =  1'b0;
+  
+      
+
+
+  
+      
+
+
+  
+
+    x_result_sel_sext =  1'b0;
+ 
+
+    x_result_sel_logic =  1'b0;
+          
+      
+
+
+    x_result_sel_add =  1'b0;
+    if (op_rcsr)
+        x_result_sel_csr =  1'b1;
+      
+ 
+         
+          
+
+ 
+        
+                  
+
+ 
+      
+                      
+
+
+
+  
+      
+                  
+
+
+  
+
+    else if (sext)
+        x_result_sel_sext =  1'b1;
+ 
+        
+    else if (logical) 
+        x_result_sel_logic =  1'b1;
+          
+      
+          
+
+
+    else 
+        x_result_sel_add =  1'b1;        
+    
+    
+
+    m_result_sel_compare = cmp;
+  
+
+    m_result_sel_shift = shift;
+ 
+
+
+    
+    w_result_sel_load = load;
+  
+
+    w_result_sel_mul = op_mul; 
+ 
+
+end
+
+
+assign x_bypass_enable =  arith 
+                        | logical
+  
+                         
+                         
+
+                        
+  
+                         
+
+
+  
+                         
+                         
+
+
+  
+                         
+
+                  
+  
+
+                        | sext 
+ 
+                        
+  
+                         
+
+
+                        | op_rcsr
+                        ;
+
+assign m_bypass_enable = x_bypass_enable 
+  
+
+                        | shift
+ 
+
+                        | cmp
+                        ;
+
+assign read_enable_0 = ~(op_bi | op_calli);
+assign read_idx_0 = instruction[25:21];
+
+assign read_enable_1 = ~(op_bi | op_calli | load);
+assign read_idx_1 = instruction[20:16];
+
+assign write_enable = ~(bra | op_raise | store | op_wcsr);
+assign write_idx = call
+                    ? 5'd29
+                    : instruction[31] == 1'b0 
+                        ? instruction[20:16] 
+                        : instruction[15:11];
+                        
+
+assign size = instruction[27:26];
+
+assign sign_extend = instruction[28];                      
+
+assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
+
+assign logic_op = instruction[29:26];
+  
+
+
+assign direction = instruction[29];
+ 
+
+
+assign branch = bra | call;
+assign branch_reg = op_call | op_b;
+assign condition = instruction[28:26];      
+  
+     
+
+
+assign scall = op_raise & instruction[2];
+assign eret = op_b & (instruction[25:21] == 5'd30);
+  
+       
+
+
+  
+
+   
+
+
+
+assign csr_write_enable = op_wcsr;
+
+
+
+assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
+assign select_high_immediate = op_andhi | op_orhi;
+assign select_call_immediate = instruction[31];
+
+assign high_immediate = {instruction[15:0], 16'h0000};
+assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
+assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
+assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
+
+assign immediate = select_high_immediate ==  1'b1 
+                        ? high_immediate 
+                        : extended_immediate;
+   
+assign branch_offset = select_call_immediate ==  1'b1   
+                        ? (call_immediate[ (32-2)-1:0])
+                        : (branch_immediate[ (32-2)-1:0]);
+    
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+           
+              
+              
+              
+
+           
+             
+           
+             
+
+                
+                  
+              
+            
+
+                 
+          
+               
+               
+              
+
+
+
+
+
+   
+    
+    
+        
+    
+    
+    
+    
+    
+    
+    
+    
+ 
+    
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+
+
+
+
+
+                               
+                                      
+                             
+                                
+                                       
+
+   
+   
+   
+   
+   
+   
+   
+   
+   
+
+
+
+
+
+                                         
+                                         
+
+                                       
+                                       
+
+                                       
+                        
+   
+                       
+                       
+                                 
+
+                                  
+            
+
+                                        
+ 
+                                      
+
+   
+
+
+
+
+                                
+   
+                              
+    
+                               
+   
+                 
+                    
+                                    
+    
+                  
+    
+
+
+
+
+
+ 
+  
+  
+  
+  
+  
+ 
+
+  
+  
+  
+  
+  
+
+  
+ 
+ 
+ 
+
+  
+  
+ 
+  
+
+ 
+
+
+
+
+
+ 
+
+
+
+
+
+   
+                 
+	  
+	   
+	    
+	     
+	       
+	                        
+	                     
+
+ 
+	    
+	     
+	      
+	                         
+	                        
+	                            
+	                     
+	                      
+	                    
+	                     
+	                     
+	                           
+	      
+	                        
+	      
+	   
+	    
+	     
+	       
+	                        
+	                     
+
+	        
+	    
+	     
+	      
+	                         
+	                        
+	                            
+	                     
+	                      
+	                    
+	                     
+	                       
+	                       
+	      
+	                         
+	      
+	   
+	
+
+
+
+
+
+
+
+
+               
+      
+       
+    
+
+
+
+
+       
+      
+       
+    
+        
+	   
+           
+    
+
+
+
+ 
+       
+    
+    
+   
+
+    
+   
+
+
+   
+    
+                                 
+                                 
+
+
+ 
+                                   
+     
+    
+   
+
+
+
+     
+
+
+
+        
+           
+     
+    
+    
+      
+         
+         
+    
+                     
+
+
+     
+   
+
+
+   
+   
+   
+
+               
+     
+     
+                      
+
+
+
+
+
+
+        
+            
+   
+
+       
+           
+    
+            
+           
+               
+    
+
+    
+
+
+
+   
+
+       
+          
+    
+          
+
+
+
+   
+
+       
+    
+          
+          
+          
+          
+    
+     
+    
+         
+
+        
+        
+                    
+               
+                  
+                
+        
+
+        
+        
+                    
+               
+ 
+	       
+                  
+	      
+
+		  
+	   
+                
+        
+        
+        
+        
+                    
+               
+                  
+               
+            
+                  
+                  
+            
+                
+            
+                  
+                  
+            
+        
+
+        
+        
+                    
+               
+            
+                   
+                
+                      
+                      
+                
+            
+        
+
+                
+    
+
+
+ 
+       
+    
+
+   
+
+       
+          
+     
+    
+         
+        
+        
+        
+                    
+               
+                  
+                
+                  
+        
+
+        
+        
+                    
+               
+                    
+        
+
+                
+    
+
+    
+
+   
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+								 
+  
+
+
+
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+          
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+              
+                  
+                 
+            
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+                     
+                   
+              
+          
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+               
+                   
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+           
+         
+       
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+          
+         
+     
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+               
+              
+          
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+                
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+               
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+           
+              
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+                  
+              
+            
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+               
+               
+              
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+   
+    
+    
+        
+    
+    
+    
+    
+    
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+    
+    
+    
+    
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+    
+    
+    
+    
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+    
+    
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+                               
+                                      
+                             
+                                
+                                       
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+   
+   
+   
+   
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+                       
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+   
+                                  
+    
+                                   
+    
+                   
+     
+                                        
+    
+                        
+    
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+                                   
+                                  
+                     
+                     
+        
+  
+                       
+                       
+                                               
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+          
+         
+          
+         
+                 
+                     
+
+                           
+                                           
+                                              
+                                             
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+                
+             
+                                        
+                   
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+   
+                     
+	  
+	   
+              
+               
+		 
+		  
+		    
+		     
+		     
+
+		      
+		    
+		     
+		      
+		      
+		      
+		      
+		      
+		      
+		      
+		      
+		          
+		     
+		      
+		         
+             
+           
+             
+		               
+		    
+		      
+		       
+			 
+			  
+			  
+
+			   
+			 
+			  
+			   
+			   
+			   
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+			   
+			   
+			       
+			       
+			  
+			   
+			  
+		  
+             
+	   
+	   
+	    
+	     
+	       
+	        
+	        
+
+	         
+	       
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+   
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+               
+      
+       
+    
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+           
+	   
+   
+    
+        
+	   
+        
+    
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+       
+    
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+ 
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+       
+          
+    
+    
+              
+              
+              
+              
+    
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+    
+    
+    
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+ 
+
+       
+          
+    
+          
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+    
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+ 
+        
+      
+                              
+                             
+    
+      
+                             
+                             
+
+   
+
+     
+                             
+                             
+   
+
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+ 
+                                   
+     
+    
+   
+
+
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+     
+       
+
+
+         
+
+
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+        
+           
+             
+         
+     
+     
+      
+                 
+                 
+             
+             
+    
+
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+             
+   
+
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+   
+   
+   
+
+           
+     
+                      
+
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+
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+        
+            
+   
+
+       
+           
+    
+            
+           
+               
+    
+
+     
+   
+
+
+   
+
+       
+          
+     
+          
+
+
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+   
+
+       
+    
+          
+          
+          
+          
+          
+    
+     
+    
+         
+
+        
+        
+        
+               
+                  
+                
+        
+        
+        
+        
+        
+               
+                  
+               
+            
+                  
+                  
+                  
+            
+                
+                  
+        
+
+        
+        
+        
+              
+               
+            
+                   
+                
+                      
+                      
+                
+            
+        
+        
+                
+    
+
+
+
+       
+    
+
+   
+
+       
+          
+     
+    
+         
+        
+        
+        
+        
+               
+                  
+        
+
+        
+        
+        
+               
+                    
+        
+        
+                
+    
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+    
+   
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+                  
+                    
+                 
+                   
+           
+             
+
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+                   
+               
+                 
+
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+                      
+                      
+                      
+
+
+ 
+                    
+
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+                    
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+  
+                    
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+
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+           
+             
+
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+           
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+               
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+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
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+                  
+                    
+                   
+                  
+                   
+          
+
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+                   
+                     
+
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+                   
+                     
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+                    
+                     
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+                      
+                      
+                      
+                     
+                     
+                      
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+                     
+ 
+                      
+                    
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+                     
+                
+ 
+                     
+                     
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+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
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+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
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+                   
+             
+               
+
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+                  
+                    
+                 
+                   
+
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+                   
+                   
+                   
+                   
+
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+                  
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+
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+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
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+
+
+  
+
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+                  
+                 
+         
+     
+     
+              
+
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+  
+    
+     
+    
+    
+    
+    
+    
+    
+    
+    
+ 
+ 
+    
+    
+    
+
+ 
+   
+   
+   
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+ 
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+		   
+ 
+    
+    
+    
+    
+    
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+                                     
+
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+                                    
+                                   
+      
+                        
+            
+                      
+ 
+ 
+                     
+       
+                   
+
+    
+                          
+            
+                          
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+
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+ 
+                                  
+                                  
+                                   
+                               
+                                       
+ 
+                     
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+                                    
+    
+
+                                    
+    
+                                 
+           
+                                 
+   
+
+
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+
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+                                        
+
+
+
+         
+                       
+                
+
+     
+         
+                
+
+                     
+       
+                   
+
+ 
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+             
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+ 
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+
+
+               
+      
+         
+    
+
+ 
+ 
+        
+       
+    
+     
+
+        
+   
+    
+   
+
+    
+               
+
+ 
+               
+      
+             
+                   
+
+
+        
+                   
+    
+   
+
+                
+                 
+
+ 
+         
+         
+         
+
+   
+ 
+         
+         
+         
+
+
+   
+
+   
+   
+   
+
+
+
+
+
+
+
+
+               
+      
+   
+
+       
+    
+          
+          
+    
+    
+    
+                 
+        
+              
+              
+        
+    
+    
+    
+
+
+
+
+               
+      
+   
+
+       
+    
+          
+          
+    
+    
+    
+           
+        
+               
+                  
+                 
+                  
+        
+      
+
+    
+
+
+
+   
+
+       
+          
+    
+    
+               
+              
+    
+    
+
+ 
+
+   
+
+       
+    
+          
+          
+    
+    
+    
+               
+        
+              
+                
+                  
+             
+                  
+        
+         
+        
+        
+            
+                     
+                       
+                    
+                   
+               
+                   
+        
+        
+        
+            
+                   
+                  
+        
+        
+        
+            
+ 
+               
+                  
+             
+
+                            
+            
+                  
+                  
+            
+        
+        
+        
+            
+ 
+               
+                  
+             
+
+                  
+        
+        
+    
+
+
+
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+  
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+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
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+ 
+ 
+ 
+ 
+ 
+
+ 
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+ 
+
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+ 
+ 
+
+ 
+ 
+
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+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_instruction_unit_medium (
+    
+    clk_i,
+    rst_i,
+    
+    stall_a,
+    stall_f,
+    stall_d,
+    stall_x,
+    stall_m,
+    valid_f,
+    valid_d,
+    kill_f,
+    branch_predict_taken_d,
+    branch_predict_address_d,
+      
+    
+    
+
+
+    exception_m,
+    branch_taken_m,
+    branch_mispredict_taken_m,
+    branch_target_m,
+  
+    
+
+
+  
+    
+    
+    
+
+        
+  
+
+    
+    i_dat_i,
+    i_ack_i,
+    i_err_i,
+    i_rty_i,
+ 
+
+  
+    
+    
+    
+    
+
+
+    
+    
+    pc_f,
+    pc_d,
+    pc_x,
+    pc_m,
+    pc_w,
+  
+    
+    
+    
+    
+
+
+  
+
+    
+    i_dat_o,
+    i_adr_o,
+    i_cyc_o,
+    i_sel_o,
+    i_stb_o,
+    i_we_o,
+    i_cti_o,
+    i_lock_o,
+    i_bte_o,
+ 
+
+  
+    
+    
+    
+
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+
+    instruction_f,
+ 
+    
+    instruction_d
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                   
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam eba_reset_minus_4 = eba_reset - 4;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+  
+  
+   
+        
+   
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_f;                                          
+input stall_d;                                          
+input stall_x;                                          
+input stall_m;                                          
+input valid_f;                                          
+input valid_d;                                          
+input kill_f;                                           
+
+input branch_predict_taken_d;                           
+input [ ((32-2)+2-1):2] branch_predict_address_d;          
+   
+      
+                                    
+                     
+
+
+input exception_m;
+input branch_taken_m;                                   
+input branch_mispredict_taken_m;                        
+input [ ((32-2)+2-1):2] branch_target_m;                   
+
+  
+                                            
+
+
+  
+                            
+                             
+ 
+
+        
+
+
+  
+
+input [ (32-1):0] i_dat_i;                         
+input i_ack_i;                                          
+input i_err_i;                                          
+input i_rty_i;                                          
+ 
+
+
+  
+                                  
+                                 
+                   
+                      
+
+
+
+
+
+
+        
+output [ ((32-2)+2-1):2] pc_f;                             
+reg    [ ((32-2)+2-1):2] pc_f;
+output [ ((32-2)+2-1):2] pc_d;                             
+reg    [ ((32-2)+2-1):2] pc_d;
+output [ ((32-2)+2-1):2] pc_x;                             
+reg    [ ((32-2)+2-1):2] pc_x;
+output [ ((32-2)+2-1):2] pc_m;                             
+reg    [ ((32-2)+2-1):2] pc_m;
+output [ ((32-2)+2-1):2] pc_w;                             
+reg    [ ((32-2)+2-1):2] pc_w;
+
+  
+                             
+   
+                           
+   
+                            
+   
+                                 
+   
+
+
+
+  
+
+output [ (32-1):0] i_dat_o;                        
+  
+     
+
+
+wire   [ (32-1):0] i_dat_o;
+ 
+
+output [ (32-1):0] i_adr_o;                        
+reg    [ (32-1):0] i_adr_o;
+output i_cyc_o;                                         
+reg    i_cyc_o; 
+output [ (4-1):0] i_sel_o;                 
+  
+     
+
+
+wire   [ (4-1):0] i_sel_o;
+ 
+
+output i_stb_o;                                         
+reg    i_stb_o;
+output i_we_o;                                          
+  
+    
+
+
+wire   i_we_o;
+ 
+
+output [ (3-1):0] i_cti_o;                       
+reg    [ (3-1):0] i_cti_o;
+output i_lock_o;                                        
+reg    i_lock_o;
+output [ (2-1):0] i_bte_o;                       
+wire   [ (2-1):0] i_bte_o;
+ 
+
+
+  
+                   
+     
+                             
+   
+
+
+
+  
+                                      
+    
+
+
+  
+
+output [ (32-1):0] instruction_f;           
+wire   [ (32-1):0] instruction_f;
+ 
+
+output [ (32-1):0] instruction_d;           
+reg    [ (32-1):0] instruction_d;
+
+
+
+
+
+reg [ ((32-2)+2-1):2] pc_a;                                
+
+  
+                       
+
+
+
+  
+                               
+                
+                                 
+           
+               
+                  
+                   
+                                          
+                        
+
+
+  
+
+reg [ (32-1):0] wb_data_f;                  
+ 
+
+ 
+
+  
+                                      
+    			     
+   
+
+
+  
+
+ 
+               
+
+
+
+   
+  
+   
+    			               
+ 
+
+
+  
+    		       
+
+
+   
+  
+                                         
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+ 
+              
+                       
+             
+               
+                      
+       
+    
+                      
+                            
+                    
+                    
+     
+                    
+                  
+                  
+              
+               
+                
+                     
+    
+              
+            
+             
+             
+                  
+                       
+    
+
+
+
+
+
+
+
+  
+   
+           
+        
+  
+      
+                          
+   
+				       
+        
+				    
+
+ 
+
+
+always @(*)
+begin
+    
+  
+       
+          
+     
+
+    
+      if (branch_taken_m ==  1'b1)
+	if ((branch_mispredict_taken_m ==  1'b1) && (exception_m ==  1'b0))
+	  pc_a = pc_x;
+	else
+          pc_a = branch_target_m;
+      
+          
+          
+
+
+      else
+	if ( (valid_d ==  1'b1) && (branch_predict_taken_d ==  1'b1) )
+	  pc_a = branch_predict_address_d;
+	else
+  
+             
+              
+	   
+
+        
+            pc_a = pc_f + 1'b1;
+end
+
+
+  
+      
+      
+        
+
+
+
+  
+
+     
+    	      
+
+     
+      
+	  
+       
+	  
+	
+	    
+     
+   
+   
+          
+
+
+  
+   
+
+
+                     
+
+  
+   
+
+
+assign instruction_f = wb_data_f;
+ 
+
+
+ 
+ 
+   
+
+  
+
+  
+
+
+assign i_dat_o = 32'd0;
+assign i_we_o =  1'b0;
+assign i_sel_o = 4'b1111;
+ 
+
+assign i_bte_o =  2'b00;
+ 
+
+
+  
+
+
+     
+    
+    
+   
+   
+   
+   
+    
+    
+    
+   
+   
+     
+    
+    
+    
+    
+   
+         
+     
+    
+    
+    
+
+
+
+                     
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        pc_f <= eba_reset_minus_4[ ((32-2)+2-1):2];
+        pc_d <= { (32-2){1'b0}};
+        pc_x <= { (32-2){1'b0}};
+        pc_m <= { (32-2){1'b0}};
+        pc_w <= { (32-2){1'b0}};
+    end
+    else
+    begin
+        if (stall_f ==  1'b0)
+            pc_f <= pc_a;
+        if (stall_d ==  1'b0)
+            pc_d <= pc_f;
+        if (stall_x ==  1'b0)
+            pc_x <= pc_d;
+        if (stall_m ==  1'b0)
+            pc_m <= pc_x;
+        pc_w <= pc_m;
+    end
+end
+
+  
+
+   
+
+       
+          
+    
+    
+ 
+         
+            
+               
+                  
+                    
+                  
+
+               
+                  
+
+
+         
+               
+                  
+
+
+    
+
+
+
+
+
+  
+   
+
+       
+          
+    
+    
+           
+              
+    
+
+
+
+
+  
+    
+                 
+ 
+
+     
+       
+       
+       
+       
+     
+
+   
+
+
+
+  
+
+   
+                   
+      
+     
+	   
+	  
+               
+               
+               
+               
+               
+               
+               
+   
+               
+  
+   
+               
+               
+               
+  
+	  
+	
+	     
+               
+             
+                
+               
+		  
+		         
+		    
+   
+                          
+			 
+			      
+			             
+			        
+			          
+			 
+                       
+  
+			 
+			       
+			      
+				 
+				   
+				   
+				   
+			      
+			    
+			        
+			      
+			    
+			      
+			      
+			 
+		    
+   
+		   
+		     
+		    
+                         
+                         
+		    
+		  
+  
+               
+             
+               
+		         
+		    
+                       
+        
+                         
+  
+                          
+                         
+                                         
+                         
+                       
+   
+                         
+  
+		    
+   
+		  
+		    
+                              
+			 
+			     
+			         
+			         
+			         
+			         
+			    
+			      
+			      
+			      
+			      
+			      
+			      
+			      
+			 
+		     
+                      
+   
+		  
+		  
+        
+		     
+                      
+   
+		     
+                      
+  
+               
+	  
+     
+ 
+
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             i_cyc_o <=  1'b0;
+             i_stb_o <=  1'b0;
+             i_adr_o <= { 32{1'b0}};
+             i_cti_o <=  3'b111;
+             i_lock_o <=  1'b0;
+             wb_data_f <= { 32{1'b0}};
+    
+               
+  
+
+	  end
+	else
+	  begin   
+             
+             if (i_cyc_o ==  1'b1)
+               begin
+		  
+		  if((i_ack_i ==  1'b1) || (i_err_i ==  1'b1))
+		    begin
+                       
+                       i_cyc_o <=  1'b0;
+                       i_stb_o <=  1'b0;
+                       
+                       wb_data_f <= i_dat_i;
+		    end
+    
+		   
+		     
+		    
+                         
+                         
+		       
+		    
+		  
+  
+
+               end
+             else
+               begin
+		  
+		  if (   (stall_a ==  1'b0) 
+     
+			    
+  
+       
+			 )
+		    begin
+                       
+         
+                         
+  
+
+                       i_adr_o <= {pc_a, 2'b00};
+                       i_cyc_o <=  1'b1;
+                       i_stb_o <=  1'b1;
+    
+                         
+  
+
+		    end
+		  else
+		    begin
+	               if (   (stall_a ==  1'b0) 
+     
+			         
+  
+       
+			      )
+			 begin
+    
+			      
+  
+
+			 end
+		    end
+               end
+	  end
+     end
+  
+
+ 
+ 
+
+   
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             instruction_d <= { 32{1'b0}};
+  
+               
+
+
+	  end
+	else
+	  begin
+             if (stall_d ==  1'b0)
+               begin
+		  instruction_d <= instruction_f;
+  
+		    
+
+
+               end
+	  end
+     end  
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+                              
+                              
+                              
+
+
+                          
+                  
+                 
+              
+             
+                    
+                        
+                        
+
+
+                  
+         
+          
+          
+          
+          
+          
+      
+      
+         
+
+
+
+
+
+  
+    
+    
+    
+     
+    
+    
+    
+ 
+    
+    
+    
+    
+
+ 
+    
+    
+
+ 
+    
+
+    
+ 
+    
+    
+
+ 
+    
+    
+    
+    
+    
+    
+    
+
+ 
+    
+    
+
+    
+    
+    
+
+
+
+
+
+                                             
+                                             
+
+                                          
+                                       
+                        
+                              
+
+ 
+                                
+                                  
+                    
+                                           
+
+ 
+                    
+                              
+
+ 
+                                     
+
+
+
+
+
+       
+ 
+                
+    
+                
+    
+
+ 
+                            
+    
+              
+    
+                          
+    
+                                 
+    
+                                
+    
+                  
+            
+                     
+    
+
+ 
+                                       
+    
+                                       
+    
+
+  
+     
+  
+    
+             
+
+
+
+
+                           
+                         
+                       
+                     
+
+
+
+     
+  
+
+                  
+        
+                       
+        
+                       
+
+
+               
+ 
+         
+  
+  
+  
+  
+                          
+
+
+         
+
+
+
+
+
+ 
+      
+   
+      
+   
+
+                 
+
+                  
+             
+
+   
+
+ 
+   
+
+   
+
+
+                  
+     
+     
+         
+                 
+
+
+
+
+   
+   
+
+
+
+   
+
+       
+    
+          
+          
+          
+          
+    
+    
+    
+          
+          
+          
+          
+    
+
+
+
+   
+
+       
+    
+          
+          
+          
+ 
+          
+          
+          
+          
+
+ 
+          
+          
+
+                  
+          
+          
+          
+          
+
+    
+    
+    
+                  
+               
+        
+             
+            
+            
+                
+                  
+                  
+            
+            
+            
+                
+                  
+            
+            
+        
+
+ 
+        
+           
+        
+              
+              
+        
+
+         
+        
+        
+            
+                 
+            
+                                  
+                 
+ 
+                
+                
+                     
+ 
+                    
+                          
+                    
+                    
+                              
+                          
+                    
+                    
+                          
+                    
+                    
+                              
+                          
+                    
+                    
+                          
+                    
+                    
+                    
+      
+                              
+                                   
+
+                          
+                    
+                    
+                    
+      
+                              
+                                   
+
+                          
+                    
+                                                   
+                
+
+                  
+                
+                
+                      
+                      
+                                    
+                
+                
+                      
+                      
+                
+
+                
+                    
+                                
+            
+        
+ 
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                   
+                      
+                 
+                      
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+             
+            
+            
+            
+                  
+                  
+                  
+            
+            
+            
+            
+                  
+                  
+                  
+            
+            
+            
+                  
+                  
+                  
+            
+            
+        
+        
+        
+               
+                      
+                  
+                  
+                    
+                  
+                  
+            
+            
+        
+        
+              
+              
+              
+            
+
+        
+    
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_interrupt_medium (
+    
+    clk_i, 
+    rst_i,
+    
+    interrupt,
+    
+    stall_x,
+  
+    
+    
+
+
+    exception,
+ 
+
+    eret_q_x,
+  
+    
+
+
+    csr,
+    csr_write_data,
+    csr_write_enable,
+    
+    interrupt_exception,
+    
+    csr_read_data
+    );
+
+
+
+
+
+parameter interrupts =  32;         
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [interrupts-1:0] interrupt;               
+
+input stall_x;                                  
+
+  
+                       
+                           
+
+
+input exception;                                
+ 
+
+input eret_q_x;                                 
+  
+                                  
+
+
+
+input [ (4 -1):0] csr;                      
+input [ (32-1):0] csr_write_data;          
+input csr_write_enable;                         
+
+
+
+
+
+output interrupt_exception;                     
+wire   interrupt_exception;
+
+output [ (32-1):0] csr_read_data;          
+reg    [ (32-1):0] csr_read_data;
+
+
+
+
+
+wire [interrupts-1:0] asserted;                 
+
+wire [interrupts-1:0] interrupt_n_exception;
+
+
+
+reg ie;                                         
+reg eie;                                        
+  
+                                         
+
+
+reg [interrupts-1:0] ip;                        
+reg [interrupts-1:0] im;                        
+
+
+
+
+
+
+assign interrupt_n_exception = ip & im;
+
+
+assign interrupt_exception = (|interrupt_n_exception) & ie;
+
+
+assign asserted = ip | interrupt;
+       
+generate
+    if (interrupts > 1) 
+    begin
+
+always @(*)
+begin
+    case (csr)
+     4 'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+                                    
+
+
+                                    1'b0,                                     
+ 
+
+                                    eie, 
+                                    ie
+                                   };
+     4 'h2:  csr_read_data = ip;
+     4 'h1:  csr_read_data = im;
+    default:       csr_read_data = { 32{1'bx}};
+    endcase
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    case (csr)
+     4 'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+                                     
+
+
+                                    1'b0,                                    
+ 
+
+                                    eie, 
+                                    ie
+                                   };
+     4 'h2:  csr_read_data = ip;
+    default:       csr_read_data = { 32{1'bx}};
+      endcase
+end
+    end
+endgenerate
+    
+
+
+
+
+  
+
+   reg [ 10:0] eie_delay  = 0;
+
+   
+generate
+
+   
+    if (interrupts > 1)
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie                   <=  1'b0;
+        eie                  <=  1'b0;
+  
+                           
+
+
+        im                   <= {interrupts{1'b0}};
+        ip                   <= {interrupts{1'b0}};
+       eie_delay             <= 0;
+       
+    end
+    else
+    begin
+        
+        ip                   <= asserted;
+  
+           
+        
+            
+                           
+                            
+        
+            
+        
+            
+                           
+                            
+        
+
+
+        if (exception ==  1'b1)
+        begin
+            
+            eie              <= ie;
+            ie               <=  1'b0;
+        end
+ 
+
+        else if (stall_x ==  1'b0)
+        begin
+
+           if(eie_delay[0])
+             ie              <= eie;
+           
+           eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+            if (eret_q_x ==  1'b1) begin
+                
+               eie_delay[ 10] <=  1'b1;
+               eie_delay[ 10-1:0] <= 0;
+            end
+           
+                      
+           
+  
+                
+                
+                       
+
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  4 'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+                      
+
+
+                end
+                if (csr ==  4 'h1)
+                    im  <= csr_write_data[interrupts-1:0];
+                if (csr ==  4 'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+else
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie              <=  1'b0;
+        eie             <=  1'b0;
+  
+                      
+
+
+        ip              <= {interrupts{1'b0}};
+       eie_delay        <= 0;
+    end
+    else
+    begin
+        
+        ip              <= asserted;
+  
+           
+        
+            
+                      
+                       
+        
+            
+        
+            
+                      
+                       
+        
+
+
+        if (exception ==  1'b1)
+        begin
+            
+            eie         <= ie;
+            ie          <=  1'b0;
+        end
+ 
+
+        else if (stall_x ==  1'b0)
+          begin
+
+             if(eie_delay[0])
+               ie              <= eie;
+           
+             eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+             if (eret_q_x ==  1'b1) begin
+                
+                eie_delay[ 10] <=  1'b1;
+                eie_delay[ 10-1:0] <= 0;
+             end
+           
+  
+                
+                
+                       
+
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  4 'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+                      
+
+
+                end
+                if (csr ==  4 'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	 
+
+ 
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+  
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+
+
+  
+
+  
+
+ 
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+ 
+ 
+                    
+
+  
+                    
+
+
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+ 
+
+
+  
+
+  
+
+ 
+
+ 
+
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+
+  
+
+  
+
+  
+ 
+ 
+
+ 
+
+
+ 
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+  
+ 
+
+
+
+
+  
+
+  
+
+ 
+
+  
+ 
+
+
+
+
+  
+
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+ 
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+ 
+ 
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+ 
+
+
+
+
+
+
+
+
+module lm32_top_medium_debug (
+    
+    clk_i,
+    rst_i,
+    
+
+    interrupt,
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+    );
+
+parameter eba_reset = 32'h00000000;
+parameter sdb_address = 32'h00000000;
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+
+input [ (32-1):0] interrupt;          
+
+
+  
+               
+                             
+
+    
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+  
+
+
+
+ 
+  
+
+
+wire [ 7:0] jtag_reg_d;
+wire [ 7:0] jtag_reg_q;
+wire jtag_update;
+wire [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_q;
+wire jtck;
+wire jrstn;
+ 
+
+
+
+  
+
+                     
+                             
+                            
+                   
+                                 
+ 
+                                 
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+   
+
+lm32_cpu_medium_debug 
+	#(
+		.eba_reset(eba_reset),
+    .sdb_address(sdb_address)
+	) cpu (
+    
+    .clk_i                 (clk_i),
+  
+                   
+
+
+    .rst_i                 (rst_i),
+    
+  
+
+    .interrupt             (interrupt),
+ 
+
+    
+  
+               
+             
+
+     
+  
+
+    
+    .jtag_clk              (jtck),
+    .jtag_update           (jtag_update),
+    .jtag_reg_q            (jtag_reg_q),
+    .jtag_reg_addr_q       (jtag_reg_addr_q),
+ 
+
+  
+
+     
+    .I_DAT_I               (I_DAT_I),
+    .I_ACK_I               (I_ACK_I),
+    .I_ERR_I               (I_ERR_I),
+    .I_RTY_I               (I_RTY_I),
+ 
+
+    
+    .D_DAT_I               (D_DAT_I),
+    .D_ACK_I               (D_ACK_I),
+    .D_ERR_I               (D_ERR_I),
+    .D_RTY_I               (D_RTY_I),
+    
+  
+                  
+            
+           
+                 
+                
+ 
+                
+
+
+
+  
+
+    .jtag_reg_d            (jtag_reg_d),
+    .jtag_reg_addr_d       (jtag_reg_addr_d),
+ 
+
+      
+                
+               
+            
+            
+
+    
+  
+
+    
+    .I_DAT_O               (I_DAT_O),
+    .I_ADR_O               (I_ADR_O),
+    .I_CYC_O               (I_CYC_O),
+    .I_SEL_O               (I_SEL_O),
+    .I_STB_O               (I_STB_O),
+    .I_WE_O                (I_WE_O),
+    .I_CTI_O               (I_CTI_O),
+    .I_LOCK_O              (I_LOCK_O),
+    .I_BTE_O               (I_BTE_O),
+     
+
+    
+    .D_DAT_O               (D_DAT_O),
+    .D_ADR_O               (D_ADR_O),
+    .D_CYC_O               (D_CYC_O),
+    .D_SEL_O               (D_SEL_O),
+    .D_STB_O               (D_STB_O),
+    .D_WE_O                (D_WE_O),
+    .D_CTI_O               (D_CTI_O),
+    .D_LOCK_O              (D_LOCK_O),
+    .D_BTE_O               (D_BTE_O)
+    );
+   
+  
+		   
+
+jtag_cores jtag_cores (
+    
+    .reg_d                 (jtag_reg_d),
+    .reg_addr_d            (jtag_reg_addr_d),
+    
+    .reg_update            (jtag_update),
+    .reg_q                 (jtag_reg_q),
+    .reg_addr_q            (jtag_reg_addr_q),
+    .jtck                  (jtck),
+    .jrstn                 (jrstn)
+    );
+ 
+        
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+           
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_mc_arithmetic_medium_debug (
+    
+    clk_i,
+    rst_i,
+    stall_d,
+    kill_x,
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+    
+
+
+    operand_0_d,
+    operand_1_d,
+    
+    result_x,
+  
+    
+
+
+    stall_request_x
+    );
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+input stall_d;                                  
+input kill_x;                                   
+  
+                                  
+                                 
+
+
+  
+                                
+
+
+  
+                              
+                             
+                             
+
+
+input [ (32-1):0] operand_0_d;
+input [ (32-1):0] operand_1_d;
+
+
+
+
+
+output [ (32-1):0] result_x;               
+reg    [ (32-1):0] result_x;
+  
+                         
+    
+
+
+output stall_request_x;                         
+wire   stall_request_x;
+
+
+
+
+
+reg [ (32-1):0] p;                         
+reg [ (32-1):0] a;
+reg [ (32-1):0] b;
+  
+  
+
+
+
+reg [ 2:0] state;                 
+reg [5:0] cycles;                               
+
+  
+                               
+                                 
+
+
+
+
+
+
+
+
+assign stall_request_x = state !=  3'b000;
+
+  
+
+      
+
+
+
+  
+
+       
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        cycles <= {6{1'b0}};
+        p <= { 32{1'b0}};
+        a <= { 32{1'b0}};
+        b <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+        result_x <= { 32{1'b0}};
+        state <=  3'b000;
+    end
+    else
+    begin
+  
+          
+
+
+        case (state)
+         3'b000:
+        begin
+            if (stall_d ==  1'b0)                 
+            begin          
+                cycles <=  32;
+                p <= 32'b0;
+                a <= operand_0_d;
+                b <= operand_1_d;                    
+  
+                   
+                      
+                   
+                      
+
+                    
+  
+                   
+                      
+
+
+  
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+
+
+            end            
+        end
+  
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+
+        
+  
+        
+        
+               
+                    
+               
+               
+              
+                   
+                  
+                
+        
+
+     
+  
+        
+               
+               
+              
+                   
+                  
+                
+        
+        
+               
+               
+              
+                   
+                  
+                
+        
+
+   
+        endcase
+    end
+end 
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_cpu_medium_debug (
+    
+    clk_i,
+  
+    
+
+
+    rst_i,
+  
+    
+
+
+  
+   
+   
+   
+   
+   
+   
+
+
+
+    
+  
+
+    interrupt,
+ 
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    jtag_clk,
+    jtag_update, 
+    jtag_reg_q,
+    jtag_reg_addr_q,
+ 
+
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+  
+    
+    
+    
+    
+    
+ 
+    
+
+
+
+  
+
+    jtag_reg_d,
+    jtag_reg_addr_d,
+ 
+
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+ 
+  
+    
+    
+    
+    
+    
+    
+    
+    
+           
+
+
+		 
+		 
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+
+		 
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                           
+  
+
+parameter deba_reset =  32'h10000000;                         
+ 
+
+parameter sdb_address =   32'h00000000;
+
+  
+
+parameter icache_associativity =  1;     
+parameter icache_sets =  256;                       
+parameter icache_bytes_per_line =  16;   
+parameter icache_base_address =  32'h0;       
+parameter icache_limit =  32'h7fffffff;                     
+ 
+       
+                         
+     
+         
+                       
+
+
+
+  
+        
+                          
+      
+          
+                        
+
+
+parameter dcache_associativity = 1;    
+parameter dcache_sets = 512;                      
+parameter dcache_bytes_per_line = 16;  
+parameter dcache_base_address = 0;      
+parameter dcache_limit = 0;                    
+ 
+
+
+  
+
+parameter watchpoints =  32'h4;                       
+ 
+   
+
+
+  
+                          
+
+
+parameter breakpoints = 0;
+ 
+
+
+  
+
+parameter interrupts =  32;                         
+ 
+   
+
+
+
+
+
+
+
+input clk_i;                                    
+  
+                                   
+
+    
+input rst_i;                                    
+
+  
+
+input [ (32-1):0] interrupt;          
+ 
+
+
+  
+               
+                             
+
+    
+
+  
+ 
+input jtag_clk;                                 
+input jtag_update;                              
+input [ 7:0] jtag_reg_q;              
+input [2:0] jtag_reg_addr_q;
+ 
+
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+    
+     
+
+
+   
+   
+  
+                   
+     
+                           
+    
+                          
+    
+                 
+     
+                               
+    
+ 
+                               
+    
+
+
+
+
+  
+
+output [ 7:0] jtag_reg_d;
+wire   [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire   [2:0] jtag_reg_addr_d;
+ 
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+
+  
+      
+     
+       
+      
+             
+
+
+   
+
+
+
+
+
+
+  
+
+reg valid_a;                                    
+ 
+
+reg valid_f;                                    
+reg valid_d;                                    
+reg valid_x;                                    
+reg valid_m;                                    
+reg valid_w;                                    
+   
+wire q_x;
+wire [ (32-1):0] immediate_d;              
+wire load_d;                                    
+reg load_x;                                     
+reg load_m;
+wire load_q_x;
+wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
+wire store_d;                                   
+reg store_x;
+reg store_m;
+wire [ 1:0] size_d;                   
+reg [ 1:0] size_x;
+wire branch_d;                                  
+wire branch_predict_d;                          
+wire branch_predict_taken_d;                    
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;   
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
+wire bi_unconditional;
+wire bi_conditional;
+reg branch_x;                                   
+reg branch_predict_x;
+reg branch_predict_taken_x;
+reg branch_m;
+reg branch_predict_m;
+reg branch_predict_taken_m;
+wire branch_mispredict_taken_m;                 
+wire branch_flushX_m;                           
+wire branch_reg_d;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;            
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;             
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+wire [ 0:0] d_result_sel_0_d; 
+wire [ 1:0] d_result_sel_1_d; 
+
+wire x_result_sel_csr_d;                        
+reg x_result_sel_csr_x;
+  
+ 
+                    
+ 
+
+
+      
+                       
+ 
+
+
+  
+
+wire x_result_sel_sext_d;                       
+reg x_result_sel_sext_x;
+ 
+
+wire x_result_sel_logic_d;                      
+  
+                        
+ 
+
+
+wire x_result_sel_add_d;                        
+reg x_result_sel_add_x;
+wire m_result_sel_compare_d;                    
+reg m_result_sel_compare_x;
+reg m_result_sel_compare_m;
+  
+
+wire m_result_sel_shift_d;                      
+reg m_result_sel_shift_x;
+reg m_result_sel_shift_m;
+ 
+
+wire w_result_sel_load_d;                       
+reg w_result_sel_load_x;
+reg w_result_sel_load_m;
+reg w_result_sel_load_w;
+  
+
+wire w_result_sel_mul_d;                        
+reg w_result_sel_mul_x;
+reg w_result_sel_mul_m;
+reg w_result_sel_mul_w;
+ 
+
+wire x_bypass_enable_d;                         
+reg x_bypass_enable_x;                          
+wire m_bypass_enable_d;                         
+reg m_bypass_enable_x;                          
+reg m_bypass_enable_m;
+wire sign_extend_d;                             
+reg sign_extend_x;
+wire write_enable_d;                            
+reg write_enable_x;
+wire write_enable_q_x;
+reg write_enable_m;
+wire write_enable_q_m;
+reg write_enable_w;
+wire write_enable_q_w;
+wire read_enable_0_d;                           
+wire [ (5-1):0] read_idx_0_d;          
+wire read_enable_1_d;                           
+wire [ (5-1):0] read_idx_1_d;          
+wire [ (5-1):0] write_idx_d;           
+reg [ (5-1):0] write_idx_x;            
+reg [ (5-1):0] write_idx_m;
+reg [ (5-1):0] write_idx_w;
+wire [ (5-1):0] csr_d;                     
+reg  [ (5-1):0] csr_x;                  
+wire [ (3-1):0] condition_d;         
+reg [ (3-1):0] condition_x;          
+  
+
+wire break_d;                                   
+reg break_x;                                    
+ 
+
+wire scall_d;                                   
+reg scall_x;    
+wire eret_d;                                    
+reg eret_x;
+wire eret_q_x;
+  
+ 
+ 
+
+
+  
+
+wire bret_d;                                    
+reg bret_x;
+wire bret_q_x;
+  
+ 
+ 
+
+
+ 
+
+wire csr_write_enable_d;                        
+reg csr_write_enable_x;
+wire csr_write_enable_q_x;
+  
+       
+
+
+
+  
+                                
+ 
+ 
+  
+
+
+
+reg [ (32-1):0] d_result_0;                
+reg [ (32-1):0] d_result_1;                
+reg [ (32-1):0] x_result;                  
+reg [ (32-1):0] m_result;                  
+reg [ (32-1):0] w_result;                  
+
+reg [ (32-1):0] operand_0_x;               
+reg [ (32-1):0] operand_1_x;               
+reg [ (32-1):0] store_operand_x;           
+reg [ (32-1):0] operand_m;                 
+reg [ (32-1):0] operand_w;                 
+
+
+  
+
+reg [ (32-1):0] reg_data_live_0;          
+reg [ (32-1):0] reg_data_live_1;  
+reg use_buf;                                    
+reg [ (32-1):0] reg_data_buf_0;
+reg [ (32-1):0] reg_data_buf_1;
+ 
+
+  
+
+ 
+     
+
+
+wire [ (32-1):0] reg_data_0;               
+wire [ (32-1):0] reg_data_1;               
+reg [ (32-1):0] bypass_data_0;             
+reg [ (32-1):0] bypass_data_1;             
+wire reg_write_enable_q_w;
+
+reg interlock;                                  
+
+wire stall_a;                                   
+wire stall_f;                                   
+wire stall_d;                                   
+wire stall_x;                                   
+wire stall_m;                                   
+
+
+wire adder_op_d;                                
+reg adder_op_x;                                 
+reg adder_op_x_n;                               
+wire [ (32-1):0] adder_result_x;           
+wire adder_overflow_x;                          
+wire adder_carry_n_x;                           
+
+
+wire [ 3:0] logic_op_d;           
+reg [ 3:0] logic_op_x;            
+wire [ (32-1):0] logic_result_x;           
+
+  
+
+
+wire [ (32-1):0] sextb_result_x;           
+wire [ (32-1):0] sexth_result_x;           
+wire [ (32-1):0] sext_result_x;            
+ 
+
+
+
+  
+
+  
+                                   
+                                     
+
+
+wire direction_d;                               
+reg direction_x;                                        
+wire [ (32-1):0] shifter_result_m;         
+ 
+
+  
+                               
+ 
+                              
+ 
+
+
+  
+           
+
+
+
+
+  
+
+wire [ (32-1):0] multiplier_result_w;      
+ 
+
+  
+                                 
+ 
+
+
+
+
+  
+                                   
+ 
+ 
+ 
+                           
+
+
+
+
+  
+                         
+  
+
+
+
+
+  
+
+wire [ (32-1):0] interrupt_csr_read_data_x;
+ 
+
+wire [ (32-1):0] cfg;                      
+wire [ (32-1):0] cfg2;                     
+  
+                          
+
+
+reg [ (32-1):0] csr_read_data_x;           
+
+
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                       
+  
+                          
+
+
+  
+
+wire [ (32-1):0] instruction_f;     
+ 
+
+
+
+wire [ (32-1):0] instruction_d;     
+  
+
+wire iflush;                                    
+wire icache_stall_request;                      
+wire icache_restart_request;                    
+wire icache_refill_request;                     
+wire icache_refilling;                          
+ 
+
+
+
+  
+                                   
+                                     
+                       
+                     
+                      
+                           
+
+
+wire [ (32-1):0] load_data_w;              
+wire stall_wb_load;                             
+
+
+  
+
+  
+
+wire [ (32-1):0] jtx_csr_read_data;        
+wire [ (32-1):0] jrx_csr_read_data;        
+ 
+
+  
+
+wire jtag_csr_write_enable;                     
+wire [ (32-1):0] jtag_csr_write_data;      
+wire [ (5-1):0] jtag_csr;                  
+wire jtag_read_enable;                          
+wire [ 7:0] jtag_read_data;
+wire jtag_write_enable;
+wire [ 7:0] jtag_write_data;
+wire [ (32-1):0] jtag_address;
+wire jtag_access_complete;
+ 
+
+  
+
+wire jtag_break;                                
+ 
+
+ 
+
+
+
+wire raw_x_0;                                   
+wire raw_x_1;                                   
+wire raw_m_0;                                   
+wire raw_m_1;                                   
+wire raw_w_0;                                   
+wire raw_w_1;                                   
+
+
+wire cmp_zero;                                  
+wire cmp_negative;                              
+wire cmp_overflow;                              
+wire cmp_carry_n;                               
+reg condition_met_x;                            
+reg condition_met_m;
+      
+                             
+
+
+wire branch_taken_m;                            
+
+wire kill_f;                                    
+wire kill_d;                                    
+wire kill_x;                                    
+wire kill_m;                                    
+wire kill_w;                                    
+
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;                 
+  
+
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;                
+ 
+
+reg [ (3-1):0] eid_x;                      
+  
+                        
+                        
+
+
+
+  
+
+  
+
+wire dc_ss;                                     
+ 
+
+wire dc_re;                                     
+wire bp_match;
+wire wp_match;
+wire exception_x;                               
+reg exception_m;                                
+wire debug_exception_x;                         
+reg debug_exception_m;
+reg debug_exception_w;
+wire debug_exception_q_w;
+wire non_debug_exception_x;                     
+reg non_debug_exception_m;
+reg non_debug_exception_w;
+wire non_debug_exception_q_w;
+ 
+                                
+ 
+ 
+ 
+
+
+
+  
+
+  
+ 
+wire reset_exception;                           
+ 
+
+  
+                            
+
+
+ 
+
+  
+
+wire interrupt_exception;                       
+ 
+
+  
+
+wire breakpoint_exception;                      
+wire watchpoint_exception;                      
+ 
+
+  
+     
+   
+            
+                   
+
+
+  
+                   
+
+
+wire system_call_exception;                     
+
+  
+                         
+
+
+
+   
+    
+
+
+     
+  
+                          
+   
+            
+   
+                          
+   
+
+    	      
+    	      
+    	      
+    	      
+    	      
+    	      
+   
+   
+
+
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+lm32_instruction_unit_medium_debug #(
+    .eba_reset              (eba_reset),
+    .associativity          (icache_associativity),
+    .sets                   (icache_sets),
+    .bytes_per_line         (icache_bytes_per_line),
+    .base_address           (icache_base_address),
+    .limit                  (icache_limit)
+  ) instruction_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .stall_d                (stall_d),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .valid_f                (valid_f),
+    .valid_d                (valid_d),
+    .kill_f                 (kill_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .branch_predict_address_d (branch_predict_address_d),
+      
+             
+            
+
+
+    .exception_m            (exception_m),
+    .branch_taken_m         (branch_taken_m),
+    .branch_mispredict_taken_m (branch_mispredict_taken_m),
+    .branch_target_m        (branch_target_m),
+  
+
+    .iflush                 (iflush),
+ 
+
+  
+     
+      
+           
+
+        
+  
+
+    
+    .i_dat_i                (I_DAT_I),
+    .i_ack_i                (I_ACK_I),
+    .i_err_i                (I_ERR_I),
+    .i_rty_i                (I_RTY_I),
+ 
+
+  
+
+    .jtag_read_enable       (jtag_read_enable),
+    .jtag_write_enable      (jtag_write_enable),
+    .jtag_write_data        (jtag_write_data),
+    .jtag_address           (jtag_address),
+ 
+
+    
+    
+    .pc_f                   (pc_f),
+    .pc_d                   (pc_d),
+    .pc_x                   (pc_x),
+    .pc_m                   (pc_m),
+    .pc_w                   (pc_w),
+  
+
+    .icache_stall_request   (icache_stall_request),
+    .icache_restart_request (icache_restart_request),
+    .icache_refill_request  (icache_refill_request),
+    .icache_refilling       (icache_refilling),
+ 
+
+  
+
+    
+    .i_dat_o                (I_DAT_O),
+    .i_adr_o                (I_ADR_O),
+    .i_cyc_o                (I_CYC_O),
+    .i_sel_o                (I_SEL_O),
+    .i_stb_o                (I_STB_O),
+    .i_we_o                 (I_WE_O),
+    .i_cti_o                (I_CTI_O),
+    .i_lock_o               (I_LOCK_O),
+    .i_bte_o                (I_BTE_O),
+ 
+ 
+
+  
+    
+    
+    
+
+
+		      	      
+  
+
+    .jtag_read_data         (jtag_read_data),
+    .jtag_access_complete   (jtag_access_complete),
+ 
+
+  
+                
+
+
+  
+
+    .instruction_f          (instruction_f),
+ 
+
+
+		      
+    .instruction_d          (instruction_d)
+
+
+		      
+    );
+
+
+lm32_decoder_medium_debug decoder (
+    
+    .instruction            (instruction_d),
+    
+    .d_result_sel_0         (d_result_sel_0_d),
+    .d_result_sel_1         (d_result_sel_1_d),
+    .x_result_sel_csr       (x_result_sel_csr_d),
+  
+      
+
+
+      
+         
+
+
+  
+
+    .x_result_sel_sext      (x_result_sel_sext_d),
+ 
+    
+    .x_result_sel_logic     (x_result_sel_logic_d),
+  
+          
+
+
+    .x_result_sel_add       (x_result_sel_add_d),
+    .m_result_sel_compare   (m_result_sel_compare_d),
+  
+
+    .m_result_sel_shift     (m_result_sel_shift_d),  
+ 
+    
+    .w_result_sel_load      (w_result_sel_load_d),
+  
+
+    .w_result_sel_mul       (w_result_sel_mul_d),
+ 
+
+    .x_bypass_enable        (x_bypass_enable_d),
+    .m_bypass_enable        (m_bypass_enable_d),
+    .read_enable_0          (read_enable_0_d),
+    .read_idx_0             (read_idx_0_d),
+    .read_enable_1          (read_enable_1_d),
+    .read_idx_1             (read_idx_1_d),
+    .write_enable           (write_enable_d),
+    .write_idx              (write_idx_d),
+    .immediate              (immediate_d),
+    .branch_offset          (branch_offset_d),
+    .load                   (load_d),
+    .store                  (store_d),
+    .size                   (size_d),
+    .sign_extend            (sign_extend_d),
+    .adder_op               (adder_op_d),
+    .logic_op               (logic_op_d),
+  
+
+    .direction              (direction_d),
+ 
+
+  
+                 
+                
+
+
+  
+                   
+
+
+  
+                     
+                    
+
+
+    .branch                 (branch_d),
+    .bi_unconditional       (bi_unconditional),
+    .bi_conditional         (bi_conditional),
+    .branch_reg             (branch_reg_d),
+    .condition              (condition_d),
+  
+
+    .break_opcode           (break_d),
+ 
+
+    .scall                  (scall_d),
+    .eret                   (eret_d),
+  
+
+    .bret                   (bret_d),
+ 
+
+  
+                
+
+
+    .csr_write_enable       (csr_write_enable_d)
+    ); 
+
+
+lm32_load_store_unit_medium_debug #(
+    .associativity          (dcache_associativity),
+    .sets                   (dcache_sets),
+    .bytes_per_line         (dcache_bytes_per_line),
+    .base_address           (dcache_base_address),
+    .limit                  (dcache_limit)
+  ) load_store_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .kill_x                 (kill_x),
+    .kill_m                 (kill_m),
+    .exception_m            (exception_m),
+    .store_operand_x        (store_operand_x),
+    .load_store_address_x   (adder_result_x),
+    .load_store_address_m   (operand_m),
+    .load_store_address_w   (operand_w[1:0]),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_q_x               (load_q_x),
+    .store_q_x              (store_q_x),
+    .load_q_m               (load_q_m),
+    .store_q_m              (store_q_m),
+    .sign_extend_x          (sign_extend_x),
+    .size_x                 (size_x),
+  
+                     
+
+
+
+  
+    
+    
+    
+    
+    
+    
+    
+
+
+		     
+    
+    .d_dat_i                (D_DAT_I),
+    .d_ack_i                (D_ACK_I),
+    .d_err_i                (D_ERR_I),
+    .d_rty_i                (D_RTY_I),
+    
+    
+  
+      
+     
+       
+           
+
+    
+    .load_data_w            (load_data_w),
+    .stall_wb_load          (stall_wb_load),
+    
+    .d_dat_o                (D_DAT_O),
+    .d_adr_o                (D_ADR_O),
+    .d_cyc_o                (D_CYC_O),
+    .d_sel_o                (D_SEL_O),
+    .d_stb_o                (D_STB_O),
+    .d_we_o                 (D_WE_O),
+    .d_cti_o                (D_CTI_O),
+    .d_lock_o               (D_LOCK_O),
+    .d_bte_o                (D_BTE_O)
+    );      
+       
+
+lm32_adder adder (
+    
+    .adder_op_x             (adder_op_x),
+    .adder_op_x_n           (adder_op_x_n),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .adder_result_x         (adder_result_x),
+    .adder_carry_n_x        (adder_carry_n_x),
+    .adder_overflow_x       (adder_overflow_x)
+    );
+
+
+lm32_logic_op logic_op (
+    
+    .logic_op_x             (logic_op_x),
+    .operand_0_x            (operand_0_x),
+
+    .operand_1_x            (operand_1_x),
+    
+    .logic_result_x         (logic_result_x)
+    );
+              
+  
+
+
+lm32_shifter shifter (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .direction_x            (direction_x),
+    .sign_extend_x          (sign_extend_x),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .shifter_result_m       (shifter_result_m)
+    );
+ 
+
+
+  
+
+
+lm32_multiplier multiplier (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .operand_0              (d_result_0),
+    .operand_1              (d_result_1),
+    
+    .result                 (multiplier_result_w)    
+    );
+ 
+
+
+  
+
+  
+    
+                      
+                      
+                    
+                     
+                   
+                   
+                  
+
+         
+                 
+
+ 
+               
+              
+              
+    
+                
+                
+    
+                   
+                   
+           
+
+            
+    
+
+
+              
+  
+
+
+lm32_interrupt_medium_debug interrupt_unit (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    
+    .interrupt              (interrupt),
+    
+    .stall_x                (stall_x),
+  
+
+    .non_debug_exception    (non_debug_exception_q_w), 
+    .debug_exception        (debug_exception_q_w),
+ 
+                   
+
+
+    .eret_q_x               (eret_q_x),
+  
+
+    .bret_q_x               (bret_q_x),
+ 
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    
+    .interrupt_exception    (interrupt_exception),
+    
+    .csr_read_data          (interrupt_csr_read_data_x)
+    );
+ 
+
+
+  
+      
+      
+        
+   
+
+
+
+
+  
+
+
+lm32_jtag_medium_debug jtag (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .jtag_clk               (jtag_clk),
+    .jtag_update            (jtag_update),
+    .jtag_reg_q             (jtag_reg_q),
+    .jtag_reg_addr_q        (jtag_reg_addr_q),
+    
+  
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    .stall_x                (stall_x),
+ 
+
+  
+
+    .jtag_read_data         (jtag_read_data),
+    .jtag_access_complete   (jtag_access_complete),
+ 
+
+  
+
+    .exception_q_w          (debug_exception_q_w || non_debug_exception_q_w),
+ 
+    
+    
+    
+  
+
+    .jtx_csr_read_data      (jtx_csr_read_data),
+    .jrx_csr_read_data      (jrx_csr_read_data),
+ 
+
+  
+
+    .jtag_csr_write_enable  (jtag_csr_write_enable),
+    .jtag_csr_write_data    (jtag_csr_write_data),
+    .jtag_csr               (jtag_csr),
+    .jtag_read_enable       (jtag_read_enable),
+    .jtag_write_enable      (jtag_write_enable),
+    .jtag_write_data        (jtag_write_data),
+    .jtag_address           (jtag_address),
+ 
+
+  
+
+    .jtag_break             (jtag_break),
+    .jtag_reset             (reset_exception),
+ 
+
+    
+    .jtag_reg_d             (jtag_reg_d),
+    .jtag_reg_addr_d        (jtag_reg_addr_d)
+    );
+ 
+
+
+  
+
+
+lm32_debug_medium_debug #(
+    .breakpoints            (breakpoints),
+    .watchpoints            (watchpoints)
+  ) hw_debug (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    .pc_x                   (pc_x),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_store_address_x   (adder_result_x),
+    .csr_write_enable_x     (csr_write_enable_q_x),
+    .csr_write_data         (operand_1_x),
+    .csr_x                  (csr_x),
+   
+
+	        
+
+    .jtag_csr_write_enable  (jtag_csr_write_enable),
+    .jtag_csr_write_data    (jtag_csr_write_data),
+    .jtag_csr               (jtag_csr),
+	       
+
+	        
+      
+        
+                   
+	      
+
+ 
+
+  
+
+    .eret_q_x               (eret_q_x),
+    .bret_q_x               (bret_q_x),
+    .stall_x                (stall_x),
+    .exception_x            (exception_x),
+    .q_x                    (q_x),
+  
+      
+
+
+ 
+
+    
+  
+
+    .dc_ss                  (dc_ss),
+ 
+
+    .dc_re                  (dc_re),
+    .bp_match               (bp_match),
+    .wp_match               (wp_match)
+    );
+ 
+
+
+
+
+  
+
+   
+           
+            
+          
+            
+
+
+             
+              
+    
+
+   wire [31:0] regfile_data_0, regfile_data_1;
+   reg [31:0]  w_result_d;
+   reg 	       regfile_raw_0, regfile_raw_0_nxt;
+   reg 	       regfile_raw_1, regfile_raw_1_nxt;
+   
+   
+             
+          
+
+   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
+     begin
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[25:21]))
+	  regfile_raw_0_nxt = 1'b1;
+	else
+	  regfile_raw_0_nxt = 1'b0;
+	
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[20:16]))
+	  regfile_raw_1_nxt = 1'b1;
+	else
+	  regfile_raw_1_nxt = 1'b0;
+     end
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_0 or w_result_d or regfile_data_0)
+     if (regfile_raw_0)
+       reg_data_live_0 = w_result_d;
+     else
+       reg_data_live_0 = regfile_data_0;
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_1 or w_result_d or regfile_data_1)
+     if (regfile_raw_1)
+       reg_data_live_1 = w_result_d;
+     else
+       reg_data_live_1 = regfile_data_1;
+   
+   
+     
+
+   always @(posedge clk_i  )
+     if (rst_i ==  1'b1)
+       begin
+	  regfile_raw_0 <= 1'b0;
+	  regfile_raw_1 <= 1'b0;
+	  w_result_d <= 32'b0;
+       end
+     else
+       begin
+	  regfile_raw_0 <= regfile_raw_0_nxt;
+	  regfile_raw_1 <= regfile_raw_1_nxt;
+	  w_result_d <= w_result;
+       end
+   
+   
+      
+
+   
+   lm32_dp_ram
+     #(
+       
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_0
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[25:21]),
+      
+      .rdata_o	(regfile_data_0)
+      );
+
+   lm32_dp_ram
+     #(
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_1
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[20:16]),
+      
+      .rdata_o	(regfile_data_1)
+      );
+ 
+
+
+  
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+   
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+
+
+
+
+
+
+
+
+  
+
+
+assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
+assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
+ 
+
+  
+
+ 
+
+   
+   
+
+
+
+
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w ==  1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w ==  1'b1);
+
+
+always @(*)
+begin
+    if (   (   (x_bypass_enable_x ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_x_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_x_1 ==  1'b1))
+               )
+           )
+        || (   (m_bypass_enable_m ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_m_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_m_1 ==  1'b1))
+               )
+           )
+       )
+        interlock =  1'b1;
+    else
+        interlock =  1'b0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_0 ==  1'b1)        
+        bypass_data_0 = x_result;
+    else if (raw_m_0 ==  1'b1)
+        bypass_data_0 = m_result;
+    else if (raw_w_0 ==  1'b1)
+        bypass_data_0 = w_result;
+    else
+        bypass_data_0 = reg_data_0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_1 ==  1'b1)
+        bypass_data_1 = x_result;
+    else if (raw_m_1 ==  1'b1)
+        bypass_data_1 = m_result;
+    else if (raw_w_1 ==  1'b1)
+        bypass_data_1 = w_result;
+    else
+        bypass_data_1 = reg_data_1;
+end
+
+   
+          
+       
+       
+     
+
+   assign branch_predict_d = bi_unconditional | bi_conditional;
+   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
+   
+   
+   assign branch_target_d = pc_d + branch_offset_d;
+
+   
+   
+   
+   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
+
+
+always @(*)
+begin
+    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
+    case (d_result_sel_1_d)
+     2'b00:      d_result_1 = { 32{1'b0}};
+     2'b01:     d_result_1 = bypass_data_1;
+     2'b10: d_result_1 = immediate_d;
+    default:                        d_result_1 = { 32{1'bx}};
+    endcase
+end
+
+      
+
+   
+   
+
+
+
+  
+
+
+assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
+assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
+assign sext_result_x = size_x ==  2'b00 ? sextb_result_x : sexth_result_x;
+ 
+
+
+  
+
+      
+
+
+
+
+assign cmp_zero = operand_0_x == operand_1_x;
+assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_overflow = adder_overflow_x;
+assign cmp_carry_n = adder_carry_n_x;
+always @(*)
+begin
+    case (condition_x)
+     3'b000:   condition_met_x =  1'b1;
+     3'b110:   condition_met_x =  1'b1;
+     3'b001:    condition_met_x = cmp_zero;
+     3'b111:   condition_met_x = !cmp_zero;
+     3'b010:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+     3'b101:   condition_met_x = cmp_carry_n && !cmp_zero;
+     3'b011:   condition_met_x = cmp_negative == cmp_overflow;
+     3'b100:  condition_met_x = cmp_carry_n;
+    default:              condition_met_x = 1'bx;
+    endcase 
+end
+
+
+always @(*)
+begin
+    x_result =   x_result_sel_add_x ? adder_result_x 
+               : x_result_sel_csr_x ? csr_read_data_x
+  
+
+               : x_result_sel_sext_x ? sext_result_x
+ 
+
+  
+                  
+
+
+  
+                  
+
+
+  
+                  
+
+
+               : logic_result_x;
+end
+
+
+always @(*)
+begin
+    m_result =   m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
+  
+
+               : m_result_sel_shift_m ? shifter_result_m
+ 
+
+               : operand_m; 
+end
+
+
+always @(*)
+begin
+    w_result =    w_result_sel_load_w ? load_data_w
+  
+
+                : w_result_sel_mul_w ? multiplier_result_w
+ 
+
+                : operand_w;
+end
+
+      
+
+          
+                                
+                                     
+                                 
+                                 
+                              
+
+
+
+
+assign branch_taken_m =      (stall_m ==  1'b0) 
+                          && (   (   (branch_m ==  1'b1) 
+                                  && (valid_m ==  1'b1)
+                                  && (   (   (condition_met_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b0)
+					 )
+				      || (   (condition_met_m ==  1'b0)
+					  && (branch_predict_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b1)
+					 )
+				     )
+                                 ) 
+                              || (exception_m ==  1'b1)
+                             );
+
+
+assign branch_mispredict_taken_m =    (condition_met_m ==  1'b0)
+                                   && (branch_predict_m ==  1'b1)
+	   			   && (branch_predict_taken_m ==  1'b1);
+   
+
+assign branch_flushX_m =    (stall_m ==  1'b0)
+                         && (   (   (branch_m ==  1'b1) 
+                                 && (valid_m ==  1'b1)
+			         && (   (condition_met_m ==  1'b1)
+				     || (   (condition_met_m ==  1'b0)
+					 && (branch_predict_m ==  1'b1)
+					 && (branch_predict_taken_m ==  1'b1)
+					)
+				    )
+			        )
+			     || (exception_m ==  1'b1)
+			    );
+
+
+assign kill_f =    (   (valid_d ==  1'b1)
+                    && (branch_predict_taken_d ==  1'b1)
+		   )
+                || (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+
+                || (icache_refill_request ==  1'b1) 
+ 
+
+                  
+                   
+
+
+                ;
+assign kill_d =    (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+
+                || (icache_refill_request ==  1'b1)     
+ 
+                
+                  
+                   
+
+
+                ;
+assign kill_x =    (branch_flushX_m ==  1'b1) 
+                  
+                   
+
+
+                ;
+assign kill_m =     1'b0
+                  
+                   
+
+
+                ;                
+assign kill_w =     1'b0
+                  
+                   
+
+                
+                ;
+
+
+
+  
+
+assign breakpoint_exception =    (   (   (break_x ==  1'b1)
+				      || (bp_match ==  1'b1)
+				     )
+				  && (valid_x ==  1'b1)
+				 )
+  
+
+                              || (jtag_break ==  1'b1)
+ 
+
+                              ;
+ 
+
+
+  
+
+assign watchpoint_exception = wp_match ==  1'b1;
+ 
+
+
+  
+        
+                                             
+                                         
+     
+
+
+
+  
+     
+
+
+
+assign system_call_exception = (   (scall_x ==  1'b1)
+  
+                                   
+
+
+			       );
+
+  
+
+assign debug_exception_x =  (breakpoint_exception ==  1'b1)
+                         || (watchpoint_exception ==  1'b1)
+                         ;
+
+assign non_debug_exception_x = (system_call_exception ==  1'b1)
+  
+
+                            || (reset_exception ==  1'b1)
+ 
+
+  
+                               
+                               
+
+
+  
+                               
+
+
+  
+
+                            || (   (interrupt_exception ==  1'b1)
+  
+
+                                && (dc_ss ==  1'b0)
+ 
+                            
+  
+ 				   
+				   
+
+
+                               )
+ 
+
+                            ;
+
+assign exception_x = (debug_exception_x ==  1'b1) || (non_debug_exception_x ==  1'b1);
+ 
+               
+ 
+                               
+                               
+
+ 
+                               
+
+ 
+                                  
+ 
+                                   
+                            
+ 
+ 				   
+				   
+
+                               
+
+                            
+
+
+
+  
+ 
+
+ 
+  
+      
+   
+      
+
+
+
+
+always @(*)
+begin
+  
+
+  
+
+    if (reset_exception ==  1'b1)
+        eid_x =  3'h0;
+    else
+ 
+     
+  
+            
+          
+    
+
+
+         if (breakpoint_exception ==  1'b1)
+        eid_x =  3'd1;
+    else
+ 
+
+  
+            
+          
+    
+            
+          
+    
+
+
+  
+
+         if (watchpoint_exception ==  1'b1)
+        eid_x =  3'd3;
+    else 
+ 
+
+  
+            
+          
+    
+
+
+  
+
+         if (   (interrupt_exception ==  1'b1)
+  
+
+             && (dc_ss ==  1'b0)
+ 
+                            
+            )
+        eid_x =  3'h6;
+    else
+ 
+
+        eid_x =  3'h7;
+end
+
+
+
+assign stall_a = (stall_f ==  1'b1);
+                
+assign stall_f = (stall_d ==  1'b1);
+                
+assign stall_d =   (stall_x ==  1'b1) 
+                || (   (interlock ==  1'b1)
+                    && (kill_d ==  1'b0)
+                   ) 
+		|| (   (   (eret_d ==  1'b1)
+			|| (scall_d ==  1'b1)
+  
+			   
+
+
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+  
+
+		|| (   (   (break_d ==  1'b1)
+			|| (bret_d ==  1'b1)
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+ 
+                   
+                || (   (csr_write_enable_d ==  1'b1)
+                    && (load_q_x ==  1'b1)
+                   )                      
+  
+                 
+                 
+                       
+		           
+			 
+			
+		    
+
+	
+                ;
+                
+assign stall_x =    (stall_m ==  1'b1)
+  
+                       
+                        
+                     
+
+
+
+	    
+                 ;
+
+assign stall_m =    (stall_wb_load ==  1'b1)
+  
+                    
+
+
+                 || (   (D_CYC_O ==  1'b1)
+                     && (   (store_m ==  1'b1)
+		         
+          
+          
+
+		  
+	 
+	
+
+          
+           
+          
+       
+
+  
+
+		         || ((store_x ==  1'b1) && (interrupt_exception ==  1'b1))
+ 
+
+                         || (load_m ==  1'b1)
+                         || (load_x ==  1'b1)
+                        ) 
+                    ) 
+ 
+                 
+  
+                         
+
+                                    
+  
+
+                 || (icache_stall_request ==  1'b1)     
+                 || ((I_CYC_O ==  1'b1) && ((branch_m ==  1'b1) || (exception_m ==  1'b1))) 
+ 
+ 
+                                
+
+
+                               
+  
+                                  
+                        
+                    
+
+
+  
+                  
+   
+
+                 ;      
+
+
+
+
+  
+         
+
+
+  
+         
+         
+
+
+  
+         
+
+
+  
+         
+         
+
+
+assign q_x = (valid_x ==  1'b1) && (kill_x ==  1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x ==  1'b1) && (q_x ==  1'b1);
+assign eret_q_x = (eret_x ==  1'b1) && (q_x ==  1'b1);
+  
+
+assign bret_q_x = (bret_x ==  1'b1) && (q_x ==  1'b1);
+ 
+
+assign load_q_x = (load_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+
+               && (bp_match ==  1'b0)
+ 
+
+                  ;
+assign store_q_x = (store_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+
+               && (bp_match ==  1'b0)
+ 
+
+                  ;
+  
+         
+
+                              
+assign q_m = (valid_m ==  1'b1) && (kill_m ==  1'b0) && (exception_m ==  1'b0);
+assign load_q_m = (load_m ==  1'b1) && (q_m ==  1'b1);
+assign store_q_m = (store_m ==  1'b1) && (q_m ==  1'b1);
+  
+
+assign debug_exception_q_w = ((debug_exception_w ==  1'b1) && (valid_w ==  1'b1));
+assign non_debug_exception_q_w = ((non_debug_exception_w ==  1'b1) && (valid_w ==  1'b1));        
+ 
+                 
+
+
+
+assign write_enable_q_x = (write_enable_x ==  1'b1) && (valid_x ==  1'b1) && (branch_flushX_m ==  1'b0);
+assign write_enable_q_m = (write_enable_m ==  1'b1) && (valid_m ==  1'b1);
+assign write_enable_q_w = (write_enable_w ==  1'b1) && (valid_w ==  1'b1);
+
+assign reg_write_enable_q_w = (write_enable_w ==  1'b1) && (kill_w ==  1'b0) && (valid_w ==  1'b1);
+
+
+assign cfg = {
+               6'h02,
+              watchpoints[3:0],
+              breakpoints[3:0],
+              interrupts[5:0],
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+ 
+               1'b1
+ 
+              
+
+
+              };
+
+assign cfg2 = {
+		     30'b0,
+  
+		     
+
+
+		      1'b0,
+ 
+
+  
+		     
+
+
+		      1'b0
+ 
+
+		     };
+   
+
+  
+
+assign iflush = (   (csr_write_enable_d ==  1'b1) 
+                 && (csr_d ==  5'h3)
+                 && (stall_d ==  1'b0)
+                 && (kill_d ==  1'b0)
+                 && (valid_d ==  1'b1))
+
+  
+
+             ||
+                (   (jtag_csr_write_enable ==  1'b1)
+		 && (jtag_csr ==  5'h3))
+ 
+
+		 ;
+ 
+ 
+  
+         
+                      
+
+ 
+               
+                       
+		      
+
+		   
+
+ 
+
+
+assign csr_d = read_idx_0_d[ (5-1):0];
+
+
+always @(*)
+begin
+    case (csr_x)
+  
+
+     5'h0,
+     5'h1,
+     5'h2:   csr_read_data_x = interrupt_csr_read_data_x;  
+ 
+
+  
+         
+
+
+     5'h6:  csr_read_data_x = cfg;
+     5'h7:  csr_read_data_x = {eba, 8'h00};
+  
+
+     5'h9: csr_read_data_x = {deba, 8'h00};
+ 
+
+  
+
+     5'he:  csr_read_data_x = jtx_csr_read_data;  
+     5'hf:  csr_read_data_x = jrx_csr_read_data;
+ 
+
+     5'ha: csr_read_data_x = cfg2;
+     5'hb:  csr_read_data_x = sdb_address;
+  
+        
+
+
+      
+      
+    default:        csr_read_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  5'h7) && (stall_x ==  1'b0))
+            eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+  
+
+   
+
+       if ((jtag_csr_write_enable ==  1'b1) && (jtag_csr ==  5'h7))
+         eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+  
+
+   
+              
+           
+ 
+	 
+ 
+
+    end
+end
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  5'h9) && (stall_x ==  1'b0))
+            deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+   
+
+    
+
+       if ((jtag_csr_write_enable ==  1'b1) && (jtag_csr ==  5'h9))
+         deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+   
+
+    
+              
+           
+  
+       
+  
+
+    end
+end
+ 
+
+
+
+  
+   
+
+       
+          
+    
+            
+
+
+
+
+  
+
+   
+
+       
+          
+    
+    
+        
+                
+             
+	     
+	
+        
+               
+              
+    
+
+
+
+ 
+
+
+  
+
+  
+ 
+
+           
+           
+       
+          
+            
+                 
+             
+          
+     
+            
+ 
+
+
+always @(*)
+begin
+    if (icache_refill_request ==  1'b1) 
+        valid_a =  1'b0;
+    else if (icache_restart_request ==  1'b1) 
+        valid_a =  1'b1;
+    else 
+        valid_a = !icache_refilling;
+end 
+ 
+
+ 
+ 
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        valid_f <=  1'b0;
+        valid_d <=  1'b0;
+        valid_x <=  1'b0;
+        valid_m <=  1'b0;
+        valid_w <=  1'b0;
+    end
+    else
+    begin    
+        if ((kill_f ==  1'b1) || (stall_a ==  1'b0))
+  
+
+            valid_f <= valid_a;    
+ 
+              
+
+            
+        else if (stall_f ==  1'b0)
+            valid_f <=  1'b0;            
+
+        if (kill_d ==  1'b1)
+            valid_d <=  1'b0;
+        else if (stall_f ==  1'b0)
+            valid_d <= valid_f & !kill_f;
+        else if (stall_d ==  1'b0)
+            valid_d <=  1'b0;
+       
+        if (stall_d ==  1'b0)
+            valid_x <= valid_d & !kill_d;
+        else if (kill_x ==  1'b1)
+            valid_x <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_x <=  1'b0;
+
+        if (kill_m ==  1'b1)
+            valid_m <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_m <= valid_x & !kill_x;
+        else if (stall_m ==  1'b0)
+            valid_m <=  1'b0;
+
+        if (stall_m ==  1'b0)
+            valid_w <= valid_m & !kill_m;
+        else 
+            valid_w <=  1'b0;        
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+  
+                 
+
+        
+        operand_0_x <= { 32{1'b0}};
+        operand_1_x <= { 32{1'b0}};
+        store_operand_x <= { 32{1'b0}};
+        branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};        
+        x_result_sel_csr_x <=  1'b0;
+  
+          
+
+
+      
+          
+
+
+  
+
+        x_result_sel_sext_x <=  1'b0;
+ 
+    
+  
+          
+
+
+        x_result_sel_add_x <=  1'b0;
+        m_result_sel_compare_x <=  1'b0;
+  
+
+        m_result_sel_shift_x <=  1'b0;
+ 
+    
+        w_result_sel_load_x <=  1'b0;
+  
+
+        w_result_sel_mul_x <=  1'b0;
+ 
+
+        x_bypass_enable_x <=  1'b0;
+        m_bypass_enable_x <=  1'b0;
+        write_enable_x <=  1'b0;
+        write_idx_x <= { 5{1'b0}};
+        csr_x <= { 5{1'b0}};
+        load_x <=  1'b0;
+        store_x <=  1'b0;
+        size_x <= { 2{1'b0}};
+        sign_extend_x <=  1'b0;
+        adder_op_x <=  1'b0;
+        adder_op_x_n <=  1'b0;
+        logic_op_x <= 4'h0;
+  
+
+        direction_x <=  1'b0;
+ 
+
+  
+          
+
+
+
+        branch_x <=  1'b0;
+        branch_predict_x <=  1'b0;
+        branch_predict_taken_x <=  1'b0;
+        condition_x <=  3'b000;
+  
+
+        break_x <=  1'b0;
+ 
+
+        scall_x <=  1'b0;
+        eret_x <=  1'b0;
+  
+
+        bret_x <=  1'b0;
+ 
+
+  
+          
+          
+
+
+        csr_write_enable_x <=  1'b0;
+        operand_m <= { 32{1'b0}};
+        branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        m_result_sel_compare_m <=  1'b0;
+  
+
+        m_result_sel_shift_m <=  1'b0;
+ 
+    
+        w_result_sel_load_m <=  1'b0;
+  
+
+        w_result_sel_mul_m <=  1'b0;
+ 
+
+        m_bypass_enable_m <=  1'b0;
+        branch_m <=  1'b0;
+        branch_predict_m <=  1'b0;
+	branch_predict_taken_m <=  1'b0;
+        exception_m <=  1'b0;
+        load_m <=  1'b0;
+        store_m <=  1'b0;
+        write_enable_m <=  1'b0;            
+        write_idx_m <= { 5{1'b0}};
+        condition_met_m <=  1'b0;
+  
+          
+
+
+  
+
+        debug_exception_m <=  1'b0;
+        non_debug_exception_m <=  1'b0;        
+ 
+
+        operand_w <= { 32{1'b0}};        
+        w_result_sel_load_w <=  1'b0;
+  
+
+        w_result_sel_mul_w <=  1'b0;
+ 
+
+        write_idx_w <= { 5{1'b0}};        
+        write_enable_w <=  1'b0;
+  
+
+        debug_exception_w <=  1'b0;
+        non_debug_exception_w <=  1'b0;        
+ 
+          
+
+
+  
+          
+
+
+    end
+    else
+    begin
+        
+       
+        if (stall_x ==  1'b0)
+        begin
+  
+                     
+
+        
+            operand_0_x <= d_result_0;
+            operand_1_x <= d_result_1;
+            store_operand_x <= bypass_data_1;
+            branch_target_x <= branch_reg_d ==  1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;            
+            x_result_sel_csr_x <= x_result_sel_csr_d;
+  
+              
+
+
+      
+              
+
+
+  
+
+            x_result_sel_sext_x <= x_result_sel_sext_d;
+ 
+    
+  
+              
+
+
+            x_result_sel_add_x <= x_result_sel_add_d;
+            m_result_sel_compare_x <= m_result_sel_compare_d;
+  
+
+            m_result_sel_shift_x <= m_result_sel_shift_d;
+ 
+    
+            w_result_sel_load_x <= w_result_sel_load_d;
+  
+
+            w_result_sel_mul_x <= w_result_sel_mul_d;
+ 
+
+            x_bypass_enable_x <= x_bypass_enable_d;
+            m_bypass_enable_x <= m_bypass_enable_d;
+            load_x <= load_d;
+            store_x <= store_d;
+            branch_x <= branch_d;
+	    branch_predict_x <= branch_predict_d;
+	    branch_predict_taken_x <= branch_predict_taken_d;
+	    write_idx_x <= write_idx_d;
+            csr_x <= csr_d;
+            size_x <= size_d;
+            sign_extend_x <= sign_extend_d;
+            adder_op_x <= adder_op_d;
+            adder_op_x_n <= ~adder_op_d;
+            logic_op_x <= logic_op_d;
+  
+
+            direction_x <= direction_d;
+ 
+
+  
+              
+
+
+            condition_x <= condition_d;
+            csr_write_enable_x <= csr_write_enable_d;
+  
+
+            break_x <= break_d;
+ 
+
+            scall_x <= scall_d;
+  
+              
+
+
+            eret_x <= eret_d;
+  
+
+            bret_x <= bret_d; 
+ 
+
+            write_enable_x <= write_enable_d;
+        end
+        
+        
+
+        if (stall_m ==  1'b0)
+        begin
+            operand_m <= x_result;
+            m_result_sel_compare_m <= m_result_sel_compare_x;
+  
+
+            m_result_sel_shift_m <= m_result_sel_shift_x;
+ 
+    
+            if (exception_x ==  1'b1)
+            begin
+                w_result_sel_load_m <=  1'b0;
+  
+
+                w_result_sel_mul_m <=  1'b0;
+ 
+
+            end
+            else
+            begin
+                w_result_sel_load_m <= w_result_sel_load_x;
+  
+
+                w_result_sel_mul_m <= w_result_sel_mul_x;
+ 
+
+            end
+            m_bypass_enable_m <= m_bypass_enable_x;
+            load_m <= load_x;
+            store_m <= store_x;
+      
+                
+
+
+            branch_m <= branch_x;
+	    branch_predict_m <= branch_predict_x;
+	    branch_predict_taken_m <= branch_predict_taken_x;
+ 
+
+  
+
+	   
+	   
+	   
+	   
+	   
+            if (non_debug_exception_x ==  1'b1) 
+                write_idx_m <=  5'd30;
+            else if (debug_exception_x ==  1'b1)
+                write_idx_m <=  5'd31;
+            else 
+                write_idx_m <= write_idx_x;
+ 
+               
+                  
+             
+                  
+
+
+            condition_met_m <= condition_met_x;
+  
+
+	   if (exception_x ==  1'b1)
+	     if ((dc_re ==  1'b1)
+		 || ((debug_exception_x ==  1'b1) 
+		     && (non_debug_exception_x ==  1'b0)))
+	       branch_target_m <= {deba, eid_x, {3{1'b0}}};
+	     else
+	       branch_target_m <= {eba, eid_x, {3{1'b0}}};
+	   else
+	     branch_target_m <= branch_target_x;
+ 
+                      
+
+
+  
+              
+              
+
+
+  
+              
+
+
+  
+ 
+               
+
+
+
+            write_enable_m <= exception_x ==  1'b1 ?  1'b1 : write_enable_x;            
+  
+
+            debug_exception_m <= debug_exception_x;
+            non_debug_exception_m <= non_debug_exception_x;        
+ 
+
+        end
+        
+        
+        if (stall_m ==  1'b0)
+        begin
+            if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+                exception_m <=  1'b1;
+            else 
+                exception_m <=  1'b0;
+  
+	           
+ 
+					    
+
+					 
+
+
+	end
+                
+        
+  
+                      
+
+
+        operand_w <= exception_m ==  1'b1 ? {pc_m, 2'b00} : m_result;
+ 
+
+        w_result_sel_load_w <= w_result_sel_load_m;
+  
+
+        w_result_sel_mul_w <= w_result_sel_mul_m;
+ 
+
+        write_idx_w <= write_idx_m;
+  
+          
+          
+ 
+           
+
+
+
+        write_enable_w <= write_enable_m;
+  
+
+        debug_exception_w <= debug_exception_m;
+        non_debug_exception_w <= non_debug_exception_m;
+ 
+          
+
+
+  
+              
+                   
+                   
+               
+	   
+            
+
+
+    end
+end
+
+  
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        use_buf <=  1'b0;
+        reg_data_buf_0 <= { 32{1'b0}};
+        reg_data_buf_1 <= { 32{1'b0}};
+    end
+    else
+    begin
+        if (stall_d ==  1'b0)
+            use_buf <=  1'b0;
+        else if (use_buf ==  1'b0)
+        begin        
+            reg_data_buf_0 <= reg_data_live_0;
+            reg_data_buf_1 <= reg_data_live_1;
+            use_buf <=  1'b1;
+        end        
+        if (reg_write_enable_q_w ==  1'b1)
+        begin
+            if (write_idx_w == read_idx_0_d)
+                reg_data_buf_0 <= w_result;
+            if (write_idx_w == read_idx_1_d)
+                reg_data_buf_1 <= w_result;
+        end
+    end
+end
+ 
+
+
+  
+
+ 
+
+   
+
+        
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+     
+           
+            
+        
+
+
+
+
+  
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+ 
+          
+
+          
+    
+    
+    
+          
+        
+ 
+               
+
+           
+
+                
+              
+              
+              
+              
+        
+        
+              
+        
+             
+        
+            
+                 
+            
+                
+                  
+                  
+            
+            
+              
+            
+              
+ 
+              
+
+        
+        
+        
+              
+ 
+              
+
+        
+    
+
+
+
+      
+
+
+
+
+
+        
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_load_store_unit_medium_debug 
+(
+    
+    clk_i,
+    rst_i,
+ 
+    stall_a,
+    stall_x,
+    stall_m,
+    kill_x,
+    kill_m,
+    exception_m,
+    store_operand_x,
+    load_store_address_x,
+    load_store_address_m,
+    load_store_address_w,
+    load_x,
+    store_x,
+    load_q_x,
+    store_q_x,
+    load_q_m,
+    store_q_m,
+    sign_extend_x,
+    size_x,
+  
+    
+
+
+    
+    d_dat_i,
+    d_ack_i,
+    d_err_i,
+    d_rty_i,
+    
+    
+  
+    
+    
+    
+    
+
+    
+  
+    
+    
+    
+    
+    
+    
+    
+
+			     
+    load_data_w,
+    stall_wb_load,
+    
+    d_dat_o,
+    d_adr_o,
+    d_cyc_o,
+    d_sel_o,
+    d_stb_o,
+    d_we_o,
+    d_cti_o,
+    d_lock_o,
+    d_bte_o
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+
+   input clk_i;                                            
+   
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+input kill_x;                                           
+input kill_m;                                           
+input exception_m;                                      
+
+input [ (32-1):0] store_operand_x;                 
+input [ (32-1):0] load_store_address_x;            
+input [ (32-1):0] load_store_address_m;            
+input [1:0] load_store_address_w;                       
+input load_x;                                           
+input store_x;                                          
+input load_q_x;                                         
+input store_q_x;                                        
+input load_q_m;                                         
+input store_q_m;                                        
+input sign_extend_x;                                    
+input [ 1:0] size_x;                          
+
+  
+                                            
+
+
+
+     
+     
+     
+      
+      
+            
+    	 
+   
+
+
+
+   reg 		 [31:0] iram_dat_d0;
+   reg 		 iram_en_d0;
+   wire 	 iram_en;
+   wire [31:0] 	 iram_data;
+   
+   
+   
+input [ (32-1):0] d_dat_i;                         
+input d_ack_i;                                          
+input d_err_i;                                          
+input d_rty_i;                                          
+
+
+
+
+
+  
+                            
+   
+                           
+   
+                             
+   
+ 
+   
+
+
+
+   
+output [ (32-1):0] load_data_w;                    
+reg    [ (32-1):0] load_data_w;
+output stall_wb_load;                                   
+reg    stall_wb_load;
+
+output [ (32-1):0] d_dat_o;                        
+reg    [ (32-1):0] d_dat_o;
+output [ (32-1):0] d_adr_o;                        
+reg    [ (32-1):0] d_adr_o;
+output d_cyc_o;                                         
+reg    d_cyc_o;
+output [ (4-1):0] d_sel_o;                 
+reg    [ (4-1):0] d_sel_o;
+output d_stb_o;                                         
+reg    d_stb_o; 
+output d_we_o;                                          
+reg    d_we_o;
+output [ (3-1):0] d_cti_o;                       
+reg    [ (3-1):0] d_cti_o;
+output d_lock_o;                                        
+reg    d_lock_o;
+output [ (2-1):0] d_bte_o;                       
+wire   [ (2-1):0] d_bte_o;
+
+
+
+
+
+
+reg [ 1:0] size_m;
+reg [ 1:0] size_w;
+reg sign_extend_m;
+reg sign_extend_w;
+reg [ (32-1):0] store_data_x;       
+reg [ (32-1):0] store_data_m;       
+reg [ (4-1):0] byte_enable_x;
+reg [ (4-1):0] byte_enable_m;
+wire [ (32-1):0] data_m;
+reg [ (32-1):0] data_w;
+
+   
+
+  
+                                    
+ 
+                      
+              
+                                 
+                  
+                   
+                                          
+                      
+
+
+  
+                                      
+ 
+                                      
+                    
+                      
+                        
+                  
+
+
+wire wb_select_x;                                       
+  
+                                      
+
+  
+    
+    
+   
+
+
+
+reg wb_select_m;
+reg [ (32-1):0] wb_data_m;                         
+reg wb_load_complete;                                   
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+ 
+              
+                       
+             
+               
+                      
+       
+    
+                      
+                            
+                    
+                    
+                    
+                  
+                  
+                     
+                    
+                 
+            
+               
+                
+                     
+    
+              
+            
+             
+             
+                  
+                  
+    
+
+
+
+
+
+
+
+
+  
+            
+                             
+
+
+
+  
+            
+                             
+
+      
+        
+
+    
+       
+
+   
+
+    
+     
+       
+     
+         
+     
+
+          
+    
+   
+   
+
+
+   
+  
+            
+                               
+ 
+                               
+
+ 
+                               
+
+                     
+
+
+	  
+   assign wb_select_x =     1'b1
+  
+                          
+
+
+  
+                         
+
+
+  
+                         
+
+
+                     ;
+
+
+always @(*)
+begin
+    case (size_x)
+     2'b00:  store_data_x = {4{store_operand_x[7:0]}};
+     2'b11: store_data_x = {2{store_operand_x[15:0]}};
+     2'b10:  store_data_x = store_operand_x;    
+    default:          store_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+always @(*)
+begin
+    casez ({size_x, load_store_address_x[1:0]})
+    { 2'b00, 2'b11}:  byte_enable_x = 4'b0001;
+    { 2'b00, 2'b10}:  byte_enable_x = 4'b0010;
+    { 2'b00, 2'b01}:  byte_enable_x = 4'b0100;
+    { 2'b00, 2'b00}:  byte_enable_x = 4'b1000;
+    { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+    { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+    { 2'b10, 2'b??}:  byte_enable_x = 4'b1111;
+    default:                   byte_enable_x = 4'bxxxx;
+    endcase
+end
+
+  
+      
+            
+
+           
+	                            
+   
+   
+               
+        
+
+
+   
+  
+  
+   
+   
+         
+                    
+                       
+                      
+                        
+                     
+                        
+  
+   
+         
+                    
+                       
+                      
+                      
+  
+ 
+   
+   
+         
+                    
+                       
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+
+   
+   
+   
+         
+                     
+                      
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+    
+   
+         
+                     
+                    
+
+  
+
+   
+   assign data_m = wb_data_m;
+   
+
+  
+
+ 
+
+
+
+always @(*)
+begin
+    casez ({size_w, load_store_address_w[1:0]})
+    { 2'b00, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+    { 2'b00, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+    { 2'b00, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+    { 2'b00, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+    { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+    { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+    { 2'b10, 2'b??}:  load_data_w = data_w;
+    default:                   load_data_w = { 32{1'bx}};
+    endcase
+end
+
+
+assign d_bte_o =  2'b00;
+
+                  
+
+ 
+     
+    
+    
+   
+   
+   
+    
+    
+    
+    
+   
+   
+     
+     
+    
+    
+    
+   
+         
+     
+     
+    
+    
+
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        d_cyc_o <=  1'b0;
+        d_stb_o <=  1'b0;
+        d_dat_o <= { 32{1'b0}};
+        d_adr_o <= { 32{1'b0}};
+        d_sel_o <= { 4{ 1'b0}};
+        d_we_o <=  1'b0;
+        d_cti_o <=  3'b111;
+        d_lock_o <=  1'b0;
+        wb_data_m <= { 32{1'b0}};
+        wb_load_complete <=  1'b0;
+        stall_wb_load <=  1'b0;
+                  
+          
+
+                
+    end
+    else 
+    begin
+   
+        
+          
+
+                
+        
+        if (d_cyc_o ==  1'b1)
+        begin
+            
+            if ((d_ack_i ==  1'b1) || (d_err_i ==  1'b1))
+            begin
+                  
+                     
+                
+                    
+                        
+                
+                
+
+                
+                begin
+                    
+                    d_cyc_o <=  1'b0;
+                    d_stb_o <=  1'b0;
+                    d_lock_o <=  1'b0;
+                end
+      
+                  
+                
+                  
+
+
+                
+                wb_data_m <= d_dat_i;
+                
+                wb_load_complete <= !d_we_o;
+            end
+            
+        end
+        else 
+        begin
+                  
+               
+            
+                
+                  
+                  
+                  
+                                  
+                  
+                  
+                
+            
+             
+
+            
+                 if (   (store_q_m ==  1'b1)
+                     && (stall_m ==  1'b0)
+  
+                        
+
+
+  
+		        
+
+			
+                    )
+            begin
+                
+                d_dat_o <= store_data_m;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b1;
+                d_cti_o <=  3'b111;
+            end        
+            else if (   (load_q_m ==  1'b1) 
+                     && (wb_select_m ==  1'b1) 
+                     && (wb_load_complete ==  1'b0)
+                     
+                    )
+            begin
+                
+                stall_wb_load <=  1'b0;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b0;
+                d_cti_o <=  3'b111;
+            end
+        end
+        
+        if (stall_m ==  1'b0)
+            wb_load_complete <=  1'b0;
+        
+        if ((load_q_x ==  1'b1) && (wb_select_x ==  1'b1) && (stall_x ==  1'b0))
+            stall_wb_load <=  1'b1;
+        
+        if ((kill_m ==  1'b1) || (exception_m ==  1'b1))
+            stall_wb_load <=  1'b0;
+    end
+end
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        sign_extend_m <=  1'b0;
+        size_m <= 2'b00;
+        byte_enable_m <=  1'b0;
+        store_data_m <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+  
+          
+			    
+
+
+        wb_select_m <=  1'b0;        
+    end
+    else
+    begin
+        if (stall_m ==  1'b0)
+        begin
+            sign_extend_m <= sign_extend_x;
+            size_m <= size_x;
+            byte_enable_m <= byte_enable_x;    
+            store_data_m <= store_data_x;
+  
+              
+
+
+  
+              
+
+
+  
+              
+			    
+
+
+            wb_select_m <= wb_select_x;
+        end
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        size_w <= 2'b00;
+        data_w <= { 32{1'b0}};
+        sign_extend_w <=  1'b0;
+    end
+    else
+    begin
+        size_w <= size_m;
+
+  
+         
+
+
+        data_w <= data_m;
+
+        sign_extend_w <= sign_extend_m;
+    end
+end
+
+
+
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_decoder_medium_debug (
+    
+    instruction,
+    
+    d_result_sel_0,
+    d_result_sel_1,        
+    x_result_sel_csr,
+  
+    
+
+    
+      
+    
+
+
+  
+
+    x_result_sel_sext,
+ 
+    
+    x_result_sel_logic,
+  
+    
+
+
+    x_result_sel_add,
+    m_result_sel_compare,
+  
+
+    m_result_sel_shift,  
+ 
+    
+    w_result_sel_load,
+  
+
+    w_result_sel_mul,
+ 
+
+    x_bypass_enable,
+    m_bypass_enable,
+    read_enable_0,
+    read_idx_0,
+    read_enable_1,
+    read_idx_1,
+    write_enable,
+    write_idx,
+    immediate,
+    branch_offset,
+    load,
+    store,
+    size,
+    sign_extend,
+    adder_op,
+    logic_op,
+  
+
+    direction,
+ 
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+
+
+    branch,
+    branch_reg,
+    condition,
+    bi_conditional,
+    bi_unconditional,
+  
+
+    break_opcode,
+ 
+
+    scall,
+    eret,
+  
+
+    bret,
+ 
+
+  
+    
+
+
+    csr_write_enable
+    );
+
+
+
+
+
+input [ (32-1):0] instruction;       
+
+
+
+
+
+output [ 0:0] d_result_sel_0;
+reg    [ 0:0] d_result_sel_0;
+output [ 1:0] d_result_sel_1;
+reg    [ 1:0] d_result_sel_1;
+output x_result_sel_csr;
+reg    x_result_sel_csr;
+  
+ 
+    
+
+
+      
+ 
+    
+
+
+  
+
+output x_result_sel_sext;
+reg    x_result_sel_sext;
+ 
+
+output x_result_sel_logic;
+reg    x_result_sel_logic;
+  
+ 
+    
+
+
+output x_result_sel_add;
+reg    x_result_sel_add;
+output m_result_sel_compare;
+reg    m_result_sel_compare;
+  
+
+output m_result_sel_shift;
+reg    m_result_sel_shift;
+ 
+
+output w_result_sel_load;
+reg    w_result_sel_load;
+  
+
+output w_result_sel_mul;
+reg    w_result_sel_mul;
+ 
+
+output x_bypass_enable;
+wire   x_bypass_enable;
+output m_bypass_enable;
+wire   m_bypass_enable;
+output read_enable_0;
+wire   read_enable_0;
+output [ (5-1):0] read_idx_0;
+wire   [ (5-1):0] read_idx_0;
+output read_enable_1;
+wire   read_enable_1;
+output [ (5-1):0] read_idx_1;
+wire   [ (5-1):0] read_idx_1;
+output write_enable;
+wire   write_enable;
+output [ (5-1):0] write_idx;
+wire   [ (5-1):0] write_idx;
+output [ (32-1):0] immediate;
+wire   [ (32-1):0] immediate;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+wire   [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+output load;
+wire   load;
+output store;
+wire   store;
+output [ 1:0] size;
+wire   [ 1:0] size;
+output sign_extend;
+wire   sign_extend;
+output adder_op;
+wire   adder_op;
+output [ 3:0] logic_op;
+wire   [ 3:0] logic_op;
+  
+
+output direction;
+wire   direction;
+ 
+
+  
+ 
+   
+ 
+   
+
+
+  
+ 
+   
+
+
+  
+ 
+   
+ 
+   
+
+
+output branch;
+wire   branch;
+output branch_reg;
+wire   branch_reg;
+output [ (3-1):0] condition;
+wire   [ (3-1):0] condition;
+output bi_conditional;
+wire bi_conditional;
+output bi_unconditional;
+wire bi_unconditional;
+  
+
+output break_opcode;
+wire   break_opcode;
+ 
+
+output scall;
+wire   scall;
+output eret;
+wire   eret;
+  
+
+output bret;
+wire   bret;
+ 
+
+  
+  
+    
+
+
+output csr_write_enable;
+wire   csr_write_enable;
+
+
+
+
+
+wire [ (32-1):0] extended_immediate;       
+wire [ (32-1):0] high_immediate;           
+wire [ (32-1):0] call_immediate;           
+wire [ (32-1):0] branch_immediate;         
+wire sign_extend_immediate;                     
+wire select_high_immediate;                     
+wire select_call_immediate;                     
+
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+  
+ 
+
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+  
+ 
+
+
+  
+
+wire op_mul;
+ 
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+  
+
+wire op_sextb;
+wire op_sexth;
+ 
+
+wire op_sh;
+  
+
+wire op_sl;
+ 
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+  
+ 
+
+
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+  
+
+wire shift;
+ 
+
+  
+ 
+
+
+  
+
+wire sext;
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+assign op_add    = instruction[ 30:26] ==  5'b01101;
+assign op_and    = instruction[ 30:26] ==  5'b01000;
+assign op_andhi  = instruction[ 31:26] ==  6'b011000;
+assign op_b      = instruction[ 31:26] ==  6'b110000;
+assign op_bi     = instruction[ 31:26] ==  6'b111000;
+assign op_be     = instruction[ 31:26] ==  6'b010001;
+assign op_bg     = instruction[ 31:26] ==  6'b010010;
+assign op_bge    = instruction[ 31:26] ==  6'b010011;
+assign op_bgeu   = instruction[ 31:26] ==  6'b010100;
+assign op_bgu    = instruction[ 31:26] ==  6'b010101;
+assign op_bne    = instruction[ 31:26] ==  6'b010111;
+assign op_call   = instruction[ 31:26] ==  6'b110110;
+assign op_calli  = instruction[ 31:26] ==  6'b111110;
+assign op_cmpe   = instruction[ 30:26] ==  5'b11001;
+assign op_cmpg   = instruction[ 30:26] ==  5'b11010;
+assign op_cmpge  = instruction[ 30:26] ==  5'b11011;
+assign op_cmpgeu = instruction[ 30:26] ==  5'b11100;
+assign op_cmpgu  = instruction[ 30:26] ==  5'b11101;
+assign op_cmpne  = instruction[ 30:26] ==  5'b11111;
+  
+       
+
+
+assign op_lb     = instruction[ 31:26] ==  6'b000100;
+assign op_lbu    = instruction[ 31:26] ==  6'b010000;
+assign op_lh     = instruction[ 31:26] ==  6'b000111;
+assign op_lhu    = instruction[ 31:26] ==  6'b001011;
+assign op_lw     = instruction[ 31:26] ==  6'b001010;
+  
+       
+
+
+  
+
+assign op_mul    = instruction[ 30:26] ==  5'b00010;
+ 
+
+assign op_nor    = instruction[ 30:26] ==  5'b00001;
+assign op_or     = instruction[ 30:26] ==  5'b01110;
+assign op_orhi   = instruction[ 31:26] ==  6'b011110;
+assign op_raise  = instruction[ 31:26] ==  6'b101011;
+assign op_rcsr   = instruction[ 31:26] ==  6'b100100;
+assign op_sb     = instruction[ 31:26] ==  6'b001100;
+  
+
+assign op_sextb  = instruction[ 31:26] ==  6'b101100;
+assign op_sexth  = instruction[ 31:26] ==  6'b110111;
+ 
+
+assign op_sh     = instruction[ 31:26] ==  6'b000011;
+  
+
+assign op_sl     = instruction[ 30:26] ==  5'b01111;      
+ 
+
+assign op_sr     = instruction[ 30:26] ==  5'b00101;
+assign op_sru    = instruction[ 30:26] ==  5'b00000;
+assign op_sub    = instruction[ 31:26] ==  6'b110010;
+assign op_sw     = instruction[ 31:26] ==  6'b010110;
+  
+       
+
+
+assign op_wcsr   = instruction[ 31:26] ==  6'b110100;
+assign op_xnor   = instruction[ 30:26] ==  5'b01001;
+assign op_xor    = instruction[ 30:26] ==  5'b00110;
+
+
+assign arith = op_add | op_sub;
+assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
+assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
+assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
+assign bi_unconditional = op_bi;
+assign bra = op_b | bi_unconditional | bi_conditional;
+assign call = op_call | op_calli;
+  
+
+assign shift = op_sl | op_sr | op_sru;
+ 
+
+  
+     
+
+
+  
+   
+     
+
+
+  
+
+assign sext = op_sextb | op_sexth;
+ 
+
+  
+   
+
+
+  
+    
+   
+
+
+assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
+assign store = op_sb | op_sh | op_sw;
+
+
+always @(*)
+begin
+    
+    if (call) 
+        d_result_sel_0 =  1'b1;
+    else 
+        d_result_sel_0 =  1'b0;
+    if (call) 
+        d_result_sel_1 =  2'b00;         
+    else if ((instruction[31] == 1'b0) && !bra) 
+        d_result_sel_1 =  2'b10;
+    else
+        d_result_sel_1 =  2'b01; 
+    
+    x_result_sel_csr =  1'b0;
+  
+      
+
+
+  
+      
+
+
+  
+
+    x_result_sel_sext =  1'b0;
+ 
+
+    x_result_sel_logic =  1'b0;
+          
+      
+
+
+    x_result_sel_add =  1'b0;
+    if (op_rcsr)
+        x_result_sel_csr =  1'b1;
+      
+ 
+         
+          
+
+ 
+        
+                  
+
+ 
+      
+                      
+
+
+
+  
+      
+                  
+
+
+  
+
+    else if (sext)
+        x_result_sel_sext =  1'b1;
+ 
+        
+    else if (logical) 
+        x_result_sel_logic =  1'b1;
+          
+      
+          
+
+
+    else 
+        x_result_sel_add =  1'b1;        
+    
+    
+
+    m_result_sel_compare = cmp;
+  
+
+    m_result_sel_shift = shift;
+ 
+
+
+    
+    w_result_sel_load = load;
+  
+
+    w_result_sel_mul = op_mul; 
+ 
+
+end
+
+
+assign x_bypass_enable =  arith 
+                        | logical
+  
+                         
+                         
+
+                        
+  
+                         
+
+
+  
+                         
+                         
+
+
+  
+                         
+
+                  
+  
+
+                        | sext 
+ 
+                        
+  
+                         
+
+
+                        | op_rcsr
+                        ;
+
+assign m_bypass_enable = x_bypass_enable 
+  
+
+                        | shift
+ 
+
+                        | cmp
+                        ;
+
+assign read_enable_0 = ~(op_bi | op_calli);
+assign read_idx_0 = instruction[25:21];
+
+assign read_enable_1 = ~(op_bi | op_calli | load);
+assign read_idx_1 = instruction[20:16];
+
+assign write_enable = ~(bra | op_raise | store | op_wcsr);
+assign write_idx = call
+                    ? 5'd29
+                    : instruction[31] == 1'b0 
+                        ? instruction[20:16] 
+                        : instruction[15:11];
+                        
+
+assign size = instruction[27:26];
+
+assign sign_extend = instruction[28];                      
+
+assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
+
+assign logic_op = instruction[29:26];
+  
+
+
+assign direction = instruction[29];
+ 
+
+
+assign branch = bra | call;
+assign branch_reg = op_call | op_b;
+assign condition = instruction[28:26];      
+  
+
+assign break_opcode = op_raise & ~instruction[2];
+ 
+
+assign scall = op_raise & instruction[2];
+assign eret = op_b & (instruction[25:21] == 5'd30);
+  
+
+assign bret = op_b & (instruction[25:21] == 5'd31);
+ 
+
+  
+
+   
+
+
+
+assign csr_write_enable = op_wcsr;
+
+
+
+assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
+assign select_high_immediate = op_andhi | op_orhi;
+assign select_call_immediate = instruction[31];
+
+assign high_immediate = {instruction[15:0], 16'h0000};
+assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
+assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
+assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
+
+assign immediate = select_high_immediate ==  1'b1 
+                        ? high_immediate 
+                        : extended_immediate;
+   
+assign branch_offset = select_call_immediate ==  1'b1   
+                        ? (call_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0])
+                        : (branch_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0]);
+    
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+					  
+  
+
+
+
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+
+
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+
+
+
+
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+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
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+ 
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+ 
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+ 
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+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_icache_medium_debug ( 
+    
+    clk_i,
+    rst_i,    
+    stall_a,
+    stall_f,
+    address_a,
+    address_f,
+    read_enable_f,
+    refill_ready,
+    refill_data,
+    iflush,
+  
+    
+
+
+    valid_d,
+    branch_predict_taken_d,
+    
+    stall_request,
+    restart_request,
+    refill_request,
+    refill_address,
+    refilling,
+    inst
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
+localparam addr_set_width = clogb2(sets)-1;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+localparam addr_set_lsb = (addr_offset_msb+1);
+localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
+localparam addr_tag_lsb = (addr_set_msb+1);
+localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
+
+
+
+
+
+input clk_i;                                        
+input rst_i;                                        
+
+input stall_a;                                      
+input stall_f;                                      
+
+input valid_d;                                      
+input branch_predict_taken_d;                       
+   
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;                     
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;                     
+input read_enable_f;                                
+
+input refill_ready;                                 
+input [ (32-1):0] refill_data;          
+
+input iflush;                                       
+  
+                                      
+
+
+   
+
+
+
+
+output stall_request;                               
+wire   stall_request;
+output restart_request;                             
+reg    restart_request;
+output refill_request;                              
+wire   refill_request;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+output refilling;                                   
+reg    refilling;
+output [ (32-1):0] inst;                
+wire   [ (32-1):0] inst;
+
+
+
+
+
+wire enable;
+wire [0:associativity-1] way_mem_we;
+wire [ (32-1):0] way_data[0:associativity-1];
+wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [0:associativity-1] way_valid;
+wire [0:associativity-1] way_match;
+wire miss;
+
+wire [ (addr_set_width-1):0] tmem_read_address;
+wire [ (addr_set_width-1):0] tmem_write_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
+wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
+
+reg [ 3:0] state;
+wire flushing;
+wire check;
+wire refill;
+
+reg [associativity-1:0] refill_way_select;
+reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
+wire last_refill;
+reg [ (addr_set_width-1):0] flush_set;
+
+genvar i;
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+   generate
+      for (i = 0; i < associativity; i = i + 1)
+	begin : memories
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 (32),
+	       .address_width              ( (addr_offset_width+addr_set_width))
+
+) 
+	   way_0_data_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (dmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (dmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i]),
+	      .write_data                 (refill_data),    
+	      
+	      .read_data                  (way_data[i])
+	      );
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 ( (addr_tag_width+1)),
+	       .address_width              ( addr_set_width)
+
+	       ) 
+	   way_0_tag_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (tmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (tmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i] | flushing),
+	      .write_data                 (tmem_write_data),
+	      
+	      .read_data                  ({way_tag[i], way_valid[i]})
+	      );
+	   
+	end
+endgenerate
+
+
+
+
+
+
+generate
+    for (i = 0; i < associativity; i = i + 1)
+    begin : match
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[ addr_tag_msb:addr_tag_lsb],  1'b1});
+    end
+endgenerate
+
+
+generate
+    if (associativity == 1)
+    begin : inst_1
+assign inst = way_match[0] ? way_data[0] : 32'b0;
+    end
+    else if (associativity == 2)
+	 begin : inst_2
+assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
+    end
+endgenerate
+
+
+generate 
+    if (bytes_per_line > 4)
+assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset};
+    else
+assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb];
+endgenerate
+    
+assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb];
+
+
+assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb];
+assign tmem_write_address = flushing 
+                                ? flush_set
+                                : refill_address[ addr_set_msb:addr_set_lsb];
+
+
+generate 
+    if (bytes_per_line > 4)                            
+assign last_refill = refill_offset == {addr_offset_width{1'b1}};
+    else
+assign last_refill =  1'b1;
+endgenerate
+
+
+assign enable = (stall_a ==  1'b0);
+
+
+generate
+    if (associativity == 1) 
+    begin : we_1     
+assign way_mem_we[0] = (refill_ready ==  1'b1);
+    end
+    else
+    begin : we_2
+assign way_mem_we[0] = (refill_ready ==  1'b1) && (refill_way_select[0] ==  1'b1);
+assign way_mem_we[1] = (refill_ready ==  1'b1) && (refill_way_select[1] ==  1'b1);
+    end
+endgenerate                     
+
+
+assign tmem_write_data[ 0] = last_refill & !flushing;
+assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+
+
+assign flushing = |state[1:0];
+assign check = state[2];
+assign refill = state[3];
+
+assign miss = (~(|way_match)) && (read_enable_f ==  1'b1) && (stall_f ==  1'b0) && !(valid_d && branch_predict_taken_d);
+assign stall_request = (check ==  1'b0);
+assign refill_request = (refill ==  1'b1);
+                      
+
+
+
+
+
+generate
+    if (associativity >= 2) 
+    begin : way_select      
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
+    else
+    begin        
+        if (miss ==  1'b1)
+            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
+    end
+end
+    end
+endgenerate
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refilling <=  1'b0;
+    else
+        refilling <= refill;
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  4'b0001;
+        flush_set <= { addr_set_width{1'b1}};
+        refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+        restart_request <=  1'b0;
+    end
+    else 
+    begin
+        case (state)
+
+        
+         4'b0001:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+                state <=  4'b0100;
+            flush_set <= flush_set - 1'b1;
+        end
+
+        
+         4'b0010:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+  
+	       
+                  
+	      
+
+
+		state <=  4'b0100;
+	   
+            flush_set <= flush_set - 1'b1;
+        end
+        
+        
+         4'b0100:
+        begin            
+            if (stall_a ==  1'b0)
+                restart_request <=  1'b0;
+            if (iflush ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b0010;
+            end
+            else if (miss ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b1000;
+            end
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+            begin
+                if (last_refill ==  1'b1)
+                begin
+                    restart_request <=  1'b1;
+                    state <=  4'b0100;
+                end
+            end
+        end
+
+        endcase        
+    end
+end
+
+generate 
+    if (bytes_per_line > 4)
+    begin
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_offset <= {addr_offset_width{1'b0}};
+    else 
+    begin
+        case (state)
+        
+        
+         4'b0100:
+        begin            
+            if (iflush ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+            else if (miss ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+                refill_offset <= refill_offset + 1'b1;
+        end
+
+        endcase        
+    end
+end
+    end
+endgenerate
+   
+endmodule
+
+ 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+								 
+  
+
+
+
+
+
+
+
+
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+ 
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+  
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+  
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+  
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+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_debug_medium_debug (
+    
+    clk_i, 
+    rst_i,
+    pc_x,
+    load_x,
+    store_x,
+    load_store_address_x,
+    csr_write_enable_x,
+    csr_write_data,
+    csr_x,
+  
+
+  
+
+    jtag_csr_write_enable,
+    jtag_csr_write_data,
+    jtag_csr,
+ 
+
+  
+   
+   
+   
+
+
+  
+
+
+		   
+  
+
+    eret_q_x,
+    bret_q_x,
+    stall_x,
+    exception_x,
+    q_x,
+  
+    
+
+
+ 
+
+
+    
+  
+
+    dc_ss,
+ 
+
+    dc_re,
+    bp_match,
+    wp_match
+    );
+    
+
+
+
+
+parameter breakpoints = 0;                      
+parameter watchpoints = 0;                      
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                      
+input load_x;                                   
+input store_x;                                  
+input [ (32-1):0] load_store_address_x;    
+input csr_write_enable_x;                       
+input [ (32-1):0] csr_write_data;          
+input [ (5-1):0] csr_x;                    
+  
+
+  
+
+input jtag_csr_write_enable;                    
+input [ (32-1):0] jtag_csr_write_data;     
+input [ (5-1):0] jtag_csr;                 
+ 
+
+     
+                          
+            
+                          
+
+
+ 
+
+
+
+  
+
+input eret_q_x;                                 
+input bret_q_x;                                 
+input stall_x;                                  
+input exception_x;                              
+input q_x;                                      
+  
+                     
+
+
+ 
+
+
+
+
+
+
+  
+
+output dc_ss;                                   
+reg    dc_ss;
+ 
+
+output dc_re;                                   
+reg    dc_re;
+output bp_match;                                
+wire   bp_match;        
+output wp_match;                                
+wire   wp_match;
+
+
+
+
+
+genvar i;                                       
+
+
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];       
+reg bp_e[0:breakpoints-1];                      
+wire [0:breakpoints-1]bp_match_n;               
+
+reg [ 1:0] wpc_c[0:watchpoints-1];   
+reg [ (32-1):0] wp[0:watchpoints-1];       
+wire [0:watchpoints-1]wp_match_n;               
+
+wire debug_csr_write_enable;                    
+wire [ (32-1):0] debug_csr_write_data;     
+wire [ (5-1):0] debug_csr;                 
+
+  
+
+
+reg [ 2:0] state;           
+
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+generate
+    for (i = 0; i < breakpoints; i = i + 1)
+    begin : bp_comb
+assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] ==  1'b1));
+    end
+endgenerate
+generate 
+  
+
+    if (breakpoints > 0) 
+assign bp_match = (|bp_match_n) || (state ==  3'b011);
+    else
+assign bp_match = state ==  3'b011;
+ 
+        
+   
+    
+   
+
+
+endgenerate    
+               
+
+generate 
+    for (i = 0; i < watchpoints; i = i + 1)
+    begin : wp_comb
+assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
+    end               
+endgenerate
+generate
+    if (watchpoints > 0) 
+assign wp_match = |wp_match_n;                
+    else
+assign wp_match =  1'b0;
+endgenerate
+                
+  
+                
+
+  
+
+assign debug_csr_write_enable = (csr_write_enable_x ==  1'b1) || (jtag_csr_write_enable ==  1'b1);
+assign debug_csr_write_data = jtag_csr_write_enable ==  1'b1 ? jtag_csr_write_data : csr_write_data;
+assign debug_csr = jtag_csr_write_enable ==  1'b1 ? jtag_csr : csr_x;
+ 
+
+   
+  
+         
+         
+         
+
+
+
+   
+ 
+   
+   
+   
+
+
+
+
+
+
+
+
+generate
+    for (i = 0; i < breakpoints; i = i + 1)
+    begin : bp_seq
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+        bp_e[i] <=  1'b0;
+    end
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h10 + i))
+        begin
+            bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+            bp_e[i] <= debug_csr_write_data[0];
+        end
+    end
+end    
+    end
+endgenerate
+
+
+generate
+    for (i = 0; i < watchpoints; i = i + 1)
+    begin : wp_seq
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        wp[i] <= { 32{1'bx}};
+        wpc_c[i] <=  2'b00;
+    end
+    else
+    begin
+        if (debug_csr_write_enable ==  1'b1)
+        begin
+            if (debug_csr ==  5'h8)
+                wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
+            if (debug_csr ==  5'h18 + i)
+                wp[i] <= debug_csr_write_data;
+        end
+    end  
+end
+    end
+endgenerate
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        dc_re <=  1'b0;
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h8))
+            dc_re <= debug_csr_write_data[1];
+    end
+end    
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  3'b000;
+        dc_ss <=  1'b0;
+    end
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h8))
+        begin
+            dc_ss <= debug_csr_write_data[0];
+            if (debug_csr_write_data[0] ==  1'b0) 
+                state <=  3'b000;
+            else 
+                state <=  3'b001;
+        end
+        case (state)
+         3'b001:
+        begin
+            
+            if (   (   (eret_q_x ==  1'b1)
+                    || (bret_q_x ==  1'b1)
+                    )
+                && (stall_x ==  1'b0)
+               )
+                state <=  3'b010; 
+        end
+         3'b010:
+        begin
+            
+            if ((q_x ==  1'b1) && (stall_x ==  1'b0))
+                state <=  3'b011;
+        end
+         3'b011:
+        begin
+            
+  
+               
+                  
+             
+
+
+                 if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+            begin
+                dc_ss <=  1'b0;
+                state <=  3'b100;
+            end
+        end
+         3'b100:
+        begin
+            
+  
+               
+                  
+             
+
+
+                state <=  3'b000;
+        end
+        endcase
+    end
+end
+ 
+
+
+endmodule
+
+ 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
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+  
+
+ 
+ 
+
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+ 
+
+     
+    
+   
+  
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+ 
+
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+
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+                  
+                    
+                 
+                   
+           
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+                   
+               
+                 
+
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+                      
+                      
+                      
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+ 
+                    
+
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+  
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+
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+           
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+ 
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+ 
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+                    
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+                
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+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_instruction_unit_medium_debug (
+    
+    clk_i,
+    rst_i,
+    
+    stall_a,
+    stall_f,
+    stall_d,
+    stall_x,
+    stall_m,
+    valid_f,
+    valid_d,
+    kill_f,
+    branch_predict_taken_d,
+    branch_predict_address_d,
+      
+    
+    
+
+
+    exception_m,
+    branch_taken_m,
+    branch_mispredict_taken_m,
+    branch_target_m,
+  
+
+    iflush,
+ 
+
+  
+    
+    
+    
+
+        
+  
+
+    
+    i_dat_i,
+    i_ack_i,
+    i_err_i,
+    i_rty_i,
+ 
+
+  
+
+    jtag_read_enable,
+    jtag_write_enable,
+    jtag_write_data,
+    jtag_address,
+ 
+
+    
+    
+    pc_f,
+    pc_d,
+    pc_x,
+    pc_m,
+    pc_w,
+  
+
+    icache_stall_request,
+    icache_restart_request,
+    icache_refill_request,
+    icache_refilling,
+ 
+
+  
+
+    
+    i_dat_o,
+    i_adr_o,
+    i_cyc_o,
+    i_sel_o,
+    i_stb_o,
+    i_we_o,
+    i_cti_o,
+    i_lock_o,
+    i_bte_o,
+ 
+
+  
+    
+    
+    
+
+
+  
+
+    jtag_read_data,
+    jtag_access_complete,
+ 
+
+  
+    
+
+
+  
+
+    instruction_f,
+ 
+    
+    instruction_d
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                   
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam eba_reset_minus_4 = eba_reset - 4;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+  
+  
+   
+        
+   
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_f;                                          
+input stall_d;                                          
+input stall_x;                                          
+input stall_m;                                          
+input valid_f;                                          
+input valid_d;                                          
+input kill_f;                                           
+
+input branch_predict_taken_d;                           
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;          
+   
+      
+                                    
+                     
+
+
+input exception_m;
+input branch_taken_m;                                   
+input branch_mispredict_taken_m;                        
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;                   
+
+  
+
+input iflush;                                           
+ 
+
+  
+                            
+                             
+ 
+
+        
+
+
+  
+
+input [ (32-1):0] i_dat_i;                         
+input i_ack_i;                                          
+input i_err_i;                                          
+input i_rty_i;                                          
+ 
+
+
+  
+
+input jtag_read_enable;                                 
+input jtag_write_enable;                                
+input [ 7:0] jtag_write_data;                 
+input [ (32-1):0] jtag_address;                    
+ 
+
+
+
+
+
+        
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
+  
+
+output icache_stall_request;                            
+wire   icache_stall_request;
+output icache_restart_request;                          
+wire   icache_restart_request;
+output icache_refill_request;                           
+wire   icache_refill_request;
+output icache_refilling;                                
+wire   icache_refilling;
+ 
+
+
+  
+
+output [ (32-1):0] i_dat_o;                        
+  
+
+reg    [ (32-1):0] i_dat_o;
+ 
+    
+
+
+output [ (32-1):0] i_adr_o;                        
+reg    [ (32-1):0] i_adr_o;
+output i_cyc_o;                                         
+reg    i_cyc_o; 
+output [ (4-1):0] i_sel_o;                 
+  
+
+reg    [ (4-1):0] i_sel_o;
+ 
+    
+
+
+output i_stb_o;                                         
+reg    i_stb_o;
+output i_we_o;                                          
+  
+
+reg    i_we_o;
+ 
+   
+
+
+output [ (3-1):0] i_cti_o;                       
+reg    [ (3-1):0] i_cti_o;
+output i_lock_o;                                        
+reg    i_lock_o;
+output [ (2-1):0] i_bte_o;                       
+wire   [ (2-1):0] i_bte_o;
+ 
+
+
+  
+
+output [ 7:0] jtag_read_data;                 
+reg    [ 7:0] jtag_read_data;
+output jtag_access_complete;                            
+wire   jtag_access_complete;
+ 
+
+
+  
+                                      
+    
+
+
+  
+
+output [ (32-1):0] instruction_f;           
+wire   [ (32-1):0] instruction_f;
+ 
+
+output [ (32-1):0] instruction_d;           
+reg    [ (32-1):0] instruction_d;
+
+
+
+
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;                                
+
+  
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;                     
+ 
+
+
+  
+
+wire icache_read_enable_f;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;              
+reg icache_refill_ready;                                
+reg [ (32-1):0] icache_refill_data;         
+wire [ (32-1):0] icache_data_f;             
+wire [ (3-1):0] first_cycle_type;                
+wire [ (3-1):0] next_cycle_type;                 
+wire last_word;                                         
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;                      
+ 
+ 
+                    
+
+
+
+  
+                                      
+    			     
+   
+
+
+  
+
+ 
+               
+
+
+
+   
+  
+   
+    			               
+ 
+
+
+  
+    		       
+
+
+   
+  
+
+reg jtag_access;                                        
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+
+lm32_icache_medium_debug #(
+    .associativity          (associativity),
+    .sets                   (sets),
+    .bytes_per_line         (bytes_per_line),
+    .base_address           (base_address),
+    .limit                  (limit)
+    ) icache ( 
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),      
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .valid_d                (valid_d),
+    .address_a              (pc_a),
+    .address_f              (pc_f),
+    .read_enable_f          (icache_read_enable_f),
+    .refill_ready           (icache_refill_ready),
+    .refill_data            (icache_refill_data),
+    .iflush                 (iflush),
+    
+    .stall_request          (icache_stall_request),
+    .restart_request        (icache_restart_request),
+    .refill_request         (icache_refill_request),
+    .refill_address         (icache_refill_address),
+    .refilling              (icache_refilling),
+    .inst                   (icache_data_f)
+    );
+ 
+
+
+
+
+
+
+  
+
+   
+   assign icache_read_enable_f =    (valid_f ==  1'b1)
+     && (kill_f ==  1'b0)
+   
+      
+ 
+                         
+    
+				       
+ 
+       
+				    ;
+ 
+ 
+
+
+always @(*)
+begin
+    
+  
+       
+          
+     
+
+    
+      if (branch_taken_m ==  1'b1)
+	if ((branch_mispredict_taken_m ==  1'b1) && (exception_m ==  1'b0))
+	  pc_a = pc_x;
+	else
+          pc_a = branch_target_m;
+      
+          
+          
+
+
+      else
+	if ( (valid_d ==  1'b1) && (branch_predict_taken_d ==  1'b1) )
+	  pc_a = branch_predict_address_d;
+	else
+  
+
+          if (icache_restart_request ==  1'b1)
+            pc_a = restart_address;
+	  else 
+ 
+        
+            pc_a = pc_f + 1'b1;
+end
+
+
+  
+      
+      
+        
+
+
+
+  
+
+     
+    	      
+
+     
+      
+	  
+       
+	  
+	
+	    
+     
+   
+   
+          
+
+
+  
+   
+
+
+                     
+
+  
+
+assign instruction_f = icache_data_f;
+ 
+   
+
+
+
+ 
+ 
+   
+
+  
+
+  
+
+ 
+   
+   
+   
+
+
+assign i_bte_o =  2'b00;
+ 
+
+
+  
+
+
+generate
+    case (bytes_per_line)
+    4:
+    begin
+assign first_cycle_type =  3'b111;
+assign next_cycle_type =  3'b111;
+assign last_word =  1'b1;
+assign first_address = icache_refill_address;
+    end
+    8:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type =  3'b111;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    16:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ?  3'b111 :  3'b010;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    endcase
+endgenerate
+ 
+
+                     
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        pc_f <= eba_reset_minus_4[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+        pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    end
+    else
+    begin
+        if (stall_f ==  1'b0)
+            pc_f <= pc_a;
+        if (stall_d ==  1'b0)
+            pc_d <= pc_f;
+        if (stall_x ==  1'b0)
+            pc_x <= pc_d;
+        if (stall_m ==  1'b0)
+            pc_m <= pc_x;
+        pc_w <= pc_m;
+    end
+end
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    else
+    begin
+  
+         
+            
+               
+                  
+                    
+                  
+
+               
+                  
+
+
+
+  
+        
+            if (icache_refill_request ==  1'b1)
+                restart_address <= icache_refill_address;
+ 
+
+ 
+
+    end
+end
+ 
+
+
+
+  
+   
+
+       
+          
+    
+    
+           
+              
+    
+
+
+
+
+  
+
+     
+
+assign jtag_access_complete = (i_cyc_o ==  1'b1) && ((i_ack_i ==  1'b1) || (i_err_i ==  1'b1)) && (jtag_access ==  1'b1);
+always @(*)
+begin
+    case (jtag_address[1:0])
+    2'b00: jtag_read_data = i_dat_i[ 31:24];
+    2'b01: jtag_read_data = i_dat_i[ 23:16];
+    2'b10: jtag_read_data = i_dat_i[ 15:8];
+    2'b11: jtag_read_data = i_dat_i[ 7:0];
+    endcase 
+end
+    
+
+ 
+
+
+  
+
+   
+   
+                
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             i_cyc_o <=  1'b0;
+             i_stb_o <=  1'b0;
+             i_adr_o <= { 32{1'b0}};
+             i_cti_o <=  3'b111;
+             i_lock_o <=  1'b0;
+             icache_refill_data <= { 32{1'b0}};
+             icache_refill_ready <=  1'b0;
+    
+               
+  
+
+    
+
+             i_we_o <=  1'b0;
+             i_sel_o <= 4'b1111;
+             jtag_access <=  1'b0;
+   
+
+	  end
+	else
+	  begin   
+             icache_refill_ready <=  1'b0;
+             
+             if (i_cyc_o ==  1'b1)
+               begin
+		  
+		  if ((i_ack_i ==  1'b1) || (i_err_i ==  1'b1))
+		    begin
+    
+
+                       if (jtag_access ==  1'b1)
+			 begin
+			    i_cyc_o <=  1'b0;
+			    i_stb_o <=  1'b0;       
+			    i_we_o <=  1'b0;  
+			    jtag_access <=  1'b0;    
+			 end
+                       else
+   
+
+			 begin
+			    if (last_word ==  1'b1)
+			      begin
+				 
+				 i_cyc_o <=  1'b0;
+				 i_stb_o <=  1'b0;
+				 i_lock_o <=  1'b0;
+			      end
+			    
+			    i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
+			    i_cti_o <= next_cycle_type;
+			    
+			    icache_refill_ready <=  1'b1;
+			    icache_refill_data <= i_dat_i;
+			 end
+		    end
+    
+		   
+		     
+		    
+                         
+                         
+		    
+		  
+  
+
+               end
+             else
+               begin
+		  if ((icache_refill_request ==  1'b1) && (icache_refill_ready ==  1'b0))
+		    begin
+                       
+    
+     
+                       i_sel_o <= 4'b1111;
+   
+
+                       i_adr_o <= {first_address, 2'b00};
+                       i_cyc_o <=  1'b1;
+                       i_stb_o <=  1'b1;                
+                       i_cti_o <= first_cycle_type;
+                       
+    
+                         
+  
+
+		    end
+    
+
+		  else
+		    begin
+                       if ((jtag_read_enable ==  1'b1) || (jtag_write_enable ==  1'b1))
+			 begin
+			    case (jtag_address[1:0])
+			      2'b00: i_sel_o <= 4'b1000;
+			      2'b01: i_sel_o <= 4'b0100;
+			      2'b10: i_sel_o <= 4'b0010;
+			      2'b11: i_sel_o <= 4'b0001;
+			    endcase
+			    i_adr_o <= jtag_address;
+			    i_dat_o <= {4{jtag_write_data}};
+			    i_cyc_o <=  1'b1;
+			    i_stb_o <=  1'b1;
+			    i_we_o <= jtag_write_enable;
+			    i_cti_o <=  3'b111;
+			    jtag_access <=  1'b1;
+			 end
+		    end 
+   
+                    
+    
+		  
+		  
+        
+		     
+                      
+   
+		     
+                      
+  
+
+               end
+	  end
+     end
+  
+      
+     
+	   
+	  
+               
+               
+               
+               
+               
+               
+   
+               
+  
+	  
+	
+	     
+             
+                
+               
+		  
+		        
+		    
+                       
+                         
+                         
+                       
+                         
+		    
+   
+		   
+		     
+		    
+                         
+                         
+		       
+		    
+		  
+  
+               
+             
+               
+		  
+		         
+    
+			    
+         
+			 
+		    
+                       
+        
+                         
+  
+                          
+                         
+                         
+   
+                         
+  
+		    
+		  
+		    
+	                      
+    
+			         
+         
+			      
+			 
+   
+			      
+  
+			 
+		    
+               
+	  
+     
+ 
+
+ 
+ 
+
+   
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             instruction_d <= { 32{1'b0}};
+  
+               
+
+
+	  end
+	else
+	  begin
+             if (stall_d ==  1'b0)
+               begin
+		  instruction_d <= instruction_f;
+  
+		    
+
+
+               end
+	  end
+     end  
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
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+ 
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+ 
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+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_jtag_medium_debug (
+    
+    clk_i,
+    rst_i,
+    jtag_clk, 
+    jtag_update,
+    jtag_reg_q,
+    jtag_reg_addr_q,
+  
+
+    csr,
+    csr_write_enable,
+    csr_write_data,
+    stall_x,
+ 
+
+  
+
+    jtag_read_data,
+    jtag_access_complete,
+ 
+
+  
+
+    exception_q_w,
+ 
+
+    
+  
+
+    jtx_csr_read_data,
+    jrx_csr_read_data,
+ 
+
+  
+
+    jtag_csr_write_enable,
+    jtag_csr_write_data,
+    jtag_csr,
+    jtag_read_enable,
+    jtag_write_enable,
+    jtag_write_data,
+    jtag_address,
+ 
+
+  
+
+    jtag_break,
+    jtag_reset,
+ 
+
+    jtag_reg_d,
+    jtag_reg_addr_d
+    );
+
+
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input jtag_clk;                                         
+input jtag_update;                                      
+input [ 7:0] jtag_reg_q;                      
+input [2:0] jtag_reg_addr_q;                            
+
+  
+
+input [ (5-1):0] csr;                              
+input csr_write_enable;                                 
+input [ (32-1):0] csr_write_data;                  
+input stall_x;                                          
+ 
+
+  
+
+input [ 7:0] jtag_read_data;                  
+input jtag_access_complete;                             
+ 
+
+  
+
+input exception_q_w;                                    
+ 
+
+
+
+
+
+       
+  
+
+output [ (32-1):0] jtx_csr_read_data;              
+wire   [ (32-1):0] jtx_csr_read_data;
+output [ (32-1):0] jrx_csr_read_data;              
+wire   [ (32-1):0] jrx_csr_read_data;
+ 
+
+  
+
+output jtag_csr_write_enable;                           
+reg    jtag_csr_write_enable;
+output [ (32-1):0] jtag_csr_write_data;            
+wire   [ (32-1):0] jtag_csr_write_data;
+output [ (5-1):0] jtag_csr;                        
+wire   [ (5-1):0] jtag_csr;
+output jtag_read_enable;                                
+reg    jtag_read_enable;
+output jtag_write_enable;                               
+reg    jtag_write_enable;
+output [ 7:0] jtag_write_data;                
+wire   [ 7:0] jtag_write_data;        
+output [ (32-1):0] jtag_address;                   
+wire   [ (32-1):0] jtag_address;
+ 
+
+  
+
+output jtag_break;                                      
+reg    jtag_break;
+output jtag_reset;                                      
+reg    jtag_reset;
+ 
+
+output [ 7:0] jtag_reg_d;
+reg    [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire   [2:0] jtag_reg_addr_d;
+             
+
+
+
+
+reg rx_update;                          
+reg rx_update_r;                        
+reg rx_update_r_r;                      
+reg rx_update_r_r_r;                    
+
+
+
+wire [ 7:0] rx_byte;   
+wire [2:0] rx_addr;
+
+  
+                 
+reg [ 7:0] uart_tx_byte;      
+reg uart_tx_valid;                      
+reg [ 7:0] uart_rx_byte;      
+reg uart_rx_valid;                      
+ 
+
+
+reg [ 3:0] command;             
+  
+
+reg [ 7:0] jtag_byte_0;       
+reg [ 7:0] jtag_byte_1;
+reg [ 7:0] jtag_byte_2;
+reg [ 7:0] jtag_byte_3;
+reg [ 7:0] jtag_byte_4;
+reg processing;                         
+ 
+
+
+reg [ 3:0] state;       
+
+
+
+
+
+  
+
+assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_csr = jtag_byte_4[ (5-1):0];
+assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_write_data = jtag_byte_4;
+ 
+
+                 
+
+  
+                 
+assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};         
+ 
+   
+
+
+  
+
+assign jtag_reg_addr_d[2] = processing;
+ 
+   
+
+
+
+  
+                 
+assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00};
+assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
+ 
+         
+                 
+
+
+
+
+assign rx_byte = jtag_reg_q;
+assign rx_addr = jtag_reg_addr_q;
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        rx_update <= 1'b0;
+        rx_update_r <= 1'b0;
+        rx_update_r_r <= 1'b0;
+        rx_update_r_r_r <= 1'b0;
+    end
+    else
+    begin
+        rx_update <= jtag_update;
+        rx_update_r <= rx_update;
+        rx_update_r_r <= rx_update_r;
+        rx_update_r_r_r <= rx_update_r_r;
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  4'h0;
+        command <= 4'b0000;
+        jtag_reg_d <= 8'h00;
+  
+
+        processing <=  1'b0;
+        jtag_csr_write_enable <=  1'b0;
+        jtag_read_enable <=  1'b0;
+        jtag_write_enable <=  1'b0;
+ 
+
+  
+
+        jtag_break <=  1'b0;
+        jtag_reset <=  1'b0;
+ 
+
+  
+                 
+        uart_tx_byte <= 8'h00;
+        uart_tx_valid <=  1'b0;
+        uart_rx_byte <= 8'h00;
+        uart_rx_valid <=  1'b0;
+ 
+
+    end
+    else
+    begin
+  
+                 
+        if ((csr_write_enable ==  1'b1) && (stall_x ==  1'b0))
+        begin
+            case (csr)
+             5'he:
+            begin
+                
+                uart_tx_byte <= csr_write_data[ 7:0];
+                uart_tx_valid <=  1'b1;
+            end
+             5'hf:
+            begin
+                
+                uart_rx_valid <=  1'b0;
+            end
+            endcase
+        end
+ 
+
+  
+
+        
+        if (exception_q_w ==  1'b1)
+        begin
+            jtag_break <=  1'b0;
+            jtag_reset <=  1'b0;
+        end
+ 
+
+        case (state)
+         4'h0:
+        begin
+            
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                command <= rx_byte[7:4];                
+                case (rx_addr)
+  
+
+                 3'b000:
+                begin
+                    case (rx_byte[7:4])
+  
+
+                     4'b0001:
+                        state <=  4'h1;
+                     4'b0011:
+                    begin
+                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+                        state <=  4'h6;
+                    end
+                     4'b0010:
+                        state <=  4'h1;
+                     4'b0100:
+                    begin
+                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+                        state <= 5;
+                    end
+                     4'b0101:
+                        state <=  4'h1;
+ 
+                    
+                     4'b0110:
+                    begin
+  
+     
+                        uart_rx_valid <=  1'b0;    
+                        uart_tx_valid <=  1'b0;         
+ 
+
+                        jtag_break <=  1'b1;
+                    end
+                     4'b0111:
+                    begin
+  
+     
+                        uart_rx_valid <=  1'b0;    
+                        uart_tx_valid <=  1'b0;         
+ 
+
+                        jtag_reset <=  1'b1;
+                    end
+                    endcase                               
+                end
+ 
+
+  
+                 
+                 3'b001:
+                begin
+                    uart_rx_byte <= rx_byte;
+                    uart_rx_valid <=  1'b1;
+                end                    
+                 3'b010:
+                begin
+                    jtag_reg_d <= uart_tx_byte;
+                    uart_tx_valid <=  1'b0;
+                end
+ 
+
+                default:
+                    ;
+                endcase                
+            end
+        end
+  
+
+         4'h1:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_0 <= rx_byte;
+                state <=  4'h2;
+            end
+        end
+         4'h2:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_1 <= rx_byte;
+                state <=  4'h3;
+            end
+        end
+         4'h3:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_2 <= rx_byte;
+                state <=  4'h4;
+            end
+        end
+         4'h4:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_3 <= rx_byte;
+                if (command ==  4'b0001)
+                    state <=  4'h6;
+                else 
+                    state <=  4'h5;
+            end
+        end
+         4'h5:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_4 <= rx_byte;
+                state <=  4'h6;
+            end
+        end
+         4'h6:
+        begin
+            case (command)
+             4'b0001,
+             4'b0011:
+            begin
+                jtag_read_enable <=  1'b1;
+                processing <=  1'b1;
+                state <=  4'h7;
+            end
+             4'b0010,
+             4'b0100:
+            begin
+                jtag_write_enable <=  1'b1;
+                processing <=  1'b1;
+                state <=  4'h7;
+            end
+             4'b0101:
+            begin
+                jtag_csr_write_enable <=  1'b1;
+                processing <=  1'b1;
+                state <=  4'h8;
+            end
+            endcase
+        end
+         4'h7:
+        begin
+            if (jtag_access_complete ==  1'b1)
+            begin          
+                jtag_read_enable <=  1'b0;
+                jtag_reg_d <= jtag_read_data;
+                jtag_write_enable <=  1'b0;  
+                processing <=  1'b0;
+                state <=  4'h0;
+            end
+        end    
+         4'h8:
+        begin
+            jtag_csr_write_enable <=  1'b0;
+            processing <=  1'b0;
+            state <=  4'h0;
+        end    
+ 
+
+        endcase
+    end
+end
+  
+endmodule
+
+ 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_interrupt_medium_debug (
+    
+    clk_i, 
+    rst_i,
+    
+    interrupt,
+    
+    stall_x,
+  
+
+    non_debug_exception,
+    debug_exception,
+ 
+    
+
+
+    eret_q_x,
+  
+
+    bret_q_x,
+ 
+
+    csr,
+    csr_write_data,
+    csr_write_enable,
+    
+    interrupt_exception,
+    
+    csr_read_data
+    );
+
+
+
+
+
+parameter interrupts =  32;         
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [interrupts-1:0] interrupt;               
+
+input stall_x;                                  
+
+  
+
+input non_debug_exception;                      
+input debug_exception;                          
+ 
+                                 
+
+
+input eret_q_x;                                 
+  
+
+input bret_q_x;                                 
+ 
+
+
+input [ (5-1):0] csr;                      
+input [ (32-1):0] csr_write_data;          
+input csr_write_enable;                         
+
+
+
+
+
+output interrupt_exception;                     
+wire   interrupt_exception;
+
+output [ (32-1):0] csr_read_data;          
+reg    [ (32-1):0] csr_read_data;
+
+
+
+
+
+wire [interrupts-1:0] asserted;                 
+
+wire [interrupts-1:0] interrupt_n_exception;
+
+
+
+reg ie;                                         
+reg eie;                                        
+  
+
+reg bie;                                        
+ 
+
+reg [interrupts-1:0] ip;                        
+reg [interrupts-1:0] im;                        
+
+
+
+
+
+
+assign interrupt_n_exception = ip & im;
+
+
+assign interrupt_exception = (|interrupt_n_exception) & ie;
+
+
+assign asserted = ip | interrupt;
+       
+generate
+    if (interrupts > 1) 
+    begin
+
+always @(*)
+begin
+    case (csr)
+     5'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+
+                                    bie,
+ 
+                                                                         
+
+
+                                    eie, 
+                                    ie
+                                   };
+     5'h2:  csr_read_data = ip;
+     5'h1:  csr_read_data = im;
+    default:       csr_read_data = { 32{1'bx}};
+    endcase
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    case (csr)
+     5'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+
+                                    bie, 
+ 
+                                                                        
+
+
+                                    eie, 
+                                    ie
+                                   };
+     5'h2:  csr_read_data = ip;
+    default:       csr_read_data = { 32{1'bx}};
+      endcase
+end
+    end
+endgenerate
+    
+
+
+
+
+  
+
+   reg [ 10:0] eie_delay  = 0;
+
+   
+generate
+
+   
+    if (interrupts > 1)
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie                   <=  1'b0;
+        eie                  <=  1'b0;
+  
+
+        bie                  <=  1'b0;
+ 
+
+        im                   <= {interrupts{1'b0}};
+        ip                   <= {interrupts{1'b0}};
+       eie_delay             <= 0;
+       
+    end
+    else
+    begin
+        
+        ip                   <= asserted;
+  
+
+        if (non_debug_exception ==  1'b1)
+        begin
+            
+            eie              <= ie;
+            ie               <=  1'b0;
+        end
+        else if (debug_exception ==  1'b1)
+        begin
+            
+            bie              <= ie;
+            ie               <=  1'b0;
+        end
+ 
+           
+        
+            
+                           
+                            
+        
+
+
+        else if (stall_x ==  1'b0)
+        begin
+
+           if(eie_delay[0])
+             ie              <= eie;
+           
+           eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+            if (eret_q_x ==  1'b1) begin
+                
+               eie_delay[ 10] <=  1'b1;
+               eie_delay[ 10-1:0] <= 0;
+            end
+           
+                      
+           
+  
+
+            else if (bret_q_x ==  1'b1)
+                
+                ie      <= bie;
+ 
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  5'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+
+                    bie <= csr_write_data[2];
+ 
+
+                end
+                if (csr ==  5'h1)
+                    im  <= csr_write_data[interrupts-1:0];
+                if (csr ==  5'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+else
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie              <=  1'b0;
+        eie             <=  1'b0;
+  
+
+        bie             <=  1'b0;
+ 
+
+        ip              <= {interrupts{1'b0}};
+       eie_delay        <= 0;
+    end
+    else
+    begin
+        
+        ip              <= asserted;
+  
+
+        if (non_debug_exception ==  1'b1)
+        begin
+            
+            eie         <= ie;
+            ie          <=  1'b0;
+        end
+        else if (debug_exception ==  1'b1)
+        begin
+            
+            bie         <= ie;
+            ie          <=  1'b0;
+        end
+ 
+           
+        
+            
+                      
+                       
+        
+
+
+        else if (stall_x ==  1'b0)
+          begin
+
+             if(eie_delay[0])
+               ie              <= eie;
+           
+             eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+             if (eret_q_x ==  1'b1) begin
+                
+                eie_delay[ 10] <=  1'b1;
+                eie_delay[ 10-1:0] <= 0;
+             end
+           
+  
+
+            else if (bret_q_x ==  1'b1)
+                
+                ie      <= bie;
+ 
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  5'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+
+                    bie <= csr_write_data[2];
+ 
+
+                end
+                if (csr ==  5'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+	 
+	 
+	 
+	 
+	
+
+ 
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+  
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+
+
+  
+
+  
+
+ 
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+ 
+ 
+                    
+
+  
+                    
+
+
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+ 
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+ 
+
+ 
+
+
+
+  
+
+  
+
+  
+ 
+ 
+
+ 
+
+
+ 
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+  
+ 
+
+
+
+
+  
+
+  
+
+ 
+
+  
+ 
+
+
+
+
+  
+
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+                   
+                     
+
+
+  
+                   
+                     
+
+
+  
+
+  
+
+ 
+
+ 
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+                      
+                    
+
+
+  
+
+  
+
+  
+
+  
+                     
+                     
+
+
+  
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+
+ 
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+ 
+
+
+
+
+
+
+
+
+module lm32_top_medium_icache (
+    
+    clk_i,
+    rst_i,
+    
+
+    interrupt,
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+    );
+
+parameter eba_reset = 32'h00000000;
+parameter sdb_address = 32'h00000000;
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+
+input [ (32-1):0] interrupt;          
+
+
+  
+               
+                             
+
+    
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+  
+
+
+
+ 
+  
+
+  
+  
+ 
+  
+  
+ 
+ 
+
+
+
+
+  
+
+                     
+                             
+                            
+                   
+                                 
+ 
+                                 
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+   
+
+lm32_cpu_medium_icache 
+	#(
+		.eba_reset(eba_reset),
+    .sdb_address(sdb_address)
+	) cpu (
+    
+    .clk_i                 (clk_i),
+  
+                   
+
+
+    .rst_i                 (rst_i),
+    
+  
+
+    .interrupt             (interrupt),
+ 
+
+    
+  
+               
+             
+
+     
+  
+    
+                  
+               
+                
+           
+
+
+  
+
+     
+    .I_DAT_I               (I_DAT_I),
+    .I_ACK_I               (I_ACK_I),
+    .I_ERR_I               (I_ERR_I),
+    .I_RTY_I               (I_RTY_I),
+ 
+
+    
+    .D_DAT_I               (D_DAT_I),
+    .D_ACK_I               (D_ACK_I),
+    .D_ERR_I               (D_ERR_I),
+    .D_RTY_I               (D_RTY_I),
+    
+  
+                  
+            
+           
+                 
+                
+ 
+                
+
+
+
+  
+                
+           
+
+
+      
+                
+               
+            
+            
+
+    
+  
+
+    
+    .I_DAT_O               (I_DAT_O),
+    .I_ADR_O               (I_ADR_O),
+    .I_CYC_O               (I_CYC_O),
+    .I_SEL_O               (I_SEL_O),
+    .I_STB_O               (I_STB_O),
+    .I_WE_O                (I_WE_O),
+    .I_CTI_O               (I_CTI_O),
+    .I_LOCK_O              (I_LOCK_O),
+    .I_BTE_O               (I_BTE_O),
+     
+
+    
+    .D_DAT_O               (D_DAT_O),
+    .D_ADR_O               (D_ADR_O),
+    .D_CYC_O               (D_CYC_O),
+    .D_SEL_O               (D_SEL_O),
+    .D_STB_O               (D_STB_O),
+    .D_WE_O                (D_WE_O),
+    .D_CTI_O               (D_CTI_O),
+    .D_LOCK_O              (D_LOCK_O),
+    .D_BTE_O               (D_BTE_O)
+    );
+   
+  		   
+
+  
+    
+                     
+                
+    
+                
+                     
+                
+                      
+                     
+    
+
+        
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+           
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_mc_arithmetic_medium_icache (
+    
+    clk_i,
+    rst_i,
+    stall_d,
+    kill_x,
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+    
+
+
+    operand_0_d,
+    operand_1_d,
+    
+    result_x,
+  
+    
+
+
+    stall_request_x
+    );
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+input stall_d;                                  
+input kill_x;                                   
+  
+                                  
+                                 
+
+
+  
+                                
+
+
+  
+                              
+                             
+                             
+
+
+input [ (32-1):0] operand_0_d;
+input [ (32-1):0] operand_1_d;
+
+
+
+
+
+output [ (32-1):0] result_x;               
+reg    [ (32-1):0] result_x;
+  
+                         
+    
+
+
+output stall_request_x;                         
+wire   stall_request_x;
+
+
+
+
+
+reg [ (32-1):0] p;                         
+reg [ (32-1):0] a;
+reg [ (32-1):0] b;
+  
+  
+
+
+
+reg [ 2:0] state;                 
+reg [5:0] cycles;                               
+
+  
+                               
+                                 
+
+
+
+
+
+
+
+
+assign stall_request_x = state !=  3'b000;
+
+  
+
+      
+
+
+
+  
+
+       
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        cycles <= {6{1'b0}};
+        p <= { 32{1'b0}};
+        a <= { 32{1'b0}};
+        b <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+        result_x <= { 32{1'b0}};
+        state <=  3'b000;
+    end
+    else
+    begin
+  
+          
+
+
+        case (state)
+         3'b000:
+        begin
+            if (stall_d ==  1'b0)                 
+            begin          
+                cycles <=  32;
+                p <= 32'b0;
+                a <= operand_0_d;
+                b <= operand_1_d;                    
+  
+                   
+                      
+                   
+                      
+
+                    
+  
+                   
+                      
+
+
+  
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+
+
+            end            
+        end
+  
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+
+        
+  
+        
+        
+               
+                    
+               
+               
+              
+                   
+                  
+                
+        
+
+     
+  
+        
+               
+               
+              
+                   
+                  
+                
+        
+        
+               
+               
+              
+                   
+                  
+                
+        
+
+   
+        endcase
+    end
+end 
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+  
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+ 
+ 
+
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+
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+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
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+ 
+ 
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+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_cpu_medium_icache (
+    
+    clk_i,
+  
+    
+
+
+    rst_i,
+  
+    
+
+
+  
+   
+   
+   
+   
+   
+   
+
+
+
+    
+  
+
+    interrupt,
+ 
+
+    
+  
+    
+    
+
+     
+  
+    
+    
+     
+    
+    
+
+
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+  
+    
+    
+    
+    
+    
+ 
+    
+
+
+
+  
+    
+    
+
+
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+ 
+  
+    
+    
+    
+    
+    
+    
+    
+    
+           
+
+
+		 
+		 
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+
+		 
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                           
+  
+                            
+
+
+parameter sdb_address =   32'h00000000;
+
+  
+
+parameter icache_associativity =  1;     
+parameter icache_sets =  256;                       
+parameter icache_bytes_per_line =  16;   
+parameter icache_base_address =  32'h0;       
+parameter icache_limit =  32'h7fffffff;                     
+ 
+       
+                         
+     
+         
+                       
+
+
+
+  
+        
+                          
+      
+          
+                        
+
+
+parameter dcache_associativity = 1;    
+parameter dcache_sets = 512;                      
+parameter dcache_bytes_per_line = 16;  
+parameter dcache_base_address = 0;      
+parameter dcache_limit = 0;                    
+ 
+
+
+  
+                          
+
+
+parameter watchpoints = 0;
+ 
+
+  
+                          
+
+
+parameter breakpoints = 0;
+ 
+
+
+  
+
+parameter interrupts =  32;                         
+ 
+   
+
+
+
+
+
+
+
+input clk_i;                                    
+  
+                                   
+
+    
+input rst_i;                                    
+
+  
+
+input [ (32-1):0] interrupt;          
+ 
+
+
+  
+               
+                             
+
+    
+
+   
+                                  
+                               
+                
+  
+
+
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+    
+     
+
+
+   
+   
+  
+                   
+     
+                           
+    
+                          
+    
+                 
+     
+                               
+    
+ 
+                               
+    
+
+
+
+
+  
+  
+    
+  
+    
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+
+  
+      
+     
+       
+      
+             
+
+
+   
+
+
+
+
+
+
+  
+
+reg valid_a;                                    
+ 
+
+reg valid_f;                                    
+reg valid_d;                                    
+reg valid_x;                                    
+reg valid_m;                                    
+reg valid_w;                                    
+   
+wire q_x;
+wire [ (32-1):0] immediate_d;              
+wire load_d;                                    
+reg load_x;                                     
+reg load_m;
+wire load_q_x;
+wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
+wire store_d;                                   
+reg store_x;
+reg store_m;
+wire [ 1:0] size_d;                   
+reg [ 1:0] size_x;
+wire branch_d;                                  
+wire branch_predict_d;                          
+wire branch_predict_taken_d;                    
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;   
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
+wire bi_unconditional;
+wire bi_conditional;
+reg branch_x;                                   
+reg branch_predict_x;
+reg branch_predict_taken_x;
+reg branch_m;
+reg branch_predict_m;
+reg branch_predict_taken_m;
+wire branch_mispredict_taken_m;                 
+wire branch_flushX_m;                           
+wire branch_reg_d;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;            
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;             
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+wire [ 0:0] d_result_sel_0_d; 
+wire [ 1:0] d_result_sel_1_d; 
+
+wire x_result_sel_csr_d;                        
+reg x_result_sel_csr_x;
+  
+ 
+                    
+ 
+
+
+      
+                       
+ 
+
+
+  
+
+wire x_result_sel_sext_d;                       
+reg x_result_sel_sext_x;
+ 
+
+wire x_result_sel_logic_d;                      
+  
+                        
+ 
+
+
+wire x_result_sel_add_d;                        
+reg x_result_sel_add_x;
+wire m_result_sel_compare_d;                    
+reg m_result_sel_compare_x;
+reg m_result_sel_compare_m;
+  
+
+wire m_result_sel_shift_d;                      
+reg m_result_sel_shift_x;
+reg m_result_sel_shift_m;
+ 
+
+wire w_result_sel_load_d;                       
+reg w_result_sel_load_x;
+reg w_result_sel_load_m;
+reg w_result_sel_load_w;
+  
+
+wire w_result_sel_mul_d;                        
+reg w_result_sel_mul_x;
+reg w_result_sel_mul_m;
+reg w_result_sel_mul_w;
+ 
+
+wire x_bypass_enable_d;                         
+reg x_bypass_enable_x;                          
+wire m_bypass_enable_d;                         
+reg m_bypass_enable_x;                          
+reg m_bypass_enable_m;
+wire sign_extend_d;                             
+reg sign_extend_x;
+wire write_enable_d;                            
+reg write_enable_x;
+wire write_enable_q_x;
+reg write_enable_m;
+wire write_enable_q_m;
+reg write_enable_w;
+wire write_enable_q_w;
+wire read_enable_0_d;                           
+wire [ (5-1):0] read_idx_0_d;          
+wire read_enable_1_d;                           
+wire [ (5-1):0] read_idx_1_d;          
+wire [ (5-1):0] write_idx_d;           
+reg [ (5-1):0] write_idx_x;            
+reg [ (5-1):0] write_idx_m;
+reg [ (5-1):0] write_idx_w;
+wire [ (4 -1):0] csr_d;                     
+reg  [ (4 -1):0] csr_x;                  
+wire [ (3-1):0] condition_d;         
+reg [ (3-1):0] condition_x;          
+  
+                                    
+                                     
+
+
+wire scall_d;                                   
+reg scall_x;    
+wire eret_d;                                    
+reg eret_x;
+wire eret_q_x;
+  
+ 
+ 
+
+
+  
+                                     
+ 
+ 
+ 
+ 
+ 
+
+
+
+wire csr_write_enable_d;                        
+reg csr_write_enable_x;
+wire csr_write_enable_q_x;
+  
+       
+
+
+
+  
+                                
+ 
+ 
+  
+
+
+
+reg [ (32-1):0] d_result_0;                
+reg [ (32-1):0] d_result_1;                
+reg [ (32-1):0] x_result;                  
+reg [ (32-1):0] m_result;                  
+reg [ (32-1):0] w_result;                  
+
+reg [ (32-1):0] operand_0_x;               
+reg [ (32-1):0] operand_1_x;               
+reg [ (32-1):0] store_operand_x;           
+reg [ (32-1):0] operand_m;                 
+reg [ (32-1):0] operand_w;                 
+
+
+  
+
+reg [ (32-1):0] reg_data_live_0;          
+reg [ (32-1):0] reg_data_live_1;  
+reg use_buf;                                    
+reg [ (32-1):0] reg_data_buf_0;
+reg [ (32-1):0] reg_data_buf_1;
+ 
+
+  
+
+ 
+     
+
+
+wire [ (32-1):0] reg_data_0;               
+wire [ (32-1):0] reg_data_1;               
+reg [ (32-1):0] bypass_data_0;             
+reg [ (32-1):0] bypass_data_1;             
+wire reg_write_enable_q_w;
+
+reg interlock;                                  
+
+wire stall_a;                                   
+wire stall_f;                                   
+wire stall_d;                                   
+wire stall_x;                                   
+wire stall_m;                                   
+
+
+wire adder_op_d;                                
+reg adder_op_x;                                 
+reg adder_op_x_n;                               
+wire [ (32-1):0] adder_result_x;           
+wire adder_overflow_x;                          
+wire adder_carry_n_x;                           
+
+
+wire [ 3:0] logic_op_d;           
+reg [ 3:0] logic_op_x;            
+wire [ (32-1):0] logic_result_x;           
+
+  
+
+
+wire [ (32-1):0] sextb_result_x;           
+wire [ (32-1):0] sexth_result_x;           
+wire [ (32-1):0] sext_result_x;            
+ 
+
+
+
+  
+
+  
+                                   
+                                     
+
+
+wire direction_d;                               
+reg direction_x;                                        
+wire [ (32-1):0] shifter_result_m;         
+ 
+
+  
+                               
+ 
+                              
+ 
+
+
+  
+           
+
+
+
+
+  
+
+wire [ (32-1):0] multiplier_result_w;      
+ 
+
+  
+                                 
+ 
+
+
+
+
+  
+                                   
+ 
+ 
+ 
+                           
+
+
+
+
+  
+                         
+  
+
+
+
+
+  
+
+wire [ (32-1):0] interrupt_csr_read_data_x;
+ 
+
+wire [ (32-1):0] cfg;                      
+wire [ (32-1):0] cfg2;                     
+  
+                          
+
+
+reg [ (32-1):0] csr_read_data_x;           
+
+
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                       
+  
+                          
+
+
+  
+
+wire [ (32-1):0] instruction_f;     
+ 
+
+
+
+wire [ (32-1):0] instruction_d;     
+  
+
+wire iflush;                                    
+wire icache_stall_request;                      
+wire icache_restart_request;                    
+wire icache_refill_request;                     
+wire icache_refilling;                          
+ 
+
+
+
+  
+                                   
+                                     
+                       
+                     
+                      
+                           
+
+
+wire [ (32-1):0] load_data_w;              
+wire stall_wb_load;                             
+
+
+  
+ 
+          
+          
+
+ 
+                      
+        
+                    
+                           
+  
+ 
+  
+  
+ 
+
+ 
+                                 
+
+
+
+
+
+wire raw_x_0;                                   
+wire raw_x_1;                                   
+wire raw_m_0;                                   
+wire raw_m_1;                                   
+wire raw_w_0;                                   
+wire raw_w_1;                                   
+
+
+wire cmp_zero;                                  
+wire cmp_negative;                              
+wire cmp_overflow;                              
+wire cmp_carry_n;                               
+reg condition_met_x;                            
+reg condition_met_m;
+      
+                             
+
+
+wire branch_taken_m;                            
+
+wire kill_f;                                    
+wire kill_d;                                    
+wire kill_x;                                    
+wire kill_m;                                    
+wire kill_w;                                    
+
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;                 
+  
+                  
+
+
+reg [ (3-1):0] eid_x;                      
+  
+                        
+                        
+
+
+
+  
+ 
+                                      
+
+                                      
+ 
+ 
+                                
+                                 
+                          
+ 
+ 
+ 
+                      
+ 
+ 
+ 
+
+
+wire exception_x;                               
+reg exception_m;
+reg exception_w;
+wire exception_q_w;
+ 
+
+
+  
+  
+                            
+
+ 
+                            
+
+
+
+  
+
+wire interrupt_exception;                       
+ 
+
+  
+                       
+                       
+
+
+  
+     
+   
+            
+                   
+
+
+  
+                   
+
+
+wire system_call_exception;                     
+
+  
+                         
+
+
+
+   
+    
+
+
+     
+  
+                          
+   
+            
+   
+                          
+   
+
+    	      
+    	      
+    	      
+    	      
+    	      
+    	      
+   
+   
+
+
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+lm32_instruction_unit_medium_icache #(
+    .eba_reset              (eba_reset),
+    .associativity          (icache_associativity),
+    .sets                   (icache_sets),
+    .bytes_per_line         (icache_bytes_per_line),
+    .base_address           (icache_base_address),
+    .limit                  (icache_limit)
+  ) instruction_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .stall_d                (stall_d),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .valid_f                (valid_f),
+    .valid_d                (valid_d),
+    .kill_f                 (kill_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .branch_predict_address_d (branch_predict_address_d),
+      
+             
+            
+
+
+    .exception_m            (exception_m),
+    .branch_taken_m         (branch_taken_m),
+    .branch_mispredict_taken_m (branch_mispredict_taken_m),
+    .branch_target_m        (branch_target_m),
+  
+
+    .iflush                 (iflush),
+ 
+
+  
+     
+      
+           
+
+        
+  
+
+    
+    .i_dat_i                (I_DAT_I),
+    .i_ack_i                (I_ACK_I),
+    .i_err_i                (I_ERR_I),
+    .i_rty_i                (I_RTY_I),
+ 
+
+  
+           
+          
+            
+               
+
+
+    
+    
+    .pc_f                   (pc_f),
+    .pc_d                   (pc_d),
+    .pc_x                   (pc_x),
+    .pc_m                   (pc_m),
+    .pc_w                   (pc_w),
+  
+
+    .icache_stall_request   (icache_stall_request),
+    .icache_restart_request (icache_restart_request),
+    .icache_refill_request  (icache_refill_request),
+    .icache_refilling       (icache_refilling),
+ 
+
+  
+
+    
+    .i_dat_o                (I_DAT_O),
+    .i_adr_o                (I_ADR_O),
+    .i_cyc_o                (I_CYC_O),
+    .i_sel_o                (I_SEL_O),
+    .i_stb_o                (I_STB_O),
+    .i_we_o                 (I_WE_O),
+    .i_cti_o                (I_CTI_O),
+    .i_lock_o               (I_LOCK_O),
+    .i_bte_o                (I_BTE_O),
+ 
+ 
+
+  
+    
+    
+    
+
+
+		      	      
+  
+             
+       
+
+
+  
+                
+
+
+  
+
+    .instruction_f          (instruction_f),
+ 
+
+
+		      
+    .instruction_d          (instruction_d)
+
+
+		      
+    );
+
+
+lm32_decoder_medium_icache decoder (
+    
+    .instruction            (instruction_d),
+    
+    .d_result_sel_0         (d_result_sel_0_d),
+    .d_result_sel_1         (d_result_sel_1_d),
+    .x_result_sel_csr       (x_result_sel_csr_d),
+  
+      
+
+
+      
+         
+
+
+  
+
+    .x_result_sel_sext      (x_result_sel_sext_d),
+ 
+    
+    .x_result_sel_logic     (x_result_sel_logic_d),
+  
+          
+
+
+    .x_result_sel_add       (x_result_sel_add_d),
+    .m_result_sel_compare   (m_result_sel_compare_d),
+  
+
+    .m_result_sel_shift     (m_result_sel_shift_d),  
+ 
+    
+    .w_result_sel_load      (w_result_sel_load_d),
+  
+
+    .w_result_sel_mul       (w_result_sel_mul_d),
+ 
+
+    .x_bypass_enable        (x_bypass_enable_d),
+    .m_bypass_enable        (m_bypass_enable_d),
+    .read_enable_0          (read_enable_0_d),
+    .read_idx_0             (read_idx_0_d),
+    .read_enable_1          (read_enable_1_d),
+    .read_idx_1             (read_idx_1_d),
+    .write_enable           (write_enable_d),
+    .write_idx              (write_idx_d),
+    .immediate              (immediate_d),
+    .branch_offset          (branch_offset_d),
+    .load                   (load_d),
+    .store                  (store_d),
+    .size                   (size_d),
+    .sign_extend            (sign_extend_d),
+    .adder_op               (adder_op_d),
+    .logic_op               (logic_op_d),
+  
+
+    .direction              (direction_d),
+ 
+
+  
+                 
+                
+
+
+  
+                   
+
+
+  
+                     
+                    
+
+
+    .branch                 (branch_d),
+    .bi_unconditional       (bi_unconditional),
+    .bi_conditional         (bi_conditional),
+    .branch_reg             (branch_reg_d),
+    .condition              (condition_d),
+  
+               
+
+
+    .scall                  (scall_d),
+    .eret                   (eret_d),
+  
+                       
+
+
+  
+                
+
+
+    .csr_write_enable       (csr_write_enable_d)
+    ); 
+
+
+lm32_load_store_unit_medium_icache #(
+    .associativity          (dcache_associativity),
+    .sets                   (dcache_sets),
+    .bytes_per_line         (dcache_bytes_per_line),
+    .base_address           (dcache_base_address),
+    .limit                  (dcache_limit)
+  ) load_store_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .kill_x                 (kill_x),
+    .kill_m                 (kill_m),
+    .exception_m            (exception_m),
+    .store_operand_x        (store_operand_x),
+    .load_store_address_x   (adder_result_x),
+    .load_store_address_m   (operand_m),
+    .load_store_address_w   (operand_w[1:0]),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_q_x               (load_q_x),
+    .store_q_x              (store_q_x),
+    .load_q_m               (load_q_m),
+    .store_q_m              (store_q_m),
+    .sign_extend_x          (sign_extend_x),
+    .size_x                 (size_x),
+  
+                     
+
+
+
+  
+    
+    
+    
+    
+    
+    
+    
+
+
+		     
+    
+    .d_dat_i                (D_DAT_I),
+    .d_ack_i                (D_ACK_I),
+    .d_err_i                (D_ERR_I),
+    .d_rty_i                (D_RTY_I),
+    
+    
+  
+      
+     
+       
+           
+
+    
+    .load_data_w            (load_data_w),
+    .stall_wb_load          (stall_wb_load),
+    
+    .d_dat_o                (D_DAT_O),
+    .d_adr_o                (D_ADR_O),
+    .d_cyc_o                (D_CYC_O),
+    .d_sel_o                (D_SEL_O),
+    .d_stb_o                (D_STB_O),
+    .d_we_o                 (D_WE_O),
+    .d_cti_o                (D_CTI_O),
+    .d_lock_o               (D_LOCK_O),
+    .d_bte_o                (D_BTE_O)
+    );      
+       
+
+lm32_adder adder (
+    
+    .adder_op_x             (adder_op_x),
+    .adder_op_x_n           (adder_op_x_n),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .adder_result_x         (adder_result_x),
+    .adder_carry_n_x        (adder_carry_n_x),
+    .adder_overflow_x       (adder_overflow_x)
+    );
+
+
+lm32_logic_op logic_op (
+    
+    .logic_op_x             (logic_op_x),
+    .operand_0_x            (operand_0_x),
+
+    .operand_1_x            (operand_1_x),
+    
+    .logic_result_x         (logic_result_x)
+    );
+              
+  
+
+
+lm32_shifter shifter (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .direction_x            (direction_x),
+    .sign_extend_x          (sign_extend_x),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .shifter_result_m       (shifter_result_m)
+    );
+ 
+
+
+  
+
+
+lm32_multiplier multiplier (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .operand_0              (d_result_0),
+    .operand_1              (d_result_1),
+    
+    .result                 (multiplier_result_w)    
+    );
+ 
+
+
+  
+
+  
+    
+                      
+                      
+                    
+                     
+                   
+                   
+                  
+
+         
+                 
+
+ 
+               
+              
+              
+    
+                
+                
+    
+                   
+                   
+           
+
+            
+    
+
+
+              
+  
+
+
+lm32_interrupt_medium_icache interrupt_unit (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    
+    .interrupt              (interrupt),
+    
+    .stall_x                (stall_x),
+  
+         
+            
+
+
+    .exception              (exception_q_w), 
+ 
+
+    .eret_q_x               (eret_q_x),
+  
+                   
+
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    
+    .interrupt_exception    (interrupt_exception),
+    
+    .csr_read_data          (interrupt_csr_read_data_x)
+    );
+ 
+
+
+  
+      
+      
+        
+   
+
+
+
+
+  
+
+  
+    
+                      
+                      
+    
+                   
+                
+                 
+            
+    
+ 
+                        
+             
+           
+                    
+
+ 
+             
+       
+
+ 
+                
+    
+    
+    
+ 
+          
+          
+
+ 
+      
+        
+                   
+           
+          
+            
+               
+
+ 
+                 
+                 
+
+    
+                 
+            
+    
+
+
+
+  
+
+ 
+                
+                
+    
+    
+                       
+                      
+                       
+                     
+                    
+       
+         
+             
+                      
+  
+	       
+      
+        
+                   
+	      
+	       
+      
+        
+                   
+	      
+
+ 
+                   
+                   
+                    
+                
+                        
+ 
+      
+
+
+    
+ 
+                      
+
+                      
+                   
+                   
+    
+
+
+
+
+
+  
+
+   
+           
+            
+          
+            
+
+
+             
+              
+    
+
+   wire [31:0] regfile_data_0, regfile_data_1;
+   reg [31:0]  w_result_d;
+   reg 	       regfile_raw_0, regfile_raw_0_nxt;
+   reg 	       regfile_raw_1, regfile_raw_1_nxt;
+   
+   
+             
+          
+
+   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
+     begin
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[25:21]))
+	  regfile_raw_0_nxt = 1'b1;
+	else
+	  regfile_raw_0_nxt = 1'b0;
+	
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[20:16]))
+	  regfile_raw_1_nxt = 1'b1;
+	else
+	  regfile_raw_1_nxt = 1'b0;
+     end
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_0 or w_result_d or regfile_data_0)
+     if (regfile_raw_0)
+       reg_data_live_0 = w_result_d;
+     else
+       reg_data_live_0 = regfile_data_0;
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_1 or w_result_d or regfile_data_1)
+     if (regfile_raw_1)
+       reg_data_live_1 = w_result_d;
+     else
+       reg_data_live_1 = regfile_data_1;
+   
+   
+     
+
+   always @(posedge clk_i  )
+     if (rst_i ==  1'b1)
+       begin
+	  regfile_raw_0 <= 1'b0;
+	  regfile_raw_1 <= 1'b0;
+	  w_result_d <= 32'b0;
+       end
+     else
+       begin
+	  regfile_raw_0 <= regfile_raw_0_nxt;
+	  regfile_raw_1 <= regfile_raw_1_nxt;
+	  w_result_d <= w_result;
+       end
+   
+   
+      
+
+   
+   lm32_dp_ram
+     #(
+       
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_0
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[25:21]),
+      
+      .rdata_o	(regfile_data_0)
+      );
+
+   lm32_dp_ram
+     #(
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_1
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[20:16]),
+      
+      .rdata_o	(regfile_data_1)
+      );
+ 
+
+
+  
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+   
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+
+
+
+
+
+
+
+
+  
+
+
+assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
+assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
+ 
+
+  
+
+ 
+
+   
+   
+
+
+
+
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w ==  1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w ==  1'b1);
+
+
+always @(*)
+begin
+    if (   (   (x_bypass_enable_x ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_x_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_x_1 ==  1'b1))
+               )
+           )
+        || (   (m_bypass_enable_m ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_m_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_m_1 ==  1'b1))
+               )
+           )
+       )
+        interlock =  1'b1;
+    else
+        interlock =  1'b0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_0 ==  1'b1)        
+        bypass_data_0 = x_result;
+    else if (raw_m_0 ==  1'b1)
+        bypass_data_0 = m_result;
+    else if (raw_w_0 ==  1'b1)
+        bypass_data_0 = w_result;
+    else
+        bypass_data_0 = reg_data_0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_1 ==  1'b1)
+        bypass_data_1 = x_result;
+    else if (raw_m_1 ==  1'b1)
+        bypass_data_1 = m_result;
+    else if (raw_w_1 ==  1'b1)
+        bypass_data_1 = w_result;
+    else
+        bypass_data_1 = reg_data_1;
+end
+
+   
+          
+       
+       
+     
+
+   assign branch_predict_d = bi_unconditional | bi_conditional;
+   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
+   
+   
+   assign branch_target_d = pc_d + branch_offset_d;
+
+   
+   
+   
+   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
+
+
+always @(*)
+begin
+    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
+    case (d_result_sel_1_d)
+     2'b00:      d_result_1 = { 32{1'b0}};
+     2'b01:     d_result_1 = bypass_data_1;
+     2'b10: d_result_1 = immediate_d;
+    default:                        d_result_1 = { 32{1'bx}};
+    endcase
+end
+
+      
+
+   
+   
+
+
+
+  
+
+
+assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
+assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
+assign sext_result_x = size_x ==  2'b00 ? sextb_result_x : sexth_result_x;
+ 
+
+
+  
+
+      
+
+
+
+
+assign cmp_zero = operand_0_x == operand_1_x;
+assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_overflow = adder_overflow_x;
+assign cmp_carry_n = adder_carry_n_x;
+always @(*)
+begin
+    case (condition_x)
+     3'b000:   condition_met_x =  1'b1;
+     3'b110:   condition_met_x =  1'b1;
+     3'b001:    condition_met_x = cmp_zero;
+     3'b111:   condition_met_x = !cmp_zero;
+     3'b010:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+     3'b101:   condition_met_x = cmp_carry_n && !cmp_zero;
+     3'b011:   condition_met_x = cmp_negative == cmp_overflow;
+     3'b100:  condition_met_x = cmp_carry_n;
+    default:              condition_met_x = 1'bx;
+    endcase 
+end
+
+
+always @(*)
+begin
+    x_result =   x_result_sel_add_x ? adder_result_x 
+               : x_result_sel_csr_x ? csr_read_data_x
+  
+
+               : x_result_sel_sext_x ? sext_result_x
+ 
+
+  
+                  
+
+
+  
+                  
+
+
+  
+                  
+
+
+               : logic_result_x;
+end
+
+
+always @(*)
+begin
+    m_result =   m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
+  
+
+               : m_result_sel_shift_m ? shifter_result_m
+ 
+
+               : operand_m; 
+end
+
+
+always @(*)
+begin
+    w_result =    w_result_sel_load_w ? load_data_w
+  
+
+                : w_result_sel_mul_w ? multiplier_result_w
+ 
+
+                : operand_w;
+end
+
+      
+
+          
+                                
+                                     
+                                 
+                                 
+                              
+
+
+
+
+assign branch_taken_m =      (stall_m ==  1'b0) 
+                          && (   (   (branch_m ==  1'b1) 
+                                  && (valid_m ==  1'b1)
+                                  && (   (   (condition_met_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b0)
+					 )
+				      || (   (condition_met_m ==  1'b0)
+					  && (branch_predict_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b1)
+					 )
+				     )
+                                 ) 
+                              || (exception_m ==  1'b1)
+                             );
+
+
+assign branch_mispredict_taken_m =    (condition_met_m ==  1'b0)
+                                   && (branch_predict_m ==  1'b1)
+	   			   && (branch_predict_taken_m ==  1'b1);
+   
+
+assign branch_flushX_m =    (stall_m ==  1'b0)
+                         && (   (   (branch_m ==  1'b1) 
+                                 && (valid_m ==  1'b1)
+			         && (   (condition_met_m ==  1'b1)
+				     || (   (condition_met_m ==  1'b0)
+					 && (branch_predict_m ==  1'b1)
+					 && (branch_predict_taken_m ==  1'b1)
+					)
+				    )
+			        )
+			     || (exception_m ==  1'b1)
+			    );
+
+
+assign kill_f =    (   (valid_d ==  1'b1)
+                    && (branch_predict_taken_d ==  1'b1)
+		   )
+                || (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+
+                || (icache_refill_request ==  1'b1) 
+ 
+
+                  
+                   
+
+
+                ;
+assign kill_d =    (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+
+                || (icache_refill_request ==  1'b1)     
+ 
+                
+                  
+                   
+
+
+                ;
+assign kill_x =    (branch_flushX_m ==  1'b1) 
+                  
+                   
+
+
+                ;
+assign kill_m =     1'b0
+                  
+                   
+
+
+                ;                
+assign kill_w =     1'b0
+                  
+                   
+
+                
+                ;
+
+
+
+  
+              
+				         
+				     
+				     
+				 
+ 
+                                 
+
+                              
+
+
+
+  
+     
+
+
+
+  
+        
+                                             
+                                         
+     
+
+
+
+  
+     
+
+
+
+assign system_call_exception = (   (scall_x ==  1'b1)
+  
+                                   
+
+
+			       );
+
+  
+      
+                            
+                         
+
+     
+ 
+                               
+
+ 
+                               
+                               
+
+ 
+                               
+
+ 
+                                  
+ 
+                                   
+                            
+ 
+ 				   
+				   
+
+                               
+
+                            
+
+         
+
+
+assign exception_x =           (system_call_exception ==  1'b1)
+  
+                               
+                               
+
+
+  
+                               
+
+
+  
+
+                            || (   (interrupt_exception ==  1'b1)
+  
+                                   
+
+                            
+  
+ 				   
+				   
+
+
+                               )
+ 
+
+                            ;
+ 
+
+
+  
+ 
+
+ 
+  
+      
+   
+      
+
+
+
+
+always @(*)
+begin
+  
+ 
+       
+          
+    
+     
+ 
+            
+          
+    
+
+            
+          
+    
+
+
+  
+            
+          
+    
+            
+          
+    
+
+
+  
+            
+          
+     
+
+
+  
+            
+          
+    
+
+
+  
+
+         if (   (interrupt_exception ==  1'b1)
+  
+                
+
+                            
+            )
+        eid_x =  3'h6;
+    else
+ 
+
+        eid_x =  3'h7;
+end
+
+
+
+assign stall_a = (stall_f ==  1'b1);
+                
+assign stall_f = (stall_d ==  1'b1);
+                
+assign stall_d =   (stall_x ==  1'b1) 
+                || (   (interlock ==  1'b1)
+                    && (kill_d ==  1'b0)
+                   ) 
+		|| (   (   (eret_d ==  1'b1)
+			|| (scall_d ==  1'b1)
+  
+			   
+
+
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+  
+		         
+			   
+		       
+		          
+			   
+			   
+			   
+			   
+		       
+                       
+		   
+
+                   
+                || (   (csr_write_enable_d ==  1'b1)
+                    && (load_q_x ==  1'b1)
+                   )                      
+  
+                 
+                 
+                       
+		           
+			 
+			
+		    
+
+	
+                ;
+                
+assign stall_x =    (stall_m ==  1'b1)
+  
+                       
+                        
+                     
+
+
+
+	    
+                 ;
+
+assign stall_m =    (stall_wb_load ==  1'b1)
+  
+                    
+
+
+                 || (   (D_CYC_O ==  1'b1)
+                     && (   (store_m ==  1'b1)
+		         
+          
+          
+
+		  
+	 
+	
+
+          
+           
+          
+       
+
+  
+
+		         || ((store_x ==  1'b1) && (interrupt_exception ==  1'b1))
+ 
+
+                         || (load_m ==  1'b1)
+                         || (load_x ==  1'b1)
+                        ) 
+                    ) 
+ 
+                 
+  
+                         
+
+                                    
+  
+
+                 || (icache_stall_request ==  1'b1)     
+                 || ((I_CYC_O ==  1'b1) && ((branch_m ==  1'b1) || (exception_m ==  1'b1))) 
+ 
+ 
+                                
+
+
+                               
+  
+                                  
+                        
+                    
+
+
+  
+                  
+   
+
+                 ;      
+
+
+
+
+  
+         
+
+
+  
+         
+         
+
+
+  
+         
+
+
+  
+         
+         
+
+
+assign q_x = (valid_x ==  1'b1) && (kill_x ==  1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x ==  1'b1) && (q_x ==  1'b1);
+assign eret_q_x = (eret_x ==  1'b1) && (q_x ==  1'b1);
+  
+         
+
+
+assign load_q_x = (load_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+                  
+
+
+                  ;
+assign store_q_x = (store_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+                  
+
+
+                  ;
+  
+         
+
+                              
+assign q_m = (valid_m ==  1'b1) && (kill_m ==  1'b0) && (exception_m ==  1'b0);
+assign load_q_m = (load_m ==  1'b1) && (q_m ==  1'b1);
+assign store_q_m = (store_m ==  1'b1) && (q_m ==  1'b1);
+  
+         
+                 
+
+
+assign exception_q_w = ((exception_w ==  1'b1) && (valid_w ==  1'b1));        
+ 
+
+
+assign write_enable_q_x = (write_enable_x ==  1'b1) && (valid_x ==  1'b1) && (branch_flushX_m ==  1'b0);
+assign write_enable_q_m = (write_enable_m ==  1'b1) && (valid_m ==  1'b1);
+assign write_enable_q_w = (write_enable_w ==  1'b1) && (valid_w ==  1'b1);
+
+assign reg_write_enable_q_w = (write_enable_w ==  1'b1) && (kill_w ==  1'b0) && (valid_w ==  1'b1);
+
+
+assign cfg = {
+               6'h02,
+              watchpoints[3:0],
+              breakpoints[3:0],
+              interrupts[5:0],
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+ 
+               1'b1
+ 
+              
+
+
+              };
+
+assign cfg2 = {
+		     30'b0,
+  
+		     
+
+
+		      1'b0,
+ 
+
+  
+		     
+
+
+		      1'b0
+ 
+
+		     };
+   
+
+  
+
+assign iflush = (   (csr_write_enable_d ==  1'b1) 
+                 && (csr_d ==  4 'h3)
+                 && (stall_d ==  1'b0)
+                 && (kill_d ==  1'b0)
+                 && (valid_d ==  1'b1))
+
+  
+             
+                     
+		    
+
+
+		 ;
+ 
+ 
+  
+         
+                      
+
+ 
+               
+                       
+		      
+
+		   
+
+ 
+
+
+assign csr_d = read_idx_0_d[ (4 -1):0];
+
+
+always @(*)
+begin
+    case (csr_x)
+  
+
+     4 'h0,
+     4 'h1,
+     4 'h2:   csr_read_data_x = interrupt_csr_read_data_x;  
+ 
+
+  
+         
+
+
+     4 'h6:  csr_read_data_x = cfg;
+     4 'h7:  csr_read_data_x = {eba, 8'h00};
+  
+        
+
+
+  
+          
+        
+
+
+     4 'ha: csr_read_data_x = cfg2;
+     4 'hb:  csr_read_data_x = sdb_address;
+  
+        
+
+
+      
+      
+    default:        csr_read_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  4 'h7) && (stall_x ==  1'b0))
+            eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+  
+  
+              
+           
+ 
+  
+              
+           
+ 	 
+
+
+    end
+end
+
+  
+
+   
+
+       
+          
+    
+    
+                   
+              
+  
+   
+              
+           
+  
+   
+              
+           
+         
+ 
+    
+
+
+
+
+
+  
+   
+
+       
+          
+    
+            
+
+
+
+
+  
+
+   
+
+       
+          
+    
+    
+        
+                
+             
+	     
+	
+        
+               
+              
+    
+
+
+
+ 
+
+
+  
+
+  
+ 
+
+           
+           
+       
+          
+            
+                 
+             
+          
+     
+            
+ 
+
+
+always @(*)
+begin
+    if (icache_refill_request ==  1'b1) 
+        valid_a =  1'b0;
+    else if (icache_restart_request ==  1'b1) 
+        valid_a =  1'b1;
+    else 
+        valid_a = !icache_refilling;
+end 
+ 
+
+ 
+ 
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        valid_f <=  1'b0;
+        valid_d <=  1'b0;
+        valid_x <=  1'b0;
+        valid_m <=  1'b0;
+        valid_w <=  1'b0;
+    end
+    else
+    begin    
+        if ((kill_f ==  1'b1) || (stall_a ==  1'b0))
+  
+
+            valid_f <= valid_a;    
+ 
+              
+
+            
+        else if (stall_f ==  1'b0)
+            valid_f <=  1'b0;            
+
+        if (kill_d ==  1'b1)
+            valid_d <=  1'b0;
+        else if (stall_f ==  1'b0)
+            valid_d <= valid_f & !kill_f;
+        else if (stall_d ==  1'b0)
+            valid_d <=  1'b0;
+       
+        if (stall_d ==  1'b0)
+            valid_x <= valid_d & !kill_d;
+        else if (kill_x ==  1'b1)
+            valid_x <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_x <=  1'b0;
+
+        if (kill_m ==  1'b1)
+            valid_m <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_m <= valid_x & !kill_x;
+        else if (stall_m ==  1'b0)
+            valid_m <=  1'b0;
+
+        if (stall_m ==  1'b0)
+            valid_w <= valid_m & !kill_m;
+        else 
+            valid_w <=  1'b0;        
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+  
+                 
+
+        
+        operand_0_x <= { 32{1'b0}};
+        operand_1_x <= { 32{1'b0}};
+        store_operand_x <= { 32{1'b0}};
+        branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};        
+        x_result_sel_csr_x <=  1'b0;
+  
+          
+
+
+      
+          
+
+
+  
+
+        x_result_sel_sext_x <=  1'b0;
+ 
+    
+  
+          
+
+
+        x_result_sel_add_x <=  1'b0;
+        m_result_sel_compare_x <=  1'b0;
+  
+
+        m_result_sel_shift_x <=  1'b0;
+ 
+    
+        w_result_sel_load_x <=  1'b0;
+  
+
+        w_result_sel_mul_x <=  1'b0;
+ 
+
+        x_bypass_enable_x <=  1'b0;
+        m_bypass_enable_x <=  1'b0;
+        write_enable_x <=  1'b0;
+        write_idx_x <= { 5{1'b0}};
+        csr_x <= { 4 {1'b0}};
+        load_x <=  1'b0;
+        store_x <=  1'b0;
+        size_x <= { 2{1'b0}};
+        sign_extend_x <=  1'b0;
+        adder_op_x <=  1'b0;
+        adder_op_x_n <=  1'b0;
+        logic_op_x <= 4'h0;
+  
+
+        direction_x <=  1'b0;
+ 
+
+  
+          
+
+
+
+        branch_x <=  1'b0;
+        branch_predict_x <=  1'b0;
+        branch_predict_taken_x <=  1'b0;
+        condition_x <=  3'b000;
+  
+          
+
+
+        scall_x <=  1'b0;
+        eret_x <=  1'b0;
+  
+          
+
+
+  
+          
+          
+
+
+        csr_write_enable_x <=  1'b0;
+        operand_m <= { 32{1'b0}};
+        branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        m_result_sel_compare_m <=  1'b0;
+  
+
+        m_result_sel_shift_m <=  1'b0;
+ 
+    
+        w_result_sel_load_m <=  1'b0;
+  
+
+        w_result_sel_mul_m <=  1'b0;
+ 
+
+        m_bypass_enable_m <=  1'b0;
+        branch_m <=  1'b0;
+        branch_predict_m <=  1'b0;
+	branch_predict_taken_m <=  1'b0;
+        exception_m <=  1'b0;
+        load_m <=  1'b0;
+        store_m <=  1'b0;
+        write_enable_m <=  1'b0;            
+        write_idx_m <= { 5{1'b0}};
+        condition_met_m <=  1'b0;
+  
+          
+
+
+  
+          
+                  
+
+
+        operand_w <= { 32{1'b0}};        
+        w_result_sel_load_w <=  1'b0;
+  
+
+        w_result_sel_mul_w <=  1'b0;
+ 
+
+        write_idx_w <= { 5{1'b0}};        
+        write_enable_w <=  1'b0;
+  
+          
+                  
+
+
+        exception_w <=  1'b0;
+ 
+
+  
+          
+
+
+    end
+    else
+    begin
+        
+       
+        if (stall_x ==  1'b0)
+        begin
+  
+                     
+
+        
+            operand_0_x <= d_result_0;
+            operand_1_x <= d_result_1;
+            store_operand_x <= bypass_data_1;
+            branch_target_x <= branch_reg_d ==  1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;            
+            x_result_sel_csr_x <= x_result_sel_csr_d;
+  
+              
+
+
+      
+              
+
+
+  
+
+            x_result_sel_sext_x <= x_result_sel_sext_d;
+ 
+    
+  
+              
+
+
+            x_result_sel_add_x <= x_result_sel_add_d;
+            m_result_sel_compare_x <= m_result_sel_compare_d;
+  
+
+            m_result_sel_shift_x <= m_result_sel_shift_d;
+ 
+    
+            w_result_sel_load_x <= w_result_sel_load_d;
+  
+
+            w_result_sel_mul_x <= w_result_sel_mul_d;
+ 
+
+            x_bypass_enable_x <= x_bypass_enable_d;
+            m_bypass_enable_x <= m_bypass_enable_d;
+            load_x <= load_d;
+            store_x <= store_d;
+            branch_x <= branch_d;
+	    branch_predict_x <= branch_predict_d;
+	    branch_predict_taken_x <= branch_predict_taken_d;
+	    write_idx_x <= write_idx_d;
+            csr_x <= csr_d;
+            size_x <= size_d;
+            sign_extend_x <= sign_extend_d;
+            adder_op_x <= adder_op_d;
+            adder_op_x_n <= ~adder_op_d;
+            logic_op_x <= logic_op_d;
+  
+
+            direction_x <= direction_d;
+ 
+
+  
+              
+
+
+            condition_x <= condition_d;
+            csr_write_enable_x <= csr_write_enable_d;
+  
+              
+
+
+            scall_x <= scall_d;
+  
+              
+
+
+            eret_x <= eret_d;
+  
+               
+
+
+            write_enable_x <= write_enable_d;
+        end
+        
+        
+
+        if (stall_m ==  1'b0)
+        begin
+            operand_m <= x_result;
+            m_result_sel_compare_m <= m_result_sel_compare_x;
+  
+
+            m_result_sel_shift_m <= m_result_sel_shift_x;
+ 
+    
+            if (exception_x ==  1'b1)
+            begin
+                w_result_sel_load_m <=  1'b0;
+  
+
+                w_result_sel_mul_m <=  1'b0;
+ 
+
+            end
+            else
+            begin
+                w_result_sel_load_m <= w_result_sel_load_x;
+  
+
+                w_result_sel_mul_m <= w_result_sel_mul_x;
+ 
+
+            end
+            m_bypass_enable_m <= m_bypass_enable_x;
+            load_m <= load_x;
+            store_m <= store_x;
+      
+                
+
+
+            branch_m <= branch_x;
+	    branch_predict_m <= branch_predict_x;
+	    branch_predict_taken_m <= branch_predict_taken_x;
+ 
+
+  
+	   
+	   
+	   
+	   
+	   
+                
+                  
+                
+                  
+             
+                  
+
+
+            if (exception_x ==  1'b1)
+                write_idx_m <=  5'd30;
+            else 
+                write_idx_m <= write_idx_x;
+ 
+
+            condition_met_m <= condition_met_x;
+  
+	      
+	        
+		     
+		        
+	           
+	     
+	           
+	   
+	       
+
+
+            branch_target_m <= exception_x ==  1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
+ 
+
+  
+              
+              
+
+
+  
+              
+
+
+  
+ 
+               
+
+
+
+            write_enable_m <= exception_x ==  1'b1 ?  1'b1 : write_enable_x;            
+  
+              
+                      
+
+
+        end
+        
+        
+        if (stall_m ==  1'b0)
+        begin
+            if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+                exception_m <=  1'b1;
+            else 
+                exception_m <=  1'b0;
+  
+	           
+ 
+					    
+
+					 
+
+
+	end
+                
+        
+  
+                      
+
+
+        operand_w <= exception_m ==  1'b1 ? {pc_m, 2'b00} : m_result;
+ 
+
+        w_result_sel_load_w <= w_result_sel_load_m;
+  
+
+        w_result_sel_mul_w <= w_result_sel_mul_m;
+ 
+
+        write_idx_w <= write_idx_m;
+  
+          
+          
+ 
+           
+
+
+
+        write_enable_w <= write_enable_m;
+  
+          
+          
+
+
+        exception_w <= exception_m;
+ 
+
+  
+              
+                   
+                   
+               
+	   
+            
+
+
+    end
+end
+
+  
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        use_buf <=  1'b0;
+        reg_data_buf_0 <= { 32{1'b0}};
+        reg_data_buf_1 <= { 32{1'b0}};
+    end
+    else
+    begin
+        if (stall_d ==  1'b0)
+            use_buf <=  1'b0;
+        else if (use_buf ==  1'b0)
+        begin        
+            reg_data_buf_0 <= reg_data_live_0;
+            reg_data_buf_1 <= reg_data_live_1;
+            use_buf <=  1'b1;
+        end        
+        if (reg_write_enable_q_w ==  1'b1)
+        begin
+            if (write_idx_w == read_idx_0_d)
+                reg_data_buf_0 <= w_result;
+            if (write_idx_w == read_idx_1_d)
+                reg_data_buf_1 <= w_result;
+        end
+    end
+end
+ 
+
+
+  
+
+ 
+
+   
+
+        
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+     
+           
+            
+        
+
+
+
+
+  
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+ 
+          
+
+          
+    
+    
+    
+          
+        
+ 
+               
+
+           
+
+                
+              
+              
+              
+              
+        
+        
+              
+        
+             
+        
+            
+                 
+            
+                
+                  
+                  
+            
+            
+              
+            
+              
+ 
+              
+
+        
+        
+        
+              
+ 
+              
+
+        
+    
+
+
+
+      
+
+
+
+
+
+        
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_load_store_unit_medium_icache 
+(
+    
+    clk_i,
+    rst_i,
+ 
+    stall_a,
+    stall_x,
+    stall_m,
+    kill_x,
+    kill_m,
+    exception_m,
+    store_operand_x,
+    load_store_address_x,
+    load_store_address_m,
+    load_store_address_w,
+    load_x,
+    store_x,
+    load_q_x,
+    store_q_x,
+    load_q_m,
+    store_q_m,
+    sign_extend_x,
+    size_x,
+  
+    
+
+
+    
+    d_dat_i,
+    d_ack_i,
+    d_err_i,
+    d_rty_i,
+    
+    
+  
+    
+    
+    
+    
+
+    
+  
+    
+    
+    
+    
+    
+    
+    
+
+			     
+    load_data_w,
+    stall_wb_load,
+    
+    d_dat_o,
+    d_adr_o,
+    d_cyc_o,
+    d_sel_o,
+    d_stb_o,
+    d_we_o,
+    d_cti_o,
+    d_lock_o,
+    d_bte_o
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+
+   input clk_i;                                            
+   
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+input kill_x;                                           
+input kill_m;                                           
+input exception_m;                                      
+
+input [ (32-1):0] store_operand_x;                 
+input [ (32-1):0] load_store_address_x;            
+input [ (32-1):0] load_store_address_m;            
+input [1:0] load_store_address_w;                       
+input load_x;                                           
+input store_x;                                          
+input load_q_x;                                         
+input store_q_x;                                        
+input load_q_m;                                         
+input store_q_m;                                        
+input sign_extend_x;                                    
+input [ 1:0] size_x;                          
+
+  
+                                            
+
+
+
+     
+     
+     
+      
+      
+            
+    	 
+   
+
+
+
+   reg 		 [31:0] iram_dat_d0;
+   reg 		 iram_en_d0;
+   wire 	 iram_en;
+   wire [31:0] 	 iram_data;
+   
+   
+   
+input [ (32-1):0] d_dat_i;                         
+input d_ack_i;                                          
+input d_err_i;                                          
+input d_rty_i;                                          
+
+
+
+
+
+  
+                            
+   
+                           
+   
+                             
+   
+ 
+   
+
+
+
+   
+output [ (32-1):0] load_data_w;                    
+reg    [ (32-1):0] load_data_w;
+output stall_wb_load;                                   
+reg    stall_wb_load;
+
+output [ (32-1):0] d_dat_o;                        
+reg    [ (32-1):0] d_dat_o;
+output [ (32-1):0] d_adr_o;                        
+reg    [ (32-1):0] d_adr_o;
+output d_cyc_o;                                         
+reg    d_cyc_o;
+output [ (4-1):0] d_sel_o;                 
+reg    [ (4-1):0] d_sel_o;
+output d_stb_o;                                         
+reg    d_stb_o; 
+output d_we_o;                                          
+reg    d_we_o;
+output [ (3-1):0] d_cti_o;                       
+reg    [ (3-1):0] d_cti_o;
+output d_lock_o;                                        
+reg    d_lock_o;
+output [ (2-1):0] d_bte_o;                       
+wire   [ (2-1):0] d_bte_o;
+
+
+
+
+
+
+reg [ 1:0] size_m;
+reg [ 1:0] size_w;
+reg sign_extend_m;
+reg sign_extend_w;
+reg [ (32-1):0] store_data_x;       
+reg [ (32-1):0] store_data_m;       
+reg [ (4-1):0] byte_enable_x;
+reg [ (4-1):0] byte_enable_m;
+wire [ (32-1):0] data_m;
+reg [ (32-1):0] data_w;
+
+   
+
+  
+                                    
+ 
+                      
+              
+                                 
+                  
+                   
+                                          
+                      
+
+
+  
+                                      
+ 
+                                      
+                    
+                      
+                        
+                  
+
+
+wire wb_select_x;                                       
+  
+                                      
+
+  
+    
+    
+   
+
+
+
+reg wb_select_m;
+reg [ (32-1):0] wb_data_m;                         
+reg wb_load_complete;                                   
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+ 
+              
+                       
+             
+               
+                      
+       
+    
+                      
+                            
+                    
+                    
+                    
+                  
+                  
+                     
+                    
+                 
+            
+               
+                
+                     
+    
+              
+            
+             
+             
+                  
+                  
+    
+
+
+
+
+
+
+
+
+  
+            
+                             
+
+
+
+  
+            
+                             
+
+      
+        
+
+    
+       
+
+   
+
+    
+     
+       
+     
+         
+     
+
+          
+    
+   
+   
+
+
+   
+  
+            
+                               
+ 
+                               
+
+ 
+                               
+
+                     
+
+
+	  
+   assign wb_select_x =     1'b1
+  
+                          
+
+
+  
+                         
+
+
+  
+                         
+
+
+                     ;
+
+
+always @(*)
+begin
+    case (size_x)
+     2'b00:  store_data_x = {4{store_operand_x[7:0]}};
+     2'b11: store_data_x = {2{store_operand_x[15:0]}};
+     2'b10:  store_data_x = store_operand_x;    
+    default:          store_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+always @(*)
+begin
+    casez ({size_x, load_store_address_x[1:0]})
+    { 2'b00, 2'b11}:  byte_enable_x = 4'b0001;
+    { 2'b00, 2'b10}:  byte_enable_x = 4'b0010;
+    { 2'b00, 2'b01}:  byte_enable_x = 4'b0100;
+    { 2'b00, 2'b00}:  byte_enable_x = 4'b1000;
+    { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+    { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+    { 2'b10, 2'b??}:  byte_enable_x = 4'b1111;
+    default:                   byte_enable_x = 4'bxxxx;
+    endcase
+end
+
+  
+      
+            
+
+           
+	                            
+   
+   
+               
+        
+
+
+   
+  
+  
+   
+   
+         
+                    
+                       
+                      
+                        
+                     
+                        
+  
+   
+         
+                    
+                       
+                      
+                      
+  
+ 
+   
+   
+         
+                    
+                       
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+
+   
+   
+   
+         
+                     
+                      
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+    
+   
+         
+                     
+                    
+
+  
+
+   
+   assign data_m = wb_data_m;
+   
+
+  
+
+ 
+
+
+
+always @(*)
+begin
+    casez ({size_w, load_store_address_w[1:0]})
+    { 2'b00, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+    { 2'b00, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+    { 2'b00, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+    { 2'b00, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+    { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+    { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+    { 2'b10, 2'b??}:  load_data_w = data_w;
+    default:                   load_data_w = { 32{1'bx}};
+    endcase
+end
+
+
+assign d_bte_o =  2'b00;
+
+                  
+
+ 
+     
+    
+    
+   
+   
+   
+    
+    
+    
+    
+   
+   
+     
+     
+    
+    
+    
+   
+         
+     
+     
+    
+    
+
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        d_cyc_o <=  1'b0;
+        d_stb_o <=  1'b0;
+        d_dat_o <= { 32{1'b0}};
+        d_adr_o <= { 32{1'b0}};
+        d_sel_o <= { 4{ 1'b0}};
+        d_we_o <=  1'b0;
+        d_cti_o <=  3'b111;
+        d_lock_o <=  1'b0;
+        wb_data_m <= { 32{1'b0}};
+        wb_load_complete <=  1'b0;
+        stall_wb_load <=  1'b0;
+                  
+          
+
+                
+    end
+    else 
+    begin
+   
+        
+          
+
+                
+        
+        if (d_cyc_o ==  1'b1)
+        begin
+            
+            if ((d_ack_i ==  1'b1) || (d_err_i ==  1'b1))
+            begin
+                  
+                     
+                
+                    
+                        
+                
+                
+
+                
+                begin
+                    
+                    d_cyc_o <=  1'b0;
+                    d_stb_o <=  1'b0;
+                    d_lock_o <=  1'b0;
+                end
+      
+                  
+                
+                  
+
+
+                
+                wb_data_m <= d_dat_i;
+                
+                wb_load_complete <= !d_we_o;
+            end
+            
+        end
+        else 
+        begin
+                  
+               
+            
+                
+                  
+                  
+                  
+                                  
+                  
+                  
+                
+            
+             
+
+            
+                 if (   (store_q_m ==  1'b1)
+                     && (stall_m ==  1'b0)
+  
+                        
+
+
+  
+		        
+
+			
+                    )
+            begin
+                
+                d_dat_o <= store_data_m;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b1;
+                d_cti_o <=  3'b111;
+            end        
+            else if (   (load_q_m ==  1'b1) 
+                     && (wb_select_m ==  1'b1) 
+                     && (wb_load_complete ==  1'b0)
+                     
+                    )
+            begin
+                
+                stall_wb_load <=  1'b0;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b0;
+                d_cti_o <=  3'b111;
+            end
+        end
+        
+        if (stall_m ==  1'b0)
+            wb_load_complete <=  1'b0;
+        
+        if ((load_q_x ==  1'b1) && (wb_select_x ==  1'b1) && (stall_x ==  1'b0))
+            stall_wb_load <=  1'b1;
+        
+        if ((kill_m ==  1'b1) || (exception_m ==  1'b1))
+            stall_wb_load <=  1'b0;
+    end
+end
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        sign_extend_m <=  1'b0;
+        size_m <= 2'b00;
+        byte_enable_m <=  1'b0;
+        store_data_m <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+  
+          
+			    
+
+
+        wb_select_m <=  1'b0;        
+    end
+    else
+    begin
+        if (stall_m ==  1'b0)
+        begin
+            sign_extend_m <= sign_extend_x;
+            size_m <= size_x;
+            byte_enable_m <= byte_enable_x;    
+            store_data_m <= store_data_x;
+  
+              
+
+
+  
+              
+
+
+  
+              
+			    
+
+
+            wb_select_m <= wb_select_x;
+        end
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        size_w <= 2'b00;
+        data_w <= { 32{1'b0}};
+        sign_extend_w <=  1'b0;
+    end
+    else
+    begin
+        size_w <= size_m;
+
+  
+         
+
+
+        data_w <= data_m;
+
+        sign_extend_w <= sign_extend_m;
+    end
+end
+
+
+
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_decoder_medium_icache (
+    
+    instruction,
+    
+    d_result_sel_0,
+    d_result_sel_1,        
+    x_result_sel_csr,
+  
+    
+
+    
+      
+    
+
+
+  
+
+    x_result_sel_sext,
+ 
+    
+    x_result_sel_logic,
+  
+    
+
+
+    x_result_sel_add,
+    m_result_sel_compare,
+  
+
+    m_result_sel_shift,  
+ 
+    
+    w_result_sel_load,
+  
+
+    w_result_sel_mul,
+ 
+
+    x_bypass_enable,
+    m_bypass_enable,
+    read_enable_0,
+    read_idx_0,
+    read_enable_1,
+    read_idx_1,
+    write_enable,
+    write_idx,
+    immediate,
+    branch_offset,
+    load,
+    store,
+    size,
+    sign_extend,
+    adder_op,
+    logic_op,
+  
+
+    direction,
+ 
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+
+
+    branch,
+    branch_reg,
+    condition,
+    bi_conditional,
+    bi_unconditional,
+  
+    
+
+
+    scall,
+    eret,
+  
+    
+
+
+  
+    
+
+
+    csr_write_enable
+    );
+
+
+
+
+
+input [ (32-1):0] instruction;       
+
+
+
+
+
+output [ 0:0] d_result_sel_0;
+reg    [ 0:0] d_result_sel_0;
+output [ 1:0] d_result_sel_1;
+reg    [ 1:0] d_result_sel_1;
+output x_result_sel_csr;
+reg    x_result_sel_csr;
+  
+ 
+    
+
+
+      
+ 
+    
+
+
+  
+
+output x_result_sel_sext;
+reg    x_result_sel_sext;
+ 
+
+output x_result_sel_logic;
+reg    x_result_sel_logic;
+  
+ 
+    
+
+
+output x_result_sel_add;
+reg    x_result_sel_add;
+output m_result_sel_compare;
+reg    m_result_sel_compare;
+  
+
+output m_result_sel_shift;
+reg    m_result_sel_shift;
+ 
+
+output w_result_sel_load;
+reg    w_result_sel_load;
+  
+
+output w_result_sel_mul;
+reg    w_result_sel_mul;
+ 
+
+output x_bypass_enable;
+wire   x_bypass_enable;
+output m_bypass_enable;
+wire   m_bypass_enable;
+output read_enable_0;
+wire   read_enable_0;
+output [ (5-1):0] read_idx_0;
+wire   [ (5-1):0] read_idx_0;
+output read_enable_1;
+wire   read_enable_1;
+output [ (5-1):0] read_idx_1;
+wire   [ (5-1):0] read_idx_1;
+output write_enable;
+wire   write_enable;
+output [ (5-1):0] write_idx;
+wire   [ (5-1):0] write_idx;
+output [ (32-1):0] immediate;
+wire   [ (32-1):0] immediate;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+wire   [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+output load;
+wire   load;
+output store;
+wire   store;
+output [ 1:0] size;
+wire   [ 1:0] size;
+output sign_extend;
+wire   sign_extend;
+output adder_op;
+wire   adder_op;
+output [ 3:0] logic_op;
+wire   [ 3:0] logic_op;
+  
+
+output direction;
+wire   direction;
+ 
+
+  
+ 
+   
+ 
+   
+
+
+  
+ 
+   
+
+
+  
+ 
+   
+ 
+   
+
+
+output branch;
+wire   branch;
+output branch_reg;
+wire   branch_reg;
+output [ (3-1):0] condition;
+wire   [ (3-1):0] condition;
+output bi_conditional;
+wire bi_conditional;
+output bi_unconditional;
+wire bi_unconditional;
+  
+ 
+   
+
+
+output scall;
+wire   scall;
+output eret;
+wire   eret;
+  
+ 
+   
+
+
+  
+  
+    
+
+
+output csr_write_enable;
+wire   csr_write_enable;
+
+
+
+
+
+wire [ (32-1):0] extended_immediate;       
+wire [ (32-1):0] high_immediate;           
+wire [ (32-1):0] call_immediate;           
+wire [ (32-1):0] branch_immediate;         
+wire sign_extend_immediate;                     
+wire select_high_immediate;                     
+wire select_call_immediate;                     
+
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+  
+ 
+
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+  
+ 
+
+
+  
+
+wire op_mul;
+ 
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+  
+
+wire op_sextb;
+wire op_sexth;
+ 
+
+wire op_sh;
+  
+
+wire op_sl;
+ 
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+  
+ 
+
+
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+  
+
+wire shift;
+ 
+
+  
+ 
+
+
+  
+
+wire sext;
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+assign op_add    = instruction[ 30:26] ==  5'b01101;
+assign op_and    = instruction[ 30:26] ==  5'b01000;
+assign op_andhi  = instruction[ 31:26] ==  6'b011000;
+assign op_b      = instruction[ 31:26] ==  6'b110000;
+assign op_bi     = instruction[ 31:26] ==  6'b111000;
+assign op_be     = instruction[ 31:26] ==  6'b010001;
+assign op_bg     = instruction[ 31:26] ==  6'b010010;
+assign op_bge    = instruction[ 31:26] ==  6'b010011;
+assign op_bgeu   = instruction[ 31:26] ==  6'b010100;
+assign op_bgu    = instruction[ 31:26] ==  6'b010101;
+assign op_bne    = instruction[ 31:26] ==  6'b010111;
+assign op_call   = instruction[ 31:26] ==  6'b110110;
+assign op_calli  = instruction[ 31:26] ==  6'b111110;
+assign op_cmpe   = instruction[ 30:26] ==  5'b11001;
+assign op_cmpg   = instruction[ 30:26] ==  5'b11010;
+assign op_cmpge  = instruction[ 30:26] ==  5'b11011;
+assign op_cmpgeu = instruction[ 30:26] ==  5'b11100;
+assign op_cmpgu  = instruction[ 30:26] ==  5'b11101;
+assign op_cmpne  = instruction[ 30:26] ==  5'b11111;
+  
+       
+
+
+assign op_lb     = instruction[ 31:26] ==  6'b000100;
+assign op_lbu    = instruction[ 31:26] ==  6'b010000;
+assign op_lh     = instruction[ 31:26] ==  6'b000111;
+assign op_lhu    = instruction[ 31:26] ==  6'b001011;
+assign op_lw     = instruction[ 31:26] ==  6'b001010;
+  
+       
+
+
+  
+
+assign op_mul    = instruction[ 30:26] ==  5'b00010;
+ 
+
+assign op_nor    = instruction[ 30:26] ==  5'b00001;
+assign op_or     = instruction[ 30:26] ==  5'b01110;
+assign op_orhi   = instruction[ 31:26] ==  6'b011110;
+assign op_raise  = instruction[ 31:26] ==  6'b101011;
+assign op_rcsr   = instruction[ 31:26] ==  6'b100100;
+assign op_sb     = instruction[ 31:26] ==  6'b001100;
+  
+
+assign op_sextb  = instruction[ 31:26] ==  6'b101100;
+assign op_sexth  = instruction[ 31:26] ==  6'b110111;
+ 
+
+assign op_sh     = instruction[ 31:26] ==  6'b000011;
+  
+
+assign op_sl     = instruction[ 30:26] ==  5'b01111;      
+ 
+
+assign op_sr     = instruction[ 30:26] ==  5'b00101;
+assign op_sru    = instruction[ 30:26] ==  5'b00000;
+assign op_sub    = instruction[ 31:26] ==  6'b110010;
+assign op_sw     = instruction[ 31:26] ==  6'b010110;
+  
+       
+
+
+assign op_wcsr   = instruction[ 31:26] ==  6'b110100;
+assign op_xnor   = instruction[ 30:26] ==  5'b01001;
+assign op_xor    = instruction[ 30:26] ==  5'b00110;
+
+
+assign arith = op_add | op_sub;
+assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
+assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
+assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
+assign bi_unconditional = op_bi;
+assign bra = op_b | bi_unconditional | bi_conditional;
+assign call = op_call | op_calli;
+  
+
+assign shift = op_sl | op_sr | op_sru;
+ 
+
+  
+     
+
+
+  
+   
+     
+
+
+  
+
+assign sext = op_sextb | op_sexth;
+ 
+
+  
+   
+
+
+  
+    
+   
+
+
+assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
+assign store = op_sb | op_sh | op_sw;
+
+
+always @(*)
+begin
+    
+    if (call) 
+        d_result_sel_0 =  1'b1;
+    else 
+        d_result_sel_0 =  1'b0;
+    if (call) 
+        d_result_sel_1 =  2'b00;         
+    else if ((instruction[31] == 1'b0) && !bra) 
+        d_result_sel_1 =  2'b10;
+    else
+        d_result_sel_1 =  2'b01; 
+    
+    x_result_sel_csr =  1'b0;
+  
+      
+
+
+  
+      
+
+
+  
+
+    x_result_sel_sext =  1'b0;
+ 
+
+    x_result_sel_logic =  1'b0;
+          
+      
+
+
+    x_result_sel_add =  1'b0;
+    if (op_rcsr)
+        x_result_sel_csr =  1'b1;
+      
+ 
+         
+          
+
+ 
+        
+                  
+
+ 
+      
+                      
+
+
+
+  
+      
+                  
+
+
+  
+
+    else if (sext)
+        x_result_sel_sext =  1'b1;
+ 
+        
+    else if (logical) 
+        x_result_sel_logic =  1'b1;
+          
+      
+          
+
+
+    else 
+        x_result_sel_add =  1'b1;        
+    
+    
+
+    m_result_sel_compare = cmp;
+  
+
+    m_result_sel_shift = shift;
+ 
+
+
+    
+    w_result_sel_load = load;
+  
+
+    w_result_sel_mul = op_mul; 
+ 
+
+end
+
+
+assign x_bypass_enable =  arith 
+                        | logical
+  
+                         
+                         
+
+                        
+  
+                         
+
+
+  
+                         
+                         
+
+
+  
+                         
+
+                  
+  
+
+                        | sext 
+ 
+                        
+  
+                         
+
+
+                        | op_rcsr
+                        ;
+
+assign m_bypass_enable = x_bypass_enable 
+  
+
+                        | shift
+ 
+
+                        | cmp
+                        ;
+
+assign read_enable_0 = ~(op_bi | op_calli);
+assign read_idx_0 = instruction[25:21];
+
+assign read_enable_1 = ~(op_bi | op_calli | load);
+assign read_idx_1 = instruction[20:16];
+
+assign write_enable = ~(bra | op_raise | store | op_wcsr);
+assign write_idx = call
+                    ? 5'd29
+                    : instruction[31] == 1'b0 
+                        ? instruction[20:16] 
+                        : instruction[15:11];
+                        
+
+assign size = instruction[27:26];
+
+assign sign_extend = instruction[28];                      
+
+assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
+
+assign logic_op = instruction[29:26];
+  
+
+
+assign direction = instruction[29];
+ 
+
+
+assign branch = bra | call;
+assign branch_reg = op_call | op_b;
+assign condition = instruction[28:26];      
+  
+     
+
+
+assign scall = op_raise & instruction[2];
+assign eret = op_b & (instruction[25:21] == 5'd30);
+  
+       
+
+
+  
+
+   
+
+
+
+assign csr_write_enable = op_wcsr;
+
+
+
+assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
+assign select_high_immediate = op_andhi | op_orhi;
+assign select_call_immediate = instruction[31];
+
+assign high_immediate = {instruction[15:0], 16'h0000};
+assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
+assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
+assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
+
+assign immediate = select_high_immediate ==  1'b1 
+                        ? high_immediate 
+                        : extended_immediate;
+   
+assign branch_offset = select_call_immediate ==  1'b1   
+                        ? (call_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0])
+                        : (branch_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0]);
+    
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_icache_medium_icache ( 
+    
+    clk_i,
+    rst_i,    
+    stall_a,
+    stall_f,
+    address_a,
+    address_f,
+    read_enable_f,
+    refill_ready,
+    refill_data,
+    iflush,
+  
+    
+
+
+    valid_d,
+    branch_predict_taken_d,
+    
+    stall_request,
+    restart_request,
+    refill_request,
+    refill_address,
+    refilling,
+    inst
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
+localparam addr_set_width = clogb2(sets)-1;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+localparam addr_set_lsb = (addr_offset_msb+1);
+localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
+localparam addr_tag_lsb = (addr_set_msb+1);
+localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
+
+
+
+
+
+input clk_i;                                        
+input rst_i;                                        
+
+input stall_a;                                      
+input stall_f;                                      
+
+input valid_d;                                      
+input branch_predict_taken_d;                       
+   
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;                     
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;                     
+input read_enable_f;                                
+
+input refill_ready;                                 
+input [ (32-1):0] refill_data;          
+
+input iflush;                                       
+  
+                                      
+
+
+   
+
+
+
+
+output stall_request;                               
+wire   stall_request;
+output restart_request;                             
+reg    restart_request;
+output refill_request;                              
+wire   refill_request;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+output refilling;                                   
+reg    refilling;
+output [ (32-1):0] inst;                
+wire   [ (32-1):0] inst;
+
+
+
+
+
+wire enable;
+wire [0:associativity-1] way_mem_we;
+wire [ (32-1):0] way_data[0:associativity-1];
+wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [0:associativity-1] way_valid;
+wire [0:associativity-1] way_match;
+wire miss;
+
+wire [ (addr_set_width-1):0] tmem_read_address;
+wire [ (addr_set_width-1):0] tmem_write_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
+wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
+
+reg [ 3:0] state;
+wire flushing;
+wire check;
+wire refill;
+
+reg [associativity-1:0] refill_way_select;
+reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
+wire last_refill;
+reg [ (addr_set_width-1):0] flush_set;
+
+genvar i;
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+   generate
+      for (i = 0; i < associativity; i = i + 1)
+	begin : memories
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 (32),
+	       .address_width              ( (addr_offset_width+addr_set_width))
+
+) 
+	   way_0_data_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (dmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (dmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i]),
+	      .write_data                 (refill_data),    
+	      
+	      .read_data                  (way_data[i])
+	      );
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 ( (addr_tag_width+1)),
+	       .address_width              ( addr_set_width)
+
+	       ) 
+	   way_0_tag_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (tmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (tmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i] | flushing),
+	      .write_data                 (tmem_write_data),
+	      
+	      .read_data                  ({way_tag[i], way_valid[i]})
+	      );
+	   
+	end
+endgenerate
+
+
+
+
+
+
+generate
+    for (i = 0; i < associativity; i = i + 1)
+    begin : match
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[ addr_tag_msb:addr_tag_lsb],  1'b1});
+    end
+endgenerate
+
+
+generate
+    if (associativity == 1)
+    begin : inst_1
+assign inst = way_match[0] ? way_data[0] : 32'b0;
+    end
+    else if (associativity == 2)
+	 begin : inst_2
+assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
+    end
+endgenerate
+
+
+generate 
+    if (bytes_per_line > 4)
+assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset};
+    else
+assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb];
+endgenerate
+    
+assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb];
+
+
+assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb];
+assign tmem_write_address = flushing 
+                                ? flush_set
+                                : refill_address[ addr_set_msb:addr_set_lsb];
+
+
+generate 
+    if (bytes_per_line > 4)                            
+assign last_refill = refill_offset == {addr_offset_width{1'b1}};
+    else
+assign last_refill =  1'b1;
+endgenerate
+
+
+assign enable = (stall_a ==  1'b0);
+
+
+generate
+    if (associativity == 1) 
+    begin : we_1     
+assign way_mem_we[0] = (refill_ready ==  1'b1);
+    end
+    else
+    begin : we_2
+assign way_mem_we[0] = (refill_ready ==  1'b1) && (refill_way_select[0] ==  1'b1);
+assign way_mem_we[1] = (refill_ready ==  1'b1) && (refill_way_select[1] ==  1'b1);
+    end
+endgenerate                     
+
+
+assign tmem_write_data[ 0] = last_refill & !flushing;
+assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+
+
+assign flushing = |state[1:0];
+assign check = state[2];
+assign refill = state[3];
+
+assign miss = (~(|way_match)) && (read_enable_f ==  1'b1) && (stall_f ==  1'b0) && !(valid_d && branch_predict_taken_d);
+assign stall_request = (check ==  1'b0);
+assign refill_request = (refill ==  1'b1);
+                      
+
+
+
+
+
+generate
+    if (associativity >= 2) 
+    begin : way_select      
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
+    else
+    begin        
+        if (miss ==  1'b1)
+            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
+    end
+end
+    end
+endgenerate
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refilling <=  1'b0;
+    else
+        refilling <= refill;
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  4'b0001;
+        flush_set <= { addr_set_width{1'b1}};
+        refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+        restart_request <=  1'b0;
+    end
+    else 
+    begin
+        case (state)
+
+        
+         4'b0001:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+                state <=  4'b0100;
+            flush_set <= flush_set - 1'b1;
+        end
+
+        
+         4'b0010:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+  
+	       
+                  
+	      
+
+
+		state <=  4'b0100;
+	   
+            flush_set <= flush_set - 1'b1;
+        end
+        
+        
+         4'b0100:
+        begin            
+            if (stall_a ==  1'b0)
+                restart_request <=  1'b0;
+            if (iflush ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b0010;
+            end
+            else if (miss ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b1000;
+            end
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+            begin
+                if (last_refill ==  1'b1)
+                begin
+                    restart_request <=  1'b1;
+                    state <=  4'b0100;
+                end
+            end
+        end
+
+        endcase        
+    end
+end
+
+generate 
+    if (bytes_per_line > 4)
+    begin
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_offset <= {addr_offset_width{1'b0}};
+    else 
+    begin
+        case (state)
+        
+        
+         4'b0100:
+        begin            
+            if (iflush ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+            else if (miss ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+                refill_offset <= refill_offset + 1'b1;
+        end
+
+        endcase        
+    end
+end
+    end
+endgenerate
+   
+endmodule
+
+ 
+
+
+
+
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+
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+								 
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+                  
+                    
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+           
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+                   
+               
+                 
+
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+                      
+                      
+                      
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+
+ 
+                    
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+                    
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+  
+                    
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+                      
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+           
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+                
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+                    
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+                  
+                    
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+          
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+                   
+                     
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+                   
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+                      
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+                   
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+                   
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+              
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+                
+                  
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+   
+    
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+        
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+                               
+                                      
+                             
+                                
+                                       
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+                                             
+                                             
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+                                           
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+                         
+                                          
+                                         
+                        
+          
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+                                      
+                       
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+                                            
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+                                    
+   
+                                  
+    
+                                   
+    
+                   
+     
+                                        
+    
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+                                   
+                                  
+                     
+                     
+        
+  
+                       
+                       
+                                               
+
+          
+         
+          
+         
+                 
+                     
+
+                           
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+                                              
+                                             
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+                                        
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+   
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+		      
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+		      
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+		      
+		          
+		     
+		      
+		         
+             
+           
+             
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+		    
+		      
+		       
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+                      
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+                     
+                
+ 
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+                     
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+              
+          
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+   
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+
+		   
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+    
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+                
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+      
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+           
+        
+               
+                  
+                 
+                  
+        
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+   
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+       
+          
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+    
+               
+              
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+          
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+               
+        
+              
+                
+                  
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+        
+         
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+            
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+                       
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+                  
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+ 
+                    
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+                    
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+          
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+                   
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+                     
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+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
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+ 
+ 
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+ 
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+                   
+             
+               
+
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+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
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+ 
+
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+
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+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_instruction_unit_medium_icache (
+    
+    clk_i,
+    rst_i,
+    
+    stall_a,
+    stall_f,
+    stall_d,
+    stall_x,
+    stall_m,
+    valid_f,
+    valid_d,
+    kill_f,
+    branch_predict_taken_d,
+    branch_predict_address_d,
+      
+    
+    
+
+
+    exception_m,
+    branch_taken_m,
+    branch_mispredict_taken_m,
+    branch_target_m,
+  
+
+    iflush,
+ 
+
+  
+    
+    
+    
+
+        
+  
+
+    
+    i_dat_i,
+    i_ack_i,
+    i_err_i,
+    i_rty_i,
+ 
+
+  
+    
+    
+    
+    
+
+
+    
+    
+    pc_f,
+    pc_d,
+    pc_x,
+    pc_m,
+    pc_w,
+  
+
+    icache_stall_request,
+    icache_restart_request,
+    icache_refill_request,
+    icache_refilling,
+ 
+
+  
+
+    
+    i_dat_o,
+    i_adr_o,
+    i_cyc_o,
+    i_sel_o,
+    i_stb_o,
+    i_we_o,
+    i_cti_o,
+    i_lock_o,
+    i_bte_o,
+ 
+
+  
+    
+    
+    
+
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+
+    instruction_f,
+ 
+    
+    instruction_d
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                   
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam eba_reset_minus_4 = eba_reset - 4;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+  
+  
+   
+        
+   
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_f;                                          
+input stall_d;                                          
+input stall_x;                                          
+input stall_m;                                          
+input valid_f;                                          
+input valid_d;                                          
+input kill_f;                                           
+
+input branch_predict_taken_d;                           
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;          
+   
+      
+                                    
+                     
+
+
+input exception_m;
+input branch_taken_m;                                   
+input branch_mispredict_taken_m;                        
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;                   
+
+  
+
+input iflush;                                           
+ 
+
+  
+                            
+                             
+ 
+
+        
+
+
+  
+
+input [ (32-1):0] i_dat_i;                         
+input i_ack_i;                                          
+input i_err_i;                                          
+input i_rty_i;                                          
+ 
+
+
+  
+                                  
+                                 
+                   
+                      
+
+
+
+
+
+
+        
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
+  
+
+output icache_stall_request;                            
+wire   icache_stall_request;
+output icache_restart_request;                          
+wire   icache_restart_request;
+output icache_refill_request;                           
+wire   icache_refill_request;
+output icache_refilling;                                
+wire   icache_refilling;
+ 
+
+
+  
+
+output [ (32-1):0] i_dat_o;                        
+  
+     
+
+
+wire   [ (32-1):0] i_dat_o;
+ 
+
+output [ (32-1):0] i_adr_o;                        
+reg    [ (32-1):0] i_adr_o;
+output i_cyc_o;                                         
+reg    i_cyc_o; 
+output [ (4-1):0] i_sel_o;                 
+  
+     
+
+
+wire   [ (4-1):0] i_sel_o;
+ 
+
+output i_stb_o;                                         
+reg    i_stb_o;
+output i_we_o;                                          
+  
+    
+
+
+wire   i_we_o;
+ 
+
+output [ (3-1):0] i_cti_o;                       
+reg    [ (3-1):0] i_cti_o;
+output i_lock_o;                                        
+reg    i_lock_o;
+output [ (2-1):0] i_bte_o;                       
+wire   [ (2-1):0] i_bte_o;
+ 
+
+
+  
+                   
+     
+                             
+   
+
+
+
+  
+                                      
+    
+
+
+  
+
+output [ (32-1):0] instruction_f;           
+wire   [ (32-1):0] instruction_f;
+ 
+
+output [ (32-1):0] instruction_d;           
+reg    [ (32-1):0] instruction_d;
+
+
+
+
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;                                
+
+  
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;                     
+ 
+
+
+  
+
+wire icache_read_enable_f;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;              
+reg icache_refill_ready;                                
+reg [ (32-1):0] icache_refill_data;         
+wire [ (32-1):0] icache_data_f;             
+wire [ (3-1):0] first_cycle_type;                
+wire [ (3-1):0] next_cycle_type;                 
+wire last_word;                                         
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;                      
+ 
+ 
+                    
+
+
+
+  
+                                      
+    			     
+   
+
+
+  
+
+ 
+               
+
+
+
+   
+  
+   
+    			               
+ 
+
+
+  
+    		       
+
+
+   
+  
+                                         
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+
+lm32_icache_medium_icache #(
+    .associativity          (associativity),
+    .sets                   (sets),
+    .bytes_per_line         (bytes_per_line),
+    .base_address           (base_address),
+    .limit                  (limit)
+    ) icache ( 
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),      
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .valid_d                (valid_d),
+    .address_a              (pc_a),
+    .address_f              (pc_f),
+    .read_enable_f          (icache_read_enable_f),
+    .refill_ready           (icache_refill_ready),
+    .refill_data            (icache_refill_data),
+    .iflush                 (iflush),
+    
+    .stall_request          (icache_stall_request),
+    .restart_request        (icache_restart_request),
+    .refill_request         (icache_refill_request),
+    .refill_address         (icache_refill_address),
+    .refilling              (icache_refilling),
+    .inst                   (icache_data_f)
+    );
+ 
+
+
+
+
+
+
+  
+
+   
+   assign icache_read_enable_f =    (valid_f ==  1'b1)
+     && (kill_f ==  1'b0)
+   
+      
+ 
+                         
+    
+				       
+ 
+       
+				    ;
+ 
+ 
+
+
+always @(*)
+begin
+    
+  
+       
+          
+     
+
+    
+      if (branch_taken_m ==  1'b1)
+	if ((branch_mispredict_taken_m ==  1'b1) && (exception_m ==  1'b0))
+	  pc_a = pc_x;
+	else
+          pc_a = branch_target_m;
+      
+          
+          
+
+
+      else
+	if ( (valid_d ==  1'b1) && (branch_predict_taken_d ==  1'b1) )
+	  pc_a = branch_predict_address_d;
+	else
+  
+
+          if (icache_restart_request ==  1'b1)
+            pc_a = restart_address;
+	  else 
+ 
+        
+            pc_a = pc_f + 1'b1;
+end
+
+
+  
+      
+      
+        
+
+
+
+  
+
+     
+    	      
+
+     
+      
+	  
+       
+	  
+	
+	    
+     
+   
+   
+          
+
+
+  
+   
+
+
+                     
+
+  
+
+assign instruction_f = icache_data_f;
+ 
+   
+
+
+
+ 
+ 
+   
+
+  
+
+  
+
+
+assign i_dat_o = 32'd0;
+assign i_we_o =  1'b0;
+assign i_sel_o = 4'b1111;
+ 
+
+assign i_bte_o =  2'b00;
+ 
+
+
+  
+
+
+generate
+    case (bytes_per_line)
+    4:
+    begin
+assign first_cycle_type =  3'b111;
+assign next_cycle_type =  3'b111;
+assign last_word =  1'b1;
+assign first_address = icache_refill_address;
+    end
+    8:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type =  3'b111;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    16:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ?  3'b111 :  3'b010;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    endcase
+endgenerate
+ 
+
+                     
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        pc_f <= eba_reset_minus_4[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+        pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    end
+    else
+    begin
+        if (stall_f ==  1'b0)
+            pc_f <= pc_a;
+        if (stall_d ==  1'b0)
+            pc_d <= pc_f;
+        if (stall_x ==  1'b0)
+            pc_x <= pc_d;
+        if (stall_m ==  1'b0)
+            pc_m <= pc_x;
+        pc_w <= pc_m;
+    end
+end
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    else
+    begin
+  
+         
+            
+               
+                  
+                    
+                  
+
+               
+                  
+
+
+
+  
+        
+            if (icache_refill_request ==  1'b1)
+                restart_address <= icache_refill_address;
+ 
+
+ 
+
+    end
+end
+ 
+
+
+
+  
+   
+
+       
+          
+    
+    
+           
+              
+    
+
+
+
+
+  
+    
+                 
+ 
+
+     
+       
+       
+       
+       
+     
+
+   
+
+
+
+  
+
+   
+   
+                
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             i_cyc_o <=  1'b0;
+             i_stb_o <=  1'b0;
+             i_adr_o <= { 32{1'b0}};
+             i_cti_o <=  3'b111;
+             i_lock_o <=  1'b0;
+             icache_refill_data <= { 32{1'b0}};
+             icache_refill_ready <=  1'b0;
+    
+               
+  
+
+    
+               
+               
+               
+  
+
+	  end
+	else
+	  begin   
+             icache_refill_ready <=  1'b0;
+             
+             if (i_cyc_o ==  1'b1)
+               begin
+		  
+		  if ((i_ack_i ==  1'b1) || (i_err_i ==  1'b1))
+		    begin
+    
+                          
+			 
+			      
+			             
+			        
+			          
+			 
+                       
+  
+
+			 begin
+			    if (last_word ==  1'b1)
+			      begin
+				 
+				 i_cyc_o <=  1'b0;
+				 i_stb_o <=  1'b0;
+				 i_lock_o <=  1'b0;
+			      end
+			    
+			    i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
+			    i_cti_o <= next_cycle_type;
+			    
+			    icache_refill_ready <=  1'b1;
+			    icache_refill_data <= i_dat_i;
+			 end
+		    end
+    
+		   
+		     
+		    
+                         
+                         
+		    
+		  
+  
+
+               end
+             else
+               begin
+		  if ((icache_refill_request ==  1'b1) && (icache_refill_ready ==  1'b0))
+		    begin
+                       
+         
+                         
+  
+
+                       i_adr_o <= {first_address, 2'b00};
+                       i_cyc_o <=  1'b1;
+                       i_stb_o <=  1'b1;                
+                       i_cti_o <= first_cycle_type;
+                       
+    
+                         
+  
+
+		    end
+    
+		  
+		    
+                              
+			 
+			     
+			         
+			         
+			         
+			         
+			    
+			      
+			      
+			      
+			      
+			      
+			      
+			      
+			 
+		     
+  
+                    
+    
+		  
+		  
+        
+		     
+                      
+   
+		     
+                      
+  
+
+               end
+	  end
+     end
+  
+      
+     
+	   
+	  
+               
+               
+               
+               
+               
+               
+   
+               
+  
+	  
+	
+	     
+             
+                
+               
+		  
+		        
+		    
+                       
+                         
+                         
+                       
+                         
+		    
+   
+		   
+		     
+		    
+                         
+                         
+		       
+		    
+		  
+  
+               
+             
+               
+		  
+		         
+    
+			    
+         
+			 
+		    
+                       
+        
+                         
+  
+                          
+                         
+                         
+   
+                         
+  
+		    
+		  
+		    
+	                      
+    
+			         
+         
+			      
+			 
+   
+			      
+  
+			 
+		    
+               
+	  
+     
+ 
+
+ 
+ 
+
+   
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             instruction_d <= { 32{1'b0}};
+  
+               
+
+
+	  end
+	else
+	  begin
+             if (stall_d ==  1'b0)
+               begin
+		  instruction_d <= instruction_f;
+  
+		    
+
+
+               end
+	  end
+     end  
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+                              
+                              
+                              
+
+
+                          
+                  
+                 
+              
+             
+                    
+                        
+                        
+
+
+                  
+         
+          
+          
+          
+          
+          
+      
+      
+         
+
+
+
+
+
+  
+    
+    
+    
+     
+    
+    
+    
+ 
+    
+    
+    
+    
+
+ 
+    
+    
+
+ 
+    
+
+    
+ 
+    
+    
+
+ 
+    
+    
+    
+    
+    
+    
+    
+
+ 
+    
+    
+
+    
+    
+    
+
+
+
+
+
+                                             
+                                             
+
+                                          
+                                       
+                        
+                              
+
+ 
+                                
+                                  
+                    
+                                           
+
+ 
+                    
+                              
+
+ 
+                                     
+
+
+
+
+
+       
+ 
+                
+    
+                
+    
+
+ 
+                            
+    
+              
+    
+                          
+    
+                                 
+    
+                                
+    
+                  
+            
+                     
+    
+
+ 
+                                       
+    
+                                       
+    
+
+  
+     
+  
+    
+             
+
+
+
+
+                           
+                         
+                       
+                     
+
+
+
+     
+  
+
+                  
+        
+                       
+        
+                       
+
+
+               
+ 
+         
+  
+  
+  
+  
+                          
+
+
+         
+
+
+
+
+
+ 
+      
+   
+      
+   
+
+                 
+
+                  
+             
+
+   
+
+ 
+   
+
+   
+
+
+                  
+     
+     
+         
+                 
+
+
+
+
+   
+   
+
+
+
+   
+
+       
+    
+          
+          
+          
+          
+    
+    
+    
+          
+          
+          
+          
+    
+
+
+
+   
+
+       
+    
+          
+          
+          
+ 
+          
+          
+          
+          
+
+ 
+          
+          
+
+                  
+          
+          
+          
+          
+
+    
+    
+    
+                  
+               
+        
+             
+            
+            
+                
+                  
+                  
+            
+            
+            
+                
+                  
+            
+            
+        
+
+ 
+        
+           
+        
+              
+              
+        
+
+         
+        
+        
+            
+                 
+            
+                                  
+                 
+ 
+                
+                
+                     
+ 
+                    
+                          
+                    
+                    
+                              
+                          
+                    
+                    
+                          
+                    
+                    
+                              
+                          
+                    
+                    
+                          
+                    
+                    
+                    
+      
+                              
+                                   
+
+                          
+                    
+                    
+                    
+      
+                              
+                                   
+
+                          
+                    
+                                                   
+                
+
+                  
+                
+                
+                      
+                      
+                                    
+                
+                
+                      
+                      
+                
+
+                
+                    
+                                
+            
+        
+ 
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                   
+                      
+                 
+                      
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+             
+            
+            
+            
+                  
+                  
+                  
+            
+            
+            
+            
+                  
+                  
+                  
+            
+            
+            
+                  
+                  
+                  
+            
+            
+        
+        
+        
+               
+                      
+                  
+                  
+                    
+                  
+                  
+            
+            
+        
+        
+              
+              
+              
+            
+
+        
+    
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_interrupt_medium_icache (
+    
+    clk_i, 
+    rst_i,
+    
+    interrupt,
+    
+    stall_x,
+  
+    
+    
+
+
+    exception,
+ 
+
+    eret_q_x,
+  
+    
+
+
+    csr,
+    csr_write_data,
+    csr_write_enable,
+    
+    interrupt_exception,
+    
+    csr_read_data
+    );
+
+
+
+
+
+parameter interrupts =  32;         
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [interrupts-1:0] interrupt;               
+
+input stall_x;                                  
+
+  
+                       
+                           
+
+
+input exception;                                
+ 
+
+input eret_q_x;                                 
+  
+                                  
+
+
+
+input [ (4 -1):0] csr;                      
+input [ (32-1):0] csr_write_data;          
+input csr_write_enable;                         
+
+
+
+
+
+output interrupt_exception;                     
+wire   interrupt_exception;
+
+output [ (32-1):0] csr_read_data;          
+reg    [ (32-1):0] csr_read_data;
+
+
+
+
+
+wire [interrupts-1:0] asserted;                 
+
+wire [interrupts-1:0] interrupt_n_exception;
+
+
+
+reg ie;                                         
+reg eie;                                        
+  
+                                         
+
+
+reg [interrupts-1:0] ip;                        
+reg [interrupts-1:0] im;                        
+
+
+
+
+
+
+assign interrupt_n_exception = ip & im;
+
+
+assign interrupt_exception = (|interrupt_n_exception) & ie;
+
+
+assign asserted = ip | interrupt;
+       
+generate
+    if (interrupts > 1) 
+    begin
+
+always @(*)
+begin
+    case (csr)
+     4 'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+                                    
+
+
+                                    1'b0,                                     
+ 
+
+                                    eie, 
+                                    ie
+                                   };
+     4 'h2:  csr_read_data = ip;
+     4 'h1:  csr_read_data = im;
+    default:       csr_read_data = { 32{1'bx}};
+    endcase
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    case (csr)
+     4 'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+                                     
+
+
+                                    1'b0,                                    
+ 
+
+                                    eie, 
+                                    ie
+                                   };
+     4 'h2:  csr_read_data = ip;
+    default:       csr_read_data = { 32{1'bx}};
+      endcase
+end
+    end
+endgenerate
+    
+
+
+
+
+  
+
+   reg [ 10:0] eie_delay  = 0;
+
+   
+generate
+
+   
+    if (interrupts > 1)
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie                   <=  1'b0;
+        eie                  <=  1'b0;
+  
+                           
+
+
+        im                   <= {interrupts{1'b0}};
+        ip                   <= {interrupts{1'b0}};
+       eie_delay             <= 0;
+       
+    end
+    else
+    begin
+        
+        ip                   <= asserted;
+  
+           
+        
+            
+                           
+                            
+        
+            
+        
+            
+                           
+                            
+        
+
+
+        if (exception ==  1'b1)
+        begin
+            
+            eie              <= ie;
+            ie               <=  1'b0;
+        end
+ 
+
+        else if (stall_x ==  1'b0)
+        begin
+
+           if(eie_delay[0])
+             ie              <= eie;
+           
+           eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+            if (eret_q_x ==  1'b1) begin
+                
+               eie_delay[ 10] <=  1'b1;
+               eie_delay[ 10-1:0] <= 0;
+            end
+           
+                      
+           
+  
+                
+                
+                       
+
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  4 'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+                      
+
+
+                end
+                if (csr ==  4 'h1)
+                    im  <= csr_write_data[interrupts-1:0];
+                if (csr ==  4 'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+else
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie              <=  1'b0;
+        eie             <=  1'b0;
+  
+                      
+
+
+        ip              <= {interrupts{1'b0}};
+       eie_delay        <= 0;
+    end
+    else
+    begin
+        
+        ip              <= asserted;
+  
+           
+        
+            
+                      
+                       
+        
+            
+        
+            
+                      
+                       
+        
+
+
+        if (exception ==  1'b1)
+        begin
+            
+            eie         <= ie;
+            ie          <=  1'b0;
+        end
+ 
+
+        else if (stall_x ==  1'b0)
+          begin
+
+             if(eie_delay[0])
+               ie              <= eie;
+           
+             eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+             if (eret_q_x ==  1'b1) begin
+                
+                eie_delay[ 10] <=  1'b1;
+                eie_delay[ 10-1:0] <= 0;
+             end
+           
+  
+                
+                
+                       
+
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  4 'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+                      
+
+
+                end
+                if (csr ==  4 'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	 
+
+ 
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+  
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+
+
+  
+
+  
+
+ 
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+ 
+ 
+                    
+
+  
+                    
+
+
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+ 
+
+
+  
+
+  
+
+ 
+
+ 
+
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+
+  
+
+  
+
+  
+ 
+ 
+
+ 
+
+
+ 
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+  
+ 
+
+
+
+
+  
+
+  
+
+ 
+
+  
+ 
+
+
+
+
+  
+
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+ 
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+ 
+ 
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+ 
+
+
+
+
+
+
+
+
+module lm32_top_medium_icache_debug (
+    
+    clk_i,
+    rst_i,
+    
+
+    interrupt,
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+    );
+
+parameter eba_reset = 32'h00000000;
+parameter sdb_address = 32'h00000000;
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+
+input [ (32-1):0] interrupt;          
+
+
+  
+               
+                             
+
+    
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+  
+
+
+
+ 
+  
+
+
+wire [ 7:0] jtag_reg_d;
+wire [ 7:0] jtag_reg_q;
+wire jtag_update;
+wire [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_q;
+wire jtck;
+wire jrstn;
+ 
+
+
+
+  
+
+                     
+                             
+                            
+                   
+                                 
+ 
+                                 
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+   
+
+lm32_cpu_medium_icache_debug 
+	#(
+		.eba_reset(eba_reset),
+    .sdb_address(sdb_address)
+	) cpu (
+    
+    .clk_i                 (clk_i),
+  
+                   
+
+
+    .rst_i                 (rst_i),
+    
+  
+
+    .interrupt             (interrupt),
+ 
+
+    
+  
+               
+             
+
+     
+  
+
+    
+    .jtag_clk              (jtck),
+    .jtag_update           (jtag_update),
+    .jtag_reg_q            (jtag_reg_q),
+    .jtag_reg_addr_q       (jtag_reg_addr_q),
+ 
+
+  
+
+     
+    .I_DAT_I               (I_DAT_I),
+    .I_ACK_I               (I_ACK_I),
+    .I_ERR_I               (I_ERR_I),
+    .I_RTY_I               (I_RTY_I),
+ 
+
+    
+    .D_DAT_I               (D_DAT_I),
+    .D_ACK_I               (D_ACK_I),
+    .D_ERR_I               (D_ERR_I),
+    .D_RTY_I               (D_RTY_I),
+    
+  
+                  
+            
+           
+                 
+                
+ 
+                
+
+
+
+  
+
+    .jtag_reg_d            (jtag_reg_d),
+    .jtag_reg_addr_d       (jtag_reg_addr_d),
+ 
+
+      
+                
+               
+            
+            
+
+    
+  
+
+    
+    .I_DAT_O               (I_DAT_O),
+    .I_ADR_O               (I_ADR_O),
+    .I_CYC_O               (I_CYC_O),
+    .I_SEL_O               (I_SEL_O),
+    .I_STB_O               (I_STB_O),
+    .I_WE_O                (I_WE_O),
+    .I_CTI_O               (I_CTI_O),
+    .I_LOCK_O              (I_LOCK_O),
+    .I_BTE_O               (I_BTE_O),
+     
+
+    
+    .D_DAT_O               (D_DAT_O),
+    .D_ADR_O               (D_ADR_O),
+    .D_CYC_O               (D_CYC_O),
+    .D_SEL_O               (D_SEL_O),
+    .D_STB_O               (D_STB_O),
+    .D_WE_O                (D_WE_O),
+    .D_CTI_O               (D_CTI_O),
+    .D_LOCK_O              (D_LOCK_O),
+    .D_BTE_O               (D_BTE_O)
+    );
+   
+  
+		   
+
+jtag_cores jtag_cores (
+    
+    .reg_d                 (jtag_reg_d),
+    .reg_addr_d            (jtag_reg_addr_d),
+    
+    .reg_update            (jtag_update),
+    .reg_q                 (jtag_reg_q),
+    .reg_addr_q            (jtag_reg_addr_q),
+    .jtck                  (jtck),
+    .jrstn                 (jrstn)
+    );
+ 
+        
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+           
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_mc_arithmetic_medium_icache_debug (
+    
+    clk_i,
+    rst_i,
+    stall_d,
+    kill_x,
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+    
+
+
+    operand_0_d,
+    operand_1_d,
+    
+    result_x,
+  
+    
+
+
+    stall_request_x
+    );
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+input stall_d;                                  
+input kill_x;                                   
+  
+                                  
+                                 
+
+
+  
+                                
+
+
+  
+                              
+                             
+                             
+
+
+input [ (32-1):0] operand_0_d;
+input [ (32-1):0] operand_1_d;
+
+
+
+
+
+output [ (32-1):0] result_x;               
+reg    [ (32-1):0] result_x;
+  
+                         
+    
+
+
+output stall_request_x;                         
+wire   stall_request_x;
+
+
+
+
+
+reg [ (32-1):0] p;                         
+reg [ (32-1):0] a;
+reg [ (32-1):0] b;
+  
+  
+
+
+
+reg [ 2:0] state;                 
+reg [5:0] cycles;                               
+
+  
+                               
+                                 
+
+
+
+
+
+
+
+
+assign stall_request_x = state !=  3'b000;
+
+  
+
+      
+
+
+
+  
+
+       
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        cycles <= {6{1'b0}};
+        p <= { 32{1'b0}};
+        a <= { 32{1'b0}};
+        b <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+        result_x <= { 32{1'b0}};
+        state <=  3'b000;
+    end
+    else
+    begin
+  
+          
+
+
+        case (state)
+         3'b000:
+        begin
+            if (stall_d ==  1'b0)                 
+            begin          
+                cycles <=  32;
+                p <= 32'b0;
+                a <= operand_0_d;
+                b <= operand_1_d;                    
+  
+                   
+                      
+                   
+                      
+
+                    
+  
+                   
+                      
+
+
+  
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+
+
+            end            
+        end
+  
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+
+        
+  
+        
+        
+               
+                    
+               
+               
+              
+                   
+                  
+                
+        
+
+     
+  
+        
+               
+               
+              
+                   
+                  
+                
+        
+        
+               
+               
+              
+                   
+                  
+                
+        
+
+   
+        endcase
+    end
+end 
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_cpu_medium_icache_debug (
+    
+    clk_i,
+  
+    
+
+
+    rst_i,
+  
+    
+
+
+  
+   
+   
+   
+   
+   
+   
+
+
+
+    
+  
+
+    interrupt,
+ 
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    jtag_clk,
+    jtag_update, 
+    jtag_reg_q,
+    jtag_reg_addr_q,
+ 
+
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+  
+    
+    
+    
+    
+    
+ 
+    
+
+
+
+  
+
+    jtag_reg_d,
+    jtag_reg_addr_d,
+ 
+
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+ 
+  
+    
+    
+    
+    
+    
+    
+    
+    
+           
+
+
+		 
+		 
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+
+		 
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                           
+  
+
+parameter deba_reset =  32'h10000000;                         
+ 
+
+parameter sdb_address =   32'h00000000;
+
+  
+
+parameter icache_associativity =  1;     
+parameter icache_sets =  256;                       
+parameter icache_bytes_per_line =  16;   
+parameter icache_base_address =  32'h0;       
+parameter icache_limit =  32'h7fffffff;                     
+ 
+       
+                         
+     
+         
+                       
+
+
+
+  
+        
+                          
+      
+          
+                        
+
+
+parameter dcache_associativity = 1;    
+parameter dcache_sets = 512;                      
+parameter dcache_bytes_per_line = 16;  
+parameter dcache_base_address = 0;      
+parameter dcache_limit = 0;                    
+ 
+
+
+  
+
+parameter watchpoints =  32'h4;                       
+ 
+   
+
+
+  
+                          
+
+
+parameter breakpoints = 0;
+ 
+
+
+  
+
+parameter interrupts =  32;                         
+ 
+   
+
+
+
+
+
+
+
+input clk_i;                                    
+  
+                                   
+
+    
+input rst_i;                                    
+
+  
+
+input [ (32-1):0] interrupt;          
+ 
+
+
+  
+               
+                             
+
+    
+
+  
+ 
+input jtag_clk;                                 
+input jtag_update;                              
+input [ 7:0] jtag_reg_q;              
+input [2:0] jtag_reg_addr_q;
+ 
+
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+    
+     
+
+
+   
+   
+  
+                   
+     
+                           
+    
+                          
+    
+                 
+     
+                               
+    
+ 
+                               
+    
+
+
+
+
+  
+
+output [ 7:0] jtag_reg_d;
+wire   [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire   [2:0] jtag_reg_addr_d;
+ 
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+
+  
+      
+     
+       
+      
+             
+
+
+   
+
+
+
+
+
+
+  
+
+reg valid_a;                                    
+ 
+
+reg valid_f;                                    
+reg valid_d;                                    
+reg valid_x;                                    
+reg valid_m;                                    
+reg valid_w;                                    
+   
+wire q_x;
+wire [ (32-1):0] immediate_d;              
+wire load_d;                                    
+reg load_x;                                     
+reg load_m;
+wire load_q_x;
+wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
+wire store_d;                                   
+reg store_x;
+reg store_m;
+wire [ 1:0] size_d;                   
+reg [ 1:0] size_x;
+wire branch_d;                                  
+wire branch_predict_d;                          
+wire branch_predict_taken_d;                    
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;   
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
+wire bi_unconditional;
+wire bi_conditional;
+reg branch_x;                                   
+reg branch_predict_x;
+reg branch_predict_taken_x;
+reg branch_m;
+reg branch_predict_m;
+reg branch_predict_taken_m;
+wire branch_mispredict_taken_m;                 
+wire branch_flushX_m;                           
+wire branch_reg_d;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;            
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;             
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+wire [ 0:0] d_result_sel_0_d; 
+wire [ 1:0] d_result_sel_1_d; 
+
+wire x_result_sel_csr_d;                        
+reg x_result_sel_csr_x;
+  
+ 
+                    
+ 
+
+
+      
+                       
+ 
+
+
+  
+
+wire x_result_sel_sext_d;                       
+reg x_result_sel_sext_x;
+ 
+
+wire x_result_sel_logic_d;                      
+  
+                        
+ 
+
+
+wire x_result_sel_add_d;                        
+reg x_result_sel_add_x;
+wire m_result_sel_compare_d;                    
+reg m_result_sel_compare_x;
+reg m_result_sel_compare_m;
+  
+
+wire m_result_sel_shift_d;                      
+reg m_result_sel_shift_x;
+reg m_result_sel_shift_m;
+ 
+
+wire w_result_sel_load_d;                       
+reg w_result_sel_load_x;
+reg w_result_sel_load_m;
+reg w_result_sel_load_w;
+  
+
+wire w_result_sel_mul_d;                        
+reg w_result_sel_mul_x;
+reg w_result_sel_mul_m;
+reg w_result_sel_mul_w;
+ 
+
+wire x_bypass_enable_d;                         
+reg x_bypass_enable_x;                          
+wire m_bypass_enable_d;                         
+reg m_bypass_enable_x;                          
+reg m_bypass_enable_m;
+wire sign_extend_d;                             
+reg sign_extend_x;
+wire write_enable_d;                            
+reg write_enable_x;
+wire write_enable_q_x;
+reg write_enable_m;
+wire write_enable_q_m;
+reg write_enable_w;
+wire write_enable_q_w;
+wire read_enable_0_d;                           
+wire [ (5-1):0] read_idx_0_d;          
+wire read_enable_1_d;                           
+wire [ (5-1):0] read_idx_1_d;          
+wire [ (5-1):0] write_idx_d;           
+reg [ (5-1):0] write_idx_x;            
+reg [ (5-1):0] write_idx_m;
+reg [ (5-1):0] write_idx_w;
+wire [ (5-1):0] csr_d;                     
+reg  [ (5-1):0] csr_x;                  
+wire [ (3-1):0] condition_d;         
+reg [ (3-1):0] condition_x;          
+  
+
+wire break_d;                                   
+reg break_x;                                    
+ 
+
+wire scall_d;                                   
+reg scall_x;    
+wire eret_d;                                    
+reg eret_x;
+wire eret_q_x;
+  
+ 
+ 
+
+
+  
+
+wire bret_d;                                    
+reg bret_x;
+wire bret_q_x;
+  
+ 
+ 
+
+
+ 
+
+wire csr_write_enable_d;                        
+reg csr_write_enable_x;
+wire csr_write_enable_q_x;
+  
+       
+
+
+
+  
+                                
+ 
+ 
+  
+
+
+
+reg [ (32-1):0] d_result_0;                
+reg [ (32-1):0] d_result_1;                
+reg [ (32-1):0] x_result;                  
+reg [ (32-1):0] m_result;                  
+reg [ (32-1):0] w_result;                  
+
+reg [ (32-1):0] operand_0_x;               
+reg [ (32-1):0] operand_1_x;               
+reg [ (32-1):0] store_operand_x;           
+reg [ (32-1):0] operand_m;                 
+reg [ (32-1):0] operand_w;                 
+
+
+  
+
+reg [ (32-1):0] reg_data_live_0;          
+reg [ (32-1):0] reg_data_live_1;  
+reg use_buf;                                    
+reg [ (32-1):0] reg_data_buf_0;
+reg [ (32-1):0] reg_data_buf_1;
+ 
+
+  
+
+ 
+     
+
+
+wire [ (32-1):0] reg_data_0;               
+wire [ (32-1):0] reg_data_1;               
+reg [ (32-1):0] bypass_data_0;             
+reg [ (32-1):0] bypass_data_1;             
+wire reg_write_enable_q_w;
+
+reg interlock;                                  
+
+wire stall_a;                                   
+wire stall_f;                                   
+wire stall_d;                                   
+wire stall_x;                                   
+wire stall_m;                                   
+
+
+wire adder_op_d;                                
+reg adder_op_x;                                 
+reg adder_op_x_n;                               
+wire [ (32-1):0] adder_result_x;           
+wire adder_overflow_x;                          
+wire adder_carry_n_x;                           
+
+
+wire [ 3:0] logic_op_d;           
+reg [ 3:0] logic_op_x;            
+wire [ (32-1):0] logic_result_x;           
+
+  
+
+
+wire [ (32-1):0] sextb_result_x;           
+wire [ (32-1):0] sexth_result_x;           
+wire [ (32-1):0] sext_result_x;            
+ 
+
+
+
+  
+
+  
+                                   
+                                     
+
+
+wire direction_d;                               
+reg direction_x;                                        
+wire [ (32-1):0] shifter_result_m;         
+ 
+
+  
+                               
+ 
+                              
+ 
+
+
+  
+           
+
+
+
+
+  
+
+wire [ (32-1):0] multiplier_result_w;      
+ 
+
+  
+                                 
+ 
+
+
+
+
+  
+                                   
+ 
+ 
+ 
+                           
+
+
+
+
+  
+                         
+  
+
+
+
+
+  
+
+wire [ (32-1):0] interrupt_csr_read_data_x;
+ 
+
+wire [ (32-1):0] cfg;                      
+wire [ (32-1):0] cfg2;                     
+  
+                          
+
+
+reg [ (32-1):0] csr_read_data_x;           
+
+
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                       
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                       
+  
+                          
+
+
+  
+
+wire [ (32-1):0] instruction_f;     
+ 
+
+
+
+wire [ (32-1):0] instruction_d;     
+  
+
+wire iflush;                                    
+wire icache_stall_request;                      
+wire icache_restart_request;                    
+wire icache_refill_request;                     
+wire icache_refilling;                          
+ 
+
+
+
+  
+                                   
+                                     
+                       
+                     
+                      
+                           
+
+
+wire [ (32-1):0] load_data_w;              
+wire stall_wb_load;                             
+
+
+  
+
+  
+
+wire [ (32-1):0] jtx_csr_read_data;        
+wire [ (32-1):0] jrx_csr_read_data;        
+ 
+
+  
+
+wire jtag_csr_write_enable;                     
+wire [ (32-1):0] jtag_csr_write_data;      
+wire [ (5-1):0] jtag_csr;                  
+wire jtag_read_enable;                          
+wire [ 7:0] jtag_read_data;
+wire jtag_write_enable;
+wire [ 7:0] jtag_write_data;
+wire [ (32-1):0] jtag_address;
+wire jtag_access_complete;
+ 
+
+  
+
+wire jtag_break;                                
+ 
+
+ 
+
+
+
+wire raw_x_0;                                   
+wire raw_x_1;                                   
+wire raw_m_0;                                   
+wire raw_m_1;                                   
+wire raw_w_0;                                   
+wire raw_w_1;                                   
+
+
+wire cmp_zero;                                  
+wire cmp_negative;                              
+wire cmp_overflow;                              
+wire cmp_carry_n;                               
+reg condition_met_x;                            
+reg condition_met_m;
+      
+                             
+
+
+wire branch_taken_m;                            
+
+wire kill_f;                                    
+wire kill_d;                                    
+wire kill_x;                                    
+wire kill_m;                                    
+wire kill_w;                                    
+
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;                 
+  
+
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;                
+ 
+
+reg [ (3-1):0] eid_x;                      
+  
+                        
+                        
+
+
+
+  
+
+  
+
+wire dc_ss;                                     
+ 
+
+wire dc_re;                                     
+wire bp_match;
+wire wp_match;
+wire exception_x;                               
+reg exception_m;                                
+wire debug_exception_x;                         
+reg debug_exception_m;
+reg debug_exception_w;
+wire debug_exception_q_w;
+wire non_debug_exception_x;                     
+reg non_debug_exception_m;
+reg non_debug_exception_w;
+wire non_debug_exception_q_w;
+ 
+                                
+ 
+ 
+ 
+
+
+
+  
+
+  
+ 
+wire reset_exception;                           
+ 
+
+  
+                            
+
+
+ 
+
+  
+
+wire interrupt_exception;                       
+ 
+
+  
+
+wire breakpoint_exception;                      
+wire watchpoint_exception;                      
+ 
+
+  
+     
+   
+            
+                   
+
+
+  
+                   
+
+
+wire system_call_exception;                     
+
+  
+                         
+
+
+
+   
+    
+
+
+     
+  
+                          
+   
+            
+   
+                          
+   
+
+    	      
+    	      
+    	      
+    	      
+    	      
+    	      
+   
+   
+
+
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+lm32_instruction_unit_medium_icache_debug #(
+    .eba_reset              (eba_reset),
+    .associativity          (icache_associativity),
+    .sets                   (icache_sets),
+    .bytes_per_line         (icache_bytes_per_line),
+    .base_address           (icache_base_address),
+    .limit                  (icache_limit)
+  ) instruction_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .stall_d                (stall_d),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .valid_f                (valid_f),
+    .valid_d                (valid_d),
+    .kill_f                 (kill_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .branch_predict_address_d (branch_predict_address_d),
+      
+             
+            
+
+
+    .exception_m            (exception_m),
+    .branch_taken_m         (branch_taken_m),
+    .branch_mispredict_taken_m (branch_mispredict_taken_m),
+    .branch_target_m        (branch_target_m),
+  
+
+    .iflush                 (iflush),
+ 
+
+  
+     
+      
+           
+
+        
+  
+
+    
+    .i_dat_i                (I_DAT_I),
+    .i_ack_i                (I_ACK_I),
+    .i_err_i                (I_ERR_I),
+    .i_rty_i                (I_RTY_I),
+ 
+
+  
+
+    .jtag_read_enable       (jtag_read_enable),
+    .jtag_write_enable      (jtag_write_enable),
+    .jtag_write_data        (jtag_write_data),
+    .jtag_address           (jtag_address),
+ 
+
+    
+    
+    .pc_f                   (pc_f),
+    .pc_d                   (pc_d),
+    .pc_x                   (pc_x),
+    .pc_m                   (pc_m),
+    .pc_w                   (pc_w),
+  
+
+    .icache_stall_request   (icache_stall_request),
+    .icache_restart_request (icache_restart_request),
+    .icache_refill_request  (icache_refill_request),
+    .icache_refilling       (icache_refilling),
+ 
+
+  
+
+    
+    .i_dat_o                (I_DAT_O),
+    .i_adr_o                (I_ADR_O),
+    .i_cyc_o                (I_CYC_O),
+    .i_sel_o                (I_SEL_O),
+    .i_stb_o                (I_STB_O),
+    .i_we_o                 (I_WE_O),
+    .i_cti_o                (I_CTI_O),
+    .i_lock_o               (I_LOCK_O),
+    .i_bte_o                (I_BTE_O),
+ 
+ 
+
+  
+    
+    
+    
+
+
+		      	      
+  
+
+    .jtag_read_data         (jtag_read_data),
+    .jtag_access_complete   (jtag_access_complete),
+ 
+
+  
+                
+
+
+  
+
+    .instruction_f          (instruction_f),
+ 
+
+
+		      
+    .instruction_d          (instruction_d)
+
+
+		      
+    );
+
+
+lm32_decoder_medium_icache_debug decoder (
+    
+    .instruction            (instruction_d),
+    
+    .d_result_sel_0         (d_result_sel_0_d),
+    .d_result_sel_1         (d_result_sel_1_d),
+    .x_result_sel_csr       (x_result_sel_csr_d),
+  
+      
+
+
+      
+         
+
+
+  
+
+    .x_result_sel_sext      (x_result_sel_sext_d),
+ 
+    
+    .x_result_sel_logic     (x_result_sel_logic_d),
+  
+          
+
+
+    .x_result_sel_add       (x_result_sel_add_d),
+    .m_result_sel_compare   (m_result_sel_compare_d),
+  
+
+    .m_result_sel_shift     (m_result_sel_shift_d),  
+ 
+    
+    .w_result_sel_load      (w_result_sel_load_d),
+  
+
+    .w_result_sel_mul       (w_result_sel_mul_d),
+ 
+
+    .x_bypass_enable        (x_bypass_enable_d),
+    .m_bypass_enable        (m_bypass_enable_d),
+    .read_enable_0          (read_enable_0_d),
+    .read_idx_0             (read_idx_0_d),
+    .read_enable_1          (read_enable_1_d),
+    .read_idx_1             (read_idx_1_d),
+    .write_enable           (write_enable_d),
+    .write_idx              (write_idx_d),
+    .immediate              (immediate_d),
+    .branch_offset          (branch_offset_d),
+    .load                   (load_d),
+    .store                  (store_d),
+    .size                   (size_d),
+    .sign_extend            (sign_extend_d),
+    .adder_op               (adder_op_d),
+    .logic_op               (logic_op_d),
+  
+
+    .direction              (direction_d),
+ 
+
+  
+                 
+                
+
+
+  
+                   
+
+
+  
+                     
+                    
+
+
+    .branch                 (branch_d),
+    .bi_unconditional       (bi_unconditional),
+    .bi_conditional         (bi_conditional),
+    .branch_reg             (branch_reg_d),
+    .condition              (condition_d),
+  
+
+    .break_opcode           (break_d),
+ 
+
+    .scall                  (scall_d),
+    .eret                   (eret_d),
+  
+
+    .bret                   (bret_d),
+ 
+
+  
+                
+
+
+    .csr_write_enable       (csr_write_enable_d)
+    ); 
+
+
+lm32_load_store_unit_medium_icache_debug #(
+    .associativity          (dcache_associativity),
+    .sets                   (dcache_sets),
+    .bytes_per_line         (dcache_bytes_per_line),
+    .base_address           (dcache_base_address),
+    .limit                  (dcache_limit)
+  ) load_store_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .kill_x                 (kill_x),
+    .kill_m                 (kill_m),
+    .exception_m            (exception_m),
+    .store_operand_x        (store_operand_x),
+    .load_store_address_x   (adder_result_x),
+    .load_store_address_m   (operand_m),
+    .load_store_address_w   (operand_w[1:0]),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_q_x               (load_q_x),
+    .store_q_x              (store_q_x),
+    .load_q_m               (load_q_m),
+    .store_q_m              (store_q_m),
+    .sign_extend_x          (sign_extend_x),
+    .size_x                 (size_x),
+  
+                     
+
+
+
+  
+    
+    
+    
+    
+    
+    
+    
+
+
+		     
+    
+    .d_dat_i                (D_DAT_I),
+    .d_ack_i                (D_ACK_I),
+    .d_err_i                (D_ERR_I),
+    .d_rty_i                (D_RTY_I),
+    
+    
+  
+      
+     
+       
+           
+
+    
+    .load_data_w            (load_data_w),
+    .stall_wb_load          (stall_wb_load),
+    
+    .d_dat_o                (D_DAT_O),
+    .d_adr_o                (D_ADR_O),
+    .d_cyc_o                (D_CYC_O),
+    .d_sel_o                (D_SEL_O),
+    .d_stb_o                (D_STB_O),
+    .d_we_o                 (D_WE_O),
+    .d_cti_o                (D_CTI_O),
+    .d_lock_o               (D_LOCK_O),
+    .d_bte_o                (D_BTE_O)
+    );      
+       
+
+lm32_adder adder (
+    
+    .adder_op_x             (adder_op_x),
+    .adder_op_x_n           (adder_op_x_n),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .adder_result_x         (adder_result_x),
+    .adder_carry_n_x        (adder_carry_n_x),
+    .adder_overflow_x       (adder_overflow_x)
+    );
+
+
+lm32_logic_op logic_op (
+    
+    .logic_op_x             (logic_op_x),
+    .operand_0_x            (operand_0_x),
+
+    .operand_1_x            (operand_1_x),
+    
+    .logic_result_x         (logic_result_x)
+    );
+              
+  
+
+
+lm32_shifter shifter (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .direction_x            (direction_x),
+    .sign_extend_x          (sign_extend_x),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .shifter_result_m       (shifter_result_m)
+    );
+ 
+
+
+  
+
+
+lm32_multiplier multiplier (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .operand_0              (d_result_0),
+    .operand_1              (d_result_1),
+    
+    .result                 (multiplier_result_w)    
+    );
+ 
+
+
+  
+
+  
+    
+                      
+                      
+                    
+                     
+                   
+                   
+                  
+
+         
+                 
+
+ 
+               
+              
+              
+    
+                
+                
+    
+                   
+                   
+           
+
+            
+    
+
+
+              
+  
+
+
+lm32_interrupt_medium_icache_debug interrupt_unit (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    
+    .interrupt              (interrupt),
+    
+    .stall_x                (stall_x),
+  
+
+    .non_debug_exception    (non_debug_exception_q_w), 
+    .debug_exception        (debug_exception_q_w),
+ 
+                   
+
+
+    .eret_q_x               (eret_q_x),
+  
+
+    .bret_q_x               (bret_q_x),
+ 
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    
+    .interrupt_exception    (interrupt_exception),
+    
+    .csr_read_data          (interrupt_csr_read_data_x)
+    );
+ 
+
+
+  
+      
+      
+        
+   
+
+
+
+
+  
+
+
+lm32_jtag_medium_icache_debug jtag (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .jtag_clk               (jtag_clk),
+    .jtag_update            (jtag_update),
+    .jtag_reg_q             (jtag_reg_q),
+    .jtag_reg_addr_q        (jtag_reg_addr_q),
+    
+  
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    .stall_x                (stall_x),
+ 
+
+  
+
+    .jtag_read_data         (jtag_read_data),
+    .jtag_access_complete   (jtag_access_complete),
+ 
+
+  
+
+    .exception_q_w          (debug_exception_q_w || non_debug_exception_q_w),
+ 
+    
+    
+    
+  
+
+    .jtx_csr_read_data      (jtx_csr_read_data),
+    .jrx_csr_read_data      (jrx_csr_read_data),
+ 
+
+  
+
+    .jtag_csr_write_enable  (jtag_csr_write_enable),
+    .jtag_csr_write_data    (jtag_csr_write_data),
+    .jtag_csr               (jtag_csr),
+    .jtag_read_enable       (jtag_read_enable),
+    .jtag_write_enable      (jtag_write_enable),
+    .jtag_write_data        (jtag_write_data),
+    .jtag_address           (jtag_address),
+ 
+
+  
+
+    .jtag_break             (jtag_break),
+    .jtag_reset             (reset_exception),
+ 
+
+    
+    .jtag_reg_d             (jtag_reg_d),
+    .jtag_reg_addr_d        (jtag_reg_addr_d)
+    );
+ 
+
+
+  
+
+
+lm32_debug_medium_icache_debug #(
+    .breakpoints            (breakpoints),
+    .watchpoints            (watchpoints)
+  ) hw_debug (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    .pc_x                   (pc_x),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_store_address_x   (adder_result_x),
+    .csr_write_enable_x     (csr_write_enable_q_x),
+    .csr_write_data         (operand_1_x),
+    .csr_x                  (csr_x),
+   
+
+	        
+
+    .jtag_csr_write_enable  (jtag_csr_write_enable),
+    .jtag_csr_write_data    (jtag_csr_write_data),
+    .jtag_csr               (jtag_csr),
+	       
+
+	        
+      
+        
+                   
+	      
+
+ 
+
+  
+
+    .eret_q_x               (eret_q_x),
+    .bret_q_x               (bret_q_x),
+    .stall_x                (stall_x),
+    .exception_x            (exception_x),
+    .q_x                    (q_x),
+  
+      
+
+
+ 
+
+    
+  
+
+    .dc_ss                  (dc_ss),
+ 
+
+    .dc_re                  (dc_re),
+    .bp_match               (bp_match),
+    .wp_match               (wp_match)
+    );
+ 
+
+
+
+
+  
+
+   
+           
+            
+          
+            
+
+
+             
+              
+    
+
+   wire [31:0] regfile_data_0, regfile_data_1;
+   reg [31:0]  w_result_d;
+   reg 	       regfile_raw_0, regfile_raw_0_nxt;
+   reg 	       regfile_raw_1, regfile_raw_1_nxt;
+   
+   
+             
+          
+
+   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
+     begin
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[25:21]))
+	  regfile_raw_0_nxt = 1'b1;
+	else
+	  regfile_raw_0_nxt = 1'b0;
+	
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[20:16]))
+	  regfile_raw_1_nxt = 1'b1;
+	else
+	  regfile_raw_1_nxt = 1'b0;
+     end
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_0 or w_result_d or regfile_data_0)
+     if (regfile_raw_0)
+       reg_data_live_0 = w_result_d;
+     else
+       reg_data_live_0 = regfile_data_0;
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_1 or w_result_d or regfile_data_1)
+     if (regfile_raw_1)
+       reg_data_live_1 = w_result_d;
+     else
+       reg_data_live_1 = regfile_data_1;
+   
+   
+     
+
+   always @(posedge clk_i  )
+     if (rst_i ==  1'b1)
+       begin
+	  regfile_raw_0 <= 1'b0;
+	  regfile_raw_1 <= 1'b0;
+	  w_result_d <= 32'b0;
+       end
+     else
+       begin
+	  regfile_raw_0 <= regfile_raw_0_nxt;
+	  regfile_raw_1 <= regfile_raw_1_nxt;
+	  w_result_d <= w_result;
+       end
+   
+   
+      
+
+   
+   lm32_dp_ram
+     #(
+       
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_0
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[25:21]),
+      
+      .rdata_o	(regfile_data_0)
+      );
+
+   lm32_dp_ram
+     #(
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_1
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[20:16]),
+      
+      .rdata_o	(regfile_data_1)
+      );
+ 
+
+
+  
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+   
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+
+
+
+
+
+
+
+
+  
+
+
+assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
+assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
+ 
+
+  
+
+ 
+
+   
+   
+
+
+
+
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w ==  1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w ==  1'b1);
+
+
+always @(*)
+begin
+    if (   (   (x_bypass_enable_x ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_x_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_x_1 ==  1'b1))
+               )
+           )
+        || (   (m_bypass_enable_m ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_m_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_m_1 ==  1'b1))
+               )
+           )
+       )
+        interlock =  1'b1;
+    else
+        interlock =  1'b0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_0 ==  1'b1)        
+        bypass_data_0 = x_result;
+    else if (raw_m_0 ==  1'b1)
+        bypass_data_0 = m_result;
+    else if (raw_w_0 ==  1'b1)
+        bypass_data_0 = w_result;
+    else
+        bypass_data_0 = reg_data_0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_1 ==  1'b1)
+        bypass_data_1 = x_result;
+    else if (raw_m_1 ==  1'b1)
+        bypass_data_1 = m_result;
+    else if (raw_w_1 ==  1'b1)
+        bypass_data_1 = w_result;
+    else
+        bypass_data_1 = reg_data_1;
+end
+
+   
+          
+       
+       
+     
+
+   assign branch_predict_d = bi_unconditional | bi_conditional;
+   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
+   
+   
+   assign branch_target_d = pc_d + branch_offset_d;
+
+   
+   
+   
+   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
+
+
+always @(*)
+begin
+    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
+    case (d_result_sel_1_d)
+     2'b00:      d_result_1 = { 32{1'b0}};
+     2'b01:     d_result_1 = bypass_data_1;
+     2'b10: d_result_1 = immediate_d;
+    default:                        d_result_1 = { 32{1'bx}};
+    endcase
+end
+
+      
+
+   
+   
+
+
+
+  
+
+
+assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
+assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
+assign sext_result_x = size_x ==  2'b00 ? sextb_result_x : sexth_result_x;
+ 
+
+
+  
+
+      
+
+
+
+
+assign cmp_zero = operand_0_x == operand_1_x;
+assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_overflow = adder_overflow_x;
+assign cmp_carry_n = adder_carry_n_x;
+always @(*)
+begin
+    case (condition_x)
+     3'b000:   condition_met_x =  1'b1;
+     3'b110:   condition_met_x =  1'b1;
+     3'b001:    condition_met_x = cmp_zero;
+     3'b111:   condition_met_x = !cmp_zero;
+     3'b010:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+     3'b101:   condition_met_x = cmp_carry_n && !cmp_zero;
+     3'b011:   condition_met_x = cmp_negative == cmp_overflow;
+     3'b100:  condition_met_x = cmp_carry_n;
+    default:              condition_met_x = 1'bx;
+    endcase 
+end
+
+
+always @(*)
+begin
+    x_result =   x_result_sel_add_x ? adder_result_x 
+               : x_result_sel_csr_x ? csr_read_data_x
+  
+
+               : x_result_sel_sext_x ? sext_result_x
+ 
+
+  
+                  
+
+
+  
+                  
+
+
+  
+                  
+
+
+               : logic_result_x;
+end
+
+
+always @(*)
+begin
+    m_result =   m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
+  
+
+               : m_result_sel_shift_m ? shifter_result_m
+ 
+
+               : operand_m; 
+end
+
+
+always @(*)
+begin
+    w_result =    w_result_sel_load_w ? load_data_w
+  
+
+                : w_result_sel_mul_w ? multiplier_result_w
+ 
+
+                : operand_w;
+end
+
+      
+
+          
+                                
+                                     
+                                 
+                                 
+                              
+
+
+
+
+assign branch_taken_m =      (stall_m ==  1'b0) 
+                          && (   (   (branch_m ==  1'b1) 
+                                  && (valid_m ==  1'b1)
+                                  && (   (   (condition_met_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b0)
+					 )
+				      || (   (condition_met_m ==  1'b0)
+					  && (branch_predict_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b1)
+					 )
+				     )
+                                 ) 
+                              || (exception_m ==  1'b1)
+                             );
+
+
+assign branch_mispredict_taken_m =    (condition_met_m ==  1'b0)
+                                   && (branch_predict_m ==  1'b1)
+	   			   && (branch_predict_taken_m ==  1'b1);
+   
+
+assign branch_flushX_m =    (stall_m ==  1'b0)
+                         && (   (   (branch_m ==  1'b1) 
+                                 && (valid_m ==  1'b1)
+			         && (   (condition_met_m ==  1'b1)
+				     || (   (condition_met_m ==  1'b0)
+					 && (branch_predict_m ==  1'b1)
+					 && (branch_predict_taken_m ==  1'b1)
+					)
+				    )
+			        )
+			     || (exception_m ==  1'b1)
+			    );
+
+
+assign kill_f =    (   (valid_d ==  1'b1)
+                    && (branch_predict_taken_d ==  1'b1)
+		   )
+                || (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+
+                || (icache_refill_request ==  1'b1) 
+ 
+
+                  
+                   
+
+
+                ;
+assign kill_d =    (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+
+                || (icache_refill_request ==  1'b1)     
+ 
+                
+                  
+                   
+
+
+                ;
+assign kill_x =    (branch_flushX_m ==  1'b1) 
+                  
+                   
+
+
+                ;
+assign kill_m =     1'b0
+                  
+                   
+
+
+                ;                
+assign kill_w =     1'b0
+                  
+                   
+
+                
+                ;
+
+
+
+  
+
+assign breakpoint_exception =    (   (   (break_x ==  1'b1)
+				      || (bp_match ==  1'b1)
+				     )
+				  && (valid_x ==  1'b1)
+				 )
+  
+
+                              || (jtag_break ==  1'b1)
+ 
+
+                              ;
+ 
+
+
+  
+
+assign watchpoint_exception = wp_match ==  1'b1;
+ 
+
+
+  
+        
+                                             
+                                         
+     
+
+
+
+  
+     
+
+
+
+assign system_call_exception = (   (scall_x ==  1'b1)
+  
+                                   
+
+
+			       );
+
+  
+
+assign debug_exception_x =  (breakpoint_exception ==  1'b1)
+                         || (watchpoint_exception ==  1'b1)
+                         ;
+
+assign non_debug_exception_x = (system_call_exception ==  1'b1)
+  
+
+                            || (reset_exception ==  1'b1)
+ 
+
+  
+                               
+                               
+
+
+  
+                               
+
+
+  
+
+                            || (   (interrupt_exception ==  1'b1)
+  
+
+                                && (dc_ss ==  1'b0)
+ 
+                            
+  
+ 				   
+				   
+
+
+                               )
+ 
+
+                            ;
+
+assign exception_x = (debug_exception_x ==  1'b1) || (non_debug_exception_x ==  1'b1);
+ 
+               
+ 
+                               
+                               
+
+ 
+                               
+
+ 
+                                  
+ 
+                                   
+                            
+ 
+ 				   
+				   
+
+                               
+
+                            
+
+
+
+  
+ 
+
+ 
+  
+      
+   
+      
+
+
+
+
+always @(*)
+begin
+  
+
+  
+
+    if (reset_exception ==  1'b1)
+        eid_x =  3'h0;
+    else
+ 
+     
+  
+            
+          
+    
+
+
+         if (breakpoint_exception ==  1'b1)
+        eid_x =  3'd1;
+    else
+ 
+
+  
+            
+          
+    
+            
+          
+    
+
+
+  
+
+         if (watchpoint_exception ==  1'b1)
+        eid_x =  3'd3;
+    else 
+ 
+
+  
+            
+          
+    
+
+
+  
+
+         if (   (interrupt_exception ==  1'b1)
+  
+
+             && (dc_ss ==  1'b0)
+ 
+                            
+            )
+        eid_x =  3'h6;
+    else
+ 
+
+        eid_x =  3'h7;
+end
+
+
+
+assign stall_a = (stall_f ==  1'b1);
+                
+assign stall_f = (stall_d ==  1'b1);
+                
+assign stall_d =   (stall_x ==  1'b1) 
+                || (   (interlock ==  1'b1)
+                    && (kill_d ==  1'b0)
+                   ) 
+		|| (   (   (eret_d ==  1'b1)
+			|| (scall_d ==  1'b1)
+  
+			   
+
+
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+  
+
+		|| (   (   (break_d ==  1'b1)
+			|| (bret_d ==  1'b1)
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+ 
+                   
+                || (   (csr_write_enable_d ==  1'b1)
+                    && (load_q_x ==  1'b1)
+                   )                      
+  
+                 
+                 
+                       
+		           
+			 
+			
+		    
+
+	
+                ;
+                
+assign stall_x =    (stall_m ==  1'b1)
+  
+                       
+                        
+                     
+
+
+
+	    
+                 ;
+
+assign stall_m =    (stall_wb_load ==  1'b1)
+  
+                    
+
+
+                 || (   (D_CYC_O ==  1'b1)
+                     && (   (store_m ==  1'b1)
+		         
+          
+          
+
+		  
+	 
+	
+
+          
+           
+          
+       
+
+  
+
+		         || ((store_x ==  1'b1) && (interrupt_exception ==  1'b1))
+ 
+
+                         || (load_m ==  1'b1)
+                         || (load_x ==  1'b1)
+                        ) 
+                    ) 
+ 
+                 
+  
+                         
+
+                                    
+  
+
+                 || (icache_stall_request ==  1'b1)     
+                 || ((I_CYC_O ==  1'b1) && ((branch_m ==  1'b1) || (exception_m ==  1'b1))) 
+ 
+ 
+                                
+
+
+                               
+  
+                                  
+                        
+                    
+
+
+  
+                  
+   
+
+                 ;      
+
+
+
+
+  
+         
+
+
+  
+         
+         
+
+
+  
+         
+
+
+  
+         
+         
+
+
+assign q_x = (valid_x ==  1'b1) && (kill_x ==  1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x ==  1'b1) && (q_x ==  1'b1);
+assign eret_q_x = (eret_x ==  1'b1) && (q_x ==  1'b1);
+  
+
+assign bret_q_x = (bret_x ==  1'b1) && (q_x ==  1'b1);
+ 
+
+assign load_q_x = (load_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+
+               && (bp_match ==  1'b0)
+ 
+
+                  ;
+assign store_q_x = (store_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+
+               && (bp_match ==  1'b0)
+ 
+
+                  ;
+  
+         
+
+                              
+assign q_m = (valid_m ==  1'b1) && (kill_m ==  1'b0) && (exception_m ==  1'b0);
+assign load_q_m = (load_m ==  1'b1) && (q_m ==  1'b1);
+assign store_q_m = (store_m ==  1'b1) && (q_m ==  1'b1);
+  
+
+assign debug_exception_q_w = ((debug_exception_w ==  1'b1) && (valid_w ==  1'b1));
+assign non_debug_exception_q_w = ((non_debug_exception_w ==  1'b1) && (valid_w ==  1'b1));        
+ 
+                 
+
+
+
+assign write_enable_q_x = (write_enable_x ==  1'b1) && (valid_x ==  1'b1) && (branch_flushX_m ==  1'b0);
+assign write_enable_q_m = (write_enable_m ==  1'b1) && (valid_m ==  1'b1);
+assign write_enable_q_w = (write_enable_w ==  1'b1) && (valid_w ==  1'b1);
+
+assign reg_write_enable_q_w = (write_enable_w ==  1'b1) && (kill_w ==  1'b0) && (valid_w ==  1'b1);
+
+
+assign cfg = {
+               6'h02,
+              watchpoints[3:0],
+              breakpoints[3:0],
+              interrupts[5:0],
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+ 
+               1'b1
+ 
+              
+
+
+              };
+
+assign cfg2 = {
+		     30'b0,
+  
+		     
+
+
+		      1'b0,
+ 
+
+  
+		     
+
+
+		      1'b0
+ 
+
+		     };
+   
+
+  
+
+assign iflush = (   (csr_write_enable_d ==  1'b1) 
+                 && (csr_d ==  5'h3)
+                 && (stall_d ==  1'b0)
+                 && (kill_d ==  1'b0)
+                 && (valid_d ==  1'b1))
+
+  
+
+             ||
+                (   (jtag_csr_write_enable ==  1'b1)
+		 && (jtag_csr ==  5'h3))
+ 
+
+		 ;
+ 
+ 
+  
+         
+                      
+
+ 
+               
+                       
+		      
+
+		   
+
+ 
+
+
+assign csr_d = read_idx_0_d[ (5-1):0];
+
+
+always @(*)
+begin
+    case (csr_x)
+  
+
+     5'h0,
+     5'h1,
+     5'h2:   csr_read_data_x = interrupt_csr_read_data_x;  
+ 
+
+  
+         
+
+
+     5'h6:  csr_read_data_x = cfg;
+     5'h7:  csr_read_data_x = {eba, 8'h00};
+  
+
+     5'h9: csr_read_data_x = {deba, 8'h00};
+ 
+
+  
+
+     5'he:  csr_read_data_x = jtx_csr_read_data;  
+     5'hf:  csr_read_data_x = jrx_csr_read_data;
+ 
+
+     5'ha: csr_read_data_x = cfg2;
+     5'hb:  csr_read_data_x = sdb_address;
+  
+        
+
+
+      
+      
+    default:        csr_read_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  5'h7) && (stall_x ==  1'b0))
+            eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+  
+
+   
+
+       if ((jtag_csr_write_enable ==  1'b1) && (jtag_csr ==  5'h7))
+         eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+  
+
+   
+              
+           
+ 
+	 
+ 
+
+    end
+end
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  5'h9) && (stall_x ==  1'b0))
+            deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+   
+
+    
+
+       if ((jtag_csr_write_enable ==  1'b1) && (jtag_csr ==  5'h9))
+         deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+   
+
+    
+              
+           
+  
+       
+  
+
+    end
+end
+ 
+
+
+
+  
+   
+
+       
+          
+    
+            
+
+
+
+
+  
+
+   
+
+       
+          
+    
+    
+        
+                
+             
+	     
+	
+        
+               
+              
+    
+
+
+
+ 
+
+
+  
+
+  
+ 
+
+           
+           
+       
+          
+            
+                 
+             
+          
+     
+            
+ 
+
+
+always @(*)
+begin
+    if (icache_refill_request ==  1'b1) 
+        valid_a =  1'b0;
+    else if (icache_restart_request ==  1'b1) 
+        valid_a =  1'b1;
+    else 
+        valid_a = !icache_refilling;
+end 
+ 
+
+ 
+ 
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        valid_f <=  1'b0;
+        valid_d <=  1'b0;
+        valid_x <=  1'b0;
+        valid_m <=  1'b0;
+        valid_w <=  1'b0;
+    end
+    else
+    begin    
+        if ((kill_f ==  1'b1) || (stall_a ==  1'b0))
+  
+
+            valid_f <= valid_a;    
+ 
+              
+
+            
+        else if (stall_f ==  1'b0)
+            valid_f <=  1'b0;            
+
+        if (kill_d ==  1'b1)
+            valid_d <=  1'b0;
+        else if (stall_f ==  1'b0)
+            valid_d <= valid_f & !kill_f;
+        else if (stall_d ==  1'b0)
+            valid_d <=  1'b0;
+       
+        if (stall_d ==  1'b0)
+            valid_x <= valid_d & !kill_d;
+        else if (kill_x ==  1'b1)
+            valid_x <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_x <=  1'b0;
+
+        if (kill_m ==  1'b1)
+            valid_m <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_m <= valid_x & !kill_x;
+        else if (stall_m ==  1'b0)
+            valid_m <=  1'b0;
+
+        if (stall_m ==  1'b0)
+            valid_w <= valid_m & !kill_m;
+        else 
+            valid_w <=  1'b0;        
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+  
+                 
+
+        
+        operand_0_x <= { 32{1'b0}};
+        operand_1_x <= { 32{1'b0}};
+        store_operand_x <= { 32{1'b0}};
+        branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};        
+        x_result_sel_csr_x <=  1'b0;
+  
+          
+
+
+      
+          
+
+
+  
+
+        x_result_sel_sext_x <=  1'b0;
+ 
+    
+  
+          
+
+
+        x_result_sel_add_x <=  1'b0;
+        m_result_sel_compare_x <=  1'b0;
+  
+
+        m_result_sel_shift_x <=  1'b0;
+ 
+    
+        w_result_sel_load_x <=  1'b0;
+  
+
+        w_result_sel_mul_x <=  1'b0;
+ 
+
+        x_bypass_enable_x <=  1'b0;
+        m_bypass_enable_x <=  1'b0;
+        write_enable_x <=  1'b0;
+        write_idx_x <= { 5{1'b0}};
+        csr_x <= { 5{1'b0}};
+        load_x <=  1'b0;
+        store_x <=  1'b0;
+        size_x <= { 2{1'b0}};
+        sign_extend_x <=  1'b0;
+        adder_op_x <=  1'b0;
+        adder_op_x_n <=  1'b0;
+        logic_op_x <= 4'h0;
+  
+
+        direction_x <=  1'b0;
+ 
+
+  
+          
+
+
+
+        branch_x <=  1'b0;
+        branch_predict_x <=  1'b0;
+        branch_predict_taken_x <=  1'b0;
+        condition_x <=  3'b000;
+  
+
+        break_x <=  1'b0;
+ 
+
+        scall_x <=  1'b0;
+        eret_x <=  1'b0;
+  
+
+        bret_x <=  1'b0;
+ 
+
+  
+          
+          
+
+
+        csr_write_enable_x <=  1'b0;
+        operand_m <= { 32{1'b0}};
+        branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        m_result_sel_compare_m <=  1'b0;
+  
+
+        m_result_sel_shift_m <=  1'b0;
+ 
+    
+        w_result_sel_load_m <=  1'b0;
+  
+
+        w_result_sel_mul_m <=  1'b0;
+ 
+
+        m_bypass_enable_m <=  1'b0;
+        branch_m <=  1'b0;
+        branch_predict_m <=  1'b0;
+	branch_predict_taken_m <=  1'b0;
+        exception_m <=  1'b0;
+        load_m <=  1'b0;
+        store_m <=  1'b0;
+        write_enable_m <=  1'b0;            
+        write_idx_m <= { 5{1'b0}};
+        condition_met_m <=  1'b0;
+  
+          
+
+
+  
+
+        debug_exception_m <=  1'b0;
+        non_debug_exception_m <=  1'b0;        
+ 
+
+        operand_w <= { 32{1'b0}};        
+        w_result_sel_load_w <=  1'b0;
+  
+
+        w_result_sel_mul_w <=  1'b0;
+ 
+
+        write_idx_w <= { 5{1'b0}};        
+        write_enable_w <=  1'b0;
+  
+
+        debug_exception_w <=  1'b0;
+        non_debug_exception_w <=  1'b0;        
+ 
+          
+
+
+  
+          
+
+
+    end
+    else
+    begin
+        
+       
+        if (stall_x ==  1'b0)
+        begin
+  
+                     
+
+        
+            operand_0_x <= d_result_0;
+            operand_1_x <= d_result_1;
+            store_operand_x <= bypass_data_1;
+            branch_target_x <= branch_reg_d ==  1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;            
+            x_result_sel_csr_x <= x_result_sel_csr_d;
+  
+              
+
+
+      
+              
+
+
+  
+
+            x_result_sel_sext_x <= x_result_sel_sext_d;
+ 
+    
+  
+              
+
+
+            x_result_sel_add_x <= x_result_sel_add_d;
+            m_result_sel_compare_x <= m_result_sel_compare_d;
+  
+
+            m_result_sel_shift_x <= m_result_sel_shift_d;
+ 
+    
+            w_result_sel_load_x <= w_result_sel_load_d;
+  
+
+            w_result_sel_mul_x <= w_result_sel_mul_d;
+ 
+
+            x_bypass_enable_x <= x_bypass_enable_d;
+            m_bypass_enable_x <= m_bypass_enable_d;
+            load_x <= load_d;
+            store_x <= store_d;
+            branch_x <= branch_d;
+	    branch_predict_x <= branch_predict_d;
+	    branch_predict_taken_x <= branch_predict_taken_d;
+	    write_idx_x <= write_idx_d;
+            csr_x <= csr_d;
+            size_x <= size_d;
+            sign_extend_x <= sign_extend_d;
+            adder_op_x <= adder_op_d;
+            adder_op_x_n <= ~adder_op_d;
+            logic_op_x <= logic_op_d;
+  
+
+            direction_x <= direction_d;
+ 
+
+  
+              
+
+
+            condition_x <= condition_d;
+            csr_write_enable_x <= csr_write_enable_d;
+  
+
+            break_x <= break_d;
+ 
+
+            scall_x <= scall_d;
+  
+              
+
+
+            eret_x <= eret_d;
+  
+
+            bret_x <= bret_d; 
+ 
+
+            write_enable_x <= write_enable_d;
+        end
+        
+        
+
+        if (stall_m ==  1'b0)
+        begin
+            operand_m <= x_result;
+            m_result_sel_compare_m <= m_result_sel_compare_x;
+  
+
+            m_result_sel_shift_m <= m_result_sel_shift_x;
+ 
+    
+            if (exception_x ==  1'b1)
+            begin
+                w_result_sel_load_m <=  1'b0;
+  
+
+                w_result_sel_mul_m <=  1'b0;
+ 
+
+            end
+            else
+            begin
+                w_result_sel_load_m <= w_result_sel_load_x;
+  
+
+                w_result_sel_mul_m <= w_result_sel_mul_x;
+ 
+
+            end
+            m_bypass_enable_m <= m_bypass_enable_x;
+            load_m <= load_x;
+            store_m <= store_x;
+      
+                
+
+
+            branch_m <= branch_x;
+	    branch_predict_m <= branch_predict_x;
+	    branch_predict_taken_m <= branch_predict_taken_x;
+ 
+
+  
+
+	   
+	   
+	   
+	   
+	   
+            if (non_debug_exception_x ==  1'b1) 
+                write_idx_m <=  5'd30;
+            else if (debug_exception_x ==  1'b1)
+                write_idx_m <=  5'd31;
+            else 
+                write_idx_m <= write_idx_x;
+ 
+               
+                  
+             
+                  
+
+
+            condition_met_m <= condition_met_x;
+  
+
+	   if (exception_x ==  1'b1)
+	     if ((dc_re ==  1'b1)
+		 || ((debug_exception_x ==  1'b1) 
+		     && (non_debug_exception_x ==  1'b0)))
+	       branch_target_m <= {deba, eid_x, {3{1'b0}}};
+	     else
+	       branch_target_m <= {eba, eid_x, {3{1'b0}}};
+	   else
+	     branch_target_m <= branch_target_x;
+ 
+                      
+
+
+  
+              
+              
+
+
+  
+              
+
+
+  
+ 
+               
+
+
+
+            write_enable_m <= exception_x ==  1'b1 ?  1'b1 : write_enable_x;            
+  
+
+            debug_exception_m <= debug_exception_x;
+            non_debug_exception_m <= non_debug_exception_x;        
+ 
+
+        end
+        
+        
+        if (stall_m ==  1'b0)
+        begin
+            if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+                exception_m <=  1'b1;
+            else 
+                exception_m <=  1'b0;
+  
+	           
+ 
+					    
+
+					 
+
+
+	end
+                
+        
+  
+                      
+
+
+        operand_w <= exception_m ==  1'b1 ? {pc_m, 2'b00} : m_result;
+ 
+
+        w_result_sel_load_w <= w_result_sel_load_m;
+  
+
+        w_result_sel_mul_w <= w_result_sel_mul_m;
+ 
+
+        write_idx_w <= write_idx_m;
+  
+          
+          
+ 
+           
+
+
+
+        write_enable_w <= write_enable_m;
+  
+
+        debug_exception_w <= debug_exception_m;
+        non_debug_exception_w <= non_debug_exception_m;
+ 
+          
+
+
+  
+              
+                   
+                   
+               
+	   
+            
+
+
+    end
+end
+
+  
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        use_buf <=  1'b0;
+        reg_data_buf_0 <= { 32{1'b0}};
+        reg_data_buf_1 <= { 32{1'b0}};
+    end
+    else
+    begin
+        if (stall_d ==  1'b0)
+            use_buf <=  1'b0;
+        else if (use_buf ==  1'b0)
+        begin        
+            reg_data_buf_0 <= reg_data_live_0;
+            reg_data_buf_1 <= reg_data_live_1;
+            use_buf <=  1'b1;
+        end        
+        if (reg_write_enable_q_w ==  1'b1)
+        begin
+            if (write_idx_w == read_idx_0_d)
+                reg_data_buf_0 <= w_result;
+            if (write_idx_w == read_idx_1_d)
+                reg_data_buf_1 <= w_result;
+        end
+    end
+end
+ 
+
+
+  
+
+ 
+
+   
+
+        
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+     
+           
+            
+        
+
+
+
+
+  
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+ 
+          
+
+          
+    
+    
+    
+          
+        
+ 
+               
+
+           
+
+                
+              
+              
+              
+              
+        
+        
+              
+        
+             
+        
+            
+                 
+            
+                
+                  
+                  
+            
+            
+              
+            
+              
+ 
+              
+
+        
+        
+        
+              
+ 
+              
+
+        
+    
+
+
+
+      
+
+
+
+
+
+        
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_load_store_unit_medium_icache_debug 
+(
+    
+    clk_i,
+    rst_i,
+ 
+    stall_a,
+    stall_x,
+    stall_m,
+    kill_x,
+    kill_m,
+    exception_m,
+    store_operand_x,
+    load_store_address_x,
+    load_store_address_m,
+    load_store_address_w,
+    load_x,
+    store_x,
+    load_q_x,
+    store_q_x,
+    load_q_m,
+    store_q_m,
+    sign_extend_x,
+    size_x,
+  
+    
+
+
+    
+    d_dat_i,
+    d_ack_i,
+    d_err_i,
+    d_rty_i,
+    
+    
+  
+    
+    
+    
+    
+
+    
+  
+    
+    
+    
+    
+    
+    
+    
+
+			     
+    load_data_w,
+    stall_wb_load,
+    
+    d_dat_o,
+    d_adr_o,
+    d_cyc_o,
+    d_sel_o,
+    d_stb_o,
+    d_we_o,
+    d_cti_o,
+    d_lock_o,
+    d_bte_o
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+
+   input clk_i;                                            
+   
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+input kill_x;                                           
+input kill_m;                                           
+input exception_m;                                      
+
+input [ (32-1):0] store_operand_x;                 
+input [ (32-1):0] load_store_address_x;            
+input [ (32-1):0] load_store_address_m;            
+input [1:0] load_store_address_w;                       
+input load_x;                                           
+input store_x;                                          
+input load_q_x;                                         
+input store_q_x;                                        
+input load_q_m;                                         
+input store_q_m;                                        
+input sign_extend_x;                                    
+input [ 1:0] size_x;                          
+
+  
+                                            
+
+
+
+     
+     
+     
+      
+      
+            
+    	 
+   
+
+
+
+   reg 		 [31:0] iram_dat_d0;
+   reg 		 iram_en_d0;
+   wire 	 iram_en;
+   wire [31:0] 	 iram_data;
+   
+   
+   
+input [ (32-1):0] d_dat_i;                         
+input d_ack_i;                                          
+input d_err_i;                                          
+input d_rty_i;                                          
+
+
+
+
+
+  
+                            
+   
+                           
+   
+                             
+   
+ 
+   
+
+
+
+   
+output [ (32-1):0] load_data_w;                    
+reg    [ (32-1):0] load_data_w;
+output stall_wb_load;                                   
+reg    stall_wb_load;
+
+output [ (32-1):0] d_dat_o;                        
+reg    [ (32-1):0] d_dat_o;
+output [ (32-1):0] d_adr_o;                        
+reg    [ (32-1):0] d_adr_o;
+output d_cyc_o;                                         
+reg    d_cyc_o;
+output [ (4-1):0] d_sel_o;                 
+reg    [ (4-1):0] d_sel_o;
+output d_stb_o;                                         
+reg    d_stb_o; 
+output d_we_o;                                          
+reg    d_we_o;
+output [ (3-1):0] d_cti_o;                       
+reg    [ (3-1):0] d_cti_o;
+output d_lock_o;                                        
+reg    d_lock_o;
+output [ (2-1):0] d_bte_o;                       
+wire   [ (2-1):0] d_bte_o;
+
+
+
+
+
+
+reg [ 1:0] size_m;
+reg [ 1:0] size_w;
+reg sign_extend_m;
+reg sign_extend_w;
+reg [ (32-1):0] store_data_x;       
+reg [ (32-1):0] store_data_m;       
+reg [ (4-1):0] byte_enable_x;
+reg [ (4-1):0] byte_enable_m;
+wire [ (32-1):0] data_m;
+reg [ (32-1):0] data_w;
+
+   
+
+  
+                                    
+ 
+                      
+              
+                                 
+                  
+                   
+                                          
+                      
+
+
+  
+                                      
+ 
+                                      
+                    
+                      
+                        
+                  
+
+
+wire wb_select_x;                                       
+  
+                                      
+
+  
+    
+    
+   
+
+
+
+reg wb_select_m;
+reg [ (32-1):0] wb_data_m;                         
+reg wb_load_complete;                                   
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+ 
+              
+                       
+             
+               
+                      
+       
+    
+                      
+                            
+                    
+                    
+                    
+                  
+                  
+                     
+                    
+                 
+            
+               
+                
+                     
+    
+              
+            
+             
+             
+                  
+                  
+    
+
+
+
+
+
+
+
+
+  
+            
+                             
+
+
+
+  
+            
+                             
+
+      
+        
+
+    
+       
+
+   
+
+    
+     
+       
+     
+         
+     
+
+          
+    
+   
+   
+
+
+   
+  
+            
+                               
+ 
+                               
+
+ 
+                               
+
+                     
+
+
+	  
+   assign wb_select_x =     1'b1
+  
+                          
+
+
+  
+                         
+
+
+  
+                         
+
+
+                     ;
+
+
+always @(*)
+begin
+    case (size_x)
+     2'b00:  store_data_x = {4{store_operand_x[7:0]}};
+     2'b11: store_data_x = {2{store_operand_x[15:0]}};
+     2'b10:  store_data_x = store_operand_x;    
+    default:          store_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+always @(*)
+begin
+    casez ({size_x, load_store_address_x[1:0]})
+    { 2'b00, 2'b11}:  byte_enable_x = 4'b0001;
+    { 2'b00, 2'b10}:  byte_enable_x = 4'b0010;
+    { 2'b00, 2'b01}:  byte_enable_x = 4'b0100;
+    { 2'b00, 2'b00}:  byte_enable_x = 4'b1000;
+    { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+    { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+    { 2'b10, 2'b??}:  byte_enable_x = 4'b1111;
+    default:                   byte_enable_x = 4'bxxxx;
+    endcase
+end
+
+  
+      
+            
+
+           
+	                            
+   
+   
+               
+        
+
+
+   
+  
+  
+   
+   
+         
+                    
+                       
+                      
+                        
+                     
+                        
+  
+   
+         
+                    
+                       
+                      
+                      
+  
+ 
+   
+   
+         
+                    
+                       
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+
+   
+   
+   
+         
+                     
+                      
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+    
+   
+         
+                     
+                    
+
+  
+
+   
+   assign data_m = wb_data_m;
+   
+
+  
+
+ 
+
+
+
+always @(*)
+begin
+    casez ({size_w, load_store_address_w[1:0]})
+    { 2'b00, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+    { 2'b00, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+    { 2'b00, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+    { 2'b00, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+    { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+    { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+    { 2'b10, 2'b??}:  load_data_w = data_w;
+    default:                   load_data_w = { 32{1'bx}};
+    endcase
+end
+
+
+assign d_bte_o =  2'b00;
+
+                  
+
+ 
+     
+    
+    
+   
+   
+   
+    
+    
+    
+    
+   
+   
+     
+     
+    
+    
+    
+   
+         
+     
+     
+    
+    
+
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        d_cyc_o <=  1'b0;
+        d_stb_o <=  1'b0;
+        d_dat_o <= { 32{1'b0}};
+        d_adr_o <= { 32{1'b0}};
+        d_sel_o <= { 4{ 1'b0}};
+        d_we_o <=  1'b0;
+        d_cti_o <=  3'b111;
+        d_lock_o <=  1'b0;
+        wb_data_m <= { 32{1'b0}};
+        wb_load_complete <=  1'b0;
+        stall_wb_load <=  1'b0;
+                  
+          
+
+                
+    end
+    else 
+    begin
+   
+        
+          
+
+                
+        
+        if (d_cyc_o ==  1'b1)
+        begin
+            
+            if ((d_ack_i ==  1'b1) || (d_err_i ==  1'b1))
+            begin
+                  
+                     
+                
+                    
+                        
+                
+                
+
+                
+                begin
+                    
+                    d_cyc_o <=  1'b0;
+                    d_stb_o <=  1'b0;
+                    d_lock_o <=  1'b0;
+                end
+      
+                  
+                
+                  
+
+
+                
+                wb_data_m <= d_dat_i;
+                
+                wb_load_complete <= !d_we_o;
+            end
+            
+        end
+        else 
+        begin
+                  
+               
+            
+                
+                  
+                  
+                  
+                                  
+                  
+                  
+                
+            
+             
+
+            
+                 if (   (store_q_m ==  1'b1)
+                     && (stall_m ==  1'b0)
+  
+                        
+
+
+  
+		        
+
+			
+                    )
+            begin
+                
+                d_dat_o <= store_data_m;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b1;
+                d_cti_o <=  3'b111;
+            end        
+            else if (   (load_q_m ==  1'b1) 
+                     && (wb_select_m ==  1'b1) 
+                     && (wb_load_complete ==  1'b0)
+                     
+                    )
+            begin
+                
+                stall_wb_load <=  1'b0;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b0;
+                d_cti_o <=  3'b111;
+            end
+        end
+        
+        if (stall_m ==  1'b0)
+            wb_load_complete <=  1'b0;
+        
+        if ((load_q_x ==  1'b1) && (wb_select_x ==  1'b1) && (stall_x ==  1'b0))
+            stall_wb_load <=  1'b1;
+        
+        if ((kill_m ==  1'b1) || (exception_m ==  1'b1))
+            stall_wb_load <=  1'b0;
+    end
+end
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        sign_extend_m <=  1'b0;
+        size_m <= 2'b00;
+        byte_enable_m <=  1'b0;
+        store_data_m <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+  
+          
+			    
+
+
+        wb_select_m <=  1'b0;        
+    end
+    else
+    begin
+        if (stall_m ==  1'b0)
+        begin
+            sign_extend_m <= sign_extend_x;
+            size_m <= size_x;
+            byte_enable_m <= byte_enable_x;    
+            store_data_m <= store_data_x;
+  
+              
+
+
+  
+              
+
+
+  
+              
+			    
+
+
+            wb_select_m <= wb_select_x;
+        end
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        size_w <= 2'b00;
+        data_w <= { 32{1'b0}};
+        sign_extend_w <=  1'b0;
+    end
+    else
+    begin
+        size_w <= size_m;
+
+  
+         
+
+
+        data_w <= data_m;
+
+        sign_extend_w <= sign_extend_m;
+    end
+end
+
+
+
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+  
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+
+
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+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
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+ 
+ 
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+ 
+ 
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+ 
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+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_decoder_medium_icache_debug (
+    
+    instruction,
+    
+    d_result_sel_0,
+    d_result_sel_1,        
+    x_result_sel_csr,
+  
+    
+
+    
+      
+    
+
+
+  
+
+    x_result_sel_sext,
+ 
+    
+    x_result_sel_logic,
+  
+    
+
+
+    x_result_sel_add,
+    m_result_sel_compare,
+  
+
+    m_result_sel_shift,  
+ 
+    
+    w_result_sel_load,
+  
+
+    w_result_sel_mul,
+ 
+
+    x_bypass_enable,
+    m_bypass_enable,
+    read_enable_0,
+    read_idx_0,
+    read_enable_1,
+    read_idx_1,
+    write_enable,
+    write_idx,
+    immediate,
+    branch_offset,
+    load,
+    store,
+    size,
+    sign_extend,
+    adder_op,
+    logic_op,
+  
+
+    direction,
+ 
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+
+
+    branch,
+    branch_reg,
+    condition,
+    bi_conditional,
+    bi_unconditional,
+  
+
+    break_opcode,
+ 
+
+    scall,
+    eret,
+  
+
+    bret,
+ 
+
+  
+    
+
+
+    csr_write_enable
+    );
+
+
+
+
+
+input [ (32-1):0] instruction;       
+
+
+
+
+
+output [ 0:0] d_result_sel_0;
+reg    [ 0:0] d_result_sel_0;
+output [ 1:0] d_result_sel_1;
+reg    [ 1:0] d_result_sel_1;
+output x_result_sel_csr;
+reg    x_result_sel_csr;
+  
+ 
+    
+
+
+      
+ 
+    
+
+
+  
+
+output x_result_sel_sext;
+reg    x_result_sel_sext;
+ 
+
+output x_result_sel_logic;
+reg    x_result_sel_logic;
+  
+ 
+    
+
+
+output x_result_sel_add;
+reg    x_result_sel_add;
+output m_result_sel_compare;
+reg    m_result_sel_compare;
+  
+
+output m_result_sel_shift;
+reg    m_result_sel_shift;
+ 
+
+output w_result_sel_load;
+reg    w_result_sel_load;
+  
+
+output w_result_sel_mul;
+reg    w_result_sel_mul;
+ 
+
+output x_bypass_enable;
+wire   x_bypass_enable;
+output m_bypass_enable;
+wire   m_bypass_enable;
+output read_enable_0;
+wire   read_enable_0;
+output [ (5-1):0] read_idx_0;
+wire   [ (5-1):0] read_idx_0;
+output read_enable_1;
+wire   read_enable_1;
+output [ (5-1):0] read_idx_1;
+wire   [ (5-1):0] read_idx_1;
+output write_enable;
+wire   write_enable;
+output [ (5-1):0] write_idx;
+wire   [ (5-1):0] write_idx;
+output [ (32-1):0] immediate;
+wire   [ (32-1):0] immediate;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+wire   [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+output load;
+wire   load;
+output store;
+wire   store;
+output [ 1:0] size;
+wire   [ 1:0] size;
+output sign_extend;
+wire   sign_extend;
+output adder_op;
+wire   adder_op;
+output [ 3:0] logic_op;
+wire   [ 3:0] logic_op;
+  
+
+output direction;
+wire   direction;
+ 
+
+  
+ 
+   
+ 
+   
+
+
+  
+ 
+   
+
+
+  
+ 
+   
+ 
+   
+
+
+output branch;
+wire   branch;
+output branch_reg;
+wire   branch_reg;
+output [ (3-1):0] condition;
+wire   [ (3-1):0] condition;
+output bi_conditional;
+wire bi_conditional;
+output bi_unconditional;
+wire bi_unconditional;
+  
+
+output break_opcode;
+wire   break_opcode;
+ 
+
+output scall;
+wire   scall;
+output eret;
+wire   eret;
+  
+
+output bret;
+wire   bret;
+ 
+
+  
+  
+    
+
+
+output csr_write_enable;
+wire   csr_write_enable;
+
+
+
+
+
+wire [ (32-1):0] extended_immediate;       
+wire [ (32-1):0] high_immediate;           
+wire [ (32-1):0] call_immediate;           
+wire [ (32-1):0] branch_immediate;         
+wire sign_extend_immediate;                     
+wire select_high_immediate;                     
+wire select_call_immediate;                     
+
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+  
+ 
+
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+  
+ 
+
+
+  
+
+wire op_mul;
+ 
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+  
+
+wire op_sextb;
+wire op_sexth;
+ 
+
+wire op_sh;
+  
+
+wire op_sl;
+ 
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+  
+ 
+
+
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+  
+
+wire shift;
+ 
+
+  
+ 
+
+
+  
+
+wire sext;
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+assign op_add    = instruction[ 30:26] ==  5'b01101;
+assign op_and    = instruction[ 30:26] ==  5'b01000;
+assign op_andhi  = instruction[ 31:26] ==  6'b011000;
+assign op_b      = instruction[ 31:26] ==  6'b110000;
+assign op_bi     = instruction[ 31:26] ==  6'b111000;
+assign op_be     = instruction[ 31:26] ==  6'b010001;
+assign op_bg     = instruction[ 31:26] ==  6'b010010;
+assign op_bge    = instruction[ 31:26] ==  6'b010011;
+assign op_bgeu   = instruction[ 31:26] ==  6'b010100;
+assign op_bgu    = instruction[ 31:26] ==  6'b010101;
+assign op_bne    = instruction[ 31:26] ==  6'b010111;
+assign op_call   = instruction[ 31:26] ==  6'b110110;
+assign op_calli  = instruction[ 31:26] ==  6'b111110;
+assign op_cmpe   = instruction[ 30:26] ==  5'b11001;
+assign op_cmpg   = instruction[ 30:26] ==  5'b11010;
+assign op_cmpge  = instruction[ 30:26] ==  5'b11011;
+assign op_cmpgeu = instruction[ 30:26] ==  5'b11100;
+assign op_cmpgu  = instruction[ 30:26] ==  5'b11101;
+assign op_cmpne  = instruction[ 30:26] ==  5'b11111;
+  
+       
+
+
+assign op_lb     = instruction[ 31:26] ==  6'b000100;
+assign op_lbu    = instruction[ 31:26] ==  6'b010000;
+assign op_lh     = instruction[ 31:26] ==  6'b000111;
+assign op_lhu    = instruction[ 31:26] ==  6'b001011;
+assign op_lw     = instruction[ 31:26] ==  6'b001010;
+  
+       
+
+
+  
+
+assign op_mul    = instruction[ 30:26] ==  5'b00010;
+ 
+
+assign op_nor    = instruction[ 30:26] ==  5'b00001;
+assign op_or     = instruction[ 30:26] ==  5'b01110;
+assign op_orhi   = instruction[ 31:26] ==  6'b011110;
+assign op_raise  = instruction[ 31:26] ==  6'b101011;
+assign op_rcsr   = instruction[ 31:26] ==  6'b100100;
+assign op_sb     = instruction[ 31:26] ==  6'b001100;
+  
+
+assign op_sextb  = instruction[ 31:26] ==  6'b101100;
+assign op_sexth  = instruction[ 31:26] ==  6'b110111;
+ 
+
+assign op_sh     = instruction[ 31:26] ==  6'b000011;
+  
+
+assign op_sl     = instruction[ 30:26] ==  5'b01111;      
+ 
+
+assign op_sr     = instruction[ 30:26] ==  5'b00101;
+assign op_sru    = instruction[ 30:26] ==  5'b00000;
+assign op_sub    = instruction[ 31:26] ==  6'b110010;
+assign op_sw     = instruction[ 31:26] ==  6'b010110;
+  
+       
+
+
+assign op_wcsr   = instruction[ 31:26] ==  6'b110100;
+assign op_xnor   = instruction[ 30:26] ==  5'b01001;
+assign op_xor    = instruction[ 30:26] ==  5'b00110;
+
+
+assign arith = op_add | op_sub;
+assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
+assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
+assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
+assign bi_unconditional = op_bi;
+assign bra = op_b | bi_unconditional | bi_conditional;
+assign call = op_call | op_calli;
+  
+
+assign shift = op_sl | op_sr | op_sru;
+ 
+
+  
+     
+
+
+  
+   
+     
+
+
+  
+
+assign sext = op_sextb | op_sexth;
+ 
+
+  
+   
+
+
+  
+    
+   
+
+
+assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
+assign store = op_sb | op_sh | op_sw;
+
+
+always @(*)
+begin
+    
+    if (call) 
+        d_result_sel_0 =  1'b1;
+    else 
+        d_result_sel_0 =  1'b0;
+    if (call) 
+        d_result_sel_1 =  2'b00;         
+    else if ((instruction[31] == 1'b0) && !bra) 
+        d_result_sel_1 =  2'b10;
+    else
+        d_result_sel_1 =  2'b01; 
+    
+    x_result_sel_csr =  1'b0;
+  
+      
+
+
+  
+      
+
+
+  
+
+    x_result_sel_sext =  1'b0;
+ 
+
+    x_result_sel_logic =  1'b0;
+          
+      
+
+
+    x_result_sel_add =  1'b0;
+    if (op_rcsr)
+        x_result_sel_csr =  1'b1;
+      
+ 
+         
+          
+
+ 
+        
+                  
+
+ 
+      
+                      
+
+
+
+  
+      
+                  
+
+
+  
+
+    else if (sext)
+        x_result_sel_sext =  1'b1;
+ 
+        
+    else if (logical) 
+        x_result_sel_logic =  1'b1;
+          
+      
+          
+
+
+    else 
+        x_result_sel_add =  1'b1;        
+    
+    
+
+    m_result_sel_compare = cmp;
+  
+
+    m_result_sel_shift = shift;
+ 
+
+
+    
+    w_result_sel_load = load;
+  
+
+    w_result_sel_mul = op_mul; 
+ 
+
+end
+
+
+assign x_bypass_enable =  arith 
+                        | logical
+  
+                         
+                         
+
+                        
+  
+                         
+
+
+  
+                         
+                         
+
+
+  
+                         
+
+                  
+  
+
+                        | sext 
+ 
+                        
+  
+                         
+
+
+                        | op_rcsr
+                        ;
+
+assign m_bypass_enable = x_bypass_enable 
+  
+
+                        | shift
+ 
+
+                        | cmp
+                        ;
+
+assign read_enable_0 = ~(op_bi | op_calli);
+assign read_idx_0 = instruction[25:21];
+
+assign read_enable_1 = ~(op_bi | op_calli | load);
+assign read_idx_1 = instruction[20:16];
+
+assign write_enable = ~(bra | op_raise | store | op_wcsr);
+assign write_idx = call
+                    ? 5'd29
+                    : instruction[31] == 1'b0 
+                        ? instruction[20:16] 
+                        : instruction[15:11];
+                        
+
+assign size = instruction[27:26];
+
+assign sign_extend = instruction[28];                      
+
+assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
+
+assign logic_op = instruction[29:26];
+  
+
+
+assign direction = instruction[29];
+ 
+
+
+assign branch = bra | call;
+assign branch_reg = op_call | op_b;
+assign condition = instruction[28:26];      
+  
+
+assign break_opcode = op_raise & ~instruction[2];
+ 
+
+assign scall = op_raise & instruction[2];
+assign eret = op_b & (instruction[25:21] == 5'd30);
+  
+
+assign bret = op_b & (instruction[25:21] == 5'd31);
+ 
+
+  
+
+   
+
+
+
+assign csr_write_enable = op_wcsr;
+
+
+
+assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
+assign select_high_immediate = op_andhi | op_orhi;
+assign select_call_immediate = instruction[31];
+
+assign high_immediate = {instruction[15:0], 16'h0000};
+assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
+assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
+assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
+
+assign immediate = select_high_immediate ==  1'b1 
+                        ? high_immediate 
+                        : extended_immediate;
+   
+assign branch_offset = select_call_immediate ==  1'b1   
+                        ? (call_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0])
+                        : (branch_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0]);
+    
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
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+              
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+               
+                   
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+  
+
+
+
+
+
+
+module lm32_icache_medium_icache_debug ( 
+    
+    clk_i,
+    rst_i,    
+    stall_a,
+    stall_f,
+    address_a,
+    address_f,
+    read_enable_f,
+    refill_ready,
+    refill_data,
+    iflush,
+  
+    
+
+
+    valid_d,
+    branch_predict_taken_d,
+    
+    stall_request,
+    restart_request,
+    refill_request,
+    refill_address,
+    refilling,
+    inst
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
+localparam addr_set_width = clogb2(sets)-1;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+localparam addr_set_lsb = (addr_offset_msb+1);
+localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
+localparam addr_tag_lsb = (addr_set_msb+1);
+localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
+
+
+
+
+
+input clk_i;                                        
+input rst_i;                                        
+
+input stall_a;                                      
+input stall_f;                                      
+
+input valid_d;                                      
+input branch_predict_taken_d;                       
+   
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;                     
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;                     
+input read_enable_f;                                
+
+input refill_ready;                                 
+input [ (32-1):0] refill_data;          
+
+input iflush;                                       
+  
+                                      
+
+
+   
+
+
+
+
+output stall_request;                               
+wire   stall_request;
+output restart_request;                             
+reg    restart_request;
+output refill_request;                              
+wire   refill_request;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;               
+output refilling;                                   
+reg    refilling;
+output [ (32-1):0] inst;                
+wire   [ (32-1):0] inst;
+
+
+
+
+
+wire enable;
+wire [0:associativity-1] way_mem_we;
+wire [ (32-1):0] way_data[0:associativity-1];
+wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [0:associativity-1] way_valid;
+wire [0:associativity-1] way_match;
+wire miss;
+
+wire [ (addr_set_width-1):0] tmem_read_address;
+wire [ (addr_set_width-1):0] tmem_write_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
+wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
+
+reg [ 3:0] state;
+wire flushing;
+wire check;
+wire refill;
+
+reg [associativity-1:0] refill_way_select;
+reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
+wire last_refill;
+reg [ (addr_set_width-1):0] flush_set;
+
+genvar i;
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+   generate
+      for (i = 0; i < associativity; i = i + 1)
+	begin : memories
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 (32),
+	       .address_width              ( (addr_offset_width+addr_set_width))
+
+) 
+	   way_0_data_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (dmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (dmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i]),
+	      .write_data                 (refill_data),    
+	      
+	      .read_data                  (way_data[i])
+	      );
+	   
+	   lm32_ram 
+	     #(
+	       
+	       .data_width                 ( (addr_tag_width+1)),
+	       .address_width              ( addr_set_width)
+
+	       ) 
+	   way_0_tag_ram 
+	     (
+	      
+	      .read_clk                   (clk_i),
+	      .write_clk                  (clk_i),
+	      .reset                      (rst_i),
+	      .read_address               (tmem_read_address),
+	      .enable_read                (enable),
+	      .write_address              (tmem_write_address),
+	      .enable_write               ( 1'b1),
+	      .write_enable               (way_mem_we[i] | flushing),
+	      .write_data                 (tmem_write_data),
+	      
+	      .read_data                  ({way_tag[i], way_valid[i]})
+	      );
+	   
+	end
+endgenerate
+
+
+
+
+
+
+generate
+    for (i = 0; i < associativity; i = i + 1)
+    begin : match
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[ addr_tag_msb:addr_tag_lsb],  1'b1});
+    end
+endgenerate
+
+
+generate
+    if (associativity == 1)
+    begin : inst_1
+assign inst = way_match[0] ? way_data[0] : 32'b0;
+    end
+    else if (associativity == 2)
+	 begin : inst_2
+assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
+    end
+endgenerate
+
+
+generate 
+    if (bytes_per_line > 4)
+assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset};
+    else
+assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb];
+endgenerate
+    
+assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb];
+
+
+assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb];
+assign tmem_write_address = flushing 
+                                ? flush_set
+                                : refill_address[ addr_set_msb:addr_set_lsb];
+
+
+generate 
+    if (bytes_per_line > 4)                            
+assign last_refill = refill_offset == {addr_offset_width{1'b1}};
+    else
+assign last_refill =  1'b1;
+endgenerate
+
+
+assign enable = (stall_a ==  1'b0);
+
+
+generate
+    if (associativity == 1) 
+    begin : we_1     
+assign way_mem_we[0] = (refill_ready ==  1'b1);
+    end
+    else
+    begin : we_2
+assign way_mem_we[0] = (refill_ready ==  1'b1) && (refill_way_select[0] ==  1'b1);
+assign way_mem_we[1] = (refill_ready ==  1'b1) && (refill_way_select[1] ==  1'b1);
+    end
+endgenerate                     
+
+
+assign tmem_write_data[ 0] = last_refill & !flushing;
+assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+
+
+assign flushing = |state[1:0];
+assign check = state[2];
+assign refill = state[3];
+
+assign miss = (~(|way_match)) && (read_enable_f ==  1'b1) && (stall_f ==  1'b0) && !(valid_d && branch_predict_taken_d);
+assign stall_request = (check ==  1'b0);
+assign refill_request = (refill ==  1'b1);
+                      
+
+
+
+
+
+generate
+    if (associativity >= 2) 
+    begin : way_select      
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
+    else
+    begin        
+        if (miss ==  1'b1)
+            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
+    end
+end
+    end
+endgenerate
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refilling <=  1'b0;
+    else
+        refilling <= refill;
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  4'b0001;
+        flush_set <= { addr_set_width{1'b1}};
+        refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+        restart_request <=  1'b0;
+    end
+    else 
+    begin
+        case (state)
+
+        
+         4'b0001:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+                state <=  4'b0100;
+            flush_set <= flush_set - 1'b1;
+        end
+
+        
+         4'b0010:
+        begin            
+            if (flush_set == { addr_set_width{1'b0}})
+  
+	       
+                  
+	      
+
+
+		state <=  4'b0100;
+	   
+            flush_set <= flush_set - 1'b1;
+        end
+        
+        
+         4'b0100:
+        begin            
+            if (stall_a ==  1'b0)
+                restart_request <=  1'b0;
+            if (iflush ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b0010;
+            end
+            else if (miss ==  1'b1)
+            begin
+                refill_address <= address_f;
+                state <=  4'b1000;
+            end
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+            begin
+                if (last_refill ==  1'b1)
+                begin
+                    restart_request <=  1'b1;
+                    state <=  4'b0100;
+                end
+            end
+        end
+
+        endcase        
+    end
+end
+
+generate 
+    if (bytes_per_line > 4)
+    begin
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        refill_offset <= {addr_offset_width{1'b0}};
+    else 
+    begin
+        case (state)
+        
+        
+         4'b0100:
+        begin            
+            if (iflush ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+            else if (miss ==  1'b1)
+                refill_offset <= {addr_offset_width{1'b0}};
+        end
+
+        
+         4'b1000:
+        begin            
+            if (refill_ready ==  1'b1)
+                refill_offset <= refill_offset + 1'b1;
+        end
+
+        endcase        
+    end
+end
+    end
+endgenerate
+   
+endmodule
+
+ 
+
+
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+								 
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+ 
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+ 
+
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+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
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+                
+           
+
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+              
+               
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+                    
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+                
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+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
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+                   
+              
+                  
+                 
+            
+
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+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
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+         
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+                  
+              
+            
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+   
+    
+    
+        
+    
+    
+    
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+    
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+
+
+                               
+                                      
+                             
+                                
+                                       
+
+   
+   
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+   
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+
+
+                                             
+                                             
+
+                                           
+                                           
+                                           
+
+                         
+                         
+                                          
+                                         
+                        
+          
+
+                                      
+                       
+
+                                            
+
+
+
+
+
+                                    
+   
+                                  
+    
+                                   
+    
+                   
+     
+                                        
+    
+                        
+    
+
+
+
+
+
+                                   
+                                  
+                     
+                     
+        
+  
+                       
+                       
+                                               
+
+          
+         
+          
+         
+                 
+                     
+
+                           
+                                           
+                                              
+                                             
+
+                                        
+                
+             
+                                        
+                   
+
+  
+
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+ 
+
+
+
+
+
+   
+                     
+	  
+	   
+              
+               
+		 
+		  
+		    
+		     
+		     
+
+		      
+		    
+		     
+		      
+		      
+		      
+		      
+		      
+		      
+		      
+		      
+		          
+		     
+		      
+		         
+             
+           
+             
+		               
+		    
+		      
+		       
+			 
+			  
+			  
+
+			   
+			 
+			  
+			   
+			   
+			   
+			   
+			   
+			   
+			   
+			       
+			       
+			  
+			   
+			  
+		  
+             
+	   
+	   
+	    
+	     
+	       
+	        
+	        
+
+	         
+	       
+		
+		 
+		 
+		 
+		 
+		 
+		 
+		 
+		 
+		 
+		
+		  
+		
+	
+      
+   
+
+
+
+
+
+
+
+               
+      
+       
+    
+
+
+
+
+           
+	   
+   
+    
+        
+	   
+        
+    
+
+
+
+       
+    
+
+ 
+
+       
+          
+    
+    
+              
+              
+              
+              
+    
+
+    
+    
+    
+
+ 
+
+       
+          
+    
+          
+
+    
+
+
+
+ 
+        
+      
+                              
+                             
+    
+      
+                             
+                             
+
+   
+
+     
+                             
+                             
+   
+
+
+ 
+                                   
+     
+    
+   
+
+
+
+     
+       
+
+
+         
+
+
+
+        
+           
+             
+         
+     
+     
+      
+                 
+                 
+             
+             
+    
+
+
+
+             
+   
+
+
+   
+   
+   
+
+           
+     
+                      
+
+
+
+
+
+
+        
+            
+   
+
+       
+           
+    
+            
+           
+               
+    
+
+     
+   
+
+
+   
+
+       
+          
+     
+          
+
+
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+    
+     
+    
+         
+
+        
+        
+        
+               
+                  
+                
+        
+        
+        
+        
+        
+               
+                  
+               
+            
+                  
+                  
+                  
+            
+                
+                  
+        
+
+        
+        
+        
+              
+               
+            
+                   
+                
+                      
+                      
+                
+            
+        
+        
+                
+    
+
+
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+       
+    
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+   
+
+       
+          
+     
+    
+         
+        
+        
+        
+        
+               
+                  
+        
+
+        
+        
+        
+               
+                    
+        
+        
+                
+    
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+                  
+                    
+                 
+                   
+           
+             
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+                   
+               
+                 
+
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+                      
+                      
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+ 
+                    
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+                    
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+  
+                    
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+                      
+
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+           
+             
+
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+                
+           
+
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+              
+               
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+                    
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+                
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+             
+               
+                 
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+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
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+ 
+                   
+                     
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+ 
+                   
+                     
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+                    
+                     
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+                      
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+ 
+                      
+                    
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+                    
+                     
+                
+ 
+                     
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+ 
+                     
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+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
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+ 
+ 
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+ 
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+
+
+
+                   
+             
+               
+
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+
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+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
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+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
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+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_debug_medium_icache_debug (
+    
+    clk_i, 
+    rst_i,
+    pc_x,
+    load_x,
+    store_x,
+    load_store_address_x,
+    csr_write_enable_x,
+    csr_write_data,
+    csr_x,
+  
+
+  
+
+    jtag_csr_write_enable,
+    jtag_csr_write_data,
+    jtag_csr,
+ 
+
+  
+   
+   
+   
+
+
+  
+
+
+		   
+  
+
+    eret_q_x,
+    bret_q_x,
+    stall_x,
+    exception_x,
+    q_x,
+  
+    
+
+
+ 
+
+
+    
+  
+
+    dc_ss,
+ 
+
+    dc_re,
+    bp_match,
+    wp_match
+    );
+    
+
+
+
+
+parameter breakpoints = 0;                      
+parameter watchpoints = 0;                      
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                      
+input load_x;                                   
+input store_x;                                  
+input [ (32-1):0] load_store_address_x;    
+input csr_write_enable_x;                       
+input [ (32-1):0] csr_write_data;          
+input [ (5-1):0] csr_x;                    
+  
+
+  
+
+input jtag_csr_write_enable;                    
+input [ (32-1):0] jtag_csr_write_data;     
+input [ (5-1):0] jtag_csr;                 
+ 
+
+     
+                          
+            
+                          
+
+
+ 
+
+
+
+  
+
+input eret_q_x;                                 
+input bret_q_x;                                 
+input stall_x;                                  
+input exception_x;                              
+input q_x;                                      
+  
+                     
+
+
+ 
+
+
+
+
+
+
+  
+
+output dc_ss;                                   
+reg    dc_ss;
+ 
+
+output dc_re;                                   
+reg    dc_re;
+output bp_match;                                
+wire   bp_match;        
+output wp_match;                                
+wire   wp_match;
+
+
+
+
+
+genvar i;                                       
+
+
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];       
+reg bp_e[0:breakpoints-1];                      
+wire [0:breakpoints-1]bp_match_n;               
+
+reg [ 1:0] wpc_c[0:watchpoints-1];   
+reg [ (32-1):0] wp[0:watchpoints-1];       
+wire [0:watchpoints-1]wp_match_n;               
+
+wire debug_csr_write_enable;                    
+wire [ (32-1):0] debug_csr_write_data;     
+wire [ (5-1):0] debug_csr;                 
+
+  
+
+
+reg [ 2:0] state;           
+
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+generate
+    for (i = 0; i < breakpoints; i = i + 1)
+    begin : bp_comb
+assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] ==  1'b1));
+    end
+endgenerate
+generate 
+  
+
+    if (breakpoints > 0) 
+assign bp_match = (|bp_match_n) || (state ==  3'b011);
+    else
+assign bp_match = state ==  3'b011;
+ 
+        
+   
+    
+   
+
+
+endgenerate    
+               
+
+generate 
+    for (i = 0; i < watchpoints; i = i + 1)
+    begin : wp_comb
+assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
+    end               
+endgenerate
+generate
+    if (watchpoints > 0) 
+assign wp_match = |wp_match_n;                
+    else
+assign wp_match =  1'b0;
+endgenerate
+                
+  
+                
+
+  
+
+assign debug_csr_write_enable = (csr_write_enable_x ==  1'b1) || (jtag_csr_write_enable ==  1'b1);
+assign debug_csr_write_data = jtag_csr_write_enable ==  1'b1 ? jtag_csr_write_data : csr_write_data;
+assign debug_csr = jtag_csr_write_enable ==  1'b1 ? jtag_csr : csr_x;
+ 
+
+   
+  
+         
+         
+         
+
+
+
+   
+ 
+   
+   
+   
+
+
+
+
+
+
+
+
+generate
+    for (i = 0; i < breakpoints; i = i + 1)
+    begin : bp_seq
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+        bp_e[i] <=  1'b0;
+    end
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h10 + i))
+        begin
+            bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+            bp_e[i] <= debug_csr_write_data[0];
+        end
+    end
+end    
+    end
+endgenerate
+
+
+generate
+    for (i = 0; i < watchpoints; i = i + 1)
+    begin : wp_seq
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        wp[i] <= { 32{1'bx}};
+        wpc_c[i] <=  2'b00;
+    end
+    else
+    begin
+        if (debug_csr_write_enable ==  1'b1)
+        begin
+            if (debug_csr ==  5'h8)
+                wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
+            if (debug_csr ==  5'h18 + i)
+                wp[i] <= debug_csr_write_data;
+        end
+    end  
+end
+    end
+endgenerate
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        dc_re <=  1'b0;
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h8))
+            dc_re <= debug_csr_write_data[1];
+    end
+end    
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  3'b000;
+        dc_ss <=  1'b0;
+    end
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h8))
+        begin
+            dc_ss <= debug_csr_write_data[0];
+            if (debug_csr_write_data[0] ==  1'b0) 
+                state <=  3'b000;
+            else 
+                state <=  3'b001;
+        end
+        case (state)
+         3'b001:
+        begin
+            
+            if (   (   (eret_q_x ==  1'b1)
+                    || (bret_q_x ==  1'b1)
+                    )
+                && (stall_x ==  1'b0)
+               )
+                state <=  3'b010; 
+        end
+         3'b010:
+        begin
+            
+            if ((q_x ==  1'b1) && (stall_x ==  1'b0))
+                state <=  3'b011;
+        end
+         3'b011:
+        begin
+            
+  
+               
+                  
+             
+
+
+                 if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+            begin
+                dc_ss <=  1'b0;
+                state <=  3'b100;
+            end
+        end
+         3'b100:
+        begin
+            
+  
+               
+                  
+             
+
+
+                state <=  3'b000;
+        end
+        endcase
+    end
+end
+ 
+
+
+endmodule
+
+ 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
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+
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+
+
+  
+
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+
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+
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+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_instruction_unit_medium_icache_debug (
+    
+    clk_i,
+    rst_i,
+    
+    stall_a,
+    stall_f,
+    stall_d,
+    stall_x,
+    stall_m,
+    valid_f,
+    valid_d,
+    kill_f,
+    branch_predict_taken_d,
+    branch_predict_address_d,
+      
+    
+    
+
+
+    exception_m,
+    branch_taken_m,
+    branch_mispredict_taken_m,
+    branch_target_m,
+  
+
+    iflush,
+ 
+
+  
+    
+    
+    
+
+        
+  
+
+    
+    i_dat_i,
+    i_ack_i,
+    i_err_i,
+    i_rty_i,
+ 
+
+  
+
+    jtag_read_enable,
+    jtag_write_enable,
+    jtag_write_data,
+    jtag_address,
+ 
+
+    
+    
+    pc_f,
+    pc_d,
+    pc_x,
+    pc_m,
+    pc_w,
+  
+
+    icache_stall_request,
+    icache_restart_request,
+    icache_refill_request,
+    icache_refilling,
+ 
+
+  
+
+    
+    i_dat_o,
+    i_adr_o,
+    i_cyc_o,
+    i_sel_o,
+    i_stb_o,
+    i_we_o,
+    i_cti_o,
+    i_lock_o,
+    i_bte_o,
+ 
+
+  
+    
+    
+    
+
+
+  
+
+    jtag_read_data,
+    jtag_access_complete,
+ 
+
+  
+    
+
+
+  
+
+    instruction_f,
+ 
+    
+    instruction_d
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                   
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam eba_reset_minus_4 = eba_reset - 4;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+  
+  
+   
+        
+   
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_f;                                          
+input stall_d;                                          
+input stall_x;                                          
+input stall_m;                                          
+input valid_f;                                          
+input valid_d;                                          
+input kill_f;                                           
+
+input branch_predict_taken_d;                           
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;          
+   
+      
+                                    
+                     
+
+
+input exception_m;
+input branch_taken_m;                                   
+input branch_mispredict_taken_m;                        
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;                   
+
+  
+
+input iflush;                                           
+ 
+
+  
+                            
+                             
+ 
+
+        
+
+
+  
+
+input [ (32-1):0] i_dat_i;                         
+input i_ack_i;                                          
+input i_err_i;                                          
+input i_rty_i;                                          
+ 
+
+
+  
+
+input jtag_read_enable;                                 
+input jtag_write_enable;                                
+input [ 7:0] jtag_write_data;                 
+input [ (32-1):0] jtag_address;                    
+ 
+
+
+
+
+
+        
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;                             
+reg    [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
+  
+
+output icache_stall_request;                            
+wire   icache_stall_request;
+output icache_restart_request;                          
+wire   icache_restart_request;
+output icache_refill_request;                           
+wire   icache_refill_request;
+output icache_refilling;                                
+wire   icache_refilling;
+ 
+
+
+  
+
+output [ (32-1):0] i_dat_o;                        
+  
+
+reg    [ (32-1):0] i_dat_o;
+ 
+    
+
+
+output [ (32-1):0] i_adr_o;                        
+reg    [ (32-1):0] i_adr_o;
+output i_cyc_o;                                         
+reg    i_cyc_o; 
+output [ (4-1):0] i_sel_o;                 
+  
+
+reg    [ (4-1):0] i_sel_o;
+ 
+    
+
+
+output i_stb_o;                                         
+reg    i_stb_o;
+output i_we_o;                                          
+  
+
+reg    i_we_o;
+ 
+   
+
+
+output [ (3-1):0] i_cti_o;                       
+reg    [ (3-1):0] i_cti_o;
+output i_lock_o;                                        
+reg    i_lock_o;
+output [ (2-1):0] i_bte_o;                       
+wire   [ (2-1):0] i_bte_o;
+ 
+
+
+  
+
+output [ 7:0] jtag_read_data;                 
+reg    [ 7:0] jtag_read_data;
+output jtag_access_complete;                            
+wire   jtag_access_complete;
+ 
+
+
+  
+                                      
+    
+
+
+  
+
+output [ (32-1):0] instruction_f;           
+wire   [ (32-1):0] instruction_f;
+ 
+
+output [ (32-1):0] instruction_d;           
+reg    [ (32-1):0] instruction_d;
+
+
+
+
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;                                
+
+  
+
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;                     
+ 
+
+
+  
+
+wire icache_read_enable_f;                              
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;              
+reg icache_refill_ready;                                
+reg [ (32-1):0] icache_refill_data;         
+wire [ (32-1):0] icache_data_f;             
+wire [ (3-1):0] first_cycle_type;                
+wire [ (3-1):0] next_cycle_type;                 
+wire last_word;                                         
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;                      
+ 
+ 
+                    
+
+
+
+  
+                                      
+    			     
+   
+
+
+  
+
+ 
+               
+
+
+
+   
+  
+   
+    			               
+ 
+
+
+  
+    		       
+
+
+   
+  
+
+reg jtag_access;                                        
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+
+lm32_icache_medium_icache_debug #(
+    .associativity          (associativity),
+    .sets                   (sets),
+    .bytes_per_line         (bytes_per_line),
+    .base_address           (base_address),
+    .limit                  (limit)
+    ) icache ( 
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),      
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .valid_d                (valid_d),
+    .address_a              (pc_a),
+    .address_f              (pc_f),
+    .read_enable_f          (icache_read_enable_f),
+    .refill_ready           (icache_refill_ready),
+    .refill_data            (icache_refill_data),
+    .iflush                 (iflush),
+    
+    .stall_request          (icache_stall_request),
+    .restart_request        (icache_restart_request),
+    .refill_request         (icache_refill_request),
+    .refill_address         (icache_refill_address),
+    .refilling              (icache_refilling),
+    .inst                   (icache_data_f)
+    );
+ 
+
+
+
+
+
+
+  
+
+   
+   assign icache_read_enable_f =    (valid_f ==  1'b1)
+     && (kill_f ==  1'b0)
+   
+      
+ 
+                         
+    
+				       
+ 
+       
+				    ;
+ 
+ 
+
+
+always @(*)
+begin
+    
+  
+       
+          
+     
+
+    
+      if (branch_taken_m ==  1'b1)
+	if ((branch_mispredict_taken_m ==  1'b1) && (exception_m ==  1'b0))
+	  pc_a = pc_x;
+	else
+          pc_a = branch_target_m;
+      
+          
+          
+
+
+      else
+	if ( (valid_d ==  1'b1) && (branch_predict_taken_d ==  1'b1) )
+	  pc_a = branch_predict_address_d;
+	else
+  
+
+          if (icache_restart_request ==  1'b1)
+            pc_a = restart_address;
+	  else 
+ 
+        
+            pc_a = pc_f + 1'b1;
+end
+
+
+  
+      
+      
+        
+
+
+
+  
+
+     
+    	      
+
+     
+      
+	  
+       
+	  
+	
+	    
+     
+   
+   
+          
+
+
+  
+   
+
+
+                     
+
+  
+
+assign instruction_f = icache_data_f;
+ 
+   
+
+
+
+ 
+ 
+   
+
+  
+
+  
+
+ 
+   
+   
+   
+
+
+assign i_bte_o =  2'b00;
+ 
+
+
+  
+
+
+generate
+    case (bytes_per_line)
+    4:
+    begin
+assign first_cycle_type =  3'b111;
+assign next_cycle_type =  3'b111;
+assign last_word =  1'b1;
+assign first_address = icache_refill_address;
+    end
+    8:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type =  3'b111;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    16:
+    begin
+assign first_cycle_type =  3'b010;
+assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ?  3'b111 :  3'b010;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+    end
+    endcase
+endgenerate
+ 
+
+                     
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        pc_f <= eba_reset_minus_4[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+        pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+        pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    end
+    else
+    begin
+        if (stall_f ==  1'b0)
+            pc_f <= pc_a;
+        if (stall_d ==  1'b0)
+            pc_d <= pc_f;
+        if (stall_x ==  1'b0)
+            pc_x <= pc_d;
+        if (stall_m ==  1'b0)
+            pc_m <= pc_x;
+        pc_w <= pc_m;
+    end
+end
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+    else
+    begin
+  
+         
+            
+               
+                  
+                    
+                  
+
+               
+                  
+
+
+
+  
+        
+            if (icache_refill_request ==  1'b1)
+                restart_address <= icache_refill_address;
+ 
+
+ 
+
+    end
+end
+ 
+
+
+
+  
+   
+
+       
+          
+    
+    
+           
+              
+    
+
+
+
+
+  
+
+     
+
+assign jtag_access_complete = (i_cyc_o ==  1'b1) && ((i_ack_i ==  1'b1) || (i_err_i ==  1'b1)) && (jtag_access ==  1'b1);
+always @(*)
+begin
+    case (jtag_address[1:0])
+    2'b00: jtag_read_data = i_dat_i[ 31:24];
+    2'b01: jtag_read_data = i_dat_i[ 23:16];
+    2'b10: jtag_read_data = i_dat_i[ 15:8];
+    2'b11: jtag_read_data = i_dat_i[ 7:0];
+    endcase 
+end
+    
+
+ 
+
+
+  
+
+   
+   
+                
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             i_cyc_o <=  1'b0;
+             i_stb_o <=  1'b0;
+             i_adr_o <= { 32{1'b0}};
+             i_cti_o <=  3'b111;
+             i_lock_o <=  1'b0;
+             icache_refill_data <= { 32{1'b0}};
+             icache_refill_ready <=  1'b0;
+    
+               
+  
+
+    
+
+             i_we_o <=  1'b0;
+             i_sel_o <= 4'b1111;
+             jtag_access <=  1'b0;
+   
+
+	  end
+	else
+	  begin   
+             icache_refill_ready <=  1'b0;
+             
+             if (i_cyc_o ==  1'b1)
+               begin
+		  
+		  if ((i_ack_i ==  1'b1) || (i_err_i ==  1'b1))
+		    begin
+    
+
+                       if (jtag_access ==  1'b1)
+			 begin
+			    i_cyc_o <=  1'b0;
+			    i_stb_o <=  1'b0;       
+			    i_we_o <=  1'b0;  
+			    jtag_access <=  1'b0;    
+			 end
+                       else
+   
+
+			 begin
+			    if (last_word ==  1'b1)
+			      begin
+				 
+				 i_cyc_o <=  1'b0;
+				 i_stb_o <=  1'b0;
+				 i_lock_o <=  1'b0;
+			      end
+			    
+			    i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
+			    i_cti_o <= next_cycle_type;
+			    
+			    icache_refill_ready <=  1'b1;
+			    icache_refill_data <= i_dat_i;
+			 end
+		    end
+    
+		   
+		     
+		    
+                         
+                         
+		    
+		  
+  
+
+               end
+             else
+               begin
+		  if ((icache_refill_request ==  1'b1) && (icache_refill_ready ==  1'b0))
+		    begin
+                       
+    
+     
+                       i_sel_o <= 4'b1111;
+   
+
+                       i_adr_o <= {first_address, 2'b00};
+                       i_cyc_o <=  1'b1;
+                       i_stb_o <=  1'b1;                
+                       i_cti_o <= first_cycle_type;
+                       
+    
+                         
+  
+
+		    end
+    
+
+		  else
+		    begin
+                       if ((jtag_read_enable ==  1'b1) || (jtag_write_enable ==  1'b1))
+			 begin
+			    case (jtag_address[1:0])
+			      2'b00: i_sel_o <= 4'b1000;
+			      2'b01: i_sel_o <= 4'b0100;
+			      2'b10: i_sel_o <= 4'b0010;
+			      2'b11: i_sel_o <= 4'b0001;
+			    endcase
+			    i_adr_o <= jtag_address;
+			    i_dat_o <= {4{jtag_write_data}};
+			    i_cyc_o <=  1'b1;
+			    i_stb_o <=  1'b1;
+			    i_we_o <= jtag_write_enable;
+			    i_cti_o <=  3'b111;
+			    jtag_access <=  1'b1;
+			 end
+		    end 
+   
+                    
+    
+		  
+		  
+        
+		     
+                      
+   
+		     
+                      
+  
+
+               end
+	  end
+     end
+  
+      
+     
+	   
+	  
+               
+               
+               
+               
+               
+               
+   
+               
+  
+	  
+	
+	     
+             
+                
+               
+		  
+		        
+		    
+                       
+                         
+                         
+                       
+                         
+		    
+   
+		   
+		     
+		    
+                         
+                         
+		       
+		    
+		  
+  
+               
+             
+               
+		  
+		         
+    
+			    
+         
+			 
+		    
+                       
+        
+                         
+  
+                          
+                         
+                         
+   
+                         
+  
+		    
+		  
+		    
+	                      
+    
+			         
+         
+			      
+			 
+   
+			      
+  
+			 
+		    
+               
+	  
+     
+ 
+
+ 
+ 
+
+   
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             instruction_d <= { 32{1'b0}};
+  
+               
+
+
+	  end
+	else
+	  begin
+             if (stall_d ==  1'b0)
+               begin
+		  instruction_d <= instruction_f;
+  
+		    
+
+
+               end
+	  end
+     end  
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_jtag_medium_icache_debug (
+    
+    clk_i,
+    rst_i,
+    jtag_clk, 
+    jtag_update,
+    jtag_reg_q,
+    jtag_reg_addr_q,
+  
+
+    csr,
+    csr_write_enable,
+    csr_write_data,
+    stall_x,
+ 
+
+  
+
+    jtag_read_data,
+    jtag_access_complete,
+ 
+
+  
+
+    exception_q_w,
+ 
+
+    
+  
+
+    jtx_csr_read_data,
+    jrx_csr_read_data,
+ 
+
+  
+
+    jtag_csr_write_enable,
+    jtag_csr_write_data,
+    jtag_csr,
+    jtag_read_enable,
+    jtag_write_enable,
+    jtag_write_data,
+    jtag_address,
+ 
+
+  
+
+    jtag_break,
+    jtag_reset,
+ 
+
+    jtag_reg_d,
+    jtag_reg_addr_d
+    );
+
+
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input jtag_clk;                                         
+input jtag_update;                                      
+input [ 7:0] jtag_reg_q;                      
+input [2:0] jtag_reg_addr_q;                            
+
+  
+
+input [ (5-1):0] csr;                              
+input csr_write_enable;                                 
+input [ (32-1):0] csr_write_data;                  
+input stall_x;                                          
+ 
+
+  
+
+input [ 7:0] jtag_read_data;                  
+input jtag_access_complete;                             
+ 
+
+  
+
+input exception_q_w;                                    
+ 
+
+
+
+
+
+       
+  
+
+output [ (32-1):0] jtx_csr_read_data;              
+wire   [ (32-1):0] jtx_csr_read_data;
+output [ (32-1):0] jrx_csr_read_data;              
+wire   [ (32-1):0] jrx_csr_read_data;
+ 
+
+  
+
+output jtag_csr_write_enable;                           
+reg    jtag_csr_write_enable;
+output [ (32-1):0] jtag_csr_write_data;            
+wire   [ (32-1):0] jtag_csr_write_data;
+output [ (5-1):0] jtag_csr;                        
+wire   [ (5-1):0] jtag_csr;
+output jtag_read_enable;                                
+reg    jtag_read_enable;
+output jtag_write_enable;                               
+reg    jtag_write_enable;
+output [ 7:0] jtag_write_data;                
+wire   [ 7:0] jtag_write_data;        
+output [ (32-1):0] jtag_address;                   
+wire   [ (32-1):0] jtag_address;
+ 
+
+  
+
+output jtag_break;                                      
+reg    jtag_break;
+output jtag_reset;                                      
+reg    jtag_reset;
+ 
+
+output [ 7:0] jtag_reg_d;
+reg    [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire   [2:0] jtag_reg_addr_d;
+             
+
+
+
+
+reg rx_update;                          
+reg rx_update_r;                        
+reg rx_update_r_r;                      
+reg rx_update_r_r_r;                    
+
+
+
+wire [ 7:0] rx_byte;   
+wire [2:0] rx_addr;
+
+  
+                 
+reg [ 7:0] uart_tx_byte;      
+reg uart_tx_valid;                      
+reg [ 7:0] uart_rx_byte;      
+reg uart_rx_valid;                      
+ 
+
+
+reg [ 3:0] command;             
+  
+
+reg [ 7:0] jtag_byte_0;       
+reg [ 7:0] jtag_byte_1;
+reg [ 7:0] jtag_byte_2;
+reg [ 7:0] jtag_byte_3;
+reg [ 7:0] jtag_byte_4;
+reg processing;                         
+ 
+
+
+reg [ 3:0] state;       
+
+
+
+
+
+  
+
+assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_csr = jtag_byte_4[ (5-1):0];
+assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_write_data = jtag_byte_4;
+ 
+
+                 
+
+  
+                 
+assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};         
+ 
+   
+
+
+  
+
+assign jtag_reg_addr_d[2] = processing;
+ 
+   
+
+
+
+  
+                 
+assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00};
+assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
+ 
+         
+                 
+
+
+
+
+assign rx_byte = jtag_reg_q;
+assign rx_addr = jtag_reg_addr_q;
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        rx_update <= 1'b0;
+        rx_update_r <= 1'b0;
+        rx_update_r_r <= 1'b0;
+        rx_update_r_r_r <= 1'b0;
+    end
+    else
+    begin
+        rx_update <= jtag_update;
+        rx_update_r <= rx_update;
+        rx_update_r_r <= rx_update_r;
+        rx_update_r_r_r <= rx_update_r_r;
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  4'h0;
+        command <= 4'b0000;
+        jtag_reg_d <= 8'h00;
+  
+
+        processing <=  1'b0;
+        jtag_csr_write_enable <=  1'b0;
+        jtag_read_enable <=  1'b0;
+        jtag_write_enable <=  1'b0;
+ 
+
+  
+
+        jtag_break <=  1'b0;
+        jtag_reset <=  1'b0;
+ 
+
+  
+                 
+        uart_tx_byte <= 8'h00;
+        uart_tx_valid <=  1'b0;
+        uart_rx_byte <= 8'h00;
+        uart_rx_valid <=  1'b0;
+ 
+
+    end
+    else
+    begin
+  
+                 
+        if ((csr_write_enable ==  1'b1) && (stall_x ==  1'b0))
+        begin
+            case (csr)
+             5'he:
+            begin
+                
+                uart_tx_byte <= csr_write_data[ 7:0];
+                uart_tx_valid <=  1'b1;
+            end
+             5'hf:
+            begin
+                
+                uart_rx_valid <=  1'b0;
+            end
+            endcase
+        end
+ 
+
+  
+
+        
+        if (exception_q_w ==  1'b1)
+        begin
+            jtag_break <=  1'b0;
+            jtag_reset <=  1'b0;
+        end
+ 
+
+        case (state)
+         4'h0:
+        begin
+            
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                command <= rx_byte[7:4];                
+                case (rx_addr)
+  
+
+                 3'b000:
+                begin
+                    case (rx_byte[7:4])
+  
+
+                     4'b0001:
+                        state <=  4'h1;
+                     4'b0011:
+                    begin
+                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+                        state <=  4'h6;
+                    end
+                     4'b0010:
+                        state <=  4'h1;
+                     4'b0100:
+                    begin
+                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+                        state <= 5;
+                    end
+                     4'b0101:
+                        state <=  4'h1;
+ 
+                    
+                     4'b0110:
+                    begin
+  
+     
+                        uart_rx_valid <=  1'b0;    
+                        uart_tx_valid <=  1'b0;         
+ 
+
+                        jtag_break <=  1'b1;
+                    end
+                     4'b0111:
+                    begin
+  
+     
+                        uart_rx_valid <=  1'b0;    
+                        uart_tx_valid <=  1'b0;         
+ 
+
+                        jtag_reset <=  1'b1;
+                    end
+                    endcase                               
+                end
+ 
+
+  
+                 
+                 3'b001:
+                begin
+                    uart_rx_byte <= rx_byte;
+                    uart_rx_valid <=  1'b1;
+                end                    
+                 3'b010:
+                begin
+                    jtag_reg_d <= uart_tx_byte;
+                    uart_tx_valid <=  1'b0;
+                end
+ 
+
+                default:
+                    ;
+                endcase                
+            end
+        end
+  
+
+         4'h1:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_0 <= rx_byte;
+                state <=  4'h2;
+            end
+        end
+         4'h2:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_1 <= rx_byte;
+                state <=  4'h3;
+            end
+        end
+         4'h3:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_2 <= rx_byte;
+                state <=  4'h4;
+            end
+        end
+         4'h4:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_3 <= rx_byte;
+                if (command ==  4'b0001)
+                    state <=  4'h6;
+                else 
+                    state <=  4'h5;
+            end
+        end
+         4'h5:
+        begin
+            if ((~rx_update_r_r_r & rx_update_r_r) ==  1'b1)
+            begin
+                jtag_byte_4 <= rx_byte;
+                state <=  4'h6;
+            end
+        end
+         4'h6:
+        begin
+            case (command)
+             4'b0001,
+             4'b0011:
+            begin
+                jtag_read_enable <=  1'b1;
+                processing <=  1'b1;
+                state <=  4'h7;
+            end
+             4'b0010,
+             4'b0100:
+            begin
+                jtag_write_enable <=  1'b1;
+                processing <=  1'b1;
+                state <=  4'h7;
+            end
+             4'b0101:
+            begin
+                jtag_csr_write_enable <=  1'b1;
+                processing <=  1'b1;
+                state <=  4'h8;
+            end
+            endcase
+        end
+         4'h7:
+        begin
+            if (jtag_access_complete ==  1'b1)
+            begin          
+                jtag_read_enable <=  1'b0;
+                jtag_reg_d <= jtag_read_data;
+                jtag_write_enable <=  1'b0;  
+                processing <=  1'b0;
+                state <=  4'h0;
+            end
+        end    
+         4'h8:
+        begin
+            jtag_csr_write_enable <=  1'b0;
+            processing <=  1'b0;
+            state <=  4'h0;
+        end    
+ 
+
+        endcase
+    end
+end
+  
+endmodule
+
+ 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+  
+
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+
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+
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+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
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+ 
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+ 
+
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+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_interrupt_medium_icache_debug (
+    
+    clk_i, 
+    rst_i,
+    
+    interrupt,
+    
+    stall_x,
+  
+
+    non_debug_exception,
+    debug_exception,
+ 
+    
+
+
+    eret_q_x,
+  
+
+    bret_q_x,
+ 
+
+    csr,
+    csr_write_data,
+    csr_write_enable,
+    
+    interrupt_exception,
+    
+    csr_read_data
+    );
+
+
+
+
+
+parameter interrupts =  32;         
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [interrupts-1:0] interrupt;               
+
+input stall_x;                                  
+
+  
+
+input non_debug_exception;                      
+input debug_exception;                          
+ 
+                                 
+
+
+input eret_q_x;                                 
+  
+
+input bret_q_x;                                 
+ 
+
+
+input [ (5-1):0] csr;                      
+input [ (32-1):0] csr_write_data;          
+input csr_write_enable;                         
+
+
+
+
+
+output interrupt_exception;                     
+wire   interrupt_exception;
+
+output [ (32-1):0] csr_read_data;          
+reg    [ (32-1):0] csr_read_data;
+
+
+
+
+
+wire [interrupts-1:0] asserted;                 
+
+wire [interrupts-1:0] interrupt_n_exception;
+
+
+
+reg ie;                                         
+reg eie;                                        
+  
+
+reg bie;                                        
+ 
+
+reg [interrupts-1:0] ip;                        
+reg [interrupts-1:0] im;                        
+
+
+
+
+
+
+assign interrupt_n_exception = ip & im;
+
+
+assign interrupt_exception = (|interrupt_n_exception) & ie;
+
+
+assign asserted = ip | interrupt;
+       
+generate
+    if (interrupts > 1) 
+    begin
+
+always @(*)
+begin
+    case (csr)
+     5'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+
+                                    bie,
+ 
+                                                                         
+
+
+                                    eie, 
+                                    ie
+                                   };
+     5'h2:  csr_read_data = ip;
+     5'h1:  csr_read_data = im;
+    default:       csr_read_data = { 32{1'bx}};
+    endcase
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    case (csr)
+     5'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+
+                                    bie, 
+ 
+                                                                        
+
+
+                                    eie, 
+                                    ie
+                                   };
+     5'h2:  csr_read_data = ip;
+    default:       csr_read_data = { 32{1'bx}};
+      endcase
+end
+    end
+endgenerate
+    
+
+
+
+
+  
+
+   reg [ 10:0] eie_delay  = 0;
+
+   
+generate
+
+   
+    if (interrupts > 1)
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie                   <=  1'b0;
+        eie                  <=  1'b0;
+  
+
+        bie                  <=  1'b0;
+ 
+
+        im                   <= {interrupts{1'b0}};
+        ip                   <= {interrupts{1'b0}};
+       eie_delay             <= 0;
+       
+    end
+    else
+    begin
+        
+        ip                   <= asserted;
+  
+
+        if (non_debug_exception ==  1'b1)
+        begin
+            
+            eie              <= ie;
+            ie               <=  1'b0;
+        end
+        else if (debug_exception ==  1'b1)
+        begin
+            
+            bie              <= ie;
+            ie               <=  1'b0;
+        end
+ 
+           
+        
+            
+                           
+                            
+        
+
+
+        else if (stall_x ==  1'b0)
+        begin
+
+           if(eie_delay[0])
+             ie              <= eie;
+           
+           eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+            if (eret_q_x ==  1'b1) begin
+                
+               eie_delay[ 10] <=  1'b1;
+               eie_delay[ 10-1:0] <= 0;
+            end
+           
+                      
+           
+  
+
+            else if (bret_q_x ==  1'b1)
+                
+                ie      <= bie;
+ 
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  5'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+
+                    bie <= csr_write_data[2];
+ 
+
+                end
+                if (csr ==  5'h1)
+                    im  <= csr_write_data[interrupts-1:0];
+                if (csr ==  5'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+else
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie              <=  1'b0;
+        eie             <=  1'b0;
+  
+
+        bie             <=  1'b0;
+ 
+
+        ip              <= {interrupts{1'b0}};
+       eie_delay        <= 0;
+    end
+    else
+    begin
+        
+        ip              <= asserted;
+  
+
+        if (non_debug_exception ==  1'b1)
+        begin
+            
+            eie         <= ie;
+            ie          <=  1'b0;
+        end
+        else if (debug_exception ==  1'b1)
+        begin
+            
+            bie         <= ie;
+            ie          <=  1'b0;
+        end
+ 
+           
+        
+            
+                      
+                       
+        
+
+
+        else if (stall_x ==  1'b0)
+          begin
+
+             if(eie_delay[0])
+               ie              <= eie;
+           
+             eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+             if (eret_q_x ==  1'b1) begin
+                
+                eie_delay[ 10] <=  1'b1;
+                eie_delay[ 10-1:0] <= 0;
+             end
+           
+  
+
+            else if (bret_q_x ==  1'b1)
+                
+                ie      <= bie;
+ 
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  5'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+
+                    bie <= csr_write_data[2];
+ 
+
+                end
+                if (csr ==  5'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+  
+
+  
+
+  
+
+  
+
+  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
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+	  
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+	  
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+	  
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+	  
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+	  
+
+	  
+	 
+	 
+	 
+	 
+	
+
+ 
+
+
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+  
+
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+  
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+
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+
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+  
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+  
+
+  
+
+
+
+  
+                    
+
+
+  
+
+  
+
+ 
+  
+                    
+
+
+ 
+
+  
+
+
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+  
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+
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+ 
+
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+ 
+
+ 
+
+
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+  
+ 
+
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+  
+ 
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+  
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+ 
+
+ 
+ 
+
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+  
+ 
+
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+  
+ 
+
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+ 
+
+
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+  
+ 
+
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+  
+ 
+
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+ 
+
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+  
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+ 
+
+  
+ 
+
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+  
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+  
+
+
+
+  
+                   
+                     
+
+
+  
+                   
+                     
+
+
+  
+
+  
+
+ 
+
+ 
+
+
+
+  
+
+  
+
+  
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+  
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+  
+
+  
+
+  
+
+  
+
+  
+                      
+                    
+
+
+  
+
+  
+
+  
+
+  
+                     
+                     
+
+
+  
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+
+ 
+
+
+  
+
+  
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+  
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+ 
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+ 
+
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+
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+  
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+  
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+  
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+  
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+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+ 
+
+
+
+
+
+
+
+
+module lm32_top_minimal (
+    
+    clk_i,
+    rst_i,
+    
+
+    interrupt,
+
+    
+  
+    
+    
+
+     
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+    );
+
+parameter eba_reset = 32'h00000000;
+parameter sdb_address = 32'h00000000;
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+
+input [ (32-1):0] interrupt;          
+
+
+  
+               
+                             
+
+    
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+  
+
+
+
+ 
+  
+
+  
+  
+ 
+  
+  
+ 
+ 
+
+
+
+
+  
+
+                     
+                             
+                            
+                   
+                                 
+ 
+                                 
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+   
+
+lm32_cpu_minimal 
+	#(
+		.eba_reset(eba_reset),
+    .sdb_address(sdb_address)
+	) cpu (
+    
+    .clk_i                 (clk_i),
+  
+                   
+
+
+    .rst_i                 (rst_i),
+    
+  
+
+    .interrupt             (interrupt),
+ 
+
+    
+  
+               
+             
+
+     
+  
+    
+                  
+               
+                
+           
+
+
+  
+
+     
+    .I_DAT_I               (I_DAT_I),
+    .I_ACK_I               (I_ACK_I),
+    .I_ERR_I               (I_ERR_I),
+    .I_RTY_I               (I_RTY_I),
+ 
+
+    
+    .D_DAT_I               (D_DAT_I),
+    .D_ACK_I               (D_ACK_I),
+    .D_ERR_I               (D_ERR_I),
+    .D_RTY_I               (D_RTY_I),
+    
+  
+                  
+            
+           
+                 
+                
+ 
+                
+
+
+
+  
+                
+           
+
+
+      
+                
+               
+            
+            
+
+    
+  
+
+    
+    .I_DAT_O               (I_DAT_O),
+    .I_ADR_O               (I_ADR_O),
+    .I_CYC_O               (I_CYC_O),
+    .I_SEL_O               (I_SEL_O),
+    .I_STB_O               (I_STB_O),
+    .I_WE_O                (I_WE_O),
+    .I_CTI_O               (I_CTI_O),
+    .I_LOCK_O              (I_LOCK_O),
+    .I_BTE_O               (I_BTE_O),
+     
+
+    
+    .D_DAT_O               (D_DAT_O),
+    .D_ADR_O               (D_ADR_O),
+    .D_CYC_O               (D_CYC_O),
+    .D_SEL_O               (D_SEL_O),
+    .D_STB_O               (D_STB_O),
+    .D_WE_O                (D_WE_O),
+    .D_CTI_O               (D_CTI_O),
+    .D_LOCK_O              (D_LOCK_O),
+    .D_BTE_O               (D_BTE_O)
+    );
+   
+  		   
+
+  
+    
+                     
+                
+    
+                
+                     
+                
+                      
+                     
+    
+
+        
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+           
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_mc_arithmetic_minimal (
+    
+    clk_i,
+    rst_i,
+    stall_d,
+    kill_x,
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+    
+
+
+    operand_0_d,
+    operand_1_d,
+    
+    result_x,
+  
+    
+
+
+    stall_request_x
+    );
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+input stall_d;                                  
+input kill_x;                                   
+  
+                                  
+                                 
+
+
+  
+                                
+
+
+  
+                              
+                             
+                             
+
+
+input [ (32-1):0] operand_0_d;
+input [ (32-1):0] operand_1_d;
+
+
+
+
+
+output [ (32-1):0] result_x;               
+reg    [ (32-1):0] result_x;
+  
+                         
+    
+
+
+output stall_request_x;                         
+wire   stall_request_x;
+
+
+
+
+
+reg [ (32-1):0] p;                         
+reg [ (32-1):0] a;
+reg [ (32-1):0] b;
+  
+  
+
+
+
+reg [ 2:0] state;                 
+reg [5:0] cycles;                               
+
+  
+                               
+                                 
+
+
+
+
+
+
+
+
+assign stall_request_x = state !=  3'b000;
+
+  
+
+      
+
+
+
+  
+
+       
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        cycles <= {6{1'b0}};
+        p <= { 32{1'b0}};
+        a <= { 32{1'b0}};
+        b <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+        result_x <= { 32{1'b0}};
+        state <=  3'b000;
+    end
+    else
+    begin
+  
+          
+
+
+        case (state)
+         3'b000:
+        begin
+            if (stall_d ==  1'b0)                 
+            begin          
+                cycles <=  32;
+                p <= 32'b0;
+                a <= operand_0_d;
+                b <= operand_1_d;                    
+  
+                   
+                      
+                   
+                      
+
+                    
+  
+                   
+                      
+
+
+  
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+
+
+            end            
+        end
+  
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+        
+        
+               
+            
+                  
+                   
+            
+             
+            
+                   
+                   
+            
+              
+                   
+            
+                
+                    
+                  
+            
+                
+        
+
+        
+  
+        
+        
+               
+                    
+               
+               
+              
+                   
+                  
+                
+        
+
+     
+  
+        
+               
+               
+              
+                   
+                  
+                
+        
+        
+               
+               
+              
+                   
+                  
+                
+        
+
+   
+        endcase
+    end
+end 
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_cpu_minimal (
+    
+    clk_i,
+  
+    
+
+
+    rst_i,
+  
+    
+
+
+  
+   
+   
+   
+   
+   
+   
+
+
+
+    
+  
+
+    interrupt,
+ 
+
+    
+  
+    
+    
+
+     
+  
+    
+    
+     
+    
+    
+
+
+  
+
+    
+    I_DAT_I,
+    I_ACK_I,
+    I_ERR_I,
+    I_RTY_I,
+ 
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+  
+    
+    
+    
+    
+    
+ 
+    
+
+
+
+  
+    
+    
+
+
+      
+    
+    
+    
+    
+
+    
+  
+
+    
+    I_DAT_O,
+    I_ADR_O,
+    I_CYC_O,
+    I_SEL_O,
+    I_STB_O,
+    I_WE_O,
+    I_CTI_O,
+    I_LOCK_O,
+    I_BTE_O,
+ 
+ 
+  
+    
+    
+    
+    
+    
+    
+    
+    
+           
+
+
+		 
+		 
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+
+		 
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                           
+  
+                            
+
+
+parameter sdb_address =   32'h00000000;
+
+  
+        
+                          
+      
+          
+                        
+
+
+parameter icache_associativity = 1;    
+parameter icache_sets = 512;                      
+parameter icache_bytes_per_line = 16;  
+parameter icache_base_address = 0;      
+parameter icache_limit = 0;                    
+ 
+
+
+  
+        
+                          
+      
+          
+                        
+
+
+parameter dcache_associativity = 1;    
+parameter dcache_sets = 512;                      
+parameter dcache_bytes_per_line = 16;  
+parameter dcache_base_address = 0;      
+parameter dcache_limit = 0;                    
+ 
+
+
+  
+                          
+
+
+parameter watchpoints = 0;
+ 
+
+  
+                          
+
+
+parameter breakpoints = 0;
+ 
+
+
+  
+
+parameter interrupts =  32;                         
+ 
+   
+
+
+
+
+
+
+
+input clk_i;                                    
+  
+                                   
+
+    
+input rst_i;                                    
+
+  
+
+input [ (32-1):0] interrupt;          
+ 
+
+
+  
+               
+                             
+
+    
+
+   
+                                  
+                               
+                
+  
+
+
+
+  
+
+input [ (32-1):0] I_DAT_I;                 
+input I_ACK_I;                                  
+input I_ERR_I;                                  
+input I_RTY_I;                                  
+ 
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+    
+     
+
+
+   
+   
+  
+                   
+     
+                           
+    
+                          
+    
+                 
+     
+                               
+    
+ 
+                               
+    
+
+
+
+
+  
+  
+    
+  
+    
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+
+output [ (32-1):0] I_DAT_O;                
+wire   [ (32-1):0] I_DAT_O;
+output [ (32-1):0] I_ADR_O;                
+wire   [ (32-1):0] I_ADR_O;
+output I_CYC_O;                                 
+wire   I_CYC_O;
+output [ (4-1):0] I_SEL_O;         
+wire   [ (4-1):0] I_SEL_O;
+output I_STB_O;                                 
+wire   I_STB_O;
+output I_WE_O;                                  
+wire   I_WE_O;
+output [ (3-1):0] I_CTI_O;               
+wire   [ (3-1):0] I_CTI_O;
+output I_LOCK_O;                                
+wire   I_LOCK_O;
+output [ (2-1):0] I_BTE_O;               
+wire   [ (2-1):0] I_BTE_O;
+ 
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+
+  
+      
+     
+       
+      
+             
+
+
+   
+
+
+
+
+
+
+  
+                                     
+
+
+reg valid_f;                                    
+reg valid_d;                                    
+reg valid_x;                                    
+reg valid_m;                                    
+reg valid_w;                                    
+   
+wire q_x;
+wire [ (32-1):0] immediate_d;              
+wire load_d;                                    
+reg load_x;                                     
+reg load_m;
+wire load_q_x;
+wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
+wire store_d;                                   
+reg store_x;
+reg store_m;
+wire [ 1:0] size_d;                   
+reg [ 1:0] size_x;
+wire branch_d;                                  
+wire branch_predict_d;                          
+wire branch_predict_taken_d;                    
+wire [ ((32-2)+2-1):2] branch_predict_address_d;   
+wire [ ((32-2)+2-1):2] branch_target_d;
+wire bi_unconditional;
+wire bi_conditional;
+reg branch_x;                                   
+reg branch_predict_x;
+reg branch_predict_taken_x;
+reg branch_m;
+reg branch_predict_m;
+reg branch_predict_taken_m;
+wire branch_mispredict_taken_m;                 
+wire branch_flushX_m;                           
+wire branch_reg_d;                              
+wire [ ((32-2)+2-1):2] branch_offset_d;            
+reg [ ((32-2)+2-1):2] branch_target_x;             
+reg [ ((32-2)+2-1):2] branch_target_m;
+wire [ 0:0] d_result_sel_0_d; 
+wire [ 1:0] d_result_sel_1_d; 
+
+wire x_result_sel_csr_d;                        
+reg x_result_sel_csr_x;
+  
+ 
+                    
+ 
+
+
+  
+    
+wire x_result_sel_shift_d;                      
+reg x_result_sel_shift_x;
+ 
+
+  
+                        
+ 
+
+
+wire x_result_sel_logic_d;                      
+  
+                        
+ 
+
+
+wire x_result_sel_add_d;                        
+reg x_result_sel_add_x;
+wire m_result_sel_compare_d;                    
+reg m_result_sel_compare_x;
+reg m_result_sel_compare_m;
+  
+                       
+ 
+ 
+
+
+wire w_result_sel_load_d;                       
+reg w_result_sel_load_x;
+reg w_result_sel_load_m;
+reg w_result_sel_load_w;
+  
+                         
+ 
+ 
+ 
+
+
+wire x_bypass_enable_d;                         
+reg x_bypass_enable_x;                          
+wire m_bypass_enable_d;                         
+reg m_bypass_enable_x;                          
+reg m_bypass_enable_m;
+wire sign_extend_d;                             
+reg sign_extend_x;
+wire write_enable_d;                            
+reg write_enable_x;
+wire write_enable_q_x;
+reg write_enable_m;
+wire write_enable_q_m;
+reg write_enable_w;
+wire write_enable_q_w;
+wire read_enable_0_d;                           
+wire [ (5-1):0] read_idx_0_d;          
+wire read_enable_1_d;                           
+wire [ (5-1):0] read_idx_1_d;          
+wire [ (5-1):0] write_idx_d;           
+reg [ (5-1):0] write_idx_x;            
+reg [ (5-1):0] write_idx_m;
+reg [ (5-1):0] write_idx_w;
+wire [ (4 -1):0] csr_d;                     
+reg  [ (4 -1):0] csr_x;                  
+wire [ (3-1):0] condition_d;         
+reg [ (3-1):0] condition_x;          
+  
+                                    
+                                     
+
+
+wire scall_d;                                   
+reg scall_x;    
+wire eret_d;                                    
+reg eret_x;
+wire eret_q_x;
+  
+ 
+ 
+
+
+  
+                                     
+ 
+ 
+ 
+ 
+ 
+
+
+
+wire csr_write_enable_d;                        
+reg csr_write_enable_x;
+wire csr_write_enable_q_x;
+  
+       
+
+
+
+  
+                                
+ 
+ 
+  
+
+
+
+reg [ (32-1):0] d_result_0;                
+reg [ (32-1):0] d_result_1;                
+reg [ (32-1):0] x_result;                  
+reg [ (32-1):0] m_result;                  
+reg [ (32-1):0] w_result;                  
+
+reg [ (32-1):0] operand_0_x;               
+reg [ (32-1):0] operand_1_x;               
+reg [ (32-1):0] store_operand_x;           
+reg [ (32-1):0] operand_m;                 
+reg [ (32-1):0] operand_w;                 
+
+
+  
+
+reg [ (32-1):0] reg_data_live_0;          
+reg [ (32-1):0] reg_data_live_1;  
+reg use_buf;                                    
+reg [ (32-1):0] reg_data_buf_0;
+reg [ (32-1):0] reg_data_buf_1;
+ 
+
+  
+
+ 
+     
+
+
+wire [ (32-1):0] reg_data_0;               
+wire [ (32-1):0] reg_data_1;               
+reg [ (32-1):0] bypass_data_0;             
+reg [ (32-1):0] bypass_data_1;             
+wire reg_write_enable_q_w;
+
+reg interlock;                                  
+
+wire stall_a;                                   
+wire stall_f;                                   
+wire stall_d;                                   
+wire stall_x;                                   
+wire stall_m;                                   
+
+
+wire adder_op_d;                                
+reg adder_op_x;                                 
+reg adder_op_x_n;                               
+wire [ (32-1):0] adder_result_x;           
+wire adder_overflow_x;                          
+wire adder_carry_n_x;                           
+
+
+wire [ 3:0] logic_op_d;           
+reg [ 3:0] logic_op_x;            
+wire [ (32-1):0] logic_result_x;           
+
+  
+
+             
+             
+              
+
+
+
+
+  
+ 
+                                   
+                                     
+
+                                
+                                         
+           
+
+
+  
+                               
+ 
+                              
+ 
+
+
+  
+
+wire [ (32-1):0] shifter_result_x;         
+ 
+
+
+
+  
+        
+
+
+  
+                                 
+ 
+
+
+
+
+  
+                                   
+ 
+ 
+ 
+                           
+
+
+
+
+  
+                         
+  
+
+
+
+
+  
+
+wire [ (32-1):0] interrupt_csr_read_data_x;
+ 
+
+wire [ (32-1):0] cfg;                      
+wire [ (32-1):0] cfg2;                     
+  
+                          
+
+
+reg [ (32-1):0] csr_read_data_x;           
+
+
+wire [ ((32-2)+2-1):2] pc_f;                       
+wire [ ((32-2)+2-1):2] pc_d;                       
+wire [ ((32-2)+2-1):2] pc_x;                       
+wire [ ((32-2)+2-1):2] pc_m;                       
+wire [ ((32-2)+2-1):2] pc_w;                       
+  
+                          
+
+
+  
+
+wire [ (32-1):0] instruction_f;     
+ 
+
+
+
+wire [ (32-1):0] instruction_d;     
+  
+                                     
+                       
+                     
+                      
+                           
+
+
+
+
+  
+                                   
+                                     
+                       
+                     
+                      
+                           
+
+
+wire [ (32-1):0] load_data_w;              
+wire stall_wb_load;                             
+
+
+  
+ 
+          
+          
+
+ 
+                      
+        
+                    
+                           
+  
+ 
+  
+  
+ 
+
+ 
+                                 
+
+
+
+
+
+wire raw_x_0;                                   
+wire raw_x_1;                                   
+wire raw_m_0;                                   
+wire raw_m_1;                                   
+wire raw_w_0;                                   
+wire raw_w_1;                                   
+
+
+wire cmp_zero;                                  
+wire cmp_negative;                              
+wire cmp_overflow;                              
+wire cmp_carry_n;                               
+reg condition_met_x;                            
+reg condition_met_m;
+      
+                             
+
+
+wire branch_taken_m;                            
+
+wire kill_f;                                    
+wire kill_d;                                    
+wire kill_x;                                    
+wire kill_m;                                    
+wire kill_w;                                    
+
+reg [ (32-2)+2-1:8] eba;                 
+  
+                  
+
+
+reg [ (3-1):0] eid_x;                      
+  
+                        
+                        
+
+
+
+  
+ 
+                                      
+
+                                      
+ 
+ 
+                                
+                                 
+                          
+ 
+ 
+ 
+                      
+ 
+ 
+ 
+
+
+wire exception_x;                               
+reg exception_m;
+reg exception_w;
+wire exception_q_w;
+ 
+
+
+  
+  
+                            
+
+ 
+                            
+
+
+
+  
+
+wire interrupt_exception;                       
+ 
+
+  
+                       
+                       
+
+
+  
+     
+   
+            
+                   
+
+
+  
+                   
+
+
+wire system_call_exception;                     
+
+  
+                         
+
+
+
+   
+    
+
+
+     
+  
+                          
+   
+            
+   
+                          
+   
+
+    	      
+    	      
+    	      
+    	      
+    	      
+    	      
+   
+   
+
+
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+lm32_instruction_unit_minimal #(
+    .eba_reset              (eba_reset),
+    .associativity          (icache_associativity),
+    .sets                   (icache_sets),
+    .bytes_per_line         (icache_bytes_per_line),
+    .base_address           (icache_base_address),
+    .limit                  (icache_limit)
+  ) instruction_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .stall_d                (stall_d),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .valid_f                (valid_f),
+    .valid_d                (valid_d),
+    .kill_f                 (kill_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .branch_predict_address_d (branch_predict_address_d),
+      
+             
+            
+
+
+    .exception_m            (exception_m),
+    .branch_taken_m         (branch_taken_m),
+    .branch_mispredict_taken_m (branch_mispredict_taken_m),
+    .branch_target_m        (branch_target_m),
+  
+                     
+
+
+  
+     
+      
+           
+
+        
+  
+
+    
+    .i_dat_i                (I_DAT_I),
+    .i_ack_i                (I_ACK_I),
+    .i_err_i                (I_ERR_I),
+    .i_rty_i                (I_RTY_I),
+ 
+
+  
+           
+          
+            
+               
+
+
+    
+    
+    .pc_f                   (pc_f),
+    .pc_d                   (pc_d),
+    .pc_x                   (pc_x),
+    .pc_m                   (pc_m),
+    .pc_w                   (pc_w),
+  
+       
+     
+      
+           
+
+
+  
+
+    
+    .i_dat_o                (I_DAT_O),
+    .i_adr_o                (I_ADR_O),
+    .i_cyc_o                (I_CYC_O),
+    .i_sel_o                (I_SEL_O),
+    .i_stb_o                (I_STB_O),
+    .i_we_o                 (I_WE_O),
+    .i_cti_o                (I_CTI_O),
+    .i_lock_o               (I_LOCK_O),
+    .i_bte_o                (I_BTE_O),
+ 
+ 
+
+  
+    
+    
+    
+
+
+		      	      
+  
+             
+       
+
+
+  
+                
+
+
+  
+
+    .instruction_f          (instruction_f),
+ 
+
+
+		      
+    .instruction_d          (instruction_d)
+
+
+		      
+    );
+
+
+lm32_decoder_minimal decoder (
+    
+    .instruction            (instruction_d),
+    
+    .d_result_sel_0         (d_result_sel_0_d),
+    .d_result_sel_1         (d_result_sel_1_d),
+    .x_result_sel_csr       (x_result_sel_csr_d),
+  
+      
+
+
+  
+    
+    .x_result_sel_shift     (x_result_sel_shift_d),
+ 
+
+  
+          
+
+    
+    .x_result_sel_logic     (x_result_sel_logic_d),
+  
+          
+
+
+    .x_result_sel_add       (x_result_sel_add_d),
+    .m_result_sel_compare   (m_result_sel_compare_d),
+  
+           
+
+    
+    .w_result_sel_load      (w_result_sel_load_d),
+  
+           
+
+
+    .x_bypass_enable        (x_bypass_enable_d),
+    .m_bypass_enable        (m_bypass_enable_d),
+    .read_enable_0          (read_enable_0_d),
+    .read_idx_0             (read_idx_0_d),
+    .read_enable_1          (read_enable_1_d),
+    .read_idx_1             (read_idx_1_d),
+    .write_enable           (write_enable_d),
+    .write_idx              (write_idx_d),
+    .immediate              (immediate_d),
+    .branch_offset          (branch_offset_d),
+    .load                   (load_d),
+    .store                  (store_d),
+    .size                   (size_d),
+    .sign_extend            (sign_extend_d),
+    .adder_op               (adder_op_d),
+    .logic_op               (logic_op_d),
+  
+                  
+
+
+  
+                 
+                
+
+
+  
+                   
+
+
+  
+                     
+                    
+
+
+    .branch                 (branch_d),
+    .bi_unconditional       (bi_unconditional),
+    .bi_conditional         (bi_conditional),
+    .branch_reg             (branch_reg_d),
+    .condition              (condition_d),
+  
+               
+
+
+    .scall                  (scall_d),
+    .eret                   (eret_d),
+  
+                       
+
+
+  
+                
+
+
+    .csr_write_enable       (csr_write_enable_d)
+    ); 
+
+
+lm32_load_store_unit_minimal #(
+    .associativity          (dcache_associativity),
+    .sets                   (dcache_sets),
+    .bytes_per_line         (dcache_bytes_per_line),
+    .base_address           (dcache_base_address),
+    .limit                  (dcache_limit)
+  ) load_store_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .kill_x                 (kill_x),
+    .kill_m                 (kill_m),
+    .exception_m            (exception_m),
+    .store_operand_x        (store_operand_x),
+    .load_store_address_x   (adder_result_x),
+    .load_store_address_m   (operand_m),
+    .load_store_address_w   (operand_w[1:0]),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_q_x               (load_q_x),
+    .store_q_x              (store_q_x),
+    .load_q_m               (load_q_m),
+    .store_q_m              (store_q_m),
+    .sign_extend_x          (sign_extend_x),
+    .size_x                 (size_x),
+  
+                     
+
+
+
+  
+    
+    
+    
+    
+    
+    
+    
+
+
+		     
+    
+    .d_dat_i                (D_DAT_I),
+    .d_ack_i                (D_ACK_I),
+    .d_err_i                (D_ERR_I),
+    .d_rty_i                (D_RTY_I),
+    
+    
+  
+      
+     
+       
+           
+
+    
+    .load_data_w            (load_data_w),
+    .stall_wb_load          (stall_wb_load),
+    
+    .d_dat_o                (D_DAT_O),
+    .d_adr_o                (D_ADR_O),
+    .d_cyc_o                (D_CYC_O),
+    .d_sel_o                (D_SEL_O),
+    .d_stb_o                (D_STB_O),
+    .d_we_o                 (D_WE_O),
+    .d_cti_o                (D_CTI_O),
+    .d_lock_o               (D_LOCK_O),
+    .d_bte_o                (D_BTE_O)
+    );      
+       
+
+lm32_adder adder (
+    
+    .adder_op_x             (adder_op_x),
+    .adder_op_x_n           (adder_op_x_n),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .adder_result_x         (adder_result_x),
+    .adder_carry_n_x        (adder_carry_n_x),
+    .adder_overflow_x       (adder_overflow_x)
+    );
+
+
+lm32_logic_op logic_op (
+    
+    .logic_op_x             (logic_op_x),
+    .operand_0_x            (operand_0_x),
+
+    .operand_1_x            (operand_1_x),
+    
+    .logic_result_x         (logic_result_x)
+    );
+              
+  
+
+  
+    
+                      
+                      
+                    
+                
+              
+                
+                
+    
+           
+    
+
+
+
+  
+
+  
+    
+                      
+                      
+                    
+                    
+                  
+                  
+    
+                         
+    
+
+
+
+  
+
+  
+    
+                      
+                      
+                    
+                     
+                   
+                   
+                  
+
+         
+                 
+
+ 
+               
+              
+              
+    
+                
+                
+    
+                   
+                   
+           
+
+            
+    
+
+
+              
+  
+
+
+lm32_interrupt_minimal interrupt_unit (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    
+    .interrupt              (interrupt),
+    
+    .stall_x                (stall_x),
+  
+         
+            
+
+
+    .exception              (exception_q_w), 
+ 
+
+    .eret_q_x               (eret_q_x),
+  
+                   
+
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    
+    .interrupt_exception    (interrupt_exception),
+    
+    .csr_read_data          (interrupt_csr_read_data_x)
+    );
+ 
+
+
+  
+      
+      
+        
+   
+
+
+
+
+  
+
+  
+    
+                      
+                      
+    
+                   
+                
+                 
+            
+    
+ 
+                        
+             
+           
+                    
+
+ 
+             
+       
+
+ 
+                
+    
+    
+    
+ 
+          
+          
+
+ 
+      
+        
+                   
+           
+          
+            
+               
+
+ 
+                 
+                 
+
+    
+                 
+            
+    
+
+
+
+  
+
+ 
+                
+                
+    
+    
+                       
+                      
+                       
+                     
+                    
+       
+         
+             
+                      
+  
+	       
+      
+        
+                   
+	      
+	       
+      
+        
+                   
+	      
+
+ 
+                   
+                   
+                    
+                
+                        
+ 
+      
+
+
+    
+ 
+                      
+
+                      
+                   
+                   
+    
+
+
+
+
+
+  
+
+   
+           
+            
+          
+            
+
+
+             
+              
+    
+
+   wire [31:0] regfile_data_0, regfile_data_1;
+   reg [31:0]  w_result_d;
+   reg 	       regfile_raw_0, regfile_raw_0_nxt;
+   reg 	       regfile_raw_1, regfile_raw_1_nxt;
+   
+   
+             
+          
+
+   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
+     begin
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[25:21]))
+	  regfile_raw_0_nxt = 1'b1;
+	else
+	  regfile_raw_0_nxt = 1'b0;
+	
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[20:16]))
+	  regfile_raw_1_nxt = 1'b1;
+	else
+	  regfile_raw_1_nxt = 1'b0;
+     end
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_0 or w_result_d or regfile_data_0)
+     if (regfile_raw_0)
+       reg_data_live_0 = w_result_d;
+     else
+       reg_data_live_0 = regfile_data_0;
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_1 or w_result_d or regfile_data_1)
+     if (regfile_raw_1)
+       reg_data_live_1 = w_result_d;
+     else
+       reg_data_live_1 = regfile_data_1;
+   
+   
+     
+
+   always @(posedge clk_i  )
+     if (rst_i ==  1'b1)
+       begin
+	  regfile_raw_0 <= 1'b0;
+	  regfile_raw_1 <= 1'b0;
+	  w_result_d <= 32'b0;
+       end
+     else
+       begin
+	  regfile_raw_0 <= regfile_raw_0_nxt;
+	  regfile_raw_1 <= regfile_raw_1_nxt;
+	  w_result_d <= w_result;
+       end
+   
+   
+      
+
+   
+   lm32_dp_ram
+     #(
+       
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_0
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[25:21]),
+      
+      .rdata_o	(regfile_data_0)
+      );
+
+   lm32_dp_ram
+     #(
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_1
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[20:16]),
+      
+      .rdata_o	(regfile_data_1)
+      );
+ 
+
+
+  
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+   
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+
+
+
+
+
+
+
+
+  
+
+
+assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
+assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
+ 
+
+  
+
+ 
+
+   
+   
+
+
+
+
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w ==  1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w ==  1'b1);
+
+
+always @(*)
+begin
+    if (   (   (x_bypass_enable_x ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_x_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_x_1 ==  1'b1))
+               )
+           )
+        || (   (m_bypass_enable_m ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_m_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_m_1 ==  1'b1))
+               )
+           )
+       )
+        interlock =  1'b1;
+    else
+        interlock =  1'b0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_0 ==  1'b1)        
+        bypass_data_0 = x_result;
+    else if (raw_m_0 ==  1'b1)
+        bypass_data_0 = m_result;
+    else if (raw_w_0 ==  1'b1)
+        bypass_data_0 = w_result;
+    else
+        bypass_data_0 = reg_data_0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_1 ==  1'b1)
+        bypass_data_1 = x_result;
+    else if (raw_m_1 ==  1'b1)
+        bypass_data_1 = m_result;
+    else if (raw_w_1 ==  1'b1)
+        bypass_data_1 = w_result;
+    else
+        bypass_data_1 = reg_data_1;
+end
+
+   
+          
+       
+       
+     
+
+   assign branch_predict_d = bi_unconditional | bi_conditional;
+   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
+   
+   
+   assign branch_target_d = pc_d + branch_offset_d;
+
+   
+   
+   
+   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
+
+
+always @(*)
+begin
+    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
+    case (d_result_sel_1_d)
+     2'b00:      d_result_1 = { 32{1'b0}};
+     2'b01:     d_result_1 = bypass_data_1;
+     2'b10: d_result_1 = immediate_d;
+    default:                        d_result_1 = { 32{1'bx}};
+    endcase
+end
+
+      
+
+   
+   
+
+
+
+  
+
+    
+    
+         
+
+
+
+  
+
+
+assign shifter_result_x = {operand_0_x[ 32-1] & sign_extend_x, operand_0_x[ 32-1:1]};
+ 
+
+
+
+assign cmp_zero = operand_0_x == operand_1_x;
+assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_overflow = adder_overflow_x;
+assign cmp_carry_n = adder_carry_n_x;
+always @(*)
+begin
+    case (condition_x)
+     3'b000:   condition_met_x =  1'b1;
+     3'b110:   condition_met_x =  1'b1;
+     3'b001:    condition_met_x = cmp_zero;
+     3'b111:   condition_met_x = !cmp_zero;
+     3'b010:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+     3'b101:   condition_met_x = cmp_carry_n && !cmp_zero;
+     3'b011:   condition_met_x = cmp_negative == cmp_overflow;
+     3'b100:  condition_met_x = cmp_carry_n;
+    default:              condition_met_x = 1'bx;
+    endcase 
+end
+
+
+always @(*)
+begin
+    x_result =   x_result_sel_add_x ? adder_result_x 
+               : x_result_sel_csr_x ? csr_read_data_x
+  
+                  
+
+
+  
+                  
+
+
+  
+
+               : x_result_sel_shift_x ? shifter_result_x
+ 
+
+  
+                  
+
+
+               : logic_result_x;
+end
+
+
+always @(*)
+begin
+    m_result =   m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
+  
+                  
+
+
+               : operand_m; 
+end
+
+
+always @(*)
+begin
+    w_result =    w_result_sel_load_w ? load_data_w
+  
+                   
+
+
+                : operand_w;
+end
+
+      
+
+          
+                                
+                                     
+                                 
+                                 
+                              
+
+
+
+
+assign branch_taken_m =      (stall_m ==  1'b0) 
+                          && (   (   (branch_m ==  1'b1) 
+                                  && (valid_m ==  1'b1)
+                                  && (   (   (condition_met_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b0)
+					 )
+				      || (   (condition_met_m ==  1'b0)
+					  && (branch_predict_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b1)
+					 )
+				     )
+                                 ) 
+                              || (exception_m ==  1'b1)
+                             );
+
+
+assign branch_mispredict_taken_m =    (condition_met_m ==  1'b0)
+                                   && (branch_predict_m ==  1'b1)
+	   			   && (branch_predict_taken_m ==  1'b1);
+   
+
+assign branch_flushX_m =    (stall_m ==  1'b0)
+                         && (   (   (branch_m ==  1'b1) 
+                                 && (valid_m ==  1'b1)
+			         && (   (condition_met_m ==  1'b1)
+				     || (   (condition_met_m ==  1'b0)
+					 && (branch_predict_m ==  1'b1)
+					 && (branch_predict_taken_m ==  1'b1)
+					)
+				    )
+			        )
+			     || (exception_m ==  1'b1)
+			    );
+
+
+assign kill_f =    (   (valid_d ==  1'b1)
+                    && (branch_predict_taken_d ==  1'b1)
+		   )
+                || (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+                    
+
+
+                  
+                   
+
+
+                ;
+assign kill_d =    (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+                        
+
+                
+                  
+                   
+
+
+                ;
+assign kill_x =    (branch_flushX_m ==  1'b1) 
+                  
+                   
+
+
+                ;
+assign kill_m =     1'b0
+                  
+                   
+
+
+                ;                
+assign kill_w =     1'b0
+                  
+                   
+
+                
+                ;
+
+
+
+  
+              
+				         
+				     
+				     
+				 
+ 
+                                 
+
+                              
+
+
+
+  
+     
+
+
+
+  
+        
+                                             
+                                         
+     
+
+
+
+  
+     
+
+
+
+assign system_call_exception = (   (scall_x ==  1'b1)
+  
+                                   
+
+
+			       );
+
+  
+      
+                            
+                         
+
+     
+ 
+                               
+
+ 
+                               
+                               
+
+ 
+                               
+
+ 
+                                  
+ 
+                                   
+                            
+ 
+ 				   
+				   
+
+                               
+
+                            
+
+         
+
+
+assign exception_x =           (system_call_exception ==  1'b1)
+  
+                               
+                               
+
+
+  
+                               
+
+
+  
+
+                            || (   (interrupt_exception ==  1'b1)
+  
+                                   
+
+                            
+  
+ 				   
+				   
+
+
+                               )
+ 
+
+                            ;
+ 
+
+
+  
+ 
+
+ 
+  
+      
+   
+      
+
+
+
+
+always @(*)
+begin
+  
+ 
+       
+          
+    
+     
+ 
+            
+          
+    
+
+            
+          
+    
+
+
+  
+            
+          
+    
+            
+          
+    
+
+
+  
+            
+          
+     
+
+
+  
+            
+          
+    
+
+
+  
+
+         if (   (interrupt_exception ==  1'b1)
+  
+                
+
+                            
+            )
+        eid_x =  3'h6;
+    else
+ 
+
+        eid_x =  3'h7;
+end
+
+
+
+assign stall_a = (stall_f ==  1'b1);
+                
+assign stall_f = (stall_d ==  1'b1);
+                
+assign stall_d =   (stall_x ==  1'b1) 
+                || (   (interlock ==  1'b1)
+                    && (kill_d ==  1'b0)
+                   ) 
+		|| (   (   (eret_d ==  1'b1)
+			|| (scall_d ==  1'b1)
+  
+			   
+
+
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+  
+		         
+			   
+		       
+		          
+			   
+			   
+			   
+			   
+		       
+                       
+		   
+
+                   
+                || (   (csr_write_enable_d ==  1'b1)
+                    && (load_q_x ==  1'b1)
+                   )                      
+  
+                 
+                 
+                       
+		           
+			 
+			
+		    
+
+	
+                ;
+                
+assign stall_x =    (stall_m ==  1'b1)
+  
+                       
+                        
+                     
+
+
+
+	    
+                 ;
+
+assign stall_m =    (stall_wb_load ==  1'b1)
+  
+                    
+
+
+                 || (   (D_CYC_O ==  1'b1)
+                     && (   (store_m ==  1'b1)
+		         
+          
+          
+
+		  
+	 
+	
+
+          
+           
+          
+       
+
+  
+
+		         || ((store_x ==  1'b1) && (interrupt_exception ==  1'b1))
+ 
+
+                         || (load_m ==  1'b1)
+                         || (load_x ==  1'b1)
+                        ) 
+                    ) 
+ 
+                 
+  
+                         
+
+                                    
+  
+                         
+                             
+
+
+  
+
+                 || (I_CYC_O ==  1'b1)            
+ 
+
+ 
+                               
+  
+                                  
+                        
+                    
+
+
+  
+                  
+   
+
+                 ;      
+
+
+
+
+  
+         
+
+
+  
+         
+         
+
+
+  
+         
+
+
+  
+         
+         
+
+
+assign q_x = (valid_x ==  1'b1) && (kill_x ==  1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x ==  1'b1) && (q_x ==  1'b1);
+assign eret_q_x = (eret_x ==  1'b1) && (q_x ==  1'b1);
+  
+         
+
+
+assign load_q_x = (load_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+                  
+
+
+                  ;
+assign store_q_x = (store_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+                  
+
+
+                  ;
+  
+         
+
+                              
+assign q_m = (valid_m ==  1'b1) && (kill_m ==  1'b0) && (exception_m ==  1'b0);
+assign load_q_m = (load_m ==  1'b1) && (q_m ==  1'b1);
+assign store_q_m = (store_m ==  1'b1) && (q_m ==  1'b1);
+  
+         
+                 
+
+
+assign exception_q_w = ((exception_w ==  1'b1) && (valid_w ==  1'b1));        
+ 
+
+
+assign write_enable_q_x = (write_enable_x ==  1'b1) && (valid_x ==  1'b1) && (branch_flushX_m ==  1'b0);
+assign write_enable_q_m = (write_enable_m ==  1'b1) && (valid_m ==  1'b1);
+assign write_enable_q_w = (write_enable_w ==  1'b1) && (valid_w ==  1'b1);
+
+assign reg_write_enable_q_w = (write_enable_w ==  1'b1) && (kill_w ==  1'b0) && (valid_w ==  1'b1);
+
+
+assign cfg = {
+               6'h02,
+              watchpoints[3:0],
+              breakpoints[3:0],
+              interrupts[5:0],
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+   
+              
+
+
+               1'b0
+ 
+
+              };
+
+assign cfg2 = {
+		     30'b0,
+  
+		     
+
+
+		      1'b0,
+ 
+
+  
+		     
+
+
+		      1'b0
+ 
+
+		     };
+   
+
+  
+         
+                    
+                    
+                    
+                    
+
+ 
+             
+                     
+		    
+
+		 
+
+ 
+  
+         
+                      
+
+ 
+               
+                       
+		      
+
+		   
+
+ 
+
+
+assign csr_d = read_idx_0_d[ (4 -1):0];
+
+
+always @(*)
+begin
+    case (csr_x)
+  
+
+     4 'h0,
+     4 'h1,
+     4 'h2:   csr_read_data_x = interrupt_csr_read_data_x;  
+ 
+
+  
+         
+
+
+     4 'h6:  csr_read_data_x = cfg;
+     4 'h7:  csr_read_data_x = {eba, 8'h00};
+  
+        
+
+
+  
+          
+        
+
+
+     4 'ha: csr_read_data_x = cfg2;
+     4 'hb:  csr_read_data_x = sdb_address;
+  
+        
+
+
+      
+      
+    default:        csr_read_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        eba <= eba_reset[ (32-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  4 'h7) && (stall_x ==  1'b0))
+            eba <= operand_1_x[ (32-2)+2-1:8];
+  
+  
+              
+           
+ 
+  
+              
+           
+ 	 
+
+
+    end
+end
+
+  
+
+   
+
+       
+          
+    
+    
+                   
+              
+  
+   
+              
+           
+  
+   
+              
+           
+         
+ 
+    
+
+
+
+
+
+  
+   
+
+       
+          
+    
+            
+
+
+
+
+  
+
+   
+
+       
+          
+    
+    
+        
+                
+             
+	     
+	
+        
+               
+              
+    
+
+
+
+ 
+
+
+  
+ 
+ 
+
+           
+           
+       
+          
+            
+                 
+             
+          
+     
+            
+ 
+
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+
+  
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+ 
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        valid_f <=  1'b0;
+        valid_d <=  1'b0;
+        valid_x <=  1'b0;
+        valid_m <=  1'b0;
+        valid_w <=  1'b0;
+    end
+    else
+    begin    
+        if ((kill_f ==  1'b1) || (stall_a ==  1'b0))
+  
+                  
+
+
+            valid_f <=  1'b1;
+ 
+            
+        else if (stall_f ==  1'b0)
+            valid_f <=  1'b0;            
+
+        if (kill_d ==  1'b1)
+            valid_d <=  1'b0;
+        else if (stall_f ==  1'b0)
+            valid_d <= valid_f & !kill_f;
+        else if (stall_d ==  1'b0)
+            valid_d <=  1'b0;
+       
+        if (stall_d ==  1'b0)
+            valid_x <= valid_d & !kill_d;
+        else if (kill_x ==  1'b1)
+            valid_x <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_x <=  1'b0;
+
+        if (kill_m ==  1'b1)
+            valid_m <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_m <= valid_x & !kill_x;
+        else if (stall_m ==  1'b0)
+            valid_m <=  1'b0;
+
+        if (stall_m ==  1'b0)
+            valid_w <= valid_m & !kill_m;
+        else 
+            valid_w <=  1'b0;        
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+  
+                 
+
+        
+        operand_0_x <= { 32{1'b0}};
+        operand_1_x <= { 32{1'b0}};
+        store_operand_x <= { 32{1'b0}};
+        branch_target_x <= { (32-2){1'b0}};        
+        x_result_sel_csr_x <=  1'b0;
+  
+          
+
+
+  
+    
+        x_result_sel_shift_x <=  1'b0;
+ 
+
+  
+          
+
+    
+  
+          
+
+
+        x_result_sel_add_x <=  1'b0;
+        m_result_sel_compare_x <=  1'b0;
+  
+          
+
+    
+        w_result_sel_load_x <=  1'b0;
+  
+          
+
+
+        x_bypass_enable_x <=  1'b0;
+        m_bypass_enable_x <=  1'b0;
+        write_enable_x <=  1'b0;
+        write_idx_x <= { 5{1'b0}};
+        csr_x <= { 4 {1'b0}};
+        load_x <=  1'b0;
+        store_x <=  1'b0;
+        size_x <= { 2{1'b0}};
+        sign_extend_x <=  1'b0;
+        adder_op_x <=  1'b0;
+        adder_op_x_n <=  1'b0;
+        logic_op_x <= 4'h0;
+  
+          
+
+
+  
+          
+
+
+
+        branch_x <=  1'b0;
+        branch_predict_x <=  1'b0;
+        branch_predict_taken_x <=  1'b0;
+        condition_x <=  3'b000;
+  
+          
+
+
+        scall_x <=  1'b0;
+        eret_x <=  1'b0;
+  
+          
+
+
+  
+          
+          
+
+
+        csr_write_enable_x <=  1'b0;
+        operand_m <= { 32{1'b0}};
+        branch_target_m <= { (32-2){1'b0}};
+        m_result_sel_compare_m <=  1'b0;
+  
+          
+
+    
+        w_result_sel_load_m <=  1'b0;
+  
+          
+
+
+        m_bypass_enable_m <=  1'b0;
+        branch_m <=  1'b0;
+        branch_predict_m <=  1'b0;
+	branch_predict_taken_m <=  1'b0;
+        exception_m <=  1'b0;
+        load_m <=  1'b0;
+        store_m <=  1'b0;
+        write_enable_m <=  1'b0;            
+        write_idx_m <= { 5{1'b0}};
+        condition_met_m <=  1'b0;
+  
+          
+
+
+  
+          
+                  
+
+
+        operand_w <= { 32{1'b0}};        
+        w_result_sel_load_w <=  1'b0;
+  
+          
+
+
+        write_idx_w <= { 5{1'b0}};        
+        write_enable_w <=  1'b0;
+  
+          
+                  
+
+
+        exception_w <=  1'b0;
+ 
+
+  
+          
+
+
+    end
+    else
+    begin
+        
+       
+        if (stall_x ==  1'b0)
+        begin
+  
+                     
+
+        
+            operand_0_x <= d_result_0;
+            operand_1_x <= d_result_1;
+            store_operand_x <= bypass_data_1;
+            branch_target_x <= branch_reg_d ==  1'b1 ? bypass_data_0[ ((32-2)+2-1):2] : branch_target_d;            
+            x_result_sel_csr_x <= x_result_sel_csr_d;
+  
+              
+
+
+  
+    
+            x_result_sel_shift_x <= x_result_sel_shift_d;
+ 
+
+  
+              
+
+    
+  
+              
+
+
+            x_result_sel_add_x <= x_result_sel_add_d;
+            m_result_sel_compare_x <= m_result_sel_compare_d;
+  
+              
+
+    
+            w_result_sel_load_x <= w_result_sel_load_d;
+  
+              
+
+
+            x_bypass_enable_x <= x_bypass_enable_d;
+            m_bypass_enable_x <= m_bypass_enable_d;
+            load_x <= load_d;
+            store_x <= store_d;
+            branch_x <= branch_d;
+	    branch_predict_x <= branch_predict_d;
+	    branch_predict_taken_x <= branch_predict_taken_d;
+	    write_idx_x <= write_idx_d;
+            csr_x <= csr_d;
+            size_x <= size_d;
+            sign_extend_x <= sign_extend_d;
+            adder_op_x <= adder_op_d;
+            adder_op_x_n <= ~adder_op_d;
+            logic_op_x <= logic_op_d;
+  
+              
+
+
+  
+              
+
+
+            condition_x <= condition_d;
+            csr_write_enable_x <= csr_write_enable_d;
+  
+              
+
+
+            scall_x <= scall_d;
+  
+              
+
+
+            eret_x <= eret_d;
+  
+               
+
+
+            write_enable_x <= write_enable_d;
+        end
+        
+        
+
+        if (stall_m ==  1'b0)
+        begin
+            operand_m <= x_result;
+            m_result_sel_compare_m <= m_result_sel_compare_x;
+  
+              
+
+    
+            if (exception_x ==  1'b1)
+            begin
+                w_result_sel_load_m <=  1'b0;
+  
+                  
+
+
+            end
+            else
+            begin
+                w_result_sel_load_m <= w_result_sel_load_x;
+  
+                  
+
+
+            end
+            m_bypass_enable_m <= m_bypass_enable_x;
+            load_m <= load_x;
+            store_m <= store_x;
+      
+                
+
+
+            branch_m <= branch_x;
+	    branch_predict_m <= branch_predict_x;
+	    branch_predict_taken_m <= branch_predict_taken_x;
+ 
+
+  
+	   
+	   
+	   
+	   
+	   
+                
+                  
+                
+                  
+             
+                  
+
+
+            if (exception_x ==  1'b1)
+                write_idx_m <=  5'd30;
+            else 
+                write_idx_m <= write_idx_x;
+ 
+
+            condition_met_m <= condition_met_x;
+  
+	      
+	        
+		     
+		        
+	           
+	     
+	           
+	   
+	       
+
+
+            branch_target_m <= exception_x ==  1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
+ 
+
+  
+              
+              
+
+
+  
+              
+
+
+  
+ 
+               
+
+
+
+            write_enable_m <= exception_x ==  1'b1 ?  1'b1 : write_enable_x;            
+  
+              
+                      
+
+
+        end
+        
+        
+        if (stall_m ==  1'b0)
+        begin
+            if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+                exception_m <=  1'b1;
+            else 
+                exception_m <=  1'b0;
+  
+	           
+ 
+					    
+
+					 
+
+
+	end
+                
+        
+  
+                      
+
+
+        operand_w <= exception_m ==  1'b1 ? {pc_m, 2'b00} : m_result;
+ 
+
+        w_result_sel_load_w <= w_result_sel_load_m;
+  
+          
+
+
+        write_idx_w <= write_idx_m;
+  
+          
+          
+ 
+           
+
+
+
+        write_enable_w <= write_enable_m;
+  
+          
+          
+
+
+        exception_w <= exception_m;
+ 
+
+  
+              
+                   
+                   
+               
+	   
+            
+
+
+    end
+end
+
+  
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        use_buf <=  1'b0;
+        reg_data_buf_0 <= { 32{1'b0}};
+        reg_data_buf_1 <= { 32{1'b0}};
+    end
+    else
+    begin
+        if (stall_d ==  1'b0)
+            use_buf <=  1'b0;
+        else if (use_buf ==  1'b0)
+        begin        
+            reg_data_buf_0 <= reg_data_live_0;
+            reg_data_buf_1 <= reg_data_live_1;
+            use_buf <=  1'b1;
+        end        
+        if (reg_write_enable_q_w ==  1'b1)
+        begin
+            if (write_idx_w == read_idx_0_d)
+                reg_data_buf_0 <= w_result;
+            if (write_idx_w == read_idx_1_d)
+                reg_data_buf_1 <= w_result;
+        end
+    end
+end
+ 
+
+
+  
+
+ 
+
+   
+
+        
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+     
+           
+            
+        
+
+
+
+
+  
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+ 
+          
+
+          
+    
+    
+    
+          
+        
+ 
+               
+
+           
+
+                
+              
+              
+              
+              
+        
+        
+              
+        
+             
+        
+            
+                 
+            
+                
+                  
+                  
+            
+            
+              
+            
+              
+ 
+              
+
+        
+        
+        
+              
+ 
+              
+
+        
+    
+
+
+
+      
+
+
+
+
+
+        
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_load_store_unit_minimal 
+(
+    
+    clk_i,
+    rst_i,
+ 
+    stall_a,
+    stall_x,
+    stall_m,
+    kill_x,
+    kill_m,
+    exception_m,
+    store_operand_x,
+    load_store_address_x,
+    load_store_address_m,
+    load_store_address_w,
+    load_x,
+    store_x,
+    load_q_x,
+    store_q_x,
+    load_q_m,
+    store_q_m,
+    sign_extend_x,
+    size_x,
+  
+    
+
+
+    
+    d_dat_i,
+    d_ack_i,
+    d_err_i,
+    d_rty_i,
+    
+    
+  
+    
+    
+    
+    
+
+    
+  
+    
+    
+    
+    
+    
+    
+    
+
+			     
+    load_data_w,
+    stall_wb_load,
+    
+    d_dat_o,
+    d_adr_o,
+    d_cyc_o,
+    d_sel_o,
+    d_stb_o,
+    d_we_o,
+    d_cti_o,
+    d_lock_o,
+    d_bte_o
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+
+   input clk_i;                                            
+   
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+input kill_x;                                           
+input kill_m;                                           
+input exception_m;                                      
+
+input [ (32-1):0] store_operand_x;                 
+input [ (32-1):0] load_store_address_x;            
+input [ (32-1):0] load_store_address_m;            
+input [1:0] load_store_address_w;                       
+input load_x;                                           
+input store_x;                                          
+input load_q_x;                                         
+input store_q_x;                                        
+input load_q_m;                                         
+input store_q_m;                                        
+input sign_extend_x;                                    
+input [ 1:0] size_x;                          
+
+  
+                                            
+
+
+
+     
+     
+     
+      
+      
+            
+    	 
+   
+
+
+
+   reg 		 [31:0] iram_dat_d0;
+   reg 		 iram_en_d0;
+   wire 	 iram_en;
+   wire [31:0] 	 iram_data;
+   
+   
+   
+input [ (32-1):0] d_dat_i;                         
+input d_ack_i;                                          
+input d_err_i;                                          
+input d_rty_i;                                          
+
+
+
+
+
+  
+                            
+   
+                           
+   
+                             
+   
+ 
+   
+
+
+
+   
+output [ (32-1):0] load_data_w;                    
+reg    [ (32-1):0] load_data_w;
+output stall_wb_load;                                   
+reg    stall_wb_load;
+
+output [ (32-1):0] d_dat_o;                        
+reg    [ (32-1):0] d_dat_o;
+output [ (32-1):0] d_adr_o;                        
+reg    [ (32-1):0] d_adr_o;
+output d_cyc_o;                                         
+reg    d_cyc_o;
+output [ (4-1):0] d_sel_o;                 
+reg    [ (4-1):0] d_sel_o;
+output d_stb_o;                                         
+reg    d_stb_o; 
+output d_we_o;                                          
+reg    d_we_o;
+output [ (3-1):0] d_cti_o;                       
+reg    [ (3-1):0] d_cti_o;
+output d_lock_o;                                        
+reg    d_lock_o;
+output [ (2-1):0] d_bte_o;                       
+wire   [ (2-1):0] d_bte_o;
+
+
+
+
+
+
+reg [ 1:0] size_m;
+reg [ 1:0] size_w;
+reg sign_extend_m;
+reg sign_extend_w;
+reg [ (32-1):0] store_data_x;       
+reg [ (32-1):0] store_data_m;       
+reg [ (4-1):0] byte_enable_x;
+reg [ (4-1):0] byte_enable_m;
+wire [ (32-1):0] data_m;
+reg [ (32-1):0] data_w;
+
+   
+
+  
+                                    
+ 
+                      
+              
+                                 
+                  
+                   
+                                          
+                      
+
+
+  
+                                      
+ 
+                                      
+                    
+                      
+                        
+                  
+
+
+wire wb_select_x;                                       
+  
+                                      
+
+  
+    
+    
+   
+
+
+
+reg wb_select_m;
+reg [ (32-1):0] wb_data_m;                         
+reg wb_load_complete;                                   
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+ 
+              
+                       
+             
+               
+                      
+       
+    
+                      
+                            
+                    
+                    
+                    
+                  
+                  
+                     
+                    
+                 
+            
+               
+                
+                     
+    
+              
+            
+             
+             
+                  
+                  
+    
+
+
+
+
+
+
+
+
+  
+            
+                             
+
+
+
+  
+            
+                             
+
+      
+        
+
+    
+       
+
+   
+
+    
+     
+       
+     
+         
+     
+
+          
+    
+   
+   
+
+
+   
+  
+            
+                               
+ 
+                               
+
+ 
+                               
+
+                     
+
+
+	  
+   assign wb_select_x =     1'b1
+  
+                          
+
+
+  
+                         
+
+
+  
+                         
+
+
+                     ;
+
+
+always @(*)
+begin
+    case (size_x)
+     2'b00:  store_data_x = {4{store_operand_x[7:0]}};
+     2'b11: store_data_x = {2{store_operand_x[15:0]}};
+     2'b10:  store_data_x = store_operand_x;    
+    default:          store_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+always @(*)
+begin
+    casez ({size_x, load_store_address_x[1:0]})
+    { 2'b00, 2'b11}:  byte_enable_x = 4'b0001;
+    { 2'b00, 2'b10}:  byte_enable_x = 4'b0010;
+    { 2'b00, 2'b01}:  byte_enable_x = 4'b0100;
+    { 2'b00, 2'b00}:  byte_enable_x = 4'b1000;
+    { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+    { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+    { 2'b10, 2'b??}:  byte_enable_x = 4'b1111;
+    default:                   byte_enable_x = 4'bxxxx;
+    endcase
+end
+
+  
+      
+            
+
+           
+	                            
+   
+   
+               
+        
+
+
+   
+  
+  
+   
+   
+         
+                    
+                       
+                      
+                        
+                     
+                        
+  
+   
+         
+                    
+                       
+                      
+                      
+  
+ 
+   
+   
+         
+                    
+                       
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+
+   
+   
+   
+         
+                     
+                      
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+    
+   
+         
+                     
+                    
+
+  
+
+   
+   assign data_m = wb_data_m;
+   
+
+  
+
+ 
+
+
+
+always @(*)
+begin
+    casez ({size_w, load_store_address_w[1:0]})
+    { 2'b00, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+    { 2'b00, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+    { 2'b00, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+    { 2'b00, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+    { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+    { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+    { 2'b10, 2'b??}:  load_data_w = data_w;
+    default:                   load_data_w = { 32{1'bx}};
+    endcase
+end
+
+
+assign d_bte_o =  2'b00;
+
+                  
+
+ 
+     
+    
+    
+   
+   
+   
+    
+    
+    
+    
+   
+   
+     
+     
+    
+    
+    
+   
+         
+     
+     
+    
+    
+
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        d_cyc_o <=  1'b0;
+        d_stb_o <=  1'b0;
+        d_dat_o <= { 32{1'b0}};
+        d_adr_o <= { 32{1'b0}};
+        d_sel_o <= { 4{ 1'b0}};
+        d_we_o <=  1'b0;
+        d_cti_o <=  3'b111;
+        d_lock_o <=  1'b0;
+        wb_data_m <= { 32{1'b0}};
+        wb_load_complete <=  1'b0;
+        stall_wb_load <=  1'b0;
+                  
+          
+
+                
+    end
+    else 
+    begin
+   
+        
+          
+
+                
+        
+        if (d_cyc_o ==  1'b1)
+        begin
+            
+            if ((d_ack_i ==  1'b1) || (d_err_i ==  1'b1))
+            begin
+                  
+                     
+                
+                    
+                        
+                
+                
+
+                
+                begin
+                    
+                    d_cyc_o <=  1'b0;
+                    d_stb_o <=  1'b0;
+                    d_lock_o <=  1'b0;
+                end
+      
+                  
+                
+                  
+
+
+                
+                wb_data_m <= d_dat_i;
+                
+                wb_load_complete <= !d_we_o;
+            end
+            
+        end
+        else 
+        begin
+                  
+               
+            
+                
+                  
+                  
+                  
+                                  
+                  
+                  
+                
+            
+             
+
+            
+                 if (   (store_q_m ==  1'b1)
+                     && (stall_m ==  1'b0)
+  
+                        
+
+
+  
+		        
+
+			
+                    )
+            begin
+                
+                d_dat_o <= store_data_m;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b1;
+                d_cti_o <=  3'b111;
+            end        
+            else if (   (load_q_m ==  1'b1) 
+                     && (wb_select_m ==  1'b1) 
+                     && (wb_load_complete ==  1'b0)
+                     
+                    )
+            begin
+                
+                stall_wb_load <=  1'b0;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b0;
+                d_cti_o <=  3'b111;
+            end
+        end
+        
+        if (stall_m ==  1'b0)
+            wb_load_complete <=  1'b0;
+        
+        if ((load_q_x ==  1'b1) && (wb_select_x ==  1'b1) && (stall_x ==  1'b0))
+            stall_wb_load <=  1'b1;
+        
+        if ((kill_m ==  1'b1) || (exception_m ==  1'b1))
+            stall_wb_load <=  1'b0;
+    end
+end
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        sign_extend_m <=  1'b0;
+        size_m <= 2'b00;
+        byte_enable_m <=  1'b0;
+        store_data_m <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+  
+          
+			    
+
+
+        wb_select_m <=  1'b0;        
+    end
+    else
+    begin
+        if (stall_m ==  1'b0)
+        begin
+            sign_extend_m <= sign_extend_x;
+            size_m <= size_x;
+            byte_enable_m <= byte_enable_x;    
+            store_data_m <= store_data_x;
+  
+              
+
+
+  
+              
+
+
+  
+              
+			    
+
+
+            wb_select_m <= wb_select_x;
+        end
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        size_w <= 2'b00;
+        data_w <= { 32{1'b0}};
+        sign_extend_w <=  1'b0;
+    end
+    else
+    begin
+        size_w <= size_m;
+
+  
+         
+
+
+        data_w <= data_m;
+
+        sign_extend_w <= sign_extend_m;
+    end
+end
+
+
+
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_decoder_minimal (
+    
+    instruction,
+    
+    d_result_sel_0,
+    d_result_sel_1,        
+    x_result_sel_csr,
+  
+    
+
+    
+  
+    
+    x_result_sel_shift,
+ 
+
+  
+    
+
+    
+    x_result_sel_logic,
+  
+    
+
+
+    x_result_sel_add,
+    m_result_sel_compare,
+  
+      
+
+    
+    w_result_sel_load,
+  
+    
+
+
+    x_bypass_enable,
+    m_bypass_enable,
+    read_enable_0,
+    read_idx_0,
+    read_enable_1,
+    read_idx_1,
+    write_enable,
+    write_idx,
+    immediate,
+    branch_offset,
+    load,
+    store,
+    size,
+    sign_extend,
+    adder_op,
+    logic_op,
+  
+    
+
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+    
+    
+
+
+    branch,
+    branch_reg,
+    condition,
+    bi_conditional,
+    bi_unconditional,
+  
+    
+
+
+    scall,
+    eret,
+  
+    
+
+
+  
+    
+
+
+    csr_write_enable
+    );
+
+
+
+
+
+input [ (32-1):0] instruction;       
+
+
+
+
+
+output [ 0:0] d_result_sel_0;
+reg    [ 0:0] d_result_sel_0;
+output [ 1:0] d_result_sel_1;
+reg    [ 1:0] d_result_sel_1;
+output x_result_sel_csr;
+reg    x_result_sel_csr;
+  
+ 
+    
+
+
+  
+    
+output x_result_sel_shift;
+reg    x_result_sel_shift;
+ 
+
+  
+ 
+    
+
+
+output x_result_sel_logic;
+reg    x_result_sel_logic;
+  
+ 
+    
+
+
+output x_result_sel_add;
+reg    x_result_sel_add;
+output m_result_sel_compare;
+reg    m_result_sel_compare;
+  
+ 
+    
+
+
+output w_result_sel_load;
+reg    w_result_sel_load;
+  
+ 
+    
+
+
+output x_bypass_enable;
+wire   x_bypass_enable;
+output m_bypass_enable;
+wire   m_bypass_enable;
+output read_enable_0;
+wire   read_enable_0;
+output [ (5-1):0] read_idx_0;
+wire   [ (5-1):0] read_idx_0;
+output read_enable_1;
+wire   read_enable_1;
+output [ (5-1):0] read_idx_1;
+wire   [ (5-1):0] read_idx_1;
+output write_enable;
+wire   write_enable;
+output [ (5-1):0] write_idx;
+wire   [ (5-1):0] write_idx;
+output [ (32-1):0] immediate;
+wire   [ (32-1):0] immediate;
+output [ ((32-2)+2-1):2] branch_offset;
+wire   [ ((32-2)+2-1):2] branch_offset;
+output load;
+wire   load;
+output store;
+wire   store;
+output [ 1:0] size;
+wire   [ 1:0] size;
+output sign_extend;
+wire   sign_extend;
+output adder_op;
+wire   adder_op;
+output [ 3:0] logic_op;
+wire   [ 3:0] logic_op;
+  
+ 
+   
+
+
+  
+ 
+   
+ 
+   
+
+
+  
+ 
+   
+
+
+  
+ 
+   
+ 
+   
+
+
+output branch;
+wire   branch;
+output branch_reg;
+wire   branch_reg;
+output [ (3-1):0] condition;
+wire   [ (3-1):0] condition;
+output bi_conditional;
+wire bi_conditional;
+output bi_unconditional;
+wire bi_unconditional;
+  
+ 
+   
+
+
+output scall;
+wire   scall;
+output eret;
+wire   eret;
+  
+ 
+   
+
+
+  
+  
+    
+
+
+output csr_write_enable;
+wire   csr_write_enable;
+
+
+
+
+
+wire [ (32-1):0] extended_immediate;       
+wire [ (32-1):0] high_immediate;           
+wire [ (32-1):0] call_immediate;           
+wire [ (32-1):0] branch_immediate;         
+wire sign_extend_immediate;                     
+wire select_high_immediate;                     
+wire select_call_immediate;                     
+
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+  
+ 
+
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+  
+ 
+
+
+  
+ 
+
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+  
+ 
+ 
+
+
+wire op_sh;
+  
+ 
+
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+  
+ 
+
+
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+  
+ 
+
+
+  
+
+wire shift;
+ 
+
+  
+ 
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+assign op_add    = instruction[ 30:26] ==  5'b01101;
+assign op_and    = instruction[ 30:26] ==  5'b01000;
+assign op_andhi  = instruction[ 31:26] ==  6'b011000;
+assign op_b      = instruction[ 31:26] ==  6'b110000;
+assign op_bi     = instruction[ 31:26] ==  6'b111000;
+assign op_be     = instruction[ 31:26] ==  6'b010001;
+assign op_bg     = instruction[ 31:26] ==  6'b010010;
+assign op_bge    = instruction[ 31:26] ==  6'b010011;
+assign op_bgeu   = instruction[ 31:26] ==  6'b010100;
+assign op_bgu    = instruction[ 31:26] ==  6'b010101;
+assign op_bne    = instruction[ 31:26] ==  6'b010111;
+assign op_call   = instruction[ 31:26] ==  6'b110110;
+assign op_calli  = instruction[ 31:26] ==  6'b111110;
+assign op_cmpe   = instruction[ 30:26] ==  5'b11001;
+assign op_cmpg   = instruction[ 30:26] ==  5'b11010;
+assign op_cmpge  = instruction[ 30:26] ==  5'b11011;
+assign op_cmpgeu = instruction[ 30:26] ==  5'b11100;
+assign op_cmpgu  = instruction[ 30:26] ==  5'b11101;
+assign op_cmpne  = instruction[ 30:26] ==  5'b11111;
+  
+       
+
+
+assign op_lb     = instruction[ 31:26] ==  6'b000100;
+assign op_lbu    = instruction[ 31:26] ==  6'b010000;
+assign op_lh     = instruction[ 31:26] ==  6'b000111;
+assign op_lhu    = instruction[ 31:26] ==  6'b001011;
+assign op_lw     = instruction[ 31:26] ==  6'b001010;
+  
+       
+
+
+  
+        
+
+
+assign op_nor    = instruction[ 30:26] ==  5'b00001;
+assign op_or     = instruction[ 30:26] ==  5'b01110;
+assign op_orhi   = instruction[ 31:26] ==  6'b011110;
+assign op_raise  = instruction[ 31:26] ==  6'b101011;
+assign op_rcsr   = instruction[ 31:26] ==  6'b100100;
+assign op_sb     = instruction[ 31:26] ==  6'b001100;
+  
+      
+      
+
+
+assign op_sh     = instruction[ 31:26] ==  6'b000011;
+  
+               
+
+
+assign op_sr     = instruction[ 30:26] ==  5'b00101;
+assign op_sru    = instruction[ 30:26] ==  5'b00000;
+assign op_sub    = instruction[ 31:26] ==  6'b110010;
+assign op_sw     = instruction[ 31:26] ==  6'b010110;
+  
+       
+
+
+assign op_wcsr   = instruction[ 31:26] ==  6'b110100;
+assign op_xnor   = instruction[ 30:26] ==  5'b01001;
+assign op_xor    = instruction[ 30:26] ==  5'b00110;
+
+
+assign arith = op_add | op_sub;
+assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
+assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
+assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
+assign bi_unconditional = op_bi;
+assign bra = op_b | bi_unconditional | bi_conditional;
+assign call = op_call | op_calli;
+  
+       
+
+
+  
+
+assign shift = op_sr | op_sru;
+ 
+
+  
+   
+     
+
+
+  
+     
+
+
+  
+   
+
+
+  
+    
+   
+
+
+assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
+assign store = op_sb | op_sh | op_sw;
+
+
+always @(*)
+begin
+    
+    if (call) 
+        d_result_sel_0 =  1'b1;
+    else 
+        d_result_sel_0 =  1'b0;
+    if (call) 
+        d_result_sel_1 =  2'b00;         
+    else if ((instruction[31] == 1'b0) && !bra) 
+        d_result_sel_1 =  2'b10;
+    else
+        d_result_sel_1 =  2'b01; 
+    
+    x_result_sel_csr =  1'b0;
+  
+      
+
+
+  
+
+    x_result_sel_shift =  1'b0;
+ 
+
+  
+      
+
+
+    x_result_sel_logic =  1'b0;
+          
+      
+
+
+    x_result_sel_add =  1'b0;
+    if (op_rcsr)
+        x_result_sel_csr =  1'b1;
+      
+ 
+         
+          
+
+ 
+        
+                  
+
+ 
+      
+                      
+
+
+
+  
+
+    else if (shift)
+        x_result_sel_shift =  1'b1;        
+ 
+
+  
+      
+          
+
+        
+    else if (logical) 
+        x_result_sel_logic =  1'b1;
+          
+      
+          
+
+
+    else 
+        x_result_sel_add =  1'b1;        
+    
+    
+
+    m_result_sel_compare = cmp;
+  
+      
+
+
+
+    
+    w_result_sel_load = load;
+  
+       
+
+
+end
+
+
+assign x_bypass_enable =  arith 
+                        | logical
+  
+                         
+                         
+
+                        
+  
+                         
+
+
+  
+                         
+                         
+
+
+  
+
+                        | shift
+ 
+                  
+  
+                          
+
+                        
+  
+                         
+
+
+                        | op_rcsr
+                        ;
+
+assign m_bypass_enable = x_bypass_enable 
+  
+                         
+
+
+                        | cmp
+                        ;
+
+assign read_enable_0 = ~(op_bi | op_calli);
+assign read_idx_0 = instruction[25:21];
+
+assign read_enable_1 = ~(op_bi | op_calli | load);
+assign read_idx_1 = instruction[20:16];
+
+assign write_enable = ~(bra | op_raise | store | op_wcsr);
+assign write_idx = call
+                    ? 5'd29
+                    : instruction[31] == 1'b0 
+                        ? instruction[20:16] 
+                        : instruction[15:11];
+                        
+
+assign size = instruction[27:26];
+
+assign sign_extend = instruction[28];                      
+
+assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
+
+assign logic_op = instruction[29:26];
+  
+
+   
+
+
+
+assign branch = bra | call;
+assign branch_reg = op_call | op_b;
+assign condition = instruction[28:26];      
+  
+     
+
+
+assign scall = op_raise & instruction[2];
+assign eret = op_b & (instruction[25:21] == 5'd30);
+  
+       
+
+
+  
+
+   
+
+
+
+assign csr_write_enable = op_wcsr;
+
+
+
+assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
+assign select_high_immediate = op_andhi | op_orhi;
+assign select_call_immediate = instruction[31];
+
+assign high_immediate = {instruction[15:0], 16'h0000};
+assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
+assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
+assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
+
+assign immediate = select_high_immediate ==  1'b1 
+                        ? high_immediate 
+                        : extended_immediate;
+   
+assign branch_offset = select_call_immediate ==  1'b1   
+                        ? (call_immediate[ (32-2)-1:0])
+                        : (branch_immediate[ (32-2)-1:0]);
+    
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+           
+              
+              
+              
+
+           
+             
+           
+             
+
+                
+                  
+              
+            
+
+                 
+          
+               
+               
+              
+
+
+
+
+
+   
+    
+    
+        
+    
+    
+    
+    
+    
+    
+    
+    
+ 
+    
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+
+
+
+
+
+                               
+                                      
+                             
+                                
+                                       
+
+   
+   
+   
+   
+   
+   
+   
+   
+   
+
+
+
+
+
+                                         
+                                         
+
+                                       
+                                       
+
+                                       
+                        
+   
+                       
+                       
+                                 
+
+                                  
+            
+
+                                        
+ 
+                                      
+
+   
+
+
+
+
+                                
+   
+                              
+    
+                               
+   
+                 
+                    
+                                    
+    
+                  
+    
+
+
+
+
+
+ 
+  
+  
+  
+  
+  
+ 
+
+  
+  
+  
+  
+  
+
+  
+ 
+ 
+ 
+
+  
+  
+ 
+  
+
+ 
+
+
+
+
+
+ 
+
+
+
+
+
+   
+                 
+	  
+	   
+	    
+	     
+	       
+	                        
+	                     
+
+ 
+	    
+	     
+	      
+	                         
+	                        
+	                            
+	                     
+	                      
+	                    
+	                     
+	                     
+	                           
+	      
+	                        
+	      
+	   
+	    
+	     
+	       
+	                        
+	                     
+
+	        
+	    
+	     
+	      
+	                         
+	                        
+	                            
+	                     
+	                      
+	                    
+	                     
+	                       
+	                       
+	      
+	                         
+	      
+	   
+	
+
+
+
+
+
+
+
+
+               
+      
+       
+    
+
+
+
+
+       
+      
+       
+    
+        
+	   
+           
+    
+
+
+
+ 
+       
+    
+    
+   
+
+    
+   
+
+
+   
+    
+                                 
+                                 
+
+
+ 
+                                   
+     
+    
+   
+
+
+
+     
+
+
+
+        
+           
+     
+    
+    
+      
+         
+         
+    
+                     
+
+
+     
+   
+
+
+   
+   
+   
+
+               
+     
+     
+                      
+
+
+
+
+
+
+        
+            
+   
+
+       
+           
+    
+            
+           
+               
+    
+
+    
+
+
+
+   
+
+       
+          
+    
+          
+
+
+
+   
+
+       
+    
+          
+          
+          
+          
+    
+     
+    
+         
+
+        
+        
+                    
+               
+                  
+                
+        
+
+        
+        
+                    
+               
+ 
+	       
+                  
+	      
+
+		  
+	   
+                
+        
+        
+        
+        
+                    
+               
+                  
+               
+            
+                  
+                  
+            
+                
+            
+                  
+                  
+            
+        
+
+        
+        
+                    
+               
+            
+                   
+                
+                      
+                      
+                
+            
+        
+
+                
+    
+
+
+ 
+       
+    
+
+   
+
+       
+          
+     
+    
+         
+        
+        
+        
+                    
+               
+                  
+                
+                  
+        
+
+        
+        
+                    
+               
+                    
+        
+
+                
+    
+
+    
+
+   
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+								 
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+           
+              
+              
+              
+
+           
+             
+           
+             
+
+                
+                  
+              
+            
+
+                 
+               
+               
+              
+
+
+
+
+
+   
+    
+    
+        
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+
+
+
+
+
+                               
+                                      
+                             
+                                
+                                       
+
+   
+   
+   
+   
+   
+   
+   
+   
+   
+
+
+
+
+
+                                             
+                                             
+
+                                           
+                                           
+                                           
+
+                         
+                         
+                                          
+                                         
+                        
+          
+
+                                      
+                       
+
+                                            
+
+
+
+
+
+                                    
+   
+                                  
+    
+                                   
+    
+                   
+     
+                                        
+    
+                        
+    
+
+
+
+
+
+                                   
+                                  
+                     
+                     
+        
+  
+                       
+                       
+                                               
+
+          
+         
+          
+         
+                 
+                     
+
+                           
+                                           
+                                              
+                                             
+
+                                        
+                
+             
+                                        
+                   
+
+  
+
+
+
+
+
+ 
+
+
+
+
+
+   
+                     
+	  
+	   
+              
+               
+		 
+		  
+		    
+		     
+		     
+
+		      
+		    
+		     
+		      
+		      
+		      
+		      
+		      
+		      
+		      
+		      
+		          
+		     
+		      
+		         
+             
+           
+             
+		               
+		    
+		      
+		       
+			 
+			  
+			  
+
+			   
+			 
+			  
+			   
+			   
+			   
+			   
+			   
+			   
+			   
+			       
+			       
+			  
+			   
+			  
+		  
+             
+	   
+	   
+	    
+	     
+	       
+	        
+	        
+
+	         
+	       
+		
+		 
+		 
+		 
+		 
+		 
+		 
+		 
+		 
+		 
+		
+		  
+		
+	
+      
+   
+
+
+
+
+
+
+
+               
+      
+       
+    
+
+
+
+
+           
+	   
+   
+    
+        
+	   
+        
+    
+
+
+
+       
+    
+
+ 
+
+       
+          
+    
+    
+              
+              
+              
+              
+    
+
+    
+    
+    
+
+ 
+
+       
+          
+    
+          
+
+    
+
+
+
+ 
+        
+      
+                              
+                             
+    
+      
+                             
+                             
+
+   
+
+     
+                             
+                             
+   
+
+
+ 
+                                   
+     
+    
+   
+
+
+
+     
+       
+
+
+         
+
+
+
+        
+           
+             
+         
+     
+     
+      
+                 
+                 
+             
+             
+    
+
+
+
+             
+   
+
+
+   
+   
+   
+
+           
+     
+                      
+
+
+
+
+
+
+        
+            
+   
+
+       
+           
+    
+            
+           
+               
+    
+
+     
+   
+
+
+   
+
+       
+          
+     
+          
+
+
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+    
+     
+    
+         
+
+        
+        
+        
+               
+                  
+                
+        
+        
+        
+        
+        
+               
+                  
+               
+            
+                  
+                  
+                  
+            
+                
+                  
+        
+
+        
+        
+        
+              
+               
+            
+                   
+                
+                      
+                      
+                
+            
+        
+        
+                
+    
+
+
+
+       
+    
+
+   
+
+       
+          
+     
+    
+         
+        
+        
+        
+        
+               
+                  
+        
+
+        
+        
+        
+               
+                    
+        
+        
+                
+    
+
+    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
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+                    
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+                
+
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+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
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+ 
+ 
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+ 
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+
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+                   
+             
+               
+
+
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+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
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+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+
+                  
+                 
+         
+     
+     
+              
+
+
+
+
+
+  
+    
+     
+    
+    
+    
+    
+    
+    
+    
+    
+ 
+ 
+    
+    
+    
+
+ 
+   
+   
+   
+
+ 
+
+		   
+ 
+    
+    
+    
+    
+    
+ 
+    
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+    
+ 
+    
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+    
+    
+    
+    
+    
+
+
+
+
+                         
+                         
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+
+
+
+
+                                     
+                                     
+
+                        
+                                    
+                                   
+      
+                        
+            
+                      
+ 
+ 
+                     
+       
+                   
+
+    
+                          
+            
+                          
+
+
+
+
+ 
+                                  
+                                  
+                                   
+                               
+                                       
+ 
+                     
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+
+
+
+ 
+                                    
+    
+
+                                    
+    
+                                 
+           
+                                 
+   
+
+
+
+
+
+                                        
+
+
+
+         
+                       
+                
+
+     
+         
+                
+
+                     
+       
+                   
+
+ 
+
+             
+
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+
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+
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+ 
+
+
+
+
+
+
+
+               
+      
+         
+    
+
+ 
+ 
+        
+       
+    
+     
+
+        
+   
+    
+   
+
+    
+               
+
+ 
+               
+      
+             
+                   
+
+
+        
+                   
+    
+   
+
+                
+                 
+
+ 
+         
+         
+         
+
+   
+ 
+         
+         
+         
+
+
+   
+
+   
+   
+   
+
+
+
+
+
+
+
+
+               
+      
+   
+
+       
+    
+          
+          
+    
+    
+    
+                 
+        
+              
+              
+        
+    
+    
+    
+
+
+
+
+               
+      
+   
+
+       
+    
+          
+          
+    
+    
+    
+           
+        
+               
+                  
+                 
+                  
+        
+      
+
+    
+
+
+
+   
+
+       
+          
+    
+    
+               
+              
+    
+    
+
+ 
+
+   
+
+       
+    
+          
+          
+    
+    
+    
+               
+        
+              
+                
+                  
+             
+                  
+        
+         
+        
+        
+            
+                     
+                       
+                    
+                   
+               
+                   
+        
+        
+        
+            
+                   
+                  
+        
+        
+        
+            
+ 
+               
+                  
+             
+
+                            
+            
+                  
+                  
+            
+        
+        
+        
+            
+ 
+               
+                  
+             
+
+                  
+        
+        
+    
+
+
+
+
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+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
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+ 
+ 
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+ 
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+ 
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+ 
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+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_instruction_unit_minimal (
+    
+    clk_i,
+    rst_i,
+    
+    stall_a,
+    stall_f,
+    stall_d,
+    stall_x,
+    stall_m,
+    valid_f,
+    valid_d,
+    kill_f,
+    branch_predict_taken_d,
+    branch_predict_address_d,
+      
+    
+    
+
+
+    exception_m,
+    branch_taken_m,
+    branch_mispredict_taken_m,
+    branch_target_m,
+  
+    
+
+
+  
+    
+    
+    
+
+        
+  
+
+    
+    i_dat_i,
+    i_ack_i,
+    i_err_i,
+    i_rty_i,
+ 
+
+  
+    
+    
+    
+    
+
+
+    
+    
+    pc_f,
+    pc_d,
+    pc_x,
+    pc_m,
+    pc_w,
+  
+    
+    
+    
+    
+
+
+  
+
+    
+    i_dat_o,
+    i_adr_o,
+    i_cyc_o,
+    i_sel_o,
+    i_stb_o,
+    i_we_o,
+    i_cti_o,
+    i_lock_o,
+    i_bte_o,
+ 
+
+  
+    
+    
+    
+
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+
+    instruction_f,
+ 
+    
+    instruction_d
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                   
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam eba_reset_minus_4 = eba_reset - 4;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+  
+  
+   
+        
+   
+
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_f;                                          
+input stall_d;                                          
+input stall_x;                                          
+input stall_m;                                          
+input valid_f;                                          
+input valid_d;                                          
+input kill_f;                                           
+
+input branch_predict_taken_d;                           
+input [ ((32-2)+2-1):2] branch_predict_address_d;          
+   
+      
+                                    
+                     
+
+
+input exception_m;
+input branch_taken_m;                                   
+input branch_mispredict_taken_m;                        
+input [ ((32-2)+2-1):2] branch_target_m;                   
+
+  
+                                            
+
+
+  
+                            
+                             
+ 
+
+        
+
+
+  
+
+input [ (32-1):0] i_dat_i;                         
+input i_ack_i;                                          
+input i_err_i;                                          
+input i_rty_i;                                          
+ 
+
+
+  
+                                  
+                                 
+                   
+                      
+
+
+
+
+
+
+        
+output [ ((32-2)+2-1):2] pc_f;                             
+reg    [ ((32-2)+2-1):2] pc_f;
+output [ ((32-2)+2-1):2] pc_d;                             
+reg    [ ((32-2)+2-1):2] pc_d;
+output [ ((32-2)+2-1):2] pc_x;                             
+reg    [ ((32-2)+2-1):2] pc_x;
+output [ ((32-2)+2-1):2] pc_m;                             
+reg    [ ((32-2)+2-1):2] pc_m;
+output [ ((32-2)+2-1):2] pc_w;                             
+reg    [ ((32-2)+2-1):2] pc_w;
+
+  
+                             
+   
+                           
+   
+                            
+   
+                                 
+   
+
+
+
+  
+
+output [ (32-1):0] i_dat_o;                        
+  
+     
+
+
+wire   [ (32-1):0] i_dat_o;
+ 
+
+output [ (32-1):0] i_adr_o;                        
+reg    [ (32-1):0] i_adr_o;
+output i_cyc_o;                                         
+reg    i_cyc_o; 
+output [ (4-1):0] i_sel_o;                 
+  
+     
+
+
+wire   [ (4-1):0] i_sel_o;
+ 
+
+output i_stb_o;                                         
+reg    i_stb_o;
+output i_we_o;                                          
+  
+    
+
+
+wire   i_we_o;
+ 
+
+output [ (3-1):0] i_cti_o;                       
+reg    [ (3-1):0] i_cti_o;
+output i_lock_o;                                        
+reg    i_lock_o;
+output [ (2-1):0] i_bte_o;                       
+wire   [ (2-1):0] i_bte_o;
+ 
+
+
+  
+                   
+     
+                             
+   
+
+
+
+  
+                                      
+    
+
+
+  
+
+output [ (32-1):0] instruction_f;           
+wire   [ (32-1):0] instruction_f;
+ 
+
+output [ (32-1):0] instruction_d;           
+reg    [ (32-1):0] instruction_d;
+
+
+
+
+
+reg [ ((32-2)+2-1):2] pc_a;                                
+
+  
+                       
+
+
+
+  
+                               
+                
+                                 
+           
+               
+                  
+                   
+                                          
+                        
+
+
+  
+
+reg [ (32-1):0] wb_data_f;                  
+ 
+
+ 
+
+  
+                                      
+    			     
+   
+
+
+  
+
+ 
+               
+
+
+
+   
+  
+   
+    			               
+ 
+
+
+  
+    		       
+
+
+   
+  
+                                         
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+ 
+              
+                       
+             
+               
+                      
+       
+    
+                      
+                            
+                    
+                    
+     
+                    
+                  
+                  
+              
+               
+                
+                     
+    
+              
+            
+             
+             
+                  
+                       
+    
+
+
+
+
+
+
+
+  
+   
+           
+        
+  
+      
+                          
+   
+				       
+        
+				    
+
+ 
+
+
+always @(*)
+begin
+    
+  
+       
+          
+     
+
+    
+      if (branch_taken_m ==  1'b1)
+	if ((branch_mispredict_taken_m ==  1'b1) && (exception_m ==  1'b0))
+	  pc_a = pc_x;
+	else
+          pc_a = branch_target_m;
+      
+          
+          
+
+
+      else
+	if ( (valid_d ==  1'b1) && (branch_predict_taken_d ==  1'b1) )
+	  pc_a = branch_predict_address_d;
+	else
+  
+             
+              
+	   
+
+        
+            pc_a = pc_f + 1'b1;
+end
+
+
+  
+      
+      
+        
+
+
+
+  
+
+     
+    	      
+
+     
+      
+	  
+       
+	  
+	
+	    
+     
+   
+   
+          
+
+
+  
+   
+
+
+                     
+
+  
+   
+
+
+assign instruction_f = wb_data_f;
+ 
+
+
+ 
+ 
+   
+
+  
+
+  
+
+
+assign i_dat_o = 32'd0;
+assign i_we_o =  1'b0;
+assign i_sel_o = 4'b1111;
+ 
+
+assign i_bte_o =  2'b00;
+ 
+
+
+  
+
+
+     
+    
+    
+   
+   
+   
+   
+    
+    
+    
+   
+   
+     
+    
+    
+    
+    
+   
+         
+     
+    
+    
+    
+
+
+
+                     
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        pc_f <= eba_reset_minus_4[ ((32-2)+2-1):2];
+        pc_d <= { (32-2){1'b0}};
+        pc_x <= { (32-2){1'b0}};
+        pc_m <= { (32-2){1'b0}};
+        pc_w <= { (32-2){1'b0}};
+    end
+    else
+    begin
+        if (stall_f ==  1'b0)
+            pc_f <= pc_a;
+        if (stall_d ==  1'b0)
+            pc_d <= pc_f;
+        if (stall_x ==  1'b0)
+            pc_x <= pc_d;
+        if (stall_m ==  1'b0)
+            pc_m <= pc_x;
+        pc_w <= pc_m;
+    end
+end
+
+  
+
+   
+
+       
+          
+    
+    
+ 
+         
+            
+               
+                  
+                    
+                  
+
+               
+                  
+
+
+         
+               
+                  
+
+
+    
+
+
+
+
+
+  
+   
+
+       
+          
+    
+    
+           
+              
+    
+
+
+
+
+  
+    
+                 
+ 
+
+     
+       
+       
+       
+       
+     
+
+   
+
+
+
+  
+
+   
+                   
+      
+     
+	   
+	  
+               
+               
+               
+               
+               
+               
+               
+   
+               
+  
+   
+               
+               
+               
+  
+	  
+	
+	     
+               
+             
+                
+               
+		  
+		         
+		    
+   
+                          
+			 
+			      
+			             
+			        
+			          
+			 
+                       
+  
+			 
+			       
+			      
+				 
+				   
+				   
+				   
+			      
+			    
+			        
+			      
+			    
+			      
+			      
+			 
+		    
+   
+		   
+		     
+		    
+                         
+                         
+		    
+		  
+  
+               
+             
+               
+		         
+		    
+                       
+        
+                         
+  
+                          
+                         
+                                         
+                         
+                       
+   
+                         
+  
+		    
+   
+		  
+		    
+                              
+			 
+			     
+			         
+			         
+			         
+			         
+			    
+			      
+			      
+			      
+			      
+			      
+			      
+			      
+			 
+		     
+                      
+   
+		  
+		  
+        
+		     
+                      
+   
+		     
+                      
+  
+               
+	  
+     
+ 
+
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             i_cyc_o <=  1'b0;
+             i_stb_o <=  1'b0;
+             i_adr_o <= { 32{1'b0}};
+             i_cti_o <=  3'b111;
+             i_lock_o <=  1'b0;
+             wb_data_f <= { 32{1'b0}};
+    
+               
+  
+
+	  end
+	else
+	  begin   
+             
+             if (i_cyc_o ==  1'b1)
+               begin
+		  
+		  if((i_ack_i ==  1'b1) || (i_err_i ==  1'b1))
+		    begin
+                       
+                       i_cyc_o <=  1'b0;
+                       i_stb_o <=  1'b0;
+                       
+                       wb_data_f <= i_dat_i;
+		    end
+    
+		   
+		     
+		    
+                         
+                         
+		       
+		    
+		  
+  
+
+               end
+             else
+               begin
+		  
+		  if (   (stall_a ==  1'b0) 
+     
+			    
+  
+       
+			 )
+		    begin
+                       
+         
+                         
+  
+
+                       i_adr_o <= {pc_a, 2'b00};
+                       i_cyc_o <=  1'b1;
+                       i_stb_o <=  1'b1;
+    
+                         
+  
+
+		    end
+		  else
+		    begin
+	               if (   (stall_a ==  1'b0) 
+     
+			         
+  
+       
+			      )
+			 begin
+    
+			      
+  
+
+			 end
+		    end
+               end
+	  end
+     end
+  
+
+ 
+ 
+
+   
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             instruction_d <= { 32{1'b0}};
+  
+               
+
+
+	  end
+	else
+	  begin
+             if (stall_d ==  1'b0)
+               begin
+		  instruction_d <= instruction_f;
+  
+		    
+
+
+               end
+	  end
+     end  
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+  
+
+                              
+                              
+                              
+
+
+                          
+                  
+                 
+              
+             
+                    
+                        
+                        
+
+
+                  
+         
+          
+          
+          
+          
+          
+      
+      
+         
+
+
+
+
+
+  
+    
+    
+    
+     
+    
+    
+    
+ 
+    
+    
+    
+    
+
+ 
+    
+    
+
+ 
+    
+
+    
+ 
+    
+    
+
+ 
+    
+    
+    
+    
+    
+    
+    
+
+ 
+    
+    
+
+    
+    
+    
+
+
+
+
+
+                                             
+                                             
+
+                                          
+                                       
+                        
+                              
+
+ 
+                                
+                                  
+                    
+                                           
+
+ 
+                    
+                              
+
+ 
+                                     
+
+
+
+
+
+       
+ 
+                
+    
+                
+    
+
+ 
+                            
+    
+              
+    
+                          
+    
+                                 
+    
+                                
+    
+                  
+            
+                     
+    
+
+ 
+                                       
+    
+                                       
+    
+
+  
+     
+  
+    
+             
+
+
+
+
+                           
+                         
+                       
+                     
+
+
+
+     
+  
+
+                  
+        
+                       
+        
+                       
+
+
+               
+ 
+         
+  
+  
+  
+  
+                          
+
+
+         
+
+
+
+
+
+ 
+      
+   
+      
+   
+
+                 
+
+                  
+             
+
+   
+
+ 
+   
+
+   
+
+
+                  
+     
+     
+         
+                 
+
+
+
+
+   
+   
+
+
+
+   
+
+       
+    
+          
+          
+          
+          
+    
+    
+    
+          
+          
+          
+          
+    
+
+
+
+   
+
+       
+    
+          
+          
+          
+ 
+          
+          
+          
+          
+
+ 
+          
+          
+
+                  
+          
+          
+          
+          
+
+    
+    
+    
+                  
+               
+        
+             
+            
+            
+                
+                  
+                  
+            
+            
+            
+                
+                  
+            
+            
+        
+
+ 
+        
+           
+        
+              
+              
+        
+
+         
+        
+        
+            
+                 
+            
+                                  
+                 
+ 
+                
+                
+                     
+ 
+                    
+                          
+                    
+                    
+                              
+                          
+                    
+                    
+                          
+                    
+                    
+                              
+                          
+                    
+                    
+                          
+                    
+                    
+                    
+      
+                              
+                                   
+
+                          
+                    
+                    
+                    
+      
+                              
+                                   
+
+                          
+                    
+                                                   
+                
+
+                  
+                
+                
+                      
+                      
+                                    
+                
+                
+                      
+                      
+                
+
+                
+                    
+                                
+            
+        
+ 
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+                 
+            
+                  
+                   
+                      
+                 
+                      
+            
+        
+        
+        
+                 
+            
+                  
+                  
+            
+        
+        
+        
+             
+            
+            
+            
+                  
+                  
+                  
+            
+            
+            
+            
+                  
+                  
+                  
+            
+            
+            
+                  
+                  
+                  
+            
+            
+        
+        
+        
+               
+                      
+                  
+                  
+                    
+                  
+                  
+            
+            
+        
+        
+              
+              
+              
+            
+
+        
+    
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_interrupt_minimal (
+    
+    clk_i, 
+    rst_i,
+    
+    interrupt,
+    
+    stall_x,
+  
+    
+    
+
+
+    exception,
+ 
+
+    eret_q_x,
+  
+    
+
+
+    csr,
+    csr_write_data,
+    csr_write_enable,
+    
+    interrupt_exception,
+    
+    csr_read_data
+    );
+
+
+
+
+
+parameter interrupts =  32;         
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [interrupts-1:0] interrupt;               
+
+input stall_x;                                  
+
+  
+                       
+                           
+
+
+input exception;                                
+ 
+
+input eret_q_x;                                 
+  
+                                  
+
+
+
+input [ (4 -1):0] csr;                      
+input [ (32-1):0] csr_write_data;          
+input csr_write_enable;                         
+
+
+
+
+
+output interrupt_exception;                     
+wire   interrupt_exception;
+
+output [ (32-1):0] csr_read_data;          
+reg    [ (32-1):0] csr_read_data;
+
+
+
+
+
+wire [interrupts-1:0] asserted;                 
+
+wire [interrupts-1:0] interrupt_n_exception;
+
+
+
+reg ie;                                         
+reg eie;                                        
+  
+                                         
+
+
+reg [interrupts-1:0] ip;                        
+reg [interrupts-1:0] im;                        
+
+
+
+
+
+
+assign interrupt_n_exception = ip & im;
+
+
+assign interrupt_exception = (|interrupt_n_exception) & ie;
+
+
+assign asserted = ip | interrupt;
+       
+generate
+    if (interrupts > 1) 
+    begin
+
+always @(*)
+begin
+    case (csr)
+     4 'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+                                    
+
+
+                                    1'b0,                                     
+ 
+
+                                    eie, 
+                                    ie
+                                   };
+     4 'h2:  csr_read_data = ip;
+     4 'h1:  csr_read_data = im;
+    default:       csr_read_data = { 32{1'bx}};
+    endcase
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    case (csr)
+     4 'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+                                     
+
+
+                                    1'b0,                                    
+ 
+
+                                    eie, 
+                                    ie
+                                   };
+     4 'h2:  csr_read_data = ip;
+    default:       csr_read_data = { 32{1'bx}};
+      endcase
+end
+    end
+endgenerate
+    
+
+
+
+
+  
+
+   reg [ 10:0] eie_delay  = 0;
+
+   
+generate
+
+   
+    if (interrupts > 1)
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie                   <=  1'b0;
+        eie                  <=  1'b0;
+  
+                           
+
+
+        im                   <= {interrupts{1'b0}};
+        ip                   <= {interrupts{1'b0}};
+       eie_delay             <= 0;
+       
+    end
+    else
+    begin
+        
+        ip                   <= asserted;
+  
+           
+        
+            
+                           
+                            
+        
+            
+        
+            
+                           
+                            
+        
+
+
+        if (exception ==  1'b1)
+        begin
+            
+            eie              <= ie;
+            ie               <=  1'b0;
+        end
+ 
+
+        else if (stall_x ==  1'b0)
+        begin
+
+           if(eie_delay[0])
+             ie              <= eie;
+           
+           eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+            if (eret_q_x ==  1'b1) begin
+                
+               eie_delay[ 10] <=  1'b1;
+               eie_delay[ 10-1:0] <= 0;
+            end
+           
+                      
+           
+  
+                
+                
+                       
+
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  4 'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+                      
+
+
+                end
+                if (csr ==  4 'h1)
+                    im  <= csr_write_data[interrupts-1:0];
+                if (csr ==  4 'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+else
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie              <=  1'b0;
+        eie             <=  1'b0;
+  
+                      
+
+
+        ip              <= {interrupts{1'b0}};
+       eie_delay        <= 0;
+    end
+    else
+    begin
+        
+        ip              <= asserted;
+  
+           
+        
+            
+                      
+                       
+        
+            
+        
+            
+                      
+                       
+        
+
+
+        if (exception ==  1'b1)
+        begin
+            
+            eie         <= ie;
+            ie          <=  1'b0;
+        end
+ 
+
+        else if (stall_x ==  1'b0)
+          begin
+
+             if(eie_delay[0])
+               ie              <= eie;
+           
+             eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+             if (eret_q_x ==  1'b1) begin
+                
+                eie_delay[ 10] <=  1'b1;
+                eie_delay[ 10-1:0] <= 0;
+             end
+           
+  
+                
+                
+                       
+
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  4 'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+                      
+
+
+                end
+                if (csr ==  4 'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+
+	  
+	 
+	 
+	 
+	 
+	
+
+ 
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+  
+
+
+
+
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+
+
+  
+ 
+
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+
+
+  
+                    
+
+
+  
+                    
+
+
+  
+
+  
+
+ 
+
+ 
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+ 
+
+
+  
+
+  
+
+ 
+
+ 
+
+
+
+  
+ 
+
+
+  
+
+  
+
+ 
+
+
+ 
+
+
+
+  
+
+  
+
+  
+ 
+ 
+
+ 
+
+
+ 
+
+
+  
+
+  
+
+ 
+ 
+ 
+
+
+
+
+
+  
+
+  
+
+ 
+
+  
+ 
+
+
+  
+ 
+
+
+
+
+  
+
+  
+
+ 
+
+  
+ 
+
+
+
+
+  
+
+
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+ 
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+ 
+
+  
+
+  
+
+  
+
+  
+                     
+                     
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+ 
+ 
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+  
+
+  
+
+
+  
+
+  
+
+
+
+  
+ 
+
+
+  
+ 
+
+
+ 
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+ 
+
+
+
+
+
+
+
+
+module lm32_top_wr_node (
+    
+    clk_i,
+    rst_i,
+    
+
+    interrupt,
+
+    
+  
+    
+    
+
+     
+  
+    
+    
+    
+    
+    
+
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+      
+    
+    
+    
+    
+
+    
+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+
+
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+    );
+
+parameter eba_reset = 32'h00000000;
+parameter sdb_address = 32'h00000000;
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+
+input [ (32-1):0] interrupt;          
+
+
+  
+               
+                             
+
+    
+
+  
+                   
+                                   
+                                   
+                                   
+
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+                  
+    
+                  
+    
+                                  
+   
+           
+    
+                                  
+   
+                                   
+   
+                 
+    
+                                 
+   
+                 
+    
+
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+  
+
+
+
+ 
+  
+
+  
+  
+ 
+  
+  
+ 
+ 
+
+
+
+
+  
+
+                     
+                             
+                            
+                   
+                                 
+ 
+                                 
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+   
+
+lm32_cpu_wr_node 
+	#(
+		.eba_reset(eba_reset),
+    .sdb_address(sdb_address)
+	) cpu (
+    
+    .clk_i                 (clk_i),
+  
+                   
+
+
+    .rst_i                 (rst_i),
+    
+  
+
+    .interrupt             (interrupt),
+ 
+
+    
+  
+               
+             
+
+     
+  
+    
+                  
+               
+                
+           
+
+
+  
+     
+                   
+                   
+                   
+                   
+
+
+    
+    .D_DAT_I               (D_DAT_I),
+    .D_ACK_I               (D_ACK_I),
+    .D_ERR_I               (D_ERR_I),
+    .D_RTY_I               (D_RTY_I),
+    
+  
+                  
+            
+           
+                 
+                
+ 
+                
+
+
+
+  
+                
+           
+
+
+      
+                
+               
+            
+            
+
+    
+  
+    
+                   
+                   
+                   
+                   
+                   
+                    
+                   
+                  
+                   
+    
+
+    
+    .D_DAT_O               (D_DAT_O),
+    .D_ADR_O               (D_ADR_O),
+    .D_CYC_O               (D_CYC_O),
+    .D_SEL_O               (D_SEL_O),
+    .D_STB_O               (D_STB_O),
+    .D_WE_O                (D_WE_O),
+    .D_CTI_O               (D_CTI_O),
+    .D_LOCK_O              (D_LOCK_O),
+    .D_BTE_O               (D_BTE_O)
+    );
+   
+  		   
+
+  
+    
+                     
+                
+    
+                
+                     
+                
+                      
+                     
+    
+
+        
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+           
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_mc_arithmetic_wr_node (
+    
+    clk_i,
+    rst_i,
+    stall_d,
+    kill_x,
+  
+
+    divide_d,
+    modulus_d,
+ 
+
+  
+    
+
+
+  
+    
+    
+    
+
+
+    operand_0_d,
+    operand_1_d,
+    
+    result_x,
+  
+
+    divide_by_zero_x,
+ 
+
+    stall_request_x
+    );
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+input stall_d;                                  
+input kill_x;                                   
+  
+
+input divide_d;                                 
+input modulus_d;                                
+ 
+
+  
+                                
+
+
+  
+                              
+                             
+                             
+
+
+input [ (32-1):0] operand_0_d;
+input [ (32-1):0] operand_1_d;
+
+
+
+
+
+output [ (32-1):0] result_x;               
+reg    [ (32-1):0] result_x;
+  
+
+output divide_by_zero_x;                        
+reg    divide_by_zero_x;
+ 
+
+output stall_request_x;                         
+wire   stall_request_x;
+
+
+
+
+
+reg [ (32-1):0] p;                         
+reg [ (32-1):0] a;
+reg [ (32-1):0] b;
+  
+
+wire [32:0] t;
+ 
+
+
+reg [ 2:0] state;                 
+reg [5:0] cycles;                               
+
+  
+                               
+                                 
+
+
+
+
+
+
+
+
+assign stall_request_x = state !=  3'b000;
+
+  
+
+
+assign t = {p[ 32-2:0], a[ 32-1]} - b;
+ 
+
+
+  
+
+       
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        cycles <= {6{1'b0}};
+        p <= { 32{1'b0}};
+        a <= { 32{1'b0}};
+        b <= { 32{1'b0}};
+  
+          
+
+
+  
+
+        divide_by_zero_x <=  1'b0;
+ 
+
+        result_x <= { 32{1'b0}};
+        state <=  3'b000;
+    end
+    else
+    begin
+  
+
+        divide_by_zero_x <=  1'b0;
+ 
+
+        case (state)
+         3'b000:
+        begin
+            if (stall_d ==  1'b0)                 
+            begin          
+                cycles <=  32;
+                p <= 32'b0;
+                a <= operand_0_d;
+                b <= operand_1_d;                    
+  
+
+                if (divide_d ==  1'b1)
+                    state <=  3'b011 ;
+                if (modulus_d ==  1'b1)
+                    state <=  3'b010   ;
+ 
+                    
+  
+                   
+                      
+
+
+  
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+                   
+                
+                      
+                      
+                      
+                      
+                      
+                
+
+
+            end            
+        end
+  
+
+         3'b011 :
+        begin
+            if (t[32] == 1'b0)
+            begin
+                p <= t[31:0];
+                a <= {a[ 32-2:0], 1'b1};
+            end
+            else 
+            begin
+                p <= {p[ 32-2:0], a[ 32-1]};
+                a <= {a[ 32-2:0], 1'b0};
+            end
+            result_x <= a;
+            if ((cycles ==  32'd0) || (kill_x ==  1'b1))
+            begin
+                
+                divide_by_zero_x <= b == { 32{1'b0}};
+                state <=  3'b000;
+            end
+            cycles <= cycles - 1'b1;
+        end
+         3'b010   :
+        begin
+            if (t[32] == 1'b0)
+            begin
+                p <= t[31:0];
+                a <= {a[ 32-2:0], 1'b1};
+            end
+            else 
+            begin
+                p <= {p[ 32-2:0], a[ 32-1]};
+                a <= {a[ 32-2:0], 1'b0};
+            end
+            result_x <= p;
+            if ((cycles ==  32'd0) || (kill_x ==  1'b1))
+            begin
+                
+                divide_by_zero_x <= b == { 32{1'b0}};
+                state <=  3'b000;
+            end
+            cycles <= cycles - 1'b1;
+        end
+ 
+        
+  
+        
+        
+               
+                    
+               
+               
+              
+                   
+                  
+                
+        
+
+     
+  
+        
+               
+               
+              
+                   
+                  
+                
+        
+        
+               
+               
+              
+                   
+                  
+                
+        
+
+   
+        endcase
+    end
+end 
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_cpu_wr_node (
+    
+    clk_i,
+  
+    
+
+
+    rst_i,
+  
+
+    enable_i,
+ 
+
+  
+
+   dbg_exception_o,
+   dbg_csr_write_enable_i,
+   dbg_csr_write_data_i,
+   dbg_csr_addr_i,
+   dbg_break_i,
+   dbg_reset_i,
+ 
+
+
+    
+  
+
+    interrupt,
+ 
+
+    
+  
+    
+    
+
+     
+  
+    
+    
+     
+    
+    
+
+
+  
+    
+    
+    
+    
+    
+
+
+    
+    D_DAT_I,
+    D_ACK_I,
+    D_ERR_I,
+    D_RTY_I,
+    
+  
+    
+    
+    
+    
+    
+ 
+    
+
+
+
+  
+    
+    
+
+
+      
+    
+    
+    
+    
+
+    
+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+
+ 
+  
+
+    iram_i_adr_o,
+    iram_i_dat_i,
+    iram_i_en_o,
+    iram_d_adr_o,
+    iram_d_dat_o,
+    iram_d_dat_i,
+    iram_d_sel_o,
+    iram_d_we_o,
+    iram_d_en_o,       
+ 
+
+		 
+		 
+    
+    D_DAT_O,
+    D_ADR_O,
+    D_CYC_O,
+    D_SEL_O,
+    D_STB_O,
+    D_WE_O,
+    D_CTI_O,
+    D_LOCK_O,
+    D_BTE_O
+
+		 
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                           
+  
+
+parameter deba_reset =  32'h10000000;                         
+ 
+
+parameter sdb_address =   32'h00000000;
+
+  
+        
+                          
+      
+          
+                        
+
+
+parameter icache_associativity = 1;    
+parameter icache_sets = 512;                      
+parameter icache_bytes_per_line = 16;  
+parameter icache_base_address = 0;      
+parameter icache_limit = 0;                    
+ 
+
+
+  
+        
+                          
+      
+          
+                        
+
+
+parameter dcache_associativity = 1;    
+parameter dcache_sets = 512;                      
+parameter dcache_bytes_per_line = 16;  
+parameter dcache_base_address = 0;      
+parameter dcache_limit = 0;                    
+ 
+
+
+  
+
+parameter watchpoints =  32'h4;                       
+ 
+   
+
+
+  
+                          
+
+
+parameter breakpoints = 0;
+ 
+
+
+  
+
+parameter interrupts =  32;                         
+ 
+   
+
+
+
+
+
+
+
+input clk_i;                                    
+  
+                                   
+
+    
+input rst_i;                                    
+
+  
+
+input [ (32-1):0] interrupt;          
+ 
+
+
+  
+               
+                             
+
+    
+
+   
+                                  
+                               
+                
+  
+
+
+
+  
+                   
+                                   
+                                   
+                                   
+
+
+
+input [ (32-1):0] D_DAT_I;                 
+input D_ACK_I;                                  
+input D_ERR_I;                                  
+input D_RTY_I;                                  
+
+
+
+
+
+  
+
+   input enable_i;
+   wire  enable_i;
+ 
+
+   
+   
+  
+                   
+     
+                           
+    
+                          
+    
+                 
+     
+                               
+    
+ 
+                               
+    
+
+
+
+
+  
+  
+    
+  
+    
+
+
+
+  
+                               
+   
+       
+     
+           
+    
+           
+    
+
+
+
+  
+                  
+    
+                  
+    
+                                  
+   
+           
+    
+                                  
+   
+                                   
+   
+                 
+    
+                                 
+   
+                 
+    
+
+
+
+output [ (32-1):0] D_DAT_O;                
+wire   [ (32-1):0] D_DAT_O;
+output [ (32-1):0] D_ADR_O;                
+wire   [ (32-1):0] D_ADR_O;
+output D_CYC_O;                                 
+wire   D_CYC_O;
+output [ (4-1):0] D_SEL_O;         
+wire   [ (4-1):0] D_SEL_O;
+output D_STB_O;                                 
+wire   D_STB_O;
+output D_WE_O;                                  
+wire   D_WE_O;
+output [ (3-1):0] D_CTI_O;               
+wire   [ (3-1):0] D_CTI_O;
+output D_LOCK_O;                                
+wire   D_LOCK_O;
+output [ (2-1):0] D_BTE_O;               
+wire   [ (2-1):0] D_BTE_O;
+
+  
+
+   output [31:0] iram_i_adr_o, iram_d_adr_o;
+   output [31:0] iram_d_dat_o;
+   input [31:0]  iram_i_dat_i, iram_d_dat_i;
+   output [3:0]  iram_d_sel_o;
+   output        iram_d_en_o, iram_i_en_o, iram_d_we_o;
+ 
+
+   
+
+
+
+
+
+
+  
+                                     
+
+
+reg valid_f;                                    
+reg valid_d;                                    
+reg valid_x;                                    
+reg valid_m;                                    
+reg valid_w;                                    
+   
+wire q_x;
+wire [ (32-1):0] immediate_d;              
+wire load_d;                                    
+reg load_x;                                     
+reg load_m;
+wire load_q_x;
+wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
+wire store_d;                                   
+reg store_x;
+reg store_m;
+wire [ 1:0] size_d;                   
+reg [ 1:0] size_x;
+wire branch_d;                                  
+wire branch_predict_d;                          
+wire branch_predict_taken_d;                    
+wire [ ((32-2)+2-1):2] branch_predict_address_d;   
+wire [ ((32-2)+2-1):2] branch_target_d;
+wire bi_unconditional;
+wire bi_conditional;
+reg branch_x;                                   
+reg branch_predict_x;
+reg branch_predict_taken_x;
+reg branch_m;
+reg branch_predict_m;
+reg branch_predict_taken_m;
+wire branch_mispredict_taken_m;                 
+wire branch_flushX_m;                           
+wire branch_reg_d;                              
+wire [ ((32-2)+2-1):2] branch_offset_d;            
+reg [ ((32-2)+2-1):2] branch_target_x;             
+reg [ ((32-2)+2-1):2] branch_target_m;
+wire [ 0:0] d_result_sel_0_d; 
+wire [ 1:0] d_result_sel_1_d; 
+
+wire x_result_sel_csr_d;                        
+reg x_result_sel_csr_x;
+  
+
+wire q_d;
+wire x_result_sel_mc_arith_d;                   
+reg x_result_sel_mc_arith_x;
+ 
+
+      
+                       
+ 
+
+
+  
+
+wire x_result_sel_sext_d;                       
+reg x_result_sel_sext_x;
+ 
+
+wire x_result_sel_logic_d;                      
+  
+                        
+ 
+
+
+wire x_result_sel_add_d;                        
+reg x_result_sel_add_x;
+wire m_result_sel_compare_d;                    
+reg m_result_sel_compare_x;
+reg m_result_sel_compare_m;
+  
+
+wire m_result_sel_shift_d;                      
+reg m_result_sel_shift_x;
+reg m_result_sel_shift_m;
+ 
+
+wire w_result_sel_load_d;                       
+reg w_result_sel_load_x;
+reg w_result_sel_load_m;
+reg w_result_sel_load_w;
+  
+
+wire w_result_sel_mul_d;                        
+reg w_result_sel_mul_x;
+reg w_result_sel_mul_m;
+reg w_result_sel_mul_w;
+ 
+
+wire x_bypass_enable_d;                         
+reg x_bypass_enable_x;                          
+wire m_bypass_enable_d;                         
+reg m_bypass_enable_x;                          
+reg m_bypass_enable_m;
+wire sign_extend_d;                             
+reg sign_extend_x;
+wire write_enable_d;                            
+reg write_enable_x;
+wire write_enable_q_x;
+reg write_enable_m;
+wire write_enable_q_m;
+reg write_enable_w;
+wire write_enable_q_w;
+wire read_enable_0_d;                           
+wire [ (5-1):0] read_idx_0_d;          
+wire read_enable_1_d;                           
+wire [ (5-1):0] read_idx_1_d;          
+wire [ (5-1):0] write_idx_d;           
+reg [ (5-1):0] write_idx_x;            
+reg [ (5-1):0] write_idx_m;
+reg [ (5-1):0] write_idx_w;
+wire [ (5-1):0] csr_d;                     
+reg  [ (5-1):0] csr_x;                  
+wire [ (3-1):0] condition_d;         
+reg [ (3-1):0] condition_x;          
+  
+
+wire break_d;                                   
+reg break_x;                                    
+ 
+
+wire scall_d;                                   
+reg scall_x;    
+wire eret_d;                                    
+reg eret_x;
+wire eret_q_x;
+  
+ 
+ 
+
+
+  
+
+wire bret_d;                                    
+reg bret_x;
+wire bret_q_x;
+  
+ 
+ 
+
+
+ 
+
+wire csr_write_enable_d;                        
+reg csr_write_enable_x;
+wire csr_write_enable_q_x;
+  
+       
+
+
+
+  
+
+wire bus_error_d;                               
+reg bus_error_x;
+reg data_bus_error_exception_m;
+reg [ ((32-2)+2-1):2] memop_pc_w;
+ 
+
+
+reg [ (32-1):0] d_result_0;                
+reg [ (32-1):0] d_result_1;                
+reg [ (32-1):0] x_result;                  
+reg [ (32-1):0] m_result;                  
+reg [ (32-1):0] w_result;                  
+
+reg [ (32-1):0] operand_0_x;               
+reg [ (32-1):0] operand_1_x;               
+reg [ (32-1):0] store_operand_x;           
+reg [ (32-1):0] operand_m;                 
+reg [ (32-1):0] operand_w;                 
+
+
+  
+
+reg [ (32-1):0] reg_data_live_0;          
+reg [ (32-1):0] reg_data_live_1;  
+reg use_buf;                                    
+reg [ (32-1):0] reg_data_buf_0;
+reg [ (32-1):0] reg_data_buf_1;
+ 
+
+  
+
+ 
+     
+
+
+wire [ (32-1):0] reg_data_0;               
+wire [ (32-1):0] reg_data_1;               
+reg [ (32-1):0] bypass_data_0;             
+reg [ (32-1):0] bypass_data_1;             
+wire reg_write_enable_q_w;
+
+reg interlock;                                  
+
+wire stall_a;                                   
+wire stall_f;                                   
+wire stall_d;                                   
+wire stall_x;                                   
+wire stall_m;                                   
+
+
+wire adder_op_d;                                
+reg adder_op_x;                                 
+reg adder_op_x_n;                               
+wire [ (32-1):0] adder_result_x;           
+wire adder_overflow_x;                          
+wire adder_carry_n_x;                           
+
+
+wire [ 3:0] logic_op_d;           
+reg [ 3:0] logic_op_x;            
+wire [ (32-1):0] logic_result_x;           
+
+  
+
+
+wire [ (32-1):0] sextb_result_x;           
+wire [ (32-1):0] sexth_result_x;           
+wire [ (32-1):0] sext_result_x;            
+ 
+
+
+
+  
+
+  
+                                   
+                                     
+
+
+wire direction_d;                               
+reg direction_x;                                        
+wire [ (32-1):0] shifter_result_m;         
+ 
+
+  
+                               
+ 
+                              
+ 
+
+
+  
+           
+
+
+
+
+  
+
+wire [ (32-1):0] multiplier_result_w;      
+ 
+
+  
+                                 
+ 
+
+
+
+
+  
+
+wire divide_d;                                  
+wire divide_q_d;
+wire modulus_d;
+wire modulus_q_d;
+wire divide_by_zero_x;                          
+ 
+
+
+
+  
+
+wire mc_stall_request_x;                        
+wire [ (32-1):0] mc_result_x;
+ 
+
+
+
+  
+
+wire [ (32-1):0] interrupt_csr_read_data_x;
+ 
+
+wire [ (32-1):0] cfg;                      
+wire [ (32-1):0] cfg2;                     
+  
+                          
+
+
+reg [ (32-1):0] csr_read_data_x;           
+
+
+wire [ ((32-2)+2-1):2] pc_f;                       
+wire [ ((32-2)+2-1):2] pc_d;                       
+wire [ ((32-2)+2-1):2] pc_x;                       
+wire [ ((32-2)+2-1):2] pc_m;                       
+wire [ ((32-2)+2-1):2] pc_w;                       
+  
+                          
+
+
+  
+
+wire [ (32-1):0] instruction_f;     
+ 
+
+
+
+wire [ (32-1):0] instruction_d;     
+  
+                                     
+                       
+                     
+                      
+                           
+
+
+
+
+  
+                                   
+                                     
+                       
+                     
+                      
+                           
+
+
+wire [ (32-1):0] load_data_w;              
+wire stall_wb_load;                             
+
+
+  
+ 
+          
+          
+
+ 
+                      
+        
+                    
+                           
+  
+ 
+  
+  
+ 
+
+ 
+                                 
+
+
+
+
+
+wire raw_x_0;                                   
+wire raw_x_1;                                   
+wire raw_m_0;                                   
+wire raw_m_1;                                   
+wire raw_w_0;                                   
+wire raw_w_1;                                   
+
+
+wire cmp_zero;                                  
+wire cmp_negative;                              
+wire cmp_overflow;                              
+wire cmp_carry_n;                               
+reg condition_met_x;                            
+reg condition_met_m;
+      
+                             
+
+
+wire branch_taken_m;                            
+
+wire kill_f;                                    
+wire kill_d;                                    
+wire kill_x;                                    
+wire kill_m;                                    
+wire kill_w;                                    
+
+reg [ (32-2)+2-1:8] eba;                 
+  
+
+reg [ (32-2)+2-1:8] deba;                
+ 
+
+reg [ (3-1):0] eid_x;                      
+  
+                        
+                        
+
+
+
+  
+
+  
+
+wire dc_ss;                                     
+ 
+
+wire dc_re;                                     
+wire bp_match;
+wire wp_match;
+wire exception_x;                               
+reg exception_m;                                
+wire debug_exception_x;                         
+reg debug_exception_m;
+reg debug_exception_w;
+wire debug_exception_q_w;
+wire non_debug_exception_x;                     
+reg non_debug_exception_m;
+reg non_debug_exception_w;
+wire non_debug_exception_q_w;
+ 
+                                
+ 
+ 
+ 
+
+
+
+  
+
+   
+                            
+
+
+  
+
+wire reset_exception;                           
+ 
+
+ 
+
+  
+
+wire interrupt_exception;                       
+ 
+
+  
+
+wire breakpoint_exception;                      
+wire watchpoint_exception;                      
+ 
+
+  
+
+   reg [ (32-1):0] data_bus_error_addr;
+   
+wire instruction_bus_error_exception;           
+wire data_bus_error_exception;                  
+ 
+
+  
+
+wire divide_by_zero_exception;                  
+ 
+
+wire system_call_exception;                     
+
+  
+
+reg data_bus_error_seen;                        
+ 
+
+
+   
+
+   wire iram_stall_request_x;
+ 
+
+     
+  
+
+input dbg_csr_write_enable_i;                         
+wire   dbg_csr_write_enable_i;
+input [ (32-1):0] dbg_csr_write_data_i;          
+wire  [ (32-1):0] dbg_csr_write_data_i;
+input [ (5-1):0] dbg_csr_addr_i;                        
+wire  [ (5-1):0] dbg_csr_addr_i;
+
+   output 	      dbg_exception_o;
+   wire 	      dbg_exception_o;
+   input 	      dbg_reset_i;
+   wire 	      dbg_reset_i;
+   input 	      dbg_break_i;
+   wire 	      dbg_break_i;
+   
+   
+ 
+
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+lm32_instruction_unit_wr_node #(
+    .eba_reset              (eba_reset),
+    .associativity          (icache_associativity),
+    .sets                   (icache_sets),
+    .bytes_per_line         (icache_bytes_per_line),
+    .base_address           (icache_base_address),
+    .limit                  (icache_limit)
+  ) instruction_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_f                (stall_f),
+    .stall_d                (stall_d),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .valid_f                (valid_f),
+    .valid_d                (valid_d),
+    .kill_f                 (kill_f),
+    .branch_predict_taken_d (branch_predict_taken_d),
+    .branch_predict_address_d (branch_predict_address_d),
+      
+             
+            
+
+
+    .exception_m            (exception_m),
+    .branch_taken_m         (branch_taken_m),
+    .branch_mispredict_taken_m (branch_mispredict_taken_m),
+    .branch_target_m        (branch_target_m),
+  
+                     
+
+
+  
+     
+      
+           
+
+        
+  
+    
+                    
+                    
+                    
+                    
+
+
+  
+
+    .jtag_read_enable       (jtag_read_enable),
+    .jtag_write_enable      (jtag_write_enable),
+    .jtag_write_data        (jtag_write_data),
+    .jtag_address           (jtag_address),
+ 
+
+    
+    
+    .pc_f                   (pc_f),
+    .pc_d                   (pc_d),
+    .pc_x                   (pc_x),
+    .pc_m                   (pc_m),
+    .pc_w                   (pc_w),
+  
+       
+     
+      
+           
+
+
+  
+    
+                    
+                    
+                    
+                    
+                    
+                     
+                    
+                   
+                    
+
+ 
+
+  
+
+    .iram_i_adr_o(iram_i_adr_o),
+    .iram_i_dat_i(iram_i_dat_i),
+    .iram_i_en_o(iram_i_en_o),
+ 
+
+		      	      
+  
+
+    .jtag_read_data         (jtag_read_data),
+    .jtag_access_complete   (jtag_access_complete),
+ 
+
+  
+
+    .bus_error_d            (bus_error_d),
+ 
+
+  
+
+    .instruction_f          (instruction_f),
+ 
+
+
+		      
+    .instruction_d          (instruction_d)
+
+
+		      
+    );
+
+
+lm32_decoder_wr_node decoder (
+    
+    .instruction            (instruction_d),
+    
+    .d_result_sel_0         (d_result_sel_0_d),
+    .d_result_sel_1         (d_result_sel_1_d),
+    .x_result_sel_csr       (x_result_sel_csr_d),
+  
+
+    .x_result_sel_mc_arith  (x_result_sel_mc_arith_d),
+ 
+
+      
+         
+
+
+  
+
+    .x_result_sel_sext      (x_result_sel_sext_d),
+ 
+    
+    .x_result_sel_logic     (x_result_sel_logic_d),
+  
+          
+
+
+    .x_result_sel_add       (x_result_sel_add_d),
+    .m_result_sel_compare   (m_result_sel_compare_d),
+  
+
+    .m_result_sel_shift     (m_result_sel_shift_d),  
+ 
+    
+    .w_result_sel_load      (w_result_sel_load_d),
+  
+
+    .w_result_sel_mul       (w_result_sel_mul_d),
+ 
+
+    .x_bypass_enable        (x_bypass_enable_d),
+    .m_bypass_enable        (m_bypass_enable_d),
+    .read_enable_0          (read_enable_0_d),
+    .read_idx_0             (read_idx_0_d),
+    .read_enable_1          (read_enable_1_d),
+    .read_idx_1             (read_idx_1_d),
+    .write_enable           (write_enable_d),
+    .write_idx              (write_idx_d),
+    .immediate              (immediate_d),
+    .branch_offset          (branch_offset_d),
+    .load                   (load_d),
+    .store                  (store_d),
+    .size                   (size_d),
+    .sign_extend            (sign_extend_d),
+    .adder_op               (adder_op_d),
+    .logic_op               (logic_op_d),
+  
+
+    .direction              (direction_d),
+ 
+
+  
+                 
+                
+
+
+  
+                   
+
+
+  
+
+    .divide                 (divide_d),
+    .modulus                (modulus_d),
+ 
+
+    .branch                 (branch_d),
+    .bi_unconditional       (bi_unconditional),
+    .bi_conditional         (bi_conditional),
+    .branch_reg             (branch_reg_d),
+    .condition              (condition_d),
+  
+
+    .break_opcode           (break_d),
+ 
+
+    .scall                  (scall_d),
+    .eret                   (eret_d),
+  
+
+    .bret                   (bret_d),
+ 
+
+  
+                
+
+
+    .csr_write_enable       (csr_write_enable_d)
+    ); 
+
+
+lm32_load_store_unit_wr_node #(
+    .associativity          (dcache_associativity),
+    .sets                   (dcache_sets),
+    .bytes_per_line         (dcache_bytes_per_line),
+    .base_address           (dcache_base_address),
+    .limit                  (dcache_limit)
+  ) load_store_unit (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    
+    .stall_a                (stall_a),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .kill_x                 (kill_x),
+    .kill_m                 (kill_m),
+    .exception_m            (exception_m),
+    .store_operand_x        (store_operand_x),
+    .load_store_address_x   (adder_result_x),
+    .load_store_address_m   (operand_m),
+    .load_store_address_w   (operand_w[1:0]),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_q_x               (load_q_x),
+    .store_q_x              (store_q_x),
+    .load_q_m               (load_q_m),
+    .store_q_m              (store_q_m),
+    .sign_extend_x          (sign_extend_x),
+    .size_x                 (size_x),
+  
+                     
+
+
+
+  
+
+    .iram_d_adr_o(iram_d_adr_o),
+    .iram_d_dat_o(iram_d_dat_o),
+    .iram_d_dat_i(iram_d_dat_i),
+    .iram_d_sel_o(iram_d_sel_o),
+    .iram_d_we_o(iram_d_we_o),
+    .iram_d_en_o(iram_d_en_o),
+    .iram_stall_request_x(iram_stall_request_x),
+ 
+
+		     
+    
+    .d_dat_i                (D_DAT_I),
+    .d_ack_i                (D_ACK_I),
+    .d_err_i                (D_ERR_I),
+    .d_rty_i                (D_RTY_I),
+    
+    
+  
+      
+     
+       
+           
+
+    
+    .load_data_w            (load_data_w),
+    .stall_wb_load          (stall_wb_load),
+    
+    .d_dat_o                (D_DAT_O),
+    .d_adr_o                (D_ADR_O),
+    .d_cyc_o                (D_CYC_O),
+    .d_sel_o                (D_SEL_O),
+    .d_stb_o                (D_STB_O),
+    .d_we_o                 (D_WE_O),
+    .d_cti_o                (D_CTI_O),
+    .d_lock_o               (D_LOCK_O),
+    .d_bte_o                (D_BTE_O)
+    );      
+       
+
+lm32_adder adder (
+    
+    .adder_op_x             (adder_op_x),
+    .adder_op_x_n           (adder_op_x_n),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .adder_result_x         (adder_result_x),
+    .adder_carry_n_x        (adder_carry_n_x),
+    .adder_overflow_x       (adder_overflow_x)
+    );
+
+
+lm32_logic_op logic_op (
+    
+    .logic_op_x             (logic_op_x),
+    .operand_0_x            (operand_0_x),
+
+    .operand_1_x            (operand_1_x),
+    
+    .logic_result_x         (logic_result_x)
+    );
+              
+  
+
+
+lm32_shifter shifter (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .direction_x            (direction_x),
+    .sign_extend_x          (sign_extend_x),
+    .operand_0_x            (operand_0_x),
+    .operand_1_x            (operand_1_x),
+    
+    .shifter_result_m       (shifter_result_m)
+    );
+ 
+
+
+  
+
+
+lm32_multiplier multiplier (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_x                (stall_x),
+    .stall_m                (stall_m),
+    .operand_0              (d_result_0),
+    .operand_1              (d_result_1),
+    
+    .result                 (multiplier_result_w)    
+    );
+ 
+
+
+  
+
+
+lm32_mc_arithmetic_wr_node mc_arithmetic (
+    
+    .clk_i                  (clk_i),
+    .rst_i                  (rst_i),
+    .stall_d                (stall_d),
+    .kill_x                 (kill_x),
+  
+                  
+    .divide_d               (divide_q_d),
+    .modulus_d              (modulus_q_d),
+ 
+
+          
+                 
+
+
+  
+               
+              
+              
+
+    
+    .operand_0_d            (d_result_0),
+    .operand_1_d            (d_result_1),
+    
+    .result_x               (mc_result_x),
+  
+                  
+    .divide_by_zero_x       (divide_by_zero_x),
+ 
+
+    .stall_request_x        (mc_stall_request_x)
+    );
+ 
+
+              
+  
+
+
+lm32_interrupt_wr_node interrupt_unit (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    
+    .interrupt              (interrupt),
+    
+    .stall_x                (stall_x),
+  
+
+    .non_debug_exception    (non_debug_exception_q_w), 
+    .debug_exception        (debug_exception_q_w),
+ 
+                   
+
+
+    .eret_q_x               (eret_q_x),
+  
+
+    .bret_q_x               (bret_q_x),
+ 
+
+    .csr                    (csr_x),
+    .csr_write_data         (operand_1_x),
+    .csr_write_enable       (csr_write_enable_q_x),
+    
+    .interrupt_exception    (interrupt_exception),
+    
+    .csr_read_data          (interrupt_csr_read_data_x)
+    );
+ 
+
+
+  
+
+   assign jtag_break = dbg_break_i;
+   assign reset_exception = dbg_reset_i;
+   assign dbg_exception_o = debug_exception_q_w || non_debug_exception_q_w;
+   
+ 
+
+
+
+  
+
+  
+    
+                      
+                      
+    
+                   
+                
+                 
+            
+    
+ 
+                        
+             
+           
+                    
+
+ 
+             
+       
+
+ 
+                
+    
+    
+    
+ 
+          
+          
+
+ 
+      
+        
+                   
+           
+          
+            
+               
+
+ 
+                 
+                 
+
+    
+                 
+            
+    
+
+
+
+  
+
+
+lm32_debug_wr_node #(
+    .breakpoints            (breakpoints),
+    .watchpoints            (watchpoints)
+  ) hw_debug (
+    
+    .clk_i                  (clk_i), 
+    .rst_i                  (rst_i),
+    .pc_x                   (pc_x),
+    .load_x                 (load_x),
+    .store_x                (store_x),
+    .load_store_address_x   (adder_result_x),
+    .csr_write_enable_x     (csr_write_enable_q_x),
+    .csr_write_data         (operand_1_x),
+    .csr_x                  (csr_x),
+   
+
+	        
+      
+        
+                   
+	      
+
+	        
+
+    .dbg_csr_write_enable_i  (dbg_csr_write_enable_i),
+    .dbg_csr_write_data_i    (dbg_csr_write_data_i),
+    .dbg_csr_addr_i               (dbg_csr_addr_i),
+	       
+
+ 
+
+  
+
+    .eret_q_x               (eret_q_x),
+    .bret_q_x               (bret_q_x),
+    .stall_x                (stall_x),
+    .exception_x            (exception_x),
+    .q_x                    (q_x),
+  
+      
+
+
+ 
+
+    
+  
+
+    .dc_ss                  (dc_ss),
+ 
+
+    .dc_re                  (dc_re),
+    .bp_match               (bp_match),
+    .wp_match               (wp_match)
+    );
+ 
+
+
+
+
+  
+
+   
+           
+            
+          
+            
+
+
+             
+              
+    
+
+   wire [31:0] regfile_data_0, regfile_data_1;
+   reg [31:0]  w_result_d;
+   reg 	       regfile_raw_0, regfile_raw_0_nxt;
+   reg 	       regfile_raw_1, regfile_raw_1_nxt;
+   
+   
+             
+          
+
+   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
+     begin
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[25:21]))
+	  regfile_raw_0_nxt = 1'b1;
+	else
+	  regfile_raw_0_nxt = 1'b0;
+	
+	if (reg_write_enable_q_w
+	    && (write_idx_w == instruction_f[20:16]))
+	  regfile_raw_1_nxt = 1'b1;
+	else
+	  regfile_raw_1_nxt = 1'b0;
+     end
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_0 or w_result_d or regfile_data_0)
+     if (regfile_raw_0)
+       reg_data_live_0 = w_result_d;
+     else
+       reg_data_live_0 = regfile_data_0;
+   
+   
+           
+           
+       
+
+   always @(regfile_raw_1 or w_result_d or regfile_data_1)
+     if (regfile_raw_1)
+       reg_data_live_1 = w_result_d;
+     else
+       reg_data_live_1 = regfile_data_1;
+   
+   
+     
+
+   always @(posedge clk_i  )
+     if (rst_i ==  1'b1)
+       begin
+	  regfile_raw_0 <= 1'b0;
+	  regfile_raw_1 <= 1'b0;
+	  w_result_d <= 32'b0;
+       end
+     else
+       begin
+	  regfile_raw_0 <= regfile_raw_0_nxt;
+	  regfile_raw_1 <= regfile_raw_1_nxt;
+	  w_result_d <= w_result;
+       end
+   
+   
+      
+
+   
+   lm32_dp_ram
+     #(
+       
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_0
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[25:21]),
+      
+      .rdata_o	(regfile_data_0)
+      );
+
+   lm32_dp_ram
+     #(
+       .addr_depth(1<<5),
+       .addr_width(5),
+       .data_width(32)
+       )
+   reg_1
+     (
+      
+      .clk_i	(clk_i),
+      .rst_i	(rst_i), 
+      .we_i	(reg_write_enable_q_w),
+      .wdata_i	(w_result),
+      .waddr_i	(write_idx_w),
+      .raddr_i	(instruction_f[20:16]),
+      
+      .rdata_o	(regfile_data_1)
+      );
+ 
+
+
+  
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+   
+   
+     
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+       
+   
+     
+      
+      
+      
+      
+      
+      
+      
+        
+      
+       
+      
+      
+      
+
+
+
+
+
+
+
+
+  
+
+
+assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
+assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
+ 
+
+  
+
+ 
+
+   
+   
+
+
+
+
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w ==  1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x ==  1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m ==  1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w ==  1'b1);
+
+
+always @(*)
+begin
+    if (   (   (x_bypass_enable_x ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_x_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_x_1 ==  1'b1))
+               )
+           )
+        || (   (m_bypass_enable_m ==  1'b0)
+            && (   ((read_enable_0_d ==  1'b1) && (raw_m_0 ==  1'b1))
+                || ((read_enable_1_d ==  1'b1) && (raw_m_1 ==  1'b1))
+               )
+           )
+       )
+        interlock =  1'b1;
+    else
+        interlock =  1'b0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_0 ==  1'b1)        
+        bypass_data_0 = x_result;
+    else if (raw_m_0 ==  1'b1)
+        bypass_data_0 = m_result;
+    else if (raw_w_0 ==  1'b1)
+        bypass_data_0 = w_result;
+    else
+        bypass_data_0 = reg_data_0;
+end
+
+
+always @(*)
+begin
+    if (raw_x_1 ==  1'b1)
+        bypass_data_1 = x_result;
+    else if (raw_m_1 ==  1'b1)
+        bypass_data_1 = m_result;
+    else if (raw_w_1 ==  1'b1)
+        bypass_data_1 = w_result;
+    else
+        bypass_data_1 = reg_data_1;
+end
+
+   
+          
+       
+       
+     
+
+   assign branch_predict_d = bi_unconditional | bi_conditional;
+   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
+   
+   
+   assign branch_target_d = pc_d + branch_offset_d;
+
+   
+   
+   
+   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
+
+
+always @(*)
+begin
+    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
+    case (d_result_sel_1_d)
+     2'b00:      d_result_1 = { 32{1'b0}};
+     2'b01:     d_result_1 = bypass_data_1;
+     2'b10: d_result_1 = immediate_d;
+    default:                        d_result_1 = { 32{1'bx}};
+    endcase
+end
+
+      
+
+   
+   
+
+
+
+  
+
+
+assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
+assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
+assign sext_result_x = size_x ==  2'b00 ? sextb_result_x : sexth_result_x;
+ 
+
+
+  
+
+      
+
+
+
+
+assign cmp_zero = operand_0_x == operand_1_x;
+assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_overflow = adder_overflow_x;
+assign cmp_carry_n = adder_carry_n_x;
+always @(*)
+begin
+    case (condition_x)
+     3'b000:   condition_met_x =  1'b1;
+     3'b110:   condition_met_x =  1'b1;
+     3'b001:    condition_met_x = cmp_zero;
+     3'b111:   condition_met_x = !cmp_zero;
+     3'b010:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+     3'b101:   condition_met_x = cmp_carry_n && !cmp_zero;
+     3'b011:   condition_met_x = cmp_negative == cmp_overflow;
+     3'b100:  condition_met_x = cmp_carry_n;
+    default:              condition_met_x = 1'bx;
+    endcase 
+end
+
+
+always @(*)
+begin
+    x_result =   x_result_sel_add_x ? adder_result_x 
+               : x_result_sel_csr_x ? csr_read_data_x
+  
+
+               : x_result_sel_sext_x ? sext_result_x
+ 
+
+  
+                  
+
+
+  
+                  
+
+
+  
+
+               : x_result_sel_mc_arith_x ? mc_result_x
+ 
+
+               : logic_result_x;
+end
+
+
+always @(*)
+begin
+    m_result =   m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
+  
+
+               : m_result_sel_shift_m ? shifter_result_m
+ 
+
+               : operand_m; 
+end
+
+
+always @(*)
+begin
+    w_result =    w_result_sel_load_w ? load_data_w
+  
+
+                : w_result_sel_mul_w ? multiplier_result_w
+ 
+
+                : operand_w;
+end
+
+      
+
+          
+                                
+                                     
+                                 
+                                 
+                              
+
+
+
+
+assign branch_taken_m =      (stall_m ==  1'b0) 
+                          && (   (   (branch_m ==  1'b1) 
+                                  && (valid_m ==  1'b1)
+                                  && (   (   (condition_met_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b0)
+					 )
+				      || (   (condition_met_m ==  1'b0)
+					  && (branch_predict_m ==  1'b1)
+					  && (branch_predict_taken_m ==  1'b1)
+					 )
+				     )
+                                 ) 
+                              || (exception_m ==  1'b1)
+                             );
+
+
+assign branch_mispredict_taken_m =    (condition_met_m ==  1'b0)
+                                   && (branch_predict_m ==  1'b1)
+	   			   && (branch_predict_taken_m ==  1'b1);
+   
+
+assign branch_flushX_m =    (stall_m ==  1'b0)
+                         && (   (   (branch_m ==  1'b1) 
+                                 && (valid_m ==  1'b1)
+			         && (   (condition_met_m ==  1'b1)
+				     || (   (condition_met_m ==  1'b0)
+					 && (branch_predict_m ==  1'b1)
+					 && (branch_predict_taken_m ==  1'b1)
+					)
+				    )
+			        )
+			     || (exception_m ==  1'b1)
+			    );
+
+
+assign kill_f =    (   (valid_d ==  1'b1)
+                    && (branch_predict_taken_d ==  1'b1)
+		   )
+                || (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+                    
+
+
+                  
+                   
+
+
+                ;
+assign kill_d =    (branch_taken_m ==  1'b1) 
+      
+                   
+
+
+  
+                        
+
+                
+                  
+                   
+
+
+                ;
+assign kill_x =    (branch_flushX_m ==  1'b1) 
+                  
+                   
+
+
+                ;
+assign kill_m =     1'b0
+                  
+                   
+
+
+                ;                
+assign kill_w =     1'b0
+                  
+                   
+
+                
+                ;
+
+
+
+  
+
+assign breakpoint_exception =    (   (   (break_x ==  1'b1)
+				      || (bp_match ==  1'b1)
+				     )
+				  && (valid_x ==  1'b1)
+				 )
+  
+                                 
+
+
+                              ;
+ 
+
+
+  
+
+assign watchpoint_exception = wp_match ==  1'b1;
+ 
+
+
+  
+
+assign instruction_bus_error_exception = (   (bus_error_x ==  1'b1)
+                                          && (valid_x ==  1'b1)
+                                         );
+assign data_bus_error_exception = data_bus_error_seen ==  1'b1;
+ 
+
+
+  
+
+assign divide_by_zero_exception = divide_by_zero_x ==  1'b1;
+ 
+
+
+assign system_call_exception = (   (scall_x ==  1'b1)
+  
+
+                                && (valid_x ==  1'b1)
+ 
+
+			       );
+
+  
+
+assign debug_exception_x =  (breakpoint_exception ==  1'b1)
+                         || (watchpoint_exception ==  1'b1)
+                         ;
+
+assign non_debug_exception_x = (system_call_exception ==  1'b1)
+  
+                               
+
+
+  
+
+                            || (instruction_bus_error_exception ==  1'b1)
+                            || (data_bus_error_exception ==  1'b1)
+ 
+
+  
+
+                            || (divide_by_zero_exception ==  1'b1)
+ 
+
+  
+
+                            || (   (interrupt_exception ==  1'b1)
+  
+
+                                && (dc_ss ==  1'b0)
+ 
+                            
+  
+
+ 				&& (store_q_m ==  1'b0)
+				&& (D_CYC_O ==  1'b0)
+ 
+
+                               )
+ 
+
+                            ;
+
+assign exception_x = (debug_exception_x ==  1'b1) || (non_debug_exception_x ==  1'b1);
+ 
+               
+ 
+                               
+                               
+
+ 
+                               
+
+ 
+                                  
+ 
+                                   
+                            
+ 
+ 				   
+				   
+
+                               
+
+                            
+
+
+
+  
+
+reg user_stall;
+
+always@(posedge clk_i)
+  if(rst_i)
+    user_stall <= 0;
+  else if(!D_CYC_O)
+    user_stall <= ~enable_i;
+ 
+
+
+
+always @(*)
+begin
+  
+
+  
+       
+          
+    
+
+     
+  
+
+         if (data_bus_error_exception ==  1'b1)
+        eid_x =  3'h4;
+    else
+ 
+
+         if (breakpoint_exception ==  1'b1)
+        eid_x =  3'd1;
+    else
+ 
+
+  
+
+         if (data_bus_error_exception ==  1'b1)
+        eid_x =  3'h4;
+    else
+         if (instruction_bus_error_exception ==  1'b1)
+        eid_x =  3'h2;
+    else
+ 
+
+  
+
+         if (watchpoint_exception ==  1'b1)
+        eid_x =  3'd3;
+    else 
+ 
+
+  
+
+         if (divide_by_zero_exception ==  1'b1)
+        eid_x =  3'h5;
+    else
+ 
+
+  
+
+         if (   (interrupt_exception ==  1'b1)
+  
+
+             && (dc_ss ==  1'b0)
+ 
+                            
+            )
+        eid_x =  3'h6;
+    else
+ 
+
+        eid_x =  3'h7;
+end
+
+
+
+assign stall_a = (stall_f ==  1'b1);
+                
+assign stall_f = (stall_d ==  1'b1);
+                
+assign stall_d =   (stall_x ==  1'b1) 
+                || (   (interlock ==  1'b1)
+                    && (kill_d ==  1'b0)
+                   ) 
+		|| (   (   (eret_d ==  1'b1)
+			|| (scall_d ==  1'b1)
+  
+
+			|| (bus_error_d ==  1'b1)
+ 
+
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+  
+
+		|| (   (   (break_d ==  1'b1)
+			|| (bret_d ==  1'b1)
+		       )
+		    && (   (load_q_x ==  1'b1)
+			|| (store_q_x ==  1'b1)
+			|| (load_q_m ==  1'b1)
+			|| (store_q_m ==  1'b1)
+			|| (D_CYC_O ==  1'b1)
+		       )
+                    && (kill_d ==  1'b0)
+		   )
+ 
+                   
+                || (   (csr_write_enable_d ==  1'b1)
+                    && (load_q_x ==  1'b1)
+                   )                      
+  
+
+                 
+                 
+                 || (   (iram_stall_request_x ==  1'b1)
+		     && (   (load_d ==  1'b1)
+			 
+			)
+		    )
+ 
+	
+                ;
+                
+assign stall_x =    (stall_m ==  1'b1)
+  
+
+                 || (   (mc_stall_request_x ==  1'b1)
+                     && (kill_x ==  1'b0)
+                    ) 
+ 
+
+
+	    
+                 ;
+
+assign stall_m =    (stall_wb_load ==  1'b1)
+  
+                    
+
+
+                 || (   (D_CYC_O ==  1'b1)
+                     && (   (store_m ==  1'b1)
+		         
+          
+          
+
+		  
+	 
+	
+
+          
+           
+          
+       
+
+  
+
+		         || ((store_x ==  1'b1) && (interrupt_exception ==  1'b1))
+ 
+
+                         || (load_m ==  1'b1)
+                         || (load_x ==  1'b1)
+                        ) 
+                    ) 
+ 
+                 
+  
+                         
+
+                                    
+  
+                         
+                             
+
+
+  
+                                
+
+
+ 
+                               
+  
+                                  
+                        
+                    
+
+
+  
+
+                 || (user_stall)
+    
+
+                 ;      
+
+
+
+
+  
+
+assign q_d = (valid_d ==  1'b1) && (kill_d ==  1'b0);
+ 
+
+  
+         
+         
+
+
+  
+         
+
+
+  
+
+assign divide_q_d = (divide_d ==  1'b1) && (q_d ==  1'b1);
+assign modulus_q_d = (modulus_d ==  1'b1) && (q_d ==  1'b1);
+ 
+
+assign q_x = (valid_x ==  1'b1) && (kill_x ==  1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x ==  1'b1) && (q_x ==  1'b1);
+assign eret_q_x = (eret_x ==  1'b1) && (q_x ==  1'b1);
+  
+
+assign bret_q_x = (bret_x ==  1'b1) && (q_x ==  1'b1);
+ 
+
+assign load_q_x = (load_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+
+               && (bp_match ==  1'b0)
+ 
+
+                  ;
+assign store_q_x = (store_x ==  1'b1) 
+               && (q_x ==  1'b1)
+  
+
+               && (bp_match ==  1'b0)
+ 
+
+                  ;
+  
+         
+
+                              
+assign q_m = (valid_m ==  1'b1) && (kill_m ==  1'b0) && (exception_m ==  1'b0);
+assign load_q_m = (load_m ==  1'b1) && (q_m ==  1'b1);
+assign store_q_m = (store_m ==  1'b1) && (q_m ==  1'b1);
+  
+
+assign debug_exception_q_w = ((debug_exception_w ==  1'b1) && (valid_w ==  1'b1));
+assign non_debug_exception_q_w = ((non_debug_exception_w ==  1'b1) && (valid_w ==  1'b1));        
+ 
+                 
+
+
+
+assign write_enable_q_x = (write_enable_x ==  1'b1) && (valid_x ==  1'b1) && (branch_flushX_m ==  1'b0);
+assign write_enable_q_m = (write_enable_m ==  1'b1) && (valid_m ==  1'b1);
+assign write_enable_q_w = (write_enable_w ==  1'b1) && (valid_w ==  1'b1);
+
+assign reg_write_enable_q_w = (write_enable_w ==  1'b1) && (kill_w ==  1'b0) && (valid_w ==  1'b1);
+
+
+assign cfg = {
+               6'h02,
+              watchpoints[3:0],
+              breakpoints[3:0],
+              interrupts[5:0],
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+              
+
+
+               1'b0,
+ 
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+
+               1'b1,
+ 
+              
+
+
+  
+ 
+               1'b1
+ 
+              
+
+
+              };
+
+assign cfg2 = {
+		     30'b0,
+  
+
+		      1'b1,
+ 
+		     
+
+
+  
+		     
+
+
+		      1'b0
+ 
+
+		     };
+   
+
+  
+         
+                    
+                    
+                    
+                    
+
+ 
+             
+                     
+		    
+
+		 
+
+ 
+  
+         
+                      
+
+ 
+               
+                       
+		      
+
+		   
+
+ 
+
+
+assign csr_d = read_idx_0_d[ (5-1):0];
+
+
+always @(*)
+begin
+    case (csr_x)
+  
+
+     5'h0,
+     5'h1,
+     5'h2:   csr_read_data_x = interrupt_csr_read_data_x;  
+ 
+
+  
+         
+
+
+     5'h6:  csr_read_data_x = cfg;
+     5'h7:  csr_read_data_x = {eba, 8'h00};
+  
+
+     5'h9: csr_read_data_x = {deba, 8'h00};
+ 
+
+  
+          
+        
+
+
+     5'ha: csr_read_data_x = cfg2;
+     5'hb:  csr_read_data_x = sdb_address;
+  
+
+     5'hc:  csr_read_data_x = data_bus_error_addr;
+ 
+
+      
+      
+    default:        csr_read_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        eba <= eba_reset[ (32-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  5'h7) && (stall_x ==  1'b0))
+            eba <= operand_1_x[ (32-2)+2-1:8];
+  
+
+   
+              
+           
+ 
+
+   
+
+       if ((dbg_csr_write_enable_i ==  1'b1) && (dbg_csr_addr_i ==  5'h7))
+         eba <= dbg_csr_write_data_i[ (32-2)+2-1:8];
+  
+	 
+ 
+
+    end
+end
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        deba <= deba_reset[ (32-2)+2-1:8];
+    else
+    begin
+        if ((csr_write_enable_q_x ==  1'b1) && (csr_x ==  5'h9) && (stall_x ==  1'b0))
+            deba <= operand_1_x[ (32-2)+2-1:8];
+   
+
+    
+              
+           
+  
+
+    
+
+       if ((dbg_csr_write_enable_i ==  1'b1) && (dbg_csr_addr_i ==  5'h9))
+         deba <= dbg_csr_write_data_i[ (32-2)+2-1:8];
+   
+       
+  
+
+    end
+end
+ 
+
+
+
+  
+   
+
+       
+          
+    
+            
+
+
+
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        data_bus_error_seen <=  1'b0;
+    else
+    begin
+        
+        if ((D_ERR_I ==  1'b1) && (D_CYC_O ==  1'b1)) begin
+           data_bus_error_seen <=  1'b1;
+	   data_bus_error_addr <= D_ADR_O;
+	end
+        
+        if ((exception_m ==  1'b1) && (kill_m ==  1'b0))
+            data_bus_error_seen <=  1'b0;
+    end
+end
+ 
+
+ 
+
+
+  
+ 
+ 
+
+           
+           
+       
+          
+            
+                 
+             
+          
+     
+            
+ 
+
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+
+  
+ 
+
+        
+          
+         
+          
+     
+          
+ 
+
+
+ 
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        valid_f <=  1'b0;
+        valid_d <=  1'b0;
+        valid_x <=  1'b0;
+        valid_m <=  1'b0;
+        valid_w <=  1'b0;
+    end
+    else
+    begin    
+        if ((kill_f ==  1'b1) || (stall_a ==  1'b0))
+  
+                  
+
+
+            valid_f <=  1'b1;
+ 
+            
+        else if (stall_f ==  1'b0)
+            valid_f <=  1'b0;            
+
+        if (kill_d ==  1'b1)
+            valid_d <=  1'b0;
+        else if (stall_f ==  1'b0)
+            valid_d <= valid_f & !kill_f;
+        else if (stall_d ==  1'b0)
+            valid_d <=  1'b0;
+       
+        if (stall_d ==  1'b0)
+            valid_x <= valid_d & !kill_d;
+        else if (kill_x ==  1'b1)
+            valid_x <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_x <=  1'b0;
+
+        if (kill_m ==  1'b1)
+            valid_m <=  1'b0;
+        else if (stall_x ==  1'b0)
+            valid_m <= valid_x & !kill_x;
+        else if (stall_m ==  1'b0)
+            valid_m <=  1'b0;
+
+        if (stall_m ==  1'b0)
+            valid_w <= valid_m & !kill_m;
+        else 
+            valid_w <=  1'b0;        
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+  
+                 
+
+        
+        operand_0_x <= { 32{1'b0}};
+        operand_1_x <= { 32{1'b0}};
+        store_operand_x <= { 32{1'b0}};
+        branch_target_x <= { (32-2){1'b0}};        
+        x_result_sel_csr_x <=  1'b0;
+  
+
+        x_result_sel_mc_arith_x <=  1'b0;
+ 
+
+      
+          
+
+
+  
+
+        x_result_sel_sext_x <=  1'b0;
+ 
+    
+  
+          
+
+
+        x_result_sel_add_x <=  1'b0;
+        m_result_sel_compare_x <=  1'b0;
+  
+
+        m_result_sel_shift_x <=  1'b0;
+ 
+    
+        w_result_sel_load_x <=  1'b0;
+  
+
+        w_result_sel_mul_x <=  1'b0;
+ 
+
+        x_bypass_enable_x <=  1'b0;
+        m_bypass_enable_x <=  1'b0;
+        write_enable_x <=  1'b0;
+        write_idx_x <= { 5{1'b0}};
+        csr_x <= { 5{1'b0}};
+        load_x <=  1'b0;
+        store_x <=  1'b0;
+        size_x <= { 2{1'b0}};
+        sign_extend_x <=  1'b0;
+        adder_op_x <=  1'b0;
+        adder_op_x_n <=  1'b0;
+        logic_op_x <= 4'h0;
+  
+
+        direction_x <=  1'b0;
+ 
+
+  
+          
+
+
+
+        branch_x <=  1'b0;
+        branch_predict_x <=  1'b0;
+        branch_predict_taken_x <=  1'b0;
+        condition_x <=  3'b000;
+  
+
+        break_x <=  1'b0;
+ 
+
+        scall_x <=  1'b0;
+        eret_x <=  1'b0;
+  
+
+        bret_x <=  1'b0;
+ 
+
+  
+
+        bus_error_x <=  1'b0;
+        data_bus_error_exception_m <=  1'b0;
+ 
+
+        csr_write_enable_x <=  1'b0;
+        operand_m <= { 32{1'b0}};
+        branch_target_m <= { (32-2){1'b0}};
+        m_result_sel_compare_m <=  1'b0;
+  
+
+        m_result_sel_shift_m <=  1'b0;
+ 
+    
+        w_result_sel_load_m <=  1'b0;
+  
+
+        w_result_sel_mul_m <=  1'b0;
+ 
+
+        m_bypass_enable_m <=  1'b0;
+        branch_m <=  1'b0;
+        branch_predict_m <=  1'b0;
+	branch_predict_taken_m <=  1'b0;
+        exception_m <=  1'b0;
+        load_m <=  1'b0;
+        store_m <=  1'b0;
+        write_enable_m <=  1'b0;            
+        write_idx_m <= { 5{1'b0}};
+        condition_met_m <=  1'b0;
+  
+          
+
+
+  
+
+        debug_exception_m <=  1'b0;
+        non_debug_exception_m <=  1'b0;        
+ 
+
+        operand_w <= { 32{1'b0}};        
+        w_result_sel_load_w <=  1'b0;
+  
+
+        w_result_sel_mul_w <=  1'b0;
+ 
+
+        write_idx_w <= { 5{1'b0}};        
+        write_enable_w <=  1'b0;
+  
+
+        debug_exception_w <=  1'b0;
+        non_debug_exception_w <=  1'b0;        
+ 
+          
+
+
+  
+
+        memop_pc_w <= { (32-2){1'b0}};
+ 
+
+    end
+    else
+    begin
+        
+       
+        if (stall_x ==  1'b0)
+        begin
+  
+                     
+
+        
+            operand_0_x <= d_result_0;
+            operand_1_x <= d_result_1;
+            store_operand_x <= bypass_data_1;
+            branch_target_x <= branch_reg_d ==  1'b1 ? bypass_data_0[ ((32-2)+2-1):2] : branch_target_d;            
+            x_result_sel_csr_x <= x_result_sel_csr_d;
+  
+
+            x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
+ 
+
+      
+              
+
+
+  
+
+            x_result_sel_sext_x <= x_result_sel_sext_d;
+ 
+    
+  
+              
+
+
+            x_result_sel_add_x <= x_result_sel_add_d;
+            m_result_sel_compare_x <= m_result_sel_compare_d;
+  
+
+            m_result_sel_shift_x <= m_result_sel_shift_d;
+ 
+    
+            w_result_sel_load_x <= w_result_sel_load_d;
+  
+
+            w_result_sel_mul_x <= w_result_sel_mul_d;
+ 
+
+            x_bypass_enable_x <= x_bypass_enable_d;
+            m_bypass_enable_x <= m_bypass_enable_d;
+            load_x <= load_d;
+            store_x <= store_d;
+            branch_x <= branch_d;
+	    branch_predict_x <= branch_predict_d;
+	    branch_predict_taken_x <= branch_predict_taken_d;
+	    write_idx_x <= write_idx_d;
+            csr_x <= csr_d;
+            size_x <= size_d;
+            sign_extend_x <= sign_extend_d;
+            adder_op_x <= adder_op_d;
+            adder_op_x_n <= ~adder_op_d;
+            logic_op_x <= logic_op_d;
+  
+
+            direction_x <= direction_d;
+ 
+
+  
+              
+
+
+            condition_x <= condition_d;
+            csr_write_enable_x <= csr_write_enable_d;
+  
+
+            break_x <= break_d;
+ 
+
+            scall_x <= scall_d;
+  
+
+            bus_error_x <= bus_error_d;
+ 
+
+            eret_x <= eret_d;
+  
+
+            bret_x <= bret_d; 
+ 
+
+            write_enable_x <= write_enable_d;
+        end
+        
+        
+
+        if (stall_m ==  1'b0)
+        begin
+            operand_m <= x_result;
+            m_result_sel_compare_m <= m_result_sel_compare_x;
+  
+
+            m_result_sel_shift_m <= m_result_sel_shift_x;
+ 
+    
+            if (exception_x ==  1'b1)
+            begin
+                w_result_sel_load_m <=  1'b0;
+  
+
+                w_result_sel_mul_m <=  1'b0;
+ 
+
+            end
+            else
+            begin
+                w_result_sel_load_m <= w_result_sel_load_x;
+  
+
+                w_result_sel_mul_m <= w_result_sel_mul_x;
+ 
+
+            end
+            m_bypass_enable_m <= m_bypass_enable_x;
+            load_m <= load_x;
+            store_m <= store_x;
+      
+                
+
+
+            branch_m <= branch_x;
+	    branch_predict_m <= branch_predict_x;
+	    branch_predict_taken_m <= branch_predict_taken_x;
+ 
+
+  
+
+	   
+	   
+	   
+	   
+	   
+            if (non_debug_exception_x ==  1'b1) 
+                write_idx_m <=  5'd30;
+            else if (debug_exception_x ==  1'b1)
+                write_idx_m <=  5'd31;
+            else 
+                write_idx_m <= write_idx_x;
+ 
+               
+                  
+             
+                  
+
+
+            condition_met_m <= condition_met_x;
+  
+
+	   if (exception_x ==  1'b1)
+	     if ((dc_re ==  1'b1)
+		 || ((debug_exception_x ==  1'b1) 
+		     && (non_debug_exception_x ==  1'b0)))
+	       branch_target_m <= {deba, eid_x, {3{1'b0}}};
+	     else
+	       branch_target_m <= {eba, eid_x, {3{1'b0}}};
+	   else
+	     branch_target_m <= branch_target_x;
+ 
+                      
+
+
+  
+              
+              
+
+
+  
+              
+
+
+  
+ 
+               
+
+
+
+            write_enable_m <= exception_x ==  1'b1 ?  1'b1 : write_enable_x;            
+  
+
+            debug_exception_m <= debug_exception_x;
+            non_debug_exception_m <= non_debug_exception_x;        
+ 
+
+        end
+        
+        
+        if (stall_m ==  1'b0)
+        begin
+            if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+                exception_m <=  1'b1;
+            else 
+                exception_m <=  1'b0;
+  
+
+	   data_bus_error_exception_m <=    (data_bus_error_exception ==  1'b1) 
+  
+
+					 && (reset_exception ==  1'b0)
+ 
+
+					 ;
+ 
+
+	end
+                
+        
+  
+
+        operand_w <= exception_m ==  1'b1 ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
+ 
+                 
+
+
+        w_result_sel_load_w <= w_result_sel_load_m;
+  
+
+        w_result_sel_mul_w <= w_result_sel_mul_m;
+ 
+
+        write_idx_w <= write_idx_m;
+  
+          
+          
+ 
+           
+
+
+
+        write_enable_w <= write_enable_m;
+  
+
+        debug_exception_w <= debug_exception_m;
+        non_debug_exception_w <= non_debug_exception_m;
+ 
+          
+
+
+  
+
+        if (   (stall_m ==  1'b0)
+            && (   (load_q_m ==  1'b1) 
+                || (store_q_m ==  1'b1)
+               )
+	   )
+          memop_pc_w <= pc_m;
+ 
+
+    end
+end
+
+  
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        use_buf <=  1'b0;
+        reg_data_buf_0 <= { 32{1'b0}};
+        reg_data_buf_1 <= { 32{1'b0}};
+    end
+    else
+    begin
+        if (stall_d ==  1'b0)
+            use_buf <=  1'b0;
+        else if (use_buf ==  1'b0)
+        begin        
+            reg_data_buf_0 <= reg_data_live_0;
+            reg_data_buf_1 <= reg_data_live_1;
+            use_buf <=  1'b1;
+        end        
+        if (reg_write_enable_q_w ==  1'b1)
+        begin
+            if (write_idx_w == read_idx_0_d)
+                reg_data_buf_0 <= w_result;
+            if (write_idx_w == read_idx_1_d)
+                reg_data_buf_1 <= w_result;
+        end
+    end
+end
+ 
+
+
+  
+
+ 
+
+   
+
+        
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+     
+           
+            
+        
+
+
+
+
+  
+
+   
+
+       
+    
+          
+          
+          
+          
+          
+ 
+          
+
+          
+    
+    
+    
+          
+        
+ 
+               
+
+           
+
+                
+              
+              
+              
+              
+        
+        
+              
+        
+             
+        
+            
+                 
+            
+                
+                  
+                  
+            
+            
+              
+            
+              
+ 
+              
+
+        
+        
+        
+              
+ 
+              
+
+        
+    
+
+
+
+      
+
+
+
+
+
+        
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_load_store_unit_wr_node 
+(
+    
+    clk_i,
+    rst_i,
+ 
+    stall_a,
+    stall_x,
+    stall_m,
+    kill_x,
+    kill_m,
+    exception_m,
+    store_operand_x,
+    load_store_address_x,
+    load_store_address_m,
+    load_store_address_w,
+    load_x,
+    store_x,
+    load_q_x,
+    store_q_x,
+    load_q_m,
+    store_q_m,
+    sign_extend_x,
+    size_x,
+  
+    
+
+
+    
+    d_dat_i,
+    d_ack_i,
+    d_err_i,
+    d_rty_i,
+    
+    
+  
+    
+    
+    
+    
+
+    
+  
+
+    iram_d_adr_o,
+    iram_d_dat_o,
+    iram_d_dat_i,
+    iram_d_sel_o,
+    iram_d_we_o,
+    iram_d_en_o,
+    iram_stall_request_x,
+ 
+			     
+    load_data_w,
+    stall_wb_load,
+    
+    d_dat_o,
+    d_adr_o,
+    d_cyc_o,
+    d_sel_o,
+    d_stb_o,
+    d_we_o,
+    d_cti_o,
+    d_lock_o,
+    d_bte_o
+    );
+
+
+
+
+
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+
+   input clk_i;                                            
+   
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_x;                                          
+input stall_m;                                          
+input kill_x;                                           
+input kill_m;                                           
+input exception_m;                                      
+
+input [ (32-1):0] store_operand_x;                 
+input [ (32-1):0] load_store_address_x;            
+input [ (32-1):0] load_store_address_m;            
+input [1:0] load_store_address_w;                       
+input load_x;                                           
+input store_x;                                          
+input load_q_x;                                         
+input store_q_x;                                        
+input load_q_m;                                         
+input store_q_m;                                        
+input sign_extend_x;                                    
+input [ 1:0] size_x;                          
+
+  
+                                            
+
+
+
+  
+   
+   output [31:0] iram_d_adr_o;
+   output [31:0] iram_d_dat_o;
+   input [31:0]  iram_d_dat_i;
+   output [3:0]  iram_d_sel_o;
+   output        iram_d_en_o, iram_d_we_o;
+   output 	 iram_stall_request_x;
+   
+ 
+
+
+   reg 		 [31:0] iram_dat_d0;
+   reg 		 iram_en_d0;
+   wire 	 iram_en;
+   wire [31:0] 	 iram_data;
+   
+   
+   
+input [ (32-1):0] d_dat_i;                         
+input d_ack_i;                                          
+input d_err_i;                                          
+input d_rty_i;                                          
+
+
+
+
+
+  
+                            
+   
+                           
+   
+                             
+   
+ 
+   
+
+
+
+   
+output [ (32-1):0] load_data_w;                    
+reg    [ (32-1):0] load_data_w;
+output stall_wb_load;                                   
+reg    stall_wb_load;
+
+output [ (32-1):0] d_dat_o;                        
+reg    [ (32-1):0] d_dat_o;
+output [ (32-1):0] d_adr_o;                        
+reg    [ (32-1):0] d_adr_o;
+output d_cyc_o;                                         
+reg    d_cyc_o;
+output [ (4-1):0] d_sel_o;                 
+reg    [ (4-1):0] d_sel_o;
+output d_stb_o;                                         
+reg    d_stb_o; 
+output d_we_o;                                          
+reg    d_we_o;
+output [ (3-1):0] d_cti_o;                       
+reg    [ (3-1):0] d_cti_o;
+output d_lock_o;                                        
+reg    d_lock_o;
+output [ (2-1):0] d_bte_o;                       
+wire   [ (2-1):0] d_bte_o;
+
+
+
+
+
+
+reg [ 1:0] size_m;
+reg [ 1:0] size_w;
+reg sign_extend_m;
+reg sign_extend_w;
+reg [ (32-1):0] store_data_x;       
+reg [ (32-1):0] store_data_m;       
+reg [ (4-1):0] byte_enable_x;
+reg [ (4-1):0] byte_enable_m;
+wire [ (32-1):0] data_m;
+reg [ (32-1):0] data_w;
+
+   
+
+  
+                                    
+ 
+                      
+              
+                                 
+                  
+                   
+                                          
+                      
+
+
+  
+                                      
+ 
+                                      
+                    
+                      
+                        
+                  
+
+
+wire wb_select_x;                                       
+  
+
+wire iram_select_x;                                     
+
+reg  iram_enable_m;
+   reg iram_select_m;
+   reg iram_d_en_d0;
+   
+
+ 
+
+reg wb_select_m;
+reg [ (32-1):0] wb_data_m;                         
+reg wb_load_complete;                                   
+   
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+ 
+              
+                       
+             
+               
+                      
+       
+    
+                      
+                            
+                    
+                    
+                    
+                  
+                  
+                     
+                    
+                 
+            
+               
+                
+                     
+    
+              
+            
+             
+             
+                  
+                  
+    
+
+
+
+
+
+
+
+
+  
+            
+                             
+
+
+
+  
+
+   assign iram_select_x =    (load_store_address_x >=  0) 
+                          && (load_store_address_x <=  32'h000fffff);
+
+   assign iram_d_sel_o = byte_enable_m;
+   assign iram_en = !stall_x || !stall_m;
+
+   always@(posedge clk_i)
+     iram_en_d0 <= iram_en;
+
+  
+
+ 
+
+  
+
+  
+
+
+       
+   
+   
+   
+ 
+
+   
+  
+            
+                               
+ 
+                               
+
+ 
+                               
+
+                     
+
+
+	  
+   assign wb_select_x =     1'b1
+  
+                          
+
+
+  
+                         
+
+
+  
+
+                        && !iram_select_x
+ 
+
+                     ;
+
+
+always @(*)
+begin
+    case (size_x)
+     2'b00:  store_data_x = {4{store_operand_x[7:0]}};
+     2'b11: store_data_x = {2{store_operand_x[15:0]}};
+     2'b10:  store_data_x = store_operand_x;    
+    default:          store_data_x = { 32{1'bx}};
+    endcase
+end
+
+
+always @(*)
+begin
+    casez ({size_x, load_store_address_x[1:0]})
+    { 2'b00, 2'b11}:  byte_enable_x = 4'b0001;
+    { 2'b00, 2'b10}:  byte_enable_x = 4'b0010;
+    { 2'b00, 2'b01}:  byte_enable_x = 4'b0100;
+    { 2'b00, 2'b00}:  byte_enable_x = 4'b1000;
+    { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+    { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+    { 2'b10, 2'b??}:  byte_enable_x = 4'b1111;
+    default:                   byte_enable_x = 4'bxxxx;
+    endcase
+end
+
+  
+
+   assign iram_d_dat_o = store_data_m;
+   assign iram_d_adr_o = (iram_enable_m && store_q_m) ? load_store_address_m : load_store_address_x;
+
+   assign iram_stall_request_x =    (iram_select_x ==  1'b1)
+	                         && (store_q_x ==  1'b1);
+   
+   
+   assign iram_d_we_o =    (iram_enable_m ==  1'b1) && (store_q_m ==  1'b1);
+   assign iram_d_en_o = !stall_m || !stall_x;
+ 
+
+   
+  
+  
+   
+   
+         
+                    
+                       
+                      
+                        
+                     
+                        
+  
+   
+         
+                    
+                       
+                      
+                      
+  
+ 
+   
+   
+         
+                    
+                       
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+
+   
+   
+   
+         
+                     
+                      
+                      
+                      
+  
+   
+         
+                     
+                    
+  
+ 
+
+    
+
+   
+   assign data_m = wb_select_m ==  1'b1 
+                   ? wb_data_m 
+                   : iram_d_dat_i;
+
+   
+   
+      
+  
+
+  
+
+ 
+
+
+
+always @(*)
+begin
+    casez ({size_w, load_store_address_w[1:0]})
+    { 2'b00, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+    { 2'b00, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+    { 2'b00, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+    { 2'b00, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+    { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+    { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+    { 2'b10, 2'b??}:  load_data_w = data_w;
+    default:                   load_data_w = { 32{1'bx}};
+    endcase
+end
+
+
+assign d_bte_o =  2'b00;
+
+                  
+
+ 
+     
+    
+    
+   
+   
+   
+    
+    
+    
+    
+   
+   
+     
+     
+    
+    
+    
+   
+         
+     
+     
+    
+    
+
+
+
+
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        d_cyc_o <=  1'b0;
+        d_stb_o <=  1'b0;
+        d_dat_o <= { 32{1'b0}};
+        d_adr_o <= { 32{1'b0}};
+        d_sel_o <= { 4{ 1'b0}};
+        d_we_o <=  1'b0;
+        d_cti_o <=  3'b111;
+        d_lock_o <=  1'b0;
+        wb_data_m <= { 32{1'b0}};
+        wb_load_complete <=  1'b0;
+        stall_wb_load <=  1'b0;
+                  
+          
+
+                
+    end
+    else 
+    begin
+   
+        
+          
+
+                
+        
+        if (d_cyc_o ==  1'b1)
+        begin
+            
+            if ((d_ack_i ==  1'b1) || (d_err_i ==  1'b1))
+            begin
+                  
+                     
+                
+                    
+                        
+                
+                
+
+                
+                begin
+                    
+                    d_cyc_o <=  1'b0;
+                    d_stb_o <=  1'b0;
+                    d_lock_o <=  1'b0;
+                end
+      
+                  
+                
+                  
+
+
+                
+                wb_data_m <= d_dat_i;
+                
+                wb_load_complete <= !d_we_o;
+            end
+            
+        end
+        else 
+        begin
+                  
+               
+            
+                
+                  
+                  
+                  
+                                  
+                  
+                  
+                
+            
+             
+
+            
+                 if (   (store_q_m ==  1'b1)
+                     && (stall_m ==  1'b0)
+  
+                        
+
+
+  
+
+		     && (iram_enable_m ==  1'b0)
+ 
+			
+                    )
+            begin
+                
+                d_dat_o <= store_data_m;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b1;
+                d_cti_o <=  3'b111;
+            end        
+            else if (   (load_q_m ==  1'b1) 
+                     && (wb_select_m ==  1'b1) 
+                     && (wb_load_complete ==  1'b0)
+                     
+                    )
+            begin
+                
+                stall_wb_load <=  1'b0;
+                d_adr_o <= load_store_address_m;
+                d_cyc_o <=  1'b1;
+                d_sel_o <= byte_enable_m;
+                d_stb_o <=  1'b1;
+                d_we_o <=  1'b0;
+                d_cti_o <=  3'b111;
+            end
+        end
+        
+        if (stall_m ==  1'b0)
+            wb_load_complete <=  1'b0;
+        
+        if ((load_q_x ==  1'b1) && (wb_select_x ==  1'b1) && (stall_x ==  1'b0))
+            stall_wb_load <=  1'b1;
+        
+        if ((kill_m ==  1'b1) || (exception_m ==  1'b1))
+            stall_wb_load <=  1'b0;
+    end
+end
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        sign_extend_m <=  1'b0;
+        size_m <= 2'b00;
+        byte_enable_m <=  1'b0;
+        store_data_m <= { 32{1'b0}};
+  
+          
+
+
+  
+          
+
+
+  
+
+        iram_enable_m <=  1'b0;
+			  iram_select_m <=  1'b0;
+ 
+
+        wb_select_m <=  1'b0;        
+    end
+    else
+    begin
+        if (stall_m ==  1'b0)
+        begin
+            sign_extend_m <= sign_extend_x;
+            size_m <= size_x;
+            byte_enable_m <= byte_enable_x;    
+            store_data_m <= store_data_x;
+  
+              
+
+
+  
+              
+
+
+  
+
+            iram_enable_m <= iram_select_x;
+			  iram_select_m <= iram_select_x;
+ 
+
+            wb_select_m <= wb_select_x;
+        end
+    end
+end
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        size_w <= 2'b00;
+        data_w <= { 32{1'b0}};
+        sign_extend_w <=  1'b0;
+    end
+    else
+    begin
+        size_w <= size_m;
+
+  
+
+       if(!iram_select_m || iram_en_d0)
+ 
+
+        data_w <= data_m;
+
+        sign_extend_w <= sign_extend_m;
+    end
+end
+
+
+
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+                  
+                    
+                 
+                   
+           
+             
+
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+                   
+               
+                 
+
+
+                      
+                      
+                      
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+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
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+                      
+
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+           
+             
+
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+                
+           
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+              
+               
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+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
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+                  
+                    
+                   
+                  
+                   
+          
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+ 
+                   
+                     
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+                   
+                     
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+                    
+                     
+
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+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
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+                     
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+                     
+ 
+
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+                   
+              
+                  
+                 
+            
+
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+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
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+           
+         
+       
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+           
+          
+         
+     
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+            
+              
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+             
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+                  
+                    
+                 
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+                 
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+               
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+          
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+                
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+  
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+  
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+  
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+  
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+  
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+
+  
+
+  
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+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_decoder_wr_node (
+    
+    instruction,
+    
+    d_result_sel_0,
+    d_result_sel_1,        
+    x_result_sel_csr,
+  
+
+    x_result_sel_mc_arith,
+ 
+    
+      
+    
+
+
+  
+
+    x_result_sel_sext,
+ 
+    
+    x_result_sel_logic,
+  
+    
+
+
+    x_result_sel_add,
+    m_result_sel_compare,
+  
+
+    m_result_sel_shift,  
+ 
+    
+    w_result_sel_load,
+  
+
+    w_result_sel_mul,
+ 
+
+    x_bypass_enable,
+    m_bypass_enable,
+    read_enable_0,
+    read_idx_0,
+    read_enable_1,
+    read_idx_1,
+    write_enable,
+    write_idx,
+    immediate,
+    branch_offset,
+    load,
+    store,
+    size,
+    sign_extend,
+    adder_op,
+    logic_op,
+  
+
+    direction,
+ 
+
+  
+    
+    
+
+
+  
+    
+
+
+  
+
+    divide,
+    modulus,
+ 
+
+    branch,
+    branch_reg,
+    condition,
+    bi_conditional,
+    bi_unconditional,
+  
+
+    break_opcode,
+ 
+
+    scall,
+    eret,
+  
+
+    bret,
+ 
+
+  
+    
+
+
+    csr_write_enable
+    );
+
+
+
+
+
+input [ (32-1):0] instruction;       
+
+
+
+
+
+output [ 0:0] d_result_sel_0;
+reg    [ 0:0] d_result_sel_0;
+output [ 1:0] d_result_sel_1;
+reg    [ 1:0] d_result_sel_1;
+output x_result_sel_csr;
+reg    x_result_sel_csr;
+  
+
+output x_result_sel_mc_arith;
+reg    x_result_sel_mc_arith;
+ 
+
+      
+ 
+    
+
+
+  
+
+output x_result_sel_sext;
+reg    x_result_sel_sext;
+ 
+
+output x_result_sel_logic;
+reg    x_result_sel_logic;
+  
+ 
+    
+
+
+output x_result_sel_add;
+reg    x_result_sel_add;
+output m_result_sel_compare;
+reg    m_result_sel_compare;
+  
+
+output m_result_sel_shift;
+reg    m_result_sel_shift;
+ 
+
+output w_result_sel_load;
+reg    w_result_sel_load;
+  
+
+output w_result_sel_mul;
+reg    w_result_sel_mul;
+ 
+
+output x_bypass_enable;
+wire   x_bypass_enable;
+output m_bypass_enable;
+wire   m_bypass_enable;
+output read_enable_0;
+wire   read_enable_0;
+output [ (5-1):0] read_idx_0;
+wire   [ (5-1):0] read_idx_0;
+output read_enable_1;
+wire   read_enable_1;
+output [ (5-1):0] read_idx_1;
+wire   [ (5-1):0] read_idx_1;
+output write_enable;
+wire   write_enable;
+output [ (5-1):0] write_idx;
+wire   [ (5-1):0] write_idx;
+output [ (32-1):0] immediate;
+wire   [ (32-1):0] immediate;
+output [ ((32-2)+2-1):2] branch_offset;
+wire   [ ((32-2)+2-1):2] branch_offset;
+output load;
+wire   load;
+output store;
+wire   store;
+output [ 1:0] size;
+wire   [ 1:0] size;
+output sign_extend;
+wire   sign_extend;
+output adder_op;
+wire   adder_op;
+output [ 3:0] logic_op;
+wire   [ 3:0] logic_op;
+  
+
+output direction;
+wire   direction;
+ 
+
+  
+ 
+   
+ 
+   
+
+
+  
+ 
+   
+
+
+  
+
+output divide;
+wire   divide;
+output modulus;
+wire   modulus;
+ 
+
+output branch;
+wire   branch;
+output branch_reg;
+wire   branch_reg;
+output [ (3-1):0] condition;
+wire   [ (3-1):0] condition;
+output bi_conditional;
+wire bi_conditional;
+output bi_unconditional;
+wire bi_unconditional;
+  
+
+output break_opcode;
+wire   break_opcode;
+ 
+
+output scall;
+wire   scall;
+output eret;
+wire   eret;
+  
+
+output bret;
+wire   bret;
+ 
+
+  
+  
+    
+
+
+output csr_write_enable;
+wire   csr_write_enable;
+
+
+
+
+
+wire [ (32-1):0] extended_immediate;       
+wire [ (32-1):0] high_immediate;           
+wire [ (32-1):0] call_immediate;           
+wire [ (32-1):0] branch_immediate;         
+wire sign_extend_immediate;                     
+wire select_high_immediate;                     
+wire select_call_immediate;                     
+
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+  
+
+wire op_divu;
+ 
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+  
+
+wire op_modu;
+ 
+
+  
+
+wire op_mul;
+ 
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+  
+
+wire op_sextb;
+wire op_sexth;
+ 
+
+wire op_sh;
+  
+
+wire op_sl;
+ 
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+  
+ 
+
+
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+  
+
+wire shift;
+ 
+
+  
+ 
+
+
+  
+
+wire sext;
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+assign op_add    = instruction[ 30:26] ==  5'b01101;
+assign op_and    = instruction[ 30:26] ==  5'b01000;
+assign op_andhi  = instruction[ 31:26] ==  6'b011000;
+assign op_b      = instruction[ 31:26] ==  6'b110000;
+assign op_bi     = instruction[ 31:26] ==  6'b111000;
+assign op_be     = instruction[ 31:26] ==  6'b010001;
+assign op_bg     = instruction[ 31:26] ==  6'b010010;
+assign op_bge    = instruction[ 31:26] ==  6'b010011;
+assign op_bgeu   = instruction[ 31:26] ==  6'b010100;
+assign op_bgu    = instruction[ 31:26] ==  6'b010101;
+assign op_bne    = instruction[ 31:26] ==  6'b010111;
+assign op_call   = instruction[ 31:26] ==  6'b110110;
+assign op_calli  = instruction[ 31:26] ==  6'b111110;
+assign op_cmpe   = instruction[ 30:26] ==  5'b11001;
+assign op_cmpg   = instruction[ 30:26] ==  5'b11010;
+assign op_cmpge  = instruction[ 30:26] ==  5'b11011;
+assign op_cmpgeu = instruction[ 30:26] ==  5'b11100;
+assign op_cmpgu  = instruction[ 30:26] ==  5'b11101;
+assign op_cmpne  = instruction[ 30:26] ==  5'b11111;
+  
+
+assign op_divu   = instruction[ 31:26] ==  6'b100011;
+ 
+
+assign op_lb     = instruction[ 31:26] ==  6'b000100;
+assign op_lbu    = instruction[ 31:26] ==  6'b010000;
+assign op_lh     = instruction[ 31:26] ==  6'b000111;
+assign op_lhu    = instruction[ 31:26] ==  6'b001011;
+assign op_lw     = instruction[ 31:26] ==  6'b001010;
+  
+
+assign op_modu   = instruction[ 31:26] ==  6'b110001;
+ 
+
+  
+
+assign op_mul    = instruction[ 30:26] ==  5'b00010;
+ 
+
+assign op_nor    = instruction[ 30:26] ==  5'b00001;
+assign op_or     = instruction[ 30:26] ==  5'b01110;
+assign op_orhi   = instruction[ 31:26] ==  6'b011110;
+assign op_raise  = instruction[ 31:26] ==  6'b101011;
+assign op_rcsr   = instruction[ 31:26] ==  6'b100100;
+assign op_sb     = instruction[ 31:26] ==  6'b001100;
+  
+
+assign op_sextb  = instruction[ 31:26] ==  6'b101100;
+assign op_sexth  = instruction[ 31:26] ==  6'b110111;
+ 
+
+assign op_sh     = instruction[ 31:26] ==  6'b000011;
+  
+
+assign op_sl     = instruction[ 30:26] ==  5'b01111;      
+ 
+
+assign op_sr     = instruction[ 30:26] ==  5'b00101;
+assign op_sru    = instruction[ 30:26] ==  5'b00000;
+assign op_sub    = instruction[ 31:26] ==  6'b110010;
+assign op_sw     = instruction[ 31:26] ==  6'b010110;
+  
+       
+
+
+assign op_wcsr   = instruction[ 31:26] ==  6'b110100;
+assign op_xnor   = instruction[ 30:26] ==  5'b01001;
+assign op_xor    = instruction[ 30:26] ==  5'b00110;
+
+
+assign arith = op_add | op_sub;
+assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
+assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
+assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
+assign bi_unconditional = op_bi;
+assign bra = op_b | bi_unconditional | bi_conditional;
+assign call = op_call | op_calli;
+  
+
+assign shift = op_sl | op_sr | op_sru;
+ 
+
+  
+     
+
+
+  
+   
+     
+
+
+  
+
+assign sext = op_sextb | op_sexth;
+ 
+
+  
+   
+
+
+  
+
+assign divide = op_divu; 
+assign modulus = op_modu;
+ 
+
+assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
+assign store = op_sb | op_sh | op_sw;
+
+
+always @(*)
+begin
+    
+    if (call) 
+        d_result_sel_0 =  1'b1;
+    else 
+        d_result_sel_0 =  1'b0;
+    if (call) 
+        d_result_sel_1 =  2'b00;         
+    else if ((instruction[31] == 1'b0) && !bra) 
+        d_result_sel_1 =  2'b10;
+    else
+        d_result_sel_1 =  2'b01; 
+    
+    x_result_sel_csr =  1'b0;
+  
+
+    x_result_sel_mc_arith =  1'b0;
+ 
+
+  
+      
+
+
+  
+
+    x_result_sel_sext =  1'b0;
+ 
+
+    x_result_sel_logic =  1'b0;
+          
+      
+
+
+    x_result_sel_add =  1'b0;
+    if (op_rcsr)
+        x_result_sel_csr =  1'b1;
+  
+    
+  
+         
+          
+
+
+  
+
+    else if (divide | modulus)
+        x_result_sel_mc_arith =  1'b1;        
+ 
+
+  
+      
+                      
+
+
+ 
+
+  
+      
+                  
+
+
+  
+
+    else if (sext)
+        x_result_sel_sext =  1'b1;
+ 
+        
+    else if (logical) 
+        x_result_sel_logic =  1'b1;
+          
+      
+          
+
+
+    else 
+        x_result_sel_add =  1'b1;        
+    
+    
+
+    m_result_sel_compare = cmp;
+  
+
+    m_result_sel_shift = shift;
+ 
+
+
+    
+    w_result_sel_load = load;
+  
+
+    w_result_sel_mul = op_mul; 
+ 
+
+end
+
+
+assign x_bypass_enable =  arith 
+                        | logical
+  
+                         
+                         
+
+                        
+  
+                         
+
+
+  
+
+                        | divide
+                        | modulus
+ 
+
+  
+                         
+
+                  
+  
+
+                        | sext 
+ 
+                        
+  
+                         
+
+
+                        | op_rcsr
+                        ;
+
+assign m_bypass_enable = x_bypass_enable 
+  
+
+                        | shift
+ 
+
+                        | cmp
+                        ;
+
+assign read_enable_0 = ~(op_bi | op_calli);
+assign read_idx_0 = instruction[25:21];
+
+assign read_enable_1 = ~(op_bi | op_calli | load);
+assign read_idx_1 = instruction[20:16];
+
+assign write_enable = ~(bra | op_raise | store | op_wcsr);
+assign write_idx = call
+                    ? 5'd29
+                    : instruction[31] == 1'b0 
+                        ? instruction[20:16] 
+                        : instruction[15:11];
+                        
+
+assign size = instruction[27:26];
+
+assign sign_extend = instruction[28];                      
+
+assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
+
+assign logic_op = instruction[29:26];
+  
+
+
+assign direction = instruction[29];
+ 
+
+
+assign branch = bra | call;
+assign branch_reg = op_call | op_b;
+assign condition = instruction[28:26];      
+  
+
+assign break_opcode = op_raise & ~instruction[2];
+ 
+
+assign scall = op_raise & instruction[2];
+assign eret = op_b & (instruction[25:21] == 5'd30);
+  
+
+assign bret = op_b & (instruction[25:21] == 5'd31);
+ 
+
+  
+
+   
+
+
+
+assign csr_write_enable = op_wcsr;
+
+
+
+assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
+assign select_high_immediate = op_andhi | op_orhi;
+assign select_call_immediate = instruction[31];
+
+assign high_immediate = {instruction[15:0], 16'h0000};
+assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
+assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
+assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
+
+assign immediate = select_high_immediate ==  1'b1 
+                        ? high_immediate 
+                        : extended_immediate;
+   
+assign branch_offset = select_call_immediate ==  1'b1   
+                        ? (call_immediate[ (32-2)-1:0])
+                        : (branch_immediate[ (32-2)-1:0]);
+    
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
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+                
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+                      
+                
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+    
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+   
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+       
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+     
+    
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+        
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+          
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+
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+                
+ 
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+ 
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+ 
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+              
+                  
+                 
+            
+
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+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
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+ 
+ 
+
+ 
+ 
+
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+
+
+
+
+                   
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+
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+                    
+                 
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+
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+                   
+                   
+                   
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+                  
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+
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+                 
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+              
+          
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+
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+                   
+                
+                
+                
+               
+
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+
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+
+
+  
+
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+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
+
+
+
+
+module lm32_debug_wr_node (
+    
+    clk_i, 
+    rst_i,
+    pc_x,
+    load_x,
+    store_x,
+    load_store_address_x,
+    csr_write_enable_x,
+    csr_write_data,
+    csr_x,
+  
+
+  
+    
+    
+    
+
+
+  
+
+   dbg_csr_write_enable_i,
+   dbg_csr_write_data_i,
+   dbg_csr_addr_i,
+ 
+
+  
+
+
+		   
+  
+
+    eret_q_x,
+    bret_q_x,
+    stall_x,
+    exception_x,
+    q_x,
+  
+    
+
+
+ 
+
+
+    
+  
+
+    dc_ss,
+ 
+
+    dc_re,
+    bp_match,
+    wp_match
+    );
+    
+
+
+
+
+parameter breakpoints = 0;                      
+parameter watchpoints = 0;                      
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [ ((32-2)+2-1):2] pc_x;                      
+input load_x;                                   
+input store_x;                                  
+input [ (32-1):0] load_store_address_x;    
+input csr_write_enable_x;                       
+input [ (32-1):0] csr_write_data;          
+input [ (5-1):0] csr_x;                    
+  
+
+  
+                     
+       
+                   
+
+
+     
+
+input dbg_csr_write_enable_i;                         
+input [ (32-1):0] dbg_csr_write_data_i;          
+input [ (5-1):0] dbg_csr_addr_i;                        
+ 
+
+ 
+
+
+
+  
+
+input eret_q_x;                                 
+input bret_q_x;                                 
+input stall_x;                                  
+input exception_x;                              
+input q_x;                                      
+  
+                     
+
+
+ 
+
+
+
+
+
+
+  
+
+output dc_ss;                                   
+reg    dc_ss;
+ 
+
+output dc_re;                                   
+reg    dc_re;
+output bp_match;                                
+wire   bp_match;        
+output wp_match;                                
+wire   wp_match;
+
+
+
+
+
+genvar i;                                       
+
+
+
+reg [ ((32-2)+2-1):2] bp_a[0:breakpoints-1];       
+reg bp_e[0:breakpoints-1];                      
+wire [0:breakpoints-1]bp_match_n;               
+
+reg [ 1:0] wpc_c[0:watchpoints-1];   
+reg [ (32-1):0] wp[0:watchpoints-1];       
+wire [0:watchpoints-1]wp_match_n;               
+
+wire debug_csr_write_enable;                    
+wire [ (32-1):0] debug_csr_write_data;     
+wire [ (5-1):0] debug_csr;                 
+
+  
+
+
+reg [ 2:0] state;           
+
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+generate
+    for (i = 0; i < breakpoints; i = i + 1)
+    begin : bp_comb
+assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] ==  1'b1));
+    end
+endgenerate
+generate 
+  
+
+    if (breakpoints > 0) 
+assign bp_match = (|bp_match_n) || (state ==  3'b011);
+    else
+assign bp_match = state ==  3'b011;
+ 
+        
+   
+    
+   
+
+
+endgenerate    
+               
+
+generate 
+    for (i = 0; i < watchpoints; i = i + 1)
+    begin : wp_comb
+assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
+    end               
+endgenerate
+generate
+    if (watchpoints > 0) 
+assign wp_match = |wp_match_n;                
+    else
+assign wp_match =  1'b0;
+endgenerate
+                
+  
+                
+
+  
+         
+         
+         
+
+
+   
+  
+
+assign debug_csr_write_enable = (csr_write_enable_x ==  1'b1) || (dbg_csr_write_enable_i ==  1'b1);
+assign debug_csr_write_data = dbg_csr_write_data_i ==  1'b1 ? dbg_csr_write_data_i : csr_write_data;
+assign debug_csr = dbg_csr_write_enable_i ==  1'b1 ? dbg_csr_addr_i : csr_x;
+
+ 
+
+   
+ 
+   
+   
+   
+
+
+
+
+
+
+
+
+generate
+    for (i = 0; i < breakpoints; i = i + 1)
+    begin : bp_seq
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        bp_a[i] <= { (32-2){1'bx}};
+        bp_e[i] <=  1'b0;
+    end
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h10 + i))
+        begin
+            bp_a[i] <= debug_csr_write_data[ ((32-2)+2-1):2];
+            bp_e[i] <= debug_csr_write_data[0];
+        end
+    end
+end    
+    end
+endgenerate
+
+
+generate
+    for (i = 0; i < watchpoints; i = i + 1)
+    begin : wp_seq
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        wp[i] <= { 32{1'bx}};
+        wpc_c[i] <=  2'b00;
+    end
+    else
+    begin
+        if (debug_csr_write_enable ==  1'b1)
+        begin
+            if (debug_csr ==  5'h8)
+                wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
+            if (debug_csr ==  5'h18 + i)
+                wp[i] <= debug_csr_write_data;
+        end
+    end  
+end
+    end
+endgenerate
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        dc_re <=  1'b0;
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h8))
+            dc_re <= debug_csr_write_data[1];
+    end
+end    
+
+  
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        state <=  3'b000;
+        dc_ss <=  1'b0;
+    end
+    else
+    begin
+        if ((debug_csr_write_enable ==  1'b1) && (debug_csr ==  5'h8))
+        begin
+            dc_ss <= debug_csr_write_data[0];
+            if (debug_csr_write_data[0] ==  1'b0) 
+                state <=  3'b000;
+            else 
+                state <=  3'b001;
+        end
+        case (state)
+         3'b001:
+        begin
+            
+            if (   (   (eret_q_x ==  1'b1)
+                    || (bret_q_x ==  1'b1)
+                    )
+                && (stall_x ==  1'b0)
+               )
+                state <=  3'b010; 
+        end
+         3'b010:
+        begin
+            
+            if ((q_x ==  1'b1) && (stall_x ==  1'b0))
+                state <=  3'b011;
+        end
+         3'b011:
+        begin
+            
+  
+               
+                  
+             
+
+
+                 if ((exception_x ==  1'b1) && (q_x ==  1'b1) && (stall_x ==  1'b0))
+            begin
+                dc_ss <=  1'b0;
+                state <=  3'b100;
+            end
+        end
+         3'b100:
+        begin
+            
+  
+               
+                  
+             
+
+
+                state <=  3'b000;
+        end
+        endcase
+    end
+end
+ 
+
+
+endmodule
+
+ 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
+
+
+ 
+                    
+
+ 
+                    
+
+  
+                    
+
+
+                      
+
+
+           
+             
+
+
+                
+           
+
+
+              
+               
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+
+ 
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+ 
+ 
+
+ 
+ 
+
+ 
+ 
+
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+                    
+
+
+                
+
+
+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_instruction_unit_wr_node (
+    
+    clk_i,
+    rst_i,
+    
+    stall_a,
+    stall_f,
+    stall_d,
+    stall_x,
+    stall_m,
+    valid_f,
+    valid_d,
+    kill_f,
+    branch_predict_taken_d,
+    branch_predict_address_d,
+      
+    
+    
+
+
+    exception_m,
+    branch_taken_m,
+    branch_mispredict_taken_m,
+    branch_target_m,
+  
+    
+
+
+  
+    
+    
+    
+
+        
+  
+    
+    
+    
+    
+    
+
+
+  
+
+    jtag_read_enable,
+    jtag_write_enable,
+    jtag_write_data,
+    jtag_address,
+ 
+
+    
+    
+    pc_f,
+    pc_d,
+    pc_x,
+    pc_m,
+    pc_w,
+  
+    
+    
+    
+    
+
+
+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+
+
+  
+
+    iram_i_adr_o,
+    iram_i_dat_i,
+    iram_i_en_o,
+ 
+
+  
+
+    jtag_read_data,
+    jtag_access_complete,
+ 
+
+  
+
+    bus_error_d,
+ 
+
+  
+
+    instruction_f,
+ 
+    
+    instruction_d
+    );
+
+
+
+
+
+parameter eba_reset =  32'h00000000;                   
+parameter associativity = 1;                            
+parameter sets = 512;                                   
+parameter bytes_per_line = 16;                          
+parameter base_address = 0;                             
+parameter limit = 0;                                    
+
+
+localparam eba_reset_minus_4 = eba_reset - 4;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+
+
+
+  
+
+output [31:0] iram_i_adr_o;
+input [31:0]  iram_i_dat_i;
+   output     iram_i_en_o;
+   
+ 
+
+
+input clk_i;                                            
+input rst_i;                                            
+
+input stall_a;                                          
+input stall_f;                                          
+input stall_d;                                          
+input stall_x;                                          
+input stall_m;                                          
+input valid_f;                                          
+input valid_d;                                          
+input kill_f;                                           
+
+input branch_predict_taken_d;                           
+input [ ((32-2)+2-1):2] branch_predict_address_d;          
+   
+      
+                                    
+                     
+
+
+input exception_m;
+input branch_taken_m;                                   
+input branch_mispredict_taken_m;                        
+input [ ((32-2)+2-1):2] branch_target_m;                   
+
+  
+                                            
+
+
+  
+                            
+                             
+ 
+
+        
+
+
+  
+                           
+                                           
+                                           
+                                           
+
+
+
+  
+
+input jtag_read_enable;                                 
+input jtag_write_enable;                                
+input [ 7:0] jtag_write_data;                 
+input [ (32-1):0] jtag_address;                    
+ 
+
+
+
+
+
+        
+output [ ((32-2)+2-1):2] pc_f;                             
+reg    [ ((32-2)+2-1):2] pc_f;
+output [ ((32-2)+2-1):2] pc_d;                             
+reg    [ ((32-2)+2-1):2] pc_d;
+output [ ((32-2)+2-1):2] pc_x;                             
+reg    [ ((32-2)+2-1):2] pc_x;
+output [ ((32-2)+2-1):2] pc_m;                             
+reg    [ ((32-2)+2-1):2] pc_m;
+output [ ((32-2)+2-1):2] pc_w;                             
+reg    [ ((32-2)+2-1):2] pc_w;
+
+  
+                             
+   
+                           
+   
+                            
+   
+                                 
+   
+
+
+
+  
+                          
+ 
+     
+
+    
+
+                          
+     
+                                          
+     
+                   
+ 
+     
+
+    
+
+                                          
+    
+                                           
+ 
+    
+
+   
+
+                         
+     
+                                         
+    
+                         
+    
+
+
+
+  
+
+output [ 7:0] jtag_read_data;                 
+reg    [ 7:0] jtag_read_data;
+output jtag_access_complete;                            
+wire   jtag_access_complete;
+ 
+
+
+  
+
+output bus_error_d;                                     
+reg    bus_error_d;
+ 
+
+  
+
+output [ (32-1):0] instruction_f;           
+wire   [ (32-1):0] instruction_f;
+ 
+
+output [ (32-1):0] instruction_d;           
+reg    [ (32-1):0] instruction_d;
+
+
+
+
+
+reg [ ((32-2)+2-1):2] pc_a;                                
+
+  
+                       
+
+
+
+  
+                               
+                
+                                 
+           
+               
+                  
+                   
+                                          
+                        
+
+
+  
+                    
+
+
+ 
+
+  
+
+wire iram_select_a;                                     
+   reg 			     iram_select_f;
+   
+ 
+
+  
+
+ 
+               
+
+
+
+  
+ 
+   
+   
+    			               
+ 
+
+ 
+
+  
+
+   wire 		     bus_error_f = 0;
+ 
+
+   
+  
+
+reg jtag_access;                                        
+ 
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+					  
+function integer clogb2;
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+        value = value >> 1;
+end
+endfunction 
+
+function integer clogb2_v1;
+input [31:0] value;
+reg   [31:0] i;
+reg   [31:0] temp;
+begin
+   temp = 0;
+   i    = 0;
+   for (i = 0; temp < value; i = i + 1)  
+	temp = 1<<i;
+   clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+  
+
+ 
+              
+                       
+             
+               
+                      
+       
+    
+                      
+                            
+                    
+                    
+     
+                    
+                  
+                  
+              
+               
+                
+                     
+    
+              
+            
+             
+             
+                  
+                       
+    
+
+
+
+
+
+
+
+  
+   
+           
+        
+  
+      
+                          
+   
+				       
+        
+				    
+
+ 
+
+
+always @(*)
+begin
+    
+  
+       
+          
+     
+
+    
+      if (branch_taken_m ==  1'b1)
+	if ((branch_mispredict_taken_m ==  1'b1) && (exception_m ==  1'b0))
+	  pc_a = pc_x;
+	else
+          pc_a = branch_target_m;
+      
+          
+          
+
+
+      else
+	if ( (valid_d ==  1'b1) && (branch_predict_taken_d ==  1'b1) )
+	  pc_a = branch_predict_address_d;
+	else
+  
+             
+              
+	   
+
+        
+            pc_a = pc_f + 1'b1;
+end
+
+
+  
+
+   assign iram_select_a = 1'b1;
+   assign iram_i_en_o = !stall_a;
+   assign iram_i_adr_o = {pc_a, 2'b00}; 
+ 
+
+
+  
+
+
+   reg [31:0] prev_instruction_f;
+   reg 	      iram_i_en_d0;
+
+   always@(posedge clk_i) 
+     if(rst_i) begin
+	iram_i_en_d0 <= 0;
+     end else begin
+	iram_i_en_d0 <= !stall_a;
+	if(iram_i_en_d0)
+	  prev_instruction_f <= iram_i_dat_i;
+     end
+   
+   
+   assign instruction_f = (!iram_i_en_d0) ? prev_instruction_f : iram_i_dat_i;
+
+
+  
+   
+ 
+                     
+
+ 
+   
+
+   
+
+
+
+ 
+   
+
+  
+ 
+
+   
+   
+   
+
+   
+
+
+
+  
+
+
+     
+    
+    
+   
+   
+   
+   
+    
+    
+    
+   
+   
+     
+    
+    
+    
+    
+   
+         
+     
+    
+    
+    
+
+
+
+                     
+
+
+
+
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+    begin
+        pc_f <= eba_reset_minus_4[ ((32-2)+2-1):2];
+        pc_d <= { (32-2){1'b0}};
+        pc_x <= { (32-2){1'b0}};
+        pc_m <= { (32-2){1'b0}};
+        pc_w <= { (32-2){1'b0}};
+    end
+    else
+    begin
+        if (stall_f ==  1'b0)
+            pc_f <= pc_a;
+        if (stall_d ==  1'b0)
+            pc_d <= pc_f;
+        if (stall_x ==  1'b0)
+            pc_x <= pc_d;
+        if (stall_m ==  1'b0)
+            pc_m <= pc_x;
+        pc_w <= pc_m;
+    end
+end
+
+  
+
+   
+
+       
+          
+    
+    
+ 
+         
+            
+               
+                  
+                    
+                  
+
+               
+                  
+
+
+         
+               
+                  
+
+
+    
+
+
+
+
+
+  
+
+always @(posedge clk_i  )
+begin
+    if (rst_i ==  1'b1)
+        iram_select_f <=  1'b0;
+    else
+    begin
+        if (stall_f ==  1'b0)
+            iram_select_f <= iram_select_a;
+    end
+end
+ 
+
+
+  
+
+     
+                 
+ 
+
+     
+       
+       
+       
+       
+     
+
+   
+
+ 
+
+
+  
+   
+                  
+      
+     
+	   
+	  
+               
+               
+               
+               
+               
+               
+               
+   
+               
+  
+   
+               
+               
+               
+  
+	  
+	
+	     
+               
+             
+                
+               
+		  
+		         
+		    
+   
+                          
+			 
+			      
+			             
+			        
+			          
+			 
+                       
+  
+			 
+			       
+			      
+				 
+				   
+				   
+				   
+			      
+			    
+			        
+			      
+			    
+			      
+			      
+			 
+		    
+   
+		   
+		     
+		    
+                         
+                         
+		    
+		  
+  
+               
+             
+               
+		         
+		    
+                       
+        
+                         
+  
+                          
+                         
+                                         
+                         
+                       
+   
+                         
+  
+		    
+   
+		  
+		    
+                              
+			 
+			     
+			         
+			         
+			         
+			         
+			    
+			      
+			      
+			      
+			      
+			      
+			      
+			      
+			 
+		     
+                      
+   
+		  
+		  
+        
+		     
+                      
+   
+		     
+                      
+  
+               
+	  
+     
+ 
+      
+     
+	   
+	  
+               
+               
+               
+               
+               
+               
+   
+               
+  
+	  
+	
+	     
+             
+                
+               
+		  
+		        
+		    
+                       
+                         
+                         
+                       
+                         
+		    
+   
+		   
+		     
+		    
+                         
+                         
+		       
+		    
+		  
+  
+               
+             
+               
+		  
+		         
+    
+			    
+         
+			 
+		    
+                       
+        
+                         
+  
+                          
+                         
+                         
+   
+                         
+  
+		    
+		  
+		    
+	                      
+    
+			         
+         
+			      
+			 
+   
+			      
+  
+			 
+		    
+               
+	  
+     
+ 
+
+ 
+
+   
+   always @(posedge clk_i  )
+     begin
+	if (rst_i ==  1'b1)
+	  begin
+             instruction_d <= { 32{1'b0}};
+  
+
+             bus_error_d <=  1'b0;
+ 
+
+	  end
+	else
+	  begin
+             if (stall_d ==  1'b0)
+               begin
+		  instruction_d <= instruction_f;
+  
+
+		  bus_error_d <= bus_error_f;
+ 
+
+               end
+	  end
+     end  
+   
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+ 
+ 
+
+
+
+
+ 
+
+     
+    
+   
+  
+
+
+
+ 
+ 
+
+
+ 
+
+
+                  
+                    
+                 
+                   
+           
+             
+
+
+                   
+               
+                 
+
+
+                      
+                      
+                      
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+                    
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+                    
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+           
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+                    
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+                  
+         
+          
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+          
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+          
+      
+      
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+    
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+        
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+                  
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+                  
+                    
+                 
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+           
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+               
+                 
+
+
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+                      
+                      
+
+
+ 
+                    
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+                    
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+  
+                    
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+
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+
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+           
+
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+              
+               
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+                    
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+             
+               
+                 
+                 
+                
+               
+                
+                
+                
+                
+
+
+                  
+                    
+                   
+                  
+                   
+          
+
+
+ 
+                   
+                     
+
+ 
+                   
+                     
+
+                    
+                     
+
+
+
+
+                      
+                      
+                      
+                     
+                     
+                      
+                     
+                     
+ 
+                      
+                    
+
+                    
+                     
+                
+ 
+                     
+                     
+
+ 
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+                     
+ 
+
+
+                   
+              
+                  
+                 
+            
+
+
+                   
+                     
+                   
+              
+          
+              
+          
+          
+               
+                   
+
+
+
+           
+         
+       
+
+           
+          
+         
+     
+
+            
+              
+
+
+ 
+ 
+
+ 
+ 
+
+
+
+
+
+
+
+
+                   
+             
+               
+
+
+
+
+
+
+                  
+                    
+                 
+                   
+
+
+                   
+                   
+                   
+                   
+
+
+                  
+                  
+
+
+ 
+
+
+
+
+
+
+                 
+                   
+               
+              
+          
+                   
+
+
+                 
+                   
+                
+                
+                
+               
+
+
+
+
+
+
+
+
+
+
+module lm32_interrupt_wr_node (
+    
+    clk_i, 
+    rst_i,
+    
+    interrupt,
+    
+    stall_x,
+  
+
+    non_debug_exception,
+    debug_exception,
+ 
+    
+
+
+    eret_q_x,
+  
+
+    bret_q_x,
+ 
+
+    csr,
+    csr_write_data,
+    csr_write_enable,
+    
+    interrupt_exception,
+    
+    csr_read_data
+    );
+
+
+
+
+
+parameter interrupts =  32;         
+
+
+
+
+
+input clk_i;                                    
+input rst_i;                                    
+
+input [interrupts-1:0] interrupt;               
+
+input stall_x;                                  
+
+  
+
+input non_debug_exception;                      
+input debug_exception;                          
+ 
+                                 
+
+
+input eret_q_x;                                 
+  
+
+input bret_q_x;                                 
+ 
+
+
+input [ (5-1):0] csr;                      
+input [ (32-1):0] csr_write_data;          
+input csr_write_enable;                         
+
+
+
+
+
+output interrupt_exception;                     
+wire   interrupt_exception;
+
+output [ (32-1):0] csr_read_data;          
+reg    [ (32-1):0] csr_read_data;
+
+
+
+
+
+wire [interrupts-1:0] asserted;                 
+
+wire [interrupts-1:0] interrupt_n_exception;
+
+
+
+reg ie;                                         
+reg eie;                                        
+  
+
+reg bie;                                        
+ 
+
+reg [interrupts-1:0] ip;                        
+reg [interrupts-1:0] im;                        
+
+
+
+
+
+
+assign interrupt_n_exception = ip & im;
+
+
+assign interrupt_exception = (|interrupt_n_exception) & ie;
+
+
+assign asserted = ip | interrupt;
+       
+generate
+    if (interrupts > 1) 
+    begin
+
+always @(*)
+begin
+    case (csr)
+     5'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+
+                                    bie,
+ 
+                                                                         
+
+
+                                    eie, 
+                                    ie
+                                   };
+     5'h2:  csr_read_data = ip;
+     5'h1:  csr_read_data = im;
+    default:       csr_read_data = { 32{1'bx}};
+    endcase
+end
+    end
+    else
+    begin
+
+always @(*)
+begin
+    case (csr)
+     5'h0:  csr_read_data = {{ 32-3{1'b0}}, 
+  
+
+                                    bie, 
+ 
+                                                                        
+
+
+                                    eie, 
+                                    ie
+                                   };
+     5'h2:  csr_read_data = ip;
+    default:       csr_read_data = { 32{1'bx}};
+      endcase
+end
+    end
+endgenerate
+    
+
+
+
+
+  
+
+   reg [ 10:0] eie_delay  = 0;
+
+   
+generate
+
+   
+    if (interrupts > 1)
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie                   <=  1'b0;
+        eie                  <=  1'b0;
+  
+
+        bie                  <=  1'b0;
+ 
+
+        im                   <= {interrupts{1'b0}};
+        ip                   <= {interrupts{1'b0}};
+       eie_delay             <= 0;
+       
+    end
+    else
+    begin
+        
+        ip                   <= asserted;
+  
+
+        if (non_debug_exception ==  1'b1)
+        begin
+            
+            eie              <= ie;
+            ie               <=  1'b0;
+        end
+        else if (debug_exception ==  1'b1)
+        begin
+            
+            bie              <= ie;
+            ie               <=  1'b0;
+        end
+ 
+           
+        
+            
+                           
+                            
+        
+
+
+        else if (stall_x ==  1'b0)
+        begin
+
+           if(eie_delay[0])
+             ie              <= eie;
+           
+           eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+            if (eret_q_x ==  1'b1) begin
+                
+               eie_delay[ 10] <=  1'b1;
+               eie_delay[ 10-1:0] <= 0;
+            end
+           
+                      
+           
+  
+
+            else if (bret_q_x ==  1'b1)
+                
+                ie      <= bie;
+ 
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  5'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+
+                    bie <= csr_write_data[2];
+ 
+
+                end
+                if (csr ==  5'h1)
+                    im  <= csr_write_data[interrupts-1:0];
+                if (csr ==  5'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+else
+    begin
+
+always @(posedge clk_i  )
+  begin
+    if (rst_i ==  1'b1)
+    begin
+        ie              <=  1'b0;
+        eie             <=  1'b0;
+  
+
+        bie             <=  1'b0;
+ 
+
+        ip              <= {interrupts{1'b0}};
+       eie_delay        <= 0;
+    end
+    else
+    begin
+        
+        ip              <= asserted;
+  
+
+        if (non_debug_exception ==  1'b1)
+        begin
+            
+            eie         <= ie;
+            ie          <=  1'b0;
+        end
+        else if (debug_exception ==  1'b1)
+        begin
+            
+            bie         <= ie;
+            ie          <=  1'b0;
+        end
+ 
+           
+        
+            
+                      
+                       
+        
+
+
+        else if (stall_x ==  1'b0)
+          begin
+
+             if(eie_delay[0])
+               ie              <= eie;
+           
+             eie_delay         <= {1'b0, eie_delay[ 10:1]};
+
+             if (eret_q_x ==  1'b1) begin
+                
+                eie_delay[ 10] <=  1'b1;
+                eie_delay[ 10-1:0] <= 0;
+             end
+           
+  
+
+            else if (bret_q_x ==  1'b1)
+                
+                ie      <= bie;
+ 
+
+            else if (csr_write_enable ==  1'b1)
+            begin
+                
+                if (csr ==  5'h0)
+                begin
+                    ie  <= csr_write_data[0];
+                    eie <= csr_write_data[1];
+  
+
+                    bie <= csr_write_data[2];
+ 
+
+                end
+                if (csr ==  5'h2)
+                    ip  <= asserted & ~csr_write_data[interrupts-1:0];
+            end
+        end
+    end
+end
+    end
+endgenerate
+
+endmodule
+
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
new file mode 100644
index 000000000..d57c9b7ab
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
@@ -0,0 +1,825 @@
+--auto-generated by gen_lmcores.py. Don't hand-edit please
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wishbone_pkg.all;
+entity xwb_lm32 is
+generic(g_profile: string;
+g_reset_vector: std_logic_vector(31 downto 0) := x"00000000";
+g_sdb_address: std_logic_vector(31 downto 0) := x"00000000");
+port(
+clk_sys_i : in  std_logic;
+rst_n_i : in  std_logic;
+irq_i : in  std_logic_vector(31 downto 0);
+dwb_o  : out t_wishbone_master_out;
+dwb_i  : in  t_wishbone_master_in;
+iwb_o  : out t_wishbone_master_out;
+iwb_i  : in  t_wishbone_master_in);
+end xwb_lm32;
+architecture rtl of xwb_lm32 is 
+function f_eval_i_burst_length(profile_name:string) return natural is
+begin
+if profile_name = "minimal" then return 1; end if; 
+if profile_name = "medium" then return 1; end if; 
+if profile_name = "medium_icache" then return 4; end if; 
+if profile_name = "medium_debug" then return 4; end if; 
+if profile_name = "medium_icache_debug" then return 4; end if; 
+if profile_name = "full" then return 4; end if; 
+if profile_name = "full_debug" then return 4; end if; 
+if profile_name = "wr_node" then return 1; end if; 
+return 0;
+end function;
+function f_eval_d_burst_length(profile_name:string) return natural is
+begin
+if profile_name = "minimal" then return 1; end if; 
+if profile_name = "medium" then return 1; end if; 
+if profile_name = "medium_icache" then return 1; end if; 
+if profile_name = "medium_debug" then return 1; end if; 
+if profile_name = "medium_icache_debug" then return 1; end if; 
+if profile_name = "full" then return 4; end if; 
+if profile_name = "full_debug" then return 4; end if; 
+if profile_name = "wr_node" then return 1; end if; 
+return 0;
+end function;
+component lm32_top_minimal is 
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
+port (
+ 
+  clk_i    : in  std_logic;
+  rst_i    : in  std_logic;
+  interrupt  : in  std_logic_vector(31 downto 0);
+  I_DAT_I  : in  std_logic_vector(31 downto 0);
+  I_ACK_I  : in  std_logic;
+  I_ERR_I  : in  std_logic;
+  I_RTY_I  : in  std_logic;
+   D_DAT_I  : in  std_logic_vector(31 downto 0);
+   D_ACK_I  : in  std_logic;
+   D_ERR_I  : in  std_logic;
+   D_RTY_I  : in  std_logic;
+   I_DAT_O  : out std_logic_vector(31 downto 0);
+   I_ADR_O  : out std_logic_vector(31 downto 0);
+   I_CYC_O  : out std_logic;
+   I_SEL_O  : out std_logic_vector(3 downto 0);
+   I_STB_O  : out std_logic;
+   I_WE_O   : out std_logic;
+   I_CTI_O  : out std_logic_vector(2 downto 0);
+   I_LOCK_O : out std_logic;
+   I_BTE_O  : out std_logic_vector(1 downto 0);
+   D_DAT_O  : out std_logic_vector(31 downto 0);
+   D_ADR_O  : out std_logic_vector(31 downto 0);
+   D_CYC_O  : out std_logic;
+   D_SEL_O  : out std_logic_vector(3 downto 0);
+   D_STB_O  : out std_logic;
+   D_WE_O   : out std_logic;
+   D_CTI_O  : out std_logic_vector(2 downto 0);
+   D_LOCK_O : out std_logic;
+   D_BTE_O  : out std_logic_vector(1 downto 0));
+end component;
+component lm32_top_medium is 
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
+port (
+ 
+  clk_i    : in  std_logic;
+  rst_i    : in  std_logic;
+  interrupt  : in  std_logic_vector(31 downto 0);
+  I_DAT_I  : in  std_logic_vector(31 downto 0);
+  I_ACK_I  : in  std_logic;
+  I_ERR_I  : in  std_logic;
+  I_RTY_I  : in  std_logic;
+   D_DAT_I  : in  std_logic_vector(31 downto 0);
+   D_ACK_I  : in  std_logic;
+   D_ERR_I  : in  std_logic;
+   D_RTY_I  : in  std_logic;
+   I_DAT_O  : out std_logic_vector(31 downto 0);
+   I_ADR_O  : out std_logic_vector(31 downto 0);
+   I_CYC_O  : out std_logic;
+   I_SEL_O  : out std_logic_vector(3 downto 0);
+   I_STB_O  : out std_logic;
+   I_WE_O   : out std_logic;
+   I_CTI_O  : out std_logic_vector(2 downto 0);
+   I_LOCK_O : out std_logic;
+   I_BTE_O  : out std_logic_vector(1 downto 0);
+   D_DAT_O  : out std_logic_vector(31 downto 0);
+   D_ADR_O  : out std_logic_vector(31 downto 0);
+   D_CYC_O  : out std_logic;
+   D_SEL_O  : out std_logic_vector(3 downto 0);
+   D_STB_O  : out std_logic;
+   D_WE_O   : out std_logic;
+   D_CTI_O  : out std_logic_vector(2 downto 0);
+   D_LOCK_O : out std_logic;
+   D_BTE_O  : out std_logic_vector(1 downto 0));
+end component;
+component lm32_top_medium_icache is 
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
+port (
+ 
+  clk_i    : in  std_logic;
+  rst_i    : in  std_logic;
+  interrupt  : in  std_logic_vector(31 downto 0);
+  I_DAT_I  : in  std_logic_vector(31 downto 0);
+  I_ACK_I  : in  std_logic;
+  I_ERR_I  : in  std_logic;
+  I_RTY_I  : in  std_logic;
+   D_DAT_I  : in  std_logic_vector(31 downto 0);
+   D_ACK_I  : in  std_logic;
+   D_ERR_I  : in  std_logic;
+   D_RTY_I  : in  std_logic;
+   I_DAT_O  : out std_logic_vector(31 downto 0);
+   I_ADR_O  : out std_logic_vector(31 downto 0);
+   I_CYC_O  : out std_logic;
+   I_SEL_O  : out std_logic_vector(3 downto 0);
+   I_STB_O  : out std_logic;
+   I_WE_O   : out std_logic;
+   I_CTI_O  : out std_logic_vector(2 downto 0);
+   I_LOCK_O : out std_logic;
+   I_BTE_O  : out std_logic_vector(1 downto 0);
+   D_DAT_O  : out std_logic_vector(31 downto 0);
+   D_ADR_O  : out std_logic_vector(31 downto 0);
+   D_CYC_O  : out std_logic;
+   D_SEL_O  : out std_logic_vector(3 downto 0);
+   D_STB_O  : out std_logic;
+   D_WE_O   : out std_logic;
+   D_CTI_O  : out std_logic_vector(2 downto 0);
+   D_LOCK_O : out std_logic;
+   D_BTE_O  : out std_logic_vector(1 downto 0));
+end component;
+component lm32_top_medium_debug is 
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
+port (
+ 
+  clk_i    : in  std_logic;
+  rst_i    : in  std_logic;
+  interrupt  : in  std_logic_vector(31 downto 0);
+  I_DAT_I  : in  std_logic_vector(31 downto 0);
+  I_ACK_I  : in  std_logic;
+  I_ERR_I  : in  std_logic;
+  I_RTY_I  : in  std_logic;
+   D_DAT_I  : in  std_logic_vector(31 downto 0);
+   D_ACK_I  : in  std_logic;
+   D_ERR_I  : in  std_logic;
+   D_RTY_I  : in  std_logic;
+   I_DAT_O  : out std_logic_vector(31 downto 0);
+   I_ADR_O  : out std_logic_vector(31 downto 0);
+   I_CYC_O  : out std_logic;
+   I_SEL_O  : out std_logic_vector(3 downto 0);
+   I_STB_O  : out std_logic;
+   I_WE_O   : out std_logic;
+   I_CTI_O  : out std_logic_vector(2 downto 0);
+   I_LOCK_O : out std_logic;
+   I_BTE_O  : out std_logic_vector(1 downto 0);
+   D_DAT_O  : out std_logic_vector(31 downto 0);
+   D_ADR_O  : out std_logic_vector(31 downto 0);
+   D_CYC_O  : out std_logic;
+   D_SEL_O  : out std_logic_vector(3 downto 0);
+   D_STB_O  : out std_logic;
+   D_WE_O   : out std_logic;
+   D_CTI_O  : out std_logic_vector(2 downto 0);
+   D_LOCK_O : out std_logic;
+   D_BTE_O  : out std_logic_vector(1 downto 0));
+end component;
+component lm32_top_medium_icache_debug is 
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
+port (
+ 
+  clk_i    : in  std_logic;
+  rst_i    : in  std_logic;
+  interrupt  : in  std_logic_vector(31 downto 0);
+  I_DAT_I  : in  std_logic_vector(31 downto 0);
+  I_ACK_I  : in  std_logic;
+  I_ERR_I  : in  std_logic;
+  I_RTY_I  : in  std_logic;
+   D_DAT_I  : in  std_logic_vector(31 downto 0);
+   D_ACK_I  : in  std_logic;
+   D_ERR_I  : in  std_logic;
+   D_RTY_I  : in  std_logic;
+   I_DAT_O  : out std_logic_vector(31 downto 0);
+   I_ADR_O  : out std_logic_vector(31 downto 0);
+   I_CYC_O  : out std_logic;
+   I_SEL_O  : out std_logic_vector(3 downto 0);
+   I_STB_O  : out std_logic;
+   I_WE_O   : out std_logic;
+   I_CTI_O  : out std_logic_vector(2 downto 0);
+   I_LOCK_O : out std_logic;
+   I_BTE_O  : out std_logic_vector(1 downto 0);
+   D_DAT_O  : out std_logic_vector(31 downto 0);
+   D_ADR_O  : out std_logic_vector(31 downto 0);
+   D_CYC_O  : out std_logic;
+   D_SEL_O  : out std_logic_vector(3 downto 0);
+   D_STB_O  : out std_logic;
+   D_WE_O   : out std_logic;
+   D_CTI_O  : out std_logic_vector(2 downto 0);
+   D_LOCK_O : out std_logic;
+   D_BTE_O  : out std_logic_vector(1 downto 0));
+end component;
+component lm32_top_full is 
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
+port (
+ 
+  clk_i    : in  std_logic;
+  rst_i    : in  std_logic;
+  interrupt  : in  std_logic_vector(31 downto 0);
+  I_DAT_I  : in  std_logic_vector(31 downto 0);
+  I_ACK_I  : in  std_logic;
+  I_ERR_I  : in  std_logic;
+  I_RTY_I  : in  std_logic;
+   D_DAT_I  : in  std_logic_vector(31 downto 0);
+   D_ACK_I  : in  std_logic;
+   D_ERR_I  : in  std_logic;
+   D_RTY_I  : in  std_logic;
+   I_DAT_O  : out std_logic_vector(31 downto 0);
+   I_ADR_O  : out std_logic_vector(31 downto 0);
+   I_CYC_O  : out std_logic;
+   I_SEL_O  : out std_logic_vector(3 downto 0);
+   I_STB_O  : out std_logic;
+   I_WE_O   : out std_logic;
+   I_CTI_O  : out std_logic_vector(2 downto 0);
+   I_LOCK_O : out std_logic;
+   I_BTE_O  : out std_logic_vector(1 downto 0);
+   D_DAT_O  : out std_logic_vector(31 downto 0);
+   D_ADR_O  : out std_logic_vector(31 downto 0);
+   D_CYC_O  : out std_logic;
+   D_SEL_O  : out std_logic_vector(3 downto 0);
+   D_STB_O  : out std_logic;
+   D_WE_O   : out std_logic;
+   D_CTI_O  : out std_logic_vector(2 downto 0);
+   D_LOCK_O : out std_logic;
+   D_BTE_O  : out std_logic_vector(1 downto 0));
+end component;
+component lm32_top_full_debug is 
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
+port (
+ 
+  clk_i    : in  std_logic;
+  rst_i    : in  std_logic;
+  interrupt  : in  std_logic_vector(31 downto 0);
+  I_DAT_I  : in  std_logic_vector(31 downto 0);
+  I_ACK_I  : in  std_logic;
+  I_ERR_I  : in  std_logic;
+  I_RTY_I  : in  std_logic;
+   D_DAT_I  : in  std_logic_vector(31 downto 0);
+   D_ACK_I  : in  std_logic;
+   D_ERR_I  : in  std_logic;
+   D_RTY_I  : in  std_logic;
+   I_DAT_O  : out std_logic_vector(31 downto 0);
+   I_ADR_O  : out std_logic_vector(31 downto 0);
+   I_CYC_O  : out std_logic;
+   I_SEL_O  : out std_logic_vector(3 downto 0);
+   I_STB_O  : out std_logic;
+   I_WE_O   : out std_logic;
+   I_CTI_O  : out std_logic_vector(2 downto 0);
+   I_LOCK_O : out std_logic;
+   I_BTE_O  : out std_logic_vector(1 downto 0);
+   D_DAT_O  : out std_logic_vector(31 downto 0);
+   D_ADR_O  : out std_logic_vector(31 downto 0);
+   D_CYC_O  : out std_logic;
+   D_SEL_O  : out std_logic_vector(3 downto 0);
+   D_STB_O  : out std_logic;
+   D_WE_O   : out std_logic;
+   D_CTI_O  : out std_logic_vector(2 downto 0);
+   D_LOCK_O : out std_logic;
+   D_BTE_O  : out std_logic_vector(1 downto 0));
+end component;
+component lm32_top_wr_node is 
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
+port (
+ 
+  clk_i    : in  std_logic;
+  rst_i    : in  std_logic;
+  interrupt  : in  std_logic_vector(31 downto 0);
+  I_DAT_I  : in  std_logic_vector(31 downto 0);
+  I_ACK_I  : in  std_logic;
+  I_ERR_I  : in  std_logic;
+  I_RTY_I  : in  std_logic;
+   D_DAT_I  : in  std_logic_vector(31 downto 0);
+   D_ACK_I  : in  std_logic;
+   D_ERR_I  : in  std_logic;
+   D_RTY_I  : in  std_logic;
+   I_DAT_O  : out std_logic_vector(31 downto 0);
+   I_ADR_O  : out std_logic_vector(31 downto 0);
+   I_CYC_O  : out std_logic;
+   I_SEL_O  : out std_logic_vector(3 downto 0);
+   I_STB_O  : out std_logic;
+   I_WE_O   : out std_logic;
+   I_CTI_O  : out std_logic_vector(2 downto 0);
+   I_LOCK_O : out std_logic;
+   I_BTE_O  : out std_logic_vector(1 downto 0);
+   D_DAT_O  : out std_logic_vector(31 downto 0);
+   D_ADR_O  : out std_logic_vector(31 downto 0);
+   D_CYC_O  : out std_logic;
+   D_SEL_O  : out std_logic_vector(3 downto 0);
+   D_STB_O  : out std_logic;
+   D_WE_O   : out std_logic;
+   D_CTI_O  : out std_logic_vector(2 downto 0);
+   D_LOCK_O : out std_logic;
+   D_BTE_O  : out std_logic_vector(1 downto 0));
+end component;
+
+  function pick(first : boolean;
+                 a, b  : t_wishbone_address)
+      return t_wishbone_address is
+   begin
+      if first then
+         return a;
+      else
+         return b;
+      end if;
+   end pick;
+   
+   function b2l(val : boolean)
+      return std_logic is
+   begin
+      if val then 
+         return '1';
+      else
+         return '0';
+      end if;
+   end b2l;
+
+ function strip_undefined
+    (x           : std_logic_vector) return std_logic_vector is
+    variable tmp : std_logic_vector(x'left downto 0);
+  begin
+    for i  in 0 to x'left loop
+      if(x(i)='1') then
+        tmp(i) := '1';
+      else
+        tmp(i) := '0';
+      end if;
+    end loop;  -- i
+    return tmp;
+  end strip_undefined;
+   
+   constant dcache_burst_length : natural := f_eval_d_burst_length(g_profile);
+   constant icache_burst_length : natural := f_eval_i_burst_length(g_profile);
+   
+   -- Control pins from the LM32
+   signal I_ADR : t_wishbone_address;
+   signal D_ADR : t_wishbone_address;
+   signal I_CYC : std_logic;
+   signal D_CYC : std_logic;
+   signal I_CTI : t_wishbone_cycle_type;
+   signal D_CTI : t_wishbone_cycle_type;
+   -- We also watch the STALL lines from the v4 slaves
+   
+   -- Registered logic:
+   signal inst_was_busy : std_logic;
+   signal data_was_busy : std_logic;
+   signal inst_addr_reg : t_wishbone_address;
+   signal data_addr_reg : t_wishbone_address;
+   signal inst_remaining : natural range 0 to icache_burst_length;
+   signal data_remaining : natural range 0 to dcache_burst_length;
+   
+   -- Asynchronous logic:
+   signal I_STB_O : std_logic;
+   signal D_STB_O : std_logic;
+   signal rst:std_logic;
+begin
+		rst <= not rst_n_i;
+gen_profile_minimal: if (g_profile = "minimal") generate
+U_Wrapped_LM32: lm32_top_minimal
+
+generic map (
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
+port map(
+      clk_i	=> clk_sys_i,
+      rst_i	=> rst,
+      interrupt	=> irq_i,
+      -- Pass slave responses through unmodified
+      I_DAT_I	=> strip_undefined(iwb_i.DAT),
+      I_ACK_I	=> iwb_i.ACK,
+      I_ERR_I	=> iwb_i.ERR,
+      I_RTY_I	=> iwb_i.RTY,
+      D_DAT_I	=> strip_undefined(dwb_i.DAT),
+      D_ACK_I	=> dwb_i.ACK,
+      D_ERR_I	=> dwb_i.ERR,
+      D_RTY_I	=> dwb_i.RTY,
+      -- Writes can only happen as a single cycle
+      I_DAT_O	=> iwb_o.DAT,
+      D_DAT_O	=> dwb_o.DAT,
+      I_WE_O	=> iwb_o.WE,
+      D_WE_O	=> dwb_o.WE,
+      -- SEL /= 1111 only for single cycles
+      I_SEL_O	=> iwb_o.SEL,
+      D_SEL_O	=> dwb_o.SEL,
+      -- We can ignore BTE as we know it's always linear burst mode
+      I_BTE_O	=> open,
+      D_BTE_O	=> open,
+      -- Lock is never flagged by LM32. Besides, WBv4 locks intercon on CYC.
+      I_LOCK_O	=> open,
+      D_LOCK_O	=> open,
+      -- The LM32 has STB=CYC always
+      I_STB_O	=> open,
+      D_STB_O	=> open,
+      -- We monitor these pins to direct the adapter's logic
+      I_ADR_O	=> I_ADR,
+      I_CYC_O	=> I_CYC,
+      I_CTI_O	=> I_CTI,
+      D_ADR_O	=> D_ADR,
+      D_CYC_O	=> D_CYC,
+      D_CTI_O	=> D_CTI);
+end generate gen_profile_minimal;
+gen_profile_medium: if (g_profile = "medium") generate
+U_Wrapped_LM32: lm32_top_medium
+
+generic map (
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
+port map(
+      clk_i	=> clk_sys_i,
+      rst_i	=> rst,
+      interrupt	=> irq_i,
+      -- Pass slave responses through unmodified
+      I_DAT_I	=> strip_undefined(iwb_i.DAT),
+      I_ACK_I	=> iwb_i.ACK,
+      I_ERR_I	=> iwb_i.ERR,
+      I_RTY_I	=> iwb_i.RTY,
+      D_DAT_I	=> strip_undefined(dwb_i.DAT),
+      D_ACK_I	=> dwb_i.ACK,
+      D_ERR_I	=> dwb_i.ERR,
+      D_RTY_I	=> dwb_i.RTY,
+      -- Writes can only happen as a single cycle
+      I_DAT_O	=> iwb_o.DAT,
+      D_DAT_O	=> dwb_o.DAT,
+      I_WE_O	=> iwb_o.WE,
+      D_WE_O	=> dwb_o.WE,
+      -- SEL /= 1111 only for single cycles
+      I_SEL_O	=> iwb_o.SEL,
+      D_SEL_O	=> dwb_o.SEL,
+      -- We can ignore BTE as we know it's always linear burst mode
+      I_BTE_O	=> open,
+      D_BTE_O	=> open,
+      -- Lock is never flagged by LM32. Besides, WBv4 locks intercon on CYC.
+      I_LOCK_O	=> open,
+      D_LOCK_O	=> open,
+      -- The LM32 has STB=CYC always
+      I_STB_O	=> open,
+      D_STB_O	=> open,
+      -- We monitor these pins to direct the adapter's logic
+      I_ADR_O	=> I_ADR,
+      I_CYC_O	=> I_CYC,
+      I_CTI_O	=> I_CTI,
+      D_ADR_O	=> D_ADR,
+      D_CYC_O	=> D_CYC,
+      D_CTI_O	=> D_CTI);
+end generate gen_profile_medium;
+gen_profile_medium_icache: if (g_profile = "medium_icache") generate
+U_Wrapped_LM32: lm32_top_medium_icache
+
+generic map (
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
+port map(
+      clk_i	=> clk_sys_i,
+      rst_i	=> rst,
+      interrupt	=> irq_i,
+      -- Pass slave responses through unmodified
+      I_DAT_I	=> strip_undefined(iwb_i.DAT),
+      I_ACK_I	=> iwb_i.ACK,
+      I_ERR_I	=> iwb_i.ERR,
+      I_RTY_I	=> iwb_i.RTY,
+      D_DAT_I	=> strip_undefined(dwb_i.DAT),
+      D_ACK_I	=> dwb_i.ACK,
+      D_ERR_I	=> dwb_i.ERR,
+      D_RTY_I	=> dwb_i.RTY,
+      -- Writes can only happen as a single cycle
+      I_DAT_O	=> iwb_o.DAT,
+      D_DAT_O	=> dwb_o.DAT,
+      I_WE_O	=> iwb_o.WE,
+      D_WE_O	=> dwb_o.WE,
+      -- SEL /= 1111 only for single cycles
+      I_SEL_O	=> iwb_o.SEL,
+      D_SEL_O	=> dwb_o.SEL,
+      -- We can ignore BTE as we know it's always linear burst mode
+      I_BTE_O	=> open,
+      D_BTE_O	=> open,
+      -- Lock is never flagged by LM32. Besides, WBv4 locks intercon on CYC.
+      I_LOCK_O	=> open,
+      D_LOCK_O	=> open,
+      -- The LM32 has STB=CYC always
+      I_STB_O	=> open,
+      D_STB_O	=> open,
+      -- We monitor these pins to direct the adapter's logic
+      I_ADR_O	=> I_ADR,
+      I_CYC_O	=> I_CYC,
+      I_CTI_O	=> I_CTI,
+      D_ADR_O	=> D_ADR,
+      D_CYC_O	=> D_CYC,
+      D_CTI_O	=> D_CTI);
+end generate gen_profile_medium_icache;
+gen_profile_medium_debug: if (g_profile = "medium_debug") generate
+U_Wrapped_LM32: lm32_top_medium_debug
+
+generic map (
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
+port map(
+      clk_i	=> clk_sys_i,
+      rst_i	=> rst,
+      interrupt	=> irq_i,
+      -- Pass slave responses through unmodified
+      I_DAT_I	=> strip_undefined(iwb_i.DAT),
+      I_ACK_I	=> iwb_i.ACK,
+      I_ERR_I	=> iwb_i.ERR,
+      I_RTY_I	=> iwb_i.RTY,
+      D_DAT_I	=> strip_undefined(dwb_i.DAT),
+      D_ACK_I	=> dwb_i.ACK,
+      D_ERR_I	=> dwb_i.ERR,
+      D_RTY_I	=> dwb_i.RTY,
+      -- Writes can only happen as a single cycle
+      I_DAT_O	=> iwb_o.DAT,
+      D_DAT_O	=> dwb_o.DAT,
+      I_WE_O	=> iwb_o.WE,
+      D_WE_O	=> dwb_o.WE,
+      -- SEL /= 1111 only for single cycles
+      I_SEL_O	=> iwb_o.SEL,
+      D_SEL_O	=> dwb_o.SEL,
+      -- We can ignore BTE as we know it's always linear burst mode
+      I_BTE_O	=> open,
+      D_BTE_O	=> open,
+      -- Lock is never flagged by LM32. Besides, WBv4 locks intercon on CYC.
+      I_LOCK_O	=> open,
+      D_LOCK_O	=> open,
+      -- The LM32 has STB=CYC always
+      I_STB_O	=> open,
+      D_STB_O	=> open,
+      -- We monitor these pins to direct the adapter's logic
+      I_ADR_O	=> I_ADR,
+      I_CYC_O	=> I_CYC,
+      I_CTI_O	=> I_CTI,
+      D_ADR_O	=> D_ADR,
+      D_CYC_O	=> D_CYC,
+      D_CTI_O	=> D_CTI);
+end generate gen_profile_medium_debug;
+gen_profile_medium_icache_debug: if (g_profile = "medium_icache_debug") generate
+U_Wrapped_LM32: lm32_top_medium_icache_debug
+
+generic map (
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
+port map(
+      clk_i	=> clk_sys_i,
+      rst_i	=> rst,
+      interrupt	=> irq_i,
+      -- Pass slave responses through unmodified
+      I_DAT_I	=> strip_undefined(iwb_i.DAT),
+      I_ACK_I	=> iwb_i.ACK,
+      I_ERR_I	=> iwb_i.ERR,
+      I_RTY_I	=> iwb_i.RTY,
+      D_DAT_I	=> strip_undefined(dwb_i.DAT),
+      D_ACK_I	=> dwb_i.ACK,
+      D_ERR_I	=> dwb_i.ERR,
+      D_RTY_I	=> dwb_i.RTY,
+      -- Writes can only happen as a single cycle
+      I_DAT_O	=> iwb_o.DAT,
+      D_DAT_O	=> dwb_o.DAT,
+      I_WE_O	=> iwb_o.WE,
+      D_WE_O	=> dwb_o.WE,
+      -- SEL /= 1111 only for single cycles
+      I_SEL_O	=> iwb_o.SEL,
+      D_SEL_O	=> dwb_o.SEL,
+      -- We can ignore BTE as we know it's always linear burst mode
+      I_BTE_O	=> open,
+      D_BTE_O	=> open,
+      -- Lock is never flagged by LM32. Besides, WBv4 locks intercon on CYC.
+      I_LOCK_O	=> open,
+      D_LOCK_O	=> open,
+      -- The LM32 has STB=CYC always
+      I_STB_O	=> open,
+      D_STB_O	=> open,
+      -- We monitor these pins to direct the adapter's logic
+      I_ADR_O	=> I_ADR,
+      I_CYC_O	=> I_CYC,
+      I_CTI_O	=> I_CTI,
+      D_ADR_O	=> D_ADR,
+      D_CYC_O	=> D_CYC,
+      D_CTI_O	=> D_CTI);
+end generate gen_profile_medium_icache_debug;
+gen_profile_full: if (g_profile = "full") generate
+U_Wrapped_LM32: lm32_top_full
+
+generic map (
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
+port map(
+      clk_i	=> clk_sys_i,
+      rst_i	=> rst,
+      interrupt	=> irq_i,
+      -- Pass slave responses through unmodified
+      I_DAT_I	=> strip_undefined(iwb_i.DAT),
+      I_ACK_I	=> iwb_i.ACK,
+      I_ERR_I	=> iwb_i.ERR,
+      I_RTY_I	=> iwb_i.RTY,
+      D_DAT_I	=> strip_undefined(dwb_i.DAT),
+      D_ACK_I	=> dwb_i.ACK,
+      D_ERR_I	=> dwb_i.ERR,
+      D_RTY_I	=> dwb_i.RTY,
+      -- Writes can only happen as a single cycle
+      I_DAT_O	=> iwb_o.DAT,
+      D_DAT_O	=> dwb_o.DAT,
+      I_WE_O	=> iwb_o.WE,
+      D_WE_O	=> dwb_o.WE,
+      -- SEL /= 1111 only for single cycles
+      I_SEL_O	=> iwb_o.SEL,
+      D_SEL_O	=> dwb_o.SEL,
+      -- We can ignore BTE as we know it's always linear burst mode
+      I_BTE_O	=> open,
+      D_BTE_O	=> open,
+      -- Lock is never flagged by LM32. Besides, WBv4 locks intercon on CYC.
+      I_LOCK_O	=> open,
+      D_LOCK_O	=> open,
+      -- The LM32 has STB=CYC always
+      I_STB_O	=> open,
+      D_STB_O	=> open,
+      -- We monitor these pins to direct the adapter's logic
+      I_ADR_O	=> I_ADR,
+      I_CYC_O	=> I_CYC,
+      I_CTI_O	=> I_CTI,
+      D_ADR_O	=> D_ADR,
+      D_CYC_O	=> D_CYC,
+      D_CTI_O	=> D_CTI);
+end generate gen_profile_full;
+gen_profile_full_debug: if (g_profile = "full_debug") generate
+U_Wrapped_LM32: lm32_top_full_debug
+
+generic map (
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
+port map(
+      clk_i	=> clk_sys_i,
+      rst_i	=> rst,
+      interrupt	=> irq_i,
+      -- Pass slave responses through unmodified
+      I_DAT_I	=> strip_undefined(iwb_i.DAT),
+      I_ACK_I	=> iwb_i.ACK,
+      I_ERR_I	=> iwb_i.ERR,
+      I_RTY_I	=> iwb_i.RTY,
+      D_DAT_I	=> strip_undefined(dwb_i.DAT),
+      D_ACK_I	=> dwb_i.ACK,
+      D_ERR_I	=> dwb_i.ERR,
+      D_RTY_I	=> dwb_i.RTY,
+      -- Writes can only happen as a single cycle
+      I_DAT_O	=> iwb_o.DAT,
+      D_DAT_O	=> dwb_o.DAT,
+      I_WE_O	=> iwb_o.WE,
+      D_WE_O	=> dwb_o.WE,
+      -- SEL /= 1111 only for single cycles
+      I_SEL_O	=> iwb_o.SEL,
+      D_SEL_O	=> dwb_o.SEL,
+      -- We can ignore BTE as we know it's always linear burst mode
+      I_BTE_O	=> open,
+      D_BTE_O	=> open,
+      -- Lock is never flagged by LM32. Besides, WBv4 locks intercon on CYC.
+      I_LOCK_O	=> open,
+      D_LOCK_O	=> open,
+      -- The LM32 has STB=CYC always
+      I_STB_O	=> open,
+      D_STB_O	=> open,
+      -- We monitor these pins to direct the adapter's logic
+      I_ADR_O	=> I_ADR,
+      I_CYC_O	=> I_CYC,
+      I_CTI_O	=> I_CTI,
+      D_ADR_O	=> D_ADR,
+      D_CYC_O	=> D_CYC,
+      D_CTI_O	=> D_CTI);
+end generate gen_profile_full_debug;
+gen_profile_wr_node: if (g_profile = "wr_node") generate
+U_Wrapped_LM32: lm32_top_wr_node
+
+generic map (
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
+port map(
+      clk_i	=> clk_sys_i,
+      rst_i	=> rst,
+      interrupt	=> irq_i,
+      -- Pass slave responses through unmodified
+      I_DAT_I	=> strip_undefined(iwb_i.DAT),
+      I_ACK_I	=> iwb_i.ACK,
+      I_ERR_I	=> iwb_i.ERR,
+      I_RTY_I	=> iwb_i.RTY,
+      D_DAT_I	=> strip_undefined(dwb_i.DAT),
+      D_ACK_I	=> dwb_i.ACK,
+      D_ERR_I	=> dwb_i.ERR,
+      D_RTY_I	=> dwb_i.RTY,
+      -- Writes can only happen as a single cycle
+      I_DAT_O	=> iwb_o.DAT,
+      D_DAT_O	=> dwb_o.DAT,
+      I_WE_O	=> iwb_o.WE,
+      D_WE_O	=> dwb_o.WE,
+      -- SEL /= 1111 only for single cycles
+      I_SEL_O	=> iwb_o.SEL,
+      D_SEL_O	=> dwb_o.SEL,
+      -- We can ignore BTE as we know it's always linear burst mode
+      I_BTE_O	=> open,
+      D_BTE_O	=> open,
+      -- Lock is never flagged by LM32. Besides, WBv4 locks intercon on CYC.
+      I_LOCK_O	=> open,
+      D_LOCK_O	=> open,
+      -- The LM32 has STB=CYC always
+      I_STB_O	=> open,
+      D_STB_O	=> open,
+      -- We monitor these pins to direct the adapter's logic
+      I_ADR_O	=> I_ADR,
+      I_CYC_O	=> I_CYC,
+      I_CTI_O	=> I_CTI,
+      D_ADR_O	=> D_ADR,
+      D_CYC_O	=> D_CYC,
+      D_CTI_O	=> D_CTI);
+end generate gen_profile_wr_node;
+
+   -- Cycle durations always match in our adapter
+   iwb_o.CYC <= I_CYC;
+   dwb_o.CYC <= D_CYC;
+   
+   iwb_o.STB <= I_STB_O;
+   dwb_o.STB <= D_STB_O;
+   
+   I_STB_O <= (I_CYC and not inst_was_busy) or b2l(inst_remaining /= 0);
+   inst : process(clk_sys_i)
+      variable inst_addr : t_wishbone_address;
+      variable inst_length : natural;
+   begin
+      if rising_edge(clk_sys_i) then
+         if rst = '1' then
+            inst_was_busy <= '0';
+            inst_remaining <= 0;
+            inst_addr_reg <= (others => '0');
+         else
+            inst_was_busy <= I_CYC;
+            
+            -- Is this the start of a new WB cycle?
+            if I_CYC = '1' and inst_was_busy = '0' then
+               inst_addr := I_ADR;
+               if I_CTI = "010" then
+                  inst_length := icache_burst_length;
+               else
+                  inst_length := 1;
+               end if;
+            else
+               inst_addr := inst_addr_reg;
+               inst_length := inst_remaining;
+            end if;
+            
+            -- When stalled, we cannot advance the address
+            if iwb_i.STALL = '0' and I_STB_O = '1' then
+               inst_addr_reg  <= std_logic_vector(unsigned(inst_addr) + 4);
+               inst_remaining <= inst_length - 1;
+            else
+               inst_addr_reg  <= inst_addr;
+               inst_remaining <= inst_length;
+            end if;
+         end if;
+      end if;
+   end process;
+   
+   D_STB_O <= (D_CYC and not data_was_busy) or b2l(data_remaining /= 0);
+   data : process(clk_sys_i)
+      variable data_addr : t_wishbone_address;
+      variable data_length : natural;
+   begin
+      if rising_edge(clk_sys_i) then
+         if rst = '1' then
+            data_was_busy <= '0';
+            data_remaining <= 0;
+            data_addr_reg <= (others => '0');
+         else
+            data_was_busy <= D_CYC;
+            
+            -- Is this the start of a new WB cycle?
+            if D_CYC = '1' and data_was_busy = '0' then
+               data_addr := D_ADR;
+               if D_CTI = "010" then
+                  data_length := dcache_burst_length;
+               else
+                  data_length := 1;
+               end if;
+            else
+               data_addr := data_addr_reg;
+               data_length := data_remaining;
+            end if;
+            
+            -- When stalled, we cannot advance the address
+            if dwb_i.STALL = '0' and D_STB_O = '1' then
+               data_addr_reg  <= std_logic_vector(unsigned(data_addr) + 4);
+               data_remaining <= data_length - 1;
+            else
+               data_addr_reg  <= data_addr;
+               data_remaining <= data_length;
+            end if;
+         end if;
+      end if;
+   end process;
+   
+   -- The first request uses the WBv3 address, thereafter an incrementing one.
+   dwb_o.ADR <= pick(data_was_busy = '0', D_ADR, data_addr_reg);
+   iwb_o.ADR <= pick(inst_was_busy = '0', I_ADR, inst_addr_reg);
+	end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
new file mode 100644
index 000000000..1821c3f6d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
@@ -0,0 +1,20 @@
+module jtag_tap(
+  output tck,
+  output tdi,
+  input tdo,
+  output capture,
+  output shift,
+  output e1dr,
+  output update,
+  output reset
+);
+
+	assign tck = 1;
+	assign tdi = 1;
+	assign capture = 0;
+	assign shift = 0;
+	assign e1dr = 0;
+	assign update = 0;
+	assign reset = 0;
+
+endmodule
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
new file mode 100644
index 000000000..ea3e0cb0d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
@@ -0,0 +1,119 @@
+// =============================================================================
+//                           COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court                            408-826-6000 (other locations)
+// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
+// U.S.A                                   email: techsupport@latticesemi.com
+// =============================================================================/
+//                         FILE DETAILS
+// Project          : LatticeMico32
+// File             : lm32_multiplier.v
+// Title            : Pipelined multiplier.
+// Dependencies     : lm32_include.v
+// Version          : 6.1.17
+//                  : Initial Release
+// Version          : 7.0SP2, 3.0
+//                  : No Change
+// Version          : 3.1
+//                  : No Change
+// =============================================================================
+                  
+`include "../../src/lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_multiplier (
+    // ----- Inputs -----
+    clk_i,
+    rst_i,
+    stall_x,
+    stall_m,
+    operand_0,
+    operand_1,
+    // ----- Ouputs -----
+    result
+    );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i;                            // Clock 
+input rst_i;                            // Reset
+input stall_x;                          // Stall instruction in X stage
+input stall_m;                          // Stall instruction in M stage
+input [`LM32_WORD_RNG] operand_0;     	// Muliplicand
+input [`LM32_WORD_RNG] operand_1;     	// Multiplier
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [`LM32_WORD_RNG] result;       	// Product of multiplication
+wire   [`LM32_WORD_RNG] result;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers 
+/////////////////////////////////////////////////////
+
+// Divide multiplicands into high and low
+`define HALF_WORD_WIDTH (`LM32_WORD_WIDTH/2)
+`define HALF_WORD_RNG (`HALF_WORD_WIDTH-1):0
+
+// Result = c+d+e = a*b
+reg [`HALF_WORD_RNG] a0, a1, b0, b1;
+reg [`HALF_WORD_RNG] c0, c1;
+reg [`HALF_WORD_RNG] d1, e1;
+reg [`HALF_WORD_RNG] result0, result1;
+
+assign result = {result1, result0};
+
+/////////////////////////////////////////////////////
+// Sequential logic
+/////////////////////////////////////////////////////
+
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+    if (rst_i == `TRUE)
+    begin
+        a0 <= {`HALF_WORD_WIDTH{1'b0}};
+        a1 <= {`HALF_WORD_WIDTH{1'b0}};
+        b0 <= {`HALF_WORD_WIDTH{1'b0}};
+        b1 <= {`HALF_WORD_WIDTH{1'b0}};
+		  c0 <= {`HALF_WORD_WIDTH{1'b0}};
+		  c1 <= {`HALF_WORD_WIDTH{1'b0}};
+		  d1 <= {`HALF_WORD_WIDTH{1'b0}};
+		  e1 <= {`HALF_WORD_WIDTH{1'b0}};
+        result0 <= {`HALF_WORD_WIDTH{1'b0}};
+        result1 <= {`HALF_WORD_WIDTH{1'b0}};
+    end
+    else
+    begin
+        if (stall_x == `FALSE)
+        begin    
+            {a1, a0} <= operand_0;
+            {b1, b0} <= operand_1;
+        end
+        if (stall_m == `FALSE)
+		  begin
+            {c1, c0} <= a0 * b0;
+				d1 <= a0 * b1;
+				e1 <= a1 * b0;
+		  end
+		  
+        result0 <= c0;
+		  result1 <= c1 + d1 + e1;
+    end
+end
+
+endmodule
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
new file mode 100644
index 000000000..78dbf0293
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
@@ -0,0 +1,66 @@
+// Modified by GSI to use simple positive edge clocking and the JTAG capture state
+
+module jtag_cores (
+    input [7:0] reg_d,
+    input [2:0] reg_addr_d,
+    output reg_update,
+    output [7:0] reg_q,
+    output [2:0] reg_addr_q,
+    output jtck,
+    output jrstn
+);
+
+wire tck;
+wire tdi;
+wire tdo;
+wire capture;
+wire shift;
+wire update;
+wire e1dr;
+wire reset;
+
+jtag_tap jtag_tap (
+	.tck(tck),
+	.tdi(tdi),
+	.tdo(tdo),
+	.capture(capture),
+	.shift(shift),
+	.e1dr(e1dr),
+	.update(update),
+	.reset(reset)
+);
+
+reg [10:0] jtag_shift;
+reg [10:0] jtag_latched;
+
+always @(posedge tck)
+begin
+	if(reset)
+		jtag_shift <= 11'b0;
+	else begin
+		if (shift)
+			jtag_shift <= {tdi, jtag_shift[10:1]};
+		else if (capture)
+			jtag_shift <= {reg_d, reg_addr_d};
+	end
+end
+
+assign tdo = jtag_shift[0];
+
+always @(posedge tck)
+begin
+	if(reset)
+		jtag_latched <= 11'b0;
+	else begin
+	   if (e1dr)
+		   jtag_latched <= jtag_shift;
+	end
+end
+
+assign reg_update = update;
+assign reg_q = jtag_latched[10:3];
+assign reg_addr_q = jtag_latched[2:0];
+assign jtck = tck;
+assign jrstn = ~reset;
+
+endmodule
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
new file mode 100644
index 000000000..b0d2d79ce
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
@@ -0,0 +1,115 @@
+// =============================================================================
+//                           COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court                            408-826-6000 (other locations)
+// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
+// U.S.A                                   email: techsupport@latticesemi.com
+// ============================================================================/
+//                         FILE DETAILS
+// Project          : LatticeMico32
+// File             : lm32_adder.v
+// Title            : Integer adder / subtractor with comparison flag generation 
+// Dependencies     : lm32_include.v
+// Version          : 6.1.17
+//                  : Initial Release
+// Version          : 7.0SP2, 3.0
+//                  : No Change
+// Version          : 3.1
+//                  : No Change
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_adder (
+    // ----- Inputs -------
+    adder_op_x,
+    adder_op_x_n,
+    operand_0_x,
+    operand_1_x,
+    // ----- Outputs -------
+    adder_result_x,
+    adder_carry_n_x,
+    adder_overflow_x
+    );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input adder_op_x;                                       // Operating to perform, 0 for addition, 1 for subtraction
+input adder_op_x_n;                                     // Inverted version of adder_op_x
+input [`LM32_WORD_RNG] operand_0_x;                     // Operand to add, or subtract from
+input [`LM32_WORD_RNG] operand_1_x;                     // Opearnd to add, or subtract by
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [`LM32_WORD_RNG] adder_result_x;                 // Result of addition or subtraction
+wire   [`LM32_WORD_RNG] adder_result_x;
+output adder_carry_n_x;                                 // Inverted carry
+wire   adder_carry_n_x;
+output adder_overflow_x;                                // Indicates if overflow occured, only valid for subtractions
+reg    adder_overflow_x;
+    
+/////////////////////////////////////////////////////
+// Internal nets and registers 
+/////////////////////////////////////////////////////
+
+wire a_sign;                                            // Sign (i.e. positive or negative) of operand 0
+wire b_sign;                                            // Sign of operand 1
+wire result_sign;                                       // Sign of result
+
+/////////////////////////////////////////////////////
+// Instantiations 
+/////////////////////////////////////////////////////
+
+lm32_addsub addsub (
+    // ----- Inputs -----
+    .DataA          (operand_0_x), 
+    .DataB          (operand_1_x), 
+    .Cin            (adder_op_x), 
+    .Add_Sub        (adder_op_x_n), 
+    // ----- Ouputs -----
+    .Result         (adder_result_x), 
+    .Cout           (adder_carry_n_x)
+    );
+
+/////////////////////////////////////////////////////
+// Combinational Logic
+/////////////////////////////////////////////////////
+
+// Extract signs of operands and result
+
+assign a_sign = operand_0_x[`LM32_WORD_WIDTH-1];
+assign b_sign = operand_1_x[`LM32_WORD_WIDTH-1];
+assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1];
+
+// Determine whether an overflow occured when performing a subtraction
+
+always @(*)
+begin    
+    //  +ve - -ve = -ve -> overflow
+    //  -ve - +ve = +ve -> overflow
+    if  (   (!a_sign & b_sign & result_sign)
+         || (a_sign & !b_sign & !result_sign)
+        )
+        adder_overflow_x = `TRUE;
+    else
+        adder_overflow_x = `FALSE;
+end
+    
+endmodule
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
new file mode 100644
index 000000000..8861cbe2d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
@@ -0,0 +1,74 @@
+// =============================================================================
+//                           COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court                            408-826-6000 (other locations)
+// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
+// U.S.A                                   email: techsupport@latticesemi.com
+// =============================================================================/
+//                         FILE DETAILS
+// Project          : LatticeMico32
+// File             : lm32_addsub.v
+// Title            : PMI adder/subtractor.
+// Version          : 6.1.17
+//                  : Initial Release
+// Version          : 7.0SP2, 3.0
+//                  : No Change
+// Version          : 3.1
+//                  : No Change
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_addsub (
+    // ----- Inputs -------
+    DataA, 
+    DataB, 
+    Cin, 
+    Add_Sub, 
+    // ----- Outputs -------
+    Result, 
+    Cout
+    );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input [31:0] DataA;
+input [31:0] DataB;
+input Cin;
+input Add_Sub;
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [31:0] Result;
+wire   [31:0] Result;
+output Cout;
+wire   Cout;
+
+/////////////////////////////////////////////////////
+// Instantiations
+///////////////////////////////////////////////////// 
+
+// Modified for Milkymist: removed non-portable instantiated block
+	     wire [32:0] tmp_addResult = DataA + DataB + Cin;
+	     wire [32:0] tmp_subResult = DataA - DataB - !Cin;   
+   
+	     assign  Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0];
+	     assign  Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32];
+
+endmodule
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
new file mode 100644
index 000000000..7f416bb95
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
@@ -0,0 +1,46 @@
+-- Work-alike to lm32_dp_ram.v, but using generic_simple_dpram
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.genram_pkg.all;
+
+entity lm32_dp_ram is
+  generic(
+    addr_width : natural := 32;
+    addr_depth : natural := 1024;
+    data_width : natural := 8);
+  port(
+    clk_i   : in std_logic;
+    rst_i   : in std_logic;
+    we_i    : in std_logic;
+    waddr_i : in  std_logic_vector(addr_width-1 downto 0);
+    wdata_i : in  std_logic_vector(data_width-1 downto 0);
+    raddr_i : in  std_logic_vector(addr_width-1 downto 0);
+    rdata_o : out std_logic_vector(data_width-1 downto 0));
+end lm32_dp_ram;
+
+architecture syn of lm32_dp_ram is
+
+  constant c_addr_width : natural := f_log2_size(addr_depth);
+
+begin
+
+  ram : generic_simple_dpram
+    generic map(
+      g_data_width               => data_width,
+      g_size                     => addr_depth,
+      g_with_byte_enable         => false,
+      g_addr_conflict_resolution => "write_first",
+      g_dual_clock               => false)
+    port map(
+      clka_i => clk_i,
+      wea_i  => we_i,
+      aa_i   => waddr_i(c_addr_width-1 downto 0),
+      da_i   => wdata_i,
+      clkb_i => clk_i,
+      ab_i   => raddr_i(c_addr_width-1 downto 0),
+      qb_o   => rdata_o);
+  
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
new file mode 100644
index 000000000..5adff9d86
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
@@ -0,0 +1,320 @@
+// =============================================================================
+//                           COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court                            408-826-6000 (other locations)
+// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
+// U.S.A                                   email: techsupport@latticesemi.com
+// =============================================================================/
+//                         FILE DETAILS
+// Project          : LatticeMico32
+// File             : lm32_include.v
+// Title            : CPU global macros
+// Version          : 6.1.17
+//                  : Initial Release
+// Version          : 7.0SP2, 3.0
+//                  : No Change
+// Version          : 3.1
+//                  : No Change
+// Version          : 3.2
+//                  : No Change
+// Version          : 3.3
+//                  : Support for extended configuration register
+// =============================================================================
+
+`ifdef LM32_INCLUDE_V
+`else
+`define LM32_INCLUDE_V
+
+// Configuration options
+//`include "system_conf.v"
+
+`ifdef TRUE
+`else
+`define TRUE    1'b1
+`define FALSE   1'b0
+`define TRUE_N  1'b0
+`define FALSE_N 1'b1
+`endif
+
+// Wishbone configuration
+`ifndef CFG_IRAM_ENABLED
+`define CFG_IWB_ENABLED
+`endif
+
+`define CFG_DWB_ENABLED
+
+// Data-path width
+`define LM32_WORD_WIDTH                 32
+`define LM32_WORD_RNG                   (`LM32_WORD_WIDTH-1):0
+`define LM32_SHIFT_WIDTH                5
+`define LM32_SHIFT_RNG                  (`LM32_SHIFT_WIDTH-1):0
+`define LM32_BYTE_SELECT_WIDTH          4
+`define LM32_BYTE_SELECT_RNG            (`LM32_BYTE_SELECT_WIDTH-1):0
+
+// Register file size
+`define LM32_REGISTERS                  32
+`define LM32_REG_IDX_WIDTH              5
+`define LM32_REG_IDX_RNG                (`LM32_REG_IDX_WIDTH-1):0
+
+// Standard register numbers
+`define LM32_RA_REG                     `LM32_REG_IDX_WIDTH'd29
+`define LM32_EA_REG                     `LM32_REG_IDX_WIDTH'd30
+`define LM32_BA_REG                     `LM32_REG_IDX_WIDTH'd31
+
+// Range of Program Counter. Two LSBs are always 0. 
+`ifdef CFG_ICACHE_ENABLED
+`define LM32_PC_WIDTH                   (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2)
+`else
+`ifdef CFG_IWB_ENABLED
+`define LM32_PC_WIDTH                   (`LM32_WORD_WIDTH-2)
+`else
+`define LM32_IRAM_ADDRESS_WIDTH 32
+`define LM32_PC_WIDTH                   (`LM32_IRAM_ADDRESS_WIDTH-2)
+`endif
+`endif
+`define LM32_PC_RNG                     (`LM32_PC_WIDTH+2-1):2
+
+// Range of an instruction
+`define LM32_INSTRUCTION_WIDTH          32
+`define LM32_INSTRUCTION_RNG            (`LM32_INSTRUCTION_WIDTH-1):0
+
+// Adder operation
+`define LM32_ADDER_OP_ADD               1'b0
+`define LM32_ADDER_OP_SUBTRACT          1'b1
+
+// Shift direction
+`define LM32_SHIFT_OP_RIGHT             1'b0
+`define LM32_SHIFT_OP_LEFT              1'b1
+
+// Derive macro that indicates whether we have single-stepping or not
+`ifdef CFG_ROM_DEBUG_ENABLED
+`define LM32_SINGLE_STEP_ENABLED
+`else
+`ifdef CFG_HW_DEBUG_ENABLED
+`define LM32_SINGLE_STEP_ENABLED
+`endif
+`endif
+
+// Derive macro that indicates whether JTAG interface is required
+`ifdef CFG_JTAG_UART_ENABLED
+`define LM32_JTAG_ENABLED
+`else
+`ifdef CFG_DEBUG_ENABLED
+`define LM32_JTAG_ENABLED
+`else
+`endif
+`endif
+
+// Derive macro that indicates whether we have a barrel-shifter or not
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+`define LM32_BARREL_SHIFT_ENABLED
+`else // CFG_PL_BARREL_SHIFT_ENABLED
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+`define LM32_BARREL_SHIFT_ENABLED
+`else
+`define LM32_NO_BARREL_SHIFT
+`endif
+`endif // CFG_PL_BARREL_SHIFT_ENABLED
+
+// Derive macro that indicates whether we have a multiplier or not
+`ifdef CFG_PL_MULTIPLY_ENABLED
+`define LM32_MULTIPLY_ENABLED
+`else
+`ifdef CFG_MC_MULTIPLY_ENABLED
+`define LM32_MULTIPLY_ENABLED
+`endif
+`endif
+
+// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
+`ifdef CFG_MC_DIVIDE_ENABLED
+`define LM32_MC_ARITHMETIC_ENABLED
+`endif
+`ifdef CFG_MC_MULTIPLY_ENABLED
+`define LM32_MC_ARITHMETIC_ENABLED
+`endif
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+`define LM32_MC_ARITHMETIC_ENABLED
+`endif
+
+// Derive macro that indicates if we are using an EBR register file
+`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
+`define LM32_EBR_REGISTER_FILE
+`endif
+`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
+`define LM32_EBR_REGISTER_FILE
+`endif
+
+// Revision number
+`define LM32_REVISION                   6'h02
+
+// Logical operations - Function encoded directly in instruction
+`define LM32_LOGIC_OP_RNG               3:0
+
+// Conditions for conditional branches
+`define LM32_CONDITION_WIDTH            3
+`define LM32_CONDITION_RNG              (`LM32_CONDITION_WIDTH-1):0
+`define LM32_CONDITION_E                3'b001
+`define LM32_CONDITION_G                3'b010
+`define LM32_CONDITION_GE               3'b011
+`define LM32_CONDITION_GEU              3'b100
+`define LM32_CONDITION_GU               3'b101
+`define LM32_CONDITION_NE               3'b111
+`define LM32_CONDITION_U1               3'b000
+`define LM32_CONDITION_U2               3'b110
+
+// Size of load or store instruction - Encoding corresponds to opcode
+`define LM32_SIZE_WIDTH                 2
+`define LM32_SIZE_RNG                   1:0
+`define LM32_SIZE_BYTE                  2'b00
+`define LM32_SIZE_HWORD                 2'b11
+`define LM32_SIZE_WORD                  2'b10
+`define LM32_ADDRESS_LSBS_WIDTH         2
+
+// Width and range of a CSR index
+`ifdef CFG_DEBUG_ENABLED
+`define LM32_CSR_WIDTH                  5
+`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
+`else
+`ifdef CFG_JTAG_ENABLED
+`define LM32_CSR_WIDTH                  4
+`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
+`else
+`define LM32_CSR_WIDTH                  4 // CFG2 is "a"
+`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
+`endif
+`endif
+
+// CSR indices
+`define LM32_CSR_IE                     `LM32_CSR_WIDTH'h0
+`define LM32_CSR_IM                     `LM32_CSR_WIDTH'h1
+`define LM32_CSR_IP                     `LM32_CSR_WIDTH'h2
+`define LM32_CSR_ICC                    `LM32_CSR_WIDTH'h3
+`define LM32_CSR_DCC                    `LM32_CSR_WIDTH'h4
+`define LM32_CSR_CC                     `LM32_CSR_WIDTH'h5
+`define LM32_CSR_CFG                    `LM32_CSR_WIDTH'h6
+`define LM32_CSR_EBA                    `LM32_CSR_WIDTH'h7
+`ifdef CFG_DEBUG_ENABLED
+`define LM32_CSR_DC                     `LM32_CSR_WIDTH'h8
+`define LM32_CSR_DEBA                   `LM32_CSR_WIDTH'h9
+`endif
+`define LM32_CSR_CFG2                   `LM32_CSR_WIDTH'ha
+`define LM32_CSR_SDB                    `LM32_CSR_WIDTH'hb
+`define LM32_CSR_ERR_ADDR               `LM32_CSR_WIDTH'hc
+`ifdef CFG_JTAG_ENABLED
+`define LM32_CSR_JTX                    `LM32_CSR_WIDTH'he
+`define LM32_CSR_JRX                    `LM32_CSR_WIDTH'hf
+`endif
+`ifdef CFG_DEBUG_ENABLED
+`define LM32_CSR_BP0                    `LM32_CSR_WIDTH'h10
+`define LM32_CSR_BP1                    `LM32_CSR_WIDTH'h11
+`define LM32_CSR_BP2                    `LM32_CSR_WIDTH'h12
+`define LM32_CSR_BP3                    `LM32_CSR_WIDTH'h13
+`define LM32_CSR_WP0                    `LM32_CSR_WIDTH'h18
+`define LM32_CSR_WP1                    `LM32_CSR_WIDTH'h19
+`define LM32_CSR_WP2                    `LM32_CSR_WIDTH'h1a
+`define LM32_CSR_WP3                    `LM32_CSR_WIDTH'h1b
+`endif 
+
+// Values for WPC CSR
+`define LM32_WPC_C_RNG                  1:0
+`define LM32_WPC_C_DISABLED             2'b00
+`define LM32_WPC_C_READ                 2'b01
+`define LM32_WPC_C_WRITE                2'b10
+`define LM32_WPC_C_READ_WRITE           2'b11
+
+// Exception IDs
+`define LM32_EID_WIDTH                  3
+`define LM32_EID_RNG                    (`LM32_EID_WIDTH-1):0
+`define LM32_EID_RESET                  3'h0
+`define LM32_EID_BREAKPOINT             3'd1
+`define LM32_EID_INST_BUS_ERROR         3'h2
+`define LM32_EID_WATCHPOINT             3'd3
+`define LM32_EID_DATA_BUS_ERROR         3'h4
+`define LM32_EID_DIVIDE_BY_ZERO         3'h5
+`define LM32_EID_INTERRUPT              3'h6
+`define LM32_EID_SCALL                  3'h7
+
+// Pipeline result selection mux controls
+
+`define LM32_D_RESULT_SEL_0_RNG          0:0
+`define LM32_D_RESULT_SEL_0_REG_0        1'b0
+`define LM32_D_RESULT_SEL_0_NEXT_PC      1'b1
+
+`define LM32_D_RESULT_SEL_1_RNG          1:0
+`define LM32_D_RESULT_SEL_1_ZERO         2'b00
+`define LM32_D_RESULT_SEL_1_REG_1        2'b01
+`define LM32_D_RESULT_SEL_1_IMMEDIATE    2'b10
+
+`define LM32_USER_OPCODE_WIDTH           11
+`define LM32_USER_OPCODE_RNG             (`LM32_USER_OPCODE_WIDTH-1):0
+
+// Derive a macro to indicate if either of the caches are implemented
+`ifdef CFG_ICACHE_ENABLED
+`define LM32_CACHE_ENABLED
+`else
+`ifdef CFG_DCACHE_ENABLED
+`define LM32_CACHE_ENABLED
+`endif
+`endif
+
+/////////////////////////////////////////////////////
+// Interrupts
+/////////////////////////////////////////////////////
+
+// Currently this is fixed to 32 and should not be changed
+`define CFG_INTERRUPTS                  32
+`define LM32_INTERRUPT_WIDTH            `CFG_INTERRUPTS
+`define LM32_INTERRUPT_RNG              (`LM32_INTERRUPT_WIDTH-1):0
+
+/////////////////////////////////////////////////////
+// General
+/////////////////////////////////////////////////////
+
+// Sub-word range types
+`define LM32_BYTE_WIDTH                 8
+`define LM32_BYTE_RNG                   7:0
+`define LM32_HWORD_WIDTH                16
+`define LM32_HWORD_RNG                  15:0
+
+// Word sub-byte indicies
+`define LM32_BYTE_0_RNG                  7:0
+`define LM32_BYTE_1_RNG                  15:8
+`define LM32_BYTE_2_RNG                  23:16
+`define LM32_BYTE_3_RNG                  31:24
+
+// Word sub-halfword indices
+`define LM32_HWORD_0_RNG                 15:0
+`define LM32_HWORD_1_RNG                 31:16
+
+// Use a synchronous reset
+`define CFG_RESET_SENSITIVITY
+
+// Wishbone defines 
+// Refer to Wishbone System-on-Chip Interconnection Architecture
+// These should probably be moved to a Wishbone common file
+
+// Wishbone cycle types
+`define LM32_CTYPE_WIDTH                3
+`define LM32_CTYPE_RNG                  (`LM32_CTYPE_WIDTH-1):0
+`define LM32_CTYPE_CLASSIC              3'b000
+`define LM32_CTYPE_CONSTANT             3'b001
+`define LM32_CTYPE_INCREMENTING         3'b010
+`define LM32_CTYPE_END                  3'b111
+
+// Wishbone burst types
+`define LM32_BTYPE_WIDTH                2
+`define LM32_BTYPE_RNG                  (`LM32_BTYPE_WIDTH-1):0
+`define LM32_BTYPE_LINEAR               2'b00
+`define LM32_BTYPE_4_BEAT               2'b01
+`define LM32_BTYPE_8_BEAT               2'b10
+`define LM32_BTYPE_16_BEAT              2'b11
+
+`endif
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
new file mode 100644
index 000000000..af1b752be
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
@@ -0,0 +1,76 @@
+// =============================================================================
+//                           COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court                            408-826-6000 (other locations)
+// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
+// U.S.A                                   email: techsupport@latticesemi.com
+// =============================================================================/
+//                         FILE DETAILS
+// Project          : LatticeMico32
+// File             : lm32_logic_op.v
+// Title            : Logic operations (and / or / not etc)
+// Dependencies     : lm32_include.v
+// Version          : 6.1.17
+//                  : Initial Release
+// Version          : 7.0SP2, 3.0
+//                  : No Change
+// Version          : 3.1
+//                  : No Change
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_logic_op (
+    // ----- Inputs -------
+    logic_op_x,
+    operand_0_x,
+    operand_1_x,
+    // ----- Outputs -------
+    logic_result_x
+    );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input [`LM32_LOGIC_OP_RNG] logic_op_x;
+input [`LM32_WORD_RNG] operand_0_x;
+input [`LM32_WORD_RNG] operand_1_x;
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [`LM32_WORD_RNG] logic_result_x;
+reg    [`LM32_WORD_RNG] logic_result_x;
+    
+/////////////////////////////////////////////////////
+// Internal nets and registers 
+/////////////////////////////////////////////////////
+
+integer logic_idx;
+
+/////////////////////////////////////////////////////
+// Combinational Logic
+/////////////////////////////////////////////////////
+
+always @(*)
+begin
+    for(logic_idx = 0; logic_idx < `LM32_WORD_WIDTH; logic_idx = logic_idx + 1)
+        logic_result_x[logic_idx] = logic_op_x[{operand_1_x[logic_idx], operand_0_x[logic_idx]}];
+end
+    
+endmodule
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
new file mode 100644
index 000000000..e39dbb999
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
@@ -0,0 +1,66 @@
+-- Work-alike to lm32_ram.v, but using generic_simple_dpram
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.genram_pkg.all;
+
+entity lm32_ram is
+  generic(
+    data_width    : natural := 1;
+    address_width : natural := 1);
+  port(
+    read_clk      : in  std_logic;
+    write_clk     : in  std_logic;
+    reset         : in  std_logic;
+    enable_read   : in  std_logic;
+    read_address  : in  std_logic_vector(address_width-1 downto 0);
+    enable_write  : in  std_logic;
+    write_address : in  std_logic_vector(address_width-1 downto 0);
+    write_data    : in  std_logic_vector(data_width   -1 downto 0);
+    write_enable  : in  std_logic;
+    read_data     : out std_logic_vector(data_width   -1 downto 0));
+end lm32_ram;
+
+architecture syn of lm32_ram is
+  
+  signal wea : std_logic;
+  signal reb : std_logic;
+  
+  -- Emulate read-enable using another bypass
+  signal old_data : std_logic_vector(data_width-1 downto 0);
+  signal new_data : std_logic_vector(data_width-1 downto 0);
+  signal data     : std_logic_vector(data_width-1 downto 0);
+
+begin
+  
+  wea <= enable_write and write_enable;
+  ram : generic_simple_dpram
+    generic map(
+      g_data_width               => data_width,
+      g_size                     => 2**address_width,
+      g_with_byte_enable         => false,
+      g_addr_conflict_resolution => "write_first",
+      g_dual_clock               => false) -- read_clk always = write_clk in LM32
+    port map(
+      clka_i => read_clk,
+      wea_i  => wea,
+      aa_i   => write_address,
+      da_i   => write_data,
+      clkb_i => write_clk,
+      ab_i   => read_address,
+      qb_o   => new_data);
+  
+  data <= old_data when reb='0' else new_data;
+  read_data <= data;
+  
+  main : process(read_clk) is
+  begin
+    if rising_edge(read_clk) then
+      old_data <= data;
+      reb <= enable_read;
+    end if;
+  end process;
+  
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
new file mode 100644
index 000000000..a9f0892b9
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
@@ -0,0 +1,138 @@
+// =============================================================================
+//                           COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court                            408-826-6000 (other locations)
+// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
+// U.S.A                                   email: techsupport@latticesemi.com
+// =============================================================================/
+//                         FILE DETAILS
+// Project          : LatticeMico32
+// File             : lm32_shifter.v
+// Title            : Barrel shifter
+// Dependencies     : lm32_include.v
+// Version          : 6.1.17
+//                  : Initial Release
+// Version          : 7.0SP2, 3.0
+//                  : No Change
+// Version          : 3.1
+//                  : No Change
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_shifter (
+    // ----- Inputs -------
+    clk_i,
+    rst_i,
+    stall_x,
+    direction_x,
+    sign_extend_x,
+    operand_0_x,
+    operand_1_x,
+    // ----- Outputs -------
+    shifter_result_m
+    );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i;                                // Clock
+input rst_i;                                // Reset
+input stall_x;                              // Stall instruction in X stage
+input direction_x;                          // Direction to shift
+input sign_extend_x;                        // Whether shift is arithmetic (1'b1) or logical (1'b0)
+input [`LM32_WORD_RNG] operand_0_x;         // Operand to shift
+input [`LM32_WORD_RNG] operand_1_x;         // Operand that specifies how many bits to shift by
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [`LM32_WORD_RNG] shifter_result_m;   // Result of shift
+wire   [`LM32_WORD_RNG] shifter_result_m;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers 
+/////////////////////////////////////////////////////
+
+reg direction_m;
+wire [`LM32_WORD_WIDTH*2-1:0] right_shift_result_x;
+reg [`LM32_WORD_RNG] left_shift_result;
+reg [`LM32_WORD_RNG] right_shift_result_m;
+reg [`LM32_WORD_RNG] left_shift_operand;
+wire [`LM32_WORD_RNG] right_shift_operand;
+wire fill_value;
+wire [`LM32_WORD_RNG] right_shift_in;
+
+integer shift_idx_0;
+integer shift_idx_1;
+
+/////////////////////////////////////////////////////
+// Combinational Logic
+/////////////////////////////////////////////////////
+    
+// Select operands - To perform a left shift, we reverse the bits and perform a right shift
+always @(*)
+begin
+    for (shift_idx_0 = 0; shift_idx_0 < `LM32_WORD_WIDTH; shift_idx_0 = shift_idx_0 + 1)
+        left_shift_operand[`LM32_WORD_WIDTH-1-shift_idx_0] = operand_0_x[shift_idx_0];
+end
+assign right_shift_operand = direction_x == `LM32_SHIFT_OP_LEFT ? left_shift_operand : operand_0_x;
+
+// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift
+assign fill_value = (sign_extend_x == `TRUE) && (direction_x == `LM32_SHIFT_OP_RIGHT) 
+                      ? operand_0_x[`LM32_WORD_WIDTH-1] 
+                      : 1'b0;
+
+// Determine bits to shift in for right shift or rotate
+assign right_shift_in = {`LM32_WORD_WIDTH{fill_value}};
+
+// Determine the result of the shifter
+assign right_shift_result_x = {right_shift_in, right_shift_operand} >> operand_1_x[`LM32_SHIFT_RNG];
+
+// Reverse bits to get left shift result
+always @(*)
+begin
+    for (shift_idx_1 = 0; shift_idx_1 < `LM32_WORD_WIDTH; shift_idx_1 = shift_idx_1 + 1)
+        left_shift_result[`LM32_WORD_WIDTH-1-shift_idx_1] = right_shift_result_m[shift_idx_1];
+end
+
+// Select result 
+assign shifter_result_m = direction_m == `LM32_SHIFT_OP_LEFT ? left_shift_result : right_shift_result_m;
+    
+/////////////////////////////////////////////////////
+// Sequential Logic
+/////////////////////////////////////////////////////
+
+// Perform right shift
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+    if (rst_i == `TRUE)
+    begin
+        right_shift_result_m <= {`LM32_WORD_WIDTH{1'b0}};
+        direction_m <= `FALSE;
+    end
+    else
+    begin
+        if (stall_x == `FALSE)
+        begin
+            right_shift_result_m <= right_shift_result_x[`LM32_WORD_RNG];
+            direction_m <= direction_x;
+        end
+    end
+end 
+    
+endmodule
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
new file mode 100644
index 000000000..b7d0abba9
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
@@ -0,0 +1,432 @@
+//////////////////////////////////////////////////////////////////////////////
+//                                                                          //
+//  Minimalistic 1-wire (onewire) master with Avalon MM bus interface       //
+//                                                                          //
+//  Copyright (C) 2010  Iztok Jeras                                         //
+//                                                                          //
+//////////////////////////////////////////////////////////////////////////////
+//                                                                          //
+//  This RTL is free hardware: you can redistribute it and/or modify        //
+//  it under the terms of the GNU Lesser General Public License             //
+//  as published by the Free Software Foundation, either                    //
+//  version 3 of the License, or (at your option) any later version.        //
+//                                                                          //
+//  This RTL is distributed in the hope that it will be useful,             //
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of          //
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           //
+//  GNU General Public License for more details.                            //
+//                                                                          //
+//  You should have received a copy of the GNU General Public License       //
+//  along with this program.  If not, see <http://www.gnu.org/licenses/>.   //
+//                                                                          //
+//////////////////////////////////////////////////////////////////////////////
+
+//////////////////////////////////////////////////////////////////////////////
+//  Modifications:
+//      2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
+//          * added default values; typos
+//////////////////////////////////////////////////////////////////////////////
+
+//////////////////////////////////////////////////////////////////////////////
+//                                                                          //
+// The clock divider parameter is computed with the next formula:           //
+//                                                                          //
+// CDR_N = f_CLK * BTP_N - 1  (example: CDR_N = 1MHz * 5.0us - 1 = 5-1)     //
+// CDR_O = f_CLK * BTP_O - 1  (example: CDR_O = 1MHz * 1.0us - 1 = 1-1)     //
+//                                                                          //
+// If the dividing factor is not a round integer, than the timing of the    //
+// controller will be slightly off, and would support only a subset of      //
+// 1-wire devices with timing closer to the typical 30us slot.              //
+//                                                                          //
+// Base time periods BTP_N = "5.0" and BTP_O = "1.0" are optimized for      //
+// onewire timing. The default timing restricts the range of available      //
+// frequences to multiples of 1MHz.                                         //
+//                                                                          //
+// If even this restrictions are too strict use timing BTP_N = "6.0" and    //
+// BTP_O = "0.5", where the actual periods can be in the range:             //
+// 6.0us <= BTP_N <= 7.5us                                                  //
+// 0.5us <= BTP_O <= 0.66us                                                 //
+//                                                                          //
+// A third timing option is available for normal mode BTP_N = "7.5", this   //
+// option is optimized for logic size.                                      //
+//                                                                          //
+//////////////////////////////////////////////////////////////////////////////
+
+module sockit_owm #(
+  // enable implementation of optional functionality
+  parameter OVD_E =    1,  // overdrive functionality is implemented by default
+  parameter CDR_E =    1,  // clock divider register is implemented by default
+  // interface parameters
+  parameter BDW   =   32,  // bus data width
+  parameter OWN   =    1,  // number of 1-wire ports
+  // computed bus address port width
+`ifdef __ICARUS__
+  parameter BAW   = (BDW==32) ? 1 : 2,
+`else
+  parameter BAW   = 1,  // TODO, the above is correct, but does not work well with Altera SOPC Builder
+`endif
+  // base time period
+  parameter BTP_N = "5.0", // normal    mode (5.0us, options are "7.5", "5.0" and "6.0")
+  parameter BTP_O = "0.5", // overdrive mode (1.0us, options are "1.0",       and "0.5")
+  // normal mode timing
+  parameter T_RSTH_N = (BTP_N == "7.5") ?  64 : (BTP_N == "5.0") ?  96 :  80,  // reset high
+  parameter T_RSTL_N = (BTP_N == "7.5") ?  64 : (BTP_N == "5.0") ?  96 :  80,  // reset low
+  parameter T_RSTP_N = (BTP_N == "7.5") ?  10 : (BTP_N == "5.0") ?  15 :  10,  // reset presence pulse
+  parameter T_DAT0_N = (BTP_N == "7.5") ?   8 : (BTP_N == "5.0") ?  12 :  10,  // bit 0 low
+  parameter T_DAT1_N = (BTP_N == "7.5") ?   1 : (BTP_N == "5.0") ?   1 :   1,  // bit 1 low
+  parameter T_BITS_N = (BTP_N == "7.5") ?   2 : (BTP_N == "5.0") ?   3 :   2,  // bit sample
+  parameter T_RCVR_N = (BTP_N == "7.5") ?   1 : (BTP_N == "5.0") ?   1 :   1,  // recovery
+  parameter T_IDLE_N = (BTP_N == "7.5") ? 128 : (BTP_N == "5.0") ? 200 : 160,  // idle timer
+  // overdrive mode timing
+  parameter T_RSTH_O = (BTP_O == "1.0") ?  48 :  96,  // reset high
+  parameter T_RSTL_O = (BTP_O == "1.0") ?  48 :  96,  // reset low
+  parameter T_RSTP_O = (BTP_O == "1.0") ?  10 :  15,  // reset presence pulse
+  parameter T_DAT0_O = (BTP_O == "1.0") ?   6 :  12,  // bit 0 low
+  parameter T_DAT1_O = (BTP_O == "1.0") ?   1 :   2,  // bit 1 low
+  parameter T_BITS_O = (BTP_O == "1.0") ?   2 :   3,  // bit sample
+  parameter T_RCVR_O = (BTP_O == "1.0") ?   2 :   4,  // recovery
+  parameter T_IDLE_O = (BTP_O == "1.0") ?  96 : 192,  // idle timer
+  // clock divider ratios (defaults are for a 1MHz clock)
+  parameter CDR_N = 5-1,  // normal    mode
+  parameter CDR_O = 1-1   // overdrive mode
+)(
+  // system signals
+  input            clk,
+  input            rst,
+  // CPU bus interface
+  input            bus_ren,  // read  enable
+  input            bus_wen,  // write enable
+  input  [BAW-1:0] bus_adr,  // address
+  input  [BDW-1:0] bus_wdt,  // write data
+  output [BDW-1:0] bus_rdt,  // read  data
+  output           bus_irq,  // interrupt request
+  // 1-wire interface
+  output [OWN-1:0] owr_p,    // output power enable
+  output [OWN-1:0] owr_e,    // output pull down enable
+  input  [OWN-1:0] owr_i     // input from bidirectional wire
+);
+
+//////////////////////////////////////////////////////////////////////////////
+// local parameters
+//////////////////////////////////////////////////////////////////////////////
+
+function integer clogb2;               
+input [31:0] value;
+begin
+   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+     value = value >> 1;
+end
+endfunction
+
+// size of combined power and select registers
+localparam PDW = (BDW==32) ? 24 : 8;
+
+// size of boudrate generator counter (divider for normal mode is largest)
+localparam CDW = CDR_E ? ((BDW==32) ? 16 : 8) : clogb2(CDR_N);
+
+// size of port select signal
+localparam SDW = clogb2(OWN);
+
+// size of cycle timing counter
+localparam TDW =       (T_RSTH_O+T_RSTL_O) >       (T_RSTH_N+T_RSTL_N)
+               ? clogb2(T_RSTH_O+T_RSTL_O) : clogb2(T_RSTH_N+T_RSTL_N);
+
+//////////////////////////////////////////////////////////////////////////////
+// local signals
+//////////////////////////////////////////////////////////////////////////////
+
+// address dependent write enable
+wire bus_ren_ctl_sts;
+wire bus_wen_ctl_sts;
+wire bus_wen_pwr_sel;
+wire bus_wen_cdr_n;
+wire bus_wen_cdr_o;
+
+// read data bus segments
+wire     [7:0] bus_rdt_ctl_sts;
+wire [PDW-1:0] bus_rdt_pwr_sel;
+
+// clock divider
+reg  [CDW-1:0] div;
+reg  [CDW-1:0] cdr_n = CDR_N[CDW-1:0];
+reg  [CDW-1:0] cdr_o = CDR_O[CDW-1:0];
+wire           pls;
+
+// cycle control and status
+reg            owr_cyc;  // cycle status
+reg  [TDW-1:0] cnt;      // cycle counter
+
+// port select
+//generate if (OWN>1) begin : sel_declaration
+reg  [SDW-1:0] owr_sel;
+//end endgenerate
+
+// modified input data for overdrive
+wire           req_ovd;
+
+// onewire signals
+reg  [OWN-1:0] owr_pwr;  // power
+reg            owr_ovd;  // overdrive
+reg            owr_rst;  // reset
+reg            owr_dat;  // data bit
+reg            owr_smp;  // sample bit
+
+reg            owr_oen;  // output enable
+wire           owr_iln;  // input line
+
+// interrupt signals
+reg            irq_ena;  // interrupt enable
+reg            irq_sts;  // interrupt status
+
+// timing signals
+wire [TDW-1:0] t_idl ;   // idle                 cycle    time
+wire [TDW-1:0] t_rst ;   // reset                cycle    time
+wire [TDW-1:0] t_bit ;   // data bit             cycle    time
+wire [TDW-1:0] t_rstp;   // reset presence pulse sampling time
+wire [TDW-1:0] t_rsth;   // reset                release  time
+wire [TDW-1:0] t_dat0;   // data bit 0           release  time
+wire [TDW-1:0] t_dat1;   // data bit 1           release  time
+wire [TDW-1:0] t_bits;   // data bit             sampling time
+wire [TDW-1:0] t_zero;   // end of               cycle    time
+
+//////////////////////////////////////////////////////////////////////////////
+// cycle timing
+//////////////////////////////////////////////////////////////////////////////
+
+// idle time
+assign t_idl  = req_ovd ? T_IDLE_O[TDW-1:0]                         : T_IDLE_N[TDW-1:0];
+// reset cycle time (reset low + reset hight)
+assign t_rst  = req_ovd ? T_RSTL_O[TDW-1:0] + T_RSTH_O[TDW-1:0]     : T_RSTL_N[TDW-1:0] + T_RSTH_N[TDW-1:0];
+// data bit cycle time (write 0 + recovery)
+assign t_bit  = req_ovd ? T_DAT0_O[TDW-1:0] + T_RCVR_O[TDW-1:0]     : T_DAT0_N[TDW-1:0] + T_RCVR_N[TDW-1:0];
+
+// reset presence pulse sampling time (reset high - reset presence)
+assign t_rstp = owr_ovd ? T_RSTH_O[TDW-1:0] - T_RSTP_O[TDW-1:0]     : T_RSTH_N[TDW-1:0] - T_RSTP_N[TDW-1:0];
+// reset      release time (reset high)
+assign t_rsth = owr_ovd ? T_RSTH_O[TDW-1:0]                         : T_RSTH_N[TDW-1:0];
+
+// data bit 0 release time (write bit 0 - write bit 0 + recovery)
+assign t_dat0 = owr_ovd ? T_DAT0_O[TDW-1:0] - T_DAT0_O[TDW-1:0] + T_RCVR_O[TDW-1:0] : T_DAT0_N[TDW-1:0] - T_DAT0_N[TDW-1:0] + T_RCVR_N[TDW-1:0];
+// data bit 1 release time (write bit 0 - write bit 1 + recovery)
+assign t_dat1 = owr_ovd ? T_DAT0_O[TDW-1:0] - T_DAT1_O[TDW-1:0] + T_RCVR_O[TDW-1:0] : T_DAT0_N[TDW-1:0] - T_DAT1_N[TDW-1:0] + T_RCVR_N[TDW-1:0];
+// data bit sampling time (write bit 0 - write bit 1 + recovery)
+assign t_bits = owr_ovd ? T_DAT0_O[TDW-1:0] - T_BITS_O[TDW-1:0] + T_RCVR_O[TDW-1:0] : T_DAT0_N[TDW-1:0] - T_BITS_N[TDW-1:0] + T_RCVR_N[TDW-1:0];
+
+// end of cycle time
+assign t_zero = 'd0;
+
+//////////////////////////////////////////////////////////////////////////////
+// bus read
+//////////////////////////////////////////////////////////////////////////////
+
+// bus segnemt - controll/status register
+assign bus_rdt_ctl_sts = {irq_ena, irq_sts, 1'b0, owr_pwr[0], owr_cyc, owr_ovd, owr_rst, owr_dat};
+
+// bus segnemt - power and select register
+generate
+  if (BDW==32) begin
+    if (OWN>1) begin
+      assign bus_rdt_pwr_sel = {{16-OWN{1'b0}}, owr_pwr, 4'h0, {4-SDW{1'b0}}, owr_sel};
+    end else begin
+      assign bus_rdt_pwr_sel = 24'h0000_00;
+    end
+  end else if (BDW==8) begin
+    if (OWN>1) begin
+      assign bus_rdt_pwr_sel = {{ 4-OWN{1'b0}}, owr_pwr,       {4-SDW{1'b0}}, owr_sel};
+    end else begin
+      assign bus_rdt_pwr_sel = 8'hxx;
+    end
+  end
+endgenerate
+
+// bus read data
+generate if (BDW==32) begin
+  assign bus_rdt = (bus_adr[0]==1'b0) ? {bus_rdt_pwr_sel, bus_rdt_ctl_sts} : (cdr_o << 16 | cdr_n);
+end else if (BDW==8) begin
+  assign bus_rdt = (bus_adr[1]==1'b0) ? ((bus_adr[0]==1'b0) ? bus_rdt_ctl_sts
+                                                            : bus_rdt_pwr_sel)
+                                      : ((bus_adr[0]==1'b0) ? cdr_n
+                                                            : cdr_o          );
+end endgenerate
+
+//////////////////////////////////////////////////////////////////////////////
+// bus write
+//////////////////////////////////////////////////////////////////////////////
+
+// combined write/read enable and address decoder
+generate if (BDW==32) begin
+  assign bus_ren_ctl_sts = bus_ren & bus_adr[0] == 1'b0;
+  assign bus_wen_ctl_sts = bus_wen & bus_adr[0] == 1'b0;
+  assign bus_wen_pwr_sel = bus_wen & bus_adr[0] == 1'b0;
+  assign bus_wen_cdr_n   = bus_wen & bus_adr[0] == 1'b1;
+  assign bus_wen_cdr_o   = bus_wen & bus_adr[0] == 1'b1;
+end else if (BDW==8) begin
+  assign bus_ren_ctl_sts = bus_ren & bus_adr[1:0] == 2'b00;
+  assign bus_wen_ctl_sts = bus_wen & bus_adr[1:0] == 2'b00;
+  assign bus_wen_pwr_sel = bus_wen & bus_adr[1:0] == 2'b01;
+  assign bus_wen_cdr_n   = bus_wen & bus_adr[1:0] == 2'b10;
+  assign bus_wen_cdr_o   = bus_wen & bus_adr[1:0] == 2'b11;
+end endgenerate
+
+//////////////////////////////////////////////////////////////////////////////
+// clock divider
+//////////////////////////////////////////////////////////////////////////////
+
+// clock divider ratio registers
+generate
+  if (CDR_E) begin
+    if (BDW==32) begin
+      always @ (posedge clk, posedge rst)
+      if (rst) begin
+        cdr_n <= CDR_N[CDW-1:0];
+        cdr_o <= CDR_O[CDW-1:0];
+      end else begin
+        if (bus_wen_cdr_n)  cdr_n <= bus_wdt[15: 0];
+        if (bus_wen_cdr_o)  cdr_o <= bus_wdt[31:16];
+      end
+    end else if (BDW==8) begin
+      always @ (posedge clk, posedge rst)
+      if (rst) begin
+        cdr_n <= CDR_N[CDW-1:0];
+        cdr_o <= CDR_O[CDW-1:0];
+      end else begin
+        if (bus_wen_cdr_n)  cdr_n <= bus_wdt;
+        if (bus_wen_cdr_o)  cdr_o <= bus_wdt;
+      end
+    end
+  end else begin
+    initial begin
+      cdr_n = CDR_N[CDW-1:0];
+      cdr_o = CDR_O[CDW-1:0];
+    end
+  end
+endgenerate
+
+// clock divider
+always @ (posedge clk, posedge rst)
+if (rst)        div <= {CDW{1'd0}};
+else begin
+  if (bus_wen)  div <= {CDW{1'd0}};
+  else          div <= pls ? {CDW{1'd0}} : div + owr_cyc;
+end
+
+// divided clock pulse
+assign pls = (div == (owr_ovd ? cdr_o : cdr_n));
+
+//////////////////////////////////////////////////////////////////////////////
+// power and select register
+//////////////////////////////////////////////////////////////////////////////
+
+// select and power register implementation
+generate if (OWN>1) begin : sel_implementation
+  // port select
+  always @ (posedge clk, posedge rst)
+  if (rst)                   owr_sel <= {SDW{1'b0}};
+  else if (bus_wen_pwr_sel)  owr_sel <= bus_wdt[(BDW==32 ?  8 : 0)+:SDW];
+  
+  // power delivery
+  always @ (posedge clk, posedge rst)
+  if (rst)                   owr_pwr <= {OWN{1'b0}};
+  else if (bus_wen_pwr_sel)  owr_pwr <= bus_wdt[(BDW==32 ? 16 : 4)+:OWN];
+end else begin
+  // port select
+  initial                    owr_sel <= 'd0; 
+  // power delivery
+  always @ (posedge clk, posedge rst)
+  if (rst)                   owr_pwr <= 1'b0;
+  else if (bus_wen_ctl_sts)  owr_pwr <= bus_wdt[4];
+end endgenerate
+
+//////////////////////////////////////////////////////////////////////////////
+// interrupt logic
+//////////////////////////////////////////////////////////////////////////////
+
+// bus interrupt
+assign bus_irq = irq_ena & irq_sts;
+
+// interrupt enable
+always @ (posedge clk, posedge rst)
+if (rst)                   irq_ena <= 1'b0;     
+else if (bus_wen_ctl_sts)  irq_ena <= bus_wdt[7]; 
+
+// transmit status (active after onewire cycle ends)
+always @ (posedge clk, posedge rst)
+if (rst)                           irq_sts <= 1'b0;
+else begin
+  if (bus_wen_ctl_sts)             irq_sts <= 1'b0;
+  else if (pls & (cnt == t_zero))  irq_sts <= 1'b1;
+  else if (bus_ren_ctl_sts)        irq_sts <= 1'b0;
+end
+
+//////////////////////////////////////////////////////////////////////////////
+// onewire state machine
+//////////////////////////////////////////////////////////////////////////////
+
+assign req_ovd = OVD_E ? bus_wen_ctl_sts & bus_wdt[2] : 1'b0; 
+
+// overdrive
+always @ (posedge clk, posedge rst)
+if (rst)                   owr_ovd <= 1'b0;
+else if (bus_wen_ctl_sts)  owr_ovd <= req_ovd;
+
+// reset
+always @ (posedge clk, posedge rst)
+if (rst)                   owr_rst <= 1'b0;
+else if (bus_wen_ctl_sts)  owr_rst <= bus_wdt[1];
+
+// transmit data, reset, overdrive
+always @ (posedge clk, posedge rst)
+if (rst)                           owr_dat <= 1'b0;
+else begin
+  if (bus_wen_ctl_sts)             owr_dat <= bus_wdt[0];
+  else if (pls & (cnt == t_zero))  owr_dat <= owr_smp;
+end
+
+// onewire cycle status
+always @ (posedge clk, posedge rst)
+if (rst)                           owr_cyc <= 1'b0;
+else begin
+  if (bus_wen_ctl_sts)             owr_cyc <= bus_wdt[3] & ~&bus_wdt[2:0];
+  else if (pls & (cnt == t_zero))  owr_cyc <= 1'b0;
+end
+
+// state counter (initial value depends whether the cycle is reset or data)
+always @ (posedge clk, posedge rst)
+if (rst)                 cnt <= 0;
+else begin
+  if (bus_wen_ctl_sts)   cnt <= (&bus_wdt[1:0] ? t_idl : bus_wdt[1] ? t_rst : t_bit) - 1'd1;
+  else if (pls)          cnt <= cnt - 1'd1;
+end
+
+// receive data (sampling point depends whether the cycle is reset or data)
+always @ (posedge clk)
+if (pls) begin
+  if      ( owr_rst & (cnt == t_rstp))  owr_smp <= owr_iln;  // presence detect
+  else if (~owr_rst & (cnt == t_bits))  owr_smp <= owr_iln;  // read data bit
+end
+
+// output register (switch point depends whether the cycle is reset or data)
+always @ (posedge clk, posedge rst)
+if (rst)                                owr_oen <= 1'b0;
+else begin
+  if (bus_wen_ctl_sts)                  owr_oen <= ~&bus_wdt[1:0];
+  else if (pls) begin
+    if      (owr_rst & (cnt == t_rsth)) owr_oen <= 1'b0;  // reset
+    else if (owr_dat & (cnt == t_dat1)) owr_oen <= 1'b0;  // write 1, read
+    else if (          (cnt == t_dat0)) owr_oen <= 1'b0;  // write 0
+  end
+end
+
+//////////////////////////////////////////////////////////////////////////////
+// IO
+//////////////////////////////////////////////////////////////////////////////
+
+// only one 1-wire line can be accessed at the same time
+assign owr_e   = owr_oen << owr_sel;
+// all 1-wire lines can be powered independently
+assign owr_p   = owr_pwr;
+
+// 1-wire line status read multiplexer
+assign owr_iln = owr_i [owr_sel];
+
+endmodule
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
new file mode 100644
index 000000000..b1f5d60b7
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
@@ -0,0 +1,184 @@
+------------------------------------------------------------------------------
+-- Title      : Wishbone 1-Wire Master
+-- Project    : General Cores Library (gencores)
+------------------------------------------------------------------------------
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-05-18
+-- Last update: 2012-02-23
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Wishbone Dallas/Maxim Semiconductor 1-Wire master.
+-------------------------------------------------------------------------------
+-- 
+-- Based on sockit_owm project Copyright (c) 2010 Iztok Jeras.
+-- http://opencores.org/project,sockit_owm
+--
+-- sockit_owm RTL is licensed under LGPL 3.
+
+-- wb_onewire_master.vhd copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-09-18  1.0      twlostow        Created
+-- 2016-08-24  1.1      jpospisi        propagated CDR_N/O generics up the
+--                                        hierarchy; added assignments to (new)
+--                                        unspecified WB signals
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+
+entity wb_onewire_master is
+
+  generic(
+    g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity : t_wishbone_address_granularity := WORD;
+    g_num_ports           : integer                        := 1;
+    g_ow_btp_normal       : string                         := "5.0";
+    g_ow_btp_overdrive    : string                         := "1.0";
+    g_CDR_N               : integer                        := 4; -- normal    mode
+    g_CDR_O               : integer                        := 0  -- overdrive mode
+    );  
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    wb_cyc_i   : in  std_logic;
+    wb_sel_i   : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+    wb_stb_i   : in  std_logic;
+    wb_we_i    : in  std_logic;
+    wb_adr_i   : in  std_logic_vector(2 downto 0);
+    wb_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_ack_o   : out std_logic;
+    wb_int_o   : out std_logic;
+    wb_stall_o : out std_logic;
+
+    owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
+    owr_en_o    : out std_logic_vector(g_num_ports -1 downto 0);
+    owr_i       : in  std_logic_vector(g_num_ports -1 downto 0)
+    );
+
+end wb_onewire_master;
+
+
+architecture rtl of wb_onewire_master is
+
+  component sockit_owm
+    generic(
+      BTP_N : string;
+      BTP_O : string;
+      OWN   : integer;
+      CDR_N : integer;
+      CDR_O : integer);
+
+    port(
+      clk     : in  std_logic;
+      rst     : in  std_logic;
+      bus_ren : in  std_logic;
+      bus_wen : in  std_logic;
+      bus_adr : in  std_logic_vector(0 downto 0);
+      bus_wdt : in  std_logic_vector(31 downto 0);
+      bus_rdt : out std_logic_vector(31 downto 0);
+      bus_irq : out std_logic;
+      owr_p   : out std_logic_vector(OWN-1 downto 0);
+      owr_e   : out std_logic_vector(OWN-1 downto 0);
+      owr_i   : in  std_logic_vector(OWN-1 downto 0)
+      );
+  end component;
+
+  signal bus_wen : std_logic;
+  signal bus_ren : std_logic;
+  signal rst     : std_logic;
+
+  signal slave_in  : t_wishbone_slave_in;
+  signal slave_out : t_wishbone_slave_out;
+
+  signal adp_out : t_wishbone_master_out;
+  signal adp_in  : t_wishbone_master_in;
+
+  signal rdat_int : std_logic_vector(31 downto 0);
+  
+begin  -- rtl
+
+  slave_in.adr(2 downto 0)                          <= wb_adr_i;
+  slave_in.adr(c_wishbone_address_width-1 downto 3) <= (others => '0');
+  slave_in.cyc                                      <= wb_cyc_i;
+  slave_in.stb                                      <= wb_stb_i;
+  slave_in.sel                                      <= wb_sel_i;
+  slave_in.dat                                      <= wb_dat_i;
+  slave_in.we                                       <= wb_we_i;
+
+  wb_int_o   <= slave_out.int;
+  wb_dat_o   <= slave_out.dat;
+  wb_stall_o <= slave_out.stall;
+  wb_ack_o   <= slave_out.ack;
+
+
+  U_Slave_adapter : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => true,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+
+      slave_i  => slave_in,
+      slave_o  => slave_out,
+      master_i => adp_in,
+      master_o => adp_out);
+
+  
+  bus_wen <= adp_out.cyc and adp_out.stb and adp_out.we and not adp_in.ack;
+  bus_ren <= adp_out.cyc and adp_out.stb and not (adp_out.we or adp_in.ack);
+
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        adp_in.ack <= '0';
+      else
+        adp_in.ack <= adp_out.stb and adp_out.cyc and not adp_in.ack;
+        adp_in.dat <= rdat_int;
+      end if;
+    end if;
+  end process;
+
+  rst <= not rst_n_i;
+
+  Wrapped_1wire : sockit_owm
+    generic map (
+      BTP_N => g_ow_btp_normal,
+      BTP_O => g_ow_btp_overdrive,
+      OWN   => g_num_ports,
+      CDR_N => g_CDR_N,
+      CDR_O => g_CDR_O)
+    port map (
+      clk     => clk_sys_i,
+      rst     => rst,
+      bus_ren => bus_ren,
+      bus_wen => bus_wen,
+      bus_adr => adp_out.adr(0 downto 0),
+      bus_wdt => adp_out.dat,
+      bus_rdt => rdat_int,
+      bus_irq => adp_in.int,
+      owr_p   => owr_pwren_o,
+      owr_e   => owr_en_o,
+      owr_i   => owr_i);
+
+  adp_in.err <= '0';
+  adp_in.rty <= '0';
+  adp_in.stall <= '0';
+
+end rtl;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
new file mode 100644
index 000000000..3920efd20
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
@@ -0,0 +1,105 @@
+--------------------------------------------------------------------------------
+--  Modifications:
+--      2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
+--          * propagated CDR_N/O generics up the hierarchy; added assignments
+--            to (new) unspecified WB signals
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.wishbone_pkg.all;
+
+entity xwb_onewire_master is
+  generic(
+    g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity : t_wishbone_address_granularity := WORD;
+    g_num_ports           : integer                        := 1;
+    g_ow_btp_normal       : string                         := "5.0";
+    g_ow_btp_overdrive    : string                         := "1.0";
+    g_CDR_N               : integer                        := 4; -- normal    mode
+    g_CDR_O               : integer                        := 0  -- overdrive mode
+    );
+
+  port(
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    -- Wishbone
+    slave_i : in  t_wishbone_slave_in;
+    slave_o : out t_wishbone_slave_out;
+    desc_o  : out t_wishbone_device_descriptor;
+
+    owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
+    owr_en_o    : out std_logic_vector(g_num_ports -1 downto 0);
+    owr_i       : in  std_logic_vector(g_num_ports -1 downto 0)
+
+    );
+
+end xwb_onewire_master;
+
+architecture rtl of xwb_onewire_master is
+
+  component wb_onewire_master
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_num_ports           : integer;
+      g_ow_btp_normal       : string;
+      g_ow_btp_overdrive    : string;
+      g_CDR_N               : integer;
+      g_CDR_O               : integer);
+    port (
+      clk_sys_i   : in  std_logic;
+      rst_n_i     : in  std_logic;
+      
+      wb_cyc_i    : in  std_logic;
+      wb_sel_i    : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+      wb_stb_i    : in  std_logic;
+      wb_we_i     : in  std_logic;
+      wb_adr_i    : in  std_logic_vector(2 downto 0);
+      wb_dat_i    : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_dat_o    : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_ack_o    : out std_logic;
+      wb_int_o    : out std_logic;
+      wb_stall_o  : out std_logic;
+      
+      owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
+      owr_en_o    : out std_logic_vector(g_num_ports -1 downto 0);
+      owr_i       : in  std_logic_vector(g_num_ports -1 downto 0));
+  end component;
+  
+begin  -- rtl
+
+  U_Wrapped_1W : wb_onewire_master
+    generic map (
+      g_interface_mode      => g_interface_mode,
+      g_address_granularity => g_address_granularity,
+      g_num_ports           => g_num_ports,
+      g_ow_btp_normal       => g_ow_btp_normal,
+      g_ow_btp_overdrive    => g_ow_btp_overdrive,
+      g_CDR_N               => g_CDR_N,
+      g_CDR_O               => g_CDR_O)
+    port map (
+      clk_sys_i   => clk_sys_i,
+      rst_n_i     => rst_n_i,
+      wb_cyc_i    => slave_i.cyc,
+      wb_sel_i    => slave_i.sel,
+      wb_stb_i    => slave_i.stb,
+      wb_we_i     => slave_i.we,
+      wb_adr_i    => slave_i.adr(2 downto 0),
+      wb_dat_i    => slave_i.dat,
+      wb_dat_o    => slave_o.dat,
+      wb_ack_o    => slave_o.ack,
+      wb_int_o    => slave_o.int,
+      wb_stall_o  => slave_o.stall,
+      owr_pwren_o => owr_pwren_o,
+      owr_en_o    => owr_en_o,
+      owr_i       => owr_i);
+
+  slave_o.err <= '0';
+  slave_o.rty <= '0';
+
+  desc_o <= (others => '0');
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
new file mode 100644
index 000000000..193fc3dc3
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
@@ -0,0 +1,232 @@
+-------------------------------------------------------------------------------
+-- Title      : Wishbone Slave Adapter
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wb_slave_adapter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- universal "adapter"
+-- pipelined <> classic
+-- word-aligned/byte-aligned address
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wishbone_pkg.all;
+
+entity wb_slave_adapter is
+
+  generic (
+    g_master_use_struct  : boolean;
+    g_master_mode        : t_wishbone_interface_mode;
+    g_master_granularity : t_wishbone_address_granularity;
+    g_slave_use_struct   : boolean;
+    g_slave_mode         : t_wishbone_interface_mode;
+    g_slave_granularity  : t_wishbone_address_granularity
+    );
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+-- slave port (i.e. wb_slave_adapter is slave)
+    sl_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
+    sl_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
+    sl_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+    sl_cyc_i : in std_logic;
+    sl_stb_i : in std_logic;
+    sl_we_i  : in std_logic;
+
+
+    sl_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    sl_err_o   : out std_logic;
+    sl_rty_o   : out std_logic;
+    sl_ack_o   : out std_logic;
+    sl_stall_o : out std_logic;
+    sl_int_o   : out std_logic;
+
+    slave_i : in  t_wishbone_slave_in;
+    slave_o : out t_wishbone_slave_out;
+
+-- master port (i.e. wb_slave_adapter is master)
+    ma_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+    ma_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    ma_sel_o : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+    ma_cyc_o : out std_logic;
+    ma_stb_o : out std_logic;
+    ma_we_o  : out std_logic;
+
+    ma_dat_i   : in std_logic_vector(c_wishbone_data_width-1 downto 0);
+    ma_err_i   : in std_logic;
+    ma_rty_i   : in std_logic;
+    ma_ack_i   : in std_logic;
+    ma_stall_i : in std_logic;
+    ma_int_i   : in std_logic;
+
+    master_i : in  t_wishbone_master_in;
+    master_o : out t_wishbone_master_out
+    );
+end wb_slave_adapter;
+
+architecture rtl of wb_slave_adapter is
+
+  function f_num_byte_address_bits
+    return integer is
+  begin
+    case c_wishbone_data_width is
+      when 8      => return 0;
+      when 16     => return 1;
+      when 32     => return 2;
+      when 64     => return 3;
+      when others =>
+        report "wb_slave_adapter: invalid c_wishbone_data_width (we support 8, 16, 32 and 64)" severity failure;
+    end case;
+    return 0;
+  end f_num_byte_address_bits;
+
+  function f_zeros(size : integer)
+    return std_logic_vector is
+  begin
+    return std_logic_vector(to_unsigned(0, size));
+  end f_zeros;
+
+  type t_fsm_state is (IDLE, WAIT4ACK);
+
+  signal fsm_state : t_fsm_state := IDLE;
+
+  signal master_in  : t_wishbone_master_in;
+  signal master_out : t_wishbone_master_out;
+  signal slave_in   : t_wishbone_slave_in;
+  signal slave_out  : t_wishbone_slave_out;
+  signal stored_we  : std_logic;
+  
+begin  -- rtl
+
+  gen_slave_use_struct : if (g_slave_use_struct) generate
+    slave_in <= slave_i;
+  end generate gen_slave_use_struct;
+
+  gen_slave_use_slv : if (not g_slave_use_struct) generate
+    slave_in.cyc <= sl_cyc_i;
+    slave_in.stb <= sl_stb_i;
+    slave_in.we  <= sl_we_i;
+    slave_in.dat <= sl_dat_i;
+    slave_in.sel <= sl_sel_i;
+    slave_in.adr <= sl_adr_i;
+  end generate gen_slave_use_slv;
+
+  slave_o    <= slave_out;
+  sl_ack_o   <= slave_out.ack;
+  sl_rty_o   <= slave_out.rty;
+  sl_err_o   <= slave_out.err;
+  sl_stall_o <= slave_out.stall;
+  sl_dat_o   <= slave_out.dat;
+  sl_int_o   <= slave_out.int;
+  
+
+  gen_master_use_struct : if (g_master_use_struct) generate
+    master_in <= master_i;
+  end generate gen_master_use_struct;
+
+  gen_master_use_slv : if (not g_master_use_struct) generate
+    master_in <= (
+      ack   => ma_ack_i,
+      rty   => ma_rty_i,
+      err   => ma_err_i,
+      dat   => ma_dat_i,
+      stall => ma_stall_i,
+      int   => ma_int_i);
+  end generate gen_master_use_slv;
+
+  master_o <= master_out;
+  ma_adr_o <= master_out.adr;
+  ma_dat_o <= master_out.dat;
+  ma_sel_o <= master_out.sel;
+  ma_cyc_o <= master_out.cyc;
+  ma_stb_o <= master_out.stb;
+  ma_we_o  <= master_out.we;
+
+  p_gen_address : process(slave_in, master_out)
+  begin
+    if(g_master_granularity = g_slave_granularity) then
+      master_out.adr <= slave_in.adr;
+    elsif(g_master_granularity = BYTE) then  -- byte->word
+      master_out.adr <= slave_in.adr(c_wishbone_address_width-f_num_byte_address_bits-1 downto 0)
+                        & f_zeros(f_num_byte_address_bits);
+    else
+      master_out.adr <= f_zeros(f_num_byte_address_bits)
+                        & slave_in.adr(c_wishbone_address_width-1 downto f_num_byte_address_bits);
+    end if;
+  end process;
+  
+  P2C : if (g_slave_mode = PIPELINED and g_master_mode = CLASSIC)   generate
+    master_out.stb  <= slave_in.stb;
+    slave_out.stall <= not master_in.ack;
+  end generate;
+  
+  C2P : if (g_slave_mode = CLASSIC   and g_master_mode = PIPELINED) generate
+    master_out.stb  <= slave_in.stb when fsm_state=IDLE else '0';
+    slave_out.stall <= '0'; -- classic will ignore this anyway
+    
+    state_machine : process(clk_sys_i) is
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_n_i = '0' then
+          fsm_state <= IDLE;
+        else
+          case fsm_state is
+            when IDLE => 
+              if slave_in.stb ='1' and slave_in.cyc = '1' and master_in.stall='0' and master_in.ack='0' then
+                fsm_state <= WAIT4ACK;
+              end if;
+            when WAIT4ACK => 
+              if (slave_in.stb = '0' and slave_in.cyc = '0') or master_in.ack='1' or master_in.err='1' then 
+                fsm_state <= IDLE;
+              end if;
+          end case;
+        end if;
+      end if;
+    end process;
+  end generate;
+  
+  X2X : if (g_slave_mode = g_master_mode) generate
+    master_out.stb  <= slave_in.stb;
+    slave_out.stall <= master_in.stall;
+  end generate;
+  
+  master_out.dat <= slave_in.dat;
+  master_out.cyc <= slave_in.cyc;
+  master_out.sel <= slave_in.sel;
+  master_out.we  <= slave_in.we;
+
+  slave_out.ack <= master_in.ack;
+  slave_out.err <= master_in.err;
+  slave_out.rty <= master_in.rty;
+  slave_out.dat <= master_in.dat;
+  slave_out.int <= master_in.int;
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
new file mode 100644
index 000000000..f9afa0f47
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
@@ -0,0 +1,167 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  spi_define.v                                                ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+//////////////////////////////////////////////////////////////////////
+//
+//  Modified to use parameters in spi_top instead of constants in this
+//  file for divider length, max char length and number of slaves,
+//  G.Daniluk, CERN 2013
+//
+//////////////////////////////////////////////////////////////////////
+
+//
+// Number of bits used for devider register. If used in system with
+// low frequency of system clock this can be reduced.
+// Use SPI_DIVIDER_LEN for fine tuning theexact number.
+//
+//`define SPI_DIVIDER_LEN_8
+//`define SPI_DIVIDER_LEN_16
+//`define SPI_DIVIDER_LEN_24
+//`define SPI_DIVIDER_LEN_32
+//
+//`ifdef SPI_DIVIDER_LEN_8
+//  `define SPI_DIVIDER_LEN       8    // Can be set from 1 to 8
+//`endif                                                          
+//`ifdef SPI_DIVIDER_LEN_16                                       
+//  `define SPI_DIVIDER_LEN       16   // Can be set from 9 to 16
+//`endif                                                          
+//`ifdef SPI_DIVIDER_LEN_24                                       
+//  `define SPI_DIVIDER_LEN       24   // Can be set from 17 to 24
+//`endif                                                          
+//`ifdef SPI_DIVIDER_LEN_32                                       
+//  `define SPI_DIVIDER_LEN       32   // Can be set from 25 to 32 
+//`endif
+
+//
+// Maximum nuber of bits that can be send/received at once. 
+// Use SPI_MAX_CHAR for fine tuning the exact number, when using
+// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8.
+//
+//`define SPI_MAX_CHAR_128
+//`define SPI_MAX_CHAR_64
+//`define SPI_MAX_CHAR_32
+//`define SPI_MAX_CHAR_24
+//`define SPI_MAX_CHAR_16
+//`define SPI_MAX_CHAR_8
+//
+//`ifdef SPI_MAX_CHAR_128
+//  `define SPI_MAX_CHAR          128  // Can only be set to 128 
+//  `define SPI_CHAR_LEN_BITS     7
+//`endif
+//`ifdef SPI_MAX_CHAR_64
+//  `define SPI_MAX_CHAR          64   // Can only be set to 64 
+//  `define SPI_CHAR_LEN_BITS     6
+//`endif
+//`ifdef SPI_MAX_CHAR_32
+//  `define SPI_MAX_CHAR          32   // Can be set from 25 to 32 
+//  `define SPI_CHAR_LEN_BITS     5
+//`endif
+//`ifdef SPI_MAX_CHAR_24
+//  `define SPI_MAX_CHAR          24   // Can be set from 17 to 24 
+//  `define SPI_CHAR_LEN_BITS     5
+//`endif
+//`ifdef SPI_MAX_CHAR_16
+//  `define SPI_MAX_CHAR          16   // Can be set from 9 to 16 
+//  `define SPI_CHAR_LEN_BITS     4
+//`endif
+//`ifdef SPI_MAX_CHAR_8
+//  `define SPI_MAX_CHAR          8    // Can be set from 1 to 8 
+//  `define SPI_CHAR_LEN_BITS     3
+//`endif
+
+//
+// Number of device select signals. Use SPI_SS_NB for fine tuning the 
+// exact number.
+//
+//`define SPI_SS_NB_8
+//`define SPI_SS_NB_16
+//`define SPI_SS_NB_24
+//`define SPI_SS_NB_32
+//
+//`ifdef SPI_SS_NB_8
+//  `define SPI_SS_NB             8    // Can be set from 1 to 8
+//`endif
+//`ifdef SPI_SS_NB_16
+//  `define SPI_SS_NB             16   // Can be set from 9 to 16
+//`endif
+//`ifdef SPI_SS_NB_24
+//  `define SPI_SS_NB             24   // Can be set from 17 to 24
+//`endif
+//`ifdef SPI_SS_NB_32
+//  `define SPI_SS_NB             32   // Can be set from 25 to 32
+//`endif
+
+//
+// Bits of WISHBONE address used for partial decoding of SPI registers.
+//
+`define SPI_OFS_BITS	          4:2
+
+//
+// Register offset
+//
+`define SPI_RX_0                0
+`define SPI_RX_1                1
+`define SPI_RX_2                2
+`define SPI_RX_3                3
+`define SPI_TX_0                0
+`define SPI_TX_1                1
+`define SPI_TX_2                2
+`define SPI_TX_3                3
+`define SPI_CTRL                4
+`define SPI_DEVIDE              5
+`define SPI_SS                  6
+
+//
+// Number of bits in ctrl register
+//
+`define SPI_CTRL_BIT_NB         14
+
+//
+// Control register bit position
+//
+`define SPI_CTRL_ASS            13
+`define SPI_CTRL_IE             12
+`define SPI_CTRL_LSB            11
+`define SPI_CTRL_TX_NEGEDGE     10
+`define SPI_CTRL_RX_NEGEDGE     9
+`define SPI_CTRL_GO             8
+`define SPI_CTRL_RES_1          7
+`define SPI_CTRL_CHAR_LEN       6:0
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
new file mode 100644
index 000000000..60d4ecbd1
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
@@ -0,0 +1,2 @@
+`timescale 1ns / 10ps
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
new file mode 100644
index 000000000..c2bb19ea4
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
@@ -0,0 +1,99 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for Simple Wishbone UART
+---------------------------------------------------------------------------------------
+-- File           : simple_uart_pkg.vhd
+-- Author         : auto-generated by wbgen2 from simple_uart_wb.wb
+-- Created        : Tue Aug 15 10:16:30 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package uart_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_uart_in_registers is record
+    sr_tx_busy_i                             : std_logic;
+    sr_rx_rdy_i                              : std_logic;
+    rdr_rx_data_i                            : std_logic_vector(7 downto 0);
+    host_tdr_rdy_i                           : std_logic;
+    host_rdr_data_i                          : std_logic_vector(7 downto 0);
+    host_rdr_rdy_i                           : std_logic;
+    host_rdr_count_i                         : std_logic_vector(15 downto 0);
+    end record;
+  
+  constant c_uart_in_registers_init_value: t_uart_in_registers := (
+    sr_tx_busy_i => '0',
+    sr_rx_rdy_i => '0',
+    rdr_rx_data_i => (others => '0'),
+    host_tdr_rdy_i => '0',
+    host_rdr_data_i => (others => '0'),
+    host_rdr_rdy_i => '0',
+    host_rdr_count_i => (others => '0')
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_uart_out_registers is record
+      bcr_o                                    : std_logic_vector(31 downto 0);
+      bcr_wr_o                                 : std_logic;
+      tdr_tx_data_o                            : std_logic_vector(7 downto 0);
+      tdr_tx_data_wr_o                         : std_logic;
+      host_tdr_data_o                          : std_logic_vector(7 downto 0);
+      host_tdr_data_wr_o                       : std_logic;
+      end record;
+    
+    constant c_uart_out_registers_init_value: t_uart_out_registers := (
+      bcr_o => (others => '0'),
+      bcr_wr_o => '0',
+      tdr_tx_data_o => (others => '0'),
+      tdr_tx_data_wr_o => '0',
+      host_tdr_data_o => (others => '0'),
+      host_tdr_data_wr_o => '0'
+      );
+    function "or" (left, right: t_uart_in_registers) return t_uart_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body uart_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if x(i) = '1' then
+tmp(i):= '1';
+else
+tmp(i):= '0';
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_uart_in_registers) return t_uart_in_registers is
+variable tmp: t_uart_in_registers;
+begin
+tmp.sr_tx_busy_i := f_x_to_zero(left.sr_tx_busy_i) or f_x_to_zero(right.sr_tx_busy_i);
+tmp.sr_rx_rdy_i := f_x_to_zero(left.sr_rx_rdy_i) or f_x_to_zero(right.sr_rx_rdy_i);
+tmp.rdr_rx_data_i := f_x_to_zero(left.rdr_rx_data_i) or f_x_to_zero(right.rdr_rx_data_i);
+tmp.host_tdr_rdy_i := f_x_to_zero(left.host_tdr_rdy_i) or f_x_to_zero(right.host_tdr_rdy_i);
+tmp.host_rdr_data_i := f_x_to_zero(left.host_rdr_data_i) or f_x_to_zero(right.host_rdr_data_i);
+tmp.host_rdr_rdy_i := f_x_to_zero(left.host_rdr_rdy_i) or f_x_to_zero(right.host_rdr_rdy_i);
+tmp.host_rdr_count_i := f_x_to_zero(left.host_rdr_count_i) or f_x_to_zero(right.host_rdr_count_i);
+return tmp;
+end function;
+end package body;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
new file mode 100644
index 000000000..62d09a5c1
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
@@ -0,0 +1,315 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for Simple Wishbone UART
+---------------------------------------------------------------------------------------
+-- File           : simple_uart_wb.vhd
+-- Author         : auto-generated by wbgen2 from simple_uart_wb.wb
+-- Created        : Tue Aug 15 10:16:30 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.uart_wbgen2_pkg.all;
+
+
+entity simple_uart_wb is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(2 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    rdr_rack_o                               : out    std_logic;
+    host_rack_o                              : out    std_logic;
+    regs_i                                   : in     t_uart_in_registers;
+    regs_o                                   : out    t_uart_out_registers
+  );
+end simple_uart_wb;
+
+architecture syn of simple_uart_wb is
+
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal rwaddr_reg                               : std_logic_vector(2 downto 0);
+signal ack_in_progress                          : std_logic      ;
+
+begin
+-- Some internal signals assignments
+  wrdata_reg <= wb_dat_i;
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      regs_o.bcr_wr_o <= '0';
+      regs_o.tdr_tx_data_wr_o <= '0';
+      rdr_rack_o <= '0';
+      regs_o.host_tdr_data_wr_o <= '0';
+      host_rack_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          regs_o.bcr_wr_o <= '0';
+          regs_o.tdr_tx_data_wr_o <= '0';
+          rdr_rack_o <= '0';
+          regs_o.host_tdr_data_wr_o <= '0';
+          host_rack_o <= '0';
+          ack_in_progress <= '0';
+        else
+          regs_o.bcr_wr_o <= '0';
+          regs_o.tdr_tx_data_wr_o <= '0';
+          regs_o.host_tdr_data_wr_o <= '0';
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(2 downto 0) is
+          when "000" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(0) <= regs_i.sr_tx_busy_i;
+            rddata_reg(1) <= regs_i.sr_rx_rdy_i;
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001" => 
+            if (wb_we_i = '1') then
+              regs_o.bcr_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010" => 
+            if (wb_we_i = '1') then
+              regs_o.tdr_tx_data_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(7 downto 0) <= regs_i.rdr_rx_data_i;
+            rdr_rack_o <= '1';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "100" => 
+            if (wb_we_i = '1') then
+              regs_o.host_tdr_data_wr_o <= '1';
+            end if;
+            rddata_reg(8) <= regs_i.host_tdr_rdy_i;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(7 downto 0) <= regs_i.host_rdr_data_i;
+            host_rack_o <= '1';
+            rddata_reg(8) <= regs_i.host_rdr_rdy_i;
+            rddata_reg(24 downto 9) <= regs_i.host_rdr_count_i;
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- TX busy
+-- RX ready
+-- Baudrate divider setting
+-- pass-through field: Baudrate divider setting in register: Baudrate control register
+  regs_o.bcr_o <= wrdata_reg(31 downto 0);
+-- Transmit data
+-- pass-through field: Transmit data in register: Transmit data regsiter
+  regs_o.tdr_tx_data_o <= wrdata_reg(7 downto 0);
+-- Received data
+-- TX Data
+-- pass-through field: TX Data in register: Host VUART Tx register
+  regs_o.host_tdr_data_o <= wrdata_reg(7 downto 0);
+-- TX Ready
+-- RX Data
+-- RX Ready
+-- RX FIFO Count
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
new file mode 100644
index 000000000..ea996e08e
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
@@ -0,0 +1,229 @@
+------------------------------------------------------------------------------
+-- Title      : Simple Wishbone UART - receiver
+-- Project    : General Cores Collection (gencores) library
+------------------------------------------------------------------------------
+-- File       : uart_async_rx.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity uart_async_rx is
+
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    baud8_tick_i: in std_logic;
+
+    rxd_i      : in  std_logic;
+    rx_ready_o : out std_logic;
+    rx_error_o : out std_logic;
+    rx_data_o  : out std_logic_vector(7 downto 0)
+
+    );
+
+end uart_async_rx;
+
+
+architecture behavioral of uart_async_rx is
+
+  signal Baud8Tick : std_logic;
+  
+  signal RxD_sync_inv      : std_logic_vector(1 downto 0);
+  signal RxD_cnt_inv       : unsigned(1 downto 0);
+  signal RxD_bit_inv       : std_logic;
+
+  signal state       : std_logic_vector(3 downto 0);
+  signal bit_spacing : std_logic_vector(3 downto 0);
+  signal next_bit    : std_logic;
+
+  signal RxD_data       : std_logic_vector(7 downto 0);
+  signal RxD_data_ready : std_logic;
+  signal RxD_data_error : std_logic;
+
+  
+
+begin  -- behavioral
+
+  Baud8Tick <= baud8_tick_i;
+               
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        RxD_sync_inv <= (others => '0');
+      else
+        if(Baud8Tick = '1') then
+          RxD_sync_inv <= RxD_sync_inv(0) & (not rxd_i);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        RxD_bit_inv <= '0';
+        RxD_cnt_inv <= (others => '0');
+      else
+        if(Baud8Tick = '1') then
+          if(RxD_sync_inv(1) = '1' and RxD_cnt_inv /= "11") then
+            RxD_cnt_inv <= RxD_cnt_inv + 1;
+          elsif (RxD_sync_inv(1) = '0' and RxD_cnt_inv /= "00") then
+            RxD_cnt_inv <= RxD_cnt_inv - 1;
+          end if;
+
+          if(RxD_cnt_inv = "00") then
+            RxD_bit_inv <= '0';
+          elsif(RxD_cnt_inv = "11") then
+            RxD_bit_inv <= '1';
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+  next_bit <= '1' when (bit_spacing = x"a") else '0';
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        bit_spacing <= (others => '0');
+      else
+        if(state = x"0") then
+          bit_spacing <= "0000";
+        elsif(Baud8Tick = '1') then
+--          bit_spacing <= std_logic_vector(resize((unsigned(bit_spacing(2 downto 0)) + 1), 4))
+          bit_spacing <= std_logic_vector(unsigned('0' & bit_spacing(2 downto 0)) + 1)
+                         or (bit_spacing(3) & "000");
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state <= (others => '0');
+      else
+        if(Baud8Tick = '1') then
+          case state is
+            when "0000" =>
+              if(RxD_bit_inv = '1') then  -- start bit
+                state <= "1000";
+              end if;
+            when "1000" =>
+              if(next_bit = '1') then
+                state <= "1001";          -- bit 0
+              end if;
+            when "1001" =>
+              if(next_bit = '1') then
+                state <= "1010";          -- bit 1
+              end if;
+            when "1010" =>
+              if(next_bit = '1') then
+                state <= "1011";          -- bit 2
+              end if;
+            when "1011" =>
+              if(next_bit = '1') then
+                state <= "1100";          -- bit 3
+              end if;
+            when "1100" =>
+              if(next_bit = '1') then
+                state <= "1101";          -- bit 4
+              end if;
+            when "1101" =>
+              if(next_bit = '1') then
+                state <= "1110";          -- bit 5
+              end if;
+            when "1110" =>
+              if(next_bit = '1') then
+                state <= "1111";          -- bit 6
+              end if;
+            when "1111" =>
+              if(next_bit = '1') then
+                state <= "0001";          -- bit 7
+              end if;
+            when "0001" =>
+              if(next_bit = '1') then
+                state <= "0000";          -- bit stop
+              end if;
+            when others => state <= "0000";
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        RxD_data <= (others => '0');
+      else
+        if(Baud8Tick = '1' and next_bit = '1' and state(3) = '1') then
+          RxD_data <= (not RxD_bit_inv) & RxD_data(7 downto 1);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        RxD_data_error <= '0';
+        RxD_data_ready <= '0';
+      else
+        if(Baud8Tick = '1' and next_bit = '1' and state = "0001" and RxD_bit_inv = '0') then
+          RxD_data_ready <= '1';
+        else
+          RxD_data_ready <= '0';
+        end if;
+
+        if(Baud8Tick = '1' and next_bit = '1' and state = "0001" and RxD_bit_inv = '1') then
+          RxD_data_error <= '1';
+        else
+          RxD_data_error <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  rx_data_o <= RxD_data;
+  rx_ready_o  <= RxD_data_ready;
+  rx_error_o <= RxD_data_error;
+  
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
new file mode 100644
index 000000000..d0a743f39
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
@@ -0,0 +1,190 @@
+------------------------------------------------------------------------------
+-- Title      : Simple Wishbone UART - tranmitter
+-- Project    : General Cores Collection (gencores) library
+------------------------------------------------------------------------------
+-- File       : uart_async_tx.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity uart_async_tx is
+  
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    baud_tick_i: in std_logic;
+    
+    txd_o        : out std_logic;
+    tx_start_p_i : in  std_logic;
+    tx_data_i    : in  std_logic_vector(7 downto 0);
+    tx_busy_o    : out std_logic
+
+    );
+
+end uart_async_tx;
+
+architecture behavioral of uart_async_tx is
+
+signal BaudTick : std_logic;
+  signal TxD_busy         : std_logic;
+  signal TxD_ready        : std_logic;
+  signal state            : std_logic_vector(3 downto 0);
+
+  signal TxD_dataReg : std_logic_vector(7 downto 0);
+  signal TxD_dataD   : std_logic_vector(7 downto 0);
+  signal muxbit      : std_logic;
+  signal TxD         : std_logic;
+
+begin  -- behavioral
+
+
+
+
+  TxD_ready <= '1' when state = "0000" else '0';
+  TxD_busy  <= not TxD_ready;
+  BaudTick  <= baud_tick_i;
+  
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        TxD_dataReg <= (others => '0');
+      elsif TxD_ready = '1' and tx_start_p_i = '1' then
+        TxD_dataReg <= tx_data_i;
+      end if;
+    end if;
+  end process;
+
+  TxD_dataD <= TxD_dataReg;
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state <= "0000";
+      else
+        case state is
+          when "0000" =>
+            if (tx_start_p_i = '1') then
+              state <= "0001";
+            end if;
+
+          when "0001" =>
+            if (BaudTick = '1') then
+              state <= "0100";
+            end if;
+          when "0100" =>
+            if (BaudTick = '1') then
+              state <= "1000";
+            end if;
+          when "1000" =>
+            if (BaudTick = '1') then
+              state <= "1001";
+            end if;
+          when "1001" =>
+            if (BaudTick = '1') then
+              state <= "1010";
+            end if;
+
+          when "1010" =>
+            if (BaudTick = '1') then
+              state <= "1011";
+            end if;
+          when "1011" =>
+            if (BaudTick = '1') then
+              state <= "1100";
+            end if;
+          when "1100" =>
+            if (BaudTick = '1') then
+              state <= "1101";
+            end if;
+          when "1101" =>
+            if (BaudTick = '1') then
+              state <= "1110";
+            end if;
+          when "1110" =>
+            if (BaudTick = '1') then
+              state <= "1111";
+            end if;
+
+          when "1111" =>
+            if (BaudTick = '1') then
+              state <= "0010";
+            end if;
+          when "0010" =>
+            if (BaudTick = '1') then
+              state <= "0011";
+            end if;
+
+          when "0011" =>
+            if (BaudTick = '1') then
+              state <= "0000";
+            end if;
+          when others =>
+            state <= "0000";
+        end case;
+      end if;
+    end if;
+  end process;
+
+
+  process(TxD_dataD, state)
+  begin
+    case state(2 downto 0) is
+      when "000"      => muxbit <= TxD_dataD(0);
+      when "001"      => muxbit <= TxD_dataD(1);
+      when "010"      => muxbit <= TxD_dataD(2);
+      when "011"      => muxbit <= TxD_dataD(3);
+      when "100"      => muxbit <= TxD_dataD(4);
+      when "101"      => muxbit <= TxD_dataD(5);
+      when "110"      => muxbit <= TxD_dataD(6);
+      when "111"      => muxbit <= TxD_dataD(7);
+      when others => null;
+    end case;
+  end process;
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        TxD <= '1';
+      else
+        if(unsigned(state) < to_unsigned(4, state'length) or (state(3) = '1' and muxbit = '1')) then
+          TxD <= '1';
+        else
+          TxD <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  txd_o      <= TxD;
+  tx_busy_o <= TxD_busy;
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
new file mode 100644
index 000000000..a565c5c20
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
@@ -0,0 +1,89 @@
+------------------------------------------------------------------------------
+-- Title      : Simple Wishbone UART - baud generator
+-- Project    : General Cores Collection (gencores) library
+------------------------------------------------------------------------------
+-- File       : uart_baud_gen.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity uart_baud_gen is
+  
+  generic (
+    g_baud_acc_width : integer := 16);
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    baudrate_i : in std_logic_vector(g_baud_acc_width  downto 0);
+
+    baud_tick_o  : out std_logic;
+    baud8_tick_o : out std_logic);
+
+end uart_baud_gen;
+
+architecture behavioral of uart_baud_gen is
+
+  signal Baud8GeneratorInc : unsigned(g_baud_acc_width downto 0);
+  signal Baud8GeneratorAcc : unsigned(g_baud_acc_width downto 0);
+  signal Baud8Tick         : std_logic;
+  signal Baud_sreg         : std_logic_vector(7 downto 0) := "10000000";
+  
+  
+begin  -- behavioral
+
+  Baud8GeneratorInc <= unsigned(baudrate_i);
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        Baud8GeneratorAcc <= (others => '0');
+      else
+        Baud8GeneratorAcc <= ('0' & Baud8GeneratorAcc(Baud8GeneratorAcc'high-1 downto 0)) + Baud8GeneratorInc;
+      end if;
+    end if;
+  end process;
+
+  Baud8Tick <= std_logic(Baud8GeneratorAcc(g_baud_acc_width));
+
+  process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        Baud_sreg <= "10000000";
+      elsif Baud8Tick = '1' then
+        Baud_sreg <= Baud_sreg(0) & Baud_sreg(7 downto 1);
+      end if;
+    end if;
+  end process;
+
+  baud_tick_o  <= Baud_sreg(0) and Baud8Tick;
+  baud8_tick_o <= Baud8Tick;
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
new file mode 100644
index 000000000..75379bf69
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
@@ -0,0 +1,323 @@
+-------------------------------------------------------------------------------
+-- Title      : Simple Wishbone UART
+-- Project    : General Cores Collection (gencores) library
+-------------------------------------------------------------------------------
+-- File       : wb_simple_uart.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2011-02-21
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generics
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: A simple UART controller, providing two modes of operation
+-- (both can be used simultenously):
+-- - physical UART (encoding fixed to 8 data bits, no parity and one stop bit)
+-- - virtual UART: TXed data is passed via a FIFO to the Wishbone host (and
+--   vice versa).
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-02-21  1.0      twlostow        Created
+-- 2011-10-04  1.1      twlostow        merged with VUART, added adapter
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.genram_pkg.all;
+use work.wishbone_pkg.all;
+use work.UART_wbgen2_pkg.all;
+
+entity wb_simple_uart is
+  generic(
+    g_with_virtual_uart   : boolean;
+    g_with_physical_uart  : boolean;
+    g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity : t_wishbone_address_granularity := WORD;
+    g_vuart_fifo_size     : integer := 1024
+    );
+  port (
+
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    wb_adr_i   : in  std_logic_vector(4 downto 0);
+    wb_dat_i   : in  std_logic_vector(31 downto 0);
+    wb_dat_o   : out std_logic_vector(31 downto 0);
+    wb_cyc_i   : in  std_logic;
+    wb_sel_i   : in  std_logic_vector(3 downto 0);
+    wb_stb_i   : in  std_logic;
+    wb_we_i    : in  std_logic;
+    wb_ack_o   : out std_logic;
+    wb_stall_o : out std_logic;
+
+    uart_rxd_i : in  std_logic;
+    uart_txd_o : out std_logic
+    );
+end wb_simple_uart;
+
+architecture syn of wb_simple_uart is
+
+  constant c_baud_acc_width  : integer := 16;
+
+  component uart_baud_gen
+    generic (
+      g_baud_acc_width : integer);
+    port (
+      clk_sys_i    : in  std_logic;
+      rst_n_i      : in  std_logic;
+      baudrate_i   : in  std_logic_vector(g_baud_acc_width downto 0);
+      baud_tick_o  : out std_logic;
+      baud8_tick_o : out std_logic);
+  end component;
+
+  component uart_async_rx
+    port (
+      clk_sys_i    : in  std_logic;
+      rst_n_i      : in  std_logic;
+      baud8_tick_i : in  std_logic;
+      rxd_i        : in  std_logic;
+      rx_ready_o   : out std_logic;
+      rx_error_o   : out std_logic;
+      rx_data_o    : out std_logic_vector(7 downto 0));
+  end component;
+
+  component uart_async_tx
+    port (
+      clk_sys_i    : in  std_logic;
+      rst_n_i      : in  std_logic;
+      baud_tick_i  : in  std_logic;
+      txd_o        : out std_logic;
+      tx_start_p_i : in  std_logic;
+      tx_data_i    : in  std_logic_vector(7 downto 0);
+      tx_busy_o    : out std_logic);
+  end component;
+
+  component simple_uart_wb
+    port (
+      rst_n_i     : in  std_logic;
+      clk_sys_i   : in  std_logic;
+      wb_adr_i    : in  std_logic_vector(2 downto 0);
+      wb_dat_i    : in  std_logic_vector(31 downto 0);
+      wb_dat_o    : out std_logic_vector(31 downto 0);
+      wb_cyc_i    : in  std_logic;
+      wb_sel_i    : in  std_logic_vector(3 downto 0);
+      wb_stb_i    : in  std_logic;
+      wb_we_i     : in  std_logic;
+      wb_ack_o    : out std_logic;
+      wb_stall_o  : out std_logic;
+      rdr_rack_o  : out std_logic;
+      host_rack_o : out std_logic;
+      regs_i      : in  t_uart_in_registers;
+      regs_o      : out t_uart_out_registers
+    );
+  end component;
+
+  signal rx_ready_reg    : std_logic;
+  signal rx_ready        : std_logic;
+  signal uart_bcr        : std_logic_vector(31 downto 0);
+
+  signal rdr_rack         : std_logic;
+  signal host_rack : std_logic;
+
+  signal baud_tick  : std_logic;
+  signal baud_tick8 : std_logic;
+
+  signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
+
+  signal wb_in  : t_wishbone_slave_in;
+  signal wb_out : t_wishbone_slave_out;
+
+  signal regs_in  : t_UART_in_registers;
+  signal regs_out : t_UART_out_registers;
+
+  signal fifo_empty, fifo_full, fifo_rd, fifo_wr : std_logic;
+  signal fifo_count                              : std_logic_vector(f_log2_size(g_vuart_fifo_size)-1 downto 0);
+
+  signal phys_rx_ready, phys_tx_busy : std_logic;
+  
+  signal phys_rx_data : std_logic_vector(7 downto 0);
+  
+  
+begin  -- syn
+
+  gen_check_generics : if(not g_with_physical_uart and not g_with_virtual_uart) generate
+    assert false report "wb_simple_uart: dummy configuration (use virtual, physical or both uarts)" severity failure;
+  end generate gen_check_generics;
+
+  resized_addr(4 downto 0)                          <= wb_adr_i;
+  resized_addr(c_wishbone_address_width-1 downto 5) <= (others => '0');
+
+  U_Adapter : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => false,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      master_i   => wb_out,
+      master_o   => wb_in,
+      sl_adr_i   => resized_addr,
+      sl_dat_i   => wb_dat_i,
+      sl_sel_i   => wb_sel_i,
+      sl_cyc_i   => wb_cyc_i,
+      sl_stb_i   => wb_stb_i,
+      sl_we_i    => wb_we_i,
+      sl_dat_o   => wb_dat_o,
+      sl_ack_o   => wb_ack_o,
+      sl_stall_o => wb_stall_o);
+
+  U_WB_SLAVE : simple_uart_wb
+    port map (
+      rst_n_i    => rst_n_i,
+      clk_sys_i  => clk_sys_i,
+      wb_adr_i   => wb_in.adr(2 downto 0),
+      wb_dat_i   => wb_in.dat,
+      wb_dat_o   => wb_out.dat,
+      wb_cyc_i   => wb_in.cyc,
+      wb_sel_i   => wb_in.sel,
+      wb_stb_i   => wb_in.stb,
+      wb_we_i    => wb_in.we,
+      wb_ack_o   => wb_out.ack,
+      wb_stall_o => wb_out.stall,
+
+      rdr_rack_o  => rdr_rack,
+      host_rack_o => host_rack,
+      regs_o      => regs_out,
+      regs_i      => regs_in);
+
+  wb_out.err <= '0';
+  wb_out.rty <= '0';
+  wb_out.int <= '0';
+
+  gen_phys_uart : if(g_with_physical_uart) generate
+
+    p_bcr_reg : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_n_i = '0' then
+          uart_bcr <= (others => '0');
+        elsif(regs_out.bcr_wr_o = '1')then
+          uart_bcr <= regs_out.bcr_o;
+        end if;
+      end if;
+    end process;
+
+    U_BAUD_GEN : uart_baud_gen
+      generic map (
+        g_baud_acc_width => c_baud_acc_width)
+      port map (
+        clk_sys_i    => clk_sys_i,
+        rst_n_i      => rst_n_i,
+        baudrate_i   => uart_bcr(c_baud_acc_width downto 0),
+        baud_tick_o  => baud_tick,
+        baud8_tick_o => baud_tick8);
+
+    U_TX : uart_async_tx
+      port map (
+        clk_sys_i    => clk_sys_i,
+        rst_n_i      => rst_n_i,
+        baud_tick_i  => baud_tick,
+        txd_o        => uart_txd_o,
+        tx_start_p_i => regs_out.tdr_tx_data_wr_o,
+        tx_data_i    => regs_out.tdr_tx_data_o,
+        tx_busy_o    => phys_tx_busy);
+
+    U_RX : uart_async_rx
+      port map (
+        clk_sys_i    => clk_sys_i,
+        rst_n_i      => rst_n_i,
+        baud8_tick_i => baud_tick8,
+        rxd_i        => uart_rxd_i,
+        rx_ready_o   => phys_rx_ready,
+        rx_error_o   => open,
+        rx_data_o    => phys_rx_data);
+
+  end generate gen_phys_uart;
+  
+  gen_vuart : if(g_with_virtual_uart) generate
+
+    fifo_wr <= not fifo_full and regs_out.tdr_tx_data_wr_o;
+    fifo_rd <= not fifo_empty and not regs_in.host_rdr_rdy_i;
+
+    U_VUART_FIFO : generic_sync_fifo
+      generic map (
+        g_data_width => 8,
+        g_size       => g_vuart_fifo_size,
+        g_with_count => true)
+      port map (
+        rst_n_i => rst_n_i,
+        clk_i   => clk_sys_i,
+        d_i     => regs_out.tdr_tx_data_o,
+        we_i    => fifo_wr,
+        q_o     => regs_in.host_rdr_data_i,
+        rd_i    => fifo_rd,
+        empty_o => fifo_empty,
+        full_o  => fifo_full,
+        count_o => fifo_count);
+
+    regs_in.host_rdr_count_i(fifo_count'left downto 0)    <= fifo_count;
+    regs_in.host_rdr_count_i(15 downto fifo_count'length) <= (others => '0');
+
+    p_vuart_rx_ready : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_n_i = '0' then
+          regs_in.host_rdr_rdy_i <= '0';
+        elsif(fifo_rd = '1') then
+          regs_in.host_rdr_rdy_i <= '1';
+        elsif(host_rack = '1') then
+          regs_in.host_rdr_rdy_i <= '0';
+        end if;
+      end if;
+    end process;
+
+  end generate gen_vuart;
+
+  p_drive_rx_ready : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        regs_in.sr_rx_rdy_i   <= '0';
+        regs_in.rdr_rx_data_i <= (others => '0');
+      else
+        if(rdr_rack = '1' and phys_rx_ready = '0' and regs_out.host_tdr_data_wr_o = '0') then
+          regs_in.sr_rx_rdy_i <= '0';
+        elsif(phys_rx_ready = '1' and g_with_physical_uart) then
+          regs_in.sr_rx_rdy_i   <= '1';
+          regs_in.rdr_rx_data_i <= phys_rx_data;
+        elsif(regs_out.host_tdr_data_wr_o = '1' and g_with_virtual_uart) then
+          regs_in.sr_rx_rdy_i   <= '1';
+          regs_in.rdr_rx_data_i <= regs_out.host_tdr_data_o;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  regs_in.sr_tx_busy_i <= phys_tx_busy when (g_with_physical_uart) else '0';
+  regs_in.host_tdr_rdy_i <= not regs_in.sr_rx_rdy_i;
+  
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
new file mode 100644
index 000000000..5914773d2
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
@@ -0,0 +1,129 @@
+------------------------------------------------------------------------------
+-- Title      : Simple Wishbone UART
+-- Project    : General Cores Collection (gencores) library
+------------------------------------------------------------------------------
+-- File       : xwb_simple_uart.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-05-18
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: A simple UART controller, providing two modes of operation
+-- (both can be used simultenously):
+-- - physical UART (encoding fixed to 8 data bits, no parity and one stop bit)
+-- - virtual UART: TXed data is passed via a FIFO to the Wishbone host (and
+--   vice versa).
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2010-05-18  1.0      twlostow        Created
+-- 2011-10-04  1.1      twlostow        xwb module
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.wishbone_pkg.all;
+
+entity xwb_simple_uart is
+  generic(
+    g_with_virtual_uart   : boolean := true;
+    g_with_physical_uart  : boolean := true;
+    g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity : t_wishbone_address_granularity := WORD;
+    g_vuart_fifo_size     : integer := 1024
+    );
+
+  port(
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    -- Wishbone
+    slave_i : in  t_wishbone_slave_in;
+    slave_o : out t_wishbone_slave_out;
+    desc_o  : out t_wishbone_device_descriptor;
+
+    uart_rxd_i: in std_logic;
+    uart_txd_o: out std_logic
+
+    );
+
+end xwb_simple_uart;
+
+architecture rtl of xwb_simple_uart is
+
+  component wb_simple_uart
+    generic (
+      g_with_virtual_uart   : boolean;
+      g_with_physical_uart  : boolean;
+      g_interface_mode      : t_wishbone_interface_mode;
+      g_address_granularity : t_wishbone_address_granularity;
+      g_vuart_fifo_size     : integer);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(4 downto 0);
+      wb_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_dat_o   : out std_logic_vector(31 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_stall_o : out std_logic;
+      uart_rxd_i : in  std_logic;
+      uart_txd_o : out std_logic);
+  end component;
+  
+begin  -- rtl
+
+  U_Wrapped_UART: wb_simple_uart
+    generic map (
+      g_with_virtual_uart   => g_with_virtual_uart,
+      g_with_physical_uart  => g_with_physical_uart,
+      g_interface_mode      => g_interface_mode,
+      g_address_granularity => g_address_granularity,
+      g_vuart_fifo_size     => g_vuart_fifo_size)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      wb_adr_i   => slave_i.adr(4 downto 0),
+      wb_dat_i   => slave_i.dat,
+      wb_dat_o   => slave_o.dat,
+      wb_cyc_i   => slave_i.cyc,
+      wb_sel_i   => slave_i.sel,
+      wb_stb_i   => slave_i.stb,
+      wb_we_i    => slave_i.we,
+      wb_ack_o   => slave_o.ack,
+      wb_stall_o => slave_o.stall,
+      uart_rxd_i => uart_rxd_i,
+      uart_txd_o => uart_txd_o);
+
+  slave_o.err <= '0';
+  slave_o.rty <= '0';
+  slave_o.int <='0';
+
+  desc_o <= (others => '0');
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
new file mode 100644
index 000000000..7962e6b6f
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
@@ -0,0 +1,241 @@
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_eic.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+use work.wbgen2_pkg.all;
+
+entity wbgen2_eic is
+  
+  generic (
+    g_num_interrupts : natural := 1;
+
+    g_irq00_mode : integer := 0;
+    g_irq01_mode : integer := 0;
+    g_irq02_mode : integer := 0;
+    g_irq03_mode : integer := 0;
+    g_irq04_mode : integer := 0;
+    g_irq05_mode : integer := 0;
+    g_irq06_mode : integer := 0;
+    g_irq07_mode : integer := 0;
+    g_irq08_mode : integer := 0;
+    g_irq09_mode : integer := 0;
+    g_irq0a_mode : integer := 0;
+    g_irq0b_mode : integer := 0;
+    g_irq0c_mode : integer := 0;
+    g_irq0d_mode : integer := 0;
+    g_irq0e_mode : integer := 0;
+    g_irq0f_mode : integer := 0;
+    g_irq10_mode : integer := 0;
+    g_irq11_mode : integer := 0;
+    g_irq12_mode : integer := 0;
+    g_irq13_mode : integer := 0;
+    g_irq14_mode : integer := 0;
+    g_irq15_mode : integer := 0;
+    g_irq16_mode : integer := 0;
+    g_irq17_mode : integer := 0;
+    g_irq18_mode : integer := 0;
+    g_irq19_mode : integer := 0;
+    g_irq1a_mode : integer := 0;
+    g_irq1b_mode : integer := 0;
+    g_irq1c_mode : integer := 0;
+    g_irq1d_mode : integer := 0;
+    g_irq1e_mode : integer := 0;
+    g_irq1f_mode : integer := 0
+    );
+  port(
+    rst_n_i : in std_logic;             -- reset & system clock, as always :)
+    clk_i   : in std_logic;
+
+    -- raw interrupt inputs
+    irq_i : in std_logic_vector(g_num_interrupts-1 downto 0);  
+
+    -- interrupt acknowledge signal, used for level-active interrupts to
+    -- indicate that the interrupt has been handled
+    irq_ack_o: out std_logic_vector(g_num_interrupts-1 downto 0);  
+
+-- interrupt mask regsiter (slv/bus read-only)
+    reg_imr_o : out std_logic_vector(g_num_interrupts-1 downto 0);
+
+-- interrupt enable/disable registers (slv/bus pass-through)
+    reg_ier_i        : in std_logic_vector(g_num_interrupts-1 downto 0);
+    reg_ier_wr_stb_i : in std_logic;
+
+    reg_idr_i        : in std_logic_vector(g_num_interrupts-1 downto 0);
+    reg_idr_wr_stb_i : in std_logic;
+
+-- interrupt status register (slv/bus write with LOAD_EXT)
+    reg_isr_o        : out std_logic_vector(g_num_interrupts-1 downto 0);
+    reg_isr_i        : in  std_logic_vector(g_num_interrupts-1 downto 0);
+    reg_isr_wr_stb_i : in  std_logic;
+
+-- multiplexed wishbone irq output
+    wb_irq_o : out std_logic
+
+    );
+
+end wbgen2_eic;
+
+architecture syn of wbgen2_eic is
+
+  subtype t_irq_mode is integer;
+  type t_irq_mode_vec is array (0 to 31) of t_irq_mode;
+
+  constant c_IRQ_MODE_RISING_EDGE  : t_irq_mode := 0;
+  constant c_IRQ_MODE_FALLING_EDGE : t_irq_mode := 1;
+  constant c_IRQ_MODE_LEVEL_0      : t_irq_mode := 2;
+  constant c_IRQ_MODE_LEVEL_1      : t_irq_mode := 3;
+
+
+  signal irq_mode : t_irq_mode_vec;
+
+  signal irq_mask    : std_logic_vector(g_num_interrupts-1 downto 0);
+  signal irq_pending : std_logic_vector(g_num_interrupts-1 downto 0);
+
+  signal irq_i_d0 : std_logic_vector(g_num_interrupts-1 downto 0);
+  signal irq_i_d1 : std_logic_vector(g_num_interrupts-1 downto 0);
+  signal irq_i_d2 : std_logic_vector(g_num_interrupts-1 downto 0);
+  
+begin  -- syn
+
+  irq_mode(0)  <= g_irq00_mode;
+  irq_mode(1)  <= g_irq01_mode;
+  irq_mode(2)  <= g_irq02_mode;
+  irq_mode(3)  <= g_irq03_mode;
+  irq_mode(4)  <= g_irq04_mode;
+  irq_mode(5)  <= g_irq05_mode;
+  irq_mode(6)  <= g_irq06_mode;
+  irq_mode(7)  <= g_irq07_mode;
+  irq_mode(8)  <= g_irq08_mode;
+  irq_mode(9)  <= g_irq09_mode;
+  irq_mode(10) <= g_irq0a_mode;
+  irq_mode(11) <= g_irq0b_mode;
+  irq_mode(12) <= g_irq0c_mode;
+  irq_mode(13) <= g_irq0d_mode;
+  irq_mode(14) <= g_irq0e_mode;
+  irq_mode(15) <= g_irq0f_mode;
+  irq_mode(16) <= g_irq10_mode;
+  irq_mode(17) <= g_irq11_mode;
+  irq_mode(18) <= g_irq12_mode;
+  irq_mode(19) <= g_irq13_mode;
+  irq_mode(20) <= g_irq14_mode;
+  irq_mode(21) <= g_irq15_mode;
+  irq_mode(22) <= g_irq16_mode;
+  irq_mode(23) <= g_irq17_mode;
+  irq_mode(24) <= g_irq18_mode;
+  irq_mode(25) <= g_irq19_mode;
+  irq_mode(26) <= g_irq1a_mode;
+  irq_mode(27) <= g_irq1b_mode;
+  irq_mode(28) <= g_irq1c_mode;
+  irq_mode(29) <= g_irq1d_mode;
+  irq_mode(30) <= g_irq1e_mode;
+  irq_mode(31) <= g_irq1f_mode;
+
+
+  process(clk_i, rst_n_i)
+  begin
+    if(rst_n_i = '0') then
+      irq_i_d0    <= (others => '0');
+      irq_i_d1    <= (others => '0');
+      irq_i_d1    <= (others => '0');
+      irq_pending <= (others => '0');
+      irq_mask    <= (others => '0');
+      
+    elsif rising_edge(clk_i) then
+
+      for i in 0 to g_num_interrupts-1 loop
+        
+        irq_i_d0(i) <= irq_i(i);
+        irq_i_d1(i) <= irq_i_d0(i);
+        irq_i_d2(i) <= irq_i_d1(i);
+
+
+        if((reg_isr_i(i) = '1' and reg_isr_wr_stb_i = '1') or irq_mask(i) = '0') then
+          irq_pending(i) <= '0';
+          irq_i_d0(i) <= '0';
+          irq_i_d1(i) <= '0';
+          irq_i_d2(i) <= '0';
+        
+        else
+          
+          case irq_mode(i) is
+            when c_IRQ_MODE_LEVEL_0      => irq_pending(i) <= not irq_i_d2(i);
+            when c_IRQ_MODE_LEVEL_1      => irq_pending(i) <= irq_i_d2(i);
+            when c_IRQ_MODE_RISING_EDGE  => irq_pending(i) <= irq_pending(i) or ((not irq_i_d2(i)) and irq_i_d1(i));
+            when c_IRQ_MODE_FALLING_EDGE => irq_pending(i) <= irq_pending(i) or ((not irq_i_d1(i)) and irq_i_d2(i));
+            when others                  => null;
+          end case;
+        end if;
+      end loop;  -- i
+
+      if(reg_ier_wr_stb_i = '1') then
+        for i in 0 to g_num_interrupts-1 loop
+          if(reg_ier_i(i) = '1') then
+            irq_mask(i) <= '1';
+          end if;
+        end loop;
+      end if;
+
+      if(reg_idr_wr_stb_i = '1') then
+        for i in 0 to g_num_interrupts-1 loop
+          if(reg_idr_i(i) = '1') then
+            irq_mask(i) <= '0';
+          end if;
+        end loop;
+      end if;
+    end if;
+  end process;
+
+  -- generation of wb_irq_o
+
+  process(clk_i, rst_n_i)
+  begin
+    if(rst_n_i = '0') then
+      wb_irq_o <= '0';
+    elsif rising_edge(clk_i) then
+      if(irq_pending = std_logic_vector(to_unsigned(0, g_num_interrupts))) then
+        wb_irq_o <= '0';
+      else
+        wb_irq_o <= '1';
+      end if;
+      
+    end if;
+  end process;
+
+  gen_irq_ack: for i in 0 to g_num_interrupts-1 generate
+    irq_ack_o(i) <= '1' when (reg_isr_wr_stb_i = '1' and reg_isr_i(i) = '1') else '0';
+  end generate gen_irq_ack;
+
+  reg_imr_o <= irq_mask;
+  reg_isr_o <= irq_pending;
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
new file mode 100644
index 000000000..8905cc9dc
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
@@ -0,0 +1,144 @@
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_fifo_sync.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.wbgen2_pkg.all;
+
+
+entity wbgen2_fifo_sync is
+  generic (
+    g_width      : integer;
+    g_size       : integer;
+    g_usedw_size : integer);
+
+  port
+    (
+
+      clk_i     : in std_logic;
+      rst_n_i : in std_logic := '1';
+
+      wr_data_i : in std_logic_vector(g_width-1 downto 0);
+      wr_req_i  : in std_logic;
+
+      rd_data_o : out std_logic_vector(g_width-1 downto 0);
+      rd_req_i  : in  std_logic;
+
+      wr_empty_o : out std_logic;
+      wr_full_o  : out std_logic;
+      wr_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0);
+
+      rd_empty_o : out std_logic;
+      rd_full_o  : out std_logic;
+      rd_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0)
+
+      );
+end wbgen2_fifo_sync;
+
+
+architecture rtl of wbgen2_fifo_sync is
+
+
+  function f_log2_size (A : natural) return natural is
+  begin
+    for I in 1 to 64 loop               -- Works for up to 64 bits
+      if (2**I > A) then
+        return(I-1);
+      end if;
+    end loop;
+    return(63);
+  end function f_log2_size;
+
+  component generic_sync_fifo
+    generic (
+      g_data_width             : natural;
+      g_size                   : natural;
+      g_show_ahead             : boolean;
+      g_with_empty             : boolean;
+      g_with_full              : boolean;
+      g_with_almost_empty      : boolean;
+      g_with_almost_full       : boolean;
+      g_with_count             : boolean;
+      g_almost_empty_threshold : integer := 0;
+      g_almost_full_threshold  : integer := 0);
+    port (
+      rst_n_i        : in  std_logic := '1';
+      clk_i          : in  std_logic;
+      d_i            : in  std_logic_vector(g_data_width-1 downto 0);
+      we_i           : in  std_logic;
+      q_o            : out std_logic_vector(g_data_width-1 downto 0);
+      rd_i           : in  std_logic;
+      empty_o        : out std_logic;
+      full_o         : out std_logic;
+      almost_empty_o : out std_logic;
+      almost_full_o  : out std_logic;
+      count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
+  end component;
+  
+  signal empty_int : std_logic;
+  signal full_int : std_logic;
+  signal usedw_int : std_logic_vector(g_usedw_size-1 downto 0);
+  
+begin
+
+  wrapped_fifo: generic_sync_fifo
+    generic map (
+      g_data_width             => g_width,
+      g_size                   => g_size,
+      g_show_ahead             => false,
+      g_with_empty             => true,
+      g_with_full              => true,
+      g_with_almost_empty      => false,
+      g_with_almost_full       => false,
+      g_with_count             => true)
+    port map (
+      rst_n_i        => rst_n_i,
+      clk_i          => clk_i,
+      d_i            => wr_data_i,
+      we_i           => wr_req_i,
+      q_o            => rd_data_o,
+      rd_i           => rd_req_i,
+      empty_o        => empty_int,
+      full_o         => full_int,
+      almost_empty_o => open,
+      almost_full_o  => open,
+      count_o        => usedw_int);
+  
+
+  rd_empty_o <= empty_int;
+  rd_full_o <= full_int;
+  rd_usedw_o <= usedw_int;
+
+  wr_empty_o <= empty_int;
+  wr_full_o <= full_int;
+  wr_usedw_o <= usedw_int;
+  
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
new file mode 100644
index 000000000..aabce15a7
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
@@ -0,0 +1,154 @@
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_pkg.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2012 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package wbgen2_pkg is
+
+  
+  component wbgen2_dpssram
+    generic (
+      g_data_width : natural;
+      g_size       : natural;
+      g_addr_width : natural;
+      g_dual_clock : boolean;
+      g_use_bwsel  : boolean);
+    port (
+      clk_a_i   : in  std_logic;
+      clk_b_i   : in  std_logic;
+      addr_a_i  : in  std_logic_vector(g_addr_width-1 downto 0);
+      addr_b_i  : in  std_logic_vector(g_addr_width-1 downto 0);
+      data_a_i  : in  std_logic_vector(g_data_width-1 downto 0);
+      data_b_i  : in  std_logic_vector(g_data_width-1 downto 0);
+      data_a_o  : out std_logic_vector(g_data_width-1 downto 0);
+      data_b_o  : out std_logic_vector(g_data_width-1 downto 0);
+      bwsel_a_i : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+      bwsel_b_i : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+      rd_a_i    : in  std_logic;
+      rd_b_i    : in  std_logic;
+      wr_a_i    : in  std_logic;
+      wr_b_i    : in  std_logic);
+  end component;
+
+
+  component wbgen2_eic
+    generic (
+      g_num_interrupts : natural;
+      g_irq00_mode     : integer;
+      g_irq01_mode     : integer;
+      g_irq02_mode     : integer;
+      g_irq03_mode     : integer;
+      g_irq04_mode     : integer;
+      g_irq05_mode     : integer;
+      g_irq06_mode     : integer;
+      g_irq07_mode     : integer;
+      g_irq08_mode     : integer;
+      g_irq09_mode     : integer;
+      g_irq0a_mode     : integer;
+      g_irq0b_mode     : integer;
+      g_irq0c_mode     : integer;
+      g_irq0d_mode     : integer;
+      g_irq0e_mode     : integer;
+      g_irq0f_mode     : integer;
+      g_irq10_mode     : integer;
+      g_irq11_mode     : integer;
+      g_irq12_mode     : integer;
+      g_irq13_mode     : integer;
+      g_irq14_mode     : integer;
+      g_irq15_mode     : integer;
+      g_irq16_mode     : integer;
+      g_irq17_mode     : integer;
+      g_irq18_mode     : integer;
+      g_irq19_mode     : integer;
+      g_irq1a_mode     : integer;
+      g_irq1b_mode     : integer;
+      g_irq1c_mode     : integer;
+      g_irq1d_mode     : integer;
+      g_irq1e_mode     : integer;
+      g_irq1f_mode     : integer);
+    port (
+      rst_n_i          : in  std_logic;
+      clk_i            : in  std_logic;
+      irq_i            : in  std_logic_vector(g_num_interrupts-1 downto 0);
+      irq_ack_o        : out std_logic_vector(g_num_interrupts-1 downto 0);
+      reg_imr_o        : out std_logic_vector(g_num_interrupts-1 downto 0);
+      reg_ier_i        : in  std_logic_vector(g_num_interrupts-1 downto 0);
+      reg_ier_wr_stb_i : in  std_logic;
+      reg_idr_i        : in  std_logic_vector(g_num_interrupts-1 downto 0);
+      reg_idr_wr_stb_i : in  std_logic;
+      reg_isr_o        : out std_logic_vector(g_num_interrupts-1 downto 0);
+      reg_isr_i        : in  std_logic_vector(g_num_interrupts-1 downto 0);
+      reg_isr_wr_stb_i : in  std_logic;
+      wb_irq_o         : out std_logic);
+  end component;
+
+  component wbgen2_fifo_async
+    generic (
+      g_size       : integer;
+      g_width      : integer;
+      g_usedw_size : integer);
+    port (
+      rst_n_i    : in  std_logic := '1';
+      rd_clk_i   : in  std_logic;
+      rd_req_i   : in  std_logic;
+      rd_data_o  : out std_logic_vector(g_width-1 downto 0);
+      rd_empty_o : out std_logic;
+      rd_full_o  : out std_logic;
+      rd_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0);
+      wr_clk_i   : in  std_logic;
+      wr_req_i   : in  std_logic;
+      wr_data_i  : in  std_logic_vector(g_width-1 downto 0);
+      wr_empty_o : out std_logic;
+      wr_full_o  : out std_logic;
+      wr_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0));
+  end component;
+
+
+  component wbgen2_fifo_sync
+    generic (
+      g_width      : integer;
+      g_size       : integer;
+      g_usedw_size : integer);
+    port (
+      clk_i      : in  std_logic;
+      rst_n_i    : in  std_logic := '1';
+      wr_data_i  : in  std_logic_vector(g_width-1 downto 0);
+      wr_req_i   : in  std_logic;
+      rd_data_o  : out std_logic_vector(g_width-1 downto 0);
+      rd_req_i   : in  std_logic;
+      wr_empty_o : out std_logic;
+      wr_full_o  : out std_logic;
+      wr_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0);
+      rd_empty_o : out std_logic;
+      rd_full_o  : out std_logic;
+      rd_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0));
+  end component;
+  
+end wbgen2_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
new file mode 100644
index 000000000..b7dfdfafc
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
@@ -0,0 +1,2130 @@
+-------------------------------------------------------------------------------
+-- Title      : Wishbone package
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wishbone_pkg.vhd
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.genram_pkg.all;
+
+package wishbone_pkg is
+
+  constant c_wishbone_address_width : integer := 32;
+  constant c_wishbone_data_width    : integer := 32;
+
+  subtype t_wishbone_address is
+    std_logic_vector(c_wishbone_address_width-1 downto 0);
+  subtype t_wishbone_data is
+    std_logic_vector(c_wishbone_data_width-1 downto 0);
+  subtype t_wishbone_byte_select is
+    std_logic_vector((c_wishbone_address_width/8)-1 downto 0);
+  subtype t_wishbone_cycle_type is
+    std_logic_vector(2 downto 0);
+  subtype t_wishbone_burst_type is
+    std_logic_vector(1 downto 0);
+
+  type t_wishbone_interface_mode is (CLASSIC, PIPELINED);
+  type t_wishbone_address_granularity is (BYTE, WORD);
+
+  type t_wishbone_master_out is record
+    cyc : std_logic;
+    stb : std_logic;
+    adr : t_wishbone_address;
+    sel : t_wishbone_byte_select;
+    we  : std_logic;
+    dat : t_wishbone_data;
+  end record t_wishbone_master_out;
+
+  subtype t_wishbone_slave_in is t_wishbone_master_out;
+
+  type t_wishbone_slave_out is record
+    ack   : std_logic;
+    err   : std_logic;
+    rty   : std_logic;
+    stall : std_logic;
+    int   : std_logic;
+    dat   : t_wishbone_data;
+  end record t_wishbone_slave_out;
+  subtype t_wishbone_master_in is t_wishbone_slave_out;
+
+  subtype t_wishbone_device_descriptor is std_logic_vector(255 downto 0);
+
+  type t_wishbone_byte_select_array is array(natural range <>) of t_wishbone_byte_select; 
+  type t_wishbone_data_array is array(natural range <>) of t_wishbone_data; 
+  type t_wishbone_address_array is array(natural range <>) of t_wishbone_address;
+  type t_wishbone_master_out_array is array (natural range <>) of t_wishbone_master_out;
+  --type t_wishbone_slave_in_array is array (natural range <>) of t_wishbone_slave_in;
+  subtype t_wishbone_slave_in_array is t_wishbone_master_out_array;
+  type t_wishbone_slave_out_array is array (natural range <>) of t_wishbone_slave_out;
+  --type t_wishbone_master_in_array is array (natural range <>) of t_wishbone_master_in;
+  subtype t_wishbone_master_in_array is t_wishbone_slave_out_array;
+
+  constant cc_dummy_address : std_logic_vector(c_wishbone_address_width-1 downto 0) :=
+    (others => 'X');
+  constant cc_dummy_data : std_logic_vector(c_wishbone_data_width-1 downto 0) :=
+    (others => 'X');
+  constant cc_dummy_sel : std_logic_vector(c_wishbone_data_width/8-1 downto 0) :=
+    (others => 'X');
+  constant cc_dummy_slave_in : t_wishbone_slave_in :=
+    ('0', '0', cc_dummy_address, cc_dummy_sel, 'X', cc_dummy_data);
+  constant cc_dummy_master_out : t_wishbone_master_out := cc_dummy_slave_in;
+
+  -- Dangerous! Will stall a bus.
+  constant cc_dummy_slave_out : t_wishbone_slave_out :=
+    ('X', 'X', 'X', 'X', 'X', cc_dummy_data);
+  constant cc_dummy_master_in : t_wishbone_master_in := cc_dummy_slave_out;
+
+  constant cc_dummy_address_array : t_wishbone_address_array(0 downto 0) := (0 => cc_dummy_address);
+
+  -- A generally useful function.
+  function f_ceil_log2(x   : natural) return natural;
+  function f_bits2string(s : std_logic_vector) return string;
+
+  function f_string2bits(s : string) return std_logic_vector;
+  function f_string2svl (s : string) return std_logic_vector;
+  function f_slv2string (slv : std_logic_vector) return string;
+
+  function f_string_fix_len( s : string; ret_len : natural := 10; fill_char : character := '0'; justify_right : boolean := true ) return string;
+  function f_hot_to_bin(x : std_logic_vector) return natural;
+  
+  -- *** Wishbone slave interface functions ***
+  -- f_wb_wr:
+  -- processes an incoming write reqest to a register while honoring the select lines
+  -- valid modes are overwrite "owr", set "set" (bits are or'ed) and clear "clr" (bits are nand'ed)
+  function f_wb_wr(pval : std_logic_vector; ival : std_logic_vector; sel : std_logic_vector; mode : string := "owr") return std_logic_vector;
+------------------------------------------------------------------------------
+-- SDB declaration
+------------------------------------------------------------------------------
+
+  constant c_sdb_device_length : natural := 512;  -- bits
+  subtype  t_sdb_record is std_logic_vector(c_sdb_device_length-1 downto 0);
+  type     t_sdb_record_array is array(natural range <>) of t_sdb_record;
+  
+  type t_sdb_product is record
+    vendor_id : std_logic_vector(63 downto 0);
+    device_id : std_logic_vector(31 downto 0);
+    version   : std_logic_vector(31 downto 0);
+    date      : std_logic_vector(31 downto 0);
+    name      : string(1 to 19);
+  end record t_sdb_product;
+
+  type t_sdb_component is record
+    addr_first : std_logic_vector(63 downto 0);
+    addr_last  : std_logic_vector(63 downto 0);
+    product    : t_sdb_product;
+  end record t_sdb_component;
+
+  constant c_sdb_endian_big    : std_logic := '0';
+  constant c_sdb_endian_little : std_logic := '1';
+  type     t_sdb_device is record
+    abi_class     : std_logic_vector(15 downto 0);
+    abi_ver_major : std_logic_vector(7 downto 0);
+    abi_ver_minor : std_logic_vector(7 downto 0);
+    wbd_endian    : std_logic;          -- 0 = big, 1 = little
+    wbd_width     : std_logic_vector(3 downto 0);  -- 3=64-bit, 2=32-bit, 1=16-bit, 0=8-bit
+    sdb_component : t_sdb_component;
+  end record t_sdb_device;
+
+  type t_sdb_msi is record
+    wbd_endian    : std_logic;          -- 0 = big, 1 = little
+    wbd_width     : std_logic_vector(3 downto 0);  -- 3=64-bit, 2=32-bit, 1=16-bit, 0=8-bit
+    sdb_component : t_sdb_component;
+  end record t_sdb_msi;
+
+  type t_sdb_bridge is record
+    sdb_child     : std_logic_vector(63 downto 0);
+    sdb_component : t_sdb_component;
+  end record t_sdb_bridge;
+
+  type t_sdb_integration is record
+    product : t_sdb_product;
+  end record t_sdb_integration;
+
+  type t_sdb_repo_url is record
+    repo_url : string(1 to 63);
+  end record t_sdb_repo_url;
+
+  type t_sdb_synthesis is record
+    syn_module_name  : string(1 to 16);
+    syn_commit_id    : string(1 to 32);
+    syn_tool_name    : string(1 to 8);
+    syn_tool_version : std_logic_vector(31 downto 0);
+    syn_date         : std_logic_vector(31 downto 0);
+    syn_username     : string(1 to 15);
+  end record t_sdb_synthesis;
+  
+  -- If you have a Wishbone master that does not receive MSI,
+  -- list it in the layout as 'f_sdb_auto_msi(c_null_msi, false)'
+  constant c_null_msi : t_sdb_msi := (
+   wbd_endian    => c_sdb_endian_big,
+   wbd_width     => x"0",
+   sdb_component => (
+   addr_first    => x"0000000000000000",
+   addr_last     => x"0000000000000000",
+   product => (
+   vendor_id     => x"0000000000000000",
+   device_id     => x"00000000",
+   version       => x"00000000",
+   date          => x"00000000",
+   name          => "                   ")));  
+
+  -- general crossbar building functions
+  function f_sdb_create_array(g_enum_dev_id  : boolean := false;
+                              g_dev_id_offs    : natural := 0;
+                              g_enum_dev_name  : boolean := false;
+                              g_dev_name_offs  : natural := 0;       
+                              device           : t_sdb_device; 
+                              instances        : natural := 1) return t_sdb_record_array;  
+  function f_sdb_join_arrays(a : t_sdb_record_array; b : t_sdb_record_array) return t_sdb_record_array;
+  function f_sdb_extract_base_addr(sdb_record : t_sdb_record) return std_logic_vector;
+  function f_sdb_extract_end_addr(sdb_record : t_sdb_record)  return std_logic_vector;
+  function f_sdb_automap_array(sdb_array : t_sdb_record_array; start_offset : t_wishbone_address := (others => '0')) return t_sdb_record_array;  
+  function f_align_addr_offset(offs : unsigned; this_rng : unsigned; prev_rng : unsigned) return unsigned; 
+  function f_sdb_create_rom_addr(sdb_array : t_sdb_record_array) return t_wishbone_address;
+
+
+  -- Used to configure a device at a certain address
+  function f_sdb_embed_device(device : t_sdb_device; address : t_wishbone_address) return t_sdb_record;
+  function f_sdb_embed_bridge(bridge : t_sdb_bridge; address : t_wishbone_address) return t_sdb_record;
+  function f_sdb_embed_msi(msi : t_sdb_msi; address : t_wishbone_address) return t_sdb_record;
+  function f_sdb_embed_integration(integr : t_sdb_integration) return t_sdb_record;
+  function f_sdb_embed_repo_url(url : t_sdb_repo_url) return t_sdb_record;
+  function f_sdb_embed_synthesis(syn : t_sdb_synthesis) return t_sdb_record;
+
+  function f_sdb_extract_device(sdb_record : t_sdb_record) return t_sdb_device;
+  function f_sdb_extract_bridge(sdb_record : t_sdb_record) return t_sdb_bridge;
+  function f_sdb_extract_msi(sdb_record : t_sdb_record) return t_sdb_msi;
+  function f_sdb_extract_integration(sdb_record : t_sdb_record) return t_sdb_integration;
+  function f_sdb_extract_repo_url(sdb_record : t_sdb_record) return t_sdb_repo_url;
+  function f_sdb_extract_synthesis(sdb_record : t_sdb_record) return t_sdb_synthesis;
+
+  -- Automatic crossbar mapping functions
+  function f_sdb_auto_device(device : t_sdb_device; enable : boolean := true; name: string := "") return t_sdb_record;
+  function f_sdb_auto_bridge(bridge : t_sdb_bridge; enable : boolean := true; name: string := "") return t_sdb_record;
+  function f_sdb_auto_msi   (msi    : t_sdb_msi;    enable : boolean := true) return t_sdb_record;
+  function f_sdb_auto_layout(records: t_sdb_record_array)                               return t_sdb_record_array;
+  function f_sdb_auto_layout(slaves : t_sdb_record_array; masters : t_sdb_record_array) return t_sdb_record_array;
+  function f_sdb_auto_sdb   (records: t_sdb_record_array)                               return t_wishbone_address;
+  function f_sdb_auto_sdb   (slaves : t_sdb_record_array; masters : t_sdb_record_array) return t_wishbone_address;
+  
+  -- For internal use by the crossbar
+  function f_sdb_bus_end(g_wraparound : boolean; g_layout : t_sdb_record_array; g_sdb_addr : t_wishbone_address; msi : boolean) return unsigned;
+  function f_sdb_embed_product(product         : t_sdb_product) return std_logic_vector;  -- (319 downto 8)
+  function f_sdb_embed_component(sdb_component : t_sdb_component; address : t_wishbone_address) return std_logic_vector;  -- (447 downto 8)
+  function f_sdb_extract_product(sdb_record    : std_logic_vector(319 downto 8)) return t_sdb_product;
+  function f_sdb_extract_component(sdb_record  : std_logic_vector(447 downto 8)) return t_sdb_component;
+
+------------------------------------------------------------------------------
+-- Components declaration
+-------------------------------------------------------------------------------
+
+  component wb_slave_adapter
+    generic (
+      g_master_use_struct  : boolean;
+      g_master_mode        : t_wishbone_interface_mode;
+      g_master_granularity : t_wishbone_address_granularity;
+      g_slave_use_struct   : boolean;
+      g_slave_mode         : t_wishbone_interface_mode;
+      g_slave_granularity  : t_wishbone_address_granularity);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      sl_adr_i   : in  std_logic_vector(c_wishbone_address_width-1 downto 0) := cc_dummy_address;
+      sl_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0)    := cc_dummy_data;
+      sl_sel_i   : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0)  := cc_dummy_sel;
+      sl_cyc_i   : in  std_logic                                             := '0';
+      sl_stb_i   : in  std_logic                                             := '0';
+      sl_we_i    : in  std_logic                                             := '0';
+      sl_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      sl_err_o   : out std_logic;
+      sl_rty_o   : out std_logic;
+      sl_ack_o   : out std_logic;
+      sl_stall_o : out std_logic;
+      sl_int_o   : out std_logic;
+      slave_i    : in  t_wishbone_slave_in                                   := cc_dummy_slave_in;
+      slave_o    : out t_wishbone_slave_out;
+      ma_adr_o   : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+      ma_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      ma_sel_o   : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+      ma_cyc_o   : out std_logic;
+      ma_stb_o   : out std_logic;
+      ma_we_o    : out std_logic;
+      ma_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0)    := cc_dummy_data;
+      ma_err_i   : in  std_logic                                             := '0';
+      ma_rty_i   : in  std_logic                                             := '0';
+      ma_ack_i   : in  std_logic                                             := '0';
+      ma_stall_i : in  std_logic                                             := '0';
+      ma_int_i   : in  std_logic                                             := '0';
+      master_i   : in  t_wishbone_master_in                                  := cc_dummy_slave_out;
+      master_o   : out t_wishbone_master_out);
+  end component;
+
+  component wb_async_bridge
+    generic (
+      g_simulation          : integer;
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_cpu_address_width   : integer);
+    port (
+      rst_n_i     : in    std_logic;
+      clk_sys_i   : in    std_logic;
+      cpu_cs_n_i  : in    std_logic;
+      cpu_wr_n_i  : in    std_logic;
+      cpu_rd_n_i  : in    std_logic;
+      cpu_bs_n_i  : in    std_logic_vector(3 downto 0);
+      cpu_addr_i  : in    std_logic_vector(g_cpu_address_width-1 downto 0);
+      cpu_data_b  : inout std_logic_vector(31 downto 0);
+      cpu_nwait_o : out   std_logic;
+      wb_adr_o    : out   std_logic_vector(c_wishbone_address_width - 1 downto 0);
+      wb_dat_o    : out   std_logic_vector(31 downto 0);
+      wb_stb_o    : out   std_logic;
+      wb_we_o     : out   std_logic;
+      wb_sel_o    : out   std_logic_vector(3 downto 0);
+      wb_cyc_o    : out   std_logic;
+      wb_dat_i    : in    std_logic_vector (c_wishbone_data_width-1 downto 0);
+      wb_ack_i    : in    std_logic;
+      wb_stall_i  : in    std_logic := '0');
+  end component;
+
+  component xwb_async_bridge
+    generic (
+      g_simulation          : integer;
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_cpu_address_width   : integer);
+    port (
+      rst_n_i     : in    std_logic;
+      clk_sys_i   : in    std_logic;
+      cpu_cs_n_i  : in    std_logic;
+      cpu_wr_n_i  : in    std_logic;
+      cpu_rd_n_i  : in    std_logic;
+      cpu_bs_n_i  : in    std_logic_vector(3 downto 0);
+      cpu_addr_i  : in    std_logic_vector(g_cpu_address_width-1 downto 0);
+      cpu_data_b  : inout std_logic_vector(31 downto 0);
+      cpu_nwait_o : out   std_logic;
+      master_o    : out   t_wishbone_master_out;
+      master_i    : in    t_wishbone_master_in);
+  end component;
+
+  component xwb_bus_fanout
+    generic (
+      g_num_outputs          : natural;
+      g_bits_per_slave       : integer;
+      g_address_granularity  : t_wishbone_address_granularity := WORD;
+      g_slave_interface_mode : t_wishbone_interface_mode      := CLASSIC);
+    port (
+      clk_sys_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+      slave_i   : in  t_wishbone_slave_in;
+      slave_o   : out t_wishbone_slave_out;
+      master_i  : in  t_wishbone_master_in_array(0 to g_num_outputs-1);
+      master_o  : out t_wishbone_master_out_array(0 to g_num_outputs-1));
+  end component;
+
+  component xwb_crossbar
+    generic (
+      g_num_masters : integer;
+      g_num_slaves  : integer;
+      g_registered  : boolean;
+      g_address     : t_wishbone_address_array;
+      g_mask        : t_wishbone_address_array);
+    port (
+      clk_sys_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+      slave_i   : in  t_wishbone_slave_in_array(g_num_masters-1 downto 0);
+      slave_o   : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
+      master_i  : in  t_wishbone_master_in_array(g_num_slaves-1 downto 0);
+      master_o  : out t_wishbone_master_out_array(g_num_slaves-1 downto 0);
+      sdb_sel_o : out std_logic_vector(g_num_masters-1 downto 0)); -- leave open!
+  end component;
+
+  -- Use the f_xwb_bridge_*_sdb to bridge a crossbar to another
+  function f_xwb_bridge_manual_sdb(     -- take a manual bus size
+    g_size     : t_wishbone_address;
+    g_sdb_addr : t_wishbone_address) return t_sdb_bridge;
+
+  function f_xwb_bridge_layout_sdb(     -- determine bus size from layout
+    g_wraparound : boolean := true;
+    g_layout     : t_sdb_record_array;
+    g_sdb_addr   : t_wishbone_address) return t_sdb_bridge;
+
+  function f_xwb_msi_manual_sdb(        -- take a manual bus size
+    g_size     : t_wishbone_address) return t_sdb_msi;
+
+  function f_xwb_msi_layout_sdb(     -- determine MSI size from layout
+    g_layout     : t_sdb_record_array) return t_sdb_msi;
+
+  component xwb_sdb_crossbar
+    generic (
+      g_num_masters : integer;
+      g_num_slaves  : integer;
+      g_registered  : boolean := false;
+      g_wraparound  : boolean := true;
+      g_layout      : t_sdb_record_array;
+      g_sdb_addr    : t_wishbone_address;
+      g_sdb_name    : string := "WB4-Crossbar-GSI   ");
+    port (
+      clk_sys_i     : in  std_logic;
+      rst_n_i       : in  std_logic;
+      slave_i       : in  t_wishbone_slave_in_array  (g_num_masters-1 downto 0);
+      slave_o       : out t_wishbone_slave_out_array (g_num_masters-1 downto 0);
+      msi_master_i  : in  t_wishbone_master_in_array (g_num_masters-1 downto 0) := (others => cc_dummy_master_in);
+      msi_master_o  : out t_wishbone_master_out_array(g_num_masters-1 downto 0);
+      master_i      : in  t_wishbone_master_in_array (g_num_slaves -1 downto 0);
+      master_o      : out t_wishbone_master_out_array(g_num_slaves -1 downto 0);
+      msi_slave_i   : in  t_wishbone_slave_in_array  (g_num_slaves -1 downto 0) := (others => cc_dummy_slave_in);
+      msi_slave_o   : out t_wishbone_slave_out_array (g_num_slaves -1 downto 0));
+  end component;
+  
+  component xwb_register_link -- puts a register of delay between crossbars
+    port(
+      clk_sys_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+      slave_i   : in  t_wishbone_slave_in;
+      slave_o   : out t_wishbone_slave_out;
+      master_i  : in  t_wishbone_master_in;
+      master_o  : out t_wishbone_master_out);
+  end component;
+
+  -- skidpad. acts like a fifo in wb flow control, but costs less
+  component wb_skidpad is
+  generic(
+     g_adrbits   : natural   := 32
+  );
+  Port(
+     clk_i        : std_logic;
+     rst_n_i      : std_logic;
+
+     push_i       : in  std_logic;
+     pop_i        : in  std_logic;
+     full_o       : out std_logic;
+     empty_o      : out std_logic;
+
+     adr_i        : in  std_logic_vector(g_adrbits-1 downto 0);
+     dat_i        : in  std_logic_vector(32-1 downto 0);
+     sel_i        : in  std_logic_vector(4-1 downto 0);
+     we_i         : in  std_logic;
+
+     adr_o        : out std_logic_vector(g_adrbits-1 downto 0);
+     dat_o        : out std_logic_vector(32-1 downto 0);
+     sel_o        : out std_logic_vector(4-1 downto 0);
+     we_o         : out std_logic
+  );
+  end component;
+
+  component sdb_rom is
+    generic(
+      g_layout  : t_sdb_record_array;
+      g_masters : natural;
+      g_bus_end : unsigned(63 downto 0);
+      g_sdb_name    : string := "WB4-Crossbar-GSI   ");
+    port(
+      clk_sys_i : in  std_logic;
+      master_i  : in  std_logic_vector(g_masters-1 downto 0);
+      slave_i   : in  t_wishbone_slave_in;
+      slave_o   : out t_wishbone_slave_out);
+  end component;
+  
+  constant c_xwb_dma_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"00",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"000000000000001f",
+      product     => (
+        vendor_id => x"0000000000000651",  -- GSI
+        device_id => x"cababa56",
+        version   => x"00000001",
+        date      => x"20120518",
+        name      => "WB4-Streaming-DMA_0")));
+  component xwb_dma is
+    generic(
+      -- Value 0 cannot stream
+      -- Value 1 only slaves with async ACK can stream
+      -- Value 2 only slaves with combined latency <= 2 can stream
+      -- Value 3 only slaves with combined latency <= 6 can stream
+      -- Value 4 only slaves with combined latency <= 14 can stream
+      -- ....
+      logRingLen : integer := 4
+      );
+    port(
+      -- Common wishbone signals
+      clk_i       : in  std_logic;
+      rst_n_i     : in  std_logic;
+      slave_i     : in  t_wishbone_slave_in;
+      slave_o     : out t_wishbone_slave_out;
+      -- Master reader port
+      r_master_i  : in  t_wishbone_master_in;
+      r_master_o  : out t_wishbone_master_out;
+      -- Master writer port
+      w_master_i  : in  t_wishbone_master_in;
+      w_master_o  : out t_wishbone_master_out;
+      -- Pulsed high completion signal
+      interrupt_o : out std_logic
+      );
+  end component;
+
+  -- If you reset one clock domain, you must reset BOTH!
+  -- Release of the reset lines may be arbitrarily out-of-phase
+  component xwb_clock_crossing is
+    generic(
+      g_size : natural := 16);
+    port(
+      -- Slave control port
+      slave_clk_i    : in  std_logic;
+      slave_rst_n_i  : in  std_logic;
+      slave_i        : in  t_wishbone_slave_in;
+      slave_o        : out t_wishbone_slave_out;
+      -- Master reader port
+      master_clk_i   : in  std_logic;
+      master_rst_n_i : in  std_logic;
+      master_i       : in  t_wishbone_master_in;
+      master_o       : out t_wishbone_master_out;
+      -- Flow control back-channel for acks
+      slave_ready_o : out std_logic;
+      slave_stall_i : in  std_logic := '0');
+  end component;
+
+  -- g_size is in words
+  function f_xwb_dpram(g_size : natural) return t_sdb_device;
+  component xwb_dpram
+    generic (
+      g_size                  : natural;
+      g_init_file             : string                         := "";
+      g_must_have_init_file   : boolean                        := true;
+      g_slave1_interface_mode : t_wishbone_interface_mode      := CLASSIC;
+      g_slave2_interface_mode : t_wishbone_interface_mode      := CLASSIC;
+      g_slave1_granularity    : t_wishbone_address_granularity := WORD;
+      g_slave2_granularity    : t_wishbone_address_granularity := WORD);
+    port (
+      clk_sys_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+      slave1_i  : in  t_wishbone_slave_in;
+      slave1_o  : out t_wishbone_slave_out;
+      slave2_i  : in  t_wishbone_slave_in;
+      slave2_o  : out t_wishbone_slave_out);
+  end component;
+
+  component xwb_dpram_mixed
+  generic(
+    g_size                  : natural := 16384;
+    g_init_file             : string  := "";
+    g_must_have_init_file   : boolean := true;
+    g_swap_word_endianness  : boolean := true;
+    g_slave1_interface_mode : t_wishbone_interface_mode;
+    g_slave2_interface_mode : t_wishbone_interface_mode;
+    g_dpram_port_a_width    : integer := 16;
+    g_dpram_port_b_width    : integer := 32;
+    g_slave1_granularity    : t_wishbone_address_granularity;
+    g_slave2_granularity    : t_wishbone_address_granularity);
+  port(
+    clk_slave1_i  : in std_logic;
+    clk_slave2_i  : in std_logic;
+    rst_n_i       : in std_logic;
+
+    slave1_i      : in  t_wishbone_slave_in;
+    slave1_o      : out t_wishbone_slave_out;
+    slave2_i      : in  t_wishbone_slave_in;
+    slave2_o      : out t_wishbone_slave_out);
+  end component;
+  
+  -- Just like the DMA controller, but constantly at address 0
+  component xwb_streamer is
+    generic(
+      -- Value 0 cannot stream
+      -- Value 1 only slaves with async ACK can stream
+      -- Value 2 only slaves with combined latency = 2 can stream
+      -- Value 3 only slaves with combined latency = 6 can stream
+      -- Value 4 only slaves with combined latency = 14 can stream
+      -- ....
+      logRingLen : integer := 4
+    );
+    port(
+      -- Common wishbone signals
+      clk_i       : in  std_logic;
+      rst_n_i     : in  std_logic;
+      -- Master reader port
+      r_master_i  : in  t_wishbone_master_in;
+      r_master_o  : out t_wishbone_master_out;
+      -- Master writer port
+      w_master_i  : in  t_wishbone_master_in;
+      w_master_o  : out t_wishbone_master_out);
+  end component;
+
+
+  constant c_xwb_gpio_port_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"441c5143",
+        version   => x"00000001",
+        date      => x"20121129",
+        name      => "WB-GPIO-Port       ")));
+
+
+  component wb_gpio_port
+    generic (
+      g_interface_mode         : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity    : t_wishbone_address_granularity := WORD;
+      g_num_pins               : natural range 1 to 256;
+      g_with_builtin_tristates : boolean                        := false);
+    port (
+      clk_sys_i  : in    std_logic;
+      rst_n_i    : in    std_logic;
+      wb_sel_i   : in    std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+      wb_cyc_i   : in    std_logic;
+      wb_stb_i   : in    std_logic;
+      wb_we_i    : in    std_logic;
+      wb_adr_i   : in    std_logic_vector(7 downto 0);
+      wb_dat_i   : in    std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_dat_o   : out   std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_ack_o   : out   std_logic;
+      wb_stall_o : out   std_logic;
+      gpio_b     : inout std_logic_vector(g_num_pins-1 downto 0);
+      gpio_out_o : out   std_logic_vector(g_num_pins-1 downto 0);
+      gpio_in_i  : in    std_logic_vector(g_num_pins-1 downto 0);
+      gpio_oen_o : out   std_logic_vector(g_num_pins-1 downto 0));
+  end component;
+
+  component xwb_gpio_port
+    generic (
+      g_interface_mode         : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity    : t_wishbone_address_granularity := WORD;
+      g_num_pins               : natural range 1 to 256;
+      g_with_builtin_tristates : boolean);
+    port (
+      clk_sys_i  : in    std_logic;
+      rst_n_i    : in    std_logic;
+      slave_i    : in    t_wishbone_slave_in;
+      slave_o    : out   t_wishbone_slave_out;
+      desc_o     : out   t_wishbone_device_descriptor;
+      gpio_b     : inout std_logic_vector(g_num_pins-1 downto 0);
+      gpio_out_o : out   std_logic_vector(g_num_pins-1 downto 0);
+      gpio_in_i  : in    std_logic_vector(g_num_pins-1 downto 0);
+      gpio_oen_o : out   std_logic_vector(g_num_pins-1 downto 0));
+  end component;
+
+  constant c_xwb_i2c_master_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"123c5443",
+        version   => x"00000001",
+        date      => x"20121129",
+        name      => "WB-I2C-Master      ")));
+
+
+  component wb_i2c_master
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_num_interfaces      : integer := 1);
+    port (
+      clk_sys_i    : in  std_logic;
+      rst_n_i      : in  std_logic;
+      wb_adr_i     : in  std_logic_vector(4 downto 0);
+      wb_dat_i     : in  std_logic_vector(31 downto 0);
+      wb_dat_o     : out std_logic_vector(31 downto 0);
+      wb_sel_i     : in  std_logic_vector(3 downto 0);
+      wb_stb_i     : in  std_logic;
+      wb_cyc_i     : in  std_logic;
+      wb_we_i      : in  std_logic;
+      wb_ack_o     : out std_logic;
+      wb_int_o     : out std_logic;
+      wb_stall_o   : out std_logic;
+      scl_pad_i    : in  std_logic_vector(g_num_interfaces-1 downto 0);
+      scl_pad_o    : out std_logic_vector(g_num_interfaces-1 downto 0);
+      scl_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0);
+      sda_pad_i    : in  std_logic_vector(g_num_interfaces-1 downto 0);
+      sda_pad_o    : out std_logic_vector(g_num_interfaces-1 downto 0);
+      sda_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0));
+  end component;
+
+  component xwb_i2c_master
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_num_interfaces      : integer := 1);
+    port (
+      clk_sys_i    : in  std_logic;
+      rst_n_i      : in  std_logic;
+      slave_i      : in  t_wishbone_slave_in;
+      slave_o      : out t_wishbone_slave_out;
+      desc_o       : out t_wishbone_device_descriptor;
+      scl_pad_i    : in  std_logic_vector(g_num_interfaces-1 downto 0);
+      scl_pad_o    : out std_logic_vector(g_num_interfaces-1 downto 0);
+      scl_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0);
+      sda_pad_i    : in  std_logic_vector(g_num_interfaces-1 downto 0);
+      sda_pad_o    : out std_logic_vector(g_num_interfaces-1 downto 0);
+      sda_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0));
+  end component;
+
+  component xwb_lm32
+    generic (
+      g_profile : string;
+      g_reset_vector : std_logic_vector(31 downto 0) := x"00000000";
+      g_sdb_address  : std_logic_vector(31 downto 0) := x"00000000");
+    port (
+      clk_sys_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+      irq_i     : in  std_logic_vector(31 downto 0);
+      dwb_o     : out t_wishbone_master_out;
+      dwb_i     : in  t_wishbone_master_in;
+      iwb_o     : out t_wishbone_master_out;
+      iwb_i     : in  t_wishbone_master_in);
+  end component;
+
+  constant c_xwb_onewire_master_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"779c5443",
+        version   => x"00000001",
+        date      => x"20121129",
+        name      => "WB-OneWire-Master  ")));
+
+  component wb_onewire_master
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_num_ports           : integer;
+      g_ow_btp_normal       : string                         := "1.0";
+      g_ow_btp_overdrive    : string                         := "5.0");
+    port (
+      clk_sys_i   : in  std_logic;
+      rst_n_i     : in  std_logic;
+      wb_cyc_i    : in  std_logic;
+      wb_sel_i    : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+      wb_stb_i    : in  std_logic;
+      wb_we_i     : in  std_logic;
+      wb_adr_i    : in  std_logic_vector(2 downto 0);
+      wb_dat_i    : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_dat_o    : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_ack_o    : out std_logic;
+      wb_int_o    : out std_logic;
+      wb_stall_o  : out std_logic;
+      owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
+      owr_en_o    : out std_logic_vector(g_num_ports -1 downto 0);
+      owr_i       : in  std_logic_vector(g_num_ports -1 downto 0));
+  end component;
+
+  component xwb_onewire_master
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_num_ports           : integer;
+      g_ow_btp_normal       : string                         := "5.0";
+      g_ow_btp_overdrive    : string                         := "1.0");
+    port (
+      clk_sys_i   : in  std_logic;
+      rst_n_i     : in  std_logic;
+      slave_i     : in  t_wishbone_slave_in;
+      slave_o     : out t_wishbone_slave_out;
+      desc_o      : out t_wishbone_device_descriptor;
+      owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
+      owr_en_o    : out std_logic_vector(g_num_ports -1 downto 0);
+      owr_i       : in  std_logic_vector(g_num_ports -1 downto 0));
+  end component;
+
+  constant c_xwb_spi_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"000000000000001F",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"e503947e",       -- echo "WB-SPI.Control     " | md5sum | cut -c1-8
+        version   => x"00000001",
+        date      => x"20121116",
+        name      => "WB-SPI.Control     ")));
+
+  component wb_spi
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_divider_len         : integer := 16;
+      g_max_char_len        : integer := 128;
+      g_num_slaves          : integer := 8);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(4 downto 0);
+      wb_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_dat_o   : out std_logic_vector(31 downto 0);
+      wb_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_cyc_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_err_o   : out std_logic;
+      wb_int_o   : out std_logic;
+      wb_stall_o : out std_logic;
+      pad_cs_o   : out std_logic_vector(g_num_slaves-1 downto 0);
+      pad_sclk_o : out std_logic;
+      pad_mosi_o : out std_logic;
+      pad_miso_i : in  std_logic);
+  end component;
+
+  component xwb_spi
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_divider_len         : integer := 16;
+      g_max_char_len        : integer := 128;
+      g_num_slaves          : integer := 8);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      slave_i    : in  t_wishbone_slave_in;
+      slave_o    : out t_wishbone_slave_out;
+      desc_o     : out t_wishbone_device_descriptor;
+      pad_cs_o   : out std_logic_vector(g_num_slaves-1 downto 0);
+      pad_sclk_o : out std_logic;
+      pad_mosi_o : out std_logic;
+      pad_miso_i : in  std_logic);
+  end component;
+
+  component wb_simple_uart
+    generic (
+      g_with_virtual_uart   : boolean                        := false;
+      g_with_physical_uart  : boolean                        := true;
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_vuart_fifo_size     : integer := 1024);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(4 downto 0);
+      wb_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_dat_o   : out std_logic_vector(31 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_stall_o : out std_logic;
+      uart_rxd_i : in  std_logic := '1';
+      uart_txd_o : out std_logic);
+  end component;
+
+  component xwb_simple_uart
+    generic (
+      g_with_virtual_uart   : boolean                        := false;
+      g_with_physical_uart  : boolean                        := true;
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_vuart_fifo_size     : integer := 1024);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      slave_i    : in  t_wishbone_slave_in;
+      slave_o    : out t_wishbone_slave_out;
+      desc_o     : out t_wishbone_device_descriptor;
+      uart_rxd_i : in  std_logic := '1';
+      uart_txd_o : out std_logic);
+  end component;
+
+  component wb_simple_pwm
+    generic (
+      g_num_channels        : integer range 1 to 8;
+      g_regs_size           : integer range 1 to 16 := 16;
+      g_default_period      : integer range 0 to 255 := 0;
+      g_default_presc       : integer range 0 to 255 := 0;
+      g_default_val         : integer range 0 to 255 := 0;
+      g_interface_mode      : t_wishbone_interface_mode      := PIPELINED;
+      g_address_granularity : t_wishbone_address_granularity := BYTE);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(5 downto 0);
+      wb_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_dat_o   : out std_logic_vector(31 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_stall_o : out std_logic;
+      pwm_o      : out std_logic_vector(g_num_channels-1 downto 0));
+  end component;
+
+  component xwb_simple_pwm
+    generic (
+      g_num_channels        : integer range 1 to 8;
+      g_regs_size           : integer range 1 to 16 := 16;
+      g_default_period      : integer range 0 to 255 := 0;
+      g_default_presc       : integer range 0 to 255 := 0;
+      g_default_val         : integer range 0 to 255 := 0;
+      g_interface_mode      : t_wishbone_interface_mode      := PIPELINED;
+      g_address_granularity : t_wishbone_address_granularity := BYTE);
+    port (
+      clk_sys_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+      slave_i   : in  t_wishbone_slave_in;
+      slave_o   : out t_wishbone_slave_out;
+      pwm_o     : out std_logic_vector(g_num_channels-1 downto 0));
+  end component;
+
+  component wb_tics
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_period              : integer);
+    port (
+      rst_n_i    : in  std_logic;
+      clk_sys_i  : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(3 downto 0);
+      wb_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_stall_o : out std_logic);
+  end component;
+
+  component xwb_tics
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_period              : integer);
+    port (
+      clk_sys_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+      slave_i   : in  t_wishbone_slave_in;
+      slave_o   : out t_wishbone_slave_out;
+      desc_o    : out t_wishbone_device_descriptor);
+  end component;
+
+  component wb_vic
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode;
+      g_address_granularity : t_wishbone_address_granularity;
+      g_num_interrupts      : natural;
+      g_init_vectors        : t_wishbone_address_array := cc_dummy_address_array;
+      g_retry_timeout : integer := 0
+      );
+    port (
+      clk_sys_i    : in  std_logic;
+      rst_n_i      : in  std_logic;
+      wb_adr_i     : in  std_logic_vector(c_wishbone_address_width-1 downto 0);
+      wb_dat_i     : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_dat_o     : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_cyc_i     : in  std_logic;
+      wb_sel_i     : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+      wb_stb_i     : in  std_logic;
+      wb_we_i      : in  std_logic;
+      wb_ack_o     : out std_logic;
+      wb_stall_o   : out std_logic;
+      irqs_i       : in  std_logic_vector(g_num_interrupts-1 downto 0);
+      irq_master_o : out std_logic);
+  end component;
+
+  constant c_xwb_vic_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"00000013",
+        version   => x"00000002",
+        date      => x"20120113",
+        name      => "WB-VIC-Int.Control ")));   
+
+  component xwb_vic
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode;
+      g_address_granularity : t_wishbone_address_granularity;
+      g_num_interrupts      : natural;
+      g_init_vectors        : t_wishbone_address_array := cc_dummy_address_array;
+    g_retry_timeout : integer := 0);
+
+    port (
+      clk_sys_i    : in  std_logic;
+      rst_n_i      : in  std_logic;
+      slave_i      : in  t_wishbone_slave_in;
+      slave_o      : out t_wishbone_slave_out;
+      irqs_i       : in  std_logic_vector(g_num_interrupts-1 downto 0);
+      irq_master_o : out std_logic);
+  end component;
+
+  constant c_wb_serial_lcd_sdb : t_sdb_device := (
+    abi_class     => x"0000", -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"00",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7", -- 8/16/32-bit port granularity
+    sdb_component => (
+    addr_first    => x"0000000000000000",
+    addr_last     => x"00000000000000ff",
+    product => (
+    vendor_id     => x"0000000000000651", -- GSI
+    device_id     => x"b77a5045",
+    version       => x"00000001",
+    date          => x"20130222",
+    name          => "SERIAL-LCD-DISPLAY ")));
+  component wb_serial_lcd
+    generic(
+      g_cols : natural := 40;
+      g_rows : natural := 24;
+      g_hold : natural := 15; -- How many times to repeat a line  (for sharpness)
+      g_wait : natural := 1); -- How many cycles per state change (for 20MHz timing)
+    port(
+      slave_clk_i  : in  std_logic;
+      slave_rstn_i : in  std_logic;
+      slave_i      : in  t_wishbone_slave_in;
+      slave_o      : out t_wishbone_slave_out;
+      di_clk_i     : in  std_logic;
+      di_scp_o     : out std_logic;
+      di_lp_o      : out std_logic;
+      di_flm_o     : out std_logic;
+      di_dat_o     : out std_logic);
+  end component;
+
+  function f_wb_spi_flash_sdb(g_bits : natural) return t_sdb_device;
+  component wb_spi_flash is
+    generic(
+      g_port_width             : natural   := 1;  -- 1 for EPCS, 4 for EPCQ
+      g_addr_width             : natural   := 24; -- log of memory (24=16MB)
+      g_idle_time              : natural   := 3;
+      g_dummy_time             : natural   := 8;
+      -- leave these at defaults if you have:
+      --   a) slow clock, b) valid constraints, or c) registered in/outputs
+      g_input_latch_edge       : std_logic := '1'; -- rising
+      g_output_latch_edge      : std_logic := '0'; -- falling
+      g_input_to_output_cycles : natural   := 1);  -- between 1 and 8
+    port(
+      clk_i     : in  std_logic;
+      rstn_i    : in  std_logic;
+      slave_i   : in  t_wishbone_slave_in;
+      slave_o   : out t_wishbone_slave_out;
+      
+      -- For properly constrained designs, set clk_out_i = clk_in_i.
+      clk_out_i : in  std_logic;
+      clk_in_i  : in  std_logic;
+      ncs_o     : out std_logic;
+      oe_o      : out std_logic_vector(g_port_width-1 downto 0);
+      asdi_o    : out std_logic_vector(g_port_width-1 downto 0);
+      data_i    : in  std_logic_vector(g_port_width-1 downto 0);
+      
+      external_request_i : in  std_logic := '0'; -- JTAG wants to use SPI?
+      external_granted_o : out std_logic);
+  end component;
+
+  -----------------------------------------------------------------------------
+  -- I2C to Wishbone bridge, following protocol defined with ELMA
+  -----------------------------------------------------------------------------
+  component wb_i2c_bridge is
+    generic
+    (
+      -- FSM watchdog timeout, see Appendix A in the component documentation for
+      -- an example of setting this generic
+      g_fsm_wdt : positive
+    );
+    port
+    (
+      -- Clock, reset
+      clk_i      : in  std_logic;
+      rst_n_i    : in  std_logic;
+
+      -- I2C lines
+      scl_i      : in  std_logic;
+      scl_o      : out std_logic;
+      scl_en_o   : out std_logic;
+      sda_i      : in  std_logic;
+      sda_o      : out std_logic;
+      sda_en_o   : out std_logic;
+
+      -- I2C address
+      i2c_addr_i : in  std_logic_vector(6 downto 0);
+
+      -- Status outputs
+      -- TIP  : Transfer In Progress
+      --        '1' when the I2C slave detects a matching I2C address, thus a
+      --            transfer is in progress
+      --        '0' when idle
+      -- ERR  : Error
+      --       '1' when the SysMon attempts to access an invalid WB slave
+      --       '0' when idle
+      -- WDTO : Watchdog timeout (single clock cycle pulse)
+      --        '1' -- timeout of watchdog occured
+      --        '0' -- when idle
+      tip_o      : out std_logic;
+      err_p_o    : out std_logic;
+      wdto_p_o   : out std_logic;
+
+      -- Wishbone master signals
+      wbm_stb_o  : out std_logic;
+      wbm_cyc_o  : out std_logic;
+      wbm_sel_o  : out std_logic_vector(3 downto 0);
+      wbm_we_o   : out std_logic;
+      wbm_dat_i  : in  std_logic_vector(31 downto 0);
+      wbm_dat_o  : out std_logic_vector(31 downto 0);
+      wbm_adr_o  : out std_logic_vector(31 downto 0);
+      wbm_ack_i  : in  std_logic;
+      wbm_rty_i  : in  std_logic;
+      wbm_err_i  : in  std_logic
+    );
+  end component wb_i2c_bridge;
+
+  ------------------------------------------------------------------------------
+  -- MultiBoot component
+  ------------------------------------------------------------------------------
+  component xwb_xil_multiboot is
+    port
+    (
+      -- Clock and reset input ports
+      clk_i   : in  std_logic;
+      rst_n_i : in  std_logic;
+
+      -- Wishbone ports
+      wbs_i   : in  t_wishbone_slave_in;
+      wbs_o   : out t_wishbone_slave_out;
+
+      -- SPI ports
+      spi_cs_n_o : out std_logic;
+      spi_sclk_o : out std_logic;
+      spi_mosi_o : out std_logic;
+      spi_miso_i : in  std_logic
+    );
+  end component xwb_xil_multiboot;
+
+  constant c_xwb_xil_multiboot_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"00",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"000000000000001f",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"11da333d",          -- echo "WB-Xilinx-MultiBoot" | md5sum | cut -c1-8
+        version   => x"00000001",
+        date      => x"20140313",
+        name      => "WB-Xilinx-MultiBoot")));
+
+  constant cc_dummy_sdb_device : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"ffffffff",
+        version   => x"00000001",
+        date      => x"20150722",
+        name      => "Unused-Device      ")));
+
+  
+end wishbone_pkg;
+
+package body wishbone_pkg is
+   -- f_wb_wr: processes a write reqest to a slave register with select lines. valid modes are "owr", "set" and "clr"
+   function f_wb_wr(pval : std_logic_vector; ival : std_logic_vector; sel : std_logic_vector; mode : string := "owr") return std_logic_vector is
+      variable n_sel     : std_logic_vector(pval'range);
+      variable n_val     : std_logic_vector(pval'range);
+      variable result 	 : std_logic_vector(pval'range);   
+   begin
+     for i in pval'range loop 
+      n_sel(i) := sel((i-pval'low) / 8); -- subtract the low index for when register width > wishbone data width
+      n_val(i) := ival(i-pval'low);
+     end loop;
+
+     if(mode = "set") then  
+      result := pval or (n_val and n_sel);
+     elsif (mode = "clr") then
+      result := pval and not (n_val and n_sel); 
+     else
+      result := (pval and not n_sel) or (n_val and n_sel);    
+     end if;  
+     
+     return result;
+   end f_wb_wr;
+  
+  function f_ceil_log2(x : natural) return natural is
+  begin
+    if x <= 1
+    then return 0;
+    else return f_ceil_log2((x+1)/2) +1;
+    end if;
+  end f_ceil_log2;
+
+  function f_sdb_embed_product(product : t_sdb_product)
+    return std_logic_vector             -- (319 downto 8)
+  is
+    variable result : std_logic_vector(319 downto 8);
+  begin
+    result(319 downto 256) := product.vendor_id;
+    result(255 downto 224) := product.device_id;
+    result(223 downto 192) := product.version;
+    result(191 downto 160) := product.date;
+    for i in 0 to 18 loop               -- string to ascii
+      result(159-i*8 downto 152-i*8) :=
+        std_logic_vector(to_unsigned(character'pos(product.name(i+1)), 8));
+    end loop;
+    return result;
+  end;
+
+  function f_sdb_extract_product(sdb_record : std_logic_vector(319 downto 8))
+    return t_sdb_product
+  is
+    variable result : t_sdb_product;
+  begin
+    result.vendor_id := sdb_record(319 downto 256);
+    result.device_id := sdb_record(255 downto 224);
+    result.version   := sdb_record(223 downto 192);
+    result.date      := sdb_record(191 downto 160);
+    for i in 0 to 18 loop               -- ascii to string
+      result.name(i+1) := character'val(to_integer(unsigned(sdb_record(159-i*8 downto 152-i*8))));
+    end loop;
+    return result;
+  end;
+
+  function f_sdb_embed_component(sdb_component : t_sdb_component; address : t_wishbone_address)
+    return std_logic_vector             -- (447 downto 8)
+  is
+    variable result : std_logic_vector(447 downto 8);
+
+    constant first : unsigned(63 downto 0) := unsigned(sdb_component.addr_first);
+    constant last  : unsigned(63 downto 0) := unsigned(sdb_component.addr_last);
+    variable base  : unsigned(63 downto 0) := (others => '0');
+  begin
+    base(address'length-1 downto 0) := unsigned(address);
+
+    result(447 downto 384) := std_logic_vector(base);
+    result(383 downto 320) := std_logic_vector(base + last - first);
+    result(319 downto 8)   := f_sdb_embed_product(sdb_component.product);
+    return result;
+  end;
+
+  function f_sdb_extract_component(sdb_record : std_logic_vector(447 downto 8))
+    return t_sdb_component
+  is
+    variable result : t_sdb_component;
+  begin
+    result.addr_first := sdb_record(447 downto 384);
+    result.addr_last  := sdb_record(383 downto 320);
+    result.product    := f_sdb_extract_product(sdb_record(319 downto 8));
+    return result;
+  end;
+
+  function f_sdb_embed_device(device : t_sdb_device; address : t_wishbone_address)
+    return t_sdb_record
+  is
+    variable result : t_sdb_record;
+  begin
+    result(511 downto 496) := device.abi_class;
+    result(495 downto 488) := device.abi_ver_major;
+    result(487 downto 480) := device.abi_ver_minor;
+    result(479 downto 456) := (others => '0');
+    result(455)            := device.wbd_endian;
+    result(454 downto 452) := (others => '0');
+    result(451 downto 448) := device.wbd_width;
+    result(447 downto 8)   := f_sdb_embed_component(device.sdb_component, address);
+    result(7 downto 0)     := x"01";    -- device
+    return result;
+  end;
+
+  function f_sdb_extract_device(sdb_record : t_sdb_record)
+    return t_sdb_device
+  is
+    variable result : t_sdb_device;
+  begin
+    result.abi_class     := sdb_record(511 downto 496);
+    result.abi_ver_major := sdb_record(495 downto 488);
+    result.abi_ver_minor := sdb_record(487 downto 480);
+    result.wbd_endian    := sdb_record(452);
+    result.wbd_width     := sdb_record(451 downto 448);
+    result.sdb_component := f_sdb_extract_component(sdb_record(447 downto 8));
+
+    assert sdb_record(7 downto 0) = x"01"
+      report "Cannot extract t_sdb_device from record of type " & integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
+      severity failure;
+    
+    return result;
+  end;
+
+  function f_sdb_embed_msi(msi : t_sdb_msi; address : t_wishbone_address)
+    return t_sdb_record
+  is
+    variable result : t_sdb_record;
+  begin
+    result(511 downto 456) := (others => '0');
+    result(455)            := msi.wbd_endian;
+    result(454 downto 452) := (others => '0');
+    result(451 downto 448) := msi.wbd_width;
+    result(447 downto 8)   := f_sdb_embed_component(msi.sdb_component, address);
+    result(7 downto 0)     := x"03";    -- msi
+    return result;
+  end;
+
+  function f_sdb_extract_msi(sdb_record : t_sdb_record)
+    return t_sdb_msi
+  is
+    variable result : t_sdb_msi;
+  begin
+    result.wbd_endian    := sdb_record(452);
+    result.wbd_width     := sdb_record(451 downto 448);
+    result.sdb_component := f_sdb_extract_component(sdb_record(447 downto 8));
+
+    assert sdb_record(7 downto 0) = x"03"
+      report "Cannot extract t_sdb_msi from record of type " & integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
+      severity failure;
+    
+    return result;
+  end;
+
+  function f_sdb_embed_integration(integr : t_sdb_integration)
+    return t_sdb_record
+  is
+    variable result : t_sdb_record;
+  begin
+    result(511 downto 320) := (others => '0');
+    result(319 downto 8)   := f_sdb_embed_product(integr.product);
+    result(7 downto 0)     := x"80"; -- integration record
+    return result;
+  end f_sdb_embed_integration;
+
+  function f_sdb_extract_integration(sdb_record : t_sdb_record)
+    return t_sdb_integration
+  is
+    variable result : t_sdb_integration;
+  begin
+    result.product := f_sdb_extract_product(sdb_record(319 downto 8));
+
+    assert sdb_record(7 downto 0) = x"80"
+    report "Cannot extract t_sdb_integration from record of type " & Integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
+    severity Failure;
+
+    return result;
+  end f_sdb_extract_integration;
+
+  function f_sdb_embed_repo_url(url : t_sdb_repo_url)
+    return t_sdb_record
+  is
+    variable result : t_sdb_record;
+  begin
+    result(511 downto 8) := f_string2svl(url.repo_url);
+    result(  7 downto 0) := x"81"; -- repo_url record
+    return result;
+  end;
+
+  function f_sdb_extract_repo_url(sdb_record : t_sdb_record)
+    return t_sdb_repo_url
+  is
+    variable result : t_sdb_repo_url;
+  begin
+    result.repo_url     := f_slv2string(sdb_record(511 downto 8));
+
+    assert sdb_record(7 downto 0) = x"81"
+    report "Cannot extract t_sdb_repo_url from record of type " & Integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
+    severity Failure;
+
+    return result;
+  end;
+
+  function f_sdb_embed_synthesis(syn : t_sdb_synthesis)
+    return t_sdb_record
+  is
+    variable result : t_sdb_record;
+  begin
+    result(511 downto 384) := f_string2svl(syn.syn_module_name);
+    result(383 downto 256) := f_string2bits(syn.syn_commit_id);
+    result(255 downto 192) := f_string2svl(syn.syn_tool_name);
+    result(191 downto 160) := syn.syn_tool_version;
+    result(159 downto 128) := syn.syn_date;
+    result(127 downto   8) := f_string2svl(syn.syn_username);
+    result(  7 downto   0) := x"82"; -- synthesis record
+    return result;
+  end;
+
+  function f_sdb_extract_synthesis(sdb_record : t_sdb_record)
+    return t_sdb_synthesis
+  is
+    variable result : t_sdb_synthesis;
+  begin
+    result.syn_module_name  := f_slv2string(sdb_record(511 downto 384));
+    result.syn_commit_id    := f_bits2string(sdb_record(383 downto 256));
+    result.syn_tool_name    := f_slv2string(sdb_record(255 downto 192));
+    result.syn_tool_version := sdb_record(191 downto 160);
+    result.syn_date         := sdb_record(159 downto 128);
+    result.syn_username     := f_slv2string(sdb_record(127 downto   8));
+
+    assert sdb_record(7 downto 0) = x"82"
+    report "Cannot extract t_sdb_repo_url from record of type " & Integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
+    severity Failure;
+
+    return result;
+  end;
+
+  function f_sdb_embed_bridge(bridge : t_sdb_bridge; address : t_wishbone_address)
+    return t_sdb_record
+  is
+    variable result : t_sdb_record;
+
+    constant first : unsigned(63 downto 0) := unsigned(bridge.sdb_component.addr_first);
+    constant child : unsigned(63 downto 0) := unsigned(bridge.sdb_child);
+    variable base  : unsigned(63 downto 0) := (others => '0');
+  begin
+    base(address'length-1 downto 0) := unsigned(address);
+
+    result(511 downto 448) := std_logic_vector(base + child - first);
+    result(447 downto 8)   := f_sdb_embed_component(bridge.sdb_component, address);
+    result(7 downto 0)     := x"02";    -- bridge
+    return result;
+  end;
+
+  function f_sdb_extract_bridge(sdb_record : t_sdb_record)
+    return t_sdb_bridge
+  is
+    variable result : t_sdb_bridge;
+  begin
+    result.sdb_child     := sdb_record(511 downto 448);
+    result.sdb_component := f_sdb_extract_component(sdb_record(447 downto 8));
+
+    assert sdb_record(7 downto 0) = x"02"
+      report "Cannot extract t_sdb_bridge from record of type " & integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
+      severity failure;
+    
+    return result;
+  end;
+  
+  function f_sdb_auto_device(device : t_sdb_device; enable : boolean := true; name: string := "")
+    return t_sdb_record
+  is
+    constant c_zero  : t_wishbone_address := (others => '0');
+    variable v_device: t_sdb_device := device;
+    variable v_empty : t_sdb_record := (others => '0');
+  begin
+    v_empty(7 downto 0) := x"f1";
+    if name /= "" then
+      v_device.sdb_component.product.name := f_string_fix_len(name , 19, ' ', false);
+    end if;
+    if enable then
+      v_empty := f_sdb_embed_device(v_device, c_zero);
+    end if;
+    return v_empty;
+  end f_sdb_auto_device;
+  
+  function f_sdb_auto_bridge(bridge : t_sdb_bridge; enable : boolean := true; name: string := "")
+    return t_sdb_record
+  is
+    constant c_zero  : t_wishbone_address := (others => '0');
+    variable v_bridge: t_sdb_bridge := bridge;
+    variable v_empty : t_sdb_record := (others => '0');
+  begin
+    v_empty(7 downto 0) := x"f2";
+    if name /= "" then
+      v_bridge.sdb_component.product.name := f_string_fix_len(name , 19, ' ', false);
+    end if;
+    if enable then
+      v_empty := f_sdb_embed_bridge(v_bridge, c_zero);
+    end if;
+    return v_empty;
+  end f_sdb_auto_bridge;
+  
+  function f_sdb_auto_msi(msi : t_sdb_msi; enable : boolean := true)
+    return t_sdb_record
+  is
+    constant c_zero  : t_wishbone_address := (others => '0');
+    variable v_empty : t_sdb_record := (others => '0');
+  begin
+    v_empty(7 downto 0) := x"f3";
+    if enable then
+      return f_sdb_embed_msi(msi, c_zero);
+    else
+      return v_empty;
+    end if;
+  end f_sdb_auto_msi;
+  
+  subtype t_usdb_address is unsigned(63 downto 0);
+  type t_usdb_address_array is array(natural range <>) of t_usdb_address;
+  
+  -- We map devices by placing the smallest ones first.
+  -- This is guaranteed to pack the maximum number of devices in the smallest space.
+  -- If a device has an address != 0, we leave it alone and let the crossbar confirm
+  -- that the address does not cause a conflict.
+  function f_sdb_auto_layout_helper(records : t_sdb_record_array)
+    return t_usdb_address_array
+  is
+    alias c_records : t_sdb_record_array(records'length-1 downto 0) is records;
+    constant c_zero : t_usdb_address := (others => '0');
+    
+    constant c_used_entries : natural := c_records'length + 1;
+    constant c_rom_entries  : natural := 2**f_ceil_log2(c_used_entries);
+    constant c_rom_bytes    : natural := c_rom_entries * c_sdb_device_length / 8;
+        
+    variable v_component : t_sdb_component;
+    variable v_sizes     : t_usdb_address_array(c_records'length downto 0);
+    variable v_address   : t_usdb_address_array(c_records'length downto 0);
+    variable v_bus_map   : std_logic_vector(c_records'length downto 0) := (others => '0');
+    variable v_bus_cursor: unsigned(63 downto 0) := (others => '0');
+    variable v_msi_map   : std_logic_vector(c_records'length downto 0) := (others => '0');
+    variable v_msi_cursor: unsigned(63 downto 0) := (others => '0');
+    variable v_increment : unsigned(63 downto 0) := (others => '0');
+    variable v_type      : std_logic_vector(7 downto 0);
+  begin
+    -- First, extract the length of the devices, ignoring those not to be mapped
+    for i in c_records'range loop
+      v_component := f_sdb_extract_component(c_records(i)(447 downto 8));
+      v_sizes(i)   := unsigned(v_component.addr_last);
+      v_address(i) := unsigned(v_component.addr_first);
+      
+      -- Silently round up to a power of two; the crossbar will give a warning for us
+      for j in 62 downto 0 loop
+        v_sizes(i)(j) := v_sizes(i)(j+1) or v_sizes(i)(j);
+      end loop;
+      
+      -- Only map devices/bridges at address zero
+      if v_address(i) = c_zero then
+        v_type := c_records(i)(7 downto 0);
+        case v_type is
+          when x"01" => v_bus_map(i) := '1';
+          when x"02" => v_bus_map(i) := '1';
+          when x"03" => v_msi_map(i) := '1';
+          when others => null;
+        end case;
+      end if;
+    end loop;
+    
+    -- Assign the SDB record a spot as well
+    v_address(c_records'length) := (others => '0');
+    v_sizes(c_records'length) := to_unsigned(c_rom_bytes-1, 64);
+    v_bus_map(c_records'length) := '1';
+    
+    -- Start assigning addresses
+    for j in 0 to 63 loop
+      v_increment := (others => '0');
+      v_increment(j) := '1';
+      
+      for i in 0 to c_records'length loop
+        if v_bus_map(i) = '1' and v_sizes(i)(j) = '0' then
+          v_bus_map(i) := '0';
+          v_address(i) := v_bus_cursor;
+          v_bus_cursor := v_bus_cursor + v_increment;
+        end if;
+        if v_msi_map(i) = '1' and v_sizes(i)(j) = '0' then
+          v_msi_map(i) := '0';
+          v_address(i) := v_msi_cursor;
+          v_msi_cursor := v_msi_cursor + v_increment;
+        end if;
+      end loop;
+      
+      -- Round up to the next required alignment
+      if v_bus_cursor(j) = '1' then
+        v_bus_cursor := v_bus_cursor + v_increment;
+      end if;
+      if v_msi_cursor(j) = '1' then
+        v_msi_cursor := v_msi_cursor + v_increment;
+      end if;
+    end loop;
+    
+    return v_address;
+  end f_sdb_auto_layout_helper;
+  
+  function f_sdb_auto_layout(records : t_sdb_record_array)
+    return t_sdb_record_array
+  is
+    alias    c_records : t_sdb_record_array(records'length-1 downto 0) is records;
+    variable v_typ     : std_logic_vector(7 downto 0);
+    variable v_result  : t_sdb_record_array(c_records'range) := c_records;
+    constant c_address : t_usdb_address_array := f_sdb_auto_layout_helper(c_records);
+    variable v_address : t_wishbone_address;
+  begin
+    -- Put the addresses into the mapping
+    for i in v_result'range loop
+      v_typ     := c_records(i)(7 downto 0);
+      v_address := std_logic_vector(c_address(i)(t_wishbone_address'range));
+
+      case v_typ is
+        when x"01" => v_result(i) := f_sdb_embed_device(f_sdb_extract_device(v_result(i)), v_address);
+        when x"02" => v_result(i) := f_sdb_embed_bridge(f_sdb_extract_bridge(v_result(i)), v_address);
+        when x"03" => v_result(i) := f_sdb_embed_msi   (f_sdb_extract_msi   (v_result(i)), v_address);
+        when others => null;
+      end case;
+    end loop;
+    
+    return v_result;
+  end f_sdb_auto_layout;
+  
+  function f_sdb_auto_layout(slaves : t_sdb_record_array; masters : t_sdb_record_array)
+    return t_sdb_record_array
+  is begin
+    return f_sdb_auto_layout(masters & slaves);
+  end f_sdb_auto_layout;
+  
+  function f_sdb_auto_sdb(records : t_sdb_record_array)
+    return t_wishbone_address
+  is
+    alias    c_records : t_sdb_record_array(records'length-1 downto 0) is records;
+    constant c_address : t_usdb_address_array(c_records'length downto 0) := f_sdb_auto_layout_helper(c_records);
+  begin
+    return std_logic_vector(c_address(c_records'length)(t_wishbone_address'range));
+  end f_sdb_auto_sdb;
+  
+  function f_sdb_auto_sdb(slaves : t_sdb_record_array; masters : t_sdb_record_array)
+    return t_wishbone_address
+  is begin
+    return f_sdb_auto_sdb(masters & slaves);
+  end f_sdb_auto_sdb;
+
+--**************************************************************************************************************************--
+-- START MAT's NEW FUNCTIONS FROM 18th Oct 2013
+------------------------------------------------------------------------------------------------------------------------------
+
+
+   function f_sdb_create_array(g_enum_dev_id    : boolean := false;
+                            g_dev_id_offs    : natural := 0;
+                            g_enum_dev_name  : boolean := false;
+                            g_dev_name_offs  : natural := 0;       
+                            device           : t_sdb_device; 
+                            instances        : natural := 1) 
+   return t_sdb_record_array is
+      variable result   : t_sdb_record_array(instances-1 downto 0);  
+      variable i,j, pos : natural;
+      variable dev, newdev      : t_sdb_device;
+      variable serial_no : string(1 to 3);
+      variable text_possible : boolean := false; 
+   begin
+      dev := device;
+             
+      report "### Creating " & integer'image(instances) & " x " & dev.sdb_component.product.name
+      severity note;       
+      for i in 0 to instances-1 loop
+         newdev := dev;        
+         if(g_enum_dev_id) then         
+            dev.sdb_component.product.device_id :=  
+            std_logic_vector( unsigned(dev.sdb_component.product.device_id) 
+                              + to_unsigned(i+g_dev_id_offs, dev.sdb_component.product.device_id'length));        
+         end if;
+         if(g_enum_dev_name) then         
+         -- find end of name
+            
+            for j in dev.sdb_component.product.name'length downto 1 loop
+               if(dev.sdb_component.product.name(j) /= ' ') then               
+                  pos := j;                  
+                  exit;
+               end if;
+            end loop;
+         -- convert i+g_dev_name_offs to string
+            serial_no := f_string_fix_len(integer'image(i+g_dev_name_offs), serial_no'length);
+            report "### Now: " & serial_no & " of " & dev.sdb_component.product.name severity note;
+         -- check if space is sufficient
+            assert (serial_no'length+1 <= dev.sdb_component.product.name'length - pos)
+            report "Not enough space in namestring of sdb_device " & dev.sdb_component.product.name
+            & " to add serial number " & serial_no & ". Space available " & 
+            integer'image(dev.sdb_component.product.name'length-pos-1) & ", required " 
+            & integer'image(serial_no'length+1)    
+            severity Failure;
+         end if;
+         if(g_enum_dev_name) then
+            newdev.sdb_component.product.name(pos+1) := '_'; 
+            for j in 1 to serial_no'length loop
+               newdev.sdb_component.product.name(pos+1+j) := serial_no(j);
+            end loop;            
+         end if;
+          
+      -- insert
+         report "### to: " & newdev.sdb_component.product.name severity note;
+         result(i) := f_sdb_embed_device(newdev, (others=>'0'));
+      end loop;
+      return result;
+   end f_sdb_create_array;
+
+   function f_sdb_join_arrays(a : t_sdb_record_array; b : t_sdb_record_array) return t_sdb_record_array is
+      variable result   : t_sdb_record_array(a'length+b'length-1 downto 0);  
+      variable i : natural;
+   begin
+      for i in 0 to a'left loop
+         result(i) := a(i);
+      end loop;
+      for i in 0 to b'left loop
+         result(i+a'length) := b(i);
+      end loop;
+      return result;
+   end f_sdb_join_arrays;
+
+
+   function f_sdb_extract_base_addr(sdb_record : t_sdb_record) return std_logic_vector is
+   begin
+      return sdb_record(447 downto 384);
+   end f_sdb_extract_base_addr;
+
+   function f_sdb_extract_end_addr(sdb_record : t_sdb_record) return std_logic_vector is
+   begin
+      return sdb_record(383 downto 320);
+   end f_sdb_extract_end_addr;
+
+
+   function f_align_addr_offset(offs : unsigned; this_rng : unsigned; prev_rng : unsigned)
+   return unsigned is
+      variable this_pow, prev_pow   : natural;  
+      variable start, env, result : unsigned(63 downto 0) := (others => '0');
+   begin
+      start(offs'left downto 0) := offs;   
+      --calculate address envelopes (next power of 2) for previous and this component and choose the larger one
+      this_pow := f_hot_to_bin(std_logic_vector(this_rng)); 
+      prev_pow := f_hot_to_bin(std_logic_vector(prev_rng));    
+      -- no max(). thank you very much, std_numeric :-/   
+      if(this_pow >= prev_pow) then
+         env(this_pow) := '1';
+      else
+         env(prev_pow) := '1';
+      end if;
+      --round up to the next multiple of the envelope...
+      if(prev_rng /= 0) then   
+         result := start + env - (start mod env);
+      else
+         result := start;   --...except for first element, result is start. 
+      end if;
+      return result;
+   end f_align_addr_offset;
+
+
+ -- generates aligned address map for an sdb_record_array, accepts optional start offset 
+   function f_sdb_automap_array(sdb_array : t_sdb_record_array; start_offset : t_wishbone_address := (others => '0'))
+   return t_sdb_record_array is
+      constant len         : natural := sdb_array'length;
+      variable this_rng    : unsigned(63 downto 0) := (others => '0');   
+      variable prev_rng    : unsigned(63 downto 0) := (others => '0');   
+      variable prev_offs   : unsigned(63 downto 0) := (others => '0');   
+      variable this_offs   : unsigned(63 downto 0) := (others => '0');   
+      variable device      : t_sdb_device;
+      variable bridge      : t_sdb_bridge;  
+      variable sdb_type    : std_logic_vector(7 downto 0);
+      variable i           : natural;
+      variable result      : t_sdb_record_array(sdb_array'length-1 downto 0); -- last 
+   begin
+   
+      prev_offs(start_offset'left downto 0) := unsigned(start_offset);
+      --traverse the array   
+      for i in 0 to len-1 loop
+         -- find the fitting extraction function by evaling the type byte. 
+         -- could also use the component, but it's safer to use Wes' embed and extract functions.      
+         sdb_type := sdb_array(i)(7 downto 0);
+         case sdb_type is
+            --device         
+            when x"01"  => device      := f_sdb_extract_device(sdb_array(i));
+                           this_rng    := unsigned(device.sdb_component.addr_last) - unsigned(device.sdb_component.addr_first);                      
+                           this_offs   := f_align_addr_offset(prev_offs, this_rng, prev_rng);
+                           result(i)   := f_sdb_embed_device(device, std_logic_vector(this_offs(31 downto 0)));
+            --bridge
+            when x"02"  => bridge      := f_sdb_extract_bridge(sdb_array(i));
+                           this_rng    := unsigned(bridge.sdb_component.addr_last) - unsigned(bridge.sdb_component.addr_first);
+                           this_offs   := f_align_addr_offset(prev_offs, this_rng, prev_rng);
+                           result(i)   := f_sdb_embed_bridge(bridge, std_logic_vector(this_offs(31 downto 0)) );
+            --other
+            when others => result(i) := sdb_array(i);   
+         end case;
+         -- doesnt hurt because this_* doesnt change if its not a device or bridge
+         prev_rng    := this_rng;
+         prev_offs   := this_offs;
+      end loop;
+      report "##* " & integer'image(sdb_array'length) & " Elements, last address: " & f_bits2string(std_logic_vector(this_offs+this_rng)) severity Note;
+      return result;
+   end f_sdb_automap_array;
+
+
+  -- find place for sdb rom on crossbar and return address. try to put it in an address gap.
+   function f_sdb_create_rom_addr(sdb_array : t_sdb_record_array) return t_wishbone_address is
+      constant len                  : natural := sdb_array'length;
+      constant rom_bytes            : natural := (2**f_ceil_log2(sdb_array'length + 1)) * (c_sdb_device_length / 8);
+      variable result               : t_wishbone_address  := (others => '0');
+      variable this_base, this_end  : unsigned(63 downto 0)          := (others => '0');    
+      variable prev_base, prev_end  : unsigned(63 downto 0)          := (others => '0');
+      variable rom_base             : unsigned(63 downto 0)          := (others => '0');
+      variable sdb_type             : std_logic_vector(7 downto 0);     
+   begin
+      --traverse the array   
+      for i in 0 to len-1 loop     
+         sdb_type := sdb_array(i)(7 downto 0);
+         if(sdb_type = x"01" or sdb_type = x"02") then
+            -- get         
+            this_base := unsigned(f_sdb_extract_base_addr(sdb_array(i)));
+            this_end  := unsigned(f_sdb_extract_end_addr(sdb_array(i)));
+            if(unsigned(result) = 0) then
+               rom_base := f_align_addr_offset(prev_base, to_unsigned(rom_bytes-1, 64), (prev_end-prev_base));
+               if(rom_base + to_unsigned(rom_bytes, 64) <= this_base) then
+                  result := std_logic_vector(rom_base(t_wishbone_address'left downto 0));
+               end if;   
+            end if;
+            prev_base := this_base;
+            prev_end  := this_end;      
+         end if;
+      end loop;   
+      -- if there was no gap to fit the sdb rom, place it at the end   
+      if(unsigned(result) = 0) then
+            result := std_logic_vector(f_align_addr_offset(this_base, to_unsigned(rom_bytes-1, 64), 
+                                       this_end-this_base)(t_wishbone_address'left downto 0));   
+      end if;      
+      return result;
+   end f_sdb_create_rom_addr; 
+------------------------------------------------------------------------------------------------------------------------------
+-- END MAT's NEW FUNCTIONS FROM  18th Oct 2013
+------------------------------------------------------------------------------------------------------------------------------
+
+  function f_sdb_bus_end(
+    g_wraparound : boolean;
+    g_layout     : t_sdb_record_array;
+    g_sdb_addr   : t_wishbone_address;
+    msi          : boolean) return unsigned
+  is
+    alias c_layout : t_sdb_record_array(g_layout'length-1 downto 0) is g_layout;
+
+    -- How much space does the ROM need?
+    constant c_used_entries : natural := c_layout'length + 1;
+    constant c_rom_entries  : natural := 2**f_ceil_log2(c_used_entries);  -- next power of 2
+    constant c_sdb_bytes    : natural := c_sdb_device_length / 8;
+    constant c_rom_bytes    : natural := c_rom_entries * c_sdb_bytes;
+    
+    variable result : unsigned(63 downto 0) := (others => '0');
+    variable typ    : std_logic_vector(7 downto 0);
+    variable last   : unsigned(63 downto 0);
+  begin
+    if not msi then
+      -- The ROM will be an addressed slave as well
+      result := (others => '0');
+      result(g_sdb_addr'range) := unsigned(g_sdb_addr);
+      result := result + to_unsigned(c_rom_bytes, 64) - 1;
+    end if;
+    
+    for i in c_layout'range loop
+      typ  := c_layout(i)(7 downto 0);
+      last := unsigned(f_sdb_extract_component(c_layout(i)(447 downto 8)).addr_last);
+      case typ is
+        when x"01" => if not msi and last > result then result := last; end if;
+        when x"02" => if not msi and last > result then result := last; end if;
+        when x"03" => if     msi and last > result then result := last; end if;
+        when others => null;
+      end case;
+    end loop;
+    
+    -- round result up to a power of two -1
+    for i in 62 downto 0 loop
+      result(i) := result(i) or result(i+1);
+    end loop;
+    
+    if not g_wraparound then
+      result := (others => '0');
+      for i in 0 to c_wishbone_address_width-1 loop
+        result(i) := '1';
+      end loop;
+    end if;
+    
+    return result;
+  end f_sdb_bus_end;
+
+  function f_xwb_bridge_manual_sdb(
+    g_size     : t_wishbone_address;
+    g_sdb_addr : t_wishbone_address) return t_sdb_bridge
+  is
+    variable result : t_sdb_bridge;
+  begin
+    result.sdb_child                                      := (others => '0');
+    result.sdb_child(c_wishbone_address_width-1 downto 0) := g_sdb_addr;
+
+    result.sdb_component.addr_first                                     := (others => '0');
+    result.sdb_component.addr_last                                      := (others => '0');
+    result.sdb_component.addr_last(c_wishbone_address_width-1 downto 0) := g_size;
+
+    result.sdb_component.product.vendor_id := x"0000000000000651";  -- GSI
+    result.sdb_component.product.device_id := x"eef0b198";
+    result.sdb_component.product.version   := x"00000001";
+    result.sdb_component.product.date      := x"20120511";
+    result.sdb_component.product.name      := "WB4-Bridge-GSI     ";
+
+    return result;
+  end f_xwb_bridge_manual_sdb;
+  
+  function f_xwb_bridge_layout_sdb(     -- determine bus size from layout
+    g_wraparound : boolean := true;
+    g_layout     : t_sdb_record_array;
+    g_sdb_addr   : t_wishbone_address) return t_sdb_bridge
+  is
+    variable address : t_wishbone_address;
+  begin
+    address := std_logic_vector(f_sdb_bus_end(g_wraparound, g_layout, g_sdb_addr, false)(address'range));
+    return f_xwb_bridge_manual_sdb(address, g_sdb_addr);
+  end f_xwb_bridge_layout_sdb;
+
+  function f_xwb_msi_manual_sdb(
+    g_size     : t_wishbone_address) return t_sdb_msi
+  is
+    variable result : t_sdb_msi;
+  begin
+    result.wbd_endian := '0';
+    result.wbd_width  := x"7";
+
+    result.sdb_component.addr_first                                     := (others => '0');
+    result.sdb_component.addr_last                                      := (others => '0');
+    result.sdb_component.addr_last(c_wishbone_address_width-1 downto 0) := g_size;
+
+    result.sdb_component.product.vendor_id := x"0000000000000651";  -- GSI
+    result.sdb_component.product.device_id := x"aa7bfb3c";
+    result.sdb_component.product.version   := x"00000001";
+    result.sdb_component.product.date      := x"20160422";
+    result.sdb_component.product.name      := "WB4-MSI-Bridge-GSI ";
+
+    return result;
+  end f_xwb_msi_manual_sdb;
+  
+  function f_xwb_msi_layout_sdb(     -- determine MSI size from layout
+    g_layout     : t_sdb_record_array) return t_sdb_msi
+  is
+    constant zero : t_wishbone_address := (others => '0');
+    variable address : t_wishbone_address;
+  begin
+    address := std_logic_vector(f_sdb_bus_end(true, g_layout, zero, true)(address'range));
+    return f_xwb_msi_manual_sdb(address);
+  end f_xwb_msi_layout_sdb;
+  
+  function f_xwb_dpram(g_size : natural) return t_sdb_device
+  is
+    variable result : t_sdb_device;
+  begin
+    result.abi_class     := x"0001";    -- RAM device
+    result.abi_ver_major := x"01";
+    result.abi_ver_minor := x"00";
+    result.wbd_width     := x"7";       -- 32/16/8-bit supported
+    result.wbd_endian    := c_sdb_endian_big;
+
+    result.sdb_component.addr_first := (others => '0');
+    result.sdb_component.addr_last  := std_logic_vector(to_unsigned(g_size*4-1, 64));
+
+    result.sdb_component.product.vendor_id := x"000000000000CE42";  -- CERN
+    result.sdb_component.product.device_id := x"66cfeb52";
+    result.sdb_component.product.version   := x"00000001";
+    result.sdb_component.product.date      := x"20120305";
+    result.sdb_component.product.name      := "WB4-BlockRAM       ";
+
+    return result;
+  end f_xwb_dpram;
+
+  function f_bits2string(s : std_logic_vector) return string is
+    --- extend length to full hex nibble
+    variable result : string((s'length+7)/4 downto 1);
+    variable s_norm : std_logic_vector(result'length*4-1 downto 0) := (others=>'0');
+    variable cut : natural;
+    variable nibble: std_logic_vector(3 downto 0);
+    constant len : natural := result'length;
+  begin
+    s_norm(s'length-1 downto 0) := s;
+    for i in len-1 downto 0 loop
+      nibble := s_norm(i*4+3 downto i*4);
+      case nibble is
+        when "0000" => result(i+1) := '0';
+        when "0001" => result(i+1) := '1';
+        when "0010" => result(i+1) := '2';
+        when "0011" => result(i+1) := '3';
+        when "0100" => result(i+1) := '4';
+        when "0101" => result(i+1) := '5';
+        when "0110" => result(i+1) := '6';
+        when "0111" => result(i+1) := '7';
+        when "1000" => result(i+1) := '8';
+        when "1001" => result(i+1) := '9';
+        when "1010" => result(i+1) := 'a';
+        when "1011" => result(i+1) := 'b';
+        when "1100" => result(i+1) := 'c';
+        when "1101" => result(i+1) := 'd';
+        when "1110" => result(i+1) := 'e';
+        when "1111" => result(i+1) := 'f';
+        when others => result(i+1) := 'X';
+      end case;
+    end loop;
+
+    -- trim leading 0s
+    strip : for i in result'length downto 1 loop
+      cut := i;
+      exit strip when result(i) /= '0';
+    end loop;
+
+    return "0x" & result(cut downto 1);
+  end f_bits2string;
+
+  -- Converts string (hex number, without leading 0x) to std_logic_vector
+  function f_string2bits(s : string) return std_logic_vector is
+    constant len : natural := s'length;
+    variable slv : std_logic_vector(s'length*4-1 downto 0);
+    variable nibble : std_logic_vector(3 downto 0);
+  begin
+    for i in 0 to len-1 loop
+      case s(i+1) is
+        when '0' => nibble := X"0";
+        when '1' => nibble := X"1";
+        when '2' => nibble := X"2";
+        when '3' => nibble := X"3";
+        when '4' => nibble := X"4";
+        when '5' => nibble := X"5";
+        when '6' => nibble := X"6";
+        when '7' => nibble := X"7";
+        when '8' => nibble := X"8";
+        when '9' => nibble := X"9";
+        when 'a' => nibble := X"A";
+        when 'A' => nibble := X"A";
+        when 'b' => nibble := X"B";
+        when 'B' => nibble := X"B";
+        when 'c' => nibble := X"C";
+        when 'C' => nibble := X"C";
+        when 'd' => nibble := X"D";
+        when 'D' => nibble := X"D";
+        when 'e' => nibble := X"E";
+        when 'E' => nibble := X"E";
+        when 'f' => nibble := X"F";
+        when 'F' => nibble := X"F";
+        when others => nibble := "XXXX";
+      end case;
+      if s'ascending then
+        slv(slv'length-(i*4)-1 downto slv'length-(i+1)*4) := nibble;
+      else
+        slv(((i+1)*4)-1 downto i*4) := nibble;
+      end if;
+    end loop;
+    return slv;
+  end f_string2bits;
+
+  -- Converts string to ascii (std_logic_vector)
+  function f_string2svl (s : string) return std_logic_vector is
+    constant len : natural := s'length;
+    variable slv : std_logic_vector((s'length * 8) - 1 downto 0);
+  begin
+    for i in 0 to len-1 loop
+      slv(slv'high-i*8 downto (slv'high-7)-i*8) :=
+        std_logic_vector(to_unsigned(character'pos(s(i+1)), 8));
+    end loop;
+    return slv;
+  end f_string2svl;
+
+  -- Converts ascii (std_logic_vector) to string
+  function f_slv2string (slv : std_logic_vector) return string is
+    constant len : natural := slv'length;
+    variable s : string(1 to slv'length/8);
+  begin
+    for i in 0 to (len/8)-1 loop
+      s(i+1) := character'val(to_integer(unsigned(slv(slv'high-i*8 downto (slv'high-7)-i*8))));
+    end loop;
+    return s;
+  end f_slv2string;
+
+    -- pads a string of unknown length to a given length (useful for integer'image)
+  function f_string_fix_len ( s : string; ret_len : natural := 10; fill_char : character := '0'; justify_right : boolean := true ) return string is
+      variable ret_v : string (1 to ret_len);
+      constant pad_len : integer := ret_len - s'length ;
+      variable pad_v : string (1 to abs(pad_len));
+   begin
+      if pad_len < 1 then
+         ret_v := s(ret_v'range);
+      else
+         pad_v := (others => fill_char);
+         if justify_right then
+           ret_v := pad_v & s;
+         else
+           ret_v := s & pad_v ;
+         end if;
+      end if;
+      return ret_v;
+   end f_string_fix_len;
+
+   -- do not synthesize
+   function f_hot_to_bin(x : std_logic_vector) return natural is
+      variable rv : natural;
+   begin
+      rv := 0;
+      -- if there are few ones set in _x_ then the most significant will be
+      -- translated to bin
+      for i in 0 to x'left loop
+         if x(i) = '1' then
+           rv := i+1;
+         end if;
+      end loop;
+      return rv;
+  end function;  
+
+  function f_wb_spi_flash_sdb(g_bits : natural) return t_sdb_device is
+    variable result : t_sdb_device := (
+      abi_class     => x"0000", -- undocumented device
+      abi_ver_major => x"01",
+      abi_ver_minor => x"02",
+      wbd_endian    => c_sdb_endian_big,
+      wbd_width     => x"7", -- 8/16/32-bit port granularity
+      sdb_component => (
+      addr_first    => x"0000000000000000",
+      addr_last     => x"0000000000ffffff",
+      product => (
+      vendor_id     => x"0000000000000651", -- GSI
+      device_id     => x"5cf12a1c",
+      version       => x"00000002",
+      date          => x"20140417",
+      name          => "SPI-FLASH-16M-MMAP ")));
+  begin
+    result.sdb_component.addr_last := std_logic_vector(to_unsigned(2**g_bits-1, 64));
+    return result;
+  end f_wb_spi_flash_sdb;
+  
+end wishbone_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/wr_fabric_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/wr_fabric_pkg.vhd
new file mode 100644
index 000000000..3e15d94cc
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/wr_fabric_pkg.vhd
@@ -0,0 +1,220 @@
+-------------------------------------------------------------------------------
+-- Title      : Wishbone Packet Fabric package
+-- Project    : WR Cores Collection
+-------------------------------------------------------------------------------
+-- File       : wr_fabric_pkg.vhd
+-- Author     : Grzegorz Daniluk
+-- Company    : CERN BE-CO-HT
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.wishbone_pkg.all;
+
+
+package wr_fabric_pkg is
+
+  constant c_WRF_DATA   : std_logic_vector(1 downto 0) := "00";
+  constant c_WRF_OOB    : std_logic_vector(1 downto 0) := "01";
+  constant c_WRF_STATUS : std_logic_vector(1 downto 0) := "10";
+  constant c_WRF_USER   : std_logic_vector(1 downto 0) := "11";
+
+  constant c_WRF_OOB_TYPE_RX : std_logic_vector(3 downto 0) := "0000";
+  constant c_WRF_OOB_TYPE_TX : std_logic_vector(3 downto 0) := "0001";
+
+  type t_wrf_mux_class is array (natural range <>) of std_logic_vector(7 downto 0);
+
+  type t_wrf_status_reg is record
+    is_hp       : std_logic;
+    has_smac    : std_logic;
+    has_crc     : std_logic;
+    error       : std_logic;
+    tag_me      : std_logic;
+    match_class : std_logic_vector(7 downto 0);
+  end record;
+
+  type t_wrf_source_out is record
+    adr : std_logic_vector(1 downto 0);
+    dat : std_logic_vector(15 downto 0);
+    cyc : std_logic;
+    stb : std_logic;
+    we  : std_logic;
+    sel : std_logic_vector(1 downto 0);
+  end record;
+
+  type t_wrf_source_in is record
+    ack   : std_logic;
+    stall : std_logic;
+    err   : std_logic;
+    rty   : std_logic;
+  end record;
+
+
+  type t_wrf_oob is record
+    valid: std_logic;
+    oob_type : std_logic_vector(3 downto 0);
+    ts_r     : std_logic_vector(27 downto 0);
+    ts_f     : std_logic_vector(3 downto 0);
+    frame_id : std_logic_vector(15 downto 0);
+    port_id  : std_logic_vector(5 downto 0);
+  end record;
+
+  subtype t_wrf_sink_in is t_wrf_source_out;
+  subtype t_wrf_sink_out is t_wrf_source_in;
+
+  type t_wrf_source_in_array is array (natural range <>) of t_wrf_source_in;
+  type t_wrf_source_out_array is array (natural range <>) of t_wrf_source_out;
+
+  subtype t_wrf_sink_in_array is t_wrf_source_out_array;
+  subtype t_wrf_sink_out_array is t_wrf_source_in_array;
+
+  function f_marshall_wrf_status (stat  : t_wrf_status_reg) return std_logic_vector;
+  function f_unmarshall_wrf_status(stat : std_logic_vector) return t_wrf_status_reg;
+
+  constant c_wrf_status_init_value : t_wrf_status_reg :=
+    ('0', '0', '0', '0', '0', (others => '0'));
+
+  constant c_dummy_src_in : t_wrf_source_in :=
+    ('0', '0', '0', '0');
+  constant c_dummy_snk_in : t_wrf_sink_in :=
+    ("XX", "XXXXXXXXXXXXXXXX", '0', '0', '0', "XX");
+
+
+  -----------------------------------------------------------------------------
+  -- WRF MUX
+  -----------------------------------------------------------------------------
+  component xwrf_mux is
+    generic(
+      g_muxed_ports	:	integer := 2);
+    port(
+      clk_sys_i	: in std_logic;
+      rst_n_i		: in std_logic;
+      --ENDPOINT
+      ep_src_o	:	out t_wrf_source_out;
+      ep_src_i	: in  t_wrf_source_in;
+      ep_snk_o	: out t_wrf_sink_out;
+      ep_snk_i  : in  t_wrf_sink_in;
+      --Muxed ports
+      mux_src_o : out t_wrf_source_out_array(g_muxed_ports-1 downto 0);
+      mux_src_i : in  t_wrf_source_in_array(g_muxed_ports-1 downto 0);
+      mux_snk_o : out t_wrf_sink_out_array(g_muxed_ports-1 downto 0);
+      mux_snk_i : in  t_wrf_sink_in_array(g_muxed_ports-1 downto 0);
+      --
+      mux_class_i : in t_wrf_mux_class(g_muxed_ports-1 downto 0)
+    );
+  end component;
+
+  component xwrf_reg is
+    generic(
+      g_adr_width : integer := 2;
+      g_dat_width : integer :=16);
+    port(
+      rst_n_i	:	in std_logic;
+      clk_i   : in std_logic;
+      snk_i		: in  t_wrf_sink_in;
+      snk_o		:	out t_wrf_sink_out;
+      src_i		:	in 	t_wrf_source_in;
+      src_o		:	out t_wrf_source_out);
+  end component;
+
+  component xwrf_loopback
+    generic(
+      g_interface_mode        : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity   : t_wishbone_address_granularity := WORD);
+    port(
+      clk_sys_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+  
+      wrf_snk_i : in  t_wrf_sink_in;
+      wrf_snk_o : out t_wrf_sink_out;
+      wrf_src_o : out t_wrf_source_out;
+      wrf_src_i : in  t_wrf_source_in;
+  
+      wb_i : in  t_wishbone_slave_in;
+      wb_o : out t_wishbone_slave_out);
+  end component;
+
+  component xwb_fabric_sink
+    port (
+      clk_i     : in  std_logic;
+      rst_n_i   : in  std_logic;
+      snk_i     : in  t_wrf_sink_in;
+      snk_o     : out t_wrf_sink_out;
+      addr_o    : out std_logic_vector(1 downto 0);
+      data_o    : out std_logic_vector(15 downto 0);
+      dvalid_o  : out std_logic;
+      sof_o     : out std_logic;
+      eof_o     : out std_logic;
+      error_o   : out std_logic;
+      bytesel_o : out std_logic;
+      dreq_i    : in  std_logic);
+  end component;
+
+  component xwb_fabric_source
+    port (
+      clk_i     : in  std_logic;
+      rst_n_i   : in  std_logic;
+      src_i     : in  t_wrf_source_in;
+      src_o     : out t_wrf_source_out;
+      addr_i    : in  std_logic_vector(1 downto 0);
+      data_i    : in  std_logic_vector(15 downto 0);
+      dvalid_i  : in  std_logic;
+      sof_i     : in  std_logic;
+      eof_i     : in  std_logic;
+      error_i   : in  std_logic;
+      bytesel_i : in  std_logic;
+      dreq_o    : out std_logic);
+  end component;
+
+end wr_fabric_pkg;
+
+package body wr_fabric_pkg is
+
+  function f_marshall_wrf_status(stat : t_wrf_status_reg)
+    return std_logic_vector is
+    variable tmp : std_logic_vector(15 downto 0);
+  begin
+    tmp(0)           := stat.is_hp;
+    tmp(1)           := stat.error;
+    tmp(2)           := stat.has_smac;
+    tmp(3)           := stat.has_crc;
+    tmp(15 downto 8) := stat.match_class;
+    return tmp;
+  end function;
+
+  function f_unmarshall_wrf_status(stat : std_logic_vector) return t_wrf_status_reg is
+    variable tmp : t_wrf_status_reg;
+  begin
+    tmp.is_hp       := stat(0);
+    tmp.error       := stat(1);
+    tmp.has_smac    := stat(2);
+    tmp.has_crc     := stat(3);
+    tmp.match_class := stat(15 downto 8);
+    return tmp;
+    
+  end function;
+
+
+end wr_fabric_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwb_fabric_sink.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwb_fabric_sink.vhd
new file mode 100644
index 000000000..978516c38
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwb_fabric_sink.vhd
@@ -0,0 +1,265 @@
+-------------------------------------------------------------------------------
+-- Title      : Wishbone Packet Fabric buffered packet sink
+-- Project    : WR Cores Collection
+-------------------------------------------------------------------------------
+-- File       : xwb_fabric_sink.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-01-16
+-- Last update: 2012-01-22
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: A simple WB packet streaming sink with builtin FIFO buffer.
+-- Outputs a trivial interface (start-of-packet, end-of-packet, data-valid)
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-16  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.genram_pkg.all;
+use work.wr_fabric_pkg.all;
+
+entity xwb_fabric_sink is
+  
+  port (
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    -- Wishbone Fabric Interface I/O
+    snk_i : in  t_wrf_sink_in;
+    snk_o : out t_wrf_sink_out;
+
+    -- Decoded & buffered fabric
+    addr_o    : out std_logic_vector(1 downto 0);
+    data_o    : out std_logic_vector(15 downto 0);
+    dvalid_o  : out std_logic;
+    sof_o     : out std_logic;
+    eof_o     : out std_logic;
+    error_o   : out std_logic;
+    bytesel_o : out std_logic;
+    dreq_i    : in  std_logic
+    );
+
+end xwb_fabric_sink;
+
+architecture rtl of xwb_fabric_sink is
+
+  constant c_fifo_width : integer := 16 + 2 + 4;
+
+  signal q_valid, full, we, rd : std_logic;
+  signal fin, fout, fout_reg   : std_logic_vector(c_fifo_width-1 downto 0);
+  signal cyc_d0, rd_d0         : std_logic;
+
+  signal pre_sof, pre_eof, pre_bytesel, pre_dvalid : std_logic;
+  signal post_sof, post_dvalid                     : std_logic;
+  signal post_addr                                 : std_logic_vector(1 downto 0);
+  signal post_data                                 : std_logic_vector(15 downto 0);
+
+  signal snk_out : t_wrf_sink_out;
+  
+begin  -- rtl
+
+
+  p_delay_cyc_and_rd : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        cyc_d0 <= '0';
+        rd_d0  <= '0';
+      else
+        if(full = '0') then
+          cyc_d0 <= snk_i.cyc;
+        end if;
+
+        rd_d0 <= rd;
+      end if;
+    end if;
+  end process;
+
+
+  pre_sof     <= snk_i.cyc and not cyc_d0;  -- sof
+  pre_eof     <= not snk_i.cyc and cyc_d0;  -- eof
+  pre_bytesel <= not snk_i.sel(0);      -- bytesel
+  pre_dvalid  <= snk_i.stb and snk_i.we and snk_i.cyc and not snk_out.stall;  -- data valid
+
+  fin(15 downto 0)  <= snk_i.dat;
+  fin(17 downto 16) <= snk_i.adr;
+  fin(21 downto 18) <= pre_sof & pre_eof & pre_bytesel & pre_dvalid;
+
+
+  snk_out.stall <= full or (snk_i.cyc and not cyc_d0);
+  snk_out.err   <= '0';
+  snk_out.rty   <= '0';
+
+  p_gen_ack : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        snk_out.ack <= '0';
+      else
+        snk_out.ack <= snk_i.cyc and snk_i.stb and snk_i.we and not snk_out.stall;
+      end if;
+    end if;
+  end process;
+
+  snk_o <= snk_out;
+
+  we <= '1' when fin(21 downto 18) /= "0000" and full = '0' else '0';
+  rd <= q_valid and dreq_i and not post_sof;
+
+  U_FIFO : generic_shiftreg_fifo
+    generic map (
+      g_data_width => c_fifo_width,
+      g_size       => 16)
+    port map (
+      rst_n_i       => rst_n_i,
+      clk_i         => clk_i,
+      d_i           => fin,
+      we_i          => we,
+      q_o           => fout,
+      rd_i          => rd,
+      almost_full_o => full,
+      q_valid_o     => q_valid);
+
+  p_fout_reg : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        fout_reg <= (others => '0');
+      elsif(rd = '1') then
+        fout_reg <= fout;
+      end if;
+    end if;
+  end process;
+
+
+  post_data <= fout_reg(15 downto 0);
+  post_addr <= fout_reg(17 downto 16);
+  post_sof  <= fout_reg(21) and rd_d0; --and q_valid;
+
+  post_dvalid <= fout_reg(18);
+
+  sof_o     <= post_sof and rd_d0;
+  dvalid_o  <= post_dvalid and rd_d0;
+  error_o   <= '1' when rd_d0 = '1' and (post_addr = c_WRF_STATUS) and (f_unmarshall_wrf_status(post_data).error = '1') else '0';
+  eof_o     <= fout_reg(20) and rd_d0;
+  bytesel_o <= fout_reg(19);
+  data_o    <= post_data;
+  addr_o    <= post_addr;
+
+  
+end rtl;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.genram_pkg.all;
+use work.wr_fabric_pkg.all;
+
+
+entity wb_fabric_sink is
+
+  port (
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    snk_dat_i   : in  std_logic_vector(15 downto 0);
+    snk_adr_i   : in  std_logic_vector(1 downto 0);
+    snk_sel_i   : in  std_logic_vector(1 downto 0);
+    snk_cyc_i   : in  std_logic;
+    snk_stb_i   : in  std_logic;
+    snk_we_i    : in  std_logic;
+    snk_stall_o : out std_logic;
+    snk_ack_o   : out std_logic;
+    snk_err_o   : out std_logic;
+    snk_rty_o   : out std_logic;
+
+    -- Decoded & buffered fabric
+    addr_o    : out std_logic_vector(1 downto 0);
+    data_o    : out std_logic_vector(15 downto 0);
+    dvalid_o  : out std_logic;
+    sof_o     : out std_logic;
+    eof_o     : out std_logic;
+    error_o   : out std_logic;
+    bytesel_o : out std_logic;
+    dreq_i    : in  std_logic
+    );
+
+end wb_fabric_sink;
+
+architecture wrapper of wb_fabric_sink is
+
+  component xwb_fabric_sink
+    port (
+      clk_i     : in  std_logic;
+      rst_n_i   : in  std_logic;
+      snk_i     : in  t_wrf_sink_in;
+      snk_o     : out t_wrf_sink_out;
+      addr_o    : out std_logic_vector(1 downto 0);
+      data_o    : out std_logic_vector(15 downto 0);
+      dvalid_o  : out std_logic;
+      sof_o     : out std_logic;
+      eof_o     : out std_logic;
+      error_o   : out std_logic;
+      bytesel_o : out std_logic;
+      dreq_i    : in  std_logic);
+  end component;
+
+  signal snk_in  : t_wrf_sink_in;
+  signal snk_out : t_wrf_sink_out;
+  
+begin  -- wrapper
+
+  U_Wrapped_Sink : xwb_fabric_sink
+    port map (
+      clk_i     => clk_i,
+      rst_n_i   => rst_n_i,
+      snk_i     => snk_in,
+      snk_o     => snk_out,
+      addr_o    => addr_o,
+      data_o    => data_o,
+      dvalid_o  => dvalid_o,
+      sof_o     => sof_o,
+      eof_o     => eof_o,
+      error_o   => error_o,
+      bytesel_o => bytesel_o,
+      dreq_i    => dreq_i);
+
+  snk_in.adr <= snk_adr_i;
+  snk_in.dat <= snk_dat_i;
+  snk_in.stb <= snk_stb_i;
+  snk_in.we  <= snk_we_i;
+  snk_in.cyc <= snk_cyc_i;
+  snk_in.sel <= snk_sel_i;
+
+  snk_stall_o <= snk_out.stall;
+  snk_ack_o   <= snk_out.ack;
+  snk_err_o   <= snk_out.err;
+  snk_rty_o   <= snk_out.rty;
+  
+end wrapper;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwb_fabric_source.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwb_fabric_source.vhd
new file mode 100644
index 000000000..ec79fb316
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwb_fabric_source.vhd
@@ -0,0 +1,229 @@
+-------------------------------------------------------------------------------
+-- Title      : Wishbone Packet Fabric buffered packet source
+-- Project    : WR Cores Collection
+-------------------------------------------------------------------------------
+-- File       : xwb_fabric_source.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-01-16
+-- Last update: 2012-01-22
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.genram_pkg.all;
+use work.wr_fabric_pkg.all;
+
+entity xwb_fabric_source is
+  
+  port (
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    -- Wishbone Fabric Interface I/O
+    src_i : in  t_wrf_source_in;
+    src_o : out t_wrf_source_out;
+
+    -- Decoded & buffered fabric
+    addr_i    : in  std_logic_vector(1 downto 0);
+    data_i    : in  std_logic_vector(15 downto 0);
+    dvalid_i  : in  std_logic;
+    sof_i     : in  std_logic;
+    eof_i     : in  std_logic;
+    error_i   : in  std_logic;
+    bytesel_i : in  std_logic;
+    dreq_o    : out std_logic
+    );
+
+end xwb_fabric_source;
+
+architecture rtl of xwb_fabric_source is
+
+  constant c_fifo_width : integer := 16 + 2 + 4;
+
+  signal q_valid, full, we, rd, rd_d0 : std_logic;
+  signal fin, fout                    : std_logic_vector(c_fifo_width-1 downto 0);
+
+  signal pre_dvalid : std_logic;
+  signal pre_eof    : std_logic;
+  signal pre_data   : std_logic_vector(15 downto 0);
+  signal pre_addr   : std_logic_vector(1 downto 0);
+
+  signal post_dvalid, post_eof, post_bytesel, post_sof : std_logic;
+
+  signal err_status : t_wrf_status_reg;
+  signal cyc_int    : std_logic;
+  
+begin  -- rtl
+
+  err_status.error <= '1';
+
+  dreq_o <= not full;
+
+  rd <= not src_i.stall;
+  we <= sof_i or eof_i or error_i or dvalid_i;
+
+  pre_dvalid <= dvalid_i or error_i;
+  pre_data   <= data_i when (error_i = '0') else f_marshall_wrf_status(err_status);
+  pre_addr   <= addr_i when (error_i = '0') else c_WRF_STATUS;
+  pre_eof    <= error_i or eof_i;
+
+  fin <= sof_i & pre_eof & bytesel_i & pre_dvalid & pre_addr & pre_data;
+
+  U_FIFO : generic_shiftreg_fifo
+    generic map (
+      g_data_width => c_fifo_width,
+      g_size       => 16)
+    port map (
+      rst_n_i       => rst_n_i,
+      clk_i         => clk_i,
+      d_i           => fin,
+      we_i          => we,
+      q_o           => fout,
+      rd_i          => rd,
+      almost_full_o => full,
+      q_valid_o     => q_valid);
+
+  post_sof    <= fout(21);
+  post_eof    <= fout(20);
+  post_dvalid <= fout(18);
+
+  p_gen_cyc : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        cyc_int <= '0';
+      else
+        if( q_valid = '1') then
+          if(post_sof = '1')then
+            cyc_int <= '1';
+          elsif(post_eof = '1') then
+            cyc_int <= '0';
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  src_o.cyc <= cyc_int;
+  src_o.we  <= '1';
+  src_o.stb <= post_dvalid and q_valid;
+  src_o.sel <= '1' & not fout(19);
+  src_o.dat <= fout(15 downto 0);
+  src_o.adr <= fout(17 downto 16);
+  
+end rtl;
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.wr_fabric_pkg.all;
+
+entity wb_fabric_source is
+  
+  port (
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    -- Wishbone Fabric Interface I/O
+
+    src_dat_o   : out std_logic_vector(15 downto 0);
+    src_adr_o   : out std_logic_vector(1 downto 0);
+    src_sel_o   : out std_logic_vector(1 downto 0);
+    src_cyc_o   : out std_logic;
+    src_stb_o   : out std_logic;
+    src_we_o    : out std_logic;
+    src_stall_i : in  std_logic;
+    src_ack_i   : in  std_logic;
+    src_err_i   : in  std_logic;
+
+    -- Decoded & buffered fabric
+    addr_i    : in  std_logic_vector(1 downto 0);
+    data_i    : in  std_logic_vector(15 downto 0);
+    dvalid_i  : in  std_logic;
+    sof_i     : in  std_logic;
+    eof_i     : in  std_logic;
+    error_i   : in  std_logic;
+    bytesel_i : in  std_logic;
+    dreq_o    : out std_logic
+    );
+
+end wb_fabric_source;
+
+architecture wrapper of wb_fabric_source is
+  component xwb_fabric_source
+    port (
+      clk_i     : in  std_logic;
+      rst_n_i   : in  std_logic;
+      src_i     : in  t_wrf_source_in;
+      src_o     : out t_wrf_source_out;
+      addr_i    : in  std_logic_vector(1 downto 0);
+      data_i    : in  std_logic_vector(15 downto 0);
+      dvalid_i  : in  std_logic;
+      sof_i     : in  std_logic;
+      eof_i     : in  std_logic;
+      error_i   : in  std_logic;
+      bytesel_i : in  std_logic;
+      dreq_o    : out std_logic);
+  end component;
+
+  signal src_in  : t_wrf_source_in;
+  signal src_out : t_wrf_source_out;
+  
+begin  -- wrapper
+
+  
+  U_Wrapped_Source : xwb_fabric_source
+    port map (
+      clk_i     => clk_i,
+      rst_n_i   => rst_n_i,
+      src_i     => src_in,
+      src_o     => src_out,
+      addr_i    => addr_i,
+      data_i    => data_i,
+      dvalid_i  => dvalid_i,
+      sof_i     => sof_i,
+      eof_i     => eof_i,
+      error_i   => error_i,
+      bytesel_i => bytesel_i,
+      dreq_o    => dreq_o);
+
+  src_cyc_o <= src_out.cyc;
+  src_stb_o <= src_out.stb;
+  src_we_o  <= src_out.we;
+  src_sel_o <= src_out.sel;
+  src_adr_o <= src_out.adr;
+  src_dat_o <= src_out.dat;
+
+  src_in.rty   <= '0';
+  src_in.err   <= src_err_i;
+  src_in.ack   <= src_ack_i;
+  src_in.stall <= src_stall_i;
+
+  
+end wrapper;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwrf_mux.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwrf_mux.vhd
new file mode 100644
index 000000000..5ff1594e1
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/xwrf_mux.vhd
@@ -0,0 +1,307 @@
+-------------------------------------------------------------------------------
+-- Title      : Simple Pipelined Wishbone MUX/DEMUX for WRPC
+-- Project    : WhiteRabbit
+-------------------------------------------------------------------------------
+-- File       : xwrf_mux.vhd
+-- Author     : Grzegorz Daniluk
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-08-11
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- This is the simple multiplexer/demultiplexer for WR Fabric interface 
+-- (Pipelined Wishbone interface). It forwards ethernet frames between 
+-- WR endpoint, Mini-NIC and external Fabric interface in both directions. 
+-- In the direction 'from' WR endpoint it also decides whether the packet 
+-- has to be forwarded to Mini-NIC (if it is the PTP message) or to the 
+-- external interface (others).
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-08-11  1.0      greg.d          Created
+-- 2012-10-16  2.0      greg.d          generic number of ports
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_misc.all;
+
+use ieee.numeric_std.all;
+
+library work;
+use work.wr_fabric_pkg.all;
+use work.genram_pkg.all;
+
+entity xwrf_mux is
+  generic(
+    g_muxed_ports : integer := 2);
+  port(
+    clk_sys_i   : in  std_logic;
+    rst_n_i     : in  std_logic;
+    --ENDPOINT
+    ep_src_o    : out t_wrf_source_out;
+    ep_src_i    : in  t_wrf_source_in;
+    ep_snk_o    : out t_wrf_sink_out;
+    ep_snk_i    : in  t_wrf_sink_in;
+    --Muxed ports
+    mux_src_o   : out t_wrf_source_out_array(g_muxed_ports-1 downto 0);
+    mux_src_i   : in  t_wrf_source_in_array(g_muxed_ports-1 downto 0);
+    mux_snk_o   : out t_wrf_sink_out_array(g_muxed_ports-1 downto 0);
+    mux_snk_i   : in  t_wrf_sink_in_array(g_muxed_ports-1 downto 0);
+    --
+    mux_class_i : in  t_wrf_mux_class(g_muxed_ports-1 downto 0)
+    );
+end xwrf_mux;
+
+architecture behaviour of xwrf_mux is
+
+  function f_hot_to_bin(x : std_logic_vector(g_muxed_ports-1 downto 0))
+    return integer is
+    variable rv : integer;
+  begin
+    rv := 0;
+    -- if there are few ones set in _x_ then the least significant will be
+    -- translated to bin
+    for i in g_muxed_ports-1 downto 0 loop
+      if x(i) = '1' then
+        rv := i;
+      end if;
+    end loop;
+    return rv;
+  end function;
+
+  function f_match_class(port_mask, pkt_mask : std_logic_vector(7 downto 0)) return std_logic is
+    variable ret : std_logic;
+  begin
+    if((port_mask and pkt_mask) /= x"00") then
+      return '1';
+    else
+      return '0';
+    end if;
+  end function;
+
+  --==================================--
+  --  Masters to Endpoint mux signals --
+  --==================================--
+  type   t_mux is (MUX_SEL, MUX_TRANSFER);
+  signal mux        : t_mux;
+  signal mux_cycs   : std_logic_vector(g_muxed_ports-1 downto 0);
+  signal mux_rrobin : std_logic_vector(g_muxed_ports-1 downto 0);
+  signal mux_select : std_logic_vector(g_muxed_ports-1 downto 0);
+
+  --==================================--
+  -- Endpoint to Slaves demux signals --
+  --==================================--
+  type   t_demux is (DMUX_WAIT, DMUX_STATUS, DMUX_PAYLOAD);
+  signal demux            : t_demux;
+  signal dmux_sel         : std_logic_vector(g_muxed_ports-1 downto 0);
+  signal dmux_status_reg  : std_logic_vector(15 downto 0);
+  signal dmux_select      : std_logic_vector(g_muxed_ports-1 downto 0);
+  signal dmux_others      : std_logic_vector(g_muxed_ports-1 downto 0);
+  signal dmux_sel_zero    : std_logic;
+  signal dmux_snd_stat    : std_logic_vector(g_muxed_ports-1 downto 0);
+  signal ep_stall_mask    : std_logic;
+  signal ep_snk_out_stall : std_logic;
+
+begin
+
+  --=============================================--
+  --                                             --
+  --   Many Fabric Masters talking to ENDPOINT   --
+  --                                             --
+  --=============================================--
+  GEN_MUX_CYCS_REG : for I in 0 to g_muxed_ports-1 generate
+    mux_cycs(I) <= mux_snk_i(I).cyc;
+  end generate;
+
+  p_mux : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if (rst_n_i = '0') then
+        mux_rrobin(0)                        <= '1';
+        mux_rrobin(g_muxed_ports-1 downto 1) <= (others => '0');
+        mux                                  <= MUX_SEL;
+      else
+        case mux is
+          when MUX_SEL =>
+            if (unsigned(mux_cycs and mux_rrobin) /= 0)then
+              mux_select <= mux_cycs and mux_rrobin;
+              mux        <= MUX_TRANSFER;
+            else
+              mux_select <= (others => '0');
+              mux_rrobin <= mux_rrobin(0) & mux_rrobin(g_muxed_ports-1 downto 1);
+            end if;
+
+          when MUX_TRANSFER =>
+            if(unsigned(mux_cycs and mux_select) = 0) then  --cycle end
+              mux_rrobin <= mux_rrobin(0) & mux_rrobin(g_muxed_ports-1 downto 1);
+              mux        <= MUX_SEL;
+            end if;
+        end case;
+
+      end if;
+    end if;
+  end process;
+
+
+  GEN_MUX_CONNS : for J in 0 to g_muxed_ports-1 generate
+    mux_snk_o(J).ack <= ep_src_i.ack when(mux /= MUX_SEL and mux_select(J) = '1') else
+                        '0';
+    mux_snk_o(J).stall <= ep_src_i.stall when(mux /= MUX_SEL and mux_select(J) = '1') else
+                          '1';
+    mux_snk_o(J).err <= ep_src_i.err when(mux /= MUX_SEL and mux_select(J) = '1') else
+                        '0';
+    mux_snk_o(J).rty <= '0';
+  end generate;
+
+  ep_src_o.cyc <= mux_snk_i(f_hot_to_bin(mux_select)).cyc when(mux /= MUX_SEL) else
+                  '0';
+  ep_src_o.stb <= mux_snk_i(f_hot_to_bin(mux_select)).stb when(mux /= MUX_SEL) else
+                  '0';
+  ep_src_o.adr <= mux_snk_i(f_hot_to_bin(mux_select)).adr;
+  ep_src_o.dat <= mux_snk_i(f_hot_to_bin(mux_select)).dat;
+  ep_src_o.sel <= mux_snk_i(f_hot_to_bin(mux_select)).sel;
+  ep_src_o.we  <= '1';
+
+
+  --=============================================--
+  --                                             --
+  --    ENDPOINT talking to many Fabric Slaves   --
+  --                                             --
+  --=============================================--
+
+  CLASS_MATCH : for I in 0 to g_muxed_ports-1 generate
+    dmux_sel(I) <= f_match_class(mux_class_i(I), f_unmarshall_wrf_status(dmux_status_reg).match_class);
+  end generate;
+
+  DMUX_FSM : process(clk_sys_i)
+    variable sel : integer range 0 to g_muxed_ports-1;
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i = '0') then
+        dmux_select     <= (others => '0');
+        dmux_snd_stat   <= (others => '0');
+        dmux_status_reg <= (others => '0');
+        ep_stall_mask   <= '0';
+        demux           <= DMUX_WAIT;
+      else
+        case demux is
+                                        ---------------------------------------------------------------
+                                        --State DMUX_WAIT: Wait for the WRF cycle to start and then
+                                        --                 wait for the STATUS word
+                                        ---------------------------------------------------------------
+          when DMUX_WAIT =>
+            dmux_select     <= (others => '0');
+            dmux_snd_stat   <= (others => '0');
+            dmux_status_reg <= (others => '0');
+            ep_stall_mask   <= '0';
+            if(ep_snk_i.cyc = '1' and ep_snk_i.stb = '1' and ep_snk_i.adr = c_WRF_STATUS) then
+              ep_stall_mask   <= '1';
+              dmux_status_reg <= ep_snk_i.dat;
+              demux           <= DMUX_STATUS;
+            end if;
+
+                                        ---------------------------------------------------------------
+                                        --State DMUX_STATUS: Send Status word to appropriate interface
+                                        ---------------------------------------------------------------
+          when DMUX_STATUS =>
+            ep_stall_mask <= '1';
+
+            if(to_integer(unsigned(dmux_sel)) = 0) then  --class not matched to anything, pass pkt to last port
+              dmux_select(g_muxed_ports-1)   <= '1';
+              dmux_snd_stat(g_muxed_ports-1) <= '1';
+              sel                            := g_muxed_ports-1;
+            else
+              dmux_select   <= dmux_sel;
+              dmux_snd_stat <= dmux_sel;
+              sel           := f_hot_to_bin(dmux_sel);
+            end if;
+            if(mux_src_i(sel).stall = '0') then
+              demux <= DMUX_PAYLOAD;
+            end if;
+
+                                        ---------------------------------------------------------------
+                                        --State DMUX_PAYLOAD: Just wait here till the end of the
+                                        --                    current transfer
+                                        ---------------------------------------------------------------
+          when DMUX_PAYLOAD =>
+            dmux_snd_stat <= (others => '0');
+            ep_stall_mask <= '0';
+
+            if(ep_snk_i.cyc = '0') then
+              demux <= DMUX_WAIT;
+            end if;
+
+          when others =>
+            demux <= DMUX_WAIT;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  dmux_sel_zero <= '1' when(to_integer(unsigned(dmux_select)) = 0) else
+                   '0';
+
+  -- dmux_others signal says for given interface I if any other interface was
+  -- also matched to packet class
+  dmux_others(0) <= '0';
+  GEN_DMUX_OTHERS : for I in 1 to g_muxed_ports-1 generate
+    dmux_others(I) <= or_reduce(dmux_select(I-1 downto 0));
+  end generate;
+
+
+  GEN_DMUX_CONN : for I in 0 to g_muxed_ports-1 generate
+    mux_src_o(I).cyc <= ep_snk_i.cyc when(dmux_select(I) = '1' and dmux_others(I) = '0') else
+                        '0';
+    mux_src_o(I).stb <= '1' when(dmux_snd_stat(I) = '1' and dmux_others(I) = '0') else
+                        ep_snk_i.stb when(dmux_select(I) = '1' and dmux_others(I) = '0') else
+                        '0';
+    mux_src_o(I).adr <= c_WRF_STATUS when(dmux_snd_stat(I) = '1' and dmux_others(I) = '0') else
+                        ep_snk_i.adr when(dmux_select(I) = '1' and dmux_others(I) = '0') else
+                        (others => '0');
+    mux_src_o(I).dat <= dmux_status_reg when(dmux_snd_stat(I) = '1' and dmux_others(I) = '0') else
+                        ep_snk_i.dat when(dmux_select(I) = '1' and dmux_others(I) = '0') else
+                        (others => '0');
+    mux_src_o(I).sel <= (others => '1') when(dmux_snd_stat(I) = '1' and dmux_others(I) = '0') else
+                        ep_snk_i.sel when(dmux_select(I) = '1' and dmux_others(I) = '0') else
+                        (others => '1');
+    mux_src_o(I).we <= '1';
+  end generate;
+
+
+  ep_snk_o.ack <= ep_snk_i.cyc and ep_snk_i.stb and not ep_snk_out_stall when(dmux_sel_zero = '1') else
+                  mux_src_i(f_hot_to_bin(dmux_select)).ack;
+
+  ep_snk_o.err <= '0' when(dmux_sel_zero = '1') else
+                  mux_src_i(f_hot_to_bin(dmux_select)).err;
+
+  ep_snk_out_stall <= '1' when(ep_stall_mask = '1') else
+                      '0' when(dmux_sel_zero = '1') else
+                      mux_src_i(f_hot_to_bin(dmux_select)).stall;
+
+  ep_snk_o.stall <= ep_snk_out_stall;
+
+  ep_snk_o.rty <= '0';
+
+end behaviour;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/dmtd_phase_meas.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/dmtd_phase_meas.vhd
new file mode 100644
index 000000000..2cabc4426
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/dmtd_phase_meas.vhd
@@ -0,0 +1,290 @@
+-------------------------------------------------------------------------------
+-- Title      : Digital DMTD Phase Measurement Unit
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : dmtd_phase_meas.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-02-25
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description: Module measures phase shift between the two input clocks
+-- using a DDMTD phase detector. The raw measurement can be further averaged to
+-- increase the accuracy.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009 - 2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2010-02-25  1.0      twlostow        Created
+-- 2011-04-18  1.1      twlostow        Added comments and header
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.NUMERIC_STD.all;
+
+library work;
+use work.gencores_pkg.all;
+
+entity dmtd_phase_meas is
+  generic (
+-- DDMTD deglitcher threshold (in clk_dmtd_i) clock cycles
+    g_deglitcher_threshold: integer;
+-- Phase tag counter size (see dmtd_with_deglitcher.vhd for explanation)
+    g_counter_bits        : integer := 14);
+
+  port (
+-- resets
+    rst_sys_n_i  : in std_logic;
+    rst_dmtd_n_i : in std_logic;
+
+-- system clock 
+    clk_sys_i  : in std_logic;
+-- Input clocks
+    clk_a_i    : in std_logic;
+    clk_b_i    : in std_logic;
+    clk_dmtd_i : in std_logic;
+
+
+    en_i : in std_logic;
+
+    navg_i         : in  std_logic_vector(11 downto 0);
+    phase_meas_o   : out std_logic_vector(31 downto 0);
+    phase_meas_p_o : out std_logic
+    );
+
+end dmtd_phase_meas;
+
+architecture syn of dmtd_phase_meas is
+
+  component dmtd_with_deglitcher
+    generic (
+      g_counter_bits : natural);
+    port (
+      rst_n_dmtdclk_i      : in  std_logic;
+      rst_n_sysclk_i       : in  std_logic;
+      clk_in_i             : in  std_logic;
+      clk_dmtd_i           : in  std_logic;
+      clk_sys_i            : in  std_logic;
+      shift_en_i           : in  std_logic;
+      shift_dir_i          : in  std_logic;
+      deglitch_threshold_i : in  std_logic_vector(15 downto 0);
+      dbg_dmtdout_o        : out std_logic;
+      tag_o                : out std_logic_vector(g_counter_bits-1 downto 0);
+      tag_stb_p1_o         : out std_logic);
+  end component;
+
+  type t_pd_state is (PD_WAIT_TAG, PD_WAIT_A, PD_WAIT_B);
+
+  signal tag_a : std_logic_vector(g_counter_bits-1 downto 0);
+  signal tag_b : std_logic_vector(g_counter_bits-1 downto 0);
+
+  signal tag_a_p : std_logic;
+  signal tag_b_p : std_logic;
+
+  signal acc     : unsigned(31 downto 0);
+  signal avg_cnt : unsigned(11 downto 0);
+
+  signal phase_raw_p : std_logic;
+  signal phase_raw   : unsigned(g_counter_bits-1 downto 0);
+  signal pd_state    : t_pd_state;
+
+  signal phase_hi, phase_lo : std_logic;
+  signal ph_acq_valid       : std_logic;
+
+
+  signal stored_sign   : std_logic;
+  signal preserve_sign : std_logic;
+  
+begin  -- syn
+
+  DMTD_A : dmtd_with_deglitcher
+    generic map (
+      g_counter_bits => g_counter_bits)
+    port map (
+      rst_n_dmtdclk_i       => rst_dmtd_n_i,
+      rst_n_sysclk_i        => rst_sys_n_i,
+      clk_dmtd_i            => clk_dmtd_i,
+      clk_sys_i             => clk_sys_i,
+      clk_in_i              => clk_a_i,
+      tag_o                 => tag_a,
+      tag_stb_p1_o           => tag_a_p,
+      shift_en_i            => '0',
+      shift_dir_i           => '0',
+      deglitch_threshold_i => std_logic_vector(to_unsigned(g_deglitcher_threshold, 16)),
+      dbg_dmtdout_o         => open);
+
+  DMTD_B : dmtd_with_deglitcher
+    generic map (
+      g_counter_bits => g_counter_bits)
+    port map (
+      rst_n_dmtdclk_i       => rst_dmtd_n_i,
+      rst_n_sysclk_i        => rst_sys_n_i,
+      clk_dmtd_i            => clk_dmtd_i,
+      clk_sys_i             => clk_sys_i,
+      clk_in_i              => clk_b_i,
+      tag_o                 => tag_b,
+      tag_stb_p1_o           => tag_b_p,
+      shift_en_i            => '0',
+      shift_dir_i           => '0',
+      deglitch_threshold_i => std_logic_vector(to_unsigned(g_deglitcher_threshold, 16)),
+      dbg_dmtdout_o         => open);
+
+
+  collect_tags : process (clk_sys_i)
+  begin  -- process   
+    if rising_edge(clk_sys_i) then
+      if(rst_sys_n_i = '0' or en_i = '0') then
+        phase_raw    <= (others => '0');
+        phase_raw_p  <= '0';
+        ph_acq_valid <= '0';
+        pd_state     <= PD_WAIT_TAG;
+
+      else
+
+        case pd_state is
+          when PD_WAIT_TAG =>
+
+            if(tag_a_p = '1' and tag_b_p = '1') then
+              phase_raw   <= unsigned(tag_b) - unsigned(tag_a);
+              phase_raw_p <= '1';
+            elsif(tag_a_p = '1') then
+              phase_raw   <= unsigned(tag_a);
+              phase_raw_p <= '0';
+              pd_state    <= PD_WAIT_B;
+            elsif (tag_b_p = '1') then
+              phase_raw   <= (not unsigned(tag_b)) + 1;
+              phase_raw_p <= '0';
+              pd_state    <= PD_WAIT_A;
+            else
+              phase_raw_p <= '0';
+            end if;
+            
+          when PD_WAIT_A =>
+            if(tag_a_p = '1') then
+              phase_raw   <= phase_raw + unsigned(tag_a);
+              phase_raw_p <= '1';
+              pd_state    <= PD_WAIT_TAG;
+            end if;
+
+          when PD_WAIT_B =>
+            if(tag_b_p = '1') then
+              phase_raw   <= phase_raw - unsigned(tag_b);
+              phase_raw_p <= '1';
+              pd_state    <= PD_WAIT_TAG;
+            end if;
+
+            
+          when others => null;
+        end case;
+
+        --if(tag_a_p = '1' and tag_b_p = '1') then
+        --  phase_raw <= unsigned(tag_b) - unsigned(tag_a);
+        --  phase_raw_p <= '1';
+        --  ph_acq_valid <= '0';
+        --elsif(tag_a_p = '1' and tag_b_p = '0' and ph_acq_valid  ='1') then
+        --  phase_raw   <= phase_raw - unsigned(tag_a); 
+        --  phase_raw_p <= '1';
+        --  ph_acq_valid <= '0';
+        --elsif(tag_a_p = '0' and tag_b_p = '1') then
+        --  phase_raw_p <= '0';
+        --  phase_raw <= unsigned(tag_b);
+        --  ph_acq_valid <= '1';
+        --else
+        --  phase_raw_p <= '0';
+        --end if;
+
+
+      end if;
+    end if;
+  end process;
+
+
+  phase_hi <= '1' when phase_raw(phase_raw'high downto phase_raw'high-1) = "11" else '0';
+  phase_lo <= '1' when phase_raw(phase_raw'high downto phase_raw'high-1) = "00" else '0';
+
+
+  calc_error : process (clk_sys_i)
+  begin  -- process calc_error
+    if rising_edge(clk_sys_i) then
+      if(rst_sys_n_i = '0' or en_i = '0') then
+        acc            <= (others => '0');
+        avg_cnt        <= (others => '0');
+        phase_meas_p_o <= '0';
+        phase_meas_o   <= (others => '0');
+        stored_sign    <= '0';
+      else
+        
+
+        if(phase_raw_p = '1') then
+          if(avg_cnt = to_unsigned(0, avg_cnt'length)) then
+            acc <= resize(phase_raw, acc'length);
+
+            if(phase_lo = '1') then
+              preserve_sign <= '1';
+              stored_sign   <= '0';
+            elsif(phase_hi = '1') then
+              preserve_sign <= '1';
+              stored_sign   <= '1';
+            else
+              preserve_sign <= '0';
+            end if;
+
+            avg_cnt        <= avg_cnt + 1;
+            phase_meas_p_o <= '0';
+          elsif (avg_cnt = unsigned(navg_i)) then
+            avg_cnt        <= (others => '0');
+            phase_meas_o   <= std_logic_vector(acc);
+            phase_meas_p_o <= '1';
+          else
+            avg_cnt        <= avg_cnt + 1;
+            phase_meas_p_o <= '0';
+
+
+
+            if(preserve_sign = '1') then
+              if(phase_lo = '1' and stored_sign = '1') then
+                --       report "preserve_sign1";
+                acc <= acc + resize(phase_raw, acc'length) + to_unsigned(2**g_counter_bits, acc'length);
+              elsif (phase_hi = '1' and stored_sign = '0') then
+
+                --report "preserve_sign0";
+                acc <= acc + resize(phase_raw, acc'length) - to_unsigned(2**g_counter_bits, acc'length);
+              else
+                acc <= acc + resize(phase_raw, acc'length);
+              end if;
+            else
+              acc <= acc + resize(phase_raw, acc'length);
+            end if;
+          end if;
+        else
+          phase_meas_p_o <= '0';
+        end if;
+      end if;
+    end if;
+  end process calc_error;
+
+
+end syn;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/dmtd_with_deglitcher.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/dmtd_with_deglitcher.vhd
new file mode 100644
index 000000000..e1f4528db
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/dmtd_with_deglitcher.vhd
@@ -0,0 +1,353 @@
+-------------------------------------------------------------------------------
+-- Title      : Digital DMTD Edge Tagger
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : dmtd_with_deglitcher.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-02-25
+-- Last update: 2014-07-15
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description: Single-channel DDMTD phase tagger with integrated bit-median
+-- deglitcher. Contains a DDMTD detector, which output signal is deglitched and
+-- tagged with a counter running in DMTD offset clock domain. Phase tags are
+-- generated for each rising edge in DDMTD output with an internal counter
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009 - 2011 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2009-01-24  1.0      twlostow        Created
+-- 2011-18-04  1.1      twlostow        Bit-median type deglitcher, comments
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.NUMERIC_STD.all;
+
+library work;
+use work.gencores_pkg.all;
+
+entity dmtd_with_deglitcher is
+  generic (
+    -- Size of the phase tag counter. Must be big enough to cover at least one
+    -- full period of the DDMTD detector output. Given the frequencies of clk_in_i
+    -- and clk_dmtd_i are respectively f_in an f_dmtd, it can be calculated with
+    -- the following formula:
+    -- g_counter_bits = log2(f_in / abs(f_in - f_dmtd)) + 1
+    g_counter_bits : natural := 17;
+    g_chipscope    : boolean := false;
+
+    -- Divides the inputs by 2 (effectively passing the clock through a flip flop)
+    -- before it gets to the DMTD, effectively removing Place&Route warnings
+    -- (at the cost of detector bandwidth)
+    g_divide_input_by_2 : boolean := false;
+
+    -- reversed mode: samples clk_dmtd with clk_in.
+    g_reverse : boolean := false
+    );
+  port (
+    -- resets for different clock domains
+    rst_n_dmtdclk_i : in std_logic;
+    rst_n_sysclk_i  : in std_logic;
+
+    -- input clock
+    clk_in_i : in std_logic;
+
+    -- DMTD sampling clock
+    clk_dmtd_i : in std_logic;
+
+    -- system clock
+    clk_sys_i : in std_logic;
+
+    -- async counter resync input: resets only the DDMTD state machine and free
+    -- running counter, synchronized to clk_dmtd_i
+    resync_p_a_i : in std_logic := '0';
+
+    -- [clk_dmtd_i] counter resync output, pulses when free_cntr == 0
+    resync_p_o : out std_logic;
+
+    -- [clk_sys_i] starts resynchronization
+    resync_start_p_i : in std_logic := '0';
+
+    -- [clk_sys_i] 1: resynchonization done
+    resync_done_o : out std_logic;
+
+    -- [clk_dmtd_i] phase shifter enable, HI level shifts the internal counter
+    -- forward/backward by 1 clk_dmtd_i cycle, effectively shifting the tag
+    -- value by +-1.
+    shift_en_i : in std_logic := '0';
+
+    -- [clk_dmtd_i] phase shift direction: 1 - forward, 0 - backward
+    shift_dir_i : in std_logic := '0';
+
+    -- DMTD clock enable, active high. Can be used to reduce the DMTD sampling
+    -- frequency - for example, two 10 MHz signals cannot be sampled directly
+    -- with a 125 MHz clock, but it's possible with a 5 MHz reference, obtained
+    -- by asserting clk_dmtd_en_i every 25 clk_dmtd_i cycles.
+
+    clk_dmtd_en_i : in std_logic := '1';
+
+    -- [clk_dmtd_i] deglitcher threshold
+    deglitch_threshold_i : in std_logic_vector(15 downto 0);
+
+    -- [clk_dmtd_i] raw DDMTD output (for debugging purposes)
+    dbg_dmtdout_o : out std_logic;
+
+    -- [clk_sys_i] deglitched edge tag value
+    tag_o : out std_logic_vector(g_counter_bits-1 downto 0);
+
+    -- [clk_sys_i] pulse indicates new phase tag on tag_o
+    tag_stb_p1_o : out std_logic;
+    dbg_clk_d3_o : out std_logic
+    );
+
+end dmtd_with_deglitcher;
+
+architecture rtl of dmtd_with_deglitcher is
+
+  type t_state is (WAIT_STABLE_0, WAIT_EDGE, GOT_EDGE);
+
+  signal state : t_state;
+
+  signal stab_cntr : unsigned(15 downto 0);
+  signal free_cntr : unsigned(g_counter_bits-1 downto 0);
+
+  signal s_one        : std_logic;
+
+  signal clk_in                                           : std_logic;
+  signal clk_i_d0, clk_i_d1, clk_i_d2, clk_i_d3, clk_i_dx : std_logic;
+
+  attribute keep             : string;
+  attribute keep of clk_in   : signal is "true";
+  attribute keep of clk_i_d0 : signal is "true";
+  attribute keep of clk_i_d1 : signal is "true";
+  attribute keep of clk_i_d2 : signal is "true";
+  attribute keep of clk_i_d3 : signal is "true";
+
+  signal new_edge_sreg : std_logic_vector(5 downto 0);
+  signal new_edge_p    : std_logic;
+
+  signal tag_int       : unsigned(g_counter_bits-1 downto 0);
+  signal resync_p_dmtd : std_logic;
+
+  signal resync_start_p_dmtd, resync_done_dmtd, resync_p_int : std_logic;
+  
+begin  -- rtl
+
+  U_Sync_Resync_Pulse : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_dmtd_i,
+      rst_n_i  => rst_n_dmtdclk_i,
+      data_i   => resync_p_a_i,
+      synced_o => resync_p_dmtd);
+
+  U_Sync_Start_Pulse : gc_pulse_synchronizer
+    port map (
+      clk_in_i  => clk_sys_i,
+      clk_out_i => clk_dmtd_i,
+      rst_n_i   => rst_n_dmtdclk_i,
+      d_ready_o => open,
+      d_p_i     => resync_start_p_i,
+      q_p_o     => resync_start_p_dmtd);
+
+  U_Sync_Resync_Done : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_sysclk_i,
+      data_i   => resync_done_dmtd,
+      synced_o => resync_done_o);
+
+
+  gen_straight : if(g_reverse = false) generate
+    
+    gen_input_div2 : if(g_divide_input_by_2 = true) generate
+      p_divide_input_clock : process(clk_in_i, rst_n_sysclk_i)
+      begin
+        if rst_n_sysclk_i = '0' then
+          clk_in <= '0';
+        elsif rising_edge(clk_in_i) then
+          clk_in <= not clk_in;
+        end if;
+      end process;
+    end generate gen_input_div2;
+
+    gen_input_straight : if(g_divide_input_by_2 = false) generate
+      clk_in <= clk_in_i;
+    end generate gen_input_straight;
+
+    p_the_dmtd_itself : process(clk_dmtd_i)
+    begin
+      if rising_edge(clk_dmtd_i) then
+        clk_i_d0 <= clk_in;
+        clk_i_d1 <= clk_i_d0;
+        clk_i_d2 <= clk_i_d1;
+        clk_i_d3 <= clk_i_d2;
+      end if;
+    end process;
+
+  end generate gen_straight;
+
+  gen_reverse : if(g_reverse = true) generate
+
+    assert (not g_divide_input_by_2) report "dmtd_with_deglitcher: g_reverse implies g_divide_input_by_2 == false" severity failure;
+
+    clk_in <= clk_in_i;
+
+    p_the_dmtd_itself : process(clk_in)
+    begin
+      if rising_edge(clk_in) then
+        clk_i_d0 <= clk_dmtd_i;
+        clk_i_d1 <= clk_i_d0;
+      end if;
+    end process;
+
+    p_sync : process(clk_dmtd_i)
+    begin
+      if rising_edge(clk_dmtd_i) then
+        clk_i_dx <= clk_i_d1;
+        clk_i_d2 <= not clk_i_dx;
+        clk_i_d3 <= clk_i_d2;
+      end if;
+    end process;
+
+  end generate gen_reverse;
+
+-- glitchproof DMTD output edge detection
+  p_deglitch : process (clk_dmtd_i)
+  begin  -- process deglitch
+
+    if rising_edge(clk_dmtd_i) then     -- rising clock edge
+
+      if (rst_n_dmtdclk_i = '0' or (resync_p_dmtd = '1' and resync_done_dmtd = '0')) then  -- synchronous reset (active low)
+        stab_cntr     <= (others => '0');
+        state         <= WAIT_STABLE_0;
+        free_cntr     <= (others => '0');
+        new_edge_sreg <= (others => '0');
+      elsif(clk_dmtd_en_i = '1') then
+        
+        if (shift_en_i = '0') then      -- phase shifter
+          free_cntr <= free_cntr + 1;
+        elsif (shift_dir_i = '1') then
+          free_cntr <= free_cntr + 2;
+        end if;
+
+        case state is
+          when WAIT_STABLE_0 =>         -- out-of-sync
+            new_edge_sreg <= '0' & new_edge_sreg(new_edge_sreg'length-1 downto 1);
+
+            if clk_i_d3 /= '0' then
+              stab_cntr <= (others => '0');
+            else
+              stab_cntr <= stab_cntr + 1;
+            end if;
+
+            -- DMTD output stable counter hit the LOW level threshold?
+            if stab_cntr = unsigned(deglitch_threshold_i) then
+              state <= WAIT_EDGE;
+            end if;
+
+          when WAIT_EDGE =>
+            if (clk_i_d3 /= '0') then   -- got a glitch?
+              state     <= GOT_EDGE;
+              tag_int   <= free_cntr;
+              stab_cntr <= (others => '0');
+            end if;
+
+          when GOT_EDGE =>
+            if (clk_i_d3 = '0') then
+              tag_int <= tag_int + 1;
+            end if;
+
+            if stab_cntr = unsigned(deglitch_threshold_i) then
+              state         <= WAIT_STABLE_0;
+              tag_o         <= std_logic_vector(tag_int);
+              new_edge_sreg <= (others => '1');
+              stab_cntr     <= (others => '0');
+            elsif (clk_i_d3 = '0') then
+              stab_cntr <= (others => '0');
+            else
+              stab_cntr <= stab_cntr + 1;
+            end if;
+
+            
+        end case;
+      end if;
+    end if;
+  end process p_deglitch;
+
+  p_resync_pulse_output : process(clk_dmtd_i)
+  begin
+    if rising_edge(clk_dmtd_i) then
+      if(unsigned(free_cntr(free_cntr'length-1 downto 3)) = 0) then
+        resync_p_o <= '1';
+      else
+        resync_p_o <= '0';
+      end if;
+    end if;
+  end process;
+
+  p_resync_pulse_trigger : process(clk_dmtd_i)
+  begin
+    if rising_edge(clk_dmtd_i) then
+      if rst_n_dmtdclk_i = '0' then
+        resync_done_dmtd <= '1';
+      else
+        if(resync_start_p_dmtd = '1') then
+          resync_done_dmtd <= '0';
+        elsif(resync_p_dmtd = '1') then
+          resync_done_dmtd <= '1';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  U_sync_tag_strobe : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_sysclk_i,
+      data_i   => new_edge_sreg(0),
+      synced_o => open,
+      npulse_o => open,
+      ppulse_o => new_edge_p);
+
+  tag_stb_p1_o <= new_edge_p;
+
+  U_Extend_Debug_Pulses : gc_extend_pulse
+    generic map (
+      g_width => 3000)
+    port map (
+      clk_i      => clk_sys_i,
+      rst_n_i    => rst_n_sysclk_i,
+      pulse_i    => new_edge_p,
+      extended_o => dbg_dmtdout_o);
+
+	dbg_clk_d3_o <= clk_i_d3;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/pulse_stamper.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/pulse_stamper.vhd
new file mode 100644
index 000000000..fb55da00c
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/pulse_stamper.vhd
@@ -0,0 +1,161 @@
+-------------------------------------------------------------------------------
+-- Entity: pulse_stamper
+-- File: pulse_stamper.vhd
+-- Description: a time-tagger which associates a time-tag with an asyncrhonous
+-- input pulse.
+-- Author: Javier Serrano (Javier.Serrano@cern.ch)
+-- Date: 24 January 2012
+-- Version: 0.01
+-- Todo: Factor out syncrhonizer in a separate reusable block.
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--               GNU LESSER GENERAL PUBLIC LICENSE                             
+--              -----------------------------------                            
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version.                           
+-- This source is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
+-- for more details. You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it from
+-- http://www.gnu.org/licenses/lgpl-2.1.html                  
+-------------------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity pulse_stamper is
+  
+  generic (
+    -- reference clock frequency
+    g_ref_clk_rate : integer := 125000000);
+
+  port(
+    clk_ref_i : in std_logic;           -- timing reference clock
+    clk_sys_i : in std_logic;           -- data output reference clock
+    rst_n_i   : in std_logic;           -- system reset
+
+    pulse_a_i : in std_logic;           -- pulses to be stamped
+
+    -------------------------------------------------------------------------------
+    -- Timing input (from WRPC), clk_ref_i domain
+    ------------------------------------------------------------------------------
+
+    -- 1: time given on tm_utc_i and tm_cycles_i is valid (otherwise, don't timestamp)
+    tm_time_valid_i : in std_logic;
+    -- number of seconds
+    tm_tai_i        : in std_logic_vector(39 downto 0);
+    -- number of clk_ref_i cycles
+    tm_cycles_i     : in std_logic_vector(27 downto 0);
+
+
+    ---------------------------------------------------------------------------
+    -- Time tag output (clk_sys_i domain)
+    ---------------------------------------------------------------------------
+    tag_tai_o      : out std_logic_vector(39 downto 0);
+    tag_cycles_o   : out std_logic_vector(27 downto 0);
+    -- single-cycle pulse: strobe tag on tag_utc_o and tag_cycles_o
+    tag_valid_o : out std_logic
+    );
+
+  
+end pulse_stamper;
+
+architecture rtl of pulse_stamper is
+
+ -- Signals for input anti-metastability ffs
+ signal pulse_ref : std_logic_vector(2 downto 0);
+ signal pulse_ref_p1 : std_logic;
+ signal pulse_ref_p1_d1 : std_logic;
+ 
+ -- Time tagger signals
+ signal tag_utc_ref : std_logic_vector(39 downto 0);
+ signal tag_cycles_ref : std_logic_vector(27 downto 0);
+
+ -- Signals for synchronizer
+ signal rst_from_sync : std_logic;
+ signal pulse_ref_d2 : std_logic;
+ signal pulse_sys : std_logic_vector(2 downto 0);
+ signal pulse_sys_p1 : std_logic;
+ signal pulse_back : std_logic_vector(2 downto 0);
+ 
+begin  -- architecture rtl
+
+ -- Synchronization of external pulse into the clk_ref_i clock domain
+ sync_ext_pulse: process (clk_ref_i)
+ begin
+  if clk_ref_i'event and clk_ref_i='1' then
+    pulse_ref <= pulse_ref(1 downto 0) & pulse_a_i;
+    pulse_ref_p1 <= pulse_ref(1) and not pulse_ref(2);
+    pulse_ref_p1_d1 <= pulse_ref_p1 and tm_time_valid_i;
+  end if;
+ end process sync_ext_pulse;
+
+ -- Time tagging of the pulse, still in the clk_ref_i domain
+ tagger: process (clk_ref_i)
+ begin
+  if clk_ref_i'event and clk_ref_i='1' then
+    if pulse_ref_p1='1' and tm_time_valid_i='1' then
+      tag_utc_ref <= tm_tai_i;
+      tag_cycles_ref <= tm_cycles_i;
+    end if;
+  end if;
+ end process tagger;
+
+ -- Synchronizer to pass UTC register data to the system clock domain
+ -- This synchronizer is made with the following three processes
+
+ -- First one FF with async reset, still in the clk_ref_i domain
+ sync_first_ff: process (clk_ref_i, rst_n_i, rst_from_sync)
+ begin
+  if rst_n_i='0' or rst_from_sync='1' then
+    pulse_ref_d2 <= '0';
+  elsif clk_ref_i'event and clk_ref_i='1' then
+    if pulse_ref_p1_d1='1' then
+      pulse_ref_d2 <= '1';
+    end if;
+  end if;
+ end process sync_first_ff;
+
+ -- Then three FFs to take the strobe safely into the clk_sys_i domain
+ sync_sys: process (clk_sys_i)
+ begin
+  if clk_sys_i'event and clk_sys_i='1' then
+   pulse_sys <= pulse_sys(1 downto 0) & pulse_ref_d2;
+   pulse_sys_p1 <= pulse_sys(1) and not pulse_sys(2);
+  end if;
+ end process sync_sys;
+
+ -- And then back into the clk_ref_i domain
+ sync_ref: process (clk_ref_i)
+ begin
+  if clk_ref_i'event and clk_ref_i='1' then
+    pulse_back <= pulse_back(1 downto 0) & pulse_sys(2);
+    rst_from_sync <= pulse_back(2);
+  end if;
+ end process sync_ref;
+
+ -- Now we can take the time tags into the clk_sys_i domain
+ sys_tags: process (clk_sys_i)
+ begin
+  if clk_sys_i'event and clk_sys_i='1' then
+    if rst_n_i='0' then
+     tag_tai_o <= (others=>'0');
+     tag_cycles_o <= (others=>'0');
+     tag_valid_o <= '0';
+    elsif pulse_sys_p1='1' then
+     tag_tai_o <= tag_utc_ref;
+     tag_cycles_o <= tag_cycles_ref;
+     tag_valid_o <= '1';
+    else
+     tag_valid_o <='0';
+    end if;
+  end if;
+ end process sys_tags;
+ 
+end architecture rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_dacs/spec_serial_dac.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_dacs/spec_serial_dac.vhd
new file mode 100644
index 000000000..c28410f68
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_dacs/spec_serial_dac.vhd
@@ -0,0 +1,209 @@
+-------------------------------------------------------------------------------
+-- Title      : Serial DAC interface
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : spec_serial_dac.vhd
+-- Author     : paas, slayer
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-02-25
+-- Last update: 2011-05-10
+-- Platform   : fpga-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: The dac unit provides an interface to a 16 bit serial Digital
+-- to Analogue converter (max5441, SPI?/QSPI?/MICROWIRE? compatible) 
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :1
+-- Date        Version  Author  Description
+-- 2009-01-24  1.0      paas    Created
+-- 2010-02-25  1.1      slayer  Modified for rev 1.1 switch
+-------------------------------------------------------------------------------
+
+
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+entity spec_serial_dac is
+
+  generic (
+    g_num_data_bits  : integer := 16;
+    g_num_extra_bits : integer := 8;
+    g_num_cs_select  : integer := 2
+    );
+
+  port (
+-- clock & reset
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+-- channel 1 value and value load strobe
+    value_i  : in std_logic_vector(g_num_data_bits-1 downto 0);
+    cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0);
+    load_i   : in std_logic;
+
+-- SCLK divider: 000 = clk_i/8 ... 111 = clk_i/1024
+    sclk_divsel_i : in std_logic_vector(2 downto 0);
+
+-- DAC I/F
+    dac_cs_n_o  : out std_logic_vector(g_num_cs_select-1 downto 0);
+    dac_sclk_o  : out std_logic;
+    dac_sdata_o : out std_logic;
+
+    xdone_o : out std_logic
+    );
+end spec_serial_dac;
+
+
+architecture syn of spec_serial_dac is
+
+  signal divider        : unsigned(11 downto 0);
+  signal dataSh         : std_logic_vector(g_num_data_bits + g_num_extra_bits-1 downto 0);
+  signal bitCounter     : std_logic_vector(g_num_data_bits + g_num_extra_bits+1 downto 0);
+  signal endSendingData : std_logic;
+  signal sendingData    : std_logic;
+  signal iDacClk        : std_logic;
+  signal iValidValue    : std_logic;
+
+  signal divider_muxed : std_logic;
+
+  signal cs_sel_reg : std_logic_vector(g_num_cs_select-1 downto 0);
+  
+begin
+
+  select_divider : process (divider, sclk_divsel_i)
+  begin  -- process
+    case sclk_divsel_i is
+      when "000"  => divider_muxed <= divider(1);  -- sclk = clk_i/8
+      when "001"  => divider_muxed <= divider(2);  -- sclk = clk_i/16
+      when "010"  => divider_muxed <= divider(3);  -- sclk = clk_i/32
+      when "011"  => divider_muxed <= divider(4);  -- sclk = clk_i/64
+      when "100"  => divider_muxed <= divider(5);  -- sclk = clk_i/128
+      when "101"  => divider_muxed <= divider(6);  -- sclk = clk_i/256
+      when "110"  => divider_muxed <= divider(7);  -- sclk = clk_i/512
+      when "111"  => divider_muxed <= divider(8);  -- sclk = clk_i/1024
+      when others => null;
+    end case;
+  end process;
+
+
+  iValidValue <= load_i;
+
+  process(clk_i, rst_n_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        sendingData <= '0';
+      else
+        if iValidValue = '1' and sendingData = '0' then
+          sendingData <= '1';
+        elsif endSendingData = '1' then
+          sendingData <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if iValidValue = '1' then
+        divider <= (others => '0');
+      elsif sendingData = '1' then
+        if(divider_muxed = '1') then
+          divider <= (others => '0');
+        else
+          divider <= divider + 1;
+        end if;
+      elsif endSendingData = '1' then
+        divider <= (others => '0');
+      end if;
+    end if;
+  end process;
+
+
+  process(clk_i, rst_n_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        iDacClk <= '1';                 -- 0
+      else
+        if iValidValue = '1' then
+          iDacClk <= '1';               -- 0
+        elsif divider_muxed = '1' then
+          iDacClk <= not(iDacClk);
+        elsif endSendingData = '1' then
+          iDacClk <= '1';               -- 0
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process(clk_i, rst_n_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        dataSh <= (others => '0');
+      else
+        if iValidValue = '1' and sendingData = '0' then
+          cs_sel_reg <= cs_sel_i;
+          dataSh(g_num_data_bits-1 downto 0)     <= value_i;
+          dataSh(dataSh'left downto g_num_data_bits) <= (others => '0');
+        elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then
+          dataSh(0)                    <= dataSh(dataSh'left);
+          dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if iValidValue = '1' and sendingData = '0' then
+        bitCounter(0)                        <= '1';
+        bitCounter(bitCounter'left downto 1) <= (others => '0');
+      elsif sendingData = '1' and to_integer(divider) = 0 and iDacClk = '1' then
+        bitCounter(0)                        <= '0';
+        bitCounter(bitCounter'left downto 1) <= bitCounter(bitCounter'left - 1 downto 0);
+      end if;
+    end if;
+  end process;
+
+  endSendingData <= bitCounter(bitCounter'left);
+
+  xdone_o <= not SendingData;
+
+  dac_sdata_o <= dataSh(dataSh'left);
+
+  gen_cs_out : for i in 0 to g_num_cs_select-1 generate
+    dac_cs_n_o(i) <= not(sendingData) or (not cs_sel_reg(i));
+  end generate gen_cs_out;
+
+  dac_sclk_o <= iDacClk;
+
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_dacs/spec_serial_dac_arb.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_dacs/spec_serial_dac_arb.vhd
new file mode 100644
index 000000000..511bb27b7
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_dacs/spec_serial_dac_arb.vhd
@@ -0,0 +1,187 @@
+-------------------------------------------------------------------------------
+-- Title      : SPEC serial DAC interface with arbiter
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : spec_serial_dac.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Platform   : fpga-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity spec_serial_dac_arb is
+  generic(
+    g_invert_sclk    : boolean;
+    g_num_extra_bits : integer
+    );
+  port(
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    val1_i  : in std_logic_vector(15 downto 0);
+    load1_i : in std_logic;
+    val2_i  : in std_logic_vector(15 downto 0);
+    load2_i : in std_logic;
+
+    dac_cs_n_o  : out std_logic_vector(1 downto 0);
+    dac_clr_n_o : out std_logic;
+    dac_sclk_o  : out std_logic;
+    dac_din_o   : out std_logic);
+
+end spec_serial_dac_arb;
+
+architecture behavioral of spec_serial_dac_arb is
+
+  component spec_serial_dac
+    generic (
+      g_num_data_bits  : integer;
+      g_num_extra_bits : integer;
+      g_num_cs_select  : integer);
+    port (
+      clk_i         : in  std_logic;
+      rst_n_i       : in  std_logic;
+      value_i       : in  std_logic_vector(g_num_data_bits-1 downto 0);
+      cs_sel_i      : in  std_logic_vector(g_num_cs_select-1 downto 0);
+      load_i        : in  std_logic;
+      sclk_divsel_i : in  std_logic_vector(2 downto 0);
+      dac_cs_n_o    : out std_logic_vector(g_num_cs_select-1 downto 0);
+      dac_sclk_o    : out std_logic;
+      dac_sdata_o   : out std_logic;
+      xdone_o       : out std_logic);
+  end component;
+
+  signal d1, d2             : std_logic_vector(15 downto 0);
+  signal d1_ready, d2_ready : std_logic;
+
+
+  signal dac_data     : std_logic_vector(15 downto 0);
+  signal dac_load     : std_logic;
+  signal dac_cs_sel   : std_logic_vector(1 downto 0);
+  signal dac_done     : std_logic;
+  signal dac_sclk_int : std_logic;
+
+  type t_state is (WAIT_DONE, LOAD_DAC, WAIT_DATA);
+
+  signal state : t_state;
+
+  signal trig0    : std_logic_vector(31 downto 0);
+  signal trig1    : std_logic_vector(31 downto 0);
+  signal trig2    : std_logic_vector(31 downto 0);
+  signal trig3    : std_logic_vector(31 downto 0);
+  signal CONTROL0 : std_logic_vector(35 downto 0);
+
+begin  -- behavioral
+
+  dac_clr_n_o <= '1';
+
+  U_DAC : spec_serial_dac
+    generic map (
+      g_num_data_bits  => 16,
+      g_num_extra_bits => g_num_extra_bits,
+      g_num_cs_select  => 2)
+    port map (
+      clk_i         => clk_i,
+      rst_n_i       => rst_n_i,
+      value_i       => dac_data,
+      cs_sel_i      => dac_cs_sel,
+      load_i        => dac_load,
+      sclk_divsel_i => "001",
+      dac_cs_n_o    => dac_cs_n_o,
+      dac_sclk_o    => dac_sclk_int,
+      dac_sdata_o   => dac_din_o,
+      xdone_o       => dac_done);
+
+
+  p_drive_sclk: process(dac_sclk_int)
+    begin
+      if(g_invert_sclk) then
+        dac_sclk_o <= not dac_sclk_int;
+       else
+        dac_sclk_o <= dac_sclk_int;
+       end if;
+      end process;
+
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        d1         <= (others => '0');
+        d1_ready   <= '0';
+        d2         <= (others => '0');
+        d2_ready   <= '0';
+        dac_load   <= '0';
+        dac_cs_sel <= (others => '0');
+        state      <= WAIT_DATA;
+      else
+
+        if(load1_i = '1' or load2_i = '1') then
+          
+          if(load1_i = '1') then
+            d1_ready <= '1';
+            d1       <= val1_i;
+          end if;
+
+          if(load2_i = '1') then
+            d2_ready <= '1';
+            d2       <= val2_i;
+          end if;
+        else
+          case state is
+            when WAIT_DATA =>
+              if(d1_ready = '1') then
+                dac_cs_sel <= "01";
+                dac_data   <= d1;
+                dac_load   <= '1';
+                d1_ready   <= '0';
+                state      <= LOAD_DAC;
+              elsif(d2_ready = '1') then
+                dac_cs_sel <= "10";
+                dac_data   <= d2;
+                dac_load   <= '1';
+                d2_ready   <= '0';
+                state      <= LOAD_DAC;
+              end if;
+
+            when LOAD_DAC=>
+              dac_load <= '0';
+              state    <= WAIT_DONE;
+
+            when WAIT_DONE =>
+              if(dac_done = '1') then
+                state <= WAIT_DATA;
+              end if;
+            when others => null;
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+
+  
+  
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/endpoint_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/endpoint_pkg.vhd
new file mode 100644
index 000000000..5d1a794ad
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/endpoint_pkg.vhd
@@ -0,0 +1,469 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000base-X MAC/Endpoint
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : endpoint_pkg.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-04-26
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description: Public package for the WR Endpoint. Contains public data
+-- structures and component declarations.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011-2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+
+package endpoint_pkg is
+
+  function f_pcs_data_width(pcs_16 : boolean) return integer;
+  function f_pcs_k_width(pcs_16 : boolean) return integer;
+  function f_pcs_bts_width(pcs_16 : boolean) return integer;
+  function f_pcs_clock_rate(pcs_16 : boolean) return integer;
+
+  type t_txtsu_timestamp is record
+    stb       : std_logic;
+    tsval     : std_logic_vector(31 downto 0);
+    port_id   : std_logic_vector(5 downto 0);
+    frame_id  : std_logic_vector(15 downto 0);
+    incorrect : std_logic;
+  end record;
+
+  type t_txtsu_timestamp_array is array(integer range <>) of t_txtsu_timestamp;
+
+  -- Endpoint's internal fabric used to connect the submodules with each other.
+  -- Easier to handle than pipelined Wishbone.
+  type t_ep_internal_fabric is record
+    sof                : std_logic;
+    eof                : std_logic;
+    error              : std_logic;
+    dvalid             : std_logic;
+    bytesel            : std_logic;
+    has_rx_timestamp   : std_logic;
+    rx_timestamp_valid : std_logic;
+    data               : std_logic_vector(15 downto 0);
+    addr               : std_logic_vector(1 downto 0);
+  end record;
+  type t_fab_pipe is array(integer range <>) of t_ep_internal_fabric;
+
+  -----------------------------
+  -- Phy i/f types
+  -----------------------------
+  -- 8-bit Serdes
+  type t_phy_8bits_to_wrc is record
+    ref_clk        : std_logic;
+    tx_disparity   : std_logic;
+    tx_enc_err     : std_logic;
+    rx_data        : std_logic_vector(7 downto 0);
+    rx_clk         : std_logic;
+    rx_k           : std_logic_vector(0 downto 0);
+    rx_enc_err     : std_logic;
+    rx_bitslide    : std_logic_vector(3 downto 0);
+    rdy            : std_logic;
+    sfp_tx_fault   : std_logic;
+    sfp_los        : std_logic;
+  end record;
+  type t_phy_8bits_from_wrc is record
+    rst            : std_logic;
+    loopen         : std_logic;
+    tx_data        : std_logic_vector(7 downto 0);
+    tx_k           : std_logic_vector(0 downto 0);
+    loopen_vec     : std_logic_vector(2 downto 0);
+    tx_prbs_sel    : std_logic_vector(2 downto 0);
+    sfp_tx_disable : std_logic;
+  end record;
+
+  constant c_dummy_phy8_to_wrc : t_phy_8bits_to_wrc :=
+    ('0', '0', '0', (others=>'0'), '0', (others=>'0'), '0',
+    (others=>'0'), '0', '0', '0');
+  constant c_dummy_phy8_from_wrc : t_phy_8bits_from_wrc :=
+    ('0', '0', (others=>'0'), (others=>'0'), (others=>'0'),
+    (others=>'0'), '0');
+
+  -- 16-bit Serdes
+  type t_phy_16bits_to_wrc is record
+    ref_clk        : std_logic;
+    tx_disparity   : std_logic;
+    tx_enc_err     : std_logic;
+    rx_data        : std_logic_vector(15 downto 0);
+    rx_clk         : std_logic;
+    rx_k           : std_logic_vector(1 downto 0);
+    rx_enc_err     : std_logic;
+    rx_bitslide    : std_logic_vector(4 downto 0);
+    rdy            : std_logic;
+    sfp_tx_fault   : std_logic;
+    sfp_los        : std_logic;
+  end record;
+  type t_phy_16bits_from_wrc is record
+    rst            : std_logic;
+    loopen         : std_logic;
+    tx_data        : std_logic_vector(15 downto 0);
+    tx_k           : std_logic_vector(1 downto 0);
+    loopen_vec     : std_logic_vector(2 downto 0);
+    tx_prbs_sel    : std_logic_vector(2 downto 0);
+    sfp_tx_disable : std_logic;
+  end record;
+
+  constant c_dummy_phy16_to_wrc : t_phy_16bits_to_wrc :=
+    ('0', '0', '0', (others=>'0'), '0', (others=>'0'), '0',
+    (others=>'0'), '0', '0', '0');
+  constant c_dummy_phy16_from_wrc : t_phy_16bits_from_wrc :=
+    ('0', '0', (others=>'0'), (others=>'0'), (others=>'0'),
+    (others=>'0'), '0');
+
+
+  -- debug CS types
+  type t_dbg_ep_rxpcs is record
+    fsm : std_logic_vector(2 downto 0);
+  end record;
+
+  type t_dbg_ep_pcs is record
+    rx : t_dbg_ep_rxpcs;
+  end record;
+
+  type t_dbg_ep_rxpath is record
+    fab_pipe  : t_fab_pipe(9 downto 0);
+    dreq_pipe : std_logic_vector(9 downto 0);
+    pcs_fifo_afull : std_logic;
+    pcs_fifo_empty : std_logic;
+    pcs_fifo_full  : std_logic;
+    rxbuf_full     : std_logic;
+  end record;
+
+  type t_dbg_ep is record
+    pcs    : t_dbg_ep_pcs;
+    rxpath : t_dbg_ep_rxpath;
+  end record;
+  ------------------------------------
+
+  constant c_epevents_sz  : integer := 29;  --how many events the endpoint generates
+
+  component xwr_endpoint
+    generic (
+      g_interface_mode        : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity   : t_wishbone_address_granularity := WORD;
+      g_simulation            : boolean                        := false;
+      g_pcs_16bit             : boolean                        := false;
+      g_records_for_phy       : boolean                        := false;
+      g_tx_force_gap_length   : integer                        := 0;
+      g_tx_runt_padding       : boolean                        := false;
+      g_rx_buffer_size        : integer                        := 1024;
+      g_with_rx_buffer        : boolean                        := true;
+      g_with_flow_control     : boolean                        := true;
+      g_with_timestamper      : boolean                        := true;
+      g_with_dpi_classifier   : boolean                        := false;
+      g_with_vlans            : boolean                        := false;
+      g_with_rtu              : boolean                        := false;
+      g_with_leds             : boolean                        := false;
+      g_with_dmtd             : boolean                        := false;
+      g_with_packet_injection : boolean                        := false;
+      g_use_new_rxcrc         :	boolean                        := false;
+      g_use_new_txcrc         :	boolean                        := false;
+      g_with_stop_traffic     : boolean                        := false);
+    port (
+      clk_ref_i            : in  std_logic;
+      clk_sys_i            : in  std_logic;
+      clk_dmtd_i           : in  std_logic                     := '0';
+      rst_sys_n_i          : in  std_logic;
+      rst_ref_n_i          : in  std_logic;
+      rst_dmtd_n_i         : in  std_logic;
+      rst_txclk_n_i        : in  std_logic;
+      rst_rxclk_n_i        : in  std_logic;
+      pps_csync_p1_i       : in  std_logic                     := '0';
+      pps_valid_i          : in  std_logic                     := '1';
+      phy_rst_o            : out std_logic;
+      phy_loopen_o         : out std_logic;
+      phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+      phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+      phy_sfp_tx_fault_i   : in  std_logic                     := '0';
+      phy_sfp_los_i        : in  std_logic                     := '0';
+      phy_sfp_tx_disable_o : out std_logic;
+      phy_rdy_i            : in  std_logic;
+      phy_ref_clk_i        : in  std_logic                     := '0';
+      phy_tx_data_o        : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+      phy_tx_k_o           : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+      phy_tx_disparity_i   : in  std_logic                     := '0';
+      phy_tx_enc_err_i     : in  std_logic                     := '0';
+      phy_rx_data_i        : in  std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy_rx_clk_i         : in  std_logic                     := '0';
+      phy_rx_k_i           : in  std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy_rx_enc_err_i     : in  std_logic                     := '0';
+      phy_rx_bitslide_i    : in  std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy8_o               : out t_phy_8bits_from_wrc;
+      phy8_i               : in  t_phy_8bits_to_wrc  := c_dummy_phy8_to_wrc;
+      phy16_o              : out t_phy_16bits_from_wrc;
+      phy16_i              : in  t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
+      gmii_tx_clk_i        : in  std_logic                     := '0';
+      gmii_txd_o           : out std_logic_vector(7 downto 0);
+      gmii_tx_en_o         : out std_logic;
+      gmii_tx_er_o         : out std_logic;
+      gmii_rx_clk_i        : in  std_logic                     := '0';
+      gmii_rxd_i           : in  std_logic_vector(7 downto 0)  := x"00";
+      gmii_rx_er_i         : in  std_logic                     := '0';
+      gmii_rx_dv_i         : in  std_logic                     := '0';
+      src_o                : out t_wrf_source_out;
+      src_i                : in  t_wrf_source_in;
+      snk_o                : out t_wrf_sink_out;
+      snk_i                : in  t_wrf_sink_in;
+      txtsu_port_id_o      : out std_logic_vector(4 downto 0);
+      txtsu_frame_id_o     : out std_logic_vector(16 -1 downto 0);
+      txtsu_ts_value_o     : out std_logic_vector(28 + 4 - 1 downto 0);
+      txtsu_ts_incorrect_o : out std_logic;
+      txtsu_stb_o          : out std_logic;
+      txtsu_ack_i          : in  std_logic                     := '1';
+      rtu_full_i           : in  std_logic                     := '0';
+      rtu_almost_full_i    : in  std_logic                     := '0';
+      rtu_rq_strobe_p1_o   : out std_logic;
+      rtu_rq_abort_o       : out std_logic;
+      rtu_rq_smac_o        : out std_logic_vector(48 - 1 downto 0);
+      rtu_rq_dmac_o        : out std_logic_vector(48 - 1 downto 0);
+      rtu_rq_vid_o         : out std_logic_vector(12 - 1 downto 0);
+      rtu_rq_has_vid_o     : out std_logic;
+      rtu_rq_prio_o        : out std_logic_vector(3 - 1 downto 0);
+      rtu_rq_has_prio_o    : out std_logic;
+      wb_i                 : in  t_wishbone_slave_in;
+      wb_o                 : out t_wishbone_slave_out;
+      pfilter_pclass_o     : out   std_logic_vector(7 downto 0);
+      pfilter_drop_o       : out   std_logic;
+      pfilter_done_o       : out   std_logic;
+      fc_tx_pause_req_i    : in std_logic := '0';
+      fc_tx_pause_delay_i  : in std_logic_vector(15 downto 0) := x"0000";
+      fc_tx_pause_ready_o  : out std_logic;
+      fc_rx_pause_start_p_o     : out std_logic;
+      fc_rx_pause_quanta_o      : out std_logic_vector(15 downto 0);
+      fc_rx_pause_prio_mask_o   : out std_logic_vector(7 downto 0);      
+      fc_rx_buffer_occupation_o : out std_logic_vector(7 downto 0);
+      inject_req_i         : in  std_logic                     := '0';
+      inject_ready_o       : out std_logic;
+      inject_packet_sel_i  : in  std_logic_vector(2 downto 0)  := "000";
+      inject_user_value_i  : in  std_logic_vector(15 downto 0) := x"0000";
+      rmon_events_o        : out std_logic_vector(c_epevents_sz-1 downto 0);
+      txts_o               : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+      rxts_o               : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+      led_link_o           : out std_logic;
+      led_act_o            : out std_logic;
+      link_kill_i          : in  std_logic                     := '0';
+      link_up_o            : out std_logic;
+      stop_traffic_i       : in std_logic := '0';
+      dbg_tx_pcs_wr_count_o     : out std_logic_vector(5+4 downto 0);
+      dbg_tx_pcs_rd_count_o     : out std_logic_vector(5+4 downto 0);
+      nice_dbg_o  : out t_dbg_ep);
+  end component;
+
+  component wr_endpoint
+    generic (
+      g_interface_mode        : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity   : t_wishbone_address_granularity := WORD;
+      g_tx_force_gap_length   : integer                        := 0;
+      g_tx_runt_padding       : boolean                        := false;
+      g_simulation            : boolean                        := false;
+      g_pcs_16bit             : boolean                        := true;
+      g_rx_buffer_size        : integer                        := 1024;
+      g_with_rx_buffer        : boolean                        := true;
+      g_with_flow_control     : boolean                        := true;
+      g_with_timestamper      : boolean                        := true;
+      g_with_dpi_classifier   : boolean                        := false;
+      g_with_vlans            : boolean                        := true;
+      g_with_rtu              : boolean                        := true;
+      g_with_leds             : boolean                        := true;
+      g_with_dmtd             : boolean                        := false;
+      g_with_packet_injection : boolean                        := false;
+      g_use_new_rxcrc         : boolean                        := false;
+      g_use_new_txcrc         : boolean                        := false;
+      g_with_stop_traffic     : boolean                        := false);
+    port (
+      clk_ref_i            : in  std_logic;
+      clk_sys_i            : in  std_logic;
+      clk_dmtd_i           : in  std_logic;
+      rst_sys_n_i          : in  std_logic;
+      rst_ref_n_i          : in  std_logic;
+      rst_dmtd_n_i         : in  std_logic;
+      rst_txclk_n_i        : in  std_logic;
+      rst_rxclk_n_i        : in  std_logic;
+      pps_csync_p1_i       : in  std_logic;
+      pps_valid_i          : in  std_logic                     := '1';
+      phy_rst_o            : out std_logic;
+      phy_loopen_o         : out std_logic;
+      phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+      phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+      phy_sfp_tx_fault_i   : in  std_logic                     := '0';
+      phy_sfp_los_i        : in  std_logic                     := '0';
+      phy_sfp_tx_disable_o : out std_logic;
+      phy_rdy_i            : in  std_logic;
+      phy_ref_clk_i        : in  std_logic;
+      phy_tx_data_o        : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+      phy_tx_k_o           : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+      phy_tx_disparity_i   : in  std_logic;
+      phy_tx_enc_err_i     : in  std_logic;
+      phy_rx_data_i        : in  std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy_rx_clk_i         : in  std_logic;
+      phy_rx_k_i           : in  std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy_rx_enc_err_i     : in  std_logic;
+      phy_rx_bitslide_i    : in  std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      gmii_tx_clk_i        : in  std_logic	 									 := '0';
+      gmii_txd_o           : out std_logic_vector(7 downto 0)  := x"00";
+      gmii_tx_en_o         : out std_logic                     := '0';
+      gmii_tx_er_o         : out std_logic                     := '0';
+      gmii_rx_clk_i        : in  std_logic										 := '0';
+      gmii_rxd_i           : in  std_logic_vector(7 downto 0)  := x"00";
+      gmii_rx_er_i         : in  std_logic := '0';
+      gmii_rx_dv_i         : in  std_logic := '0';
+      src_dat_o            : out std_logic_vector(15 downto 0);
+      src_adr_o            : out std_logic_vector(1 downto 0);
+      src_sel_o            : out std_logic_vector(1 downto 0);
+      src_cyc_o            : out std_logic;
+      src_stb_o            : out std_logic;
+      src_we_o             : out std_logic;
+      src_stall_i          : in  std_logic;
+      src_ack_i            : in  std_logic;
+      src_err_i            : in  std_logic;
+      snk_dat_i            : in  std_logic_vector(15 downto 0);
+      snk_adr_i            : in  std_logic_vector(1 downto 0);
+      snk_sel_i            : in  std_logic_vector(1 downto 0);
+      snk_cyc_i            : in  std_logic;
+      snk_stb_i            : in  std_logic;
+      snk_we_i             : in  std_logic;
+      snk_stall_o          : out std_logic;
+      snk_ack_o            : out std_logic;
+      snk_err_o            : out std_logic;
+      snk_rty_o            : out std_logic;
+      txtsu_port_id_o      : out std_logic_vector(4 downto 0);
+      txtsu_frame_id_o     : out std_logic_vector(16 -1 downto 0);
+      txtsu_ts_value_o     : out std_logic_vector(28 + 4 - 1 downto 0);
+      txtsu_ts_incorrect_o : out std_logic;
+      txtsu_stb_o          : out std_logic;
+      txtsu_ack_i          : in  std_logic;
+      rtu_full_i           : in  std_logic;
+      rtu_almost_full_i    : in  std_logic;
+      rtu_rq_strobe_p1_o   : out std_logic;
+      rtu_rq_abort_o       : out std_logic;
+      rtu_rq_smac_o        : out std_logic_vector(48 - 1 downto 0);
+      rtu_rq_dmac_o        : out std_logic_vector(48 - 1 downto 0);
+      rtu_rq_vid_o         : out std_logic_vector(12 - 1 downto 0);
+      rtu_rq_has_vid_o     : out std_logic;
+      rtu_rq_prio_o        : out std_logic_vector(3 - 1 downto 0);
+      rtu_rq_has_prio_o    : out std_logic;
+      wb_cyc_i             : in  std_logic;
+      wb_stb_i             : in  std_logic;
+      wb_we_i              : in  std_logic;
+      wb_sel_i             : in  std_logic_vector(3 downto 0);
+      wb_adr_i             : in  std_logic_vector(7 downto 0);
+      wb_dat_i             : in  std_logic_vector(31 downto 0);
+      wb_dat_o             : out std_logic_vector(31 downto 0);
+      wb_ack_o             : out std_logic;
+      wb_stall_o           : out std_logic;
+      pfilter_pclass_o     : out   std_logic_vector(7 downto 0);
+      pfilter_drop_o       : out   std_logic;
+      pfilter_done_o       : out   std_logic;
+      fc_tx_pause_req_i    : in std_logic := '0';
+      fc_tx_pause_delay_i  : in std_logic_vector(15 downto 0) := x"0000";
+      fc_tx_pause_ready_o  : out std_logic;
+      fc_rx_pause_start_p_o     : out std_logic;
+      fc_rx_pause_quanta_o      : out std_logic_vector(15 downto 0);
+      fc_rx_pause_prio_mask_o   : out std_logic_vector(7 downto 0);     
+      fc_rx_buffer_occupation_o : out std_logic_vector(7 downto 0);
+      inject_req_i         : in  std_logic                     := '0';
+      inject_ready_o       : out std_logic;
+      inject_packet_sel_i  : in  std_logic_vector(2 downto 0)  := "000";
+      inject_user_value_i  : in  std_logic_vector(15 downto 0) := x"0000";
+      rmon_events_o        : out std_logic_vector(c_epevents_sz-1 downto 0);
+      txts_o               : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+      rxts_o               : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+      led_link_o           : out std_logic;
+      led_act_o            : out std_logic;
+      link_kill_i          : in  std_logic                     := '0';
+      link_up_o            : out std_logic;
+      stop_traffic_i       : in std_logic := '0';
+      dbg_tx_pcs_wr_count_o     : out std_logic_vector(5+4 downto 0);
+      dbg_tx_pcs_rd_count_o     : out std_logic_vector(5+4 downto 0);
+      nice_dbg_o  : out t_dbg_ep);
+  end component;
+  
+  constant c_xwr_endpoint_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"650c2d4f",
+        version   => x"00000002",
+        date      => x"20121116",
+        name      => "WR-Endpoint        ")));
+
+end endpoint_pkg;
+
+package body endpoint_pkg is
+
+  function f_pcs_data_width(pcs_16 : boolean)
+    return integer is
+  begin
+    if (pcs_16) then
+      return 16;
+    else
+      return 8;
+    end if;
+  end function;
+
+  function f_pcs_k_width(pcs_16 : boolean)
+    return integer is
+  begin
+    if (pcs_16) then
+      return 2;
+    else
+      return 1;
+    end if;
+  end function;
+
+  function f_pcs_bts_width(pcs_16 : boolean)
+    return integer is
+  begin
+    if (pcs_16) then
+      return 5;
+    else
+      return 4;
+    end if;
+  end function;
+
+  function f_pcs_clock_rate(pcs_16 : boolean)
+    return integer is
+  begin
+    if (pcs_16) then
+      return 62500000;
+    else
+      return 125000000;
+    end if;
+  end function;
+
+end package body endpoint_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/endpoint_private_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/endpoint_private_pkg.vhd
new file mode 100644
index 000000000..3191e71cb
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/endpoint_private_pkg.vhd
@@ -0,0 +1,930 @@
+-------------------------------------------------------------------------------
+-- Title      : Private constants/types/functions package
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : endpoint_private_pkg.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Endpoint private definitions:
+-- - 8B10B codes
+-- - VLAN control registers
+-- - Data types: internal fabric, RMON, RTU
+-- - 18-bit FIFO fabric packing/unpacking functions
+-- - Endpoint subcomponents declarations
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.ep_wbgen2_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.genram_pkg.all;
+
+package endpoint_private_pkg is
+
+  -- special/control characters
+  constant c_k28_5 : std_logic_vector(7 downto 0) := "10111100";  -- bc
+  constant c_k23_7 : std_logic_vector(7 downto 0) := "11110111";  -- f7
+  constant c_k27_7 : std_logic_vector(7 downto 0) := "11111011";  -- fb
+  constant c_k29_7 : std_logic_vector(7 downto 0) := "11111101";  -- fd
+  constant c_k30_7 : std_logic_vector(7 downto 0) := "11111110";  -- fe
+  constant c_k28_7 : std_logic_vector(7 downto 0) := "11111100";  -- fc
+  constant c_d21_5 : std_logic_vector(7 downto 0) := "10110101";  -- b5
+
+  constant c_d2_2          : std_logic_vector(7 downto 0) := "01000010";  -- 42
+  constant c_d5_6          : std_logic_vector(7 downto 0) := "11000101";  -- c5
+  constant c_d16_2         : std_logic_vector(7 downto 0) := "01010000";  -- 50
+  constant c_preamble_char : std_logic_vector(7 downto 0) := "01010101";
+  constant c_preamble_sfd  : std_logic_vector(7 downto 0) := "11010101";
+
+  constant c_QMODE_PORT_ACCESS        : std_logic_vector(1 downto 0) := "00";
+  constant c_QMODE_PORT_TRUNK         : std_logic_vector(1 downto 0) := "01";
+  constant c_QMODE_PORT_UNQUALIFIED   : std_logic_vector(1 downto 0) := "11";
+  constant c_QMODE_PORT_VLAN_DISABLED : std_logic_vector(1 downto 0) := "10";
+
+  -- fixme: remove these along with the non-WB version of the endpoint
+  constant c_wrsw_ctrl_none      : std_logic_vector(4 - 1 downto 0) := x"0";
+  constant c_wrsw_ctrl_dst_mac   : std_logic_vector(4 - 1 downto 0) := x"1";
+  constant c_wrsw_ctrl_src_mac   : std_logic_vector(4 - 1 downto 0) := x"2";
+  constant c_wrsw_ctrl_ethertype : std_logic_vector(4 - 1 downto 0) := x"3";
+  constant c_wrsw_ctrl_vid_prio  : std_logic_vector(4 - 1 downto 0) := x"4";
+  constant c_wrsw_ctrl_tx_oob    : std_logic_vector(4 - 1 downto 0) := x"5";
+  constant c_wrsw_ctrl_rx_oob    : std_logic_vector(4 - 1 downto 0) := x"6";
+  constant c_wrsw_ctrl_payload   : std_logic_vector(4 - 1 downto 0) := x"7";
+  constant c_wrsw_ctrl_fcs       : std_logic_vector(4 - 1 downto 0) := x"8";
+
+  type t_ep_internal_rtu_request is record
+    smac     : std_logic_vector(47 downto 0);
+    dmac     : std_logic_vector(47 downto 0);
+    vid      : std_logic_vector(11 downto 0);
+    prio     : std_logic_vector(2 downto 0);
+    has_vid  : std_logic;
+    has_prio : std_logic;
+    hash     : std_logic_vector(15 downto 0);
+  end record;
+
+  type t_rmon_triggers is record
+    rx_sync_lost           : std_logic;
+    rx_invalid_code        : std_logic;
+    rx_overrun             : std_logic;
+    rx_crc_err             : std_logic;
+    rx_ok                  : std_logic;
+    rx_pfilter_drop        : std_logic;
+    rx_runt                : std_logic;
+    rx_giant               : std_logic;
+    rx_pause               : std_logic;
+    rx_pcs_err             : std_logic;
+    rx_buffer_overrun      : std_logic;
+    rx_rtu_overrun         : std_logic;
+    rx_path_timing_failure : std_logic;
+    tx_pause               : std_logic;
+    tx_underrun            : std_logic;
+    rx_pclass              : std_logic_vector(7 downto 0); -- packet class (from filter)
+    rx_tclass              : std_logic_vector(7 downto 0); -- traffic class (priority)
+    tx_frame               : std_logic;
+    rx_frame               : std_logic;
+    rx_drop_at_rtu_full    : std_logic;
+  end record;
+
+  component ep_1000basex_pcs
+    generic (
+      g_simulation : boolean;
+      g_16bit      : boolean);
+    port (
+      rst_sys_n_i                   : in  std_logic;
+      rst_txclk_n_i                 : in  std_logic;
+      rst_rxclk_n_i                 : in  std_logic;
+      clk_sys_i                     : in  std_logic;
+      rxpcs_fab_o                   : out t_ep_internal_fabric;
+      rxpcs_fifo_almostfull_i       : in  std_logic;
+      rxpcs_busy_o                  : out std_logic;
+      rxpcs_timestamp_trigger_p_a_o : out std_logic;
+      rxpcs_timestamp_i             : in  std_logic_vector(31 downto 0);
+      rxpcs_timestamp_stb_i         : in  std_logic;
+      rxpcs_timestamp_valid_i       : in  std_logic;
+      txpcs_fab_i                   : in  t_ep_internal_fabric;
+      txpcs_error_o                 : out std_logic;
+      txpcs_busy_o                  : out std_logic;
+      txpcs_dreq_o                  : out std_logic;
+      txpcs_timestamp_trigger_p_a_o : out std_logic;
+      link_ok_o                     : out std_logic;
+      link_ctr_i                    : in  std_logic := '1';
+      serdes_rst_o                  : out std_logic;
+      serdes_loopen_o               : out std_logic;
+      serdes_loopen_vec_o           : out std_logic_vector(2 downto 0);
+      serdes_tx_prbs_sel_o          : out std_logic_vector(2 downto 0);
+      serdes_sfp_tx_fault_i         : in  std_logic;
+      serdes_sfp_los_i              : in  std_logic;
+      serdes_sfp_tx_disable_o       : out std_logic;
+      serdes_rdy_i                  : in  std_logic;
+      serdes_tx_clk_i               : in  std_logic;
+      serdes_tx_data_o              : out std_logic_vector(f_pcs_data_width(g_16bit)-1 downto 0);
+      serdes_tx_k_o                 : out std_logic_vector(f_pcs_k_width(g_16bit)-1 downto 0);
+      serdes_tx_disparity_i         : in  std_logic;
+      serdes_tx_enc_err_i           : in  std_logic;
+      serdes_rx_clk_i               : in  std_logic;
+      serdes_rx_data_i              : in  std_logic_vector(f_pcs_data_width(g_16bit)-1 downto 0);
+      serdes_rx_k_i                 : in  std_logic_vector(f_pcs_k_width(g_16bit)-1 downto 0);
+      serdes_rx_enc_err_i           : in  std_logic;
+      serdes_rx_bitslide_i          : in  std_logic_vector(f_pcs_bts_width(g_16bit)-1 downto 0);
+      rmon_o                        : out t_rmon_triggers;
+      mdio_addr_i                   : in  std_logic_vector(15 downto 0);
+      mdio_data_i                   : in  std_logic_vector(15 downto 0);
+      mdio_data_o                   : out std_logic_vector(15 downto 0);
+      mdio_stb_i                    : in  std_logic;
+      mdio_rw_i                     : in  std_logic;
+      mdio_ready_o                  : out std_logic;
+      dbg_tx_pcs_wr_count_o     : out std_logic_vector(5+4 downto 0);
+      dbg_tx_pcs_rd_count_o     : out std_logic_vector(5+4 downto 0);
+      nice_dbg_o  : out t_dbg_ep_pcs);
+  end component;
+
+  component ep_tx_pcs_8bit
+    port (
+      rst_n_i                 : in  std_logic;
+      rst_txclk_n_i           : in  std_logic;
+      clk_sys_i               : in  std_logic;
+      pcs_fab_i               : in  t_ep_internal_fabric;
+      pcs_error_o             : out std_logic;
+      pcs_busy_o              : out std_logic;
+      pcs_dreq_o              : out std_logic;
+      mdio_mcr_reset_i        : in  std_logic;
+      mdio_mcr_pdown_i        : in  std_logic;
+      mdio_wr_spec_tx_cal_i   : in  std_logic;
+      an_tx_en_i              : in  std_logic;
+      an_tx_val_i             : in  std_logic_vector(15 downto 0);
+      timestamp_trigger_p_a_o : out std_logic;
+      rmon_tx_underrun        : out std_logic;
+      phy_tx_clk_i            : in  std_logic;
+      phy_tx_data_o           : out std_logic_vector(7 downto 0);
+      phy_tx_k_o              : out std_logic;
+      phy_tx_disparity_i      : in  std_logic;
+      phy_tx_enc_err_i        : in  std_logic);
+  end component;
+
+  component ep_tx_pcs_16bit
+    port (
+      rst_n_i                 : in  std_logic;
+      rst_txclk_n_i           : in  std_logic;
+      clk_sys_i               : in  std_logic;
+      pcs_fab_i               : in  t_ep_internal_fabric;
+      pcs_error_o             : out std_logic;
+      pcs_busy_o              : out std_logic;
+      pcs_dreq_o              : out std_logic;
+      mdio_mcr_reset_i        : in  std_logic;
+      mdio_mcr_pdown_i        : in  std_logic;
+      mdio_wr_spec_tx_cal_i   : in  std_logic;
+      an_tx_en_i              : in  std_logic;
+      an_tx_val_i             : in  std_logic_vector(15 downto 0);
+      timestamp_trigger_p_a_o : out std_logic;
+      rmon_tx_underrun        : out std_logic;
+      phy_tx_clk_i            : in  std_logic;
+      phy_tx_data_o           : out std_logic_vector(15 downto 0);
+      phy_tx_k_o              : out std_logic_vector(1 downto 0);
+      phy_tx_disparity_i      : in  std_logic;
+      phy_tx_enc_err_i        : in  std_logic;
+      dbg_wr_count_o     : out std_logic_vector(5+4 downto 0);
+      dbg_rd_count_o     : out std_logic_vector(5+4 downto 0));
+  end component;
+
+  component ep_rx_pcs_8bit
+    generic (
+      g_simulation : boolean);
+    port (
+      clk_sys_i                  : in  std_logic;
+      rst_n_i                    : in  std_logic;
+      rst_rxclk_n_i              : in  std_logic;
+      pcs_fifo_almostfull_i      : in  std_logic;
+      pcs_busy_o                 : out std_logic;
+      pcs_fab_o                  : out t_ep_internal_fabric;
+      timestamp_trigger_p_a_o    : out std_logic;  -- strobe for RX timestamping
+      timestamp_i                : in  std_logic_vector(31 downto 0);
+      timestamp_stb_i            : in  std_logic;
+      timestamp_valid_i          : in  std_logic;
+      phy_rdy_i                  : in  std_logic;
+      phy_rx_clk_i               : in  std_logic;
+      phy_rx_data_i              : in  std_logic_vector(7 downto 0);
+      phy_rx_k_i                 : in  std_logic;
+      phy_rx_enc_err_i           : in  std_logic;
+      mdio_mcr_reset_i           : in  std_logic;
+      mdio_mcr_pdown_i           : in  std_logic;
+      mdio_wr_spec_cal_crst_i    : in  std_logic;
+      mdio_wr_spec_rx_cal_stat_o : out std_logic;
+      synced_o                   : out std_logic;
+      sync_lost_o                : out std_logic;
+      an_rx_en_i                 : in  std_logic;
+      an_rx_val_o                : out std_logic_vector(15 downto 0);
+      an_rx_valid_o              : out std_logic;
+      an_idle_match_o            : out std_logic;
+      rmon_rx_overrun            : out std_logic;
+      rmon_rx_inv_code           : out std_logic;
+      rmon_rx_sync_lost          : out std_logic);
+  end component;
+
+  component ep_rx_pcs_16bit
+    generic (
+      g_simulation : boolean);
+    port (
+      clk_sys_i                  : in  std_logic;
+      rst_n_i                    : in  std_logic;
+      rst_rxclk_n_i              : in  std_logic;
+      pcs_fifo_almostfull_i      : in  std_logic;
+      pcs_busy_o                 : out std_logic;
+      pcs_fab_o                  : out t_ep_internal_fabric;
+      timestamp_trigger_p_a_o    : out std_logic;  -- strobe for RX timestamping
+      timestamp_i                : in  std_logic_vector(31 downto 0);
+      timestamp_stb_i            : in  std_logic;
+      timestamp_valid_i          : in  std_logic;
+      phy_rdy_i                  : in  std_logic;
+      phy_rx_clk_i               : in  std_logic;
+      phy_rx_data_i              : in  std_logic_vector(15 downto 0);
+      phy_rx_k_i                 : in  std_logic_vector(1 downto 0);
+      phy_rx_enc_err_i           : in  std_logic;
+      mdio_mcr_reset_i           : in  std_logic;
+      mdio_mcr_pdown_i           : in  std_logic;
+      mdio_wr_spec_cal_crst_i    : in  std_logic;
+      mdio_wr_spec_rx_cal_stat_o : out std_logic;
+      synced_o                   : out std_logic;
+      sync_lost_o                : out std_logic;
+      an_rx_en_i                 : in  std_logic;
+      an_rx_val_o                : out std_logic_vector(15 downto 0);
+      an_rx_valid_o              : out std_logic;
+      an_idle_match_o            : out std_logic;
+      rmon_rx_overrun            : out std_logic;
+      rmon_rx_inv_code           : out std_logic;
+      rmon_rx_sync_lost          : out std_logic;
+      nice_dbg_o                 : out t_dbg_ep_rxpcs);
+  end component;
+
+  component ep_autonegotiation
+    generic (
+      g_simulation : boolean);
+    port (
+      clk_sys_i               : in  std_logic;
+      rst_n_i                 : in  std_logic;
+      pcs_synced_i            : in  std_logic;
+      pcs_los_i               : in  std_logic;
+      pcs_link_ok_o           : out std_logic;
+      an_idle_match_i         : in  std_logic;
+      an_rx_en_o              : out std_logic;
+      an_rx_val_i             : in  std_logic_vector(15 downto 0);
+      an_rx_valid_i           : in  std_logic;
+      an_tx_en_o              : out std_logic;
+      an_tx_val_o             : out std_logic_vector(15 downto 0);
+      mdio_mcr_anrestart_i    : in  std_logic;
+      mdio_mcr_anenable_i     : in  std_logic;
+      mdio_msr_anegcomplete_o : out std_logic;
+      mdio_advertise_pause_i  : in  std_logic_vector(1 downto 0);
+      mdio_advertise_rfault_i : in  std_logic_vector(1 downto 0);
+      mdio_lpa_full_o         : out std_logic;
+      mdio_lpa_half_o         : out std_logic;
+      mdio_lpa_pause_o        : out std_logic_vector(1 downto 0);
+      mdio_lpa_rfault_o       : out std_logic_vector(1 downto 0);
+      mdio_lpa_lpack_o        : out std_logic;
+      mdio_lpa_npage_o        : out std_logic);
+  end component;
+
+  component ep_pcs_tbi_mdio_wb
+    port (
+      rst_n_i                    : in  std_logic;
+      clk_sys_i                  : in  std_logic;
+      wb_adr_i                   : in  std_logic_vector(4 downto 0);
+      wb_dat_i                   : in  std_logic_vector(31 downto 0);
+      wb_dat_o                   : out std_logic_vector(31 downto 0);
+      wb_cyc_i                   : in  std_logic;
+      wb_sel_i                   : in  std_logic_vector(3 downto 0);
+      wb_stb_i                   : in  std_logic;
+      wb_we_i                    : in  std_logic;
+      wb_ack_o                   : out std_logic;
+      wb_stall_o                 : out std_logic;
+      tx_clk_i                   : in  std_logic;
+      rx_clk_i                   : in  std_logic;
+      mdio_mcr_uni_en_o          : out std_logic;
+      mdio_mcr_anrestart_o       : out std_logic;
+      mdio_mcr_pdown_o           : out std_logic;
+      mdio_mcr_anenable_o        : out std_logic;
+      mdio_mcr_reset_o           : out std_logic;
+      mdio_mcr_loopback_o        : out std_logic;
+      mdio_msr_lstatus_i         : in  std_logic;
+      lstat_read_notify_o        : out std_logic;
+      mdio_msr_rfault_i          : in  std_logic;
+      mdio_msr_anegcomplete_i    : in  std_logic;
+      mdio_advertise_pause_o     : out std_logic_vector(1 downto 0);
+      mdio_advertise_rfault_o    : out std_logic_vector(1 downto 0);
+      mdio_lpa_full_i            : in  std_logic;
+      mdio_lpa_half_i            : in  std_logic;
+      mdio_lpa_pause_i           : in  std_logic_vector(1 downto 0);
+      mdio_lpa_rfault_i          : in  std_logic_vector(1 downto 0);
+      mdio_lpa_lpack_i           : in  std_logic;
+      mdio_lpa_npage_i           : in  std_logic;
+      mdio_wr_spec_tx_cal_o      : out std_logic;
+      mdio_wr_spec_rx_cal_stat_i : in  std_logic;
+      mdio_wr_spec_cal_crst_o    : out std_logic;
+      mdio_wr_spec_bslide_i      : in  std_logic_vector(4 downto 0);
+      mdio_ectrl_lpbck_vec_o       : out std_logic_vector(2 downto 0);
+      mdio_ectrl_sfp_tx_fault_i    : in  std_logic;
+      mdio_ectrl_sfp_loss_i        : in  std_logic;
+      mdio_ectrl_sfp_tx_disable_o  : out std_logic;
+      mdio_ectrl_tx_prbs_sel_o     : out std_logic_vector(2 downto 0));
+  end component;
+
+  component ep_tx_header_processor
+    generic (
+      g_with_packet_injection : boolean;
+      g_with_timestamper      : boolean;
+      g_force_gap_length      : integer;
+      g_runt_padding          : boolean);
+    port (
+      clk_sys_i              : in  std_logic;
+      rst_n_i                : in  std_logic;
+      src_fab_o              : out t_ep_internal_fabric;
+      src_dreq_i             : in  std_logic;
+      pcs_busy_i             : in  std_logic;
+      pcs_error_i            : in  std_logic;
+      wb_snk_i               : in  t_wrf_sink_in;
+      wb_snk_o               : out t_wrf_sink_out;
+      fc_pause_req_i         : in  std_logic;
+      fc_pause_delay_i       : in  std_logic_vector(15 downto 0);
+      fc_pause_ready_o       : out std_logic;
+      fc_flow_enable_i       : in  std_logic;
+      txtsu_port_id_o        : out std_logic_vector(4 downto 0);
+      txtsu_fid_o            : out std_logic_vector(16 -1 downto 0);
+      txtsu_ts_value_o       : out std_logic_vector(28 + 4 - 1 downto 0);
+      txtsu_ts_incorrect_o   : out std_logic;
+      txtsu_stb_o            : out std_logic;
+      txtsu_ack_i            : in  std_logic;
+      txts_timestamp_i       : in  std_logic_vector(31 downto 0);
+      txts_timestamp_valid_i : in  std_logic;
+      ep_ctrl_i              : in std_logic;
+      regs_i                 : in  t_ep_out_registers);
+  end component;
+
+  component ep_tx_vlan_unit
+    port (
+      clk_sys_i         : in  std_logic;
+      rst_n_i           : in  std_logic;
+      snk_fab_i         : in  t_ep_internal_fabric;
+      snk_dreq_o        : out std_logic;
+      src_fab_o         : out t_ep_internal_fabric;
+      src_dreq_i        : in  std_logic;
+      inject_mem_addr_i : in  std_logic_vector(9 downto 0);
+      inject_mem_data_o : out std_logic_vector(17 downto 0);
+      uram_offset_wr_i  : in  std_logic;
+      uram_offset_i     : in  std_logic_vector(9 downto 0);
+      uram_data_i       : in  std_logic_vector(17 downto 0));
+  end component;
+  
+  component ep_timestamping_unit
+    generic (
+      g_timestamp_bits_r : natural;
+      g_timestamp_bits_f : natural;
+      g_ref_clock_rate   : integer);
+    port (
+      clk_ref_i                  : in  std_logic;
+      clk_sys_i                  : in  std_logic;
+      clk_rx_i                   : in  std_logic;
+      rst_n_rx_i                 : in  std_logic;
+      rst_n_ref_i                : in  std_logic;
+      rst_n_sys_i                : in  std_logic;
+      pps_csync_p1_i             : in  std_logic;
+      pps_valid_i                : in  std_logic;
+      tx_timestamp_trigger_p_a_i : in  std_logic;
+      rx_timestamp_trigger_p_a_i : in  std_logic;
+      rxts_timestamp_o           : out std_logic_vector(31 downto 0);
+      rxts_timestamp_stb_o       : out std_logic;
+      rxts_timestamp_valid_o     : out std_logic;
+      txts_timestamp_o           : out std_logic_vector(31 downto 0);
+      txts_timestamp_stb_o       : out std_logic;
+      txts_timestamp_valid_o     : out std_logic;
+      txts_o                     : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+      rxts_o                     : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+      regs_i                     : in  t_ep_out_registers;
+      regs_o                     : out t_ep_in_registers);
+  end component;
+
+  component ep_flow_control
+    port (
+      clk_sys_i          : in  std_logic;
+      rst_n_i            : in  std_logic;
+      rx_pause_p1_i      : in  std_logic;
+      rx_pause_delay_i   : in  std_logic_vector(15 downto 0);
+      tx_pause_o         : out std_logic;
+      tx_pause_delay_o   : out std_logic_vector(15 downto 0);
+      tx_pause_ack_i     : in  std_logic;
+      tx_flow_enable_o   : out std_logic;
+      rx_buffer_used_i   : in  std_logic_vector(7 downto 0);
+      ep_fcr_txpause_i   : in  std_logic;
+      ep_fcr_rxpause_i   : in  std_logic;
+      ep_fcr_tx_thr_i    : in  std_logic_vector(7 downto 0);
+      ep_fcr_tx_quanta_i : in  std_logic_vector(15 downto 0);
+      rmon_rcvd_pause_o  : out std_logic;
+      rmon_sent_pause_o  : out std_logic);
+  end component;
+
+  component ep_wishbone_controller
+    port (
+      rst_n_i            : in  std_logic;
+      clk_sys_i          : in  std_logic;
+      wb_adr_i          : in  std_logic_vector(4 downto 0);
+      wb_dat_i          : in  std_logic_vector(31 downto 0);
+      wb_dat_o          : out std_logic_vector(31 downto 0);
+      wb_cyc_i           : in  std_logic;
+      wb_sel_i           : in  std_logic_vector(3 downto 0);
+      wb_stb_i           : in  std_logic;
+      wb_we_i            : in  std_logic;
+      wb_ack_o           : out std_logic;
+      wb_stall_o         : out std_logic;
+      tx_clk_i           : in  std_logic;
+      rx_clk_i           : in  std_logic;
+      regs_o             : out t_ep_out_registers;
+      regs_i             : in  t_ep_in_registers);
+  end component;
+
+  component ep_leds_controller
+    generic (
+      g_blink_period_log2 : integer);
+    port (
+      clk_sys_i   : in  std_logic;
+      rst_n_i     : in  std_logic;
+      dvalid_tx_i : in  std_logic;
+      dvalid_rx_i : in  std_logic;
+      link_ok_i   : in  std_logic;
+      led_link_o  : out std_logic;
+      led_act_o   : out std_logic);
+  end component;
+
+  component ep_tx_packet_injection
+    port (
+      clk_sys_i           : in  std_logic;
+      rst_n_i             : in  std_logic;
+      snk_fab_i           : in  t_ep_internal_fabric;
+      snk_dreq_o          : out std_logic;
+      src_fab_o           : out t_ep_internal_fabric;
+      src_dreq_i          : in  std_logic;
+      inject_req_i        : in  std_logic;
+      inject_ready_o      : out std_logic;
+      inject_packet_sel_i : in  std_logic_vector(2 downto 0);
+      inject_user_value_i : in  std_logic_vector(15 downto 0);
+      inject_mode_i       : in  std_logic_vector(1 downto 0);
+      mem_addr_o          : out std_logic_vector(9 downto 0);
+      mem_data_i          : in  std_logic_vector(17 downto 0));
+  end component;
+
+  component ep_rtu_header_extract
+    generic (
+      g_with_rtu : boolean);
+    port (
+      clk_sys_i        : in  std_logic;
+      rst_n_i          : in  std_logic;
+      snk_fab_i        : in  t_ep_internal_fabric;
+      snk_dreq_o       : out std_logic;
+      src_fab_o        : out t_ep_internal_fabric;
+      src_dreq_i       : in  std_logic;
+      mbuf_is_pause_i  : in  std_logic;
+      vlan_class_i     : in  std_logic_vector(2 downto 0);
+      vlan_vid_i       : in  std_logic_vector(11 downto 0);
+      vlan_tag_done_i  : in  std_logic;
+      vlan_is_tagged_i : in  std_logic;
+      rmon_drp_at_rtu_full_o: out std_logic;
+      rtu_rq_o         : out t_ep_internal_rtu_request;
+      rtu_full_i       : in  std_logic;
+      rtu_rq_abort_o   : out std_logic;
+      rtu_rq_valid_o   : out std_logic;
+      rxbuf_full_i     : in  std_logic);
+  end component;
+
+  component ep_rx_early_address_match
+    port (
+      clk_sys_i               : in  std_logic;
+      clk_rx_i                : in  std_logic;
+      rst_n_sys_i             : in  std_logic;
+      rst_n_rx_i              : in  std_logic;
+      snk_fab_i               : in  t_ep_internal_fabric;
+      src_fab_o               : out t_ep_internal_fabric;
+      match_done_o            : out std_logic;
+      match_is_hp_o           : out std_logic;
+      match_is_pause_o        : out std_logic;
+      match_pause_quanta_o    : out std_logic_vector(15 downto 0);
+      match_pause_prio_mask_o : out std_logic_vector(7 downto 0);
+      match_pause_p_o         : out std_logic;
+      regs_i                  : in  t_ep_out_registers);
+  end component;
+
+  component ep_clock_alignment_fifo
+    generic (
+      g_size                 : integer;
+      g_almostfull_threshold : integer);
+    port (
+      rst_n_rd_i       : in  std_logic;
+      rst_n_wr_i       : in std_logic;
+      clk_wr_i         : in  std_logic;
+      clk_rd_i         : in  std_logic;
+      dreq_i           : in  std_logic;
+      fab_i            : in  t_ep_internal_fabric;
+      fab_o            : out t_ep_internal_fabric;
+      full_o           : out std_logic;
+      empty_o          : out std_logic;
+      almostfull_o     : out std_logic;
+      pass_threshold_i : in  std_logic_vector(f_log2_size(g_size)-1 downto 0));
+  end component;
+
+  component ep_packet_filter
+    port (
+      clk_rx_i    : in  std_logic;
+      clk_sys_i   : in  std_logic;
+      rst_n_rx_i  : in  std_logic;
+      rst_n_sys_i : in  std_logic;
+      snk_fab_i   : in  t_ep_internal_fabric;
+      src_fab_o   : out t_ep_internal_fabric;
+      done_o      : out std_logic;
+      pclass_o    : out std_logic_vector(7 downto 0);
+      drop_o      : out std_logic;
+      regs_i      : in  t_ep_out_registers);
+  end component;
+
+  component ep_rx_vlan_unit
+    port (
+      clk_sys_i   : in    std_logic;
+      rst_n_i     : in    std_logic;
+      snk_fab_i   : in    t_ep_internal_fabric;
+      snk_dreq_o  : out   std_logic;
+      src_fab_o   : out   t_ep_internal_fabric;
+      src_dreq_i  : in    std_logic;
+      tclass_o    : out   std_logic_vector(2 downto 0);
+      vid_o       : out   std_logic_vector(11 downto 0);
+      tag_done_o  : out   std_logic;
+      is_tagged_o : out   std_logic;
+      regs_i      : in    t_ep_out_registers;
+      regs_o      : out   t_ep_in_registers);
+  end component;
+
+  component ep_rx_oob_insert
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      snk_fab_i  : in  t_ep_internal_fabric;
+      snk_dreq_o : out std_logic;
+      src_fab_o  : out t_ep_internal_fabric;
+      src_dreq_i : in  std_logic;
+      regs_i     : in  t_ep_out_registers);
+  end component;
+
+  component ep_rx_crc_size_check
+  	generic (
+      g_use_new_crc : boolean := false);
+    port (
+      clk_sys_i      : in  std_logic;
+      rst_n_i        : in  std_logic;
+      snk_fab_i      : in  t_ep_internal_fabric;
+      snk_dreq_o     : out std_logic;
+      src_fab_o      : out t_ep_internal_fabric;
+      src_dreq_i     : in  std_logic;
+      regs_i         : in  t_ep_out_registers;
+      rmon_pcs_err_o : out std_logic;
+      rmon_giant_o   : out std_logic;
+      rmon_runt_o    : out std_logic;
+      rmon_crc_err_o : out std_logic);
+  end component;
+
+  component ep_rx_wb_master
+    generic (
+      g_ignore_ack   : boolean;
+      g_cyc_on_stall : boolean := false);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      snk_fab_i  : in  t_ep_internal_fabric;
+      snk_dreq_o : out std_logic;
+      src_wb_i   : in  t_wrf_source_in;
+      src_wb_o   : out t_wrf_source_out);
+  end component;
+
+  component ep_rx_status_reg_insert
+    port (
+      clk_sys_i           : in  std_logic;
+      rst_n_i             : in  std_logic;
+      snk_fab_i           : in  t_ep_internal_fabric;
+      snk_dreq_o          : out std_logic;
+      src_fab_o           : out t_ep_internal_fabric;
+      src_dreq_i          : in  std_logic;
+      mbuf_valid_i        : in  std_logic;
+      mbuf_ack_o          : out std_logic;
+      mbuf_drop_i         : in  std_logic;
+      mbuf_pclass_i       : in  std_logic_vector(7 downto 0);
+      mbuf_is_hp_i        : in  std_logic;
+      mbuf_is_pause_i     : in  std_logic;
+      rmon_pfilter_drop_o : out std_logic);
+  end component;
+
+  component ep_rx_buffer
+    generic (
+      g_size : integer;
+      g_with_fc : boolean := false);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      snk_fab_i  : in  t_ep_internal_fabric;
+      snk_dreq_o : out std_logic;
+      src_fab_o  : out t_ep_internal_fabric;
+      src_dreq_i : in  std_logic;
+      level_o    : out std_logic_vector(7 downto 0);
+      full_o     : out std_logic;
+      drop_req_i : in std_logic;
+      dropped_o  : out std_logic;
+      regs_i     : in  t_ep_out_registers);
+  end component;
+
+
+  component ep_rx_path
+    generic (
+      g_with_vlans          : boolean;
+      g_with_dpi_classifier : boolean;
+      g_with_rtu            : boolean;
+      g_with_rx_buffer      : boolean;
+      g_rx_buffer_size      : integer;
+      g_use_new_crc         :	boolean);
+    port (
+      clk_sys_i              : in  std_logic;
+      clk_rx_i               : in  std_logic;
+      rst_n_sys_i            : in  std_logic;
+      rst_n_rx_i             : in  std_logic;
+      pcs_fab_i              : in  t_ep_internal_fabric;
+      pcs_fifo_almostfull_o  : out std_logic;
+      pcs_busy_i             : in  std_logic;
+      src_wb_o               : out t_wrf_source_out;
+      src_wb_i               : in  t_wrf_source_in;
+      fc_pause_p_o           : out std_logic;
+      fc_pause_quanta_o      : out std_logic_vector(15 downto 0);
+      fc_pause_prio_mask_o   : out std_logic_vector(7 downto 0);
+      fc_buffer_occupation_o : out std_logic_vector(7 downto 0);
+      rmon_o                 : out t_rmon_triggers;
+      regs_i                 : in  t_ep_out_registers;
+      regs_o                 : out t_ep_in_registers;
+      pfilter_pclass_o       : out std_logic_vector(7 downto 0);
+      pfilter_drop_o         : out std_logic;
+      pfilter_done_o         : out std_logic;
+      rtu_rq_o               : out t_ep_internal_rtu_request;
+      rtu_full_i             : in  std_logic;
+      rtu_rq_valid_o         : out std_logic;
+      rtu_rq_abort_o         : out std_logic;
+      nice_dbg_o             : out t_dbg_ep_rxpath);
+  end component;
+
+  component ep_tx_path
+    generic (
+      g_with_vlans            : boolean;
+      g_with_timestamper      : boolean;
+      g_with_packet_injection : boolean;
+      g_force_gap_length      : integer;
+      g_runt_padding          : boolean;
+      g_use_new_crc           :	boolean := false);
+    port (
+      clk_sys_i              : in  std_logic;
+      rst_n_i                : in  std_logic;
+      pcs_fab_o              : out t_ep_internal_fabric;
+      pcs_error_i            : in  std_logic;
+      pcs_busy_i             : in  std_logic;
+      pcs_dreq_i             : in  std_logic;
+      snk_i                  : in  t_wrf_sink_in;
+      snk_o                  : out t_wrf_sink_out;
+      fc_pause_req_i         : in  std_logic;
+      fc_pause_delay_i       : in  std_logic_vector(15 downto 0);
+      fc_pause_ready_o       : out std_logic;
+      fc_flow_enable_i       : in  std_logic;
+      txtsu_port_id_o        : out std_logic_vector(4 downto 0);
+      txtsu_fid_o            : out std_logic_vector(16 -1 downto 0);
+      txtsu_ts_value_o       : out std_logic_vector(28 + 4 - 1 downto 0);
+      txtsu_ts_incorrect_o   : out std_logic;
+      txtsu_stb_o            : out std_logic;
+      txtsu_ack_i            : in  std_logic;
+      txts_timestamp_i       : in  std_logic_vector(31 downto 0);
+      txts_timestamp_valid_i : in  std_logic;
+      inject_req_i           : in  std_logic                     := '0';
+      inject_ready_o         : out std_logic;
+      inject_packet_sel_i    : in  std_logic_vector(2 downto 0)  := "000";
+      inject_user_value_i    : in  std_logic_vector(15 downto 0) := x"0000";
+      ep_ctrl_i              : in  std_logic                     := '1';
+      regs_i                 : in  t_ep_out_registers;
+      regs_o                 : out t_ep_in_registers;
+      dbg_o                  : out std_logic_vector(33 downto 0));
+  end component;
+
+  component ep_tx_crc_inserter
+    generic(
+      g_use_new_crc	: boolean := false);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      snk_fab_i  : in  t_ep_internal_fabric;
+      snk_dreq_o : out std_logic;
+      src_fab_o  : out t_ep_internal_fabric;
+      src_dreq_i : in  std_logic;
+      dbg_o      : out std_logic_vector(2 downto 0));
+  end component;
+  
+  component ep_tx_inject_ctrl
+    generic(
+      g_min_if_gap_length     : integer
+      );
+    port (
+      clk_sys_i             : in  std_logic;
+      rst_n_i               : in  std_logic;
+      snk_fab_i             : in  t_ep_internal_fabric;
+      snk_dreq_o            : out std_logic;
+      src_fab_o             : out t_ep_internal_fabric;
+      src_dreq_i            : in  std_logic;
+      inject_req_o          : out std_logic;
+      inject_ready_i        : in  std_logic;
+      inject_packet_sel_o   : out std_logic_vector(2 downto 0);
+      inject_user_value_o   : out std_logic_vector(15 downto 0);
+      inject_ctr_ena_o      : out std_logic;
+      inject_ctr_mode_o     : out std_logic_vector(1 downto 0);
+      regs_i                : in  t_ep_out_registers;
+      regs_o                : out t_ep_in_registers);
+  end component;
+
+
+  procedure f_pack_fifo_contents (
+    signal fab        : in  t_ep_internal_fabric;
+    signal dout       : out std_logic_vector;
+    signal dout_valid : out std_logic;
+    early_eof         :     boolean := false);
+
+
+  procedure f_unpack_fifo_contents (
+    signal din         : in  std_logic_vector;
+    constant din_valid : in  std_logic;
+    signal fab         : out t_ep_internal_fabric;
+    early_eof          : boolean := false);
+
+
+  procedure f_pack_rmon_triggers (
+      signal trig_in  : in t_rmon_triggers;
+      signal trig_out : out std_logic_vector(c_epevents_sz-1 downto 0));
+
+end endpoint_private_pkg;
+
+-------------------------------------------------------------------------------
+
+package body endpoint_private_pkg is
+
+  procedure f_pack_fifo_contents
+    (
+      signal fab        : in  t_ep_internal_fabric;
+      signal dout       : out std_logic_vector;
+      signal dout_valid : out std_logic;
+      early_eof         :     boolean := false) is
+  begin
+    -- the encodings are slightly different:
+    -- - if early_eof == 1, the target needs the EOF information along with the last data word.
+    --   This is the case for ep_tx_pcs.
+    -- - if early_eof == 0, EOF is an independent transfer
+    if(early_eof) then
+      if(fab.sof = '1' or fab.error = '1') then
+        -- tag = 01
+        dout(17 downto 16) <= "01";
+        dout(15)           <= fab.sof;
+        dout(14)           <= 'X';
+        dout(13)           <= fab.error;
+        dout(12 downto 0)  <= (others => 'X');
+        dout_valid         <= '1';
+      elsif(fab.eof = '1' and 
+         fab.dvalid = '1') then -- ML: it happened that the last word was "stalled" by PCS (dreq_i LOW)
+                                -- at the EOF... CRC indiated that this word is not valid (dvalid LOW)
+                                -- but this information was ignored... and tx was hanging the tree
+        -- tag = 1x
+        dout(17)          <= '1';
+        dout(16)          <= fab.bytesel;
+        dout(15 downto 0) <= fab.data;
+        dout_valid        <= '1';
+      elsif(fab.dvalid = '1') then
+        -- tag = 00
+        dout(17)          <= '0';
+        dout(16)          <= '0';
+        dout(15 downto 0) <= fab.data;
+        dout_valid        <= '1';
+      else
+        dout(17 downto 0) <= (others => 'X');
+        dout_valid        <= '0';
+      end if;
+    else
+      if(fab.sof = '1' or fab.error = '1' or fab.eof = '1' or fab.has_rx_timestamp = '1') then
+        -- tag = 01
+        dout(17)          <= 'X';
+        dout(16)          <= '1';
+        dout(15)          <= fab.sof;
+        dout(14)          <= fab.eof;
+        dout(13)          <= fab.error;
+        dout(12)          <= fab.has_rx_timestamp;
+        dout(11)          <= fab.rx_timestamp_valid;
+        dout(10 downto 0) <= (others => 'X');
+        dout_valid        <= '1';
+      elsif(fab.dvalid = '1') then
+        dout(17)          <= fab.bytesel;
+        dout(16)          <= '0';
+        dout(15 downto 0) <= fab.data;
+        dout_valid        <= '1';
+      else
+        dout(17 downto 0) <= (others => 'X');
+        dout_valid        <= '0';
+      end if;
+
+    end if;
+  end f_pack_fifo_contents;
+
+  procedure f_unpack_fifo_contents
+    (
+      signal din         : in  std_logic_vector;
+      constant din_valid : in  std_logic;
+      signal fab         : out t_ep_internal_fabric;
+      early_eof          : boolean := false) is
+  begin
+
+    fab.data <= din(15 downto 0);
+    fab.addr <= (others => '0');
+    if(din_valid = '1') then
+      if(early_eof) then
+        fab.dvalid             <= not (not din(17) and din(16));
+        fab.sof                <= not din(17) and din(16) and din(15);
+        fab.eof                <= din(17);
+        fab.error              <= not din(17) and din(16) and din(13);
+        fab.has_rx_timestamp   <= '0';
+        fab.rx_timestamp_valid <= '0';
+        fab.bytesel            <= din(17) and din(16);
+
+      else
+        fab.dvalid             <= not din(16);
+        fab.sof                <= din(16) and din(15);
+        fab.eof                <= din(16) and din(14);
+        fab.error              <= din(16) and din(13);
+        fab.has_rx_timestamp   <= din(16) and din(12);
+        fab.rx_timestamp_valid <= din(16) and din(11);
+        fab.bytesel            <= (not din(16)) and din(17);
+      end if;
+    else
+      fab.bytesel            <= 'X';
+      fab.dvalid             <= '0';
+      fab.sof                <= '0';
+      fab.eof                <= '0';
+      fab.error              <= '0';
+      fab.has_rx_timestamp   <= '0';
+      fab.rx_timestamp_valid <= '0';
+      fab.data               <= (others => 'X');
+    end if;
+  end f_unpack_fifo_contents;
+
+
+  procedure f_pack_rmon_triggers
+    (
+      signal trig_in  : in t_rmon_triggers;
+      signal trig_out : out std_logic_vector(c_epevents_sz-1 downto 0)) is
+  begin
+    --from 1000base pcs
+    trig_out(0) <= trig_in.tx_underrun;
+    trig_out(1) <= trig_in.rx_overrun;
+    trig_out(2) <= trig_in.rx_invalid_code;
+    trig_out(3) <= trig_in.rx_sync_lost;
+    trig_out(4) <= trig_in.rx_pause;
+    trig_out(5) <= trig_in.rx_pfilter_drop;
+    trig_out(6) <= trig_in.rx_pcs_err;
+    trig_out(7) <= trig_in.rx_giant;
+    trig_out(8) <= trig_in.rx_runt;
+    trig_out(9) <= trig_in.rx_crc_err;
+    trig_out(17 downto 10) <= trig_in.rx_pclass(7 downto 0);
+    trig_out(18)<= trig_in.tx_frame;
+    trig_out(19)<= trig_in.rx_frame;
+    trig_out(20)<= trig_in.rx_drop_at_rtu_full;
+    trig_out(28 downto 21) <= trig_in.rx_tclass(7 downto 0);
+  end f_pack_rmon_triggers;
+
+
+end endpoint_private_pkg;
+
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_1000basex_pcs.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_1000basex_pcs.vhd
new file mode 100644
index 000000000..900726f69
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_1000basex_pcs.vhd
@@ -0,0 +1,635 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000Base-X Physical Coding Sublayer (PCS)
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_1000basex_pcs.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Module implements the top level of a 1000Base-X compliant PCS
+-- (Physical Coding Sublayer) with precise RX/TX timestamping. The PCS module
+-- incorporates:
+-- - configurable 8/16-bit RX/TX data paths,
+-- - TX clock alignment FIFO,
+-- - 802.3 autonegotiation.
+-- - White Rabbit serdes-specific features (calibration patterns & bitslide)
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2010-11-18  0.4      twlostow  Created (separeted from wrsw_endpoint)
+-- 2011-02-07  0.5      twlostow  Tested on Spartan6 GTP
+-- 2011-10-18  0.6      twlostow  Virtex-6 GTX port
+-- 2012-01-24  0.7      twlostow  Redone TX timestamping
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.gencores_pkg.all;
+
+entity ep_1000basex_pcs is
+
+  generic (
+    -- simulation mode: when true, all internal timeouts are reduced by few orders of
+    -- magnitude to speed up simulations.
+    g_simulation : boolean;
+    -- PCS datapath width selection: true = 16-bit (Virtex-6), false = 8-bit
+    -- (Spartan-6 or TBI).
+    g_16bit      : boolean);
+
+  port (
+
+    ---------------------------------------------------------------------------
+    -- System clock & resets (system + rx/tx)
+    ---------------------------------------------------------------------------
+
+    rst_sys_n_i   : in std_logic;
+    rst_txclk_n_i : in std_logic;
+    rst_rxclk_n_i : in std_logic;
+    clk_sys_i     : in std_logic;
+
+    ---------------------------------------------------------------------------
+    -- PCS <-> MAC Interface
+    ---------------------------------------------------------------------------
+
+    -- Internal data output (incoming data).
+    rxpcs_fab_o : out t_ep_internal_fabric;
+
+    -- 1: RX FIFO is almost full (drop the packet).
+    rxpcs_fifo_almostfull_i : in std_logic;
+
+    -- 1: RX PCS is busy receiving a packet or waiting for its' timestamp.
+    rxpcs_busy_o : out std_logic;
+
+    -- 1-pulse: RX timestamp trigger (to timestamping unit).
+    rxpcs_timestamp_trigger_p_a_o : out std_logic;
+
+    -- RX timestamp value (4 falling : 28 rising edge bits).
+    rxpcs_timestamp_i : in std_logic_vector(31 downto 0);
+
+    rxpcs_timestamp_stb_i : in std_logic;
+
+    -- 1: timestamp on rxpcs_timestamp_i is valid).
+    rxpcs_timestamp_valid_i : in std_logic;
+
+    -- Internal data input (data to be TXed).
+    txpcs_fab_i : in t_ep_internal_fabric;
+
+    -- 1: TX error occured.
+    txpcs_error_o : out std_logic;
+
+    -- 1: TX PCS is busy transmitting a packet.
+    txpcs_busy_o : out std_logic;
+
+    -- 1: TX PCS requests another transfer on txpcs_fab_i.
+    txpcs_dreq_o : out std_logic;
+
+    -- 1-pulse: TX timestamp trigger (to timestamping unit).
+    txpcs_timestamp_trigger_p_a_o : out std_logic;
+
+    link_ok_o : out std_logic;
+    link_ctr_i : in std_logic;
+    -----------------------------------------------------------------------------
+    -- GTP/GTX/TBI Serdes interface
+    ---------------------------------------------------------------------------
+
+    -- 1: serdes is reset, 0: serdes is operating normally.
+    serdes_rst_o : out std_logic;
+
+    -- 1: serdes near-end PMA loopback is enabled.
+    serdes_loopen_o         : out std_logic;
+
+    -- 000: loopback vector "normal operation" (see Serdes User Guide)
+    serdes_loopen_vec_o     : out std_logic_vector(2 downto 0);
+
+    -- 000: "normal operation" (see Serdes User Guide)
+    serdes_tx_prbs_sel_o    : out   std_logic_vector(2 downto 0);
+    
+    -- 1: indicates laser fault
+    serdes_sfp_tx_fault_i   : in  std_logic;
+
+    -- 1: indicates Loss Of Signal
+    serdes_sfp_los_i        : in  std_logic;
+    
+    -- 1: Disables the transmitter
+    serdes_sfp_tx_disable_o : out std_logic;
+
+    -- 1: serdes is locked and aligned
+    serdes_rdy_i    : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Serdes TX path (all synchronous to serdes_tx_clk_i)
+    ---------------------------------------------------------------------------
+
+    -- Transmit path clock:
+    -- 62.5 MHz in 16-bit mode, 125 MHz in 8-bit mode.
+    serdes_tx_clk_i : in std_logic;
+
+    -- TX Code group. In 16-bit mode, the MSB is TXed first (tx_data_o[15:8],
+    -- then tx_data_o[7:0]). In 8-bit mode only bits [7:0] are used.
+    serdes_tx_data_o : out std_logic_vector(f_pcs_data_width(g_16bit)-1 downto 0);
+
+    -- TX Control Code: When 1, a K-character is transmitted. In 16-bit mode,
+    -- bit 1 goes first, in 8-bit mode only bit 0 is used.
+    serdes_tx_k_o : out std_logic_vector(f_pcs_k_width(g_16bit)-1 downto 0);
+
+    -- TX Disparity input: 1 = last transmitted code group ended with negative
+    -- running disparity, 0 = positive RD.
+    serdes_tx_disparity_i : in std_logic;
+
+    -- TX Encoding Error: 1 = PHY encountered a transmission error, drop the current
+    -- packet.
+    serdes_tx_enc_err_i : in std_logic;
+
+    -------------------------------------------------------------------------------
+    -- Serdes RX path (all synchronous to serdes_rx_clk_i)
+    -------------------------------------------------------------------------------
+
+    -- RX recovered clock. MUST be synchronous to incoming serial data stream
+    -- for proper PTP/SyncE operation. 62.5 MHz in 16-bit mode, 125 MHz in 8-bit mode.
+    serdes_rx_clk_i      : in std_logic;
+    serdes_rx_data_i     : in std_logic_vector(f_pcs_data_width(g_16bit)-1 downto 0);
+    serdes_rx_k_i        : in std_logic_vector(f_pcs_k_width(g_16bit)-1 downto 0);
+    serdes_rx_enc_err_i  : in std_logic;
+    serdes_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_16bit)-1 downto 0);
+
+    -- RMON events, aligned to clk_sys
+    rmon_o : out t_rmon_triggers;
+
+    --  MDIO interface
+
+    mdio_addr_i  : in  std_logic_vector(15 downto 0);
+    mdio_data_i  : in  std_logic_vector(15 downto 0);
+    mdio_data_o  : out std_logic_vector(15 downto 0);
+    mdio_stb_i   : in  std_logic;
+    mdio_rw_i    : in  std_logic;
+    mdio_ready_o : out std_logic;
+    
+    dbg_tx_pcs_wr_count_o     : out std_logic_vector(5+4 downto 0);
+    dbg_tx_pcs_rd_count_o     : out std_logic_vector(5+4 downto 0);
+    nice_dbg_o                : out t_dbg_ep_pcs);
+
+end ep_1000basex_pcs;
+
+architecture rtl of ep_1000basex_pcs is
+
+  alias rst_n_i : std_logic is rst_sys_n_i;
+
+  signal mdio_mcr_anrestart       : std_logic;
+  signal mdio_mcr_pdown           : std_logic;
+  signal mdio_mcr_pdown_cpu       : std_logic;
+  signal mdio_mcr_anenable        : std_logic;
+  signal mdio_mcr_reset           : std_logic;
+  signal mdio_msr_lstatus         : std_logic;
+  signal mdio_msr_rfault          : std_logic;
+  signal mdio_msr_anegcomplete    : std_logic;
+  signal mdio_advertise_pause     : std_logic_vector(1 downto 0);
+  signal mdio_advertise_rfault    : std_logic_vector(1 downto 0);
+  signal mdio_lpa_full            : std_logic;
+  signal mdio_lpa_half            : std_logic;
+  signal mdio_lpa_pause           : std_logic_vector(1 downto 0);
+  signal mdio_lpa_rfault          : std_logic_vector(1 downto 0);
+  signal mdio_lpa_lpack           : std_logic;
+  signal mdio_lpa_npage           : std_logic;
+  signal mdio_wr_spec_tx_cal      : std_logic;
+  signal mdio_wr_spec_rx_cal_stat : std_logic;
+  signal mdio_wr_spec_cal_crst    : std_logic;
+  signal mdio_wr_spec_bslide      : std_logic_vector(4 downto 0);
+  signal mdio_data_in             : std_logic_vector(31 downto 0);
+  signal mdio_data_out            : std_logic_vector(31 downto 0);
+
+  signal lstat_read_notify : std_logic;
+
+-------------------------------------------------------------------------------
+-- Autonegotiation signals
+-------------------------------------------------------------------------------
+
+  signal an_tx_en      : std_logic;
+  signal an_rx_en      : std_logic;
+  signal an_tx_val     : std_logic_vector(15 downto 0);
+  signal an_rx_val     : std_logic_vector(15 downto 0);
+  signal an_rx_valid   : std_logic;
+  signal an_idle_match : std_logic;
+
+  signal pcs_enable        : std_logic;
+  signal synced, sync_lost : std_logic;
+  signal synced_d1         : std_logic;
+
+  signal txpcs_busy_int : std_logic;
+  signal link_ok        : std_logic;
+
+  signal pcs_reset_n : std_logic;
+
+  signal wb_stb, wb_ack : std_logic;
+
+  signal tx_clk, rx_clk : std_logic;
+
+  --RMON events
+  signal rmon_tx_underrun : std_logic;
+  signal rmon_rx_overrun  : std_logic;
+  signal rmon_rx_inv_code : std_logic;
+  signal rmon_rx_sync_lost: std_logic;
+  
+begin  -- rtl
+
+  pcs_reset_n <= '0' when (mdio_mcr_reset = '1' or rst_n_i = '0') else '1';
+
+  gen_16bit : if(g_16bit) generate
+    U_TX_PCS : ep_tx_pcs_16bit
+      port map (
+        rst_n_i   => pcs_reset_n,
+        clk_sys_i => clk_sys_i,
+
+        rst_txclk_n_i => rst_txclk_n_i,
+
+        pcs_fab_i   => txpcs_fab_i,
+        pcs_error_o => txpcs_error_o,
+        pcs_busy_o  => txpcs_busy_int,
+        pcs_dreq_o  => txpcs_dreq_o,
+
+        mdio_mcr_reset_i      => mdio_mcr_reset,
+        mdio_mcr_pdown_i      => mdio_mcr_pdown,
+        mdio_wr_spec_tx_cal_i => mdio_wr_spec_tx_cal,
+
+        an_tx_en_i              => an_tx_en,
+        an_tx_val_i             => an_tx_val,
+        timestamp_trigger_p_a_o => txpcs_timestamp_trigger_p_a_o,
+        rmon_tx_underrun        => rmon_tx_underrun,
+
+        phy_tx_clk_i       => serdes_tx_clk_i,
+        phy_tx_data_o      => serdes_tx_data_o,
+        phy_tx_k_o         => serdes_tx_k_o,
+        phy_tx_disparity_i => serdes_tx_disparity_i,
+        phy_tx_enc_err_i   => serdes_tx_enc_err_i,
+        dbg_wr_count_o     => dbg_tx_pcs_wr_count_o,
+        dbg_rd_count_o     => dbg_tx_pcs_rd_count_o     
+        );
+
+    U_RX_PCS : ep_rx_pcs_16bit
+      generic map (
+        g_simulation => g_simulation)
+      port map (
+        clk_sys_i => clk_sys_i,
+        rst_n_i   => pcs_reset_n,
+
+        rst_rxclk_n_i => rst_rxclk_n_i,
+
+        pcs_busy_o            => rxpcs_busy_o,
+        pcs_fab_o             => rxpcs_fab_o,
+        pcs_fifo_almostfull_i => rxpcs_fifo_almostfull_i,
+
+        timestamp_trigger_p_a_o => rxpcs_timestamp_trigger_p_a_o,
+        timestamp_i             => rxpcs_timestamp_i,
+        timestamp_valid_i       => rxpcs_timestamp_valid_i,
+        timestamp_stb_i         => rxpcs_timestamp_stb_i,
+
+        mdio_mcr_reset_i           => mdio_mcr_reset,
+        mdio_mcr_pdown_i           => mdio_mcr_pdown,
+        mdio_wr_spec_cal_crst_i    => mdio_wr_spec_cal_crst,
+        mdio_wr_spec_rx_cal_stat_o => mdio_wr_spec_rx_cal_stat,
+
+        synced_o        => synced,
+        sync_lost_o     => sync_lost,
+        an_rx_en_i      => an_rx_en,
+        an_rx_val_o     => an_rx_val,
+        an_rx_valid_o   => an_rx_valid,
+        an_idle_match_o => an_idle_match,
+
+        rmon_rx_overrun  => rmon_rx_overrun,
+        rmon_rx_inv_code => rmon_rx_inv_code,
+        rmon_rx_sync_lost=> rmon_rx_sync_lost,
+
+        phy_rdy_i        => serdes_rdy_i,
+        phy_rx_clk_i     => serdes_rx_clk_i,
+        phy_rx_data_i    => serdes_rx_data_i,
+        phy_rx_k_i       => serdes_rx_k_i,
+        phy_rx_enc_err_i => serdes_rx_enc_err_i,
+
+        nice_dbg_o => nice_dbg_o.rx
+        );
+
+    mdio_wr_spec_bslide <= serdes_rx_bitslide_i(4 downto 0);
+    
+  end generate gen_16bit;
+
+  gen_8bit : if(not g_16bit) generate
+    U_TX_PCS : ep_tx_pcs_8bit
+      port map (
+        rst_n_i   => pcs_reset_n,
+        clk_sys_i => clk_sys_i,
+
+        rst_txclk_n_i => rst_txclk_n_i,
+
+        pcs_fab_i   => txpcs_fab_i,
+        pcs_error_o => txpcs_error_o,
+        pcs_busy_o  => txpcs_busy_int,
+        pcs_dreq_o  => txpcs_dreq_o,
+
+        mdio_mcr_reset_i      => mdio_mcr_reset,
+        mdio_mcr_pdown_i      => mdio_mcr_pdown,
+        mdio_wr_spec_tx_cal_i => mdio_wr_spec_tx_cal,
+
+        an_tx_en_i              => an_tx_en,
+        an_tx_val_i             => an_tx_val,
+        timestamp_trigger_p_a_o => txpcs_timestamp_trigger_p_a_o,
+        rmon_tx_underrun        => rmon_tx_underrun,
+
+        phy_tx_clk_i       => serdes_tx_clk_i,
+        phy_tx_data_o      => serdes_tx_data_o(7 downto 0),
+        phy_tx_k_o         => serdes_tx_k_o(0),
+        phy_tx_disparity_i => serdes_tx_disparity_i,
+        phy_tx_enc_err_i   => serdes_tx_enc_err_i
+        );
+
+    U_RX_PCS : ep_rx_pcs_8bit
+      generic map (
+        g_simulation => g_simulation)
+      port map (
+        clk_sys_i => clk_sys_i,
+        rst_n_i   => pcs_reset_n,
+
+        rst_rxclk_n_i => rst_rxclk_n_i,
+
+        pcs_busy_o            => rxpcs_busy_o,
+        pcs_fab_o             => rxpcs_fab_o,
+        pcs_fifo_almostfull_i => rxpcs_fifo_almostfull_i,
+
+        timestamp_trigger_p_a_o => rxpcs_timestamp_trigger_p_a_o,
+        timestamp_i             => rxpcs_timestamp_i,
+        timestamp_valid_i       => rxpcs_timestamp_valid_i,
+        timestamp_stb_i         => rxpcs_timestamp_stb_i,
+
+        mdio_mcr_reset_i           => mdio_mcr_reset,
+        mdio_mcr_pdown_i           => mdio_mcr_pdown,
+        mdio_wr_spec_cal_crst_i    => mdio_wr_spec_cal_crst,
+        mdio_wr_spec_rx_cal_stat_o => mdio_wr_spec_rx_cal_stat,
+
+        synced_o        => synced,
+        sync_lost_o     => sync_lost,
+        an_rx_en_i      => an_rx_en,
+        an_rx_val_o     => an_rx_val,
+        an_rx_valid_o   => an_rx_valid,
+        an_idle_match_o => an_idle_match,
+
+        rmon_rx_overrun  => rmon_rx_overrun,
+        rmon_rx_inv_code => rmon_rx_inv_code,
+        rmon_rx_sync_lost=> rmon_rx_sync_lost,
+
+        phy_rdy_i        => serdes_rdy_i,
+        phy_rx_clk_i     => serdes_rx_clk_i,
+        phy_rx_data_i    => serdes_rx_data_i(7 downto 0),
+        phy_rx_k_i       => serdes_rx_k_i(0),
+        phy_rx_enc_err_i => serdes_rx_enc_err_i
+        );
+
+    mdio_wr_spec_bslide <= '0' & serdes_rx_bitslide_i(3 downto 0);
+
+    dbg_tx_pcs_rd_count_o <= (others => '0');
+    dbg_tx_pcs_wr_count_o <= (others => '0');
+    nice_dbg_o.rx.fsm     <= (others => '0');
+
+  end generate gen_8bit;
+
+  txpcs_busy_o <= txpcs_busy_int;
+
+  -- to enable killing of link (by ML)
+  mdio_mcr_pdown <= mdio_mcr_pdown_cpu or (not link_ctr_i);
+
+  -- keep PHY reset also when SFP reports LOS (DL)
+  serdes_rst_o <= (not pcs_reset_n) or mdio_mcr_pdown or serdes_sfp_los_i;
+
+  U_MDIO_WB : ep_pcs_tbi_mdio_wb
+    port map (
+      rst_n_i   => rst_n_i,
+      clk_sys_i => clk_sys_i,
+      wb_adr_i  => mdio_addr_i(4 downto 0),
+      wb_dat_i  => mdio_data_in,
+      wb_dat_o  => mdio_data_out,
+
+      wb_cyc_i   => wb_stb,
+      wb_sel_i   => "1111",
+      wb_stb_i   => wb_stb,
+      wb_we_i    => mdio_rw_i,
+      wb_ack_o   => wb_ack,
+      wb_stall_o => open,
+      tx_clk_i   => serdes_tx_clk_i,
+      rx_clk_i   => serdes_rx_clk_i,
+
+      mdio_mcr_uni_en_o          => open,
+      mdio_mcr_anrestart_o       => mdio_mcr_anrestart,
+      mdio_mcr_pdown_o           => mdio_mcr_pdown_cpu,
+      mdio_mcr_anenable_o        => mdio_mcr_anenable,
+      mdio_mcr_reset_o           => mdio_mcr_reset,
+      mdio_mcr_loopback_o        => serdes_loopen_o,
+      mdio_msr_lstatus_i         => mdio_msr_lstatus,
+      mdio_msr_rfault_i          => mdio_msr_rfault,
+      mdio_msr_anegcomplete_i    => mdio_msr_anegcomplete,
+      mdio_advertise_pause_o     => mdio_advertise_pause,
+      mdio_advertise_rfault_o    => mdio_advertise_rfault,
+      mdio_lpa_full_i            => mdio_lpa_full,
+      mdio_lpa_half_i            => mdio_lpa_half,
+      mdio_lpa_pause_i           => mdio_lpa_pause,
+      mdio_lpa_rfault_i          => mdio_lpa_rfault,
+      mdio_lpa_lpack_i           => mdio_lpa_lpack,
+      mdio_lpa_npage_i           => mdio_lpa_npage,
+      mdio_wr_spec_tx_cal_o      => mdio_wr_spec_tx_cal,
+      mdio_wr_spec_rx_cal_stat_i => mdio_wr_spec_rx_cal_stat,
+      mdio_wr_spec_cal_crst_o    => mdio_wr_spec_cal_crst,
+      mdio_wr_spec_bslide_i      => mdio_wr_spec_bslide,
+      mdio_ectrl_lpbck_vec_o       => serdes_loopen_vec_o,
+      mdio_ectrl_sfp_tx_fault_i    => serdes_sfp_tx_fault_i,
+      mdio_ectrl_sfp_loss_i        => serdes_sfp_los_i,
+      mdio_ectrl_sfp_tx_disable_o  => serdes_sfp_tx_disable_o,
+      mdio_ectrl_tx_prbs_sel_o     => serdes_tx_prbs_sel_o,
+
+      lstat_read_notify_o => lstat_read_notify
+      );
+
+
+  mdio_data_in <= X"0000" & mdio_data_i;
+  mdio_data_o  <= mdio_data_out(15 downto 0);
+
+  mdio_msr_rfault <= '0';
+
+  U_AUTONEGOTIATION : ep_autonegotiation
+    generic map (
+      g_simulation => g_simulation)
+
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => pcs_reset_n,
+
+      pcs_synced_i  => synced,
+      pcs_los_i     => sync_lost,
+      pcs_link_ok_o => link_ok,
+
+      an_idle_match_i         => an_idle_match,
+      an_rx_en_o              => an_rx_en,
+      an_rx_val_i             => an_rx_val,
+      an_rx_valid_i           => an_rx_valid,
+      an_tx_en_o              => an_tx_en,
+      an_tx_val_o             => an_tx_val,
+      mdio_mcr_anrestart_i    => mdio_mcr_anrestart,
+      mdio_mcr_anenable_i     => mdio_mcr_anenable,
+      mdio_msr_anegcomplete_o => mdio_msr_anegcomplete,
+      mdio_advertise_pause_i  => mdio_advertise_pause,
+      mdio_advertise_rfault_i => mdio_advertise_rfault,
+      mdio_lpa_full_o         => mdio_lpa_full,
+      mdio_lpa_half_o         => mdio_lpa_half,
+      mdio_lpa_pause_o        => mdio_lpa_pause,
+      mdio_lpa_rfault_o       => mdio_lpa_rfault,
+      mdio_lpa_lpack_o        => mdio_lpa_lpack,
+      mdio_lpa_npage_o        => mdio_lpa_npage
+      );
+
+  -- process: translates the MDIO reads/writes into Wishbone read/writes
+  -- inputs: mdio_stb_i, wb_ack
+  -- ouputs: mdio_ready_o, wb_stb
+  p_translate_mdio_wb : process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if (rst_n_i = '0') then
+        wb_stb       <= '0';
+        mdio_ready_o <= '1';
+      else
+        if(mdio_stb_i = '1' and wb_stb = '0') then
+          wb_stb       <= '1';
+          mdio_ready_o <= '0';
+        elsif(wb_stb = '1' and wb_ack = '1') then
+          mdio_ready_o <= '1';
+          wb_stb       <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -- process: handles the LSTATUS bit in MSR register
+  -- inputs: sync_lost, synced, lstat_read_notify
+  -- outputs: mdio_msr_lstatus
+  p_gen_link_status : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(pcs_reset_n = '0') then
+        mdio_msr_lstatus <= '0';
+      else
+        if(sync_lost = '1') then
+          mdio_msr_lstatus <= '0';
+        elsif(lstat_read_notify = '1') then
+          mdio_msr_lstatus <= synced and link_ok;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -- The process delays by 1 cyc synced signal. This delayed synced, called synced_d1
+  -- is then used to produce link_ok_o (below he process).
+  -- This is done to avoid 1-cycle glitches of link_ok_o. Such glitch happened after
+  -- the autonegotation FSM was in pseudo AN_ENABLED state caused by synced=LOW (in
+  -- this state, link_ok is HIGH). When synced goes HIGH, the FSM enters "proper" 
+  -- AN_ENABLED state, it drives link_ok LOW.s All in all, this glitch is avoided
+  -- when we use delayed synced_d1 to produce the final link_ok_o
+  p_delay_synced: process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(pcs_reset_n = '0') then
+        synced_d1 <= '0';
+      else
+        synced_d1 <= synced;
+      end if;
+    end if;
+  end process;
+
+  link_ok_o <= link_ok and synced_d1;
+
+  --RMON events
+  U_sync_tx_underrun: gc_sync_ffs
+  generic map (
+    g_sync_edge => "positive")
+  port map (
+    clk_i    => clk_sys_i,
+    rst_n_i  => rst_n_i,
+    data_i   => rmon_tx_underrun,
+    synced_o => open,
+    npulse_o => open,
+    ppulse_o => rmon_o.tx_underrun);
+
+  U_sync_rx_overrun: gc_sync_ffs
+  generic map (
+    g_sync_edge => "positive")
+  port map (
+    clk_i    => clk_sys_i,
+    rst_n_i  => rst_n_i,
+    data_i   => rmon_rx_overrun,
+    synced_o => open,
+    npulse_o => open,
+    ppulse_o => rmon_o.rx_overrun);
+
+  U_sync_rx_inv_code: gc_sync_ffs
+  generic map (
+    g_sync_edge => "positive")
+  port map (
+    clk_i    => clk_sys_i,
+    rst_n_i  => rst_n_i,
+    data_i   => rmon_rx_inv_code,
+    synced_o => open,
+    npulse_o => open,
+    ppulse_o => rmon_o.rx_invalid_code);
+
+  U_sync_rx_sync_lost: gc_sync_ffs
+  generic map (
+    g_sync_edge => "positive")
+  port map (
+    clk_i    => clk_sys_i,
+    rst_n_i  => rst_n_i,
+    data_i   => rmon_rx_sync_lost,
+    synced_o => open,
+    npulse_o => open,
+    ppulse_o => rmon_o.rx_sync_lost);
+
+  -- drive unused outputs
+  rmon_o.rx_crc_err             <= '0';
+  rmon_o.rx_ok                  <= '0';
+  rmon_o.rx_pfilter_drop        <= '0';
+  rmon_o.rx_runt                <= '0';
+  rmon_o.rx_giant               <= '0';
+  rmon_o.rx_pause               <= '0';
+  rmon_o.rx_pcs_err             <= '0';
+  rmon_o.rx_buffer_overrun      <= '0';
+  rmon_o.rx_rtu_overrun         <= '0';
+  rmon_o.rx_path_timing_failure <= '0';
+  rmon_o.tx_pause               <= '0';
+  rmon_o.rx_pclass              <= (others => '0');
+  rmon_o.rx_tclass              <= (others => '0');
+  rmon_o.tx_frame               <= '0';
+  rmon_o.rx_frame               <= '0';
+  rmon_o.rx_drop_at_rtu_full    <= '0';
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_autonegotiation.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_autonegotiation.vhd
new file mode 100644
index 000000000..69dbe4c06
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_autonegotiation.vhd
@@ -0,0 +1,281 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000Base-X Autonegotiation 
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_autonegotiation.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2017-02-21
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Module implements the 1000Base-X autonegotiation engine as
+-- defined in IEEE802.3.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1l.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2010-11-18  0.4      twlostow  Initial release
+-- 2011-02-07  0.5      twlostow  Tested on Spartan6 GTP
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.endpoint_private_pkg.all;
+
+entity ep_autonegotiation is
+  generic (
+    g_simulation : boolean);
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    -- RX PCS signals
+    pcs_synced_i  : in  std_logic;
+    pcs_los_i     : in  std_logic;
+    pcs_link_ok_o : out std_logic;
+
+    an_idle_match_i : in  std_logic;
+    an_rx_en_o      : out std_logic;
+    an_rx_val_i     : in  std_logic_vector(15 downto 0);
+    an_rx_valid_i   : in  std_logic;
+
+    -- TX PCS signals
+    an_tx_en_o  : out std_logic;
+    an_tx_val_o : out std_logic_vector(15 downto 0);
+
+    mdio_mcr_anrestart_i    : in  std_logic;
+    mdio_mcr_anenable_i     : in  std_logic;
+    mdio_msr_anegcomplete_o : out std_logic;
+
+    mdio_advertise_pause_i  : in std_logic_vector(1 downto 0);
+    mdio_advertise_rfault_i : in std_logic_vector(1 downto 0);
+
+    mdio_lpa_full_o   : out std_logic;
+    mdio_lpa_half_o   : out std_logic;
+    mdio_lpa_pause_o  : out std_logic_vector(1 downto 0);
+    mdio_lpa_rfault_o : out std_logic_vector(1 downto 0);
+    mdio_lpa_lpack_o  : out std_logic;
+    mdio_lpa_npage_o  : out std_logic
+    );
+
+end ep_autonegotiation;
+
+architecture syn of ep_autonegotiation is
+
+  type t_autoneg_state is (AN_ENABLE, AN_RESTART, AN_ABILITY_DETECT, AN_DISABLE_LINK_OK, AN_ACKNOWLEDGE_DETECT, AN_COMPLETE_ACKNOWLEDGE, AN_IDLE_DETECT, AN_LINK_OK);
+
+  signal state : t_autoneg_state;
+
+
+  function f_eval_link_timer_size
+    return integer is
+  begin  -- f_eval_link_timer_size
+    if(g_simulation = false) then
+      return 20;
+      else
+        return 11;
+      end if;
+  end f_eval_link_timer_size;
+
+  constant c_link_timer_bits : integer := f_eval_link_timer_size;
+  
+  signal link_timer : unsigned(c_link_timer_bits downto 0);  -- 23 for normal operation
+
+
+  signal link_timer_restart : std_logic;
+  signal link_timer_expired : std_logic;
+
+  signal an_enable_changed, an_enable_d0 : std_logic;
+  signal toggle_tx, toggle_rx            : std_logic;
+
+  signal rx_config_reg : std_logic_vector(15 downto 0);
+
+  signal acknowledge_match : std_logic;
+  signal ability_match     : std_logic;
+  signal consistency_match : std_logic;
+  
+  
+  
+begin  -- syn
+
+
+  -- process: link timer (counts until MSB of link_timer == 1).
+  -- inputs: link_timer_restart
+  -- outputs: link_timer_expired
+  p_link_timer : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' or link_timer_restart ='1'  then
+        link_timer <= (others => '0');
+      else
+        if(link_timer_expired = '0') then
+          link_timer <= link_timer + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  link_timer_expired <= std_logic(link_timer(link_timer'high)) and (not link_timer_restart);
+
+
+  -- process: detects the changes of Autonegotiation Enable bit.
+  -- inputs: mdio_mcr_anenable_i
+  -- outputs: an_enable_changed
+  p_detect_enable_changed : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      an_enable_d0      <= mdio_mcr_anenable_i;
+      an_enable_changed <= an_enable_d0 xor mdio_mcr_anenable_i;
+    end if;
+  end process;
+
+
+  -- generate some FSM conditions combinatorially outside the FSM process to
+  -- make the code more readable
+  ability_match     <= an_rx_valid_i;
+  acknowledge_match <= an_rx_valid_i and an_rx_val_i(14);
+  consistency_match <= '1' when (an_rx_valid_i = '1' and rx_config_reg (15) = an_rx_val_i(15) and rx_config_reg(13 downto 0) = an_rx_val_i(13 downto 0));
+
+
+-- process: main auto-negotiation state machine. More or less compatible with
+-- IEEE 802.3.
+  p_autonegotation_fsm : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        link_timer_restart <= '0';
+        state              <= AN_ENABLE;
+        pcs_link_ok_o      <= '0';
+
+        an_tx_en_o  <= '0';
+        an_rx_en_o  <= '1';
+        an_tx_val_o <= (others => '0');
+
+        mdio_lpa_lpack_o        <= '0';
+        mdio_msr_anegcomplete_o <= '0';
+        rx_config_reg           <= (others => '0');
+      else
+
+        if(mdio_mcr_anrestart_i = '1' or an_enable_changed = '1' or pcs_synced_i = '0') then
+          state <= AN_ENABLE;
+        else
+          
+          case state is
+            when AN_ENABLE =>
+              mdio_msr_anegcomplete_o <= '0';
+              pcs_link_ok_o <= '0';
+
+              if mdio_mcr_anenable_i = '1' then
+                an_tx_val_o        <= (others => '0');  -- send breaklink
+                an_tx_en_o         <= '1';
+                link_timer_restart <= '1';
+                state              <= AN_RESTART;
+              else
+                state <= AN_DISABLE_LINK_OK;
+              end if;
+
+            when AN_DISABLE_LINK_OK =>
+              an_tx_en_o    <= '0';
+              pcs_link_ok_o <= '1';
+              
+            when AN_RESTART =>
+              link_timer_restart <= '0';
+              if(link_timer_expired = '1') then
+                state <= AN_ABILITY_DETECT;
+              end if;
+
+
+            when AN_ABILITY_DETECT =>
+--              toggle_tx <= mr_adv_ability<12> -- ???
+              an_rx_en_o                 <= '1';
+              an_tx_en_o                 <= '1';
+              an_tx_val_o (15)           <= '0';
+              an_tx_val_o (14)           <= '0';
+              an_tx_val_o (13 downto 12) <= mdio_advertise_rfault_i;
+              an_tx_val_o (11 downto 9)  <= (others => '0');
+              an_tx_val_o (8 downto 7)   <= mdio_advertise_pause_i;
+              an_tx_val_o (6)            <= '0';  -- hdx not supported
+              an_tx_val_o (5)            <= '1';  -- fdx supported
+              an_tx_val_o (4 downto 0)   <= (others => '0');
+
+              if(an_rx_valid_i = '1' and an_rx_val_i /= x"0000") then  -- ability_match=true
+                state         <= AN_ACKNOWLEDGE_DETECT;
+                rx_config_reg <= an_rx_val_i;
+              end if;
+
+            when AN_ACKNOWLEDGE_DETECT =>
+              an_tx_val_o(14) <= '1';
+              if(acknowledge_match = '1' and consistency_match = '0')
+                or (ability_match = '1' and an_rx_val_i = x"0000") then
+                state <= AN_ENABLE;
+              elsif(acknowledge_match = '1' and consistency_match = '1') then
+                state              <= AN_COMPLETE_ACKNOWLEDGE;
+                link_timer_restart <= '1';
+              end if;
+
+            when AN_COMPLETE_ACKNOWLEDGE =>
+              link_timer_restart <= '0';
+
+              mdio_lpa_npage_o  <= an_rx_val_i(15);
+              mdio_lpa_lpack_o  <= an_rx_val_i(14);
+              mdio_lpa_rfault_o <= an_rx_val_i(13 downto 12);
+              mdio_lpa_pause_o  <= an_rx_val_i (8 downto 7);
+              mdio_lpa_half_o   <= an_rx_val_i(6);
+              mdio_lpa_full_o   <= an_rx_val_i(5);
+
+
+              if(ability_match = '1' and an_rx_val_i = x"0000")then
+                state <= AN_ENABLE;
+              elsif(link_timer_expired = '1' and (ability_match = '0' or an_rx_val_i /= x"0000")) then
+                link_timer_restart <= '1';
+                state              <= AN_IDLE_DETECT;
+              end if;
+
+            when AN_IDLE_DETECT =>
+              link_timer_restart <= '0';
+              an_tx_en_o         <= '0';
+              if(ability_match = '1' and an_rx_val_i = x"0000") then
+                state <= AN_ENABLE;
+              elsif (an_idle_match_i = '1' and link_timer_expired = '1') then
+                state <= AN_LINK_OK;
+              end if;
+
+
+            when AN_LINK_OK =>
+              mdio_msr_anegcomplete_o <= '1';
+              pcs_link_ok_o           <= '1';
+              if(ability_match = '1') then
+                state <= AN_ENABLE;
+              end if;
+              
+            when others => null;
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_clock_alignment_fifo.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
new file mode 100644
index 000000000..09a214467
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
@@ -0,0 +1,127 @@
+-------------------------------------------------------------------------------
+-- Title      : RX Clock Alignment FIFO
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_clock_alignment_fifo.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2012-08-28
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Asynchronous FIFO with internal fabric (t_ep_internal_fabric)
+-- interface used to pass packet data between the RX clock->system clock
+-- domains. 
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.genram_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+
+entity ep_clock_alignment_fifo is
+
+  generic(
+    g_size                 : integer := 64;
+    g_almostfull_threshold : integer := 56);
+
+  port(
+    rst_n_rd_i : in std_logic;
+    rst_n_wr_i : in std_logic;
+    clk_wr_i   : in std_logic;
+    clk_rd_i   : in std_logic;
+
+    dreq_i : in  std_logic;
+    fab_i  : in  t_ep_internal_fabric;
+    fab_o  : out t_ep_internal_fabric;
+
+    full_o       : out std_logic;
+    empty_o      : out std_logic;
+    almostfull_o : out std_logic;
+
+    -- number of data words which enables the output. Used
+    -- to control the minimum latency
+    pass_threshold_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0)
+    );
+end ep_clock_alignment_fifo;
+
+architecture structural of ep_clock_alignment_fifo is
+  signal fifo_in   : std_logic_vector(17 downto 0);
+  signal fifo_out  : std_logic_vector(17 downto 0);
+  signal rx_rdreq  : std_logic;
+  signal empty_int : std_logic;
+  signal valid_int : std_logic;
+
+
+  signal fab_int      : t_ep_internal_fabric;
+  signal fifo_we      : std_logic;
+begin
+
+  f_pack_fifo_contents (fab_i, fifo_in, fifo_we, false);
+
+-- Clock adjustment FIFO
+  U_FIFO : generic_async_fifo
+    generic map (
+      g_data_width             => 18,
+      g_size                   => g_size,
+      g_with_wr_almost_full    => true,
+      g_almost_full_threshold  => g_almostfull_threshold
+      )
+    port map (
+      rst_n_i           => rst_n_wr_i,
+      clk_wr_i          => clk_wr_i,
+      d_i               => fifo_in,
+      we_i              => fifo_we,
+      wr_full_o         => full_o,
+      wr_almost_full_o  => almostfull_o,
+      clk_rd_i          => clk_rd_i,
+      q_o               => fifo_out,
+      rd_i              => rx_rdreq,
+      rd_empty_o        => empty_int);
+  
+
+  rx_rdreq <= (not empty_int) and dreq_i; -- and dreq_mask;
+
+
+  p_readout : process (clk_rd_i)
+  begin
+    if rising_edge(clk_rd_i) then
+      if(rst_n_rd_i = '0') then
+        valid_int <= '0';
+      else
+        valid_int <= rx_rdreq;
+      end if;
+    end if;
+  end process;
+
+  -- FIFO output data formatting
+  f_unpack_fifo_contents(fifo_out, valid_int, fab_int, false);
+
+  fab_o   <= fab_int;
+  empty_o <= empty_int;
+  
+end structural;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_crc32_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_crc32_pkg.vhd
new file mode 100644
index 000000000..c51f95827
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_crc32_pkg.vhd
@@ -0,0 +1,128 @@
+-------------------------------------------------------------------------------
+-- Title      : CRC32 package
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_crc32_pkg.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2013 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package ep_crc32_pkg is
+
+
+  constant c_CRC32_RESIDUE_FULL : std_logic_vector(31 downto 0) := x"1cdf4421";
+  constant c_CRC32_RESIDUE_HALF : std_logic_vector(31 downto 0) := x"1df722c6";
+  constant c_CRC32_INIT_VALUE   : std_logic_vector(31 downto 0) := x"00000000";
+
+  function f_update_crc32_d16(d : std_logic_vector; data_in : std_logic_vector) return std_logic_vector;
+  function f_update_crc32_d8(d  : std_logic_vector(31 downto 0); data_in : std_logic_vector(7 downto 0)) return std_logic_vector;
+  
+end ep_crc32_pkg;
+
+package body ep_crc32_pkg is
+
+
+  function f_update_crc32_d16(d : std_logic_vector; data_in : std_logic_vector) return std_logic_vector is
+    variable q : std_logic_vector(d'length-1 downto 0);
+  begin
+    q(7)  := not ((not d(23)) xor (not d(17)) xor (not d(30)) xor (not d(29)) xor (not d(27)) xor data_in(7) xor data_in(1) xor data_in(14) xor data_in(13) xor data_in(11));
+    q(6)  := not ((not d(23)) xor (not d(22)) xor (not d(17)) xor (not d(16)) xor (not d(30)) xor (not d(28)) xor (not d(27)) xor (not d(26)) xor data_in(7) xor data_in(6) xor data_in(1) xor data_in(0) xor data_in(14) xor data_in(12) xor data_in(11) xor data_in(10));
+    q(5)  := not ((not d(23)) xor (not d(22)) xor (not d(21)) xor (not d(17)) xor (not d(16)) xor (not d(31)) xor (not d(30)) xor (not d(26)) xor (not d(25)) xor data_in(7) xor data_in(6) xor data_in(5) xor data_in(1) xor data_in(0) xor data_in(15) xor data_in(14) xor data_in(10) xor data_in(9));
+    q(4)  := not ((not d(22)) xor (not d(21)) xor (not d(20)) xor (not d(16)) xor (not d(31)) xor (not d(30)) xor (not d(29)) xor (not d(25)) xor (not d(24)) xor data_in(6) xor data_in(5) xor data_in(4) xor data_in(0) xor data_in(15) xor data_in(14) xor data_in(13) xor data_in(9) xor data_in(8));
+    q(3)  := not ((not d(23)) xor (not d(21)) xor (not d(20)) xor (not d(19)) xor (not d(17)) xor (not d(31)) xor (not d(28)) xor (not d(27)) xor (not d(24)) xor data_in(7) xor data_in(5) xor data_in(4) xor data_in(3) xor data_in(1) xor data_in(15) xor data_in(12) xor data_in(11) xor data_in(8));
+    q(2)  := not ((not d(23)) xor (not d(22)) xor (not d(20)) xor (not d(19)) xor (not d(18)) xor (not d(17)) xor (not d(16)) xor (not d(29)) xor (not d(26)) xor data_in(7) xor data_in(6) xor data_in(4) xor data_in(3) xor data_in(2) xor data_in(1) xor data_in(0) xor data_in(13) xor data_in(10));
+    q(1)  := not ((not d(22)) xor (not d(21)) xor (not d(19)) xor (not d(18)) xor (not d(17)) xor (not d(16)) xor (not d(31)) xor (not d(28)) xor (not d(25)) xor data_in(6) xor data_in(5) xor data_in(3) xor data_in(2) xor data_in(1) xor data_in(0) xor data_in(15) xor data_in(12) xor data_in(9));
+    q(0)  := not ((not d(23)) xor (not d(21)) xor (not d(20)) xor (not d(18)) xor (not d(16)) xor (not d(31)) xor (not d(29)) xor (not d(24)) xor data_in(7) xor data_in(5) xor data_in(4) xor data_in(2) xor data_in(0) xor data_in(15) xor data_in(13) xor data_in(8));
+    q(15) := not ((not d(23)) xor (not d(22)) xor (not d(20)) xor (not d(19)) xor (not d(31)) xor (not d(29)) xor (not d(28)) xor (not d(27)) xor data_in(7) xor data_in(6) xor data_in(4) xor data_in(3) xor data_in(15) xor data_in(13) xor data_in(12) xor data_in(11));
+    q(14) := not ((not d(22)) xor (not d(21)) xor (not d(19)) xor (not d(18)) xor (not d(30)) xor (not d(28)) xor (not d(27)) xor (not d(26)) xor data_in(6) xor data_in(5) xor data_in(3) xor data_in(2) xor data_in(14) xor data_in(12) xor data_in(11) xor data_in(10));
+    q(13) := not ((not d(23)) xor (not d(21)) xor (not d(20)) xor (not d(18)) xor (not d(30)) xor (not d(26)) xor (not d(25)) xor data_in(7) xor data_in(5) xor data_in(4) xor data_in(2) xor data_in(14) xor data_in(10) xor data_in(9));
+    q(12) := not ((not d(23)) xor (not d(22)) xor (not d(20)) xor (not d(19)) xor (not d(30)) xor (not d(27)) xor (not d(25)) xor (not d(24)) xor data_in(7) xor data_in(6) xor data_in(4) xor data_in(3) xor data_in(14) xor data_in(11) xor data_in(9) xor data_in(8));
+    q(11) := not ((not d(23)) xor (not d(22)) xor (not d(21)) xor (not d(19)) xor (not d(18)) xor (not d(17)) xor (not d(30)) xor (not d(27)) xor (not d(26)) xor (not d(24)) xor data_in(7) xor data_in(6) xor data_in(5) xor data_in(3) xor data_in(2) xor data_in(1) xor data_in(14) xor data_in(11) xor data_in(10) xor data_in(8));
+    q(10) := not ((not d(22)) xor (not d(21)) xor (not d(20)) xor (not d(18)) xor (not d(17)) xor (not d(16)) xor (not d(29)) xor (not d(26)) xor (not d(25)) xor data_in(6) xor data_in(5) xor data_in(4) xor data_in(2) xor data_in(1) xor data_in(0) xor data_in(13) xor data_in(10) xor data_in(9));
+    q(9)  := not ((not d(21)) xor (not d(20)) xor (not d(19)) xor (not d(17)) xor (not d(16)) xor (not d(31)) xor (not d(28)) xor (not d(25)) xor (not d(24)) xor data_in(5) xor data_in(4) xor data_in(3) xor data_in(1) xor data_in(0) xor data_in(15) xor data_in(12) xor data_in(9) xor data_in(8));
+    q(8)  := not ((not d(20)) xor (not d(19)) xor (not d(18)) xor (not d(16)) xor (not d(31)) xor (not d(30)) xor (not d(27)) xor (not d(24)) xor data_in(4) xor data_in(3) xor data_in(2) xor data_in(0) xor data_in(15) xor data_in(14) xor data_in(11) xor data_in(8));
+    q(23) := not ((not d(7)) xor (not d(23)) xor (not d(19)) xor (not d(18)) xor (not d(31)) xor (not d(27)) xor (not d(26)) xor data_in(7) xor data_in(3) xor data_in(2) xor data_in(15) xor data_in(11) xor data_in(10));
+    q(22) := not ((not d(6)) xor (not d(22)) xor (not d(18)) xor (not d(17)) xor (not d(30)) xor (not d(26)) xor (not d(25)) xor data_in(6) xor data_in(2) xor data_in(1) xor data_in(14) xor data_in(10) xor data_in(9));
+    q(21) := not ((not d(5)) xor (not d(21)) xor (not d(17)) xor (not d(16)) xor (not d(29)) xor (not d(25)) xor (not d(24)) xor data_in(5) xor data_in(1) xor data_in(0) xor data_in(13) xor data_in(9) xor data_in(8));
+    q(20) := not ((not d(4)) xor (not d(20)) xor (not d(16)) xor (not d(31)) xor (not d(28)) xor (not d(24)) xor data_in(4) xor data_in(0) xor data_in(15) xor data_in(12) xor data_in(8));
+    q(19) := not ((not d(3)) xor (not d(19)) xor (not d(31)) xor (not d(30)) xor (not d(27)) xor data_in(3) xor data_in(15) xor data_in(14) xor data_in(11));
+    q(18) := not ((not d(2)) xor (not d(18)) xor (not d(30)) xor (not d(29)) xor (not d(26)) xor data_in(2) xor data_in(14) xor data_in(13) xor data_in(10));
+    q(17) := not ((not d(1)) xor (not d(23)) xor (not d(30)) xor (not d(28)) xor (not d(27)) xor (not d(25)) xor data_in(7) xor data_in(14) xor data_in(12) xor data_in(11) xor data_in(9));
+    q(16) := not ((not d(0)) xor (not d(23)) xor (not d(22)) xor (not d(17)) xor (not d(30)) xor (not d(26)) xor (not d(24)) xor data_in(7) xor data_in(6) xor data_in(1) xor data_in(14) xor data_in(10) xor data_in(8));
+    q(31) := not ((not d(15)) xor (not d(22)) xor (not d(21)) xor (not d(16)) xor (not d(29)) xor (not d(25)) xor data_in(6) xor data_in(5) xor data_in(0) xor data_in(13) xor data_in(9));
+    q(30) := not ((not d(14)) xor (not d(21)) xor (not d(20)) xor (not d(31)) xor (not d(28)) xor (not d(24)) xor data_in(5) xor data_in(4) xor data_in(15) xor data_in(12) xor data_in(8));
+    q(29) := not ((not d(13)) xor (not d(23)) xor (not d(20)) xor (not d(19)) xor (not d(17)) xor (not d(29)) xor data_in(7) xor data_in(4) xor data_in(3) xor data_in(1) xor data_in(13));
+    q(28) := not ((not d(12)) xor (not d(22)) xor (not d(19)) xor (not d(18)) xor (not d(16)) xor (not d(28)) xor data_in(6) xor data_in(3) xor data_in(2) xor data_in(0) xor data_in(12));
+    q(27) := not ((not d(11)) xor (not d(21)) xor (not d(18)) xor (not d(17)) xor (not d(31)) xor (not d(27)) xor data_in(5) xor data_in(2) xor data_in(1) xor data_in(15) xor data_in(11));
+    q(26) := not ((not d(10)) xor (not d(20)) xor (not d(17)) xor (not d(16)) xor (not d(30)) xor (not d(26)) xor data_in(4) xor data_in(1) xor data_in(0) xor data_in(14) xor data_in(10));
+    q(25) := not ((not d(9)) xor (not d(19)) xor (not d(16)) xor (not d(31)) xor (not d(29)) xor (not d(25)) xor data_in(3) xor data_in(0) xor data_in(15) xor data_in(13) xor data_in(9));
+    q(24) := not ((not d(8)) xor (not d(18)) xor (not d(31)) xor (not d(30)) xor (not d(28)) xor (not d(24)) xor data_in(2) xor data_in(15) xor data_in(14) xor data_in(12) xor data_in(8));
+
+    return q;
+  end f_update_crc32_d16;
+
+
+  function f_update_crc32_d8(d : std_logic_vector(31 downto 0); data_in : std_logic_vector(7 downto 0)) return std_logic_vector is
+    variable q : std_logic_vector(31 downto 0);
+  begin
+    q(7)  := not ((not d(31)) xor (not d(25)) xor data_in(7) xor data_in(1));
+    q(6)  := not ((not d(31)) xor (not d(30)) xor (not d(25)) xor (not d(24)) xor data_in(7) xor data_in(6) xor data_in(1) xor data_in(0));
+    q(5)  := not ((not d(31)) xor (not d(30)) xor (not d(29)) xor (not d(25)) xor (not d(24)) xor data_in(7) xor data_in(6) xor data_in(5) xor data_in(1) xor data_in(0));
+    q(4)  := not ((not d(30)) xor (not d(29)) xor (not d(28)) xor (not d(24)) xor data_in(6) xor data_in(5) xor data_in(4) xor data_in(0));
+    q(3)  := not ((not d(31)) xor (not d(29)) xor (not d(28)) xor (not d(27)) xor (not d(25)) xor data_in(7) xor data_in(5) xor data_in(4) xor data_in(3) xor data_in(1));
+    q(2)  := not ((not d(31)) xor (not d(30)) xor (not d(28)) xor (not d(27)) xor (not d(26)) xor (not d(25)) xor (not d(24)) xor data_in(7) xor data_in(6) xor data_in(4) xor data_in(3) xor data_in(2) xor data_in(1) xor data_in(0));
+    q(1)  := not ((not d(30)) xor (not d(29)) xor (not d(27)) xor (not d(26)) xor (not d(25)) xor (not d(24)) xor data_in(6) xor data_in(5) xor data_in(3) xor data_in(2) xor data_in(1) xor data_in(0));
+    q(0)  := not ((not d(31)) xor (not d(29)) xor (not d(28)) xor (not d(26)) xor (not d(24)) xor data_in(7) xor data_in(5) xor data_in(4) xor data_in(2) xor data_in(0));
+    q(15) := not ((not d(7)) xor (not d(31)) xor (not d(30)) xor (not d(28)) xor (not d(27)) xor data_in(7) xor data_in(6) xor data_in(4) xor data_in(3));
+    q(14) := not ((not d(6)) xor (not d(30)) xor (not d(29)) xor (not d(27)) xor (not d(26)) xor data_in(6) xor data_in(5) xor data_in(3) xor data_in(2));
+    q(13) := not ((not d(5)) xor (not d(31)) xor (not d(29)) xor (not d(28)) xor (not d(26)) xor data_in(7) xor data_in(5) xor data_in(4) xor data_in(2));
+    q(12) := not ((not d(4)) xor (not d(31)) xor (not d(30)) xor (not d(28)) xor (not d(27)) xor data_in(7) xor data_in(6) xor data_in(4) xor data_in(3));
+    q(11) := not ((not d(3)) xor (not d(31)) xor (not d(30)) xor (not d(29)) xor (not d(27)) xor (not d(26)) xor (not d(25)) xor data_in(7) xor data_in(6) xor data_in(5) xor data_in(3) xor data_in(2) xor data_in(1));
+    q(10) := not ((not d(2)) xor (not d(30)) xor (not d(29)) xor (not d(28)) xor (not d(26)) xor (not d(25)) xor (not d(24)) xor data_in(6) xor data_in(5) xor data_in(4) xor data_in(2) xor data_in(1) xor data_in(0));
+    q(9)  := not ((not d(1)) xor (not d(29)) xor (not d(28)) xor (not d(27)) xor (not d(25)) xor (not d(24)) xor data_in(5) xor data_in(4) xor data_in(3) xor data_in(1) xor data_in(0));
+    q(8)  := not ((not d(0)) xor (not d(28)) xor (not d(27)) xor (not d(26)) xor (not d(24)) xor data_in(4) xor data_in(3) xor data_in(2) xor data_in(0));
+    q(23) := not ((not d(15)) xor (not d(31)) xor (not d(27)) xor (not d(26)) xor data_in(7) xor data_in(3) xor data_in(2));
+    q(22) := not ((not d(14)) xor (not d(30)) xor (not d(26)) xor (not d(25)) xor data_in(6) xor data_in(2) xor data_in(1));
+    q(21) := not ((not d(13)) xor (not d(29)) xor (not d(25)) xor (not d(24)) xor data_in(5) xor data_in(1) xor data_in(0));
+    q(20) := not ((not d(12)) xor (not d(28)) xor (not d(24)) xor data_in(4) xor data_in(0));
+    q(19) := not ((not d(11)) xor (not d(27)) xor data_in(3));
+    q(18) := not ((not d(10)) xor (not d(26)) xor data_in(2));
+    q(17) := not ((not d(9)) xor (not d(31)) xor data_in(7));
+    q(16) := not ((not d(8)) xor (not d(31)) xor (not d(30)) xor (not d(25)) xor data_in(7) xor data_in(6) xor data_in(1));
+    q(31) := not ((not d(23)) xor (not d(30)) xor (not d(29)) xor (not d(24)) xor data_in(6) xor data_in(5) xor data_in(0));
+    q(30) := not ((not d(22)) xor (not d(29)) xor (not d(28)) xor data_in(5) xor data_in(4));
+    q(29) := not ((not d(21)) xor (not d(31)) xor (not d(28)) xor (not d(27)) xor (not d(25)) xor data_in(7) xor data_in(4) xor data_in(3) xor data_in(1));
+    q(28) := not ((not d(20)) xor (not d(30)) xor (not d(27)) xor (not d(26)) xor (not d(24)) xor data_in(6) xor data_in(3) xor data_in(2) xor data_in(0));
+    q(27) := not ((not d(19)) xor (not d(29)) xor (not d(26)) xor (not d(25)) xor data_in(5) xor data_in(2) xor data_in(1));
+    q(26) := not ((not d(18)) xor (not d(28)) xor (not d(25)) xor (not d(24)) xor data_in(4) xor data_in(1) xor data_in(0));
+    q(25) := not ((not d(17)) xor (not d(27)) xor (not d(24)) xor data_in(3) xor data_in(0));
+    q(24) := not ((not d(16)) xor (not d(26)) xor data_in(2));
+    return q;
+  end f_update_crc32_d8;
+end ep_crc32_pkg;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_leds_controller.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_leds_controller.vhd
new file mode 100644
index 000000000..28582fb52
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_leds_controller.vhd
@@ -0,0 +1,129 @@
+-------------------------------------------------------------------------------
+-- Title      : Endpoint LEDs controller
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_leds_controller.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 - 2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.endpoint_private_pkg.all;
+use work.gencores_pkg.all;
+
+entity ep_leds_controller is
+  
+  generic (
+    g_blink_period_log2 : integer := 21);
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    -- data valid (from PCS <> framers)
+    dvalid_tx_i : in std_logic;
+    dvalid_rx_i : in std_logic;
+
+    link_ok_i : in std_logic;
+
+    led_link_o : out std_logic;
+    led_act_o  : out std_logic
+    );  
+
+end ep_leds_controller;
+
+architecture rtl of ep_leds_controller is
+
+  type t_state is (INACTIVE, BLINKING);
+
+  signal cnt                    : unsigned(g_blink_period_log2-1 downto 0);
+  signal cnt_reset, cnt_expired : std_logic;
+  signal state                  : t_state;
+  signal led_act                : std_logic;
+  signal last_cycle_act         : std_logic;
+  signal txrx                   : std_logic;
+begin  -- rtl
+
+  led_link_o <= link_ok_i;
+
+  txrx <= dvalid_rx_i or dvalid_tx_i;
+
+  p_counter : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      
+      if(rst_n_i = '0' or cnt_reset = '1')then
+        cnt <= (others => '0');
+      else
+        cnt <= cnt + 1;
+        if((not cnt) = 0) then
+          cnt_expired <= '1';
+        else
+          cnt_expired <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_gen_act_led : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state     <= INACTIVE;
+        led_act   <= '0';
+        cnt_reset <= '0';
+      else
+        case state is
+          when INACTIVE =>
+            if(txrx = '1') then
+              state     <= BLINKING;
+              led_act   <= '1';
+              cnt_reset <= '1';
+            end if;
+          when BLINKING =>
+            cnt_reset <= '0';
+            if(cnt_expired = '1') then
+              led_act <= not led_act;
+              if(last_cycle_act = '0') then
+                led_act <= '0';
+                state   <= INACTIVE;
+              end if;
+              last_cycle_act <= '0';
+            else
+              if(txrx = '1') then
+                last_cycle_act <= '1';
+              end if;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  led_act_o <= led_act;
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_packet_filter.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_packet_filter.vhd
new file mode 100644
index 000000000..79b4c4cbd
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_packet_filter.vhd
@@ -0,0 +1,371 @@
+-------------------------------------------------------------------------------
+-- Title      : Programmable Packet Filter/Inspector
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_packet_filter.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2017-02-02
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: A simple packet inspection CPU, capable of classifying incoming
+-- packets to 8 different packet classes. The microcode format and programming
+-- constaints are described in detail in the Endpoint's manual.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011-2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1l.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+
+entity ep_packet_filter is
+
+  port (
+    clk_rx_i    : in std_logic;
+    clk_sys_i   : in std_logic;
+    rst_n_rx_i  : in std_logic;
+    rst_n_sys_i : in std_logic;
+
+    snk_fab_i : in  t_ep_internal_fabric;
+    src_fab_o : out t_ep_internal_fabric;
+
+    done_o   : out std_logic;
+    pclass_o : out std_logic_vector(7 downto 0);
+    drop_o   : out std_logic;
+
+    regs_i : in t_ep_out_registers
+    );
+
+end ep_packet_filter;
+
+architecture behavioral of ep_packet_filter is
+
+  constant c_PC_SIZE : integer := 6;
+
+  constant c_MODE_LOGIC   : std_logic := '1';
+  constant c_MODE_COMPARE : std_logic := '0';
+
+  type t_microcode_instruction is record
+    fin       : std_logic;
+    mode      : std_logic;
+    cmp_bit   : std_logic;
+    cmp_mask  : std_logic_vector(3 downto 0);
+    cmp_value : std_logic_vector(15 downto 0);
+    offset    : std_logic_vector(5 downto 0);
+    op        : std_logic_vector(2 downto 0);
+    op2       : std_logic_vector(2 downto 0);
+
+    rd : std_logic_vector(4 downto 0);
+    ra : std_logic_vector(4 downto 0);
+    rb : std_logic_vector(4 downto 0);
+    rc : std_logic_vector(4 downto 0);
+  end record;
+
+  function f_decode_insn
+    (ir           : std_logic_vector) return t_microcode_instruction is
+    variable insn : t_microcode_instruction;
+  begin
+    insn.fin            := ir(35);
+    insn.mode           := ir(34);
+    insn.cmp_bit        := ir(33);
+    insn.cmp_mask       := ir(32 downto 29);
+    insn.cmp_value      := ir(28 downto 13);
+    insn.offset         := ir(12 downto 7);
+    insn.rd(3 downto 0) := ir(6 downto 3);
+    insn.op             := ir(2 downto 0);
+    insn.rd(4)          := ir(34) and ir(7);
+    insn.ra             := ir(12 downto 8);
+    insn.rb             := ir(17 downto 13);
+    insn.rc             := ir(22 downto 18);
+    insn.op2            := ir(25 downto 23);
+    return insn;
+  end f_decode_insn;
+
+  function f_eval
+    (
+      a, b : std_logic;
+      op   : std_logic_vector
+      ) return std_logic is
+    variable r    : std_logic;
+    variable op_t : std_logic_vector(2 downto 0);
+  begin
+    op_t := op;
+    case op_t is
+      when "000"  => r := a and b;
+      when "100"  => r := a nand b;
+      when "001"  => r := a or b;
+      when "101"  => r := a nor b;
+      when "010"  => r := a xor b;
+      when "110"  => r := a xnor b;
+      when "011"  => r := a;
+      when "111"  => r := not a;
+      when others => null;
+    end case;
+    return r;
+  end f_eval;
+
+  function f_pick_reg(regs : std_logic_vector; index : std_logic_vector)return std_logic is
+    variable idx_int : integer;
+  begin
+    idx_int := to_integer(unsigned(index));
+    return regs(idx_int);
+  end f_pick_reg;
+
+
+
+  signal pc              : unsigned(c_PC_SIZE-1 downto 0);
+  signal ir, ir_d        : std_logic_vector(35 downto 0);
+  signal insn, insn_d    : t_microcode_instruction;
+  signal insn_predecoded : t_microcode_instruction;
+
+  signal done_int : std_logic;
+  signal regs     : std_logic_vector(31 downto 0);
+
+  signal result_cmp : std_logic;
+  signal mask       : std_logic_vector(15 downto 0);
+
+  signal ra, rb, rc, result1, result2, rd : std_logic;
+
+  signal pmem_rdata : std_logic_vector(15 downto 0);
+
+  signal mm_write           : std_logic;
+  signal mm_rdata, mm_wdata : std_logic_vector(35 downto 0);
+
+  type t_state is (WAIT_FRAME, PROCESS_FRAME, GEN_OUTPUT);
+
+  signal stage1, stage2, stage3 : std_logic;
+  signal r_pfcr1_mm_data_lsb : std_logic_vector(11 downto 0);
+
+  signal pfcr0_enable_rxclk : std_logic;
+
+begin  -- behavioral
+
+  U_sync_pfcr0_enable : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_rx_i,
+      rst_n_i  => '1',
+      data_i   => regs_i.pfcr0_enable_o,
+      synced_o => pfcr0_enable_rxclk,
+      npulse_o => open,
+      ppulse_o => open);
+
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(regs_i.pfcr1_mm_data_lsb_wr_o = '1') then
+        r_pfcr1_mm_data_lsb <= regs_i.pfcr1_mm_data_lsb_o;
+      end if;
+    end if;
+  end process;
+
+
+  mm_write <= not regs_i.pfcr0_enable_o and regs_i.pfcr0_mm_write_o and regs_i.pfcr0_mm_write_wr_o;
+  mm_wdata <= regs_i.pfcr0_mm_data_msb_o & r_pfcr1_mm_data_lsb;
+
+  U_microcode_ram : generic_dpram
+    generic map (
+      g_data_width => 36,
+      g_size       => 2**c_PC_SIZE,
+      g_dual_clock => true)
+    port map (
+      rst_n_i => rst_n_sys_i,
+      clka_i  => clk_rx_i,
+      bwea_i  => "00000",
+      wea_i   => '0',
+      aa_i    => std_logic_vector(pc),
+      da_i    => x"000000000",
+      qa_o    => mm_rdata,
+      clkb_i  => clk_sys_i,
+      bweb_i  => "11111",
+      web_i   => mm_write,
+      ab_i    => regs_i.pfcr0_mm_addr_o,
+      db_i    => mm_wdata
+      );
+
+
+
+  U_backlog_ram : generic_dpram
+    generic map (
+      g_data_width       => 16,
+      g_size             => 2**c_PC_SIZE,
+      g_with_byte_enable => false,
+      g_dual_clock       => false)
+    port map (
+      rst_n_i => rst_n_rx_i,
+      clka_i  => clk_rx_i,
+      bwea_i  => "11",
+      wea_i   => snk_fab_i.dvalid,
+      aa_i    => std_logic_vector(pc),
+      da_i    => snk_fab_i.data,
+      qa_o    => open,
+      clkb_i  => clk_rx_i,
+      bweb_i  => "00",
+      web_i   => '0',
+      ab_i    => insn_predecoded.offset,
+      db_i    => x"0000",
+      qb_o    => pmem_rdata);
+
+  insn_predecoded <= f_decode_insn(mm_rdata);
+
+  src_fab_o <= snk_fab_i;
+
+  p_pc_counter : process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if rst_n_rx_i = '0' or snk_fab_i.eof = '1' or snk_fab_i.error = '1' or done_int = '1' then
+        pc     <= (others => '0');
+        stage1 <= '0';
+      elsif(snk_fab_i.dvalid = '1') then
+        pc     <= pc + 1;
+        stage1 <= '1';
+      else
+        stage1 <= '0';
+      end if;
+    end if;
+  end process;
+
+  p_stage2 : process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if rst_n_rx_i = '0' or done_int = '1' or snk_fab_i.error = '1' then
+        stage2 <= '0';
+        ir     <= (others => '0');
+      else
+        stage2 <= stage1;
+        ir     <= mm_rdata;
+      end if;
+    end if;
+  end process;
+
+  p_gen_mask : process(insn)
+  begin
+    if(insn.cmp_bit = '0') then
+      mask <= (3 downto 0   => insn.cmp_mask(0),
+               7 downto 4   => insn.cmp_mask(1),
+               11 downto 8  => insn.cmp_mask(2),
+               15 downto 12 => insn.cmp_mask(3));
+    else
+      case insn.cmp_mask is
+        when x"0"   => mask <= x"0001";
+        when x"1"   => mask <= x"0002";
+        when x"2"   => mask <= x"0004";
+        when x"3"   => mask <= x"0008";
+        when x"4"   => mask <= x"0010";
+        when x"5"   => mask <= x"0020";
+        when x"6"   => mask <= x"0040";
+        when x"7"   => mask <= x"0080";
+        when x"8"   => mask <= x"0100";
+        when x"9"   => mask <= x"0200";
+        when x"a"   => mask <= x"0400";
+        when x"b"   => mask <= x"0800";
+        when x"c"   => mask <= x"1000";
+        when x"d"   => mask <= x"2000";
+        when x"e"   => mask <= x"4000";
+        when x"f"   => mask <= x"8000";
+        when others => mask <= (others => 'X');
+      end case;
+    end if;
+  end process;
+
+  p_compare : process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if stage2 = '1' then
+        stage3 <= '1';
+        ir_d   <= ir;
+        if (((pmem_rdata and mask) = insn.cmp_value)) then
+          result_cmp <= '1';
+        else
+          result_cmp <= '0';
+        end if;
+
+      else
+        stage3 <= '0';
+      end if;
+    end if;
+  end process;
+
+  insn <= f_decode_insn(ir);
+  insn_d <= f_decode_insn(ir_d);
+  ra     <= f_pick_reg(regs, insn_d.ra) when insn_d.mode = c_MODE_LOGIC else result_cmp;
+  rb     <= f_pick_reg(regs, insn_d.rb) when insn_d.mode = c_MODE_LOGIC else f_pick_reg(regs, insn_d.rd);
+  rc     <= f_pick_reg(regs, insn_d.rc);
+
+  result1 <= f_eval(ra, rb, insn_d.op);
+  result2 <= f_eval(result1, rc, insn_d.op2);
+
+  rd <= result2 when insn_d.mode = c_MODE_LOGIC else result1;
+
+
+  p_execute : process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if rst_n_rx_i = '0' or snk_fab_i.eof = '1' or snk_fab_i.error = '1' or done_int = '1' then
+        regs <= (others => '0');
+      else
+        if(stage3 = '1') then
+          regs(to_integer(unsigned(insn_d.rd))) <= rd;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_gen_status : process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if (rst_n_rx_i = '0' or snk_fab_i.sof = '1') then
+        done_int <= '0';
+        drop_o   <= '0';
+      else
+        if(pfcr0_enable_rxclk = '0') then
+          done_int <= '0';
+          drop_o   <= '0';
+          pclass_o <= (others => '0');
+        elsif( (stage3 = '1' and insn_d.fin = '1') or
+               ((snk_fab_i.error = '1' or snk_fab_i.eof = '1') and done_int = '0') ) then
+          done_int <= '1';
+          pclass_o <= regs(31 downto 24);
+          drop_o   <= regs(23);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  U_Sync_Done : gc_pulse_synchronizer
+    port map (
+      clk_in_i  => clk_rx_i,
+      clk_out_i => clk_sys_i,
+      rst_n_i   => rst_n_rx_i,
+      d_p_i     => done_int,
+      q_p_o     => done_o);
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
new file mode 100644
index 000000000..f94b29b11
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
@@ -0,0 +1,627 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Endpoint 1000base-X TBI PCS register block
+---------------------------------------------------------------------------------------
+-- File           : ep_pcs_tbi_mdio_wb.vhd
+-- Author         : auto-generated by wbgen2 from pcs_regs.wb
+-- Created        : Wed Aug 16 22:43:42 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ep_pcs_tbi_mdio_wb is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(4 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    tx_clk_i                                 : in     std_logic;
+    rx_clk_i                                 : in     std_logic;
+-- Port for BIT field: 'Unidirectional Enable' in reg: 'MDIO Control Register'
+    mdio_mcr_uni_en_o                        : out    std_logic;
+-- Port for MONOSTABLE field: 'Restart Auto-Negotiation' in reg: 'MDIO Control Register'
+    mdio_mcr_anrestart_o                     : out    std_logic;
+-- Port for BIT field: 'Power Down' in reg: 'MDIO Control Register'
+    mdio_mcr_pdown_o                         : out    std_logic;
+-- Port for BIT field: 'Auto-Negotiation Enable' in reg: 'MDIO Control Register'
+    mdio_mcr_anenable_o                      : out    std_logic;
+-- Port for BIT field: 'Loopback' in reg: 'MDIO Control Register'
+    mdio_mcr_loopback_o                      : out    std_logic;
+-- Port for MONOSTABLE field: 'Reset' in reg: 'MDIO Control Register'
+    mdio_mcr_reset_o                         : out    std_logic;
+-- Port for BIT field: 'Link Status' in reg: 'MDIO Status Register'
+    mdio_msr_lstatus_i                       : in     std_logic;
+    lstat_read_notify_o                      : out    std_logic;
+-- Port for BIT field: 'Remote Fault' in reg: 'MDIO Status Register'
+    mdio_msr_rfault_i                        : in     std_logic;
+-- Port for BIT field: 'Auto-Negotiation Complete' in reg: 'MDIO Status Register'
+    mdio_msr_anegcomplete_i                  : in     std_logic;
+-- Port for std_logic_vector field: 'Pause' in reg: 'MDIO Auto-Negotiation Advertisement Register'
+    mdio_advertise_pause_o                   : out    std_logic_vector(1 downto 0);
+-- Port for std_logic_vector field: 'Remote Fault' in reg: 'MDIO Auto-Negotiation Advertisement Register'
+    mdio_advertise_rfault_o                  : out    std_logic_vector(1 downto 0);
+-- Port for BIT field: 'Full Duplex' in reg: 'MDIO Auto-Negotiation Link Partner Ability Register'
+    mdio_lpa_full_i                          : in     std_logic;
+-- Port for BIT field: 'Half Duplex' in reg: 'MDIO Auto-Negotiation Link Partner Ability Register'
+    mdio_lpa_half_i                          : in     std_logic;
+-- Port for std_logic_vector field: 'Pause' in reg: 'MDIO Auto-Negotiation Link Partner Ability Register'
+    mdio_lpa_pause_i                         : in     std_logic_vector(1 downto 0);
+-- Port for std_logic_vector field: 'Remote Fault' in reg: 'MDIO Auto-Negotiation Link Partner Ability Register'
+    mdio_lpa_rfault_i                        : in     std_logic_vector(1 downto 0);
+-- Port for BIT field: 'Acknowledge' in reg: 'MDIO Auto-Negotiation Link Partner Ability Register'
+    mdio_lpa_lpack_i                         : in     std_logic;
+-- Port for BIT field: 'Next Page' in reg: 'MDIO Auto-Negotiation Link Partner Ability Register'
+    mdio_lpa_npage_i                         : in     std_logic;
+-- Port for asynchronous (clock: tx_clk_i) BIT field: 'TX Calibration Pattern' in reg: 'WhiteRabbit-specific Configuration Register'
+    mdio_wr_spec_tx_cal_o                    : out    std_logic;
+-- Port for asynchronous (clock: rx_clk_i) BIT field: 'Calibration Pattern RX Status' in reg: 'WhiteRabbit-specific Configuration Register'
+    mdio_wr_spec_rx_cal_stat_i               : in     std_logic;
+-- Port for asynchronous (clock: rx_clk_i) MONOSTABLE field: 'Reset calibration counter' in reg: 'WhiteRabbit-specific Configuration Register'
+    mdio_wr_spec_cal_crst_o                  : out    std_logic;
+-- Port for asynchronous (clock: rx_clk_i) std_logic_vector field: 'GTP RX Bitslide' in reg: 'WhiteRabbit-specific Configuration Register'
+    mdio_wr_spec_bslide_i                    : in     std_logic_vector(4 downto 0);
+-- Port for std_logic_vector field: 'Loopback - detailed' in reg: 'MDIO Extended Control Register'
+    mdio_ectrl_lpbck_vec_o                   : out    std_logic_vector(2 downto 0);
+-- Port for BIT field: 'SFP TX Fault Status' in reg: 'MDIO Extended Control Register'
+    mdio_ectrl_sfp_tx_fault_i                : in     std_logic;
+-- Port for BIT field: 'SFP LOS' in reg: 'MDIO Extended Control Register'
+    mdio_ectrl_sfp_loss_i                    : in     std_logic;
+-- Port for BIT field: 'SFP TX Disable' in reg: 'MDIO Extended Control Register'
+    mdio_ectrl_sfp_tx_disable_o              : out    std_logic;
+-- Port for std_logic_vector field: 'tx_prbs_sel' in reg: 'MDIO Extended Control Register'
+    mdio_ectrl_tx_prbs_sel_o                 : out    std_logic_vector(2 downto 0)
+  );
+end ep_pcs_tbi_mdio_wb;
+
+architecture syn of ep_pcs_tbi_mdio_wb is
+
+signal mdio_mcr_uni_en_int                      : std_logic      ;
+signal mdio_mcr_anrestart_dly0                  : std_logic      ;
+signal mdio_mcr_anrestart_int                   : std_logic      ;
+signal mdio_mcr_pdown_int                       : std_logic      ;
+signal mdio_mcr_anenable_int                    : std_logic      ;
+signal mdio_mcr_loopback_int                    : std_logic      ;
+signal mdio_mcr_reset_dly0                      : std_logic      ;
+signal mdio_mcr_reset_int                       : std_logic      ;
+signal mdio_advertise_pause_int                 : std_logic_vector(1 downto 0);
+signal mdio_advertise_rfault_int                : std_logic_vector(1 downto 0);
+signal mdio_wr_spec_tx_cal_int                  : std_logic      ;
+signal mdio_wr_spec_tx_cal_sync0                : std_logic      ;
+signal mdio_wr_spec_tx_cal_sync1                : std_logic      ;
+signal mdio_wr_spec_rx_cal_stat_sync0           : std_logic      ;
+signal mdio_wr_spec_rx_cal_stat_sync1           : std_logic      ;
+signal mdio_wr_spec_cal_crst_int                : std_logic      ;
+signal mdio_wr_spec_cal_crst_int_delay          : std_logic      ;
+signal mdio_wr_spec_cal_crst_sync0              : std_logic      ;
+signal mdio_wr_spec_cal_crst_sync1              : std_logic      ;
+signal mdio_wr_spec_cal_crst_sync2              : std_logic      ;
+signal mdio_wr_spec_bslide_int                  : std_logic_vector(4 downto 0);
+signal mdio_wr_spec_bslide_lwb                  : std_logic      ;
+signal mdio_wr_spec_bslide_lwb_delay            : std_logic      ;
+signal mdio_wr_spec_bslide_lwb_in_progress      : std_logic      ;
+signal mdio_wr_spec_bslide_lwb_s0               : std_logic      ;
+signal mdio_wr_spec_bslide_lwb_s1               : std_logic      ;
+signal mdio_wr_spec_bslide_lwb_s2               : std_logic      ;
+signal mdio_ectrl_lpbck_vec_int                 : std_logic_vector(2 downto 0);
+signal mdio_ectrl_sfp_tx_disable_int            : std_logic      ;
+signal mdio_ectrl_tx_prbs_sel_int               : std_logic_vector(2 downto 0);
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal rwaddr_reg                               : std_logic_vector(4 downto 0);
+signal ack_in_progress                          : std_logic      ;
+
+begin
+-- Some internal signals assignments
+  wrdata_reg <= wb_dat_i;
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      mdio_mcr_uni_en_int <= '0';
+      mdio_mcr_anrestart_int <= '0';
+      mdio_mcr_pdown_int <= '0';
+      mdio_mcr_anenable_int <= '0';
+      mdio_mcr_loopback_int <= '0';
+      mdio_mcr_reset_int <= '0';
+      lstat_read_notify_o <= '0';
+      mdio_advertise_pause_int <= "00";
+      mdio_advertise_rfault_int <= "00";
+      mdio_wr_spec_tx_cal_int <= '0';
+      mdio_wr_spec_cal_crst_int <= '0';
+      mdio_wr_spec_cal_crst_int_delay <= '0';
+      mdio_wr_spec_bslide_lwb <= '0';
+      mdio_wr_spec_bslide_lwb_delay <= '0';
+      mdio_wr_spec_bslide_lwb_in_progress <= '0';
+      mdio_ectrl_lpbck_vec_int <= "000";
+      mdio_ectrl_sfp_tx_disable_int <= '0';
+      mdio_ectrl_tx_prbs_sel_int <= "000";
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          mdio_mcr_anrestart_int <= '0';
+          mdio_mcr_reset_int <= '0';
+          lstat_read_notify_o <= '0';
+          ack_in_progress <= '0';
+        else
+          mdio_wr_spec_cal_crst_int <= mdio_wr_spec_cal_crst_int_delay;
+          mdio_wr_spec_cal_crst_int_delay <= '0';
+          mdio_wr_spec_bslide_lwb <= mdio_wr_spec_bslide_lwb_delay;
+          mdio_wr_spec_bslide_lwb_delay <= '0';
+          if ((ack_sreg(1) = '1') and (mdio_wr_spec_bslide_lwb_in_progress = '1')) then
+            rddata_reg(8 downto 4) <= mdio_wr_spec_bslide_int;
+            mdio_wr_spec_bslide_lwb_in_progress <= '0';
+          end if;
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(4 downto 0) is
+          when "00000" => 
+            if (wb_we_i = '1') then
+              mdio_mcr_uni_en_int <= wrdata_reg(5);
+              mdio_mcr_anrestart_int <= wrdata_reg(9);
+              mdio_mcr_pdown_int <= wrdata_reg(11);
+              mdio_mcr_anenable_int <= wrdata_reg(12);
+              mdio_mcr_loopback_int <= wrdata_reg(14);
+              mdio_mcr_reset_int <= wrdata_reg(15);
+            end if;
+            rddata_reg(4 downto 0) <= "00000";
+            rddata_reg(5) <= mdio_mcr_uni_en_int;
+            rddata_reg(6) <= '1';
+            rddata_reg(7) <= '0';
+            rddata_reg(8) <= '1';
+            rddata_reg(9) <= '0';
+            rddata_reg(10) <= '0';
+            rddata_reg(11) <= mdio_mcr_pdown_int;
+            rddata_reg(12) <= mdio_mcr_anenable_int;
+            rddata_reg(13) <= '0';
+            rddata_reg(14) <= mdio_mcr_loopback_int;
+            rddata_reg(15) <= '0';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(2) <= '1';
+            ack_in_progress <= '1';
+          when "00001" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(0) <= '0';
+            rddata_reg(1) <= '0';
+            rddata_reg(2) <= mdio_msr_lstatus_i;
+            lstat_read_notify_o <= '1';
+            rddata_reg(3) <= '1';
+            rddata_reg(4) <= mdio_msr_rfault_i;
+            rddata_reg(5) <= mdio_msr_anegcomplete_i;
+            rddata_reg(6) <= '0';
+            rddata_reg(7) <= '1';
+            rddata_reg(8) <= '1';
+            rddata_reg(9) <= '0';
+            rddata_reg(10) <= '0';
+            rddata_reg(11) <= '0';
+            rddata_reg(12) <= '0';
+            rddata_reg(13) <= '0';
+            rddata_reg(14) <= '0';
+            rddata_reg(15) <= '0';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00010" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(15 downto 0) <= "0000000000000000";
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(3 downto 0) <= "0000";
+            rddata_reg(9 downto 4) <= "000000";
+            rddata_reg(15 downto 10) <= "000000";
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00100" => 
+            if (wb_we_i = '1') then
+              mdio_advertise_pause_int <= wrdata_reg(8 downto 7);
+              mdio_advertise_rfault_int <= wrdata_reg(13 downto 12);
+            end if;
+            rddata_reg(4 downto 0) <= "00000";
+            rddata_reg(5) <= '1';
+            rddata_reg(6) <= '0';
+            rddata_reg(8 downto 7) <= mdio_advertise_pause_int;
+            rddata_reg(11 downto 9) <= "000";
+            rddata_reg(13 downto 12) <= mdio_advertise_rfault_int;
+            rddata_reg(14) <= '0';
+            rddata_reg(15) <= '0';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(4 downto 0) <= "00000";
+            rddata_reg(5) <= mdio_lpa_full_i;
+            rddata_reg(6) <= mdio_lpa_half_i;
+            rddata_reg(8 downto 7) <= mdio_lpa_pause_i;
+            rddata_reg(11 downto 9) <= "000";
+            rddata_reg(13 downto 12) <= mdio_lpa_rfault_i;
+            rddata_reg(14) <= mdio_lpa_lpack_i;
+            rddata_reg(15) <= mdio_lpa_npage_i;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00110" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(0) <= '0';
+            rddata_reg(1) <= '0';
+            rddata_reg(2) <= '0';
+            rddata_reg(15 downto 3) <= "0000000000000";
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01111" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(11 downto 0) <= "000000000000";
+            rddata_reg(12) <= '0';
+            rddata_reg(13) <= '0';
+            rddata_reg(14) <= '0';
+            rddata_reg(15) <= '1';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10000" => 
+            if (wb_we_i = '1') then
+              mdio_wr_spec_tx_cal_int <= wrdata_reg(0);
+              mdio_wr_spec_cal_crst_int <= wrdata_reg(2);
+              mdio_wr_spec_cal_crst_int_delay <= wrdata_reg(2);
+            end if;
+            rddata_reg(0) <= mdio_wr_spec_tx_cal_int;
+            rddata_reg(1) <= mdio_wr_spec_rx_cal_stat_sync1;
+            rddata_reg(2) <= '0';
+            if (wb_we_i = '0') then
+              mdio_wr_spec_bslide_lwb <= '1';
+              mdio_wr_spec_bslide_lwb_delay <= '1';
+              mdio_wr_spec_bslide_lwb_in_progress <= '1';
+            end if;
+            rddata_reg(3) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(5) <= '1';
+            ack_in_progress <= '1';
+          when "10001" => 
+            if (wb_we_i = '1') then
+              mdio_ectrl_lpbck_vec_int <= wrdata_reg(2 downto 0);
+              mdio_ectrl_sfp_tx_disable_int <= wrdata_reg(5);
+              mdio_ectrl_tx_prbs_sel_int <= wrdata_reg(10 downto 8);
+            end if;
+            rddata_reg(2 downto 0) <= mdio_ectrl_lpbck_vec_int;
+            rddata_reg(3) <= mdio_ectrl_sfp_tx_fault_i;
+            rddata_reg(4) <= mdio_ectrl_sfp_loss_i;
+            rddata_reg(5) <= mdio_ectrl_sfp_tx_disable_int;
+            rddata_reg(10 downto 8) <= mdio_ectrl_tx_prbs_sel_int;
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- Unidirectional Enable
+  mdio_mcr_uni_en_o <= mdio_mcr_uni_en_int;
+-- Restart Auto-Negotiation
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      mdio_mcr_anrestart_dly0 <= '0';
+      mdio_mcr_anrestart_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      mdio_mcr_anrestart_dly0 <= mdio_mcr_anrestart_int;
+      mdio_mcr_anrestart_o <= mdio_mcr_anrestart_int and (not mdio_mcr_anrestart_dly0);
+    end if;
+  end process;
+  
+  
+-- Power Down
+  mdio_mcr_pdown_o <= mdio_mcr_pdown_int;
+-- Auto-Negotiation Enable
+  mdio_mcr_anenable_o <= mdio_mcr_anenable_int;
+-- Loopback
+  mdio_mcr_loopback_o <= mdio_mcr_loopback_int;
+-- Reset
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      mdio_mcr_reset_dly0 <= '0';
+      mdio_mcr_reset_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      mdio_mcr_reset_dly0 <= mdio_mcr_reset_int;
+      mdio_mcr_reset_o <= mdio_mcr_reset_int and (not mdio_mcr_reset_dly0);
+    end if;
+  end process;
+  
+  
+-- Link Status
+-- Remote Fault
+-- Auto-Negotiation Complete
+-- Pause
+  mdio_advertise_pause_o <= mdio_advertise_pause_int;
+-- Remote Fault
+  mdio_advertise_rfault_o <= mdio_advertise_rfault_int;
+-- Full Duplex
+-- Half Duplex
+-- Pause
+-- Remote Fault
+-- Acknowledge
+-- Next Page
+-- TX Calibration Pattern
+-- synchronizer chain for field : TX Calibration Pattern (type RW/RO, clk_sys_i <-> tx_clk_i)
+  process (tx_clk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      mdio_wr_spec_tx_cal_o <= '0';
+      mdio_wr_spec_tx_cal_sync0 <= '0';
+      mdio_wr_spec_tx_cal_sync1 <= '0';
+    elsif rising_edge(tx_clk_i) then
+      mdio_wr_spec_tx_cal_sync0 <= mdio_wr_spec_tx_cal_int;
+      mdio_wr_spec_tx_cal_sync1 <= mdio_wr_spec_tx_cal_sync0;
+      mdio_wr_spec_tx_cal_o <= mdio_wr_spec_tx_cal_sync1;
+    end if;
+  end process;
+  
+  
+-- Calibration Pattern RX Status
+-- synchronizer chain for field : Calibration Pattern RX Status (type RO/WO, rx_clk_i -> clk_sys_i)
+  process (rx_clk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      mdio_wr_spec_rx_cal_stat_sync0 <= '0';
+      mdio_wr_spec_rx_cal_stat_sync1 <= '0';
+    elsif rising_edge(rx_clk_i) then
+      mdio_wr_spec_rx_cal_stat_sync0 <= mdio_wr_spec_rx_cal_stat_i;
+      mdio_wr_spec_rx_cal_stat_sync1 <= mdio_wr_spec_rx_cal_stat_sync0;
+    end if;
+  end process;
+  
+  
+-- Reset calibration counter
+  process (rx_clk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      mdio_wr_spec_cal_crst_o <= '0';
+      mdio_wr_spec_cal_crst_sync0 <= '0';
+      mdio_wr_spec_cal_crst_sync1 <= '0';
+      mdio_wr_spec_cal_crst_sync2 <= '0';
+    elsif rising_edge(rx_clk_i) then
+      mdio_wr_spec_cal_crst_sync0 <= mdio_wr_spec_cal_crst_int;
+      mdio_wr_spec_cal_crst_sync1 <= mdio_wr_spec_cal_crst_sync0;
+      mdio_wr_spec_cal_crst_sync2 <= mdio_wr_spec_cal_crst_sync1;
+      mdio_wr_spec_cal_crst_o <= mdio_wr_spec_cal_crst_sync2 and (not mdio_wr_spec_cal_crst_sync1);
+    end if;
+  end process;
+  
+  
+-- GTP RX Bitslide
+-- asynchronous std_logic_vector register : GTP RX Bitslide (type RO/WO, rx_clk_i <-> clk_sys_i)
+  process (rx_clk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      mdio_wr_spec_bslide_lwb_s0 <= '0';
+      mdio_wr_spec_bslide_lwb_s1 <= '0';
+      mdio_wr_spec_bslide_lwb_s2 <= '0';
+      mdio_wr_spec_bslide_int <= "00000";
+    elsif rising_edge(rx_clk_i) then
+      mdio_wr_spec_bslide_lwb_s0 <= mdio_wr_spec_bslide_lwb;
+      mdio_wr_spec_bslide_lwb_s1 <= mdio_wr_spec_bslide_lwb_s0;
+      mdio_wr_spec_bslide_lwb_s2 <= mdio_wr_spec_bslide_lwb_s1;
+      if ((mdio_wr_spec_bslide_lwb_s1 = '1') and (mdio_wr_spec_bslide_lwb_s2 = '0')) then
+        mdio_wr_spec_bslide_int <= mdio_wr_spec_bslide_i;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Loopback - detailed
+  mdio_ectrl_lpbck_vec_o <= mdio_ectrl_lpbck_vec_int;
+-- SFP TX Fault Status
+-- SFP LOS
+-- SFP TX Disable
+  mdio_ectrl_sfp_tx_disable_o <= mdio_ectrl_sfp_tx_disable_int;
+-- tx_prbs_sel
+  mdio_ectrl_tx_prbs_sel_o <= mdio_ectrl_tx_prbs_sel_int;
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_registers_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_registers_pkg.vhd
new file mode 100644
index 000000000..9f5983d51
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_registers_pkg.vhd
@@ -0,0 +1,261 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR switch endpoint controller
+---------------------------------------------------------------------------------------
+-- File           : ep_registers_pkg.vhd
+-- Author         : auto-generated by wbgen2 from ep_wishbone_controller.wb
+-- Created        : Wed Aug 16 22:43:41 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package ep_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_ep_in_registers is record
+    ecr_feat_vlan_i                          : std_logic;
+    ecr_feat_dmtd_i                          : std_logic;
+    ecr_feat_ptp_i                           : std_logic;
+    ecr_feat_dpi_i                           : std_logic;
+    tscr_cs_done_i                           : std_logic;
+    tscr_rx_cal_result_i                     : std_logic;
+    tcar_pcp_map_i                           : std_logic_vector(23 downto 0);
+    mdio_asr_rdata_i                         : std_logic_vector(15 downto 0);
+    mdio_asr_ready_i                         : std_logic;
+    dsr_lstatus_i                            : std_logic;
+    dsr_lact_i                               : std_logic;
+    dmcr_en_i                                : std_logic;
+    dmcr_n_avg_i                             : std_logic_vector(11 downto 0);
+    dmsr_ps_val_i                            : std_logic_vector(23 downto 0);
+    dmsr_ps_rdy_i                            : std_logic;
+    inj_ctrl_pic_conf_ifg_i                  : std_logic_vector(15 downto 0);
+    inj_ctrl_pic_conf_sel_i                  : std_logic_vector(2 downto 0);
+    inj_ctrl_pic_conf_valid_i                : std_logic;
+    inj_ctrl_pic_mode_id_i                   : std_logic_vector(2 downto 0);
+    inj_ctrl_pic_mode_valid_i                : std_logic;
+    inj_ctrl_pic_ena_i                       : std_logic;
+    end record;
+  
+  constant c_ep_in_registers_init_value: t_ep_in_registers := (
+    ecr_feat_vlan_i => '0',
+    ecr_feat_dmtd_i => '0',
+    ecr_feat_ptp_i => '0',
+    ecr_feat_dpi_i => '0',
+    tscr_cs_done_i => '0',
+    tscr_rx_cal_result_i => '0',
+    tcar_pcp_map_i => (others => '0'),
+    mdio_asr_rdata_i => (others => '0'),
+    mdio_asr_ready_i => '0',
+    dsr_lstatus_i => '0',
+    dsr_lact_i => '0',
+    dmcr_en_i => '0',
+    dmcr_n_avg_i => (others => '0'),
+    dmsr_ps_val_i => (others => '0'),
+    dmsr_ps_rdy_i => '0',
+    inj_ctrl_pic_conf_ifg_i => (others => '0'),
+    inj_ctrl_pic_conf_sel_i => (others => '0'),
+    inj_ctrl_pic_conf_valid_i => '0',
+    inj_ctrl_pic_mode_id_i => (others => '0'),
+    inj_ctrl_pic_mode_valid_i => '0',
+    inj_ctrl_pic_ena_i => '0'
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_ep_out_registers is record
+      ecr_portid_o                             : std_logic_vector(4 downto 0);
+      ecr_rst_cnt_o                            : std_logic;
+      ecr_tx_en_o                              : std_logic;
+      ecr_rx_en_o                              : std_logic;
+      tscr_en_txts_o                           : std_logic;
+      tscr_en_rxts_o                           : std_logic;
+      tscr_cs_start_o                          : std_logic;
+      tscr_rx_cal_start_o                      : std_logic;
+      rfcr_a_runt_o                            : std_logic;
+      rfcr_a_giant_o                           : std_logic;
+      rfcr_a_hp_o                              : std_logic;
+      rfcr_keep_crc_o                          : std_logic;
+      rfcr_hpap_o                              : std_logic_vector(7 downto 0);
+      rfcr_mru_o                               : std_logic_vector(13 downto 0);
+      vcr0_qmode_o                             : std_logic_vector(1 downto 0);
+      vcr0_fix_prio_o                          : std_logic;
+      vcr0_prio_val_o                          : std_logic_vector(2 downto 0);
+      vcr0_pvid_o                              : std_logic_vector(11 downto 0);
+      vcr1_offset_o                            : std_logic_vector(9 downto 0);
+      vcr1_offset_wr_o                         : std_logic;
+      vcr1_data_o                              : std_logic_vector(17 downto 0);
+      vcr1_data_wr_o                           : std_logic;
+      pfcr0_mm_addr_o                          : std_logic_vector(5 downto 0);
+      pfcr0_mm_addr_wr_o                       : std_logic;
+      pfcr0_mm_write_o                         : std_logic;
+      pfcr0_mm_write_wr_o                      : std_logic;
+      pfcr0_enable_o                           : std_logic;
+      pfcr0_mm_data_msb_o                      : std_logic_vector(23 downto 0);
+      pfcr0_mm_data_msb_wr_o                   : std_logic;
+      pfcr1_mm_data_lsb_o                      : std_logic_vector(11 downto 0);
+      pfcr1_mm_data_lsb_wr_o                   : std_logic;
+      tcar_pcp_map_o                           : std_logic_vector(23 downto 0);
+      tcar_pcp_map_load_o                      : std_logic;
+      fcr_rxpause_o                            : std_logic;
+      fcr_txpause_o                            : std_logic;
+      fcr_rxpause_802_1q_o                     : std_logic;
+      fcr_txpause_802_1q_o                     : std_logic;
+      fcr_tx_thr_o                             : std_logic_vector(7 downto 0);
+      fcr_tx_quanta_o                          : std_logic_vector(15 downto 0);
+      mach_o                                   : std_logic_vector(15 downto 0);
+      macl_o                                   : std_logic_vector(31 downto 0);
+      mdio_cr_data_o                           : std_logic_vector(15 downto 0);
+      mdio_cr_data_wr_o                        : std_logic;
+      mdio_cr_addr_o                           : std_logic_vector(7 downto 0);
+      mdio_cr_rw_o                             : std_logic;
+      mdio_asr_phyad_o                         : std_logic_vector(7 downto 0);
+      dsr_lact_o                               : std_logic;
+      dsr_lact_load_o                          : std_logic;
+      dmcr_en_o                                : std_logic;
+      dmcr_en_load_o                           : std_logic;
+      dmcr_n_avg_o                             : std_logic_vector(11 downto 0);
+      dmcr_n_avg_load_o                        : std_logic;
+      dmsr_ps_rdy_o                            : std_logic;
+      dmsr_ps_rdy_load_o                       : std_logic;
+      inj_ctrl_pic_conf_ifg_o                  : std_logic_vector(15 downto 0);
+      inj_ctrl_pic_conf_ifg_load_o             : std_logic;
+      inj_ctrl_pic_conf_sel_o                  : std_logic_vector(2 downto 0);
+      inj_ctrl_pic_conf_sel_load_o             : std_logic;
+      inj_ctrl_pic_conf_valid_o                : std_logic;
+      inj_ctrl_pic_conf_valid_load_o           : std_logic;
+      inj_ctrl_pic_mode_id_o                   : std_logic_vector(2 downto 0);
+      inj_ctrl_pic_mode_id_load_o              : std_logic;
+      inj_ctrl_pic_mode_valid_o                : std_logic;
+      inj_ctrl_pic_mode_valid_load_o           : std_logic;
+      inj_ctrl_pic_ena_o                       : std_logic;
+      inj_ctrl_pic_ena_load_o                  : std_logic;
+      end record;
+    
+    constant c_ep_out_registers_init_value: t_ep_out_registers := (
+      ecr_portid_o => (others => '0'),
+      ecr_rst_cnt_o => '0',
+      ecr_tx_en_o => '0',
+      ecr_rx_en_o => '0',
+      tscr_en_txts_o => '0',
+      tscr_en_rxts_o => '0',
+      tscr_cs_start_o => '0',
+      tscr_rx_cal_start_o => '0',
+      rfcr_a_runt_o => '0',
+      rfcr_a_giant_o => '0',
+      rfcr_a_hp_o => '0',
+      rfcr_keep_crc_o => '0',
+      rfcr_hpap_o => (others => '0'),
+      rfcr_mru_o => (others => '0'),
+      vcr0_qmode_o => (others => '0'),
+      vcr0_fix_prio_o => '0',
+      vcr0_prio_val_o => (others => '0'),
+      vcr0_pvid_o => (others => '0'),
+      vcr1_offset_o => (others => '0'),
+      vcr1_offset_wr_o => '0',
+      vcr1_data_o => (others => '0'),
+      vcr1_data_wr_o => '0',
+      pfcr0_mm_addr_o => (others => '0'),
+      pfcr0_mm_addr_wr_o => '0',
+      pfcr0_mm_write_o => '0',
+      pfcr0_mm_write_wr_o => '0',
+      pfcr0_enable_o => '0',
+      pfcr0_mm_data_msb_o => (others => '0'),
+      pfcr0_mm_data_msb_wr_o => '0',
+      pfcr1_mm_data_lsb_o => (others => '0'),
+      pfcr1_mm_data_lsb_wr_o => '0',
+      tcar_pcp_map_o => (others => '0'),
+      tcar_pcp_map_load_o => '0',
+      fcr_rxpause_o => '0',
+      fcr_txpause_o => '0',
+      fcr_rxpause_802_1q_o => '0',
+      fcr_txpause_802_1q_o => '0',
+      fcr_tx_thr_o => (others => '0'),
+      fcr_tx_quanta_o => (others => '0'),
+      mach_o => (others => '0'),
+      macl_o => (others => '0'),
+      mdio_cr_data_o => (others => '0'),
+      mdio_cr_data_wr_o => '0',
+      mdio_cr_addr_o => (others => '0'),
+      mdio_cr_rw_o => '0',
+      mdio_asr_phyad_o => (others => '0'),
+      dsr_lact_o => '0',
+      dsr_lact_load_o => '0',
+      dmcr_en_o => '0',
+      dmcr_en_load_o => '0',
+      dmcr_n_avg_o => (others => '0'),
+      dmcr_n_avg_load_o => '0',
+      dmsr_ps_rdy_o => '0',
+      dmsr_ps_rdy_load_o => '0',
+      inj_ctrl_pic_conf_ifg_o => (others => '0'),
+      inj_ctrl_pic_conf_ifg_load_o => '0',
+      inj_ctrl_pic_conf_sel_o => (others => '0'),
+      inj_ctrl_pic_conf_sel_load_o => '0',
+      inj_ctrl_pic_conf_valid_o => '0',
+      inj_ctrl_pic_conf_valid_load_o => '0',
+      inj_ctrl_pic_mode_id_o => (others => '0'),
+      inj_ctrl_pic_mode_id_load_o => '0',
+      inj_ctrl_pic_mode_valid_o => '0',
+      inj_ctrl_pic_mode_valid_load_o => '0',
+      inj_ctrl_pic_ena_o => '0',
+      inj_ctrl_pic_ena_load_o => '0'
+      );
+    function "or" (left, right: t_ep_in_registers) return t_ep_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body ep_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if x(i) = '1' then
+tmp(i):= '1';
+else
+tmp(i):= '0';
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_ep_in_registers) return t_ep_in_registers is
+variable tmp: t_ep_in_registers;
+begin
+tmp.ecr_feat_vlan_i := f_x_to_zero(left.ecr_feat_vlan_i) or f_x_to_zero(right.ecr_feat_vlan_i);
+tmp.ecr_feat_dmtd_i := f_x_to_zero(left.ecr_feat_dmtd_i) or f_x_to_zero(right.ecr_feat_dmtd_i);
+tmp.ecr_feat_ptp_i := f_x_to_zero(left.ecr_feat_ptp_i) or f_x_to_zero(right.ecr_feat_ptp_i);
+tmp.ecr_feat_dpi_i := f_x_to_zero(left.ecr_feat_dpi_i) or f_x_to_zero(right.ecr_feat_dpi_i);
+tmp.tscr_cs_done_i := f_x_to_zero(left.tscr_cs_done_i) or f_x_to_zero(right.tscr_cs_done_i);
+tmp.tscr_rx_cal_result_i := f_x_to_zero(left.tscr_rx_cal_result_i) or f_x_to_zero(right.tscr_rx_cal_result_i);
+tmp.tcar_pcp_map_i := f_x_to_zero(left.tcar_pcp_map_i) or f_x_to_zero(right.tcar_pcp_map_i);
+tmp.mdio_asr_rdata_i := f_x_to_zero(left.mdio_asr_rdata_i) or f_x_to_zero(right.mdio_asr_rdata_i);
+tmp.mdio_asr_ready_i := f_x_to_zero(left.mdio_asr_ready_i) or f_x_to_zero(right.mdio_asr_ready_i);
+tmp.dsr_lstatus_i := f_x_to_zero(left.dsr_lstatus_i) or f_x_to_zero(right.dsr_lstatus_i);
+tmp.dsr_lact_i := f_x_to_zero(left.dsr_lact_i) or f_x_to_zero(right.dsr_lact_i);
+tmp.dmcr_en_i := f_x_to_zero(left.dmcr_en_i) or f_x_to_zero(right.dmcr_en_i);
+tmp.dmcr_n_avg_i := f_x_to_zero(left.dmcr_n_avg_i) or f_x_to_zero(right.dmcr_n_avg_i);
+tmp.dmsr_ps_val_i := f_x_to_zero(left.dmsr_ps_val_i) or f_x_to_zero(right.dmsr_ps_val_i);
+tmp.dmsr_ps_rdy_i := f_x_to_zero(left.dmsr_ps_rdy_i) or f_x_to_zero(right.dmsr_ps_rdy_i);
+tmp.inj_ctrl_pic_conf_ifg_i := f_x_to_zero(left.inj_ctrl_pic_conf_ifg_i) or f_x_to_zero(right.inj_ctrl_pic_conf_ifg_i);
+tmp.inj_ctrl_pic_conf_sel_i := f_x_to_zero(left.inj_ctrl_pic_conf_sel_i) or f_x_to_zero(right.inj_ctrl_pic_conf_sel_i);
+tmp.inj_ctrl_pic_conf_valid_i := f_x_to_zero(left.inj_ctrl_pic_conf_valid_i) or f_x_to_zero(right.inj_ctrl_pic_conf_valid_i);
+tmp.inj_ctrl_pic_mode_id_i := f_x_to_zero(left.inj_ctrl_pic_mode_id_i) or f_x_to_zero(right.inj_ctrl_pic_mode_id_i);
+tmp.inj_ctrl_pic_mode_valid_i := f_x_to_zero(left.inj_ctrl_pic_mode_valid_i) or f_x_to_zero(right.inj_ctrl_pic_mode_valid_i);
+tmp.inj_ctrl_pic_ena_i := f_x_to_zero(left.inj_ctrl_pic_ena_i) or f_x_to_zero(right.inj_ctrl_pic_ena_i);
+return tmp;
+end function;
+end package body;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rtu_header_extract.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rtu_header_extract.vhd
new file mode 100644
index 000000000..a071bdd3a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rtu_header_extract.vhd
@@ -0,0 +1,205 @@
+-------------------------------------------------------------------------------
+-- Title      : RTU header extract
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_rtu_header_extract.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 - 2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+
+
+entity ep_rtu_header_extract is
+  generic(
+    g_with_rtu : boolean);
+  port(
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    snk_fab_i  : in  t_ep_internal_fabric;
+    snk_dreq_o : out std_logic;
+
+    src_fab_o  : out t_ep_internal_fabric;
+    src_dreq_i : in  std_logic;
+
+    mbuf_is_pause_i : in std_logic; 
+
+    vlan_class_i   : in std_logic_vector(2 downto 0);
+    vlan_vid_i      : in std_logic_vector(11 downto 0);
+    vlan_tag_done_i : in std_logic;
+    vlan_is_tagged_i: in std_logic;
+     
+    rmon_drp_at_rtu_full_o: out std_logic;
+    
+    rtu_rq_o       : out t_ep_internal_rtu_request;
+    rtu_full_i     : in  std_logic;
+    rtu_rq_abort_o : out std_logic;
+    rtu_rq_valid_o : out std_logic;
+    rxbuf_full_i   : in  std_logic
+    );
+
+end ep_rtu_header_extract;
+
+architecture rtl of ep_rtu_header_extract is
+
+  signal hdr_offset : std_logic_vector(11 downto 0);
+  signal in_packet  : std_logic;
+  signal in_header     : std_logic;
+  signal rtu_rq_valid_basic   : std_logic;
+  signal rtu_rq_valid_tagged   : std_logic;
+  signal rtu_rq_valid_out   : std_logic;
+  signal rtu_rq_abort       : std_logic;
+  
+
+  procedure f_extract_rtu(signal q         : out std_logic_vector;
+                          signal fab       :     t_ep_internal_fabric;
+                          signal at_offset :     std_logic) is
+  begin
+    if(at_offset = '1' and fab.dvalid = '1') then
+      q <= fab.data;
+    end if;
+  end f_extract_rtu;
+
+begin  -- rtl
+
+  gen_with_rtu : if(g_with_rtu) generate
+    
+    p_hdr_offset_sreg : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if (rst_n_i = '0' or snk_fab_i.sof = '1') then
+          hdr_offset(hdr_offset'left downto 1) <= (others => '0');
+          hdr_offset(0)                        <= '1';
+        elsif(snk_fab_i.dvalid = '1') then
+          hdr_offset <= hdr_offset(hdr_offset'left-1 downto 0) & '0';
+        end if;
+      end if;
+    end process;
+
+    p_gen_rtu_request : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_n_i = '0' then
+          rtu_rq_o.smac     <= (others => '0');
+          rtu_rq_o.dmac     <= (others => '0');
+          in_packet         <= '0';
+          rtu_rq_valid_basic<= '0';
+          rmon_drp_at_rtu_full_o <='0';
+          rtu_rq_abort     <= '0';
+          in_header        <= '0';
+        else
+          rmon_drp_at_rtu_full_o <='0';
+
+          if(snk_fab_i.sof = '1' and rtu_full_i = '0' and rxbuf_full_i = '0') then
+            in_packet <= '1';
+            in_header <= '1';
+          elsif(snk_fab_i.sof = '1' and rtu_full_i = '1') then
+            rmon_drp_at_rtu_full_o <='1';
+          end if;
+
+          if((snk_fab_i.eof   = '1' and snk_fab_i.sof = '0') or -- in case both (sof & eof) are HIGH
+              snk_fab_i.error = '1') then
+            in_packet <= '0';
+          end if;
+          
+          if(snk_fab_i.error = '1' or rtu_rq_valid_out = '1') then
+            in_header <= '0';
+          end if;
+          
+          
+          f_extract_rtu(rtu_rq_o.dmac(47 downto 32), snk_fab_i, hdr_offset(0));
+          f_extract_rtu(rtu_rq_o.dmac(31 downto 16), snk_fab_i, hdr_offset(1));
+          f_extract_rtu(rtu_rq_o.dmac(15 downto 0), snk_fab_i, hdr_offset(2));
+          f_extract_rtu(rtu_rq_o.smac(47 downto 32), snk_fab_i, hdr_offset(3));
+          f_extract_rtu(rtu_rq_o.smac(31 downto 16), snk_fab_i, hdr_offset(4));
+          f_extract_rtu(rtu_rq_o.smac(15 downto 0), snk_fab_i, hdr_offset(5));
+          
+          if(snk_fab_i.dvalid = '1'  and hdr_offset(6) = '1' and in_packet = '1') then
+            rtu_rq_valid_basic <='1';
+          elsif(rtu_rq_valid_out = '1' or   -- reset after making request or
+                snk_fab_i.error = '1') then -- when there is error in the header, so we don't 
+                                            -- make request for invalid frame which will be dumped
+                                            -- in the SWcore (which reads error status).
+                                            -- the special case when error occurs when the request
+                                            -- is made, we do end with the output of error (below, end of file)
+            rtu_rq_valid_basic     <= '0';
+          end if;
+          
+          if(in_packet       = '1' and in_header    = '0' and -- if we have packet and the header is already processed
+             snk_fab_i.error = '1' and rtu_rq_abort = '0') then 
+            rtu_rq_abort <= '1';
+          else
+            rtu_rq_abort <= '0';
+          end if;
+          
+        end if;
+      end if;
+    end process;
+ 
+    rtu_rq_abort_o <= rtu_rq_abort;
+    src_fab_o.sof <= snk_fab_i.sof and not rtu_full_i; -- null dev
+    
+    rtu_rq_valid_tagged <= rtu_rq_valid_basic and vlan_tag_done_i;
+    
+    -- the request is not done for PAUSE frames as they never go outside of Endpoint 
+    -- (they are dropped inside Endpoint)
+    rtu_rq_valid_out <= (rtu_rq_valid_tagged and (not mbuf_is_pause_i))when (vlan_is_tagged_i = '1') else
+                        (rtu_rq_valid_basic  and (not mbuf_is_pause_i));
+                        
+
+  end generate gen_with_rtu;
+
+  gen_without_rtu : if (not g_with_rtu) generate
+    src_fab_o.sof          <= snk_fab_i.sof;
+    rtu_rq_valid_out       <= '0';
+    rtu_rq_o.smac          <= (others => '0');
+    rtu_rq_o.dmac          <= (others => '0');
+    rtu_rq_abort_o         <= '0';
+    rmon_drp_at_rtu_full_o <= '0';
+  end generate gen_without_rtu;
+
+  snk_dreq_o <= src_dreq_i;
+
+  src_fab_o.eof                <= snk_fab_i.eof;
+  src_fab_o.dvalid             <= snk_fab_i.dvalid;
+  src_fab_o.error              <= snk_fab_i.error;
+  src_fab_o.bytesel            <= snk_fab_i.bytesel;
+  src_fab_o.data               <= snk_fab_i.data;
+  src_fab_o.addr               <= snk_fab_i.addr;
+  src_fab_o.has_rx_timestamp   <= snk_fab_i.has_rx_timestamp;
+  src_fab_o.rx_timestamp_valid <= snk_fab_i.rx_timestamp_valid;
+
+  rtu_rq_o.vid      <= vlan_vid_i;
+  rtu_rq_o.has_vid  <= vlan_is_tagged_i;
+  rtu_rq_o.prio     <= vlan_class_i;
+  rtu_rq_o.has_prio <= vlan_is_tagged_i;
+  rtu_rq_valid_o    <= rtu_rq_valid_out and not snk_fab_i.ERROR;
+  rtu_rq_o.hash     <= (others => '0');
+  
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_buffer.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_buffer.vhd
new file mode 100644
index 000000000..8295fac4b
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_buffer.vhd
@@ -0,0 +1,321 @@
+-------------------------------------------------------------------------------
+-- Title      : RX Packet Buffer
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_rx_buffer.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2017-02-02
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: A simple RX packet buffer, optimized for 18-bit Block RAM-based
+-- FIFOs.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1l.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+use work.genram_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.ep_wbgen2_pkg.all;
+
+entity ep_rx_buffer is
+  generic (
+    g_size    : integer := 1024;
+    g_with_fc : boolean := false
+    );
+  port(
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    snk_fab_i  : in  t_ep_internal_fabric;
+    snk_dreq_o : out std_logic;
+    src_fab_o  : out t_ep_internal_fabric;
+    src_dreq_i : in  std_logic;
+
+    level_o    : out std_logic_vector(7 downto 0);
+    full_o     : out std_logic;
+    drop_req_i : in  std_logic;
+    dropped_o  : out std_logic;
+    regs_i     : in  t_ep_out_registers
+    );
+
+end ep_rx_buffer;
+
+architecture behavioral of ep_rx_buffer is
+
+  constant c_drop_threshold    : integer := g_size - 3;
+  constant c_release_threshold : integer := g_size * 7 / 8;
+
+  type t_write_state is(WAIT_FRAME, DATA);
+
+  procedure f_pack_rbuf_contents
+    (
+      signal st         : in  t_write_state;
+      signal fab        : in  t_ep_internal_fabric;
+      signal prev_addr  : in  std_logic_vector;
+      signal dout       : out std_logic_vector;
+      signal dout_valid : out std_logic) is
+    variable valid_tmp : std_logic;
+  begin
+    if(fab.sof = '1' or fab.error = '1' or fab.eof = '1') then
+      -- tag = 11
+      dout(17)          <= '1';
+      dout(16)          <= '1';
+      dout(15)          <= fab.sof;
+      dout(14)          <= fab.eof;
+      dout(13)          <= fab.error;
+      dout(12 downto 0) <= (others => '0');
+      valid_tmp         := '1';
+--      dout_valid        <= '1';
+    elsif(fab.dvalid = '1') then
+
+      if(prev_addr /= fab.addr) then
+        dout(17 downto 16) <= "10";     -- reg-change
+      else
+        dout(17 downto 16) <= '0' & fab.bytesel;
+      end if;
+
+      dout(15 downto 0) <= fab.data;
+      valid_tmp         := '1';
+    else
+      dout(17 downto 0) <= (others => '0');
+      valid_tmp         := '0';
+    end if;
+
+    if(fab.sof = '1') then
+      dout_valid <= valid_tmp;
+    elsif(st = DATA) then
+      dout_valid <= valid_tmp;
+    else
+      dout_valid <= '0';
+    end if;
+  end f_pack_rbuf_contents;
+
+  procedure f_unpack_rbuf_contents
+    (
+      signal din       : in  std_logic_vector;
+      signal cur_addr  : in  std_logic_vector;
+      signal din_valid : in  std_logic;
+      signal fab       : out t_ep_internal_fabric;
+      early_eof        :     boolean := false) is
+  begin
+
+    fab.data <= din(15 downto 0);
+    if(din_valid = '1') then
+
+      if(din(17 downto 16) = "10") then  -- some fancy encoding is necessary here
+        case cur_addr(1 downto 0) is
+          when c_WRF_DATA =>
+            fab.addr <= c_WRF_OOB after 1 ns;
+          when c_WRF_STATUS =>
+            fab.addr <= c_WRF_DATA after 1 ns;
+          when others => fab.addr <= c_WRF_DATA after 1 ns;
+        end case;
+
+      else
+        fab.addr <= cur_addr after 1 ns;
+      end if;
+
+      fab.dvalid  <= not din(17) or (din(17) and not din(16));
+      fab.sof     <= din(15) and din(17) and din(16);
+      fab.eof     <= din(14) and din(17) and din(16);
+      fab.error   <= din(13) and din(17) and din(16);
+      fab.bytesel <= not din(17) and din(16);
+
+    else
+      fab.bytesel <= '0';
+      fab.addr    <= cur_addr after 1 ns;
+      fab.dvalid  <= '0';
+      fab.sof     <= '0';
+      fab.eof     <= '0';
+      fab.error   <= '0';
+      fab.data    <= (others => '0');
+    end if;
+    fab.has_rx_timestamp   <= '0';
+    fab.rx_timestamp_valid <= '0';
+  end f_unpack_rbuf_contents;
+
+
+  signal q_in, q_out             : std_logic_vector(17 downto 0);
+  signal q_usedw                 : std_logic_vector(f_log2_size(g_size)-1 downto 0);
+  signal q_empty                 : std_logic;
+  signal q_reset                 : std_logic;
+  signal q_rd                    : std_logic;
+  signal q_drop                  : std_logic;
+  signal q_in_valid, q_out_valid : std_logic;
+  signal q_aempty, q_afull       : std_logic;
+
+
+  signal state         : t_write_state;
+  signal fab_to_encode : t_ep_internal_fabric;
+  signal src_fab_int   : t_ep_internal_fabric;
+
+  signal in_prev_addr : std_logic_vector(1 downto 0);
+  signal out_cur_addr : std_logic_vector(1 downto 0);
+  
+begin
+
+  full_o <= q_drop;
+ 
+  p_fifo_write : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        q_drop       <= '0';
+        state        <= WAIT_FRAME;
+        in_prev_addr <= (others => '0');
+        dropped_o    <= '0';
+      else
+
+        if(snk_fab_i.dvalid = '1') then
+          in_prev_addr <= snk_fab_i.addr;
+        end if;
+
+        if(q_afull = '1') then
+          q_drop <= '1';
+        elsif(q_aempty = '1') then
+          q_drop <= '0';
+        end if;
+
+        case state is
+          when WAIT_FRAME =>
+            in_prev_addr <= c_WRF_STATUS;
+
+            if(snk_fab_i.sof = '1' and q_drop = '0' and drop_req_i = '0') then
+              state <= DATA;
+              dropped_o <= '0';
+            elsif(snk_fab_i.sof = '1' and (q_drop = '1' or drop_req_i = '1')) then
+              dropped_o <= '1';
+            end if;
+
+          when DATA =>
+            if(q_drop = '1' or snk_fab_i.eof = '1' or snk_fab_i.error = '1') then
+              state <= WAIT_FRAME;
+            end if;
+            
+          when others => null;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  p_pack_rbuf : process(state, fab_to_encode, in_prev_addr, q_in, q_in_valid)
+  begin
+    f_pack_rbuf_contents(state, fab_to_encode, in_prev_addr, q_in, q_in_valid);
+  end process;
+
+
+  p_encode_fifo_in : process(drop_req_i, q_drop, snk_fab_i, state)
+    variable fab_pre_encode : t_ep_internal_fabric;
+    
+  begin
+    fab_pre_encode := snk_fab_i;
+
+    if(fab_pre_encode.sof = '1' and (q_drop = '1' or drop_req_i = '1')) then
+      fab_pre_encode.sof := '0';
+    end if;
+
+    if(state = DATA and q_drop = '1') then
+      fab_pre_encode.dvalid := '0';
+      fab_pre_encode.error  := '1';
+    end if;
+
+    fab_to_encode <= fab_pre_encode;
+  end process;
+
+  q_reset <= rst_n_i and regs_i.ecr_rx_en_o;
+
+  BUF_FIFO : generic_sync_fifo
+    generic map (
+      g_data_width => 18,
+      g_size       => g_size,
+      g_with_almost_empty => true,
+      g_with_almost_full  => true,
+      g_almost_empty_threshold  => c_release_threshold,
+      g_almost_full_threshold   => c_drop_threshold,
+      g_with_count              => g_with_fc)
+    port map (
+      rst_n_i        => q_reset,
+      clk_i          => clk_sys_i,
+      d_i            => q_in,
+      we_i           => q_in_valid,
+      q_o            => q_out,
+      rd_i           => q_rd,
+      empty_o        => q_empty,
+      full_o         => open,
+      almost_empty_o => q_aempty,
+      almost_full_o  => q_afull,
+      count_o        => q_usedw);
+
+  
+  
+  q_rd <= (not q_empty) and src_dreq_i;
+
+  rd_valid_gen : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i = '0') then
+        q_out_valid  <= '0';
+        out_cur_addr <= c_WRF_STATUS;
+      else
+        q_out_valid <= q_rd;
+
+        if(src_fab_int.sof = '1' or src_fab_int.eof = '1' or src_fab_int.error = '1')then
+          out_cur_addr <= c_WRF_STATUS;
+        else
+          out_cur_addr <= src_fab_int.addr;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_unpack : process(q_out, out_cur_addr, q_out_valid,src_fab_int)
+  begin
+    f_unpack_rbuf_contents(q_out, out_cur_addr, q_out_valid, src_fab_int);
+  end process;
+
+  src_fab_o  <= src_fab_int;
+  snk_dreq_o <= '1';
+
+  GEN_FC: if g_with_fc = true generate
+    GEN_LEV_BIG : if f_log2_size(g_size)-1 > level_o'left generate
+      level_o <= q_usedw(q_usedw'left downto q_usedw'left - 7);
+    end generate;
+    GEN_LEV_SML : if f_log2_size(g_size)-1 < level_o'left+1 generate
+      level_o(q_usedw'left downto 0) <= q_usedw;
+    end generate;
+  end generate;
+
+  GEN_NOFC: if g_with_fc = false generate
+    level_o <= (others=>'X');
+  end generate;
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_crc_size_check.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_crc_size_check.vhd
new file mode 100644
index 000000000..23230b849
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_crc_size_check.vhd
@@ -0,0 +1,404 @@
+-------------------------------------------------------------------------------
+-- Title      : Rx CRC checker
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_rx_crc_size_check.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 - 2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;              -- for gc_crc_gen
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.ep_wbgen2_pkg.all;
+use work.ep_crc32_pkg.all;
+
+-- 1st deframing pipeline stage - CRC/PCS error/Size checker
+
+entity ep_rx_crc_size_check is
+  generic
+    (
+      g_use_new_crc : boolean := false);
+  port(
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    snk_fab_i  : in  t_ep_internal_fabric;
+    snk_dreq_o : out std_logic;
+
+    src_fab_o  : out t_ep_internal_fabric;
+    src_dreq_i : in  std_logic;
+
+    regs_i         : in  t_ep_out_registers;
+    rmon_pcs_err_o : out std_logic;
+    rmon_giant_o   : out std_logic;
+    rmon_runt_o    : out std_logic;
+    rmon_crc_err_o : out std_logic
+    );
+
+end ep_rx_crc_size_check;
+
+architecture behavioral of ep_rx_crc_size_check is
+
+  constant c_MIN_FRAME_SIZE : integer := 64;
+
+  component ep_rx_bypass_queue
+    generic (
+      g_size  : integer;
+      g_width : integer);
+    port (
+      rst_n_i : in  std_logic;
+      clk_i   : in  std_logic;
+      d_i     : in  std_logic_vector(g_width-1 downto 0);
+      valid_i : in  std_logic;
+      dreq_o  : out std_logic;
+      q_o     : out std_logic_vector(g_width-1 downto 0);
+      valid_o : out std_logic;
+      dreq_i  : in  std_logic;
+      flush_i : in  std_logic;
+      purge_i : in  std_logic;
+      empty_o : out std_logic);
+  end component;
+
+
+  type t_state is (ST_WAIT_FRAME, ST_DATA, ST_OOB);
+
+  signal crc_gen_enable        : std_logic;
+  signal crc_gen_reset         : std_logic;
+  signal crc_match, crc_match2 : std_logic;
+
+  signal crc_cur         : std_logic_vector(31 downto 0);
+  signal crc_in_data     : std_logic_vector(15 downto 0);
+  signal crc_last_is_odd : std_logic;
+
+  signal byte_cntr     : unsigned(13 downto 0);
+  signal is_runt       : std_logic;
+  signal is_giant      : std_logic;
+  signal size_check_ok : std_logic;
+
+  signal state : t_state;
+
+  signal q_flush, q_empty : std_logic;
+  signal q_purge          : std_logic;
+  signal q_in, q_out      : std_logic_vector(17 downto 0);
+  signal q_bytesel        : std_logic;
+  signal q_dvalid_in      : std_logic;
+  signal q_dvalid_out     : std_logic;
+  signal q_dreq_out       : std_logic;
+  
+  -- bypass_queue stuff comes here
+  constant c_crc_size    : integer := 2;
+  constant c_dat_width   : integer := 18;
+
+  type t_queue_array is array(0 to c_crc_size-1) of std_logic_vector(c_dat_width-1 downto 0);
+
+  signal q_data           : t_queue_array;
+  signal q_valid          : std_logic_vector(c_crc_size-1 downto 0);
+
+  signal qempty, qfull    : std_logic;
+  signal sreg_enable      : std_logic;
+  signal oob_in           : std_logic;
+  signal dat_in           : std_logic;
+  signal valid_mask       : std_logic;
+  signal err_on_giant     : std_logic;
+
+  function f_queue_occupation(q : std_logic_vector; check_empty : std_logic) return std_logic is
+    variable i : integer;
+  begin
+    for i in 0 to q'length-1 loop
+      if(q(i) = check_empty) then
+        return '0';
+      end if;
+    end loop;  -- i
+    return '1';
+  end function;
+
+begin  -- behavioral
+
+  crc_gen_reset  <= snk_fab_i.sof or (not rst_n_i);
+  crc_gen_enable <= '1' when (snk_fab_i.addr = c_WRF_DATA and snk_fab_i.dvalid = '1') else '0';
+
+  gen_old_crc : if(g_use_new_crc = false) generate
+    U_rx_crc_generator : gc_crc_gen
+      generic map (
+        g_polynomial              => x"04C11DB7",
+        g_init_value              => x"ffffffff",
+        g_residue                 => x"1cdf4421",
+        g_data_width              => 16,
+        g_half_width              => 8,
+        g_sync_reset              => 1,
+        g_dual_width              => 1,
+        g_registered_match_output => false)
+      port map (
+        clk_i   => clk_sys_i,
+        rst_i   => crc_gen_reset,
+        en_i    => crc_gen_enable,
+        half_i  => snk_fab_i.bytesel,
+        data_i  => snk_fab_i.data(15 downto 0),
+        match_o => crc_match,
+        crc_o   => open);
+  end generate gen_old_crc;
+
+  gen_new_crc : if(g_use_new_crc = true) generate
+
+    crc_in_data(15 downto 8) <= snk_fab_i.data(15 downto 8);
+    crc_in_data(7 downto 0)  <= x"00" when snk_fab_i.bytesel = '1' else snk_fab_i.data(7 downto 0);
+
+    p_check_crc : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if crc_gen_reset = '1' then
+          crc_cur <= c_CRC32_INIT_VALUE;
+        elsif(crc_gen_enable = '1') then
+          crc_cur         <= f_update_crc32_d16(crc_cur, crc_in_data);
+          crc_last_is_odd <= snk_fab_i.bytesel;
+        end if;
+      end if;
+    end process;
+
+    crc_match <= '1' when (crc_last_is_odd = '0' and crc_cur = c_CRC32_RESIDUE_FULL)
+                 or (crc_last_is_odd = '1' and crc_cur = c_CRC32_RESIDUE_HALF) else '0';
+
+  end generate gen_new_crc;
+
+--   U_bypass_queue : ep_rx_bypass_queue
+--     generic map (
+--       g_size  => 3,
+--       g_width => 18)
+--     port map (
+--       rst_n_i => rst_n_i,
+--       clk_i   => clk_sys_i,
+--       d_i     => q_in,
+--       valid_i => q_dvalid_in,
+--       dreq_o  => q_dreq_out,
+--       q_o     => q_out,
+--       valid_o => q_dvalid_out,
+--       dreq_i  => src_dreq_i,
+--       flush_i => '0',
+--       purge_i => q_purge,
+--       empty_o => q_empty);
+
+  snk_dreq_o <= q_dreq_out and not (snk_fab_i.eof or snk_fab_i.error);
+
+
+  p_count_bytes : process (clk_sys_i, rst_n_i)
+  begin  -- process
+    if rising_edge(clk_sys_i) then
+      if (rst_n_i = '0' or regs_i.ecr_rx_en_o = '0') then
+        byte_cntr <= (others => '0');
+        is_runt   <= '0';
+        is_giant  <= '0';
+      else
+        if(snk_fab_i.sof = '1') then
+          byte_cntr <= (others => '0');
+          is_runt   <= '1';
+        end if;
+
+        if(snk_fab_i.dvalid = '1') then
+          if(snk_fab_i.bytesel = '1') then
+            byte_cntr <= byte_cntr + 1;
+          else
+            byte_cntr <= byte_cntr + 2;
+          end if;
+        end if;
+
+        if(byte_cntr = to_unsigned(c_MIN_FRAME_SIZE - 2, byte_cntr'length) and snk_fab_i.dvalid = '1' and snk_fab_i.bytesel = '0') then
+          is_runt <= '0';
+        end if;
+
+        if(byte_cntr > unsigned(regs_i.rfcr_mru_o) and snk_fab_i.sof = '0') then
+          is_giant <= '1';
+        else
+          is_giant <= '0';
+        end if;
+        
+      end if;
+    end if;
+  end process;
+
+  size_check_ok <= '0' when (is_runt = '1' and regs_i.rfcr_a_runt_o = '0') or
+                   (is_giant = '1' and regs_i.rfcr_a_giant_o = '0') else '1';
+  err_on_giant  <= '1' when (is_giant = '1' and regs_i.rfcr_a_giant_o = '0') else '0';
+
+  p_gen_output : process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+
+      if rst_n_i = '0' or regs_i.ecr_rx_en_o = '0' then
+
+        q_purge   <= '0';
+        q_bytesel <= '0';
+
+        state <= ST_WAIT_FRAME;
+
+        rmon_pcs_err_o <= '0';
+        rmon_giant_o   <= '0';
+        rmon_runt_o    <= '0';
+        rmon_crc_err_o <= '0';
+
+        src_fab_o.sof <= '0';
+
+      else
+        case state is
+          when ST_WAIT_FRAME =>
+            q_purge         <= '0';
+            rmon_pcs_err_o  <= '0';
+            rmon_giant_o    <= '0';
+            rmon_runt_o     <= '0';
+            rmon_crc_err_o  <= '0';
+            q_bytesel       <= '0';
+            src_fab_o.error <= '0';
+            src_fab_o.sof   <= '0';
+
+            if(snk_fab_i.sof = '1') then
+              state         <= ST_DATA;
+              src_fab_o.sof <= '1';
+            end if;
+
+          when ST_DATA =>
+
+            src_fab_o.sof <= '0';
+
+            if(snk_fab_i.dvalid = '1' and snk_fab_i.addr = c_WRF_DATA) then
+              q_bytesel <= snk_fab_i.bytesel;
+            end if;
+
+            if(snk_fab_i.error = '1' or    -- an error from the source?
+               (q_bytesel = '1' and oob_in = '0' and snk_fab_i.dvalid = '1')) then -- we expect bytesel at the last byte of data
+
+              src_fab_o.error <= '1';
+              rmon_pcs_err_o  <= '1';
+              state           <= ST_WAIT_FRAME;
+              q_purge         <= '1';
+
+--             elsif(snk_fab_i.eof = '1' or oob_in = '1') then 
+            elsif(snk_fab_i.eof = '1' or oob_in = '1' or err_on_giant = '1') then
+              if(size_check_ok = '0' or crc_match = '0') then  -- bad frame?
+                state           <= ST_WAIT_FRAME;
+                src_fab_o.error <= '1';
+                q_purge         <= '1';
+              elsif(snk_fab_i.eof = '1') then
+                state         <= ST_WAIT_FRAME;
+              else
+                state       <= ST_OOB;
+              end if;
+
+              rmon_runt_o    <= is_runt and (not regs_i.rfcr_a_runt_o);
+              rmon_giant_o   <= is_giant and (not regs_i.rfcr_a_giant_o);
+              rmon_crc_err_o <= not crc_match;
+            end if;
+
+            
+          when ST_OOB =>
+            rmon_runt_o    <= '0';
+            rmon_giant_o   <= '0';
+            rmon_crc_err_o <= '0';
+           
+            if(src_dreq_i = '1' and snk_fab_i.eof='1') then
+              state         <= ST_WAIT_FRAME;
+            end if;
+            
+        end case;
+      end if;
+    end if;
+  end process;
+
+  --
+  q_in(15 downto 0)  <= snk_fab_i.data;
+  q_in(17 downto 16) <= snk_fab_i.addr;
+  q_dvalid_in        <= '1' when snk_fab_i.dvalid = '1' and (state = ST_DATA or state = ST_OOB) else '0';
+
+  --ML optimized queue_bypass so can remove masks tuff
+  src_fab_o.dvalid  <= q_dvalid_out;
+  src_fab_o.data    <= q_in(15 downto 0)  when (oob_in = '1') else q_out(15 downto 0);
+  src_fab_o.addr    <= q_in(17 downto 16) when (oob_in = '1') else q_out(17 downto 16) ;
+  src_fab_o.bytesel <= snk_fab_i.bytesel  when (dat_in = '1') else '0';
+  src_fab_o.eof     <= snk_fab_i.eof;
+
+  src_fab_o.has_rx_timestamp   <= snk_fab_i.has_rx_timestamp;
+  src_fab_o.rx_timestamp_valid <= snk_fab_i.rx_timestamp_valid;
+
+  --------------------- the whole of bypass_queue is here ------------------------------------
+  -- it was put inside as the optimization made it far from "universal" and apparently this
+  -- was the cause of doing the bypass_queue a separate module
+  --------------------------------------------------------------------------------------------
+  qempty       <= f_queue_occupation(q_valid, '1') ;
+  qfull        <= f_queue_occupation(q_valid, '0');
+
+  q_dvalid_out <= (qfull and q_dvalid_in) or (oob_in and valid_mask);
+  q_dreq_out   <= (src_dreq_i or not qfull);
+  oob_in       <= '1' when (snk_fab_i.addr = c_WRF_OOB  and q_dvalid_in = '1') else '0';
+  dat_in       <= '1' when (snk_fab_i.addr = c_WRF_DATA and q_dvalid_in = '1') else '0';
+  
+
+  sreg_enable  <= '1' when ((q_dvalid_in = '1') or (qempty = '0' and q_dvalid_out = '1')) else '0';
+  
+  q_out        <= q_data(0);
+
+  p_fifo: process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(sreg_enable = '1') then
+        q_data(c_crc_size-1)  <= q_in;
+        L0: for i in 0 to c_crc_size-2 loop
+            q_data(i)       <= q_data(i+1);
+        end loop L0;        
+      end if;
+    end if;
+  end process; 
+
+  p_queue : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' or q_purge = '1' then
+        valid_mask <= '0';
+        q_valid    <= (others => '0');
+      else
+
+        valid_mask <= src_dreq_i;
+
+        if sreg_enable = '1' then
+          q_valid(0)                           <= q_dvalid_in;
+          if(oob_in = '1' ) then -- flashing CRC
+            q_valid                            <=(others => '0');
+          else
+            q_valid(q_valid'length-1 downto 1) <= q_valid(q_valid'length-2 downto 0);
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+end behavioral;
+
+
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_early_address_match.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_early_address_match.vhd
new file mode 100644
index 000000000..427b5d322
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_early_address_match.vhd
@@ -0,0 +1,271 @@
+-------------------------------------------------------------------------------
+-- Title      : Rx Early Address Match
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_rx_early_address_match.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 - 2015 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;              -- for gc_crc_gen
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+
+-- 1st stage in the RX pipeline: early address matching/header parsing
+-- to filter out pause and HP frames in advance.
+
+entity ep_rx_early_address_match is
+  generic
+    (
+      g_early_hp_detection : boolean := false);
+  port(
+    clk_sys_i : in std_logic;
+    clk_rx_i  : in std_logic;
+
+    rst_n_sys_i : in std_logic;
+    rst_n_rx_i  : in std_logic;
+
+    snk_fab_i : in  t_ep_internal_fabric;
+    src_fab_o : out t_ep_internal_fabric;
+
+    match_done_o         : out std_logic;
+    match_is_hp_o        : out std_logic;
+    
+    -- indicate that pause was detected
+    match_is_pause_o     : out std_logic;
+    
+    -- tell quanta (for prio-based pause it is the greatest of all prios)
+    match_pause_quanta_o : out std_logic_vector(15 downto 0);
+    
+    -- mask with priorities which shall be PAUSEd
+    match_pause_prio_mask_o : out std_logic_vector(7 downto 0);
+   
+    -- once the PAUSE frame is decoded, it requests pausing from SWcore
+    match_pause_p_o      : out std_logic; 
+  
+    regs_i : in t_ep_out_registers
+    );
+
+end ep_rx_early_address_match;
+
+architecture behavioral of ep_rx_early_address_match is
+
+  signal hdr_offset : std_logic_vector(16 downto 0);
+
+  signal at_ethertype    : std_logic;
+  signal at_vid          : std_logic;
+  signal is_tagged       : std_logic;
+  signal pause_match_int : std_logic_vector(7 downto 0);
+
+  signal comb_pcp_matches_hp : std_logic;
+  signal done_int            : std_logic;
+
+  signal pause_prio_mask      : std_logic_vector(7 downto 0);
+  signal match_pause_req     : std_logic;
+  signal match_is_pause      : std_logic;
+  signal is_perprio_pause    : std_logic;
+  signal match_pause_quanta  : std_logic_vector(15 downto 0);
+
+  function f_compare_slv (a : std_logic_vector; b : std_logic_vector) return std_logic is
+  begin
+    if(a = b) then
+      return '1';
+    else
+      return '0';
+    end if;
+  end f_compare_slv;
+
+ 
+  
+begin  -- behavioral
+
+  at_ethertype <= hdr_offset(5) and snk_fab_i.dvalid;
+  at_vid       <= hdr_offset(7) and snk_fab_i.dvalid and is_tagged;
+
+  src_fab_o <= snk_fab_i;
+
+  p_hdr_offset_sreg : process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if (rst_n_rx_i = '0' or snk_fab_i.sof = '1') then
+        hdr_offset(hdr_offset'left downto 1) <= (others => '0');
+        hdr_offset(0)                        <= '1';
+      elsif(snk_fab_i.dvalid = '1') then
+        hdr_offset <= hdr_offset(hdr_offset'left-1 downto 0) & '0';
+      end if;
+    end if;
+  end process;
+
+  p_match_pause : process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if rst_n_rx_i = '0' or snk_fab_i.sof = '1' then
+        pause_match_int      <= (others => '0');
+        match_pause_quanta   <= (others => '0');
+        match_is_pause       <= '0';
+        pause_prio_mask      <= (others => '0');
+        match_pause_req      <= '0';
+        is_perprio_pause     <= '0';
+      else
+        if(snk_fab_i.dvalid = '1') then
+          if(hdr_offset(0) = '1') then
+            pause_match_int (0) <= f_compare_slv(snk_fab_i.data, x"0180");
+          end if;
+          if(hdr_offset(1) = '1') then
+            pause_match_int (1) <= f_compare_slv(snk_fab_i.data, x"c200");
+          end if;
+          if(hdr_offset(2) = '1') then
+            pause_match_int (2) <= f_compare_slv(snk_fab_i.data, x"0001");
+          end if;
+--           if(hdr_offset(3) = '1') then
+--             pause_match_int (3) <= f_compare_slv(snk_fab_i.data, regs_i.mach_o);
+--           end if;
+--           if(hdr_offset(4) = '1') then
+--             pause_match_int (4) <= f_compare_slv(snk_fab_i.data, regs_i.macl_o(31 downto 16));
+--           end if;
+--           if(hdr_offset(5) = '1') then
+--             pause_match_int (5) <= f_compare_slv(snk_fab_i.data, regs_i.macl_o(15 downto 0));
+--           end if;
+          if(hdr_offset(6) = '1') then
+            pause_match_int (3) <= f_compare_slv(snk_fab_i.data, x"8808");
+          end if;
+          if(hdr_offset(7) = '1') then
+            pause_match_int (4) <= f_compare_slv(snk_fab_i.data, x"0001"); -- 802.3 PAUSE
+            pause_match_int (5) <= f_compare_slv(snk_fab_i.data, x"0101"); -- 802.1Q PAUSE (per-prio)
+          end if;
+          if(hdr_offset(8) = '1') then
+            if(f_compare_slv(pause_match_int, b"0001_1111") = '1') then  -- 802.3 PAUSE
+
+              match_is_pause            <= '1'; -- to indicate that frame shall be dropped
+
+              if(regs_i.fcr_rxpause_o = '1') then
+                match_pause_req         <= '1';
+                match_pause_quanta      <= snk_fab_i.data;  
+                pause_prio_mask         <= (others => '1');
+              end if;
+
+            elsif(f_compare_slv(pause_match_int, b"0010_1111") = '1') then  -- 802.1Q PAUSE (per-prio)
+
+              match_is_pause          <= '1'; -- to indicate that frame shall be dropped
+
+              if(regs_i.fcr_rxpause_802_1q_o = '1') then
+                pause_prio_mask       <=  snk_fab_i.data(7 downto 0);
+                is_perprio_pause      <= '1';
+              end if;
+  
+            end if;
+          end if;
+          if (is_perprio_pause ='1' and ((hdr_offset(16 downto 9) and pause_prio_mask) /= b"0000_0000")) then
+            if(snk_fab_i.data > match_pause_quanta) then
+              match_pause_quanta <= snk_fab_i.data;
+            end if;  
+          end if;
+          if(hdr_offset(16) = '1' and is_perprio_pause = '1') then
+            match_pause_req           <= '1';
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  match_is_pause_o        <= match_is_pause;
+  match_pause_prio_mask_o <= pause_prio_mask;
+  match_pause_quanta_o    <= match_pause_quanta;
+
+  gen_with_early_hp_det: if(g_early_hp_detection) generate
+  -- ML: the p_match_hp is not used, instead identification of HP is done in RTU 
+  p_match_hp : process(clk_rx_i)
+    variable index : integer;
+  begin
+    
+    if rising_edge(clk_rx_i) then
+      index := to_integer(unsigned(snk_fab_i.data(15 downto 13)));
+
+      if rst_n_rx_i = '0' or snk_fab_i.sof = '1' then
+        is_tagged     <= '0';
+        match_is_hp_o <= '0';
+      else
+        if(at_ethertype = '1') then
+          is_tagged <= f_compare_slv(snk_fab_i.data, x"8100");
+        end if;
+
+        if (at_vid = '1') then
+          if(regs_i.rfcr_a_hp_o = '1' and regs_i.rfcr_hpap_o(index) = '1' and is_tagged = '1') then
+            match_is_hp_o <= '1';
+          else
+            match_is_hp_o <= '0';
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+  end generate gen_with_early_hp_det;
+  
+  gen_without_early_hp_det: if(not g_early_hp_detection) generate
+    match_is_hp_o <='0';
+  end generate gen_without_early_hp_det;
+
+  p_gen_done : process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if rst_n_rx_i = '0' or snk_fab_i.sof = '1' then
+        done_int <= '0';
+      else
+        if hdr_offset(8) = '1' or snk_fab_i.error = '1' then
+          done_int <= '1';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  U_sync_done : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_sys_i,
+      data_i   => done_int,
+      ppulse_o => match_done_o);
+
+  U_sync_pause : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_sys_i,
+      data_i   => match_pause_req,
+      ppulse_o => match_pause_p_o);
+
+end behavioral;
+
+
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_oob_insert.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_oob_insert.vhd
new file mode 100644
index 000000000..4fbaf7596
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_oob_insert.vhd
@@ -0,0 +1,171 @@
+-------------------------------------------------------------------------------
+-- Title      : RX OOB inserter
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_rx_oob_insert.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 - 2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;              -- for gc_crc_gen
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+use work.wr_fabric_pkg.all;
+
+
+entity ep_rx_oob_insert is
+  port(clk_sys_i : in std_logic;
+       rst_n_i   : in std_logic;
+
+       snk_fab_i  : in  t_ep_internal_fabric;
+       snk_dreq_o : out std_logic;
+
+       src_fab_o  : out t_ep_internal_fabric;
+       src_dreq_i : in  std_logic;
+
+       regs_i : in t_ep_out_registers
+       );
+
+end ep_rx_oob_insert;
+
+architecture behavioral of ep_rx_oob_insert is
+
+  type t_state is (WAIT_OOB, OOB);
+  signal state : t_state;
+
+  signal src_dreq_d0 : std_logic;
+
+  --component chipscope_ila
+  --  port (
+  --    CONTROL : inout std_logic_vector(35 downto 0);
+  --    CLK     : in    std_logic;
+  --    TRIG0   : in    std_logic_vector(31 downto 0);
+  --    TRIG1   : in    std_logic_vector(31 downto 0);
+  --    TRIG2   : in    std_logic_vector(31 downto 0);
+  --    TRIG3   : in    std_logic_vector(31 downto 0));
+  --end component;
+
+  --component chipscope_icon
+  --  port (
+  --    CONTROL0 : inout std_logic_vector (35 downto 0));
+  --end component;
+  
+  --signal CONTROL : std_logic_vector(35 downto 0);
+  --signal CLK     : std_logic;
+  --signal TRIG0   : std_logic_vector(31 downto 0);
+  --signal TRIG1   : std_logic_vector(31 downto 0);
+  --signal TRIG2   : std_logic_vector(31 downto 0);
+  --signal TRIG3   : std_logic_vector(31 downto 0);
+  
+begin
+  --chipscope_ila_1 : chipscope_ila
+  --  port map (
+  --    CONTROL => CONTROL,
+  --    CLK     => clk_sys_i,
+  --    TRIG0   => TRIG0,
+  --    TRIG1   => TRIG1,
+  --    TRIG2   => TRIG2,
+  --    TRIG3   => TRIG3);
+
+  --chipscope_icon_1 : chipscope_icon
+  --  port map (
+  --    CONTROL0 => CONTROL);
+
+  --TRIG0(15 downto 0) <= snk_fab_i.data;
+  --trig0(16) <= snk_fab_i.sof;
+  --trig0(17) <= snk_fab_i.eof;
+  --trig0(18) <= snk_fab_i.error;
+  --trig0(19) <= snk_fab_i.bytesel;
+  --trig0(20) <= snk_fab_i.has_rx_timestamp;
+  --trig0(21) <= snk_fab_i.dvalid;
+  --trig0(22) <= '1' when state = WAIT_OOB else '0';
+  --trig0(24 downto 23) <= snk_fab_i.addr;
+
+  snk_dreq_o                   <= src_dreq_i;
+  src_fab_o.sof                <= snk_fab_i.sof;
+  src_fab_o.eof                <= snk_fab_i.eof;
+  src_fab_o.ERROR              <= snk_fab_i.ERROR;
+  src_fab_o.bytesel            <= snk_fab_i.bytesel;
+  src_fab_o.has_rx_timestamp   <= snk_fab_i.has_rx_timestamp;
+  src_fab_o.rx_timestamp_valid <= snk_fab_i.rx_timestamp_valid;
+  
+  p_comb_src : process (state, snk_fab_i, src_dreq_i, regs_i)
+  begin
+
+    if(snk_fab_i.has_rx_timestamp = '1')then
+      src_fab_o.data   <= c_WRF_OOB_TYPE_RX & (not snk_fab_i.rx_timestamp_valid) & "000000" & regs_i.ecr_portid_o;
+      src_fab_o.dvalid <= '1';
+      src_fab_o.addr   <= c_WRF_OOB;
+    else
+      if(state = WAIT_OOB) then
+        src_fab_o.addr <= c_WRF_DATA;
+      else
+        src_fab_o.addr <= c_WRF_OOB;
+      end if;
+      src_fab_o.data   <= snk_fab_i.data;
+      src_fab_o.dvalid <= snk_fab_i.dvalid;
+    end if;
+  end process;
+
+  p_fsm : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' or regs_i.ecr_rx_en_o = '0' then
+        state <= WAIT_OOB;
+      else
+
+        if(snk_fab_i.error = '1' or snk_fab_i.sof = '1') then
+          state <= WAIT_OOB;
+        else
+
+          case state is
+            when WAIT_OOB =>
+              if(snk_fab_i.has_rx_timestamp = '1') then
+                state <= OOB;
+              end if;
+
+            when OOB =>
+              if(snk_fab_i.eof = '1') then
+                state <= WAIT_OOB;
+              end if;
+              
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+end behavioral;
+
+
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_path.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_path.vhd
new file mode 100644
index 000000000..7398828f2
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_path.vhd
@@ -0,0 +1,515 @@
+-------------------------------------------------------------------------------
+-- Title      : Gigabit Ethernet reception pipeline
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_rx_path.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2009-06-22
+-- Last update: 2017-02-02
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: RX path unit:
+-- - provides elastic buffering between RX and system clock
+-- - checks frame CRC and size
+-- - inserts/removes 802.1q headers when necessary 
+-- - parses packet headers and generates RTU requests
+-- - performs programmable packet inspection and classifying
+-- - distinguishes between HP and non-HP frames
+-- - issues RTU requests
+-- - embeds RX OOB block with timestamp information
+-- 
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2009-06-22  0.1      twlostow        Created
+-- 2011-10-18  0.5      twlostow        WB rev B4 - compatible data path
+------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+use work.wr_fabric_pkg.all;
+
+entity ep_rx_path is
+  generic (
+    g_with_vlans          : boolean := true;
+    g_with_dpi_classifier : boolean := true;
+    g_with_rtu            : boolean := true;
+    g_with_rx_buffer      : boolean := true;
+    g_with_early_match    : boolean := false;
+    g_rx_buffer_size      : integer := 1024;
+    g_use_new_crc         :	boolean := false);
+  port (
+    clk_sys_i   : in std_logic;
+    clk_rx_i    : in std_logic;
+    rst_n_sys_i : in std_logic;
+    rst_n_rx_i  : in std_logic;
+
+-- physical coding sublayer (PCS) interface
+    pcs_fab_i             : in  t_ep_internal_fabric;
+    pcs_fifo_almostfull_o : out std_logic;
+    pcs_busy_i            : in  std_logic;
+
+-- Wishbone I/O
+    src_wb_o : out t_wrf_source_out;
+    src_wb_i : in  t_wrf_source_in;
+
+-- flow control signals
+    fc_pause_p_o           : out std_logic;
+    fc_pause_quanta_o      : out std_logic_vector(15 downto 0);
+    fc_pause_prio_mask_o   : out std_logic_vector(7 downto 0);
+    fc_buffer_occupation_o : out std_logic_vector(7 downto 0);
+
+-- RMON/statistic counters signals
+    rmon_o : out t_rmon_triggers;
+    regs_i : in  t_ep_out_registers;
+    regs_o : out t_ep_in_registers;
+
+-- info for TRU module
+    pfilter_pclass_o : out std_logic_vector(7 downto 0);
+    pfilter_drop_o   : out std_logic;
+    pfilter_done_o   : out std_logic;
+
+-------------------------------------------------------------------------------
+-- RTU interface
+-------------------------------------------------------------------------------
+
+    rtu_rq_o       : out t_ep_internal_rtu_request;
+    rtu_full_i     : in  std_logic;
+    rtu_rq_valid_o : out std_logic;
+    rtu_rq_abort_o : out std_logic;
+
+    nice_dbg_o     : out t_dbg_ep_rxpath
+    );
+end ep_rx_path;
+
+architecture behavioral of ep_rx_path is
+
+  type t_rx_deframer_state is (RXF_IDLE, RXF_DATA, RXF_FLUSH_STALL, RXF_FINISH_CYCLE, RXF_THROW_ERROR);
+
+  signal state : t_rx_deframer_state;
+
+  signal gap_cntr : unsigned(3 downto 0);
+
+  -- new sigs
+  signal counter : unsigned(7 downto 0);
+
+  signal rxdata_saved : std_logic_vector(15 downto 0);
+  signal next_hdr     : std_logic;
+  signal is_pause     : std_logic;
+
+  signal data_firstword : std_logic;
+
+
+  signal flush_stall : std_logic;
+  signal stb_int     : std_logic;
+
+  signal fab_int  : t_ep_internal_fabric;
+  signal dreq_int : std_logic;
+
+  signal ack_count   : unsigned(7 downto 0);
+  signal src_out_int : t_wrf_source_out;
+
+  signal tmp_sel : std_logic;
+  signal tmp_dat : std_logic_vector(15 downto 0);
+
+
+  signal fab_pipe  : t_fab_pipe(0 to 9);
+  signal dreq_pipe : std_logic_vector(9 downto 0);
+
+  signal ematch_done     : std_logic;
+  signal ematch_is_hp    : std_logic;
+  signal ematch_is_pause : std_logic;
+  signal fc_pause_p      : std_logic;
+
+  signal pfilter_pclass : std_logic_vector(7 downto 0);
+  signal pfilter_drop   : std_logic;
+  signal pfilter_done   : std_logic;
+
+  signal vlan_tclass    : std_logic_vector(2 downto 0);
+  signal vlan_vid       : std_logic_vector(11 downto 0);
+  signal vlan_tag_done  : std_logic;
+  signal vlan_is_tagged : std_logic;
+
+  signal pcs_fifo_almostfull                                    : std_logic;
+  signal mbuf_rd, mbuf_valid, mbuf_we, mbuf_pf_drop, mbuf_is_hp : std_logic;
+  signal mbuf_is_pause, mbuf_full : std_logic;
+  signal mbuf_pf_class            : std_logic_vector(7 downto 0);
+  signal rtu_rq_valid         : std_logic;
+  signal stat_reg_mbuf_valid  : std_logic;
+
+  signal rxbuf_full       : std_logic;
+  signal rxbuf_dropped    : std_logic;
+
+  signal src_wb_out : t_wrf_source_out;
+  signal src_wb_cyc_d0 : std_logic;
+  
+  signal rst_n_rx_match_buff : std_logic;
+
+begin  -- behavioral
+
+  fab_pipe(0) <= pcs_fab_i;
+
+  fc_pause_p_o    <= fc_pause_p;
+  gen_with_early_match : if(g_with_early_match) generate
+    U_early_addr_match : ep_rx_early_address_match
+      port map (
+        clk_sys_i               => clk_sys_i,
+        clk_rx_i                => clk_rx_i,
+        rst_n_sys_i             => rst_n_sys_i,
+        rst_n_rx_i              => rst_n_rx_i,
+        snk_fab_i               => fab_pipe(0),
+        src_fab_o               => fab_pipe(1),
+        match_done_o            => ematch_done,
+        match_is_hp_o           => ematch_is_hp,
+        match_is_pause_o        => ematch_is_pause,
+        match_pause_quanta_o    => fc_pause_quanta_o,
+        match_pause_prio_mask_o => fc_pause_prio_mask_o,
+        match_pause_p_o         => fc_pause_p,
+        regs_i                  => regs_i);
+  end generate gen_with_early_match;
+
+  gen_without_early_match : if(not g_with_early_match) generate
+    fab_pipe(1)          <= fab_pipe(0);
+    ematch_done          <= '0';
+    ematch_is_hp         <= '0';
+    ematch_is_pause      <= '0';
+    fc_pause_quanta_o    <= (others =>'0');
+    fc_pause_prio_mask_o <= (others =>'0');
+    fc_pause_p           <= '0';
+  end generate gen_without_early_match;
+
+  gen_with_packet_filter : if(g_with_dpi_classifier) generate
+    U_packet_filter : ep_packet_filter
+      port map (
+        clk_sys_i   => clk_sys_i,
+        clk_rx_i    => clk_rx_i,
+        rst_n_sys_i => rst_n_sys_i,
+        rst_n_rx_i  => rst_n_rx_i,
+
+        snk_fab_i => fab_pipe(1),
+        src_fab_o => fab_pipe(2),
+        done_o    => pfilter_done,
+        pclass_o  => pfilter_pclass,
+        drop_o    => pfilter_drop,
+        regs_i    => regs_i);
+  end generate gen_with_packet_filter;
+
+  gen_without_packet_filter : if(not g_with_dpi_classifier) generate
+    fab_pipe(2)    <= fab_pipe(1);
+    pfilter_drop   <= '0';
+    pfilter_done   <= '1';
+    pfilter_pclass <= (others => '0');
+  end generate gen_without_packet_filter;
+
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if (rst_n_sys_i = '0') then
+        mbuf_we <= '0';
+      -- if rx_buffer has dropped a frame (e.g. because it was full) we
+      -- shouldn't store pfilter decision in the mbuf as well
+      elsif( ((ematch_done='1' and g_with_early_match) or
+              (pfilter_done='1' and g_with_dpi_classifier)) and
+              rxbuf_dropped='0') then
+        mbuf_we <= '1';
+      elsif(mbuf_rd = '1' or mbuf_full = '0') then
+        mbuf_we <= '0';
+      end if;
+    end if;
+  end process;
+
+  gen_with_match_buff: if( g_with_early_match or g_with_dpi_classifier) generate
+    U_Sync_Rst_match_buff : gc_sync_ffs
+      port map (
+        clk_i    => clk_sys_i,
+        rst_n_i  => '1',
+        data_i   => rst_n_rx_i,
+        synced_o => rst_n_rx_match_buff);
+
+    U_match_buffer : generic_shiftreg_fifo
+      generic map (
+        g_data_width => 8 + 1 + 1 + 1,
+        g_size       => 16)
+      port map (
+        rst_n_i           => rst_n_rx_match_buff,
+        clk_i             => clk_sys_i,
+        d_i (0)           => ematch_is_hp,
+        d_i (1)           => ematch_is_pause,
+        d_i (2)           => pfilter_drop,
+        d_i (10 downto 3) => pfilter_pclass,
+
+        we_i              => mbuf_we,
+        q_o (0)           => mbuf_is_hp,
+        q_o (1)           => mbuf_is_pause,
+        q_o (2)           => mbuf_pf_drop,
+        q_o (10 downto 3) => mbuf_pf_class,
+
+        rd_i      => mbuf_rd,
+        full_o    => mbuf_full,
+        q_valid_o => mbuf_valid);
+  end generate;
+
+  gen_without_match_buf: if(not (g_with_early_match or g_with_dpi_classifier)) generate
+    mbuf_is_hp    <= '0';
+    mbuf_is_pause <= '0';
+    mbuf_pf_drop  <= '0';
+    mbuf_pf_class <= (others=>'0');
+    mbuf_full     <= '0';
+    mbuf_valid    <= '1';
+  end generate;
+
+  -- don't block ep_rx_status_reg_insert when pfilter is disabled and early
+  -- match is not used
+  stat_reg_mbuf_valid <= '1' when (not g_with_early_match and g_with_dpi_classifier
+                                   and regs_i.pfcr0_enable_o='0') else
+                         mbuf_valid;
+
+  U_Rx_Clock_Align_FIFO : ep_clock_alignment_fifo
+    generic map (
+      g_size                 => 128,
+      g_almostfull_threshold => 112)
+    port map (
+      rst_n_rd_i       => rst_n_sys_i,
+      rst_n_wr_i       => rst_n_rx_i,
+      clk_wr_i         => clk_rx_i,
+      clk_rd_i         => clk_sys_i,
+      dreq_i           => dreq_pipe(3),
+      fab_i            => fab_pipe(2),
+      fab_o            => fab_pipe(3),
+      full_o           => nice_dbg_o.pcs_fifo_full,
+      empty_o          => nice_dbg_o.pcs_fifo_empty,
+      almostfull_o     => pcs_fifo_almostfull,
+      pass_threshold_i => std_logic_vector(to_unsigned(32, 7)));  -- fixme: add
+                                                                  -- register
+  pcs_fifo_almostfull_o <= pcs_fifo_almostfull;
+
+  U_Insert_OOB : ep_rx_oob_insert
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_sys_i,
+      snk_fab_i  => fab_pipe(3),
+      snk_dreq_o => dreq_pipe(3),
+      src_dreq_i => dreq_pipe(4),
+      src_fab_o  => fab_pipe(4),
+      regs_i     => regs_i);
+
+  U_crc_size_checker : ep_rx_crc_size_check
+    generic map (
+      g_use_new_crc	 => g_use_new_crc)
+    port map (
+      clk_sys_i      => clk_sys_i,
+      rst_n_i        => rst_n_sys_i,
+      snk_fab_i      => fab_pipe(4),
+      snk_dreq_o     => dreq_pipe(4),
+      src_dreq_i     => dreq_pipe(5),
+      src_fab_o      => fab_pipe(5),
+      regs_i         => regs_i,
+      rmon_pcs_err_o => rmon_o.rx_pcs_err,
+      rmon_giant_o   => rmon_o.rx_giant,
+      rmon_runt_o    => rmon_o.rx_runt,
+      rmon_crc_err_o => rmon_o.rx_crc_err);
+
+  gen_with_vlan_unit : if(g_with_vlans) generate
+    U_vlan_unit : ep_rx_vlan_unit
+      port map (
+        clk_sys_i   => clk_sys_i,
+        rst_n_i     => rst_n_sys_i,
+        snk_fab_i   => fab_pipe(5),
+        snk_dreq_o  => dreq_pipe(5),
+        src_fab_o   => fab_pipe(6),
+        src_dreq_i  => dreq_pipe(6),
+        tclass_o    => vlan_tclass,
+        vid_o       => vlan_vid,
+        tag_done_o  => vlan_tag_done,
+        is_tagged_o => vlan_is_tagged,
+        regs_i      => regs_i,
+        regs_o      => regs_o);
+  end generate gen_with_vlan_unit;
+
+
+  gen_without_vlan_unit : if(not g_with_vlans) generate
+    fab_pipe(6)    <= fab_pipe(5);
+    dreq_pipe(5)   <= dreq_pipe(6);
+    vlan_tclass    <= (others => '0');
+    vlan_vid       <= (others => '0');
+    vlan_tag_done  <= '0';
+    vlan_is_tagged <= '0';
+    regs_o         <= c_ep_in_registers_init_value;
+  end generate gen_without_vlan_unit;
+
+  U_RTU_Header_Extract : ep_rtu_header_extract
+    generic map (
+      g_with_rtu => g_with_rtu)
+    port map (
+      clk_sys_i        => clk_sys_i,
+      rst_n_i          => rst_n_sys_i,
+      snk_fab_i        => fab_pipe(6),
+      snk_dreq_o       => dreq_pipe(6),
+      src_fab_o        => fab_pipe(7),
+      src_dreq_i       => dreq_pipe(7),
+      mbuf_is_pause_i  => mbuf_is_pause,  -- this module is in the pipe before ep_rx_status_reg_insert,
+                                          -- however, we know that mbuf_is_pause is valid when it 
+                                          -- is used by this module -- this is because blocks the pipe
+                                          -- untill mbuf_valid is HIGH, and rtu_rq_valid_o is inserted HIGH
+                                          -- at the end of the header... (clear ??:)
+      vlan_class_i     => vlan_tclass,
+      vlan_vid_i       => vlan_vid,
+      vlan_tag_done_i  => vlan_tag_done,
+      vlan_is_tagged_i => vlan_is_tagged,
+      
+      rmon_drp_at_rtu_full_o => rmon_o.rx_drop_at_rtu_full,
+      
+      rtu_rq_o         => rtu_rq_o,
+      rtu_full_i       => rtu_full_i,
+      rtu_rq_abort_o   => rtu_rq_abort_o,
+      rtu_rq_valid_o   => rtu_rq_valid,
+      rxbuf_full_i     => rxbuf_full);
+
+  gen_with_rx_buffer : if g_with_rx_buffer generate
+    U_Rx_Buffer : ep_rx_buffer
+      generic map (
+        g_size    => g_rx_buffer_size,
+        g_with_fc => false)
+      port map (
+        clk_sys_i  => clk_sys_i,
+        rst_n_i    => rst_n_sys_i,
+        snk_fab_i  => fab_pipe(7),
+        snk_dreq_o => dreq_pipe(7),
+        src_fab_o  => fab_pipe(8),
+        src_dreq_i => dreq_pipe(8),
+        level_o    => fc_buffer_occupation_o,
+        full_o     => rxbuf_full,
+        drop_req_i => mbuf_we,  -- if mbuf_we is high that means it waits to be
+                                -- stored in mbuf => mbuf is probably full so we
+                                -- should drop this frame
+        dropped_o  => rxbuf_dropped,
+        regs_i     => regs_i);
+  end generate gen_with_rx_buffer;
+
+  gen_without_rx_buffer : if (not g_with_rx_buffer) generate
+    fab_pipe(8)  <= fab_pipe(7);
+    dreq_pipe(7) <= dreq_pipe(8);
+    rxbuf_full  <= '0';
+  end generate gen_without_rx_buffer;
+
+  U_Gen_Status : ep_rx_status_reg_insert
+    port map (
+      clk_sys_i           => clk_sys_i,
+      rst_n_i             => rst_n_sys_i,
+      snk_fab_i           => fab_pipe(8),
+      snk_dreq_o          => dreq_pipe(8),
+      src_fab_o           => fab_pipe(9),
+      src_dreq_i          => dreq_pipe(9),
+      mbuf_valid_i        => stat_reg_mbuf_valid,
+      mbuf_ack_o          => mbuf_rd,
+      mbuf_drop_i         => mbuf_pf_drop,
+      mbuf_pclass_i       => mbuf_pf_class,
+      mbuf_is_hp_i        => mbuf_is_hp,
+      mbuf_is_pause_i     => mbuf_is_pause,
+      rmon_pfilter_drop_o => rmon_o.rx_pfilter_drop);
+
+  U_RX_Wishbone_Master : ep_rx_wb_master
+    generic map (
+      g_ignore_ack => true)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_sys_i,
+      snk_fab_i  => fab_pipe(9),
+      snk_dreq_o => dreq_pipe(9),
+      src_wb_i   => src_wb_i,
+      src_wb_o   => src_wb_out
+      );
+
+  src_wb_o <= src_wb_out;
+
+  -- direct output of packet filter data (for TRU)
+  pfilter_pclass_o <= pfilter_pclass;
+  pfilter_drop_o   <= pfilter_drop;
+  pfilter_done_o   <= pfilter_done;
+
+  rtu_rq_valid_o   <= rtu_rq_valid;
+  -----------------------------------------
+  -- RMON events
+  -----------------------------------------
+  rmon_o.rx_pause <= fc_pause_p;
+  GEN_PCLASS_EVT: for i in 0 to 7 generate
+    rmon_o.rx_pclass(i) <= pfilter_pclass(i) and pfilter_done;
+  end generate;
+
+  rmon_o.rx_tclass(0) <= rtu_rq_valid when (vlan_tclass = "000" and vlan_is_tagged = '1') else '0';
+  rmon_o.rx_tclass(1) <= rtu_rq_valid when (vlan_tclass = "001" and vlan_is_tagged = '1') else '0';
+  rmon_o.rx_tclass(2) <= rtu_rq_valid when (vlan_tclass = "010" and vlan_is_tagged = '1') else '0';
+  rmon_o.rx_tclass(3) <= rtu_rq_valid when (vlan_tclass = "011" and vlan_is_tagged = '1') else '0';
+  rmon_o.rx_tclass(4) <= rtu_rq_valid when (vlan_tclass = "100" and vlan_is_tagged = '1') else '0';
+  rmon_o.rx_tclass(5) <= rtu_rq_valid when (vlan_tclass = "101" and vlan_is_tagged = '1') else '0';
+  rmon_o.rx_tclass(6) <= rtu_rq_valid when (vlan_tclass = "110" and vlan_is_tagged = '1') else '0';
+  rmon_o.rx_tclass(7) <= rtu_rq_valid when (vlan_tclass = "111" and vlan_is_tagged = '1') else '0';
+
+  GEN_DBG: for i in 0 to 9 generate
+    nice_dbg_o.fab_pipe(i) <= fab_pipe(i);
+    nice_dbg_o.dreq_pipe(i)<= dreq_pipe(i);
+  end generate GEN_DBG;
+
+  nice_dbg_o.pcs_fifo_afull <= pcs_fifo_almostfull;
+  nice_dbg_o.rxbuf_full <= rxbuf_full;
+
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if (rst_n_sys_i = '0') then
+        src_wb_cyc_d0 <= '0';
+      else
+        src_wb_cyc_d0 <= src_wb_out.cyc;
+      end if;
+    end if;
+  end process;
+
+  rmon_o.rx_frame <= '1' when (src_wb_out.cyc = '1' and src_wb_cyc_d0 = '0') else
+                     '0';
+
+  -- drive unused signals and outputs
+  dreq_pipe(2 downto 0)         <= (others => '0');
+  rmon_o.rx_sync_lost           <= '0';
+  rmon_o.rx_invalid_code        <= '0';
+  rmon_o.rx_overrun             <= '0';
+  rmon_o.rx_ok                  <= '0';
+  rmon_o.rx_buffer_overrun      <= '0';
+  rmon_o.rx_rtu_overrun         <= '0';
+  rmon_o.rx_path_timing_failure <= '0';
+  rmon_o.tx_pause               <= '0';
+  rmon_o.tx_underrun            <= '0';
+  rmon_o.tx_frame               <= '0';
+
+end behavioral;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_pcs_16bit.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
new file mode 100644
index 000000000..ea0fd8818
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
@@ -0,0 +1,765 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000BaseT/X MAC Endpoint - receive path PCS for 1000BaseX
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : ep_rx_pcs_16bit.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2009-06-16
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Module implements the reception path for 1000BaseX PCS
+-- (Physical Coding Sublayer) with native 16-bit datapath.
+-- It provides synchronization between the PHY RX clock and system reference clock,
+-- elastic buffering, preamble, SFD and other 8b10b patterns recognition.
+-- It also generates deterministic timestamping pulses for RXed packets.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2011-10-17  0.2      twlostow  Virtex6 port
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+
+entity ep_rx_pcs_16bit is
+  generic (
+    g_simulation : boolean);
+  port (
+-- 62.5 MHz refclk divided by 2
+    clk_sys_i : in std_logic;
+
+-- reset (refclk2-synchronous)
+    rst_n_i : in std_logic;
+
+-- reset (phy_rx_clk_i sync)
+    rst_rxclk_n_i : in std_logic;
+
+    pcs_fifo_almostfull_i : in  std_logic;
+-- RX path busy indicator (active HI).
+-- When asserted, the receiver is in the middle of reception of a frame
+    pcs_busy_o            : out std_logic;
+-- data FIFO output
+    pcs_fab_o             : out t_ep_internal_fabric;
+
+
+    timestamp_trigger_p_a_o : out std_logic;  -- strobe for RX timestamping
+    timestamp_i       : in  std_logic_vector(31 downto 0);
+    timestamp_stb_i: in std_logic;
+    timestamp_valid_i : in  std_logic;
+
+-------------------------------------------------------------------------------
+-- PHY interface
+-------------------------------------------------------------------------------    
+
+    phy_rdy_i        : in std_logic;
+    phy_rx_clk_i     : in std_logic;
+    phy_rx_data_i    : in std_logic_vector(15 downto 0);
+    phy_rx_k_i       : in std_logic_vector(1 downto 0);
+    phy_rx_enc_err_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- Wishbone registers
+-------------------------------------------------------------------------------    
+
+    -- Receive control regsiter
+    mdio_mcr_reset_i           : in  std_logic;
+    mdio_mcr_pdown_i           : in  std_logic;
+    mdio_wr_spec_cal_crst_i    : in  std_logic;
+    mdio_wr_spec_rx_cal_stat_o : out std_logic;
+
+    synced_o    : out std_logic;
+    sync_lost_o : out std_logic;
+
+    -- autonegotiation signals
+    an_rx_en_i      : in  std_logic;
+    an_rx_val_o     : out std_logic_vector(15 downto 0);
+    an_rx_valid_o   : out std_logic;
+    an_idle_match_o : out std_logic;
+
+    -- RMON events
+    rmon_rx_overrun   : out std_logic;
+    rmon_rx_inv_code  : out std_logic;
+    rmon_rx_sync_lost : out std_logic;
+     
+    nice_dbg_o  : out t_dbg_ep_rxpcs
+    );
+
+end ep_rx_pcs_16bit;
+
+architecture behavioral of ep_rx_pcs_16bit is
+
+-- RX state machine definitions
+  type t_tbif_rx_state is (RX_NOFRAME, RX_CR, RX_SPD_PREAMBLE, RX_PAYLOAD, RX_EXTEND);
+
+-- size of the calibrration pattern detection counter. It counts up every time
+-- a valid calibration pattern character is received and resets upon detecion
+-- of non-calibration character. The pattern is validated when the counter
+-- overflows (after 2**c_cal_pattern_counter_bits counts)
+
+  function f_calc_pattern_counter_bits
+    return integer is
+  begin  -- f_calc_pattern_counter_bits
+    if(g_simulation) then
+      return 8;                         -- use smaller calibration counter to
+                                        -- speed up the simulation
+    else
+      return 17;
+    end if;
+  end f_calc_pattern_counter_bits;
+
+  function f_to_sl(x : boolean) return std_logic is
+  begin
+    if(x) then
+      return '1';
+    else
+      return '0';
+    end if;
+  end f_to_sl;
+
+
+  constant c_cal_pattern_counter_bits : integer := f_calc_pattern_counter_bits;
+
+  component ep_sync_detect_16bit
+    port (
+      rst_n_i  : in  std_logic;
+      rbclk_i  : in  std_logic;
+      en_i     : in  std_logic;
+      data_i   : in  std_logic_vector(15 downto 0);
+      k_i      : in  std_logic_vector(1 downto 0);
+      err_i    : in  std_logic;
+      synced_o : out std_logic;
+      cal_i    : in  std_logic);
+  end component;
+
+  signal rst_n_rx : std_logic;
+
+  signal rx_state         : t_tbif_rx_state;
+  signal preamble_cntr    : unsigned(2 downto 0);
+  signal rx_busy          : std_logic;
+  signal rx_enable_synced : std_logic;
+  signal rx_rdreq         : std_logic;
+
+  -- 8b10b decoding and postprocessing signals
+  signal d_data                                 : std_logic_vector(15 downto 0);
+  signal d_err, d_is_idle, d_is_spd_preamble    : std_logic;
+  signal d_is_eof_extend, d_is_eof, d_is_extend : std_logic;
+  signal d_is_preamble, d_is_preamble_sfd       : std_logic;
+  signal d_is_k                                 : std_logic_vector(1 downto 0);
+  signal d_is_lcr                               : std_logic;
+  signal d_is_cal                               : std_logic;
+
+-- Synchronization detection FSM signals
+  signal rx_synced      : std_logic;
+  signal rx_sync_lost_p : std_logic;
+  signal rx_sync_status : std_logic;
+  signal rx_sync_enable : std_logic;
+
+-- Autonegotiation control signals
+  signal an_rx_en_synced : std_logic;
+
+  signal lcr_ready         : std_logic;
+  signal lcr_prev_val      : std_logic_vector(15 downto 0);
+  signal lcr_cur_val       : std_logic_vector(15 downto 0);
+  signal lcr_final_val     : std_logic_vector(15 downto 0);
+  signal lcr_validity_cntr : unsigned(1 downto 0);
+
+  signal an_idle_cntr      : unsigned(1 downto 0);
+  signal an_idle_match_int : std_logic;
+
+-- RMON counter pulses
+  signal rmon_rx_overrun_p_int   : std_logic;
+  signal rmon_syncloss_p_int     : std_logic;
+  signal rmon_invalid_code_p_int : std_logic;
+
+-- Misc. signals
+  signal cal_pattern_cntr      : unsigned(c_cal_pattern_counter_bits-1 downto 0);
+  signal mdio_mcr_reset_synced : std_logic;
+  signal mdio_mcr_pdown_synced : std_logic;
+
+
+  signal pcs_valid_int     : std_logic;
+  signal timestamp_pending : std_logic_vector(2 downto 0) := "000";
+  
+begin
+-------------------------------------------------------------------------------
+-- synchronizer chains for Wishbone-accessible control signals
+-------------------------------------------------------------------------------
+
+  U_sync_pcs_busy : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => '1',
+      data_i   => rx_busy,
+      synced_o => pcs_busy_o,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_an_rx_enable : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_rx_clk_i,
+      rst_n_i  => rst_n_rx,
+      data_i   => an_rx_en_i,
+      synced_o => an_rx_en_synced,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_mcr_reset : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_rx_clk_i,
+      rst_n_i  => '1',
+      data_i   => mdio_mcr_reset_i,
+      synced_o => mdio_mcr_reset_synced,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_power_down : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_rx_clk_i,
+      rst_n_i  => '1',
+      data_i   => mdio_mcr_pdown_i,
+      synced_o => mdio_mcr_pdown_synced,
+      npulse_o => open,
+      ppulse_o => open);
+
+  rx_sync_enable <= not mdio_mcr_pdown_synced;
+  rst_n_rx  <= rst_rxclk_n_i and not mdio_mcr_reset_synced and phy_rdy_i;
+
+-------------------------------------------------------------------------------
+-- 802.3z Link Synchronization State Machine
+-------------------------------------------------------------------------------
+
+  U_SYNC_DET : ep_sync_detect_16bit
+    port map (
+      rst_n_i  => rst_n_rx,
+      rbclk_i  => phy_rx_clk_i,
+      en_i     => rx_sync_enable,
+      data_i   => phy_rx_data_i,
+      k_i      => phy_rx_k_i,
+      err_i    => phy_rx_enc_err_i,
+      synced_o => rx_synced,
+      cal_i    => d_is_cal);
+
+  -- synchronizer chain for rx_synced signal, also serving as a loss-of-sync detector
+  U_sync_los : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => '1',
+      data_i   => rx_synced,
+      synced_o => rx_sync_status,
+      npulse_o => rx_sync_lost_p,
+      ppulse_o => open);
+
+  synced_o    <= rx_sync_status;        -- drive the PCS outputs
+  sync_lost_o <= rx_sync_lost_p;
+
+-------------------------------------------------------------------------------
+-- Calibration pattern logic
+-------------------------------------------------------------------------------
+
+  -- process checks the presence of valid calibtaion pattern and controls the
+  -- state of CAL_STA bit in Receive Control Register.
+  --
+  -- reads: phy_rx_data_i, mdio_wr_spec_cal_crst_i
+  -- writes: mdio_wr_spec_rx_cal_stat_o
+  --
+  p_detect_cal : process(phy_rx_clk_i)
+  begin
+    if rising_edge(phy_rx_clk_i) then
+      if rst_n_rx = '0' then
+        cal_pattern_cntr <= (others => '0');
+        d_is_cal         <= '0';
+      else
+
+        d_is_cal <= f_to_sl(phy_rx_data_i = (c_k28_7 & c_k28_7) and phy_rx_k_i = "11");
+
+        if(d_is_cal = '1' and mdio_wr_spec_cal_crst_i = '0') then
+
+-- we've got c_cal_pattern_threshold valid calibration characters - indicate
+-- that we're receiving a valid calibration pattern
+          if(cal_pattern_cntr(cal_pattern_cntr'high) = '1') then
+            mdio_wr_spec_rx_cal_stat_o <= '1';
+          else
+            mdio_wr_spec_rx_cal_stat_o <= '0';
+            cal_pattern_cntr           <= cal_pattern_cntr + 1;
+          end if;
+-- we've got a non-calibration character or the pattern detection has been reset
+        else
+          mdio_wr_spec_rx_cal_stat_o <= '0';
+          cal_pattern_cntr           <= (others => '0');
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+-------------------------------------------------------------------------------
+-- Clock adjustment FIFO
+-------------------------------------------------------------------------------  
+
+
+  -- process postprocesses the raw 8b10b decoder output (phy_rx_data_i, phy_rx_k_i, phy_rx_enc_err_ior)
+  -- providing 1-bit signals indicating various 8b10b control patterns
+  p_8b10b_postprocess : process(phy_rx_clk_i)
+  begin
+    if rising_edge(phy_rx_clk_i) then
+      
+      if(rst_n_rx = '0' or rx_synced = '0') then
+        d_data            <= (others => '0');
+        d_is_idle         <= '0';
+        d_is_k            <= "00";
+        d_is_spd_preamble <= '0';
+        d_is_preamble_sfd <= '0';
+        d_is_preamble     <= '0';
+        d_is_eof          <= '0';
+        d_is_extend       <= '0';
+        d_is_eof_extend   <= '0';
+        d_is_lcr          <= '0';
+        d_err             <= '0';
+      else
+
+        d_data <= phy_rx_data_i;
+        d_is_k <= phy_rx_k_i;
+
+        if(phy_rx_enc_err_i = '0') then
+          d_err <= '0';
+
+          
+          d_is_idle <= f_to_sl(phy_rx_data_i(15 downto 8) = c_K28_5
+                               and (phy_rx_data_i(7 downto 0) = c_d16_2
+                                    or phy_rx_data_i(7 downto 0) = c_d5_6)
+                               and phy_rx_k_i = "10");
+
+
+          d_is_spd_preamble <= f_to_sl(
+            phy_rx_data_i(15 downto 8) = c_k27_7
+            and phy_rx_data_i(7 downto 0) = c_preamble_char
+            and phy_rx_k_i = "10");
+
+          d_is_preamble <= f_to_sl(
+            phy_rx_data_i = c_preamble_char & c_preamble_char
+            and phy_rx_k_i = "00");
+
+          d_is_preamble_sfd <= f_to_sl(
+            phy_rx_data_i = c_preamble_char & c_preamble_sfd
+            and phy_rx_k_i = "00");
+
+-- data + EPD
+          d_is_eof <= f_to_sl(
+            phy_rx_data_i(7 downto 0) = c_K29_7
+            and phy_rx_k_i = "01");
+
+          -- EPD + extend
+          d_is_eof_extend <= f_to_sl(
+            phy_rx_data_i(15 downto 8) = c_K29_7
+            and phy_rx_data_i(7 downto 0) = c_k23_7
+            and phy_rx_k_i = "11");
+
+          d_is_extend <= f_to_sl(
+            phy_rx_data_i = c_K23_7 & c_K23_7
+            and phy_rx_k_i = "11");
+
+          d_is_lcr <= f_to_sl(
+            phy_rx_data_i(15 downto 8) = c_K28_5
+            and (phy_rx_data_i(7 downto 0) = c_d21_5
+                 or phy_rx_data_i(7 downto 0) = c_d2_2)
+            and phy_rx_k_i = "10");
+
+
+-- invalid code received?
+        else
+          d_err             <= '1';
+          d_is_idle         <= 'X';
+          d_is_spd_preamble <= 'X';
+          d_is_preamble_sfd <= 'X';
+          d_is_preamble     <= 'X';
+          d_is_eof          <= 'X';
+          d_is_extend       <= 'X';
+          d_is_eof_extend   <= 'X';
+          d_is_lcr          <= 'X';
+        end if;
+      end if;
+    end if;
+  end process;
+
+-- process: RBCLK-driven RX state machine. Implements the receive logic od 802.3z compliant
+-- 1000BaseX PCS.
+-- reads: almost everything
+-- writes: almost everything
+
+  
+  rx_fsm : process (phy_rx_clk_i)
+  begin
+    if rising_edge(phy_rx_clk_i) then
+      -- reset or PCS disabled
+      if(rst_n_rx = '0' or mdio_mcr_pdown_synced = '1') then
+        rx_state <= RX_NOFRAME;
+        rx_busy  <= '0';
+
+        pcs_fab_o.sof    <= '0';
+        pcs_fab_o.eof    <= '0';
+        pcs_fab_o.error  <= '0';
+        pcs_fab_o.dvalid <= '0';
+        pcs_fab_o.bytesel <= '0';
+        pcs_fab_o.has_rx_timestamp <= '0';
+        pcs_fab_o.data <= (others => 'X');
+
+        lcr_ready         <= '0';
+        lcr_cur_val       <= (others => '0');
+        lcr_prev_val      <= (others => '0');
+        -- lcr_final_val ===> DO NOT CLEAR on reset
+        lcr_validity_cntr <= (others => '0');
+        an_idle_cntr      <= (others => '0');
+        an_idle_match_int <= '0';
+
+        rmon_rx_overrun_p_int   <= '0';
+        rmon_invalid_code_p_int <= '0';
+        timestamp_trigger_p_a_o <= '0';
+        timestamp_pending       <= "000";
+      else                              -- normal PCS operation
+
+        -- clear the autogotiation variables if the autonegotiation is disabled
+        if(an_rx_en_synced = '0') then
+          lcr_ready         <= '0';
+          lcr_validity_cntr <= (others => '0');
+          lcr_prev_val      <= (others => '0');
+          an_idle_cntr      <= (others => '0');
+          an_idle_match_int <= '0';
+        end if;
+
+-------------------------------------------------------------------------------
+-- Main RX PCS state machine
+-------------------------------------------------------------------------------          
+        case rx_state is
+
+-------------------------------------------------------------------------------
+-- State NOFRAME: receiver is receiving IDLE pattern
+-------------------------------------------------------------------------------            
+          when RX_NOFRAME =>
+
+            preamble_cntr <= "011";
+            pcs_fab_o.eof   <= '0';
+            pcs_fab_o.error <= '0';
+            pcs_fab_o.bytesel <= '0';
+            pcs_fab_o.has_rx_timestamp <= '0';
+
+            rx_busy           <= '0';
+            timestamp_trigger_p_a_o <= '0';
+
+            -- insert the RX timestamp into the FIFO
+            if(timestamp_pending /= "000") then
+              pcs_fab_o.dvalid <= '1';
+            else
+              pcs_fab_o.dvalid <= '0';
+            end if;
+
+            if(timestamp_pending(0) = '1')then
+              pcs_fab_o.data <= timestamp_i(31 downto 16);
+              pcs_fab_o.eof  <= '0';
+            elsif(timestamp_pending(1) = '1')then
+              pcs_fab_o.data <= timestamp_i(15 downto 0);
+              pcs_fab_o.eof  <= '0';
+            elsif(timestamp_pending(2) = '1')then
+              pcs_fab_o.data <= (others => 'X');
+              pcs_fab_o.eof  <= '1';
+            end if;
+
+            timestamp_pending <= timestamp_pending(1 downto 0) & '0';
+
+            if (rx_synced = '0') then  -- PCS is not synced: stay in NOFRAME state and ignore the incoming codes.
+              rx_state <= RX_NOFRAME;
+            else
+
+              if(d_is_spd_preamble = '1') then  -- we've got a Start-of-Packet Delimeter
+                if(pcs_fifo_almostfull_i = '0') then
+                  rx_state <= RX_SPD_PREAMBLE;
+                else
+                  rx_state              <= RX_NOFRAME;
+                  rmon_rx_overrun_p_int <= '1';
+                end if;
+              end if;
+
+              if (d_is_lcr = '1') then
+                rx_state          <= RX_CR;
+                an_idle_match_int <= '0';
+                an_idle_cntr      <= (others => '0');
+                rx_busy           <= '1';
+              end if;
+
+              if(d_is_idle = '1') then
+                lcr_ready         <= '0';
+                an_idle_match_int <= '0';
+                an_idle_cntr      <= (others => '0');
+                lcr_validity_cntr <= (others => '0');
+
+                if(an_idle_cntr = "11") then
+                  an_idle_match_int <= '1';
+                else
+                  an_idle_cntr <= an_idle_cntr + 1;
+                end if;
+                rx_busy <= '0';
+              end if;
+            end if;
+
+-- produce a pulse at every invalid 8b10b code.
+            rmon_invalid_code_p_int <= d_err;
+
+-------------------------------------------------------------------------------
+-- States CR3/CR4: reception of LCR register value.
+-------------------------------------------------------------------------------              
+          when RX_CR =>  -- receives the 1st byte of Config_Reg and
+            -- checks if the subsequent Config_Reg
+            -- values are identical.
+
+-- an error? - abort the reception and go to NOFRAME state.
+            if(d_err = '1' or d_is_k /= "00" or rx_synced = '0') then
+              rx_state                <= RX_NOFRAME;
+              rmon_invalid_code_p_int <= d_err;
+
+              -- reset the Config_Reg value and mark it as invalid
+              lcr_ready         <= '0';
+              lcr_validity_cntr <= (others => '0');
+
+-- check if the autonegotiation unit has enabled the reception of LCR
+            elsif (an_rx_en_synced = '1') then
+              lcr_prev_val <= lcr_cur_val;
+
+-- check for 3 subsequent Configuration sequences with identical Config_Reg value
+              if(lcr_cur_val = lcr_prev_val) then
+                if(lcr_validity_cntr = "10") then
+-- we've got 3? Indicate that we have received valid Config_Reg.
+                  lcr_ready <= '1';
+                  lcr_final_val <= lcr_cur_val;
+                else
+                  lcr_validity_cntr <= lcr_validity_cntr + 1;
+                  lcr_ready         <= '0';
+                end if;
+              else
+-- the subsequent values of Config_Reg are different?
+                lcr_validity_cntr <= (others => '0');
+                lcr_ready         <= '0';
+              end if;
+
+              lcr_cur_val <= d_data(7 downto 0) & d_data(15 downto 8);
+            end if;
+
+            rx_state <= RX_NOFRAME;
+
+-------------------------------------------------------------------------------
+-- State SPD_PREAMBLE: we've received an Start-Of-Packet delimeter. Check for
+-- the valid preamble.
+-------------------------------------------------------------------------------                            
+          when RX_SPD_PREAMBLE =>
+
+            rx_busy <= '1';
+
+            if(d_err = '1' or rx_synced = '0') then  -- check for encoding errors.
+              rx_state                <= RX_NOFRAME;
+              rmon_invalid_code_p_int <= d_err;
+            else
+
+              -- keep looking for Ethernet SFD char (0xd5). If it occurs on
+              -- the right position, start receiving the frame payload
+              if d_is_preamble_sfd = '1' then
+-- generate the RX timestamp pulse
+                timestamp_trigger_p_a_o <= '1';
+
+-- we've got an SFD at proper offset from the beginning of the preamble
+                if (preamble_cntr = "010") or (preamble_cntr = "001") then
+
+-- indicate a start-of-packet condition in the RX FIFO and enable writing to
+-- the FIFO.
+                  pcs_fab_o.sof <= '1';
+                  rx_state      <= RX_PAYLOAD;
+                end if;
+                
+              elsif (d_is_preamble = '1') then
+                preamble_cntr <= preamble_cntr - 1;
+              -- got duplicated SPD code?
+              elsif (d_is_spd_preamble = '1') then
+                preamble_cntr <= "111";
+              else
+                rx_state                <= RX_NOFRAME;  -- not a preamble sequence?
+                rmon_invalid_code_p_int <= '1';
+              end if;
+
+              if(preamble_cntr = "000") then  -- too long preamble - abort reception
+                rx_state <= RX_NOFRAME;
+              end if;
+            end if;
+
+-------------------------------------------------------------------------------
+-- State PAYLOAD: receives the full frame payload (including the MAC header and
+-- the CRC)
+-------------------------------------------------------------------------------
+
+          when RX_PAYLOAD =>
+
+            pcs_fab_o.sof <= '0';
+            pcs_fab_o.eof <= '0';
+            pcs_fab_o.has_rx_timestamp <= '0';
+            pcs_fab_o.data <= d_data;
+
+            -- check for errors.
+            if (d_err = '1' or rx_synced = '0' or pcs_fifo_almostfull_i = '1'
+                or (d_is_k /= "00" and d_is_eof_extend = '0' and d_is_eof = '0')) then
+
+              -- indicate an errorneous termination of the current frame in the
+              -- RX FIFO
+              pcs_fab_o.error <= '1';
+              pcs_fab_o.dvalid <= '0';
+              pcs_fab_o.bytesel <= 'X';
+              
+              rmon_invalid_code_p_int <= d_err;
+              rmon_rx_overrun_p_int   <= pcs_fifo_almostfull_i;
+
+              rx_state <= RX_NOFRAME;
+            elsif d_is_eof = '1' or d_is_eof_extend = '1' then
+
+              pcs_fab_o.error <= '0';
+
+              if d_is_eof = '1' then    -- got EPD at even position
+                pcs_fab_o.bytesel <= '1';
+                pcs_fab_o.dvalid  <= '1';
+                rx_state          <= RX_EXTEND;
+              else
+                pcs_fab_o.bytesel <= '0';
+                pcs_fab_o.dvalid  <= '0';
+                rx_state          <= RX_EXTEND;
+              end if;
+              
+            else
+              pcs_fab_o.bytesel <= '0';
+              pcs_fab_o.error  <= '0';
+              pcs_fab_o.dvalid <= '1';
+            end if;
+
+
+-------------------------------------------------------------------------------
+-- State EXTEND: receive carrier extension
+-------------------------------------------------------------------------------
+
+          when RX_EXTEND =>
+
+            timestamp_trigger_p_a_o <= '0';
+            pcs_fab_o.dvalid  <= '0';
+
+            if d_is_extend = '1' then   -- got carrier extend. Just keep
+                                        -- receiving it.
+              rx_state        <= RX_EXTEND;
+              pcs_fab_o.eof   <= '0';
+              pcs_fab_o.error <= '0';
+            elsif d_is_idle = '1' then  -- got comma, real end-of-frame
+              -- indicate the correct ending of the current frame in the RX FIFO
+              pcs_fab_o.eof              <= not timestamp_stb_i;
+              pcs_fab_o.error            <= '0';
+              pcs_fab_o.has_rx_timestamp <= timestamp_stb_i;
+              timestamp_pending          <= (others => timestamp_stb_i);
+
+              rx_state <= RX_NOFRAME;
+            else
+              -- got anything else than comma (for example, the /V/ code):
+              pcs_fab_o.error         <= '1';
+              rmon_invalid_code_p_int <= '1';
+              rx_state                <= RX_NOFRAME;
+            end if;
+        end case;
+      end if;
+    end if;     
+  end process;
+
+  an_rx_val_o <= lcr_final_val;
+
+  U_sync_an_rx_ready : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => lcr_ready,
+      synced_o => an_rx_valid_o,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_an_idle_match : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => an_idle_match_int,
+      synced_o => an_idle_match_o,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_ext_rmon_1 : gc_extend_pulse
+    generic map (
+      g_width => 3)
+    port map (
+      clk_i      => phy_rx_clk_i,
+      rst_n_i    => rst_n_rx,
+      pulse_i    => rmon_invalid_code_p_int,
+      extended_o => rmon_rx_inv_code);
+
+  U_ext_rmon_2 : gc_extend_pulse
+    generic map (
+      g_width => 3)
+    port map (
+      clk_i      => phy_rx_clk_i,
+      rst_n_i    => rst_n_rx,
+      pulse_i    => rmon_rx_overrun_p_int,
+      extended_o => rmon_rx_overrun);
+
+-- drive the "RX PCS Sync Lost" event counter
+  rmon_rx_sync_lost <= rx_sync_lost_p and (not mdio_mcr_pdown_i);
+
+  pcs_fab_o.rx_timestamp_valid <= timestamp_valid_i;
+
+  nice_dbg_o.fsm <= "000" when (rx_state = RX_NOFRAME) else
+                    "001" when (rx_state = RX_CR) else
+                    "010" when (rx_state = RX_SPD_PREAMBLE) else
+                    "011" when (rx_state = RX_PAYLOAD) else
+                    "100" when (rx_state = RX_EXTEND) else
+                    "111";
+
+end behavioral;
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_pcs_8bit.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
new file mode 100644
index 000000000..9310cf36a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
@@ -0,0 +1,858 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000BaseT/X MAC Endpoint - receive path PCS for 1000BaseX
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : ep_rx_pcs_tbi.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2009-06-16
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Module implements the reception path for 1000BaseX PCS
+-- (Physical Coding Sublayer). It provides synchronization between the PHY RX
+-- clock and system reference clock, elastic buffering, preamble, SFD and other
+-- 8b10b patterns recognition. It also generates deterministic timestamping
+-- pulses for RXed packets.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2009-06-16  0.1      twlostow  Created (no error propagation supported yet)
+-- 2010-10-25  0.2      twlostow  Names updated to comply with the coding,
+--                                added some comments
+-- 2010-11-18  0.4      twlostow  Added support for Xilinx GTP transceivers.
+-- 2011-02-07  0.5      twlostow  Tested on Spartan6 GTP
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+
+entity ep_rx_pcs_8bit is
+  generic (
+    g_simulation : boolean);
+  port (
+-- 62.5 MHz refclk divided by 2
+    clk_sys_i : in std_logic;
+
+-- reset (refclk2-synchronous)
+    rst_n_i : in std_logic;
+
+-- reset (phy_rx_clk_i sync)
+    rst_rxclk_n_i : in std_logic;
+
+    pcs_fifo_almostfull_i : in  std_logic;
+-- RX path busy indicator (active HI).
+-- When asserted, the receiver is in the middle of reception of a frame
+    pcs_busy_o            : out std_logic;
+-- data FIFO output
+    pcs_fab_o             : out t_ep_internal_fabric;
+
+
+    timestamp_trigger_p_a_o : out std_logic;  -- strobe for RX timestamping
+
+    timestamp_i           : in  std_logic_vector(31 downto 0);
+    timestamp_stb_i       : in  std_logic;
+    timestamp_valid_i     : in  std_logic;
+
+-------------------------------------------------------------------------------
+-- PHY interface
+-------------------------------------------------------------------------------    
+
+    phy_rdy_i        : in std_logic;
+    phy_rx_clk_i     : in std_logic;
+    phy_rx_data_i    : in std_logic_vector(7 downto 0);
+    phy_rx_k_i       : in std_logic;
+    phy_rx_enc_err_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- Wishbone registers
+-------------------------------------------------------------------------------    
+
+    -- Receive control regsiter
+    mdio_mcr_reset_i           : in  std_logic;
+    mdio_mcr_pdown_i           : in  std_logic;
+    mdio_wr_spec_cal_crst_i    : in  std_logic;
+    mdio_wr_spec_rx_cal_stat_o : out std_logic;
+
+    synced_o    : out std_logic;
+    sync_lost_o : out std_logic;
+
+    -- autonegotiation signals
+    an_rx_en_i      : in  std_logic;
+    an_rx_val_o     : out std_logic_vector(15 downto 0);
+    an_rx_valid_o   : out std_logic;
+    an_idle_match_o : out std_logic;
+
+    -- RMON events
+    rmon_rx_overrun   : out std_logic;
+    rmon_rx_inv_code  : out std_logic;
+    rmon_rx_sync_lost : out std_logic
+    );
+
+end ep_rx_pcs_8bit;
+
+architecture behavioral of ep_rx_pcs_8bit is
+
+-- RX state machine definitions
+  type t_tbif_rx_state is (RX_NOFRAME, RX_COMMA, RX_CR3, RX_CR4, RX_SPD_PREAMBLE, RX_PAYLOAD, RX_EXTEND);
+
+-- size of the calibrration pattern detection counter. It counts up every time
+-- a valid calibration pattern character is received and resets upon detecion
+-- of non-calibration character. The pattern is validated when the counter
+-- overflows (after 2**c_cal_pattern_counter_bits counts)
+
+
+  function f_calc_pattern_counter_bits
+    return integer is
+  begin  -- f_calc_pattern_counter_bits
+    if(g_simulation) then
+      return 8;                         -- use smaller calibration counter to
+                                        -- speed up the simulation
+    else
+      return 17;
+    end if;
+  end f_calc_pattern_counter_bits;
+
+  constant c_cal_pattern_counter_bits : integer := f_calc_pattern_counter_bits;
+
+  component ep_sync_detect
+    port (
+      rst_n_i  : in  std_logic;
+      rbclk_i  : in  std_logic;
+      en_i     : in  std_logic;
+      data_i   : in  std_logic_vector(7 downto 0);
+      k_i      : in  std_logic;
+      err_i    : in  std_logic;
+      synced_o : out std_logic;
+      even_o   : out std_logic;
+      cal_i    : in  std_logic);
+  end component;
+
+  signal rst_n_rx : std_logic;
+
+  signal rx_state             : t_tbif_rx_state;
+  signal preamble_cntr        : unsigned(2 downto 0);
+  signal rx_busy              : std_logic;
+  signal rx_enable_synced     : std_logic;
+  signal rx_rdreq, fifo_wrreq : std_logic;
+
+  -- 8b10b decoding and postprocessing signals
+  signal d_is_k, d_err, d_is_comma, d_is_epd        : std_logic;
+  signal d_is_spd, d_is_extend, d_is_idle, d_is_lcr : std_logic;
+  signal d_is_sfd_char, d_is_preamble_char          : std_logic;
+  signal d_data                                     : std_logic_vector(7 downto 0);
+  signal d_is_even                                  : std_logic;
+  signal d_is_cal                                   : std_logic;
+
+  -- Clock alignment FIFO signals
+  signal fifo_wr_toggle     : std_logic;
+  signal fifo_rx_data       : std_logic_vector(15 downto 0);
+  signal fifo_mask_write    : std_logic;
+  signal fifo_bytesel       : std_logic;
+  signal fifo_sof, fifo_eof : std_logic;
+  signal fifo_error         : std_logic;
+  signal fifo_almostfull    : std_logic;
+  signal fifo_clear_n       : std_logic;
+  signal fifo_with_rx_ts    : std_logic;
+  signal fifo_ts_valid    : std_logic;
+
+-- Synchronization detection FSM signals
+  signal rx_synced, rx_even : std_logic;
+  signal rx_sync_lost_p     : std_logic;
+  signal rx_sync_status     : std_logic;
+  signal rx_sync_enable     : std_logic;
+
+-- Autonegotiation control signals
+  signal an_rx_en_synced : std_logic;
+
+  signal lcr_ready         : std_logic;
+  signal lcr_prev_val      : std_logic_vector(15 downto 0);
+  signal lcr_cur_val       : std_logic_vector(15 downto 0);
+  signal lcr_final_val     : std_logic_vector(15 downto 0);
+  signal lcr_validity_cntr : unsigned(1 downto 0);
+
+  signal an_idle_cntr      : unsigned(1 downto 0);
+  signal an_idle_match_int : std_logic;
+
+-- RMON counter pulses
+  signal rmon_rx_overrun_p_int   : std_logic;
+  signal rmon_invalid_code_p_int : std_logic;
+
+-- Misc. signals
+  signal cal_pattern_cntr      : unsigned(c_cal_pattern_counter_bits-1 downto 0);
+  signal mdio_mcr_reset_synced : std_logic;
+  signal mdio_mcr_pdown_synced : std_logic;
+
+
+  signal pcs_valid_int     : std_logic;
+  signal timestamp_pending : std_logic_vector(2 downto 0);
+  
+begin
+-------------------------------------------------------------------------------
+-- synchronizer chains for Wishbone-accessible control signals
+-------------------------------------------------------------------------------
+
+  U_sync_pcs_busy : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => '1',
+      data_i   => rx_busy,
+      synced_o => pcs_busy_o,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_an_rx_enable : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_rx_clk_i,
+      rst_n_i  => rst_n_rx,
+      data_i   => an_rx_en_i,
+      synced_o => an_rx_en_synced,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_mcr_reset : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_rx_clk_i,
+      rst_n_i  => '1',
+      data_i   => mdio_mcr_reset_i,
+      synced_o => mdio_mcr_reset_synced,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_power_down : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_rx_clk_i,
+      rst_n_i  => '1',
+      data_i   => mdio_mcr_pdown_i,
+      synced_o => mdio_mcr_pdown_synced,
+      npulse_o => open,
+      ppulse_o => open);
+
+  rx_sync_enable <= not mdio_mcr_pdown_synced;
+  rst_n_rx  <= rst_rxclk_n_i and not mdio_mcr_reset_synced and phy_rdy_i;
+
+-------------------------------------------------------------------------------
+-- 802.3z Link Synchronization State Machine
+-------------------------------------------------------------------------------
+
+  U_SYNC_DET : ep_sync_detect
+    port map (
+      rst_n_i  => rst_n_rx,
+      rbclk_i  => phy_rx_clk_i,
+      en_i     => rx_sync_enable,
+      data_i   => phy_rx_data_i,
+      k_i      => phy_rx_k_i,
+      err_i    => phy_rx_enc_err_i,
+      synced_o => rx_synced,
+      even_o   => rx_even,
+      cal_i    => d_is_cal);
+
+  -- synchronizer chain for rx_synced signal, also serving as a loss-of-sync detector
+  U_sync_los : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => '1',
+      data_i   => rx_synced,
+      synced_o => rx_sync_status,
+      npulse_o => rx_sync_lost_p,
+      ppulse_o => open);
+
+  synced_o    <= rx_sync_status;        -- drive the PCS outputs
+  sync_lost_o <= rx_sync_lost_p;
+
+-------------------------------------------------------------------------------
+-- Calibration pattern logic
+-------------------------------------------------------------------------------
+
+  -- process checks the presence of valid calibtaion pattern and controls the
+  -- state of CAL_STA bit in Receive Control Register.
+  --
+  -- reads: phy_rx_data_i, mdio_wr_spec_cal_crst_i
+  -- writes: mdio_wr_spec_rx_cal_stat_o
+  --
+  p_detect_cal : process(phy_rx_clk_i)
+  begin
+    if rising_edge(phy_rx_clk_i) then
+      if rst_n_rx = '0' then
+        cal_pattern_cntr <= (others => '0');
+        d_is_cal         <= '0';
+      else
+        
+        if(phy_rx_data_i = c_k28_7 and phy_rx_k_i = '1') then
+          d_is_cal <= '1';
+        else
+          d_is_cal <= '0';
+        end if;
+
+        if(d_is_cal = '1' and mdio_wr_spec_cal_crst_i = '0') then
+
+-- we've got c_cal_pattern_threshold valid calibration characters - indicate
+-- that we're receiving a valid calibration pattern
+          if(cal_pattern_cntr(cal_pattern_cntr'high) = '1') then
+            mdio_wr_spec_rx_cal_stat_o <= '1';
+          else
+            mdio_wr_spec_rx_cal_stat_o <= '0';
+            cal_pattern_cntr           <= cal_pattern_cntr + 1;
+          end if;
+-- we've got a non-calibration character or the pattern detection has been reset
+        else
+          mdio_wr_spec_rx_cal_stat_o <= '0';
+          cal_pattern_cntr           <= (others => '0');
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+-------------------------------------------------------------------------------
+-- Clock adjustment FIFO
+-------------------------------------------------------------------------------  
+
+  -- FIFO input data formatting
+  fifo_wrreq <= fifo_wr_toggle and fifo_mask_write;
+
+  pcs_fab_o.data             <= fifo_rx_data;
+  pcs_fab_o.addr             <= (others => '0');
+  pcs_fab_o.sof              <= fifo_sof and fifo_wrreq;
+  pcs_fab_o.eof              <= fifo_eof and fifo_wrreq;
+  pcs_fab_o.bytesel          <= fifo_bytesel;
+  pcs_fab_o.error            <= fifo_error and fifo_wrreq;
+  pcs_fab_o.has_rx_timestamp <= fifo_with_rx_ts;
+  pcs_fab_o.rx_timestamp_valid <= timestamp_valid_i;
+  pcs_fab_o.dvalid           <= not (fifo_sof or fifo_eof or fifo_error) and fifo_wrreq;
+
+  fifo_almostfull <= pcs_fifo_almostfull_i;
+
+  -- process postprocesses the raw 8b10b decoder output (phy_rx_data_i, phy_rx_k_i, phy_rx_enc_err_ior)
+  -- providing 1-bit signals indicating various 8b10b control patterns
+  p_8b10b_postprocess : process(phy_rx_clk_i)
+  begin
+    if rising_edge(phy_rx_clk_i) then
+      
+      if(rst_n_rx = '0') then
+        d_data             <= (others => '0');
+        d_is_comma         <= '0';
+        d_is_spd           <= '0';
+        d_is_extend        <= '0';
+        d_is_lcr           <= '0';
+        d_is_epd           <= '0';
+        d_is_idle          <= '0';
+        d_is_k             <= '0';
+        d_err              <= '0';
+        d_is_sfd_char      <= '0';
+        d_is_preamble_char <= '0';
+        d_err              <= '0';
+      else
+
+        -- store the odd/even field information from sync detection unit (U_SYNC_DET)
+        d_is_even <= rx_even;
+        d_data    <= phy_rx_data_i;
+        d_is_k    <= phy_rx_k_i;
+
+        if(phy_rx_enc_err_i = '0') then
+          d_err <= '0';
+
+-- decode commas and other control characters....
+          if(phy_rx_data_i = c_K28_5 and phy_rx_k_i = '1') then
+            d_is_comma <= '1';
+          else
+            d_is_comma <= '0';
+          end if;
+
+          if(phy_rx_data_i = c_k23_7 and phy_rx_k_i = '1') then
+            d_is_extend <= '1';
+          else
+            d_is_extend <= '0';
+          end if;
+
+          if(phy_rx_data_i = c_k27_7 and phy_rx_k_i = '1') then
+            d_is_spd <= '1';
+          else
+            d_is_spd <= '0';
+          end if;
+
+          if(phy_rx_data_i = c_K29_7 and phy_rx_k_i = '1') then
+            d_is_epd <= '1';
+          else
+            d_is_epd <= '0';
+          end if;
+
+          if((phy_rx_data_i = c_d21_5 or phy_rx_data_i = c_d2_2) and phy_rx_k_i = '0') then
+            d_is_lcr <= '1';
+          else
+            d_is_lcr <= '0';
+          end if;
+
+          if((phy_rx_data_i = c_d5_6 or phy_rx_data_i = c_d16_2) and phy_rx_k_i = '0') then
+            d_is_idle <= '1';
+          else
+            d_is_idle <= '0';
+          end if;
+
+          if(phy_rx_data_i = c_preamble_sfd and phy_rx_k_i = '0') then
+            d_is_sfd_char <= '1';
+          else
+            d_is_sfd_char <= '0';
+          end if;
+
+          if(phy_rx_data_i = c_preamble_char and phy_rx_k_i = '0') then
+            d_is_preamble_char <= '1';
+          else
+            d_is_preamble_char <= '0';
+          end if;
+
+-- invalid code received?
+        else
+          d_err              <= '1';
+          d_is_sfd_char      <= '0';
+          d_is_preamble_char <= '0';
+          d_is_comma         <= '0';
+          d_is_spd           <= '0';
+          d_is_extend        <= '0';
+          d_is_lcr           <= '0';
+          d_is_epd           <= '0';
+          d_is_idle          <= '0';
+          d_is_k             <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+-- process: RBCLK-driven RX state machine. Implements the receive logic od 802.3z compliant
+-- 1000BaseX PCS.
+-- reads: almost everything
+-- writes: almost everything
+
+  rx_fsm : process (phy_rx_clk_i)
+  begin
+    if rising_edge(phy_rx_clk_i) then
+      -- reset or PCS disabled
+      if(rst_n_rx = '0' or mdio_mcr_pdown_synced = '1') then
+        rx_state <= RX_NOFRAME;
+        rx_busy  <= '0';
+
+        fifo_sof        <= '0';
+        fifo_eof        <= '0';
+        fifo_error      <= '0';
+        fifo_wr_toggle  <= '0';
+        fifo_mask_write <= '0';
+        fifo_with_rx_ts <= '0';
+
+        lcr_ready         <= '0';
+        lcr_cur_val       <= (others => '0');
+        lcr_prev_val      <= (others => '0');
+        -- lcr_final_val ===> DO NOT CLEAR on reset
+        lcr_validity_cntr <= (others => '0');
+        an_idle_cntr      <= (others => '0');
+        an_idle_match_int <= '0';
+
+        rmon_rx_overrun_p_int   <= '0';
+        rmon_invalid_code_p_int <= '0';
+
+        timestamp_trigger_p_a_o <= '0';
+        timestamp_pending <= "000";
+      else                              -- normal PCS operation
+
+        -- clear the autogotiation variables if the autonegotiation is disabled
+        if(an_rx_en_synced = '0') then
+          lcr_ready         <= '0';
+          lcr_validity_cntr <= (others => '0');
+          lcr_prev_val      <= (others => '0');
+          an_idle_cntr      <= (others => '0');
+          an_idle_match_int <= '0';
+        end if;
+
+-------------------------------------------------------------------------------
+-- Main RX PCS state machine
+-------------------------------------------------------------------------------          
+        case rx_state is
+
+-------------------------------------------------------------------------------
+-- State NOFRAME: receiver is receiving IDLE pattern
+-------------------------------------------------------------------------------            
+          when RX_NOFRAME =>
+
+            
+            fifo_sof     <= '0';
+            fifo_eof     <= '0';
+            fifo_error   <= '0';
+            fifo_bytesel <= '0';
+
+            rx_busy           <= '0';
+            timestamp_trigger_p_a_o <= '0';
+
+            -- insert the RX timestamp into the FIFO
+            if(timestamp_pending /= "000") then
+              fifo_mask_write <= '1';
+              fifo_wr_toggle  <= '1';
+            else
+              fifo_mask_write <= '0';
+              fifo_wr_toggle  <= '0';
+            end if;
+
+            if(timestamp_pending(0) = '1')then
+              fifo_rx_data <= timestamp_i(31 downto 16);
+            elsif(timestamp_pending(1) = '1')then
+              fifo_rx_data <= timestamp_i(15 downto 0);
+            elsif(timestamp_pending(2) = '1')then
+              fifo_eof <= '1';
+            end if;
+
+            timestamp_pending <= timestamp_pending(1 downto 0) & '0';
+
+            if (rx_synced = '0') then
+-- PCS is not synced: stay in NOFRAME state and ignore the incoming codes.
+              rx_state <= RX_NOFRAME;
+
+            elsif(d_is_comma = '1') then
+-- we've got a comma character: it's probably an idle sequence or a Config_Reg value,
+-- check the next code.
+              rx_state <= RX_COMMA;
+            elsif (d_is_spd = '1') then
+-- we've got a Start-of-Packet Delimeter
+
+              if(d_is_even = '1' and fifo_almostfull = '0') then
+                preamble_cntr <= "111";
+                rx_state      <= RX_SPD_PREAMBLE;
+              elsif (fifo_almostfull = '1') then
+                rmon_rx_overrun_p_int <= '1';
+              end if;
+              
+            end if;
+
+
+-- produce a pulse at every invalid 8b10b code.
+            rmon_invalid_code_p_int <= d_err;
+
+-------------------------------------------------------------------------------
+-- State COMMA: we've received a comma character followed by something else.
+-- Determine what's "something else"
+-------------------------------------------------------------------------------                            
+
+          when RX_COMMA =>
+-- received a code with error (or a control code group) or a misaligned code:
+-- go to the initial NOFRAME state and account the error.
+
+            fifo_mask_write <= '0';
+            fifo_wr_toggle  <= '0';
+            fifo_with_rx_ts <= '0';
+
+            if (d_err = '1' or d_is_k = '1' or d_is_even = '1' or rx_synced = '0') then
+              rmon_invalid_code_p_int <= d_err;
+              rx_state                <= RX_NOFRAME;
+
+              lcr_ready         <= '0';
+              an_idle_match_int <= '0';
+              an_idle_cntr      <= (others => '0');
+            else
+
+-- don't write anything to the PCS FIFO, it's a control character
+              fifo_mask_write <= '0';
+
+-- received D5.6 or D16.2 - it's an idle pattern. Simply ignore it.
+              if(d_is_idle = '1') then
+                rx_state  <= RX_NOFRAME;
+                lcr_ready <= '0';
+
+
+                if(an_idle_cntr = "11") then
+                  an_idle_match_int <= '1';
+                else
+                  an_idle_cntr <= an_idle_cntr + 1;
+                end if;
+
+
+-- received D21.5 or D2.2 - it's a 802.3x autonegotiation Config_Reg (802.3 p.
+-- 36.2.4.10). Begin the reception of its value.
+              elsif(d_is_lcr = '1') then
+                an_idle_match_int <= '0';
+                an_idle_cntr      <= (others => '0');
+                rx_busy           <= '1';
+                rx_state          <= RX_CR3;
+              else
+                lcr_ready         <= '0';
+                an_idle_match_int <= '0';
+                an_idle_cntr      <= (others => '0');
+                lcr_validity_cntr <= (others => '0');
+              end if;
+            end if;
+
+-------------------------------------------------------------------------------
+-- States CR3/CR4: reception of LCR register value.
+-------------------------------------------------------------------------------              
+          when RX_CR3 =>  -- receives the 1st byte of Config_Reg and
+            -- checks if the subsequent Config_Reg
+            -- values are identical.
+
+-- an error? - abort the reception and go to NOFRAME state.
+            if(d_err = '1' or d_is_k = '1' or d_is_even = '0' or rx_synced = '0') then
+              rx_state                <= RX_NOFRAME;
+              rmon_invalid_code_p_int <= d_err;
+
+              -- reset the Config_Reg value and mark it as invalid
+              lcr_ready         <= '0';
+              lcr_validity_cntr <= (others => '0');
+
+-- check if the autonegotiation unit has enabled the reception of LCR
+            elsif (an_rx_en_synced = '1') then
+              lcr_prev_val <= lcr_cur_val;
+
+-- check for 3 subsequent Configuration sequences with identical Config_Reg value
+              if(lcr_cur_val = lcr_prev_val) then
+                if(lcr_validity_cntr = "10") then
+-- we've got 3? Indicate that we have received valid Config_Reg.
+                  lcr_ready <= '1';
+                  lcr_final_val <= lcr_cur_val; -- only latched here, not even on reset
+                else
+                  lcr_validity_cntr <= lcr_validity_cntr + 1;
+                  lcr_ready         <= '0';
+                end if;
+              else
+-- the subsequent values of Config_Reg are different?
+                lcr_validity_cntr <= (others => '0');
+                lcr_ready         <= '0';
+              end if;
+
+              lcr_cur_val (7 downto 0) <= d_data;
+            end if;
+
+            rx_state <= RX_CR4;
+
+          when RX_CR4 =>                -- receives the 2nd byte of LCR
+
+            if(d_err = '1' or d_is_k = '1' or d_is_even = '1' or rx_synced = '0') then
+              -- in case of an error
+              rx_state                <= RX_NOFRAME;
+              rmon_invalid_code_p_int <= d_err;
+            elsif (an_rx_en_synced = '1') then
+              -- store the value of the LSB of the Config_Reg
+              lcr_cur_val (15 downto 8) <= d_data;
+            end if;
+
+            rx_state <= RX_NOFRAME;
+
+-------------------------------------------------------------------------------
+-- State SPD_PREAMBLE: we've received an Start-Of-Packet delimeter. Check for
+-- the valid preamble.
+-------------------------------------------------------------------------------                            
+          when RX_SPD_PREAMBLE =>
+
+            rx_busy <= '1';
+
+            if(d_err = '1' or rx_synced = '0') then  -- check for encoding errors.
+              rx_state                <= RX_NOFRAME;
+              rmon_invalid_code_p_int <= d_err;
+            else
+
+              -- keep looking for Ethernet SFD char (0xd5). If it occurs on
+              -- the right position, start receiving the frame payload
+              if d_is_sfd_char = '1' then
+-- generate the RX timestamp pulse
+                timestamp_trigger_p_a_o <= '1';
+
+-- we've got an SFD at proper offset from the beginning of the preamble
+                if (preamble_cntr = "010") or (preamble_cntr = "001") then
+
+-- indicate a start-of-packet condition in the RX FIFO and enable writing to
+-- the FIFO.
+                  fifo_sof        <= '1';
+                  fifo_mask_write <= '1';
+                  fifo_wr_toggle  <= '1';
+                  rx_state        <= RX_PAYLOAD;
+                end if;
+                
+              elsif (d_is_preamble_char = '1') then
+                preamble_cntr <= preamble_cntr - 1;
+                -- got duplicated SPD code?
+              elsif (d_is_spd = '1') then
+                preamble_cntr <= "111";
+              end if;
+
+              if(preamble_cntr = "000") then  -- too long preamble - abort reception
+                rx_state <= RX_NOFRAME;
+              end if;
+            end if;
+
+-------------------------------------------------------------------------------
+-- State PAYLOAD: receives the full frame payload (including the MAC header and
+-- the CRC)
+-------------------------------------------------------------------------------
+
+          when RX_PAYLOAD =>
+
+            fifo_sof <= '0';
+
+            -- check for errors.
+            if (d_err = '1' or rx_synced = '0' or fifo_almostfull = '1') then
+              rmon_invalid_code_p_int <= d_err;
+              rmon_rx_overrun_p_int   <= fifo_almostfull;
+
+              rx_state <= RX_NOFRAME;
+
+              -- indicate an errorneous termination of the current frame in the
+              -- RX FIFO
+              fifo_error     <= '1';
+              fifo_wr_toggle <= '1';
+              
+            elsif d_is_k = '1' then
+              if d_is_epd = '1' then    -- got an EPD (End-of-packet delimeter)
+
+                fifo_bytesel   <= not fifo_wr_toggle;
+                fifo_wr_toggle <= not fifo_wr_toggle;
+
+                rx_state <= RX_EXTEND;
+
+              else
+                -- any other K-character in the middle of frame (premature
+                -- end)? - terminate the frame and indicate an error in the
+                -- RX FIFO.
+
+                if d_is_comma = '1' then  -- got link idle inside frame
+                  rx_state <= RX_COMMA;
+                else
+                  rx_state <= RX_NOFRAME;
+                end if;
+
+                fifo_error     <= '1';
+                fifo_wr_toggle <= '1';
+              end if;
+            else
+              -- got a data character. Every 2 characters, write them to the
+              -- 16-bit FIFO.
+
+              fifo_wr_toggle <= not fifo_wr_toggle;
+
+              if fifo_wr_toggle = '1' then
+                fifo_rx_data(15 downto 8) <= d_data;
+              else
+                fifo_rx_data(7 downto 0) <= d_data;
+              end if;
+            end if;
+
+-------------------------------------------------------------------------------
+-- State EXTEND: receive carrier extension
+-------------------------------------------------------------------------------
+
+          when RX_EXTEND =>
+
+            timestamp_trigger_p_a_o <= '0';
+
+            if d_is_extend = '1' then    -- got carrier extend. Just keep
+                                         -- receiving it.
+              fifo_mask_write <= '0';
+              rx_state        <= RX_EXTEND;
+            elsif d_is_comma = '1' then  -- got comma, real end-of-frame
+              -- indicate the correct ending of the current frame in the RX FIFO
+              fifo_eof          <= not timestamp_stb_i;
+              fifo_with_rx_ts   <= timestamp_stb_i;
+              fifo_mask_write   <= '1';
+              fifo_wr_toggle    <= '1';
+              timestamp_pending <= (others => timestamp_stb_i);
+
+
+              rx_state <= RX_COMMA;
+              
+            else
+              -- got anything else than comma (for example, the /V/ code):
+
+              rmon_invalid_code_p_int <= '1';
+              fifo_error              <= '1';
+              fifo_mask_write         <= '1';
+              fifo_wr_toggle          <= '1';
+
+              rx_state <= RX_NOFRAME;
+            end if;
+
+          when others => null;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  an_rx_val_o <= lcr_final_val;
+
+  U_sync_an_rx_ready : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => lcr_ready,
+      synced_o => an_rx_valid_o,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_an_idle_match : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => an_idle_match_int,
+      synced_o => an_idle_match_o,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_ext_rmon_1 : gc_extend_pulse
+    generic map (
+      g_width => 3)
+    port map (
+      clk_i      => phy_rx_clk_i,
+      rst_n_i    => rst_n_rx,
+      pulse_i    => rmon_invalid_code_p_int,
+      extended_o => rmon_rx_inv_code);
+
+  U_ext_rmon_2 : gc_extend_pulse
+    generic map (
+      g_width => 3)
+    port map (
+      clk_i      => phy_rx_clk_i,
+      rst_n_i    => rst_n_rx,
+      pulse_i    => rmon_rx_overrun_p_int,
+      extended_o => rmon_rx_overrun);
+
+-- drive the "RX PCS Sync Lost" event counter
+  rmon_rx_sync_lost <= rx_sync_lost_p and (not mdio_mcr_pdown_i);
+
+end behavioral;
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_status_reg_insert.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
new file mode 100644
index 000000000..974c2659b
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
@@ -0,0 +1,153 @@
+-------------------------------------------------------------------------------
+-- Title      : RX Status Register Inserter
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_rx_status_reg_insert.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 - 2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_fabric_pkg.all;
+
+entity ep_rx_status_reg_insert is
+  
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    snk_fab_i  : in  t_ep_internal_fabric;
+    snk_dreq_o : out std_logic;
+
+    src_fab_o  : out t_ep_internal_fabric;
+    src_dreq_i : in  std_logic;
+
+    mbuf_valid_i    : in  std_logic;
+    mbuf_ack_o      : out std_logic;
+    mbuf_drop_i     : in  std_logic;
+    mbuf_pclass_i   : in  std_logic_vector(7 downto 0);
+    mbuf_is_hp_i    : in  std_logic;
+    mbuf_is_pause_i : in  std_logic;
+
+    rmon_pfilter_drop_o : out std_logic
+    );
+
+end ep_rx_status_reg_insert;
+
+architecture rtl of ep_rx_status_reg_insert is
+
+  type t_state is (WAIT_FRAME, WAIT_MBUF, GEN_STATUS);
+
+  signal dreq_mask    : std_logic;
+  signal embed_status : std_logic;
+  signal sreg         : t_wrf_status_reg;
+  signal state        : t_state;
+  signal src_fab_out  : t_ep_internal_fabric;
+
+  signal sof_mask : std_logic;
+  
+begin  -- rtl
+  
+  embed_status     <= '1'                         when (state = GEN_STATUS) else '0';
+  src_fab_out.data <= f_marshall_wrf_status(sreg) when (embed_status = '1') else snk_fab_i.data;
+  src_fab_out.addr <= c_WRF_STATUS                when (embed_status = '1') else snk_fab_i.addr;
+
+  src_fab_out.eof     <= snk_fab_i.eof;
+  src_fab_out.error   <= snk_fab_i.error;
+  src_fab_out.bytesel <= snk_fab_i.bytesel;
+  src_fab_out.dvalid  <= snk_fab_i.dvalid or (embed_status and src_dreq_i);
+
+  src_fab_out.has_rx_timestamp   <= snk_fab_i.has_rx_timestamp;
+  src_fab_out.rx_timestamp_valid <= snk_fab_i.rx_timestamp_valid;
+
+  src_fab_o <= src_fab_out;
+
+  src_fab_out.sof <= '1' when (mbuf_valid_i = '1' and state = WAIT_MBUF and mbuf_drop_i = '0' and mbuf_is_pause_i = '0') else '0';
+  mbuf_ack_o      <= '1' when (mbuf_valid_i = '1' and state = WAIT_MBUF)                                                 else '0';
+
+  snk_dreq_o <= src_dreq_i and dreq_mask and not snk_fab_i.sof;
+--   snk_dreq_o <= src_dreq_i and not snk_fab_i.sof;
+
+  p_gen_status : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        rmon_pfilter_drop_o <= '0';
+        state     <= WAIT_FRAME;
+        dreq_mask <= '1';
+        sreg.match_class <= (others =>'0');
+        sreg.is_hp       <= '0';
+        sreg.has_crc     <= '0';
+        sreg.has_smac    <= '0';
+        sreg.error       <= '0';        
+      else
+        case state is
+          when WAIT_FRAME =>
+            rmon_pfilter_drop_o <= '0';
+            if(snk_fab_i.sof = '1') then
+              state     <= WAIT_MBUF;
+              dreq_mask <= '0';
+            end if;
+            
+          when WAIT_MBUF =>
+            if(mbuf_valid_i = '1') then
+                rmon_pfilter_drop_o <= mbuf_drop_i;
+
+                if(mbuf_drop_i = '0' and mbuf_is_pause_i = '0') then
+                  state <= GEN_STATUS;
+                  dreq_mask <= '1';
+                else
+                  state <= WAIT_FRAME;
+                  dreq_mask <= '1';
+                end if;
+
+                sreg.match_class <= mbuf_pclass_i;
+                sreg.is_hp       <= mbuf_is_hp_i;
+                sreg.has_crc     <= '0';
+                sreg.has_smac    <= '1';
+                sreg.error       <= '0';
+            else
+              rmon_pfilter_drop_o <= '0';
+              --rmon_o.rx_path_timing_failure <= '0';
+            end if;
+            
+          when GEN_STATUS =>
+            rmon_pfilter_drop_o <= '0';
+            if(src_dreq_i = '1') then
+              state     <= WAIT_FRAME;
+              dreq_mask <= '1';
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_vlan_unit.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_vlan_unit.vhd
new file mode 100644
index 000000000..ed027d6dc
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_vlan_unit.vhd
@@ -0,0 +1,449 @@
+-------------------------------------------------------------------------------
+-- Title      : RX VLAN unit
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_rx_vlan_unit.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011-2015 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+use work.wr_fabric_pkg.all;
+
+
+-- 3rd deframing pipeline stage - VLAN Unit
+
+entity ep_rx_vlan_unit is
+  port(clk_sys_i : in std_logic;
+       rst_n_i   : in std_logic;
+
+       snk_fab_i  : in  t_ep_internal_fabric;
+       snk_dreq_o : out std_logic;
+
+       src_fab_o  : out t_ep_internal_fabric;
+       src_dreq_i : in  std_logic;
+
+       tclass_o   : out std_logic_vector(2 downto 0);
+       vid_o      : out std_logic_vector(11 downto 0);
+       tag_done_o : out std_logic;
+       is_tagged_o: out std_logic;
+
+       regs_i : in    t_ep_out_registers;
+       regs_o : out   t_ep_in_registers
+       );
+
+end ep_rx_vlan_unit;
+
+architecture behavioral of ep_rx_vlan_unit is
+
+  
+  type t_tag_type is (NONE, PRIO, VLAN, NULL_VLAN);
+  type t_state is (WAIT_FRAME, DATA, FLUSH_STALL, DISCARD_FRAME, INSERT_TAG, END_FRAME);
+
+  signal dreq_mask  : std_logic;
+  signal hdr_offset : std_logic_vector(11 downto 0);
+
+  signal comb_tag_type : t_tag_type;
+
+  signal tag_type : t_tag_type;
+  signal state    : t_state;
+
+  signal at_ethertype     : std_logic;
+  signal at_vid           : std_logic;
+  signal at_tpid          : std_logic;
+  signal is_tagged        : std_logic;
+  signal stored_ethertype : std_logic_vector(15 downto 0);
+  signal stored_fab       : t_ep_internal_fabric;
+
+  signal prio_int     : std_logic_vector(2 downto 0);
+  signal force_dvalid : std_logic;
+
+  signal r_tcar_pcp_map : std_logic_vector(23 downto 0);
+  signal is_tag_inserted: std_logic;
+
+  procedure f_vlan_decision
+    (tag_type       :     t_tag_type;
+     qmode          : in  std_logic_vector(1 downto 0);
+     admit          : out std_logic;
+     use_pvid       : out std_logic;
+     use_fixed_prio : out std_logic) is
+  begin
+
+    use_pvid       := 'X';
+    use_fixed_prio := 'X';
+    admit          := '0';
+
+    -- From Jose's table. Thanks a lot!
+    case (qmode) is
+      when c_QMODE_PORT_ACCESS =>
+        case tag_type is
+          when NONE =>
+            admit := '1'; use_pvid := '1'; use_fixed_prio := '1';
+          when PRIO =>
+            admit := '1'; use_pvid := '1'; use_fixed_prio := '0';
+          when VLAN =>
+            admit := '0'; use_pvid := '0';
+          when NULL_VLAN =>
+            admit := '0';
+        end case;
+
+      when c_QMODE_PORT_TRUNK =>
+        case tag_type is
+          when NONE =>
+            admit := '0';
+          when PRIO =>
+            admit := '0';
+          when VLAN =>
+            admit          := '1';
+            use_pvid       := '0';
+            use_fixed_prio := '0';
+          when NULL_VLAN =>
+            admit := '0';
+        end case;
+
+      when c_QMODE_PORT_UNQUALIFIED =>
+        
+        case tag_type is
+          when NONE =>
+            admit    := '1';
+            use_pvid := '1'; use_fixed_prio := '1';
+          when PRIO =>
+            admit    := '1';
+            use_pvid := '1'; use_fixed_prio := '0';
+          when VLAN =>
+            admit    := '1';
+            use_pvid := '0'; use_fixed_prio := '0';
+          when NULL_VLAN =>
+            admit := '0';
+        end case;
+
+      when c_QMODE_PORT_VLAN_DISABLED =>
+        case tag_type is
+          when NONE =>
+            admit          := '1';
+            use_pvid       := '0';
+            use_fixed_prio := '1';
+          when PRIO =>
+            admit          := '1';
+            use_pvid       := '0';
+            use_fixed_prio := '0';
+          when VLAN =>
+            admit          := '1';
+            use_pvid       := '0';
+            use_fixed_prio := '0';
+          when NULL_VLAN =>
+            admit          := '1';
+            use_pvid       := '0';
+            use_fixed_prio := '0';
+        end case;
+      when others => null;
+    end case;
+  end procedure;
+
+  
+begin  -- behavioral
+
+  at_ethertype <= hdr_offset(6) and snk_fab_i.dvalid;
+  at_tpid      <= hdr_offset(6) and snk_fab_i.dvalid and is_tagged;--unused 
+  at_vid       <= hdr_offset(7) and snk_fab_i.dvalid and is_tagged;
+
+  snk_dreq_o <= src_dreq_i and dreq_mask;-- and not at_ethertype;
+
+  p_decode_tag_type : process(snk_fab_i, is_tagged)
+  begin
+    if(is_tagged = '0') then
+      comb_tag_type <= NONE;
+    else
+      case snk_fab_i.data(11 downto 0) is
+        when x"000" => comb_tag_type <= PRIO;
+        when x"fff" => comb_tag_type <= NULL_VLAN;
+        when others => comb_tag_type <= VLAN;
+      end case;
+    end if;
+  end process;
+
+  p_tag_untag : process(clk_sys_i)
+    variable admit, use_pvid, use_fixed_prio : std_logic;
+    variable v_dreq_mask                     : std_logic;
+    variable v_stored_fab                    : t_ep_internal_fabric;
+    variable v_src_fab                       : t_ep_internal_fabric;
+    variable v_next_state                    : t_state;
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' or regs_i.ecr_rx_en_o = '0' then
+        hdr_offset(hdr_offset'left downto 1) <= (others => '0');
+        hdr_offset(0)    <= '1';
+        state            <= WAIT_FRAME;
+        dreq_mask        <= '0';
+        vid_o            <= (others =>'0');
+        is_tag_inserted  <= '0';
+        is_tagged        <= '0';
+        src_fab_o.eof    <= '0';
+        src_fab_o.error  <= '0';
+        src_fab_o.dvalid <= '0';
+        
+      else
+        if(snk_fab_i.error = '1') then
+          state <= DISCARD_FRAME;
+        else
+
+          case state is
+            when WAIT_FRAME =>
+              dreq_mask       <= '1';
+              src_fab_o.eof   <= '0';
+              src_fab_o.error <= '0';
+              is_tagged       <= '0';
+              is_tag_inserted <= '0';
+              prio_int        <= regs_i.vcr0_prio_val_o;
+              vid_o           <= (others =>'0');
+
+              if(snk_fab_i.sof = '1') then
+                hdr_offset(hdr_offset'left downto 1) <= (others => '0');
+                hdr_offset(0)                        <= '1';
+                state                                <= DATA;
+              end if;
+
+            when DATA =>
+
+              v_dreq_mask     := '1';
+              v_src_fab.eof   := '0';
+              v_src_fab.error := '0';
+              v_next_state    := DATA;
+
+              if (snk_fab_i.dvalid = '1' and src_dreq_i = '0') then
+                v_stored_fab.bytesel := snk_fab_i.bytesel;
+                v_stored_fab.data    := snk_fab_i.data;
+                v_stored_fab.addr    := snk_fab_i.addr;
+                v_stored_fab.dvalid  := '1';
+                v_next_state         := FLUSH_STALL;
+              else
+                v_src_fab.addr    := snk_fab_i.addr;
+                v_src_fab.data    := snk_fab_i.data;
+                v_src_fab.dvalid  := src_dreq_i and snk_fab_i.dvalid;
+                v_src_fab.bytesel := snk_fab_i.bytesel;
+              end if;
+
+              if(at_ethertype = '1') then
+                stored_ethertype <= snk_fab_i.data;
+
+                if(snk_fab_i.data = x"8100") then  -- got a 802.1q tagged frame
+                  is_tagged <= '1';
+                else
+                  if (regs_i.vcr0_qmode_o = c_QMODE_PORT_ACCESS) then
+                    prio_int <= regs_i.vcr0_prio_val_o;
+                    is_tag_inserted  <= '1';
+                    v_src_fab.dvalid := '0';
+                    v_next_state     := INSERT_TAG;
+                    v_dreq_mask      := '0';
+                  elsif (regs_i.vcr0_qmode_o = c_QMODE_PORT_TRUNK) then
+                    v_src_fab.dvalid := '0';
+                    v_next_state     := DISCARD_FRAME;
+                  end if;
+                  is_tagged <= '0';
+                end if;
+              end if;
+
+              if(snk_fab_i.eof = '1') then
+                if(src_dreq_i = '1') then
+                  v_src_fab.eof := '1';
+                  v_next_state  := WAIT_FRAME;
+                else
+                  v_next_state := END_FRAME;
+                end if;
+              end if;
+
+              if(at_vid = '1') then
+
+                -- decide what to do with the frame, basing on the port mode
+                -- (ACCESS, TRUNK, UNQUALIFIED), and whether the frame is tagged
+                -- or not.
+                f_vlan_decision(comb_tag_type, regs_i.vcr0_qmode_o, admit, use_pvid, use_fixed_prio);
+
+                -- assign the VID
+                if(admit = '0') then    -- oops...
+                  v_next_state := DISCARD_FRAME;
+                end if;
+
+                if(use_pvid = '1')then
+                  v_stored_fab.data(11 downto 0) := regs_i.vcr0_pvid_o;
+                  v_src_fab.data(11 downto 0)    := regs_i.vcr0_pvid_o;
+                end if;
+                vid_o   <= v_src_fab.data(11 downto 0);
+                -- assign the priority 
+                if(regs_i.vcr0_fix_prio_o = '1' or use_fixed_prio = '1') then
+                  -- Forced priority (or a non-priority tagged frame)? Take the priority
+                  -- value from VCR0 register
+                  prio_int <= regs_i.vcr0_prio_val_o;
+                else
+                  -- Got a priority tag - use the value from the VLAN tag
+                  prio_int <= snk_fab_i.data(15 downto 13);
+                end if;
+              end if;
+
+              if(snk_fab_i.dvalid = '1') then
+                hdr_offset <= hdr_offset(hdr_offset'left-1 downto 0) & '0';
+              end if;
+
+              if(v_next_state = INSERT_TAG) then
+                src_fab_o.eof     <= '0';              
+                src_fab_o.dvalid  <= '1';
+                src_fab_o.error   <= '0';
+                src_fab_o.addr    <= c_WRF_DATA;
+                src_fab_o.data    <= x"8100";
+                src_fab_o.bytesel <= '0';
+              else
+                src_fab_o.eof     <= v_src_fab.eof;              
+                src_fab_o.dvalid  <= v_src_fab.dvalid;
+                src_fab_o.error   <= v_src_fab.error;
+                src_fab_o.addr    <= v_src_fab.addr;
+                src_fab_o.data    <= v_src_fab.data;
+                src_fab_o.bytesel <= v_src_fab.bytesel;
+              end if;
+
+              dreq_mask  <= v_dreq_mask;
+              stored_fab <= v_stored_fab;
+              state      <= v_next_state;
+              
+            when END_FRAME =>
+              if(src_dreq_i = '1')then
+                src_fab_o.eof    <= '1';
+                src_fab_o.dvalid <= '0';
+                state            <= WAIT_FRAME;
+              end if;
+              
+            when DISCARD_FRAME =>
+              if(src_dreq_i = '1') then
+                src_fab_o.error  <= '1';
+                src_fab_o.dvalid <= '0';
+                state            <= WAIT_FRAME;
+              end if;
+
+            when FLUSH_STALL =>
+              if(src_dreq_i = '1')then
+                src_fab_o.addr    <= stored_fab.addr;
+                src_fab_o.data    <= stored_fab.data;
+                src_fab_o.dvalid  <= stored_fab.dvalid;
+                src_fab_o.bytesel <= stored_fab.bytesel;
+                state             <= DATA;
+              else
+                src_fab_o.DATA   <= (others => 'X');
+                src_fab_o.dvalid <= '0';
+              end if;
+
+            when INSERT_TAG =>
+              src_fab_o.dvalid <= '0';
+
+              if(src_dreq_i = '1') then
+-- we are at 7th word from the beginning of the frame, but the sink reception
+-- is disabled, so we can insert the original ethertype as the TPID
+
+                if(hdr_offset(7) = '1') then
+                  src_fab_o.addr   <= c_WRF_DATA;
+                  src_fab_o.data   <= regs_i.vcr0_prio_val_o & '0' & regs_i.vcr0_pvid_o;
+                  src_fab_o.dvalid <= '1';
+                  vid_o            <= regs_i.vcr0_pvid_o; -- use the inserted PVID
+                  dreq_mask        <= '0';
+                  stored_fab.bytesel <= snk_fab_i.bytesel;
+                  stored_fab.data    <= snk_fab_i.data;
+                  stored_fab.addr    <= snk_fab_i.addr;
+                  stored_fab.dvalid  <= snk_fab_i.dvalid;
+
+                end if;
+
+                if(hdr_offset(8) = '1') then
+                  src_fab_o.addr   <= c_WRF_DATA;
+                  src_fab_o.data   <= stored_ethertype;
+                  src_fab_o.dvalid <= '1';
+                  dreq_mask        <= '1';
+                end if;
+
+                if(hdr_offset(9) = '1') then
+                  src_fab_o.addr    <= stored_fab.addr;
+                  src_fab_o.data    <= stored_fab.data;
+                  src_fab_o.dvalid  <= stored_fab.dvalid;
+                  src_fab_o.bytesel <= stored_fab.bytesel;
+                  dreq_mask        <= '1';
+                  state            <= DATA;                  
+                end if;
+
+                hdr_offset <= hdr_offset(hdr_offset'left-1 downto 0) & '0';
+              else
+                src_fab_o.dvalid <= '0';
+              end if;
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+-- Process: p_map_prio_to_tc
+-- Maps the PCP value from the 802.1q header into a traffic class for further
+-- processing. The mapping table is stored in TCAR register.
+
+  regs_o.tcar_pcp_map_i <= r_tcar_pcp_map;
+
+  p_map_prio_to_tc : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+
+      if(regs_i.tcar_pcp_map_load_o = '1') then
+        r_tcar_pcp_map <= regs_i.tcar_pcp_map_o;
+      end if;
+
+      if(rst_n_i = '0' or regs_i.ecr_rx_en_o = '0' or snk_fab_i.sof = '1')then
+        tag_done_o <= '0';
+        tclass_o   <= "000";
+      elsif(hdr_offset(9) = '1') then
+        -- we're already after the headers, so prio_int is
+        -- certainly valid
+        tag_done_o <= '1';
+        case prio_int is
+          when "000"  => tclass_o <= r_tcar_pcp_map(2 downto 0);
+          when "001"  => tclass_o <= r_tcar_pcp_map(5 downto 3);
+          when "010"  => tclass_o <= r_tcar_pcp_map(8 downto 6);
+          when "011"  => tclass_o <= r_tcar_pcp_map(11 downto 9);
+          when "100"  => tclass_o <= r_tcar_pcp_map(14 downto 12);
+          when "101"  => tclass_o <= r_tcar_pcp_map(17 downto 15);
+          when "110"  => tclass_o <= r_tcar_pcp_map(20 downto 18);
+          when "111"  => tclass_o <= r_tcar_pcp_map(23 downto 21);
+          when others => tclass_o <= "000";--"XXX";  -- packet probably contains porn
+        end case;
+      end if;
+    end if;
+  end process;
+
+  src_fab_o.sof <= regs_i.ecr_rx_en_o and snk_fab_i.sof;
+  is_tagged_o   <= is_tagged or is_tag_inserted;
+  
+end behavioral;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_wb_master.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_wb_master.vhd
new file mode 100644
index 000000000..b496ee3b7
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_rx_wb_master.vhd
@@ -0,0 +1,226 @@
+-------------------------------------------------------------------------------
+-- Title      : White Rabbit MAC/Endpoint 
+-- Project    : White Rabbit Switch 
+-------------------------------------------------------------------------------
+-- File       : ep_rx_wb_master
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2009-06-22
+-- Last update: 2017-02-02
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: RX Wishbone Master. Converts the internal fabric (DREQ-VALID
+-- throttling) to Pipelined Wishbone (b4)
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author  Description
+-- 2011-08-22  0.1      twlostow  Created
+------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_fabric_pkg.all;
+
+entity ep_rx_wb_master is
+  generic(
+    g_ignore_ack   : boolean := true;
+    g_cyc_on_stall : boolean := false);
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+-- physical coding sublayer (PCS) interface
+    snk_fab_i  : in  t_ep_internal_fabric;
+    snk_dreq_o : out std_logic;
+
+-- Wishbone I/O (master)
+    src_wb_i : in  t_wrf_source_in;
+    src_wb_o : out t_wrf_source_out
+    );
+
+end ep_rx_wb_master;
+
+architecture behavioral of ep_rx_wb_master is
+
+  type t_state is (IDLE, DATA, FLUSH_STALL, FINISH_CYCLE, THROW_ERROR);
+
+  signal state       : t_state;
+  signal ack_count   : unsigned(3 downto 0);
+  signal src_out_int : t_wrf_source_out;
+
+  signal tmp_sel : std_logic;
+  signal tmp_dat : std_logic_vector(15 downto 0);
+  signal tmp_adr : std_logic_vector(1 downto 0);
+  signal enter_idle : std_logic;
+  signal sof_reg  : std_logic;
+
+begin  -- behavioral
+  
+  gen_cyc_on_stall: if g_cyc_on_stall = true generate
+    snk_dreq_o <= '1' when ((src_wb_i.stall = '0' and state /= FINISH_CYCLE and
+                  state /= THROW_ERROR and snk_fab_i.eof = '0' and snk_fab_i.error = '0' and snk_fab_i.sof = '0' and enter_idle = '0') or state = IDLE) else '0';
+  end generate;
+
+  gen_nocyc_on_stall: if g_cyc_on_stall = false generate
+--     snk_dreq_o <= '1' when (src_wb_i.stall = '0' and state /= FINISH_CYCLE and snk_fab_i.eof = '0' and snk_fab_i.error = '0' and snk_fab_i.sof = '0' and enter_idle = '0') else '0';
+--     snk_dreq_o <= '1' when (src_wb_i.stall = '0' and state /= FINISH_CYCLE and snk_fab_i.eof = '0' and snk_fab_i.error = '0' and enter_idle = '0') else '0';
+    snk_dreq_o <= '1' when (src_wb_i.stall = '0' and state /= FINISH_CYCLE and
+                  state /= THROW_ERROR and snk_fab_i.eof = '0' and snk_fab_i.error = '0') else '0';
+  end generate;
+
+  p_count_acks : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' or src_out_int.cyc = '0' then
+        ack_count <= (others => '0');
+      else
+        if(src_out_int.stb = '1' and src_wb_i.stall = '0' and src_wb_i.ack = '0') then
+          ack_count <= ack_count + 1;
+        elsif(src_wb_i.ack = '1' and not(src_out_int.stb = '1' and src_wb_i.stall = '0')) then
+          ack_count <= ack_count - 1;
+        end if;
+        
+      end if;
+    end if;
+  end process;
+
+  process(clk_sys_i)
+    variable stat : t_wrf_status_reg := c_wrf_status_init_value;
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state           <= IDLE;
+        src_out_int.stb <= '0';
+        src_out_int.we  <= '1';
+        src_out_int.adr <= c_WRF_DATA;
+        src_out_int.cyc <= '0';
+        enter_idle <= '1';
+        sof_reg    <= '0';
+      else
+        case state is
+          when IDLE =>
+            enter_idle <= '0';
+            src_out_int.adr <= snk_fab_i.addr;
+            src_out_int.dat <= snk_fab_i.data;
+
+            if((snk_fab_i.sof='1' or sof_reg='1') and src_wb_i.err = '0') then
+              src_out_int.cyc <= '1';
+              state           <= DATA;
+            end if;
+            
+          when DATA =>
+            sof_reg <= '0';
+            if(src_wb_i.stall = '0') then
+              src_out_int.adr <= snk_fab_i.addr;
+              src_out_int.dat    <= snk_fab_i.data;
+              src_out_int.stb    <= snk_fab_i.dvalid;
+              src_out_int.sel(1) <= '1';
+              src_out_int.sel(0) <= not snk_fab_i.bytesel;
+            end if;
+
+
+            if(src_wb_i.err = '1') then
+              state <= IDLE;
+              enter_idle <= '1';
+              src_out_int.cyc <= '0';
+              src_out_int.stb <= '0';
+            elsif(snk_fab_i.error = '1') then
+              state <= THROW_ERROR;
+            elsif(src_wb_i.stall = '1' and snk_fab_i.dvalid = '1') then
+              state <= FLUSH_STALL;
+            end if;
+
+            if(snk_fab_i.eof = '1')then
+              state <= FINISH_CYCLE;
+            end if;
+
+            
+            
+            tmp_adr <= snk_fab_i.addr;
+            tmp_dat <= snk_fab_i.data;
+            tmp_sel <= snk_fab_i.bytesel;
+
+          when FLUSH_STALL =>
+            if(src_wb_i.err = '1') then
+              state <= IDLE;
+              enter_idle <= '1';
+              src_out_int.cyc <= '0';
+              src_out_int.stb <= '0';
+            elsif(src_wb_i.stall = '0') then
+              src_out_int.dat    <= tmp_dat;
+              src_out_int.adr    <= tmp_adr;
+              src_out_int.stb    <= '1';
+              src_out_int.sel(1) <= '1';
+              src_out_int.sel(0) <= not tmp_sel;
+              state              <= DATA;
+            end if;
+
+          when THROW_ERROR =>
+            if(snk_fab_i.sof='1') then
+              sof_reg <= '1';
+            end if;
+            if(src_wb_i.err = '1') then
+              enter_idle <= '1';
+              state <= IDLE;
+              src_out_int.cyc <= '0';
+              src_out_int.stb <= '0';
+            elsif(src_wb_i.stall = '0') then
+              stat.error      := '1';
+              src_out_int.adr <= c_WRF_STATUS;
+              src_out_int.dat <= f_marshall_wrf_status(stat);
+              src_out_int.stb <= '1';
+              state           <= FINISH_CYCLE;
+            end if;
+              
+            
+          when FINISH_CYCLE =>
+            if(snk_fab_i.sof='1') then
+              sof_reg <= '1';
+            end if;
+            if(src_wb_i.stall = '0') then
+              src_out_int.stb <= '0';
+            end if;
+
+            if(((ack_count = 0) or g_ignore_ack) and src_out_int.stb = '0') then
+              src_out_int.cyc <= '0';
+              enter_idle <= '1';
+              state           <= IDLE;
+            end if;
+          when others => null;
+        end case;
+      end if;
+    end if;
+  end process;
+
+
+  src_wb_o <= src_out_int;
+  
+end behavioral;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_sync_detect.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_sync_detect.vhd
new file mode 100644
index 000000000..cf0be4e9a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_sync_detect.vhd
@@ -0,0 +1,280 @@
+-------------------------------------------------------------------------------
+-- Title      : 802.3x 1000base-X compatible synchronization detect unit
+-- Project    : WhiteRabbit Switch
+-------------------------------------------------------------------------------
+-- File       : ep_sync_detect.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-05-28
+-- Last update: 2012-04-27
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description: Module implements a link synchronization detect state machine
+-- compatible with 802.3x spec.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2010-05-28  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.endpoint_private_pkg.all;
+
+entity ep_sync_detect is
+  
+  port (
+-- reset, synchronous to rbclk_i, active LOW
+    rst_n_i  : in  std_logic;
+-- recovered byte clock
+    rbclk_i  : in  std_logic;
+-- enable, active HI
+    en_i     : in  std_logic;
+-- decoded data input, active HI
+    data_i   : in  std_logic_vector(7 downto 0);
+-- decoded K signal, active HI
+    k_i      : in  std_logic;
+-- 8b10b coding error indication, active HI
+    err_i    : in  std_logic;
+-- sync detect output, active HI
+    synced_o : out std_logic;
+-- odd/even field indicator (HI = even field)
+    even_o   : out std_logic;
+
+    cal_i: in std_logic
+    );
+
+end ep_sync_detect;
+
+architecture behavioral of ep_sync_detect is
+
+  type t_sync_fsm_state is (LOSS_OF_SYNC, COMMA_DETECT_1, ACQUIRE_SYNC_1, COMMA_DETECT_2, ACQUIRE_SYNC_2, COMMA_DETECT_3, SYNC_ACQUIRED_1, SYNC_ACQUIRED_2, SYNC_ACQUIRED_3, SYNC_ACQUIRED_4, SYNC_ACQUIRED_2A, SYNC_ACQUIRED_3A, SYNC_ACQUIRED_4A);
+
+  signal state      : t_sync_fsm_state;
+  signal cggood     : std_logic;
+  signal cgbad      : std_logic;
+  signal comma      : std_logic;
+  signal rx_even    : std_logic;
+  signal is_d       : std_logic;
+  signal is_k       : std_logic;
+  signal is_k28_5   : std_logic;
+  signal good_cgs   : unsigned(2 downto 0);
+  
+  
+begin  -- behavioral
+
+
+  is_k28_5 <= '1' when data_i = c_k28_5 else '0';
+  is_d     <= (not k_i);
+
+  comma <= is_k28_5;
+
+--  cgbad <= err_i or (k_i and comma and rx_even);
+
+  cgbad  <= err_i or (k_i and comma and (not rx_even));
+  cggood <= not (err_i or (k_i and comma and (not rx_even)));
+
+  even_o <= rx_even;
+
+-- fixme!
+
+  -- 1000base-x sync detect state machine
+  -- as defined in 802.3-2008, figure 36-9.
+
+
+  sync_fsm : process (rbclk_i, rst_n_i)
+  begin  -- process sync_fsm
+    if rising_edge(rbclk_i) then
+      if(rst_n_i = '0') then
+        state      <= LOSS_OF_SYNC;
+        synced_o   <= '0';
+        rx_even    <= '0';
+        good_cgs   <= (others => '0');
+      else
+        if(en_i = '0') then
+          state      <= LOSS_OF_SYNC;
+          synced_o   <= '0';
+          rx_even    <= '0';
+          good_cgs   <= (others => '0');
+        else
+
+          -- prevents from 
+          if(cal_i = '0') then  
+            
+            case state is
+              when LOSS_OF_SYNC =>
+                synced_o <= '0';
+                if(comma = '1') then
+                  rx_even <= '0';
+                  state <= COMMA_DETECT_1;
+                else
+                  rx_even  <= not rx_even;
+                end if;
+
+              when COMMA_DETECT_1 =>
+                rx_even <= not rx_even;
+                if(is_d = '1') then     -- got data
+                  state <= ACQUIRE_SYNC_1;
+                else
+                  state <= LOSS_OF_SYNC;
+                end if;
+
+              when ACQUIRE_SYNC_1 =>
+                if(cgbad = '1') then
+                  state <= LOSS_OF_SYNC;
+                  rx_even <= not rx_even;
+                elsif (rx_even = '1' and comma = '1') then
+                  rx_even <= '0';         -- was 1
+                  state <= COMMA_DETECT_2;
+                else
+                  rx_even <= not rx_even;
+                end if;
+
+              when COMMA_DETECT_2 =>
+                rx_even <= not rx_even;
+                if(is_d = '1') then
+                  state <= ACQUIRE_SYNC_2;
+                else
+                  state <= LOSS_OF_SYNC;
+                end if;
+
+              when ACQUIRE_SYNC_2 =>
+                if(cgbad = '1') then
+                  rx_even <= not rx_even;
+                  state <= LOSS_OF_SYNC;
+                elsif (rx_even = '1' and comma = '1') then
+                  state <= COMMA_DETECT_3;
+                  rx_even <= '0';
+                else
+                  rx_even <= not rx_even;
+                end if;
+
+              when COMMA_DETECT_3 =>
+                rx_even <= not rx_even;
+                if(is_d = '1') then
+                  state <= SYNC_ACQUIRED_1;
+                else
+                  state <= LOSS_OF_SYNC;
+                end if;
+
+              when SYNC_ACQUIRED_1 =>
+                synced_o <= '1';
+                rx_even  <= not rx_even;
+
+                if(cggood = '1') then
+                  state <= SYNC_ACQUIRED_1;
+                end if;
+
+                if (cgbad = '1') then
+                  state <= SYNC_ACQUIRED_2;
+                end if;
+
+              when SYNC_ACQUIRED_2 =>
+                rx_even  <= not rx_even;
+                good_cgs <= (others => '0');
+
+                if(cggood = '1') then
+                  state <= SYNC_ACQUIRED_2A;
+                end if;
+
+                if(cgbad = '1') then
+                  state <= SYNC_ACQUIRED_3;
+                end if;
+
+              when SYNC_ACQUIRED_2A =>
+                rx_even  <= not rx_even;
+                good_cgs <= good_cgs + 1;
+
+                if(good_cgs = "011" and cggood = '1') then
+                  state <= SYNC_ACQUIRED_1;
+                end if;
+
+                if(cgbad = '1') then
+                  state <= SYNC_ACQUIRED_3;
+                end if;
+
+              when SYNC_ACQUIRED_3 =>
+                rx_even  <= not rx_even;
+                good_cgs <= (others => '0');
+
+                if(cggood = '1') then
+                  state <= SYNC_ACQUIRED_3A;
+                end if;
+
+                if(cgbad = '1') then
+                  state <= SYNC_ACQUIRED_4;
+                end if;
+                
+              when SYNC_ACQUIRED_3A =>
+                rx_even  <= not rx_even;
+                good_cgs <= good_cgs + 1;
+
+                if(good_cgs = "011" and cggood = '1') then
+                  state <= SYNC_ACQUIRED_2;
+                end if;
+
+                if(cgbad = '1') then
+                  state <= SYNC_ACQUIRED_4;
+                end if;
+
+              when SYNC_ACQUIRED_4 =>
+                rx_even  <= not rx_even;
+                good_cgs <= (others => '0');
+
+                if(cggood = '1') then
+                  state <= SYNC_ACQUIRED_4A;
+                end if;
+
+                if(cgbad = '1') then
+                  state <= LOSS_OF_SYNC;
+                end if;
+
+              when SYNC_ACQUIRED_4A =>
+                rx_even  <= not rx_even;
+                good_cgs <= good_cgs + 1;
+
+                if(good_cgs = "011" and cggood = '1') then
+                  state <= SYNC_ACQUIRED_3;
+                end if;
+
+                if (cgbad = '1') then
+                  state <= LOSS_OF_SYNC;
+                end if;
+              when others => null;
+            end case;
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+
+  
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_sync_detect_16bit.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_sync_detect_16bit.vhd
new file mode 100644
index 000000000..c49209499
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_sync_detect_16bit.vhd
@@ -0,0 +1,193 @@
+-------------------------------------------------------------------------------
+-- Title      : 802.3x 1000base-X compatible synchronization detect unit
+-- Project    : WhiteRabbit Switch
+-------------------------------------------------------------------------------
+-- File       : ep_sync_detect.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-05-28
+-- Last update: 2012-01-18
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description: Module implements a link synchronization detect state machine
+-- compatible with 802.3x spec.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2010-05-28  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.endpoint_private_pkg.all;
+
+entity ep_sync_detect_16bit is
+  
+  port (
+-- reset, synchronous to rbclk_i, active LOW
+    rst_n_i  : in  std_logic;
+-- recovered byte clock
+    rbclk_i  : in  std_logic;
+-- enable, active HI
+    en_i     : in  std_logic;
+-- decoded data input, active HI
+    data_i   : in  std_logic_vector(15 downto 0);
+-- decoded K signal, active HI
+    k_i      : in  std_logic_vector(1 downto 0);
+-- 8b10b coding error indication, active HI
+    err_i    : in  std_logic;
+-- sync detect output, active HI
+    synced_o : out std_logic;
+
+    cal_i : in std_logic
+    );
+
+end ep_sync_detect_16bit;
+
+architecture behavioral of ep_sync_detect_16bit is
+
+  type t_sync_fsm_state is (LOSS_OF_SYNC, CD_ACQ_1, CD_ACQ_2, CD_ACQ_3, SYNC_ACQUIRED_1, SYNC_ACQUIRED_2, SYNC_ACQUIRED_3, SYNC_ACQUIRED_4, SYNC_ACQUIRED_2A, SYNC_ACQUIRED_3A, SYNC_ACQUIRED_4A);
+
+  
+  function f_pick(sel : std_logic;
+                  w1  : t_sync_fsm_state;
+                  w0  : t_sync_fsm_state) return t_sync_fsm_state is
+
+  begin
+    if(sel = '1') then
+      return w1;
+    else
+      return w0;
+    end if;
+  end f_pick;
+
+
+
+  signal state    : t_sync_fsm_state;
+  signal good_cgs : unsigned(2 downto 0);
+
+  signal valid_idle   : std_logic;
+  signal invalid_code : std_logic;
+  signal valid_data   : std_logic;
+  
+begin  -- behavioral
+
+  valid_idle   <= '1' when (k_i = "10" and data_i(15 downto 8) = c_k28_5 and err_i = '0')   else '0';
+  valid_data   <= '1' when (k_i = "00" and err_i = '0')                                     else '0';
+  invalid_code <= '1' when (err_i = '1' or (k_i(0) = '1' and data_i(7 downto 0) = c_k28_5)) else '0';
+
+
+  sync_fsm : process (rbclk_i, rst_n_i)
+  begin  -- process sync_fsm
+    if rising_edge(rbclk_i) then
+      if(rst_n_i = '0') then
+        state    <= LOSS_OF_SYNC;
+        synced_o <= '0';
+        good_cgs <= (others => '0');
+      else
+        if(en_i = '0') then
+          state    <= LOSS_OF_SYNC;
+          synced_o <= '0';
+          good_cgs <= (others => '0');
+        else
+
+          -- prevents from 
+          if(cal_i = '0') then
+            
+            case state is
+              when LOSS_OF_SYNC =>
+                synced_o <= '0';
+                state    <= f_pick(valid_idle, CD_ACQ_1, LOSS_OF_SYNC);
+              when CD_ACQ_1 =>
+                state <= f_pick(valid_idle or valid_data, CD_ACQ_2, LOSS_OF_SYNC);
+              when CD_ACQ_2 =>
+                state <= f_pick(valid_idle, CD_ACQ_3, LOSS_OF_SYNC);
+              when CD_ACQ_3 =>
+                state <= f_pick(valid_idle or valid_data, SYNC_ACQUIRED_1, LOSS_OF_SYNC);
+                
+              when SYNC_ACQUIRED_1 =>
+                synced_o <= '1';
+                state    <= f_pick(invalid_code, SYNC_ACQUIRED_2, SYNC_ACQUIRED_1);
+
+              when SYNC_ACQUIRED_2 =>
+                good_cgs <= (others => '0');
+                state    <= f_pick(invalid_code, SYNC_ACQUIRED_3, SYNC_ACQUIRED_2A);
+
+              when SYNC_ACQUIRED_2A =>
+                good_cgs <= good_cgs + 1;
+
+                if(good_cgs = "011" and invalid_code = '0') then
+                  state <= SYNC_ACQUIRED_1;
+                end if;
+
+                if(invalid_code = '1') then
+                  state <= SYNC_ACQUIRED_3;
+                end if;
+
+              when SYNC_ACQUIRED_3 =>
+                good_cgs <= (others => '0');
+                state    <= f_pick(invalid_code, SYNC_ACQUIRED_4, SYNC_ACQUIRED_3A);
+
+                
+              when SYNC_ACQUIRED_3A =>
+                good_cgs <= good_cgs + 1;
+
+                if(good_cgs = "011" and invalid_code = '0') then
+                  state <= SYNC_ACQUIRED_2;
+                end if;
+
+                if(invalid_code = '1') then
+                  state <= SYNC_ACQUIRED_4;
+                end if;
+
+              when SYNC_ACQUIRED_4 =>
+                good_cgs <= (others => '0');
+                state    <= f_pick(invalid_code, LOSS_OF_SYNC, SYNC_ACQUIRED_4A);
+                
+              when SYNC_ACQUIRED_4A =>
+                good_cgs <= good_cgs + 1;
+
+                if(good_cgs = "011" and invalid_code = '0') then
+                  state <= SYNC_ACQUIRED_3;
+                end if;
+
+                if (invalid_code = '1') then
+                  state <= LOSS_OF_SYNC;
+                end if;
+            end case;
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_timestamping_unit.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_timestamping_unit.vhd
new file mode 100644
index 000000000..0ea2cfd2b
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_timestamping_unit.vhd
@@ -0,0 +1,424 @@
+-------------------------------------------------------------------------------
+-- Title      : Optical 1000base-X endpoint - IEEE1588/WhiteRabbit
+--              timestamping unit
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_timestamping_unit.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2009-06-22
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: Timestamping unit. Takes both TX and RX timestamps upon
+-- detection of rising edge on asynchronous timestamp strobe inputs.
+-- There are 2 timestamps taken:
+-- - rising edge timestamp (28 bits by default) - the main timestamp value
+-- - falling edge timestamp (4 least significant bits of the TS counter) which
+--   are used to detect metastabilities and setup/hold violations which may
+--   occur during sampling asynchronous timestamp strobes.
+-- Both timestamps are taken using refclk_i.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009 - 2012 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2009-06-22  0.1      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.ep_wbgen2_pkg.all;
+
+entity ep_timestamping_unit is
+  generic (
+-- size of rising edge timestamp
+    g_timestamp_bits_r : natural := 28;
+-- size of falling edge timestamp
+    g_timestamp_bits_f : natural := 4;
+    g_ref_clock_rate   : integer := 125000000
+    );
+
+  port (
+-- reference clock (for the timestamping counters)
+    clk_ref_i : in std_logic;
+
+-- reference / 2 (bus-side logic)
+    clk_sys_i : in std_logic;
+
+-- RX clock
+    clk_rx_i : in std_logic;
+
+    -- resets
+    rst_n_rx_i  : in std_logic;
+    rst_n_ref_i : in std_logic;
+    rst_n_sys_i : in std_logic;
+
+-- PPS pulse input (active HI for 1 clk_ref_i cycle) for internal TS counter synchronization
+    pps_csync_p1_i : in std_logic;
+
+    pps_valid_i : in std_logic;
+
+-- asynchronous TX/RX timestamp triggers (from PCS)
+    tx_timestamp_trigger_p_a_i : in std_logic;
+    rx_timestamp_trigger_p_a_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- RX Timestamp output (clk_rx_i clock domain)
+-------------------------------------------------------------------------------
+
+    -- RX timestamp (to RX deframer)
+    rxts_timestamp_o : out std_logic_vector(31 downto 0);
+
+    -- RX timestamp strobe (back to the PCSr). When HI,
+    -- rxts_timestamp_o and rxts_timestamp_valid_o contain information about
+    -- the RX timestamp and its validity
+    rxts_timestamp_stb_o : out std_logic;
+
+    -- RX timestamp valid (to RX deframer)
+    rxts_timestamp_valid_o : out std_logic;
+
+-------------------------------------------------------------------------------
+-- TX Timestamp output (clk_ref_i clock domain)
+-------------------------------------------------------------------------------    
+
+    -- TX timestamp output (to TXTSU/Framer)
+    txts_timestamp_o : out std_logic_vector(31 downto 0);
+
+    -- TX timestamp strobe (to TXTSU/Framer). When HI,
+    -- txts_timestamp_o and txts_timestamp_valid_o contain information about
+    -- the TX timestamp and its validity
+    txts_timestamp_stb_o : out std_logic;
+
+    -- TX timestamp valid (to TXTSU/Framer)
+    txts_timestamp_valid_o : out std_logic;
+
+    txts_o                 : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+    rxts_o                 : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+
+-------------------------------------------------------------------------------
+-- Wishbone regs
+-------------------------------------------------------------------------------
+
+    regs_i : in  t_ep_out_registers;
+    regs_o : out t_ep_in_registers
+    );
+
+end ep_timestamping_unit;
+
+
+
+architecture syn of ep_timestamping_unit is
+
+
+  component ep_ts_counter
+    generic (
+      g_num_bits_r : natural;
+      g_num_bits_f : natural;
+      g_init_value : natural;
+      g_max_value  : natural);
+    port (
+      clk_i          : in  std_logic;
+      rst_n_i        : in  std_logic;
+      overflow_o     : out std_logic := '0';
+      value_r_o      : out std_logic_vector(g_num_bits_r-1 downto 0);
+      value_f_o      : out std_logic_vector(g_num_bits_f-1 downto 0);
+      pps_p_i        : in  std_logic;
+      sync_start_p_i : in  std_logic;
+      sync_done_o    : out std_logic);
+  end component;
+
+  signal cntr_rx_r : std_logic_vector(g_timestamp_bits_r-1 downto 0);
+  signal cntr_rx_f : std_logic_vector(g_timestamp_bits_f-1 downto 0);
+  signal cntr_tx_r : std_logic_vector(g_timestamp_bits_r-1 downto 0);
+  signal cntr_tx_f : std_logic_vector(g_timestamp_bits_f-1 downto 0);
+
+  signal cntr_r : std_logic_vector(g_timestamp_bits_r-1 downto 0);
+  signal cntr_f : std_logic_vector(g_timestamp_bits_f-1 downto 0);
+
+  signal take_tx_synced_p, take_rx_synced_p             : std_logic;
+  signal take_tx_synced_p_fedge, take_rx_synced_p_fedge : std_logic;
+
+  signal tx_sync_delay : std_logic_vector(4 downto 0);
+  signal rx_sync_delay : std_logic_vector(4 downto 0);
+  signal rx_ts_done    : std_logic;
+  signal tx_ts_done    : std_logic;
+
+  signal got_tx_oob : std_logic;
+  signal tx_oob_reg : std_logic_vector(15 downto 0);
+
+
+  signal rx_oob_reg : std_logic_vector(47 downto 0);
+  signal fid_valid  : std_logic;
+
+  signal txts_valid : std_logic;
+
+  signal valid_rx, valid_tx : std_logic;
+
+
+  signal cal_count                                   : unsigned(5 downto 0);
+  signal rx_trigger_mask, rx_trigger_a, rx_cal_pulse_a : std_logic;
+
+  signal regs_o_tscr_cs_done       : std_logic;
+  signal regs_o_tscr_rx_cal_result : std_logic;
+  
+begin  -- syn
+
+  -- Instatniation of the timestamping counter
+  U_counter : ep_ts_counter
+    generic map (
+      g_num_bits_r => g_timestamp_bits_r,
+      g_num_bits_f => g_timestamp_bits_f,
+      g_init_value => 0,
+      g_max_value  => g_ref_clock_rate-1)
+    port map (
+
+      clk_i          => clk_ref_i,
+      rst_n_i        => rst_n_ref_i,
+      pps_p_i        => pps_csync_p1_i,
+      overflow_o     => open,
+      value_r_o      => cntr_r,
+      value_f_o      => cntr_f,
+      sync_start_p_i => regs_i.tscr_cs_start_o,
+      sync_done_o    => regs_o_tscr_cs_done
+      );
+
+
+  p_gen_regs_o: process (regs_o_tscr_cs_done, regs_o_tscr_rx_cal_result) is
+  begin
+    -- initial values
+    regs_o <= c_ep_in_registers_init_value;
+
+    -- override initial values
+    regs_o.tscr_cs_done_i       <= regs_o_tscr_cs_done;
+    regs_o.tscr_rx_cal_result_i <= regs_o_tscr_rx_cal_result;
+
+  end process p_gen_regs_o;
+
+  p_rx_timestamper_calibration : process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if rst_n_rx_i = '0' then
+        cal_count       <= (others => '0');
+        rx_cal_pulse_a  <= '0';
+        rx_trigger_mask <= '1';
+        
+      elsif(regs_i.tscr_rx_cal_start_o = '1') then
+        cal_count       <= to_unsigned(1, 6);
+        rx_trigger_mask <= '0';
+      elsif(cal_count /= 0) then
+        cal_count <= cal_count + 1;
+
+        if(rx_ts_done = '1') then
+          if(cntr_rx_f /= cntr_rx_r(g_timestamp_bits_f-1 downto 0)) then
+            regs_o_tscr_rx_cal_result <= '1';
+          else
+            regs_o_tscr_rx_cal_result <= '0';
+          end if;
+        end if;
+
+      else
+        
+        rx_trigger_mask <= '1';
+      end if;
+
+      if(cal_count (5 downto 4) = x"01") then
+        rx_cal_pulse_a <= '1';
+      else
+        rx_cal_pulse_a <= '0';
+      end if;
+      
+    end if;
+  end process;
+
+
+  rx_trigger_a       <= (rx_timestamp_trigger_p_a_i and rx_trigger_mask) or rx_cal_pulse_a;
+  -- Sync chains for timestamp strobes: 4 combinations - (TX-RX) -> (rising/falling)
+  sync_ffs_tx_r : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_ref_i,
+      rst_n_i  => rst_n_ref_i,
+      data_i   => tx_timestamp_trigger_p_a_i,
+      synced_o => open,
+      npulse_o => open,
+      ppulse_o => take_tx_synced_p);
+
+
+  
+  sync_ffs_rx_r : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_ref_i,
+      rst_n_i  => rst_n_ref_i,
+      data_i   => rx_trigger_a,
+      synced_o => open,
+      npulse_o => open,
+      ppulse_o => take_rx_synced_p);
+
+
+  sync_ffs_tx_f : gc_sync_ffs
+    generic map (
+      g_sync_edge => "negative")
+    port map (
+      clk_i    => clk_ref_i,
+      rst_n_i  => rst_n_ref_i,
+      data_i   => tx_timestamp_trigger_p_a_i,
+      synced_o => open,
+      npulse_o => open,
+      ppulse_o => take_tx_synced_p_fedge);
+
+  sync_ffs_rx_f : gc_sync_ffs
+    generic map (
+      g_sync_edge => "negative")
+    port map (
+      clk_i    => clk_ref_i,
+      rst_n_i  => rst_n_ref_i,
+      data_i   => rx_trigger_a,
+      synced_o => open,
+      npulse_o => open,
+      ppulse_o => take_rx_synced_p_fedge);
+
+  
+
+  take_r : process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      if(rst_n_ref_i = '0') then
+        cntr_rx_r <= (others => '0');
+        cntr_tx_r <= (others => '0');
+
+        rx_sync_delay <= (others => '0');
+        tx_sync_delay <= (others => '0');
+      else
+        -- shift reg
+
+        if take_rx_synced_p = '1' then
+          cntr_rx_r                                                           <= cntr_r;
+          valid_rx                                                            <= pps_valid_i;
+          rx_sync_delay(rx_sync_delay'length-1 downto rx_sync_delay'length-4) <= (others => '1');
+        else
+          rx_sync_delay <= '0' & rx_sync_delay(rx_sync_delay'length-1 downto 1);
+        end if;
+
+        if take_tx_synced_p = '1' then
+          cntr_tx_r                                                           <= cntr_r;
+          valid_tx                                                            <= pps_valid_i;
+          tx_sync_delay(tx_sync_delay'length-1 downto tx_sync_delay'length-4) <= (others => '1');
+        else
+          tx_sync_delay <= '0' & tx_sync_delay(tx_sync_delay'length-1 downto 1);
+        end if;
+        
+      end if;
+    end if;
+  end process;
+
+  take_f : process(clk_ref_i)
+  begin
+    if falling_edge(clk_ref_i) then
+      if rst_n_ref_i = '0' then
+        cntr_rx_f <= (others => '0');
+        cntr_tx_f <= (others => '0');
+      else
+        if take_rx_synced_p_fedge = '1' then
+          cntr_rx_f <= cntr_f;
+        end if;
+        if take_tx_synced_p_fedge = '1' then
+          cntr_tx_f <= cntr_f;
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+  -- timestamping "done" signals sync chains (clk_ref -> clk_sys)
+  tx_done_gen : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_sys_i,
+      data_i   => tx_sync_delay(0),
+      synced_o => open,
+      npulse_o => tx_ts_done,
+      ppulse_o => open);
+
+  -- timestamping "done" signals sync chains (clk_rx -> clk_sys)
+  rx_done_gen : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_rx_i,
+      rst_n_i  => rst_n_rx_i,
+      data_i   => rx_sync_delay(0),
+      synced_o => open,
+      npulse_o => rx_ts_done,
+      ppulse_o => open);
+
+  txts_o <= tx_ts_done; 		-- 2013-Nov-28 peterj added for debugging/calibration
+  rxts_o <= rx_ts_done; 		-- 2013-Nov-28 peterj added for debugging/calibration
+
+  p_output_rx_ts : process (clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if(rst_n_rx_i = '0') then
+        rxts_timestamp_stb_o   <= '0';
+        rxts_timestamp_o       <= (others => '0');
+        rxts_timestamp_valid_o <= '0';
+      else
+        if(regs_i. tscr_en_rxts_o = '0') then
+          rxts_timestamp_stb_o <= '0';
+        elsif(rx_ts_done = '1' and regs_i.tscr_en_rxts_o = '1') then
+          rxts_timestamp_stb_o   <= '1';
+          rxts_timestamp_valid_o <= valid_rx;
+          rxts_timestamp_o       <= cntr_rx_f & cntr_rx_r;
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+  p_output_tx_ts : process (clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_sys_i = '0') then
+        txts_timestamp_o       <= (others => '0');
+        txts_timestamp_stb_o   <= '0';
+        txts_timestamp_valid_o <= '0';
+      elsif(tx_ts_done = '1' and regs_i.tscr_en_txts_o = '1') then
+        txts_timestamp_o       <= cntr_tx_f & cntr_tx_r;
+        txts_timestamp_stb_o   <= '1';
+        txts_timestamp_valid_o <= valid_tx;
+      end if;
+    end if;
+  end process;
+
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_ts_counter.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_ts_counter.vhd
new file mode 100644
index 000000000..2b9589f5a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_ts_counter.vhd
@@ -0,0 +1,152 @@
+-------------------------------------------------------------------------------
+-- Title      : Optical 1000base-X endpoint - IEEE1588 timestamping counter
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : ep_ts_counter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2009-06-22
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: Implementation of dual-edge synchronous counter for
+-- PTP timestamping purposes. Falling edge counter always follows the value of
+-- rising edge counter. For space reasons only some LSBs of falling edge
+-- counter are outputted.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2009-06-22  1.0      twlostow  Created
+-- 2010-09-01  1.0      twlostow  Added PPS sync
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.endpoint_private_pkg.all;
+
+entity ep_ts_counter is
+
+  generic (
+-- number of bits for rising edge counter
+    g_num_bits_r : natural := 27;
+-- number of bits to copy for falling edge counter
+    g_num_bits_f : natural := 5;
+-- initial value of the counter (after reset)
+    g_init_value : natural := 124999990;
+-- max value of the counter after reaching which it goes back to 0
+    g_max_value  : natural := 124999999
+    );
+
+  port (
+    -- counter clock 
+    clk_i      : in  std_logic;
+    -- synchronous reset, active LOW
+    rst_n_i    : in  std_logic;
+-- overflow indicator, active HI when counter value = g_max_value
+    overflow_o : out std_logic := '0';
+-- counter values (rising and falling edge)
+    value_r_o  : out std_logic_vector(g_num_bits_r-1 downto 0);
+    value_f_o  : out std_logic_vector(g_num_bits_f-1 downto 0);
+
+-- PPS pulse input, active HI, synchronous to clk_i. Resets the counter when
+-- synchronization is enabled
+    pps_p_i : in std_logic;
+
+-- Synchronization enable: a HI pulse on this line will cause the counter to be
+-- synced to next incoming PPS pulse. After then, sync_done_o will become HI.
+    sync_start_p_i : in std_logic;
+
+-- Synchronization done: HI indicates that we've got a PPS pulse we've been waiting for
+-- and now the counter value equals 0 when PPS pulse is active.
+    sync_done_o : out std_logic
+    );
+
+end ep_ts_counter;
+
+architecture syn of ep_ts_counter is
+
+  signal cntr_r           : unsigned(g_num_bits_r-1 downto 0) := (others => '0');
+  signal cntr_f           : unsigned (g_num_bits_f-1 downto 0);
+  
+begin  -- syn
+
+
+  -- the main TS counter counts on rising clock edge.
+  rising_ctr : process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if(rst_n_i = '0') then
+        cntr_r           <= to_unsigned(g_init_value, g_num_bits_r);
+        sync_done_o      <= '1';
+      else
+
+-- we've got a synchronization request
+        --if(sync_start_p_i = '1') then
+        --  sync_in_progress <= '1';
+        --  sync_done_o      <= '0';
+-- so wait for the next PPS pulse, and then set the PPS counter to 1 (so it
+-- equals to 0 when PPS input is active)
+        --elsif(sync_in_progress = '1' and pps_p_i = '1') then
+        --  sync_in_progress <= '0';
+        --  sync_done_o      <= '1';
+        --  cntr_r           <= to_unsigned(1, g_num_bits_r);
+        --else
+
+
+        -- increment the counter, reset on overflow
+        if(cntr_r = to_unsigned(g_max_value, g_num_bits_r) or pps_p_i = '1') then
+          cntr_r <= (others => '0');
+        else
+          cntr_r <= cntr_r + 1;
+        end if;
+      end if;
+
+      -- generate overflow output
+      if(cntr_r = to_unsigned(0, g_num_bits_r)) then
+        overflow_o <= '1';
+      else
+        overflow_o <= '0';
+      end if;
+--      end if;
+    end if;
+  end process;
+
+
+-- the falling edge counter just copies the rising edge counter half a clock
+-- cycle after.
+  falling_ctr : process(clk_i)
+  begin
+    if falling_edge(clk_i)then
+      cntr_f <= cntr_r(g_num_bits_f-1 downto 0);
+    end if;
+  end process;
+
+  -- stupid VHDL type conversion mumbo-jumbo
+  value_r_o <= std_logic_vector(cntr_r);
+  value_f_o <= std_logic_vector(cntr_f);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_crc_inserter.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_crc_inserter.vhd
new file mode 100644
index 000000000..a560f06e6
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_crc_inserter.vhd
@@ -0,0 +1,267 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000base-X MAC/Endpoint
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_tx_crc_inserter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2009-06-22
+-- Last update: 2017-02-02
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Calculates and embeds the CRC into the transmitted frame.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2012 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+use work.gencores_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+use work.ep_crc32_pkg.all;
+
+entity ep_tx_crc_inserter is
+  generic(
+    g_use_new_crc	: boolean := false);
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    snk_fab_i  : in  t_ep_internal_fabric;
+    snk_dreq_o : out std_logic;
+
+    src_fab_o  : out t_ep_internal_fabric;
+    src_dreq_i : in  std_logic;
+    dbg_o      : out std_logic_vector(2 downto 0)
+    );
+end ep_tx_crc_inserter;
+
+architecture behavioral of ep_tx_crc_inserter is
+
+  type t_state is (IDLE, WAIT_CRC, EMBED_1, EMBED_2, EMBED_3);
+
+-- general signals
+  signal state : t_state;
+
+-- CRC generator signals
+  signal crc_gen_reset  : std_logic;
+  signal crc_gen_enable : std_logic;
+  signal crc_value      : std_logic_vector(31 downto 0);
+
+  signal odd_length : std_logic;
+
+  signal embed_valid : std_logic;
+
+  signal stored_msb : std_logic_vector(7 downto 0);
+  signal in_payload : std_logic;
+  signal src_dreq_d0 : std_logic;
+
+  signal crc_p_value, crc_n_value : std_logic_vector(31 downto 0);
+  --signal crc_next, crc_new	:	std_logic_vector(31 downto 0);
+  
+begin  -- behavioral
+
+  dbg_o          <= "111" when (state = IDLE) else
+                    "110" when (state = WAIT_CRC) else
+                    "101" when (state = EMBED_1) else
+                    "100" when (state = EMBED_2) else
+                    "011" when (state = EMBED_3) else
+                    "000";
+
+  in_payload     <= '1' when (state = IDLE or state = WAIT_CRC) else '0';
+-- ML: potential optimization (if desperate)
+-- in_payload     <= '1' when (state = IDLE or state = WAIT_CRC) or (src_dreq_d0 = '1' and odd_length = '0' and state = EMBED_2)) else '0';
+  crc_gen_reset  <= '1' when rst_n_i = '0' or snk_fab_i.sof = '1'                                         else '0';
+  crc_gen_enable <= '1' when (snk_fab_i.dvalid = '1' and in_payload = '1') else '0';
+
+	gen_old_crc: if(g_use_new_crc = false) generate
+  	U_tx_crc_generator : gc_crc_gen
+  	  generic map (
+  	    g_polynomial              => x"04C11DB7",
+  	    g_init_value              => x"ffffffff",
+  	    g_residue                 => x"38fb2284",
+  	    g_data_width              => 16,
+  	    g_half_width              => 8,
+  	    g_sync_reset              => 1,
+  	    g_dual_width              => 1,
+  	    g_registered_match_output => false,
+  	    g_registered_crc_output   => true)
+  	  port map (
+  	    clk_i   => clk_sys_i,
+  	    rst_i   => crc_gen_reset,
+  	    en_i    => crc_gen_enable,
+  	    half_i  => snk_fab_i.bytesel,
+  	    data_i  => snk_fab_i.data,
+  	    match_o => open,
+  	    crc_o   => crc_value);
+	end generate;
+
+	gen_new_crc: if(g_use_new_crc = true) generate
+		p_check_crc_p: process(clk_sys_i)
+		begin
+			if falling_edge(clk_sys_i) then
+				if(crc_gen_reset = '1')then
+					crc_n_value <= c_CRC32_INIT_VALUE;
+				elsif(crc_gen_enable = '1') then
+					crc_n_value <= f_update_crc32_d8(crc_p_value, snk_fab_i.data(15 downto 8));
+				end if;
+			end if;
+		end process;
+
+		p_check_crc_n: process(clk_sys_i)
+		begin
+			if rising_edge(clk_sys_i) then
+				if(crc_gen_reset = '1') then
+					crc_p_value <= c_CRC32_INIT_VALUE;
+				elsif(crc_gen_enable = '1' and snk_fab_i.bytesel = '0') then
+					crc_p_value <= f_update_crc32_d8(crc_n_value, snk_fab_i.data(7 downto 0));
+				end if;
+			end if;
+		end process;
+
+		crc_value <= crc_p_value when odd_length = '0' else
+								 crc_n_value;
+
+	end generate;
+
+  p_delay_dreq: process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        src_dreq_d0 <= src_dreq_i;
+      end if;
+    end process;
+  
+  p_crc_fsm : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i = '0' or snk_fab_i.error = '1') then
+        state     <= IDLE;
+      else
+        case state is
+          when IDLE =>
+            odd_length <= '0';
+
+            if(snk_fab_i.sof = '1') then
+              state <= WAIT_CRC;
+            end if;
+            
+          when WAIT_CRC =>
+            if(snk_fab_i.bytesel = '1') then
+              odd_length <= '1';
+              stored_msb <= snk_fab_i.data(15 downto 8);
+            end if;
+
+            if(snk_fab_i.eof = '1' or snk_fab_i.addr = c_WRF_OOB) then
+              state <= EMBED_1;
+            end if;
+
+          when EMBED_1 =>
+            if(src_dreq_d0 = '1') then
+              state <= EMBED_2;
+            end if;
+
+          when EMBED_2 =>
+            if(src_dreq_d0 = '1') then
+              if(odd_length = '1') then
+                state <= EMBED_3;
+              else
+                state     <= IDLE;
+              end if;
+            end if;
+            
+          when EMBED_3 =>
+            if(src_dreq_d0 = '1') then
+              state     <= IDLE;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  p_drive_data_addr : process(state, crc_value, odd_length, stored_msb, snk_fab_i, src_dreq_d0)
+  begin
+
+    case state is
+      when EMBED_1 =>
+        if(odd_length = '1') then
+          src_fab_o.data    <= stored_msb & crc_value(31 downto 24);
+          src_fab_o.addr    <= c_WRF_DATA;
+          src_fab_o.bytesel <= '0';
+          src_fab_o.dvalid <= src_dreq_d0;
+          src_fab_o.eof <= '0';
+        else
+          src_fab_o.data    <= crc_value(31 downto 16);
+          src_fab_o.addr    <= c_WRF_DATA;
+          src_fab_o.bytesel <= '0';
+          src_fab_o.dvalid <= src_dreq_d0;
+          src_fab_o.eof <= '0';
+        end if;
+
+      when EMBED_2 =>
+        if(odd_length = '1') then
+          src_fab_o.data    <= crc_value(23 downto 8);
+          src_fab_o.addr    <= c_WRF_DATA;
+          src_fab_o.bytesel <= '0';
+          src_fab_o.dvalid <= src_dreq_d0;
+          src_fab_o.eof <= '0';
+        else
+          src_fab_o.data    <= crc_value(15 downto 0);
+          src_fab_o.addr    <= c_WRF_DATA;
+          src_fab_o.bytesel <= '0';
+          src_fab_o.dvalid <= src_dreq_d0;
+          src_fab_o.eof <= '1';
+        end if;
+        
+      when EMBED_3 =>
+        src_fab_o.data    <= crc_value(7 downto 0) & "XXXXXXXX";
+        src_fab_o.addr    <= c_WRF_DATA;
+        src_fab_o.bytesel <= '1';
+        src_fab_o.dvalid <= src_dreq_d0;
+        src_fab_o.eof <= '1';
+
+      when others =>
+        src_fab_o.data    <= snk_fab_i.data;
+        src_fab_o.addr    <= snk_fab_i.addr;
+        src_fab_o.bytesel <= '0';
+        src_fab_o.dvalid <= snk_fab_i.dvalid and not snk_fab_i.bytesel;
+        src_fab_o.eof <= '0';
+  
+    end case;
+
+    src_fab_o.addr <= c_WRF_DATA;
+  end process;
+
+  snk_dreq_o                   <= src_dreq_i and in_payload;
+  src_fab_o.sof                <= snk_fab_i.sof;
+  src_fab_o.error              <= snk_fab_i.error;
+  src_fab_o.has_rx_timestamp   <= snk_fab_i.has_rx_timestamp;
+  src_fab_o.rx_timestamp_valid <= snk_fab_i.rx_timestamp_valid;
+
+end behavioral;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_header_processor.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_header_processor.vhd
new file mode 100644
index 000000000..233f0b130
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_header_processor.vhd
@@ -0,0 +1,723 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000base-X MAC/Endpoint - TX packet header processing unit
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : ep_tx_header_processor.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2009-06-22
+-- Last update: 2017-02-02
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Processes headers and OOBs of the packets to be transmitted.
+-- - provides a Wishbone-B4 interface to the host
+-- - embeds source MAC addresses if they aren't defined by the host
+-- - decodes TX OOB data and passes it to the timestamping unit
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009 - 2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+
+entity ep_tx_header_processor is
+  generic(
+    g_with_packet_injection : boolean;
+    g_with_timestamper      : boolean;
+    g_force_gap_length      : integer;
+    g_runt_padding          : boolean
+    );
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+------------------------------------------------------------------------------
+-- Physical Coding Sublayer (PCS) interface
+------------------------------------------------------------------------------
+
+    src_fab_o  : out t_ep_internal_fabric;
+    src_dreq_i : in  std_logic;
+
+    pcs_busy_i  : in std_logic;
+    pcs_error_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- WRF Sink (see WRF specification for the details)
+-------------------------------------------------------------------------------    
+
+    wb_snk_i : in  t_wrf_sink_in;
+    wb_snk_o : out t_wrf_sink_out;
+
+-------------------------------------------------------------------------------
+-- Flow Control Unit signals
+-------------------------------------------------------------------------------    
+
+-- TX send pause frame - when active, the framer will send a PAUSE frame
+-- as soon as possible. The pause quanta must be provided on tx_pause_delay_i input.
+    fc_pause_req_i   : in std_logic;
+    fc_pause_delay_i : in std_logic_vector(15 downto 0);
+
+-- TX send pause acknowledge - active after the current pause send request has
+-- been completed
+    fc_pause_ready_o : out std_logic;
+
+-- When active, the framer will allow for packet transmission.
+    fc_flow_enable_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- OOB/TSU signals
+-------------------------------------------------------------------------------    
+
+-- Port ID value
+    txtsu_port_id_o      : out std_logic_vector(4 downto 0);
+-- Frame ID value
+    txtsu_fid_o          : out std_logic_vector(16 -1 downto 0);
+-- Encoded timestamps
+    txtsu_ts_value_o     : out std_logic_vector(28 + 4 - 1 downto 0);
+    txtsu_ts_incorrect_o : out std_logic;
+
+-- TX timestamp strobe: HI tells the TX timestamping unit that a timestamp is
+-- available on txtsu_ts_value_o, txtsu_fid_o andd txtsu_port_id_o. The correctness
+-- of the timestamping is indiacted on txtsu_ts_incorrect_o. Line remains HI
+-- until assertion of txtsu_ack_i.
+    txtsu_stb_o : out std_logic;
+
+-- TX timestamp acknowledge: HI indicates that TXTSU has successfully received
+-- the timestamp
+    txtsu_ack_i : in std_logic;
+
+---------------------------------------------------------------------------
+-- Timestamp input from the timestamping unit
+---------------------------------------------------------------------------
+    txts_timestamp_i       : in std_logic_vector(31 downto 0);
+    txts_timestamp_valid_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- Control registers
+-------------------------------------------------------------------------------
+    ep_ctrl_i           : in std_logic;
+    regs_i : in t_ep_out_registers
+
+    );
+
+
+end ep_tx_header_processor;
+
+architecture behavioral of ep_tx_header_processor is
+
+  constant c_IFG_LENGTH : integer := g_force_gap_length ;--0;
+  constant c_MIN_FRAME_THR  : integer := 30;
+  constant c_MIN_QFRAME_THR : integer := 32; -- we need to pad more 802.1q
+                                             -- tagged frame if it's going to be
+                                             -- untagged later in the tx_path
+
+  type t_tx_framer_state is (TXF_IDLE, TXF_DELAYED_SOF, TXF_ADDR, TXF_DATA, TXF_GAP, TXF_PAD, TXF_ABORT, TXF_STORE_TSTAMP);
+
+-- general signals
+  signal state   : t_tx_framer_state;
+  signal counter : unsigned(13 downto 0);
+
+-- Flow Control-related signals
+  signal tx_pause_mode  : std_logic;
+
+  signal snk_valid : std_logic;
+
+  signal sof_p1, eof_p1, abort_p1, error_p1 : std_logic;
+  signal snk_cyc_d0                         : std_logic;
+
+  signal stored_status : t_wrf_status_reg;
+
+  type t_oob_fsm_state is (OOB_IDLE, OOB_1, OOB_2);
+
+  signal oob_state : t_oob_fsm_state;
+  signal oob       : t_wrf_oob;
+
+  signal wb_out         : t_wrf_sink_out;
+  signal decoded_status : t_wrf_status_reg;
+
+  signal abort_now : std_logic;
+  signal stall_int : std_logic;
+  signal tx_en        : std_logic;
+  signal ep_ctrl     : std_logic;
+  signal bitsel_d    : std_logic;
+  signal needs_padding  : std_logic;
+  signal to_be_untagged : std_logic;
+  signal sof_reg     : std_logic;
+
+  function b2s (x : boolean)
+    return std_logic is
+  begin
+    if(x) then
+      return '1';
+    else
+      return '0';
+    end if;
+  end function;
+
+  function f_pick (cond : boolean; when_1 : std_logic_vector; when_0 : std_logic_vector)
+    return std_logic_vector is
+  begin
+    if(cond) then
+      return when_1;
+    else
+      return when_0;
+    end if;
+  end function;
+
+  function f_pick (cond : std_logic; when_1 : std_logic_vector; when_0 : std_logic_vector)
+    return std_logic_vector is
+  begin
+    if(cond = '1') then
+      return when_1;
+    else
+      return when_0;
+    end if;
+  end function;
+
+  function f_pick (cond : boolean; when_1 : std_logic ; when_0 : std_logic)
+    return std_logic is
+  begin
+    if(cond) then
+      return when_1;
+    else
+      return when_0;
+    end if;
+  end function;
+  
+  function f_fabric_2_slv (
+    in_i : t_wrf_sink_in;
+    in_o : t_wrf_sink_out) return std_logic_vector is
+    variable tmp : std_logic_vector(31 downto 0);
+  begin
+    tmp(15 downto 0)  := in_i.dat;
+    tmp(17 downto 16) := in_i.adr;
+    tmp(19 downto 18) := in_i.sel;
+    tmp(20)           := in_i.cyc;
+    tmp(21)           := in_i.stb;
+    tmp(22)           := in_i.we;
+    tmp(23)           := in_o.ack;
+    tmp(24)           := in_o.stall;
+    tmp(25)           := in_o.err;
+    tmp(26)           := in_o.rty;
+    return tmp;
+  end f_fabric_2_slv;
+  
+begin  -- behavioral
+  
+  p_detect_frame : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        snk_cyc_d0 <= '0';
+      else
+        snk_cyc_d0 <= wb_snk_i.cyc;
+      end if;
+    end if;
+  end process;
+
+  sof_p1 <= not snk_cyc_d0 and wb_snk_i.cyc;
+  eof_p1 <= snk_cyc_d0 and not wb_snk_i.cyc;
+
+  snk_valid <= (wb_snk_i.cyc and wb_snk_i.stb and wb_snk_i.we) and not wb_out.stall;
+
+  decoded_status <= f_unmarshall_wrf_status(wb_snk_i.dat);
+
+  error_p1 <= snk_valid and b2s(wb_snk_i.adr = c_WRF_STATUS) and decoded_status.error;
+
+-- abort_now <= '1' when (state /= TXF_IDLE and state /= TXF_GAP) and (regs_i.ecr_tx_en_o = '0' or error_p1 = '1') else '0';
+ abort_now <= '1' when (state /= TXF_IDLE and state /= TXF_GAP) and (tx_en = '0' or error_p1 = '1') else
+              '1' when (state = TXF_ABORT and wb_snk_i.cyc = '1' ) else 
+              '0'; -- ML
+
+  GEN_PADDING: if(g_runt_padding) generate
+    needs_padding <= '1' when( (to_be_untagged = '1' and counter < c_MIN_QFRAME_THR) or
+                                counter < c_MIN_FRAME_THR) else
+                     '0';
+  end generate;
+  GEN_NOPADDING: if( not g_runt_padding) generate
+    -- even if padding is disabled, we still need to pad short 802.1q frames
+    -- that will be untagged
+    needs_padding <= '1' when (to_be_untagged = '1' and counter < c_MIN_QFRAME_THR) else
+                     '0';
+  end generate;
+
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i='0') then
+        sof_reg <= '0';
+      elsif(sof_p1='1') then
+        sof_reg <= '1';
+      elsif(state = TXF_ADDR) then
+        sof_reg <= '0';
+      end if;
+    end if;
+  end process;
+
+  p_store_status : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      
+      if rst_n_i = '0' or tx_pause_mode = '1' then
+        stored_status.has_smac <= '0';
+        stored_status.is_hp    <= '0';
+        stored_status.has_crc  <= '0';
+      else
+        if(snk_valid = '1' and wb_snk_i.adr = c_WRF_STATUS) then
+          stored_status <= f_unmarshall_wrf_status(wb_snk_i.dat);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -----------------------------------------------------------------------------
+  -- Out-of-band handling state machine. When a packet comes with OOB info
+  -- (frame ID), it is registered here. Then the main FSM waits until the TX
+  -- FIFO of the endpoint is completely empty and pushes the last timestamp 
+  -- from the PCS to the TX Timestamping Unit
+  -----------------------------------------------------------------------------
+  gen_ts_supported : if(g_with_timestamper) generate
+    p_oob_fsm : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if (rst_n_i = '0' or state = TXF_ADDR) then
+          oob_state    <= OOB_1;
+          oob.valid    <= '0';
+          oob.oob_type <= (others => '0');
+        else
+          
+          case oob_state is
+            when OOB_1 =>
+              if(snk_valid = '1' and wb_snk_i.adr = c_WRF_OOB) then
+                oob.oob_type <= wb_snk_i.dat(15 downto 12);
+                oob_state    <= OOB_2;
+                oob.valid    <= '0';
+              end if;
+              
+            when OOB_2 =>
+              if(snk_valid = '1' and wb_snk_i.adr = c_WRF_OOB and oob.oob_type = c_WRF_OOB_TYPE_TX) then
+                oob.frame_id <= wb_snk_i.dat(15 downto 0);
+                oob_state    <= OOB_IDLE;
+                oob.valid    <= '1';
+              end if;
+              
+            when OOB_IDLE =>
+              oob_state <= OOB_IDLE;
+          end case;
+        end if;
+      end if;
+    end process;
+  end generate gen_ts_supported;
+
+  p_tx_fsm : process (clk_sys_i)
+  begin  -- process
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i = '0') then
+        state <= TXF_IDLE;
+
+        src_fab_o.has_rx_timestamp   <= '0';
+        src_fab_o.rx_timestamp_valid <= '0';
+        src_fab_o.dvalid             <= '0';
+        src_fab_o.ERROR              <= '0';
+        src_fab_o.sof                <= '0';
+        src_fab_o.eof                <= '0';
+        src_fab_o.bytesel            <= '0';
+
+        wb_out.err <= '0';
+        wb_out.rty <= '0';
+
+        tx_pause_mode <= '0';
+
+        fc_pause_ready_o <= '1';
+
+        txtsu_stb_o <= '0';
+        bitsel_d  <= '0';
+        to_be_untagged <= '0';
+
+      else
+
+        -- we are in the middle of the frame and the framer has got suddenly
+        -- disabled or we've received an ABORT command or an error occured in the PCS:
+
+        if(pcs_error_i = '1') then
+          state      <= TXF_IDLE;
+          wb_out.rty <= '1';
+          ----------------------------------------------------------------------------------
+          src_fab_o.error  <= '1'; -- nasty-bug-fix: it might happen that PCS throws error
+                                   -- to a previous frame, but we already start sending
+                                   -- the next one, in this case the frame is stopped being
+                                   -- sent but PCS does not know why... in the end we see
+                                   -- two SOFs in PACs
+          ----------------------------------------------------------------------------------                         
+        elsif(abort_now = '1') then
+          -- abort the current frame
+          state            <= TXF_ABORT;
+          src_fab_o.sof    <= '0';
+          src_fab_o.dvalid <= '0';
+
+        else
+
+          case state is
+
+-------------------------------------------------------------------------------
+-- TX FSM state IDLE: awaits incoming TX frames
+-------------------------------------------------------------------------------
+
+            when TXF_IDLE =>            -- idle state - wait for the next frame
+
+              wb_out.err <= '0';
+              wb_out.rty <= '0';
+
+              txtsu_stb_o <= '0';
+              bitsel_d    <= '0';
+
+              src_fab_o.error  <= '0';
+              src_fab_o.eof    <= '0';
+              src_fab_o.dvalid <= '0';
+              src_fab_o.bytesel <= '0';
+              to_be_untagged    <= '0';
+
+              -- Check start-of-frame and send-pause signals and eventually
+              -- commence frame transmission
+
+--             if(src_dreq_i = '1' and (sof_p1 = '1' or fc_pause_req_i = '1') and tx_en = '1') then --ML:removed
+--            EXPLANATION: removed src_dreq_i = '1' as the cycle can start on stall HIGH (dreq_i LOW), 
+--            it means that if we wait for dreq to be high.... we can miss SOF and thus entire frame. 
+--            New state added to include a case where SOF (start of cycle) starts when dreq is LOW.
+--            (we cannot just go to TXF_ADDR... it is because the PCS needs the minimal gap to add CRC)
+              if((sof_p1 = '1' or sof_reg='1' or fc_pause_req_i = '1') and tx_en = '1') then --ML
+
+                fc_pause_ready_o <= '0';
+                tx_pause_mode    <= fc_pause_req_i;
+
+                counter       <= (others => '0');
+                
+                if(src_dreq_i = '1') then
+                  state         <= TXF_ADDR;
+                  src_fab_o.sof <= '1';
+                end if;
+                
+              else
+                src_fab_o.sof <= '0';
+              end if;
+
+-------------------------------------------------------------------------------
+-- TX FSM (ML-added): this state takes into accunt the rare case where SOF happens 
+-- when dreq is LOW (PCS not ready). So we wait for dreq HIGH and STALL in the 
+-- meanttime (see process at the end)
+-------------------------------------------------------------------------------
+            when TXF_DELAYED_SOF =>
+             
+              if(src_dreq_i = '1') then
+                state         <= TXF_ADDR;
+                src_fab_o.sof <= '1';
+             end if;              
+-------------------------------------------------------------------------------
+-- TX FSM state HEADER: processes the frame header, send pause frames
+-- if compiled without packet injection support.
+-------------------------------------------------------------------------------
+
+            when TXF_ADDR =>
+              src_fab_o.sof <= '0';
+              
+              if (src_dreq_i = '1' and ((snk_valid = '1' and wb_snk_i.adr = c_WRF_DATA) or (tx_pause_mode = '1' and not g_with_packet_injection))) then
+
+                counter          <= counter + 1;
+                src_fab_o.dvalid <= '1';
+
+                case counter(3 downto 0) is
+                  when x"0" =>
+                    src_fab_o.data <= f_pick(tx_pause_mode = '1' and not g_with_packet_injection, x"0180", wb_snk_i.dat);
+                  when x"1" =>
+                    src_fab_o.data <= f_pick(tx_pause_mode = '1' and not g_with_packet_injection, x"c200", wb_snk_i.dat);
+                  when x"2" =>
+                    src_fab_o.data <= f_pick(tx_pause_mode = '1' and not g_with_packet_injection, x"0001", wb_snk_i.dat);
+                  when x"3" =>
+                    src_fab_o.data <= f_pick(stored_status.has_smac, wb_snk_i.dat, regs_i.mach_o);
+                  when x"4" =>
+                    src_fab_o.data <= f_pick(stored_status.has_smac, wb_snk_i.dat, regs_i.macl_o(31 downto 16));
+                  when x"5" =>
+                    src_fab_o.data <= f_pick(stored_status.has_smac, wb_snk_i.dat, regs_i.macl_o(15 downto 0));
+                    if(tx_pause_mode = '0' or g_with_packet_injection) then
+                      state <= TXF_DATA;
+                    end if;
+                  when x"6" =>
+                    src_fab_o.data <= f_pick(g_with_packet_injection, "XXXXXXXXXXXXXXXX", x"8808");
+                    to_be_untagged <= f_pick(wb_snk_i.dat = x"8100" and
+                                             regs_i.vcr0_qmode_o = c_QMODE_PORT_ACCESS, '1', '0');
+                  when x"7" =>
+                    src_fab_o.data <= f_pick(g_with_packet_injection, "XXXXXXXXXXXXXXXX", x"0001"); -- peterj: IEEE 802.3 Table 31A-1 MAC control codes PAUSE (Annex 31B)
+                  when x"8" =>
+                    src_fab_o.data <= f_pick(g_with_packet_injection, "XXXXXXXXXXXXXXXX", fc_pause_delay_i); -- ML: bug ??? (forget optcode: 0x0001)
+                    state          <= TXF_PAD;
+                  when others =>
+                    state <= TXF_PAD;
+                end case;
+                
+                src_fab_o.addr   <= c_WRF_DATA;
+                
+              else
+                src_fab_o.dvalid <= '0';
+                src_fab_o.data   <= (others => 'X');
+                src_fab_o.addr   <= (others => 'X');
+              end if;
+
+-------------------------------------------------------------------------------
+-- TX FSM state PAD: pads a pause frame to 64 bytes.
+-------------------------------------------------------------------------------
+
+            when TXF_PAD =>
+              
+              if(src_dreq_i = '1') then
+                counter <= counter + 1;
+
+                src_fab_o.data   <= (others => '0');
+                src_fab_o.dvalid <= '1';
+                src_fab_o.addr   <= (others => '0');
+
+                if( (to_be_untagged = '1' and counter = c_MIN_QFRAME_THR-1) or
+                    (to_be_untagged = '0' and counter = c_MIN_FRAME_THR-1) ) then
+                  state <= TXF_GAP;
+                  src_fab_o.eof    <= '1';
+                end if;
+                
+              else
+                src_fab_o.data   <= (others => '0');
+                src_fab_o.dvalid <= '0';
+                src_fab_o.addr   <= (others => '0');
+              end if;
+
+-------------------------------------------------------------------------------
+-- TX FSM state DATA: trasmits frame payload
+-------------------------------------------------------------------------------
+
+            when TXF_DATA =>
+
+              -- ML: added this EOF force LOW to make sure that EOF is single cycle, withouth
+              -- this, it might have happened that we had eof_p1 but PCS was busy, so we set
+              -- src_fab_o.eof to HIGH but actually did not exit the TXF_DATA state... this
+              -- caused EOF to be longer than one cycle
+              src_fab_o.eof   <= '0'; 
+
+              if (counter = x"6") then
+                to_be_untagged <= f_pick(wb_snk_i.dat = x"8100" and
+                                         regs_i.vcr0_qmode_o = c_QMODE_PORT_ACCESS, '1', '0');
+              end if;
+              
+              if((wb_snk_i.adr = c_WRF_OOB or eof_p1='1') and needs_padding='1') then
+                state <= TXF_PAD;
+              elsif(eof_p1 = '1' and needs_padding='0') then
+                src_fab_o.eof <= '1';
+                counter       <= (others => '0');
+    
+                if(g_force_gap_length = 0 and bitsel_d = '1') then -- only for odd
+
+                  -- Submit the TX timestamp to the TXTSU queue
+                  if(oob.valid = '1' and oob.oob_type = c_WRF_OOB_TYPE_TX) then
+                    if(pcs_busy_i = '0') then
+                      txtsu_stb_o          <= '1';
+                      txtsu_ts_incorrect_o <= not txts_timestamp_valid_i;
+                      txtsu_ts_value_o     <= txts_timestamp_i;
+                      txtsu_port_id_o      <= regs_i.ecr_portid_o;
+                      txtsu_fid_o          <= oob.frame_id;
+                      state                <= TXF_STORE_TSTAMP;
+                    else
+                       -- wait in the GAP state for pcs_busy_i LOW
+                      state                <= TXF_GAP;
+                    end if;                                      ---if(pcs_busy_i = '0') then
+                  else
+                    -- dont need timestamp, don't need GAP, just go to IDLE
+                    state <= TXF_IDLE;
+                  end if;                                        -- if(oob.valid = '1' and oob.oob_type = c_WRF_OOB_TYPE_TX) then
+                else -- need some GAP
+                  state         <= TXF_GAP;
+                end if;                                          -- f(g_force_gap_length = 0 and bitsel_d = '1') then      
+              end if;                                            -- if(eof_p1 = '1') then
+
+              if(snk_valid = '1' and wb_snk_i.adr = c_WRF_DATA) then
+                src_fab_o.data    <= wb_snk_i.dat;
+                src_fab_o.dvalid  <= '1';
+                src_fab_o.bytesel <= (not wb_snk_i.sel(0)) and (not needs_padding);
+                counter <= counter + 1;
+              else
+                src_fab_o.dvalid  <= '0';
+                src_fab_o.data    <= (others => 'X');
+                src_fab_o.bytesel <= '0';
+              end if;
+              
+              if(wb_snk_i.sel(0) = '0') then
+                bitsel_d <='1';
+              end if;  
+
+              if(needs_padding='1') then
+                src_fab_o.addr  <= (others=>'0');
+              else
+                src_fab_o.addr    <= wb_snk_i.adr;
+              end if;
+
+-------------------------------------------------------------------------------
+-- TX FSM states: WAIT_CRC, EMBED_CRC: dealing with frame checksum field
+-------------------------------------------------------------------------------            
+
+            when TXF_GAP =>
+              src_fab_o.eof    <= '0';
+              src_fab_o.error  <= '0';
+              src_fab_o.dvalid <= '0';
+              wb_out.err       <= '0';
+              wb_out.rty       <= '0';
+              src_fab_o.bytesel <= '0';
+
+              if(counter >= c_IFG_LENGTH or g_force_gap_length = 0) then
+
+                -- Submit the TX timestamp to the TXTSU queue
+                if(oob.valid = '1' and oob.oob_type = c_WRF_OOB_TYPE_TX) then
+                  if(pcs_busy_i = '0') then
+                    txtsu_stb_o          <= '1';
+                    txtsu_ts_incorrect_o <= not txts_timestamp_valid_i;
+                    txtsu_ts_value_o     <= txts_timestamp_i;
+                    txtsu_port_id_o      <= regs_i.ecr_portid_o;
+                    txtsu_fid_o          <= oob.frame_id;
+                    state                <= TXF_STORE_TSTAMP;
+                  end if;
+                else
+                  state <= TXF_IDLE;
+                end if;
+
+              else
+                counter <= counter + 1;
+              end if;
+
+            when TXF_STORE_TSTAMP =>  -- to slow ??? anyway, we can finish the frame
+              
+              src_fab_o.eof    <= '0';
+              src_fab_o.error  <= '0';
+              src_fab_o.dvalid <= '0';
+              wb_out.err       <= '0';
+              wb_out.rty       <= '0';
+              src_fab_o.bytesel<= '0';
+
+              if(txtsu_ack_i = '1') then
+                txtsu_stb_o <= '0';
+                state       <= TXF_IDLE;
+              end if;
+
+-------------------------------------------------------------------------------
+-- TX FSM state ABORT: signalize underlying PCS block to abort the frame
+-- immediately, corrupting its contents
+-------------------------------------------------------------------------------            
+            when TXF_ABORT =>
+              src_fab_o.sof    <= '0';
+              src_fab_o.dvalid <= '1';
+              src_fab_o.error  <= '1';
+
+              counter <= (others => '0');
+              state   <= TXF_IDLE;
+
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  tx_en <= regs_i.ecr_tx_en_o and ep_ctrl and ep_ctrl_i; 
+
+  --p_gen_stall : process(src_dreq_i, state, regs_i, wb_snk_i, snk_cyc_d0, tx_en)
+  p_gen_stall : process(src_dreq_i, state, tx_en, wb_snk_i, eof_p1)
+  begin
+    --if(regs_i.ecr_tx_en_o = '0') then
+    if(tx_en = '0') then --ML
+      wb_out.stall <= '0';              -- /dev/null if TX disabled
+--     elsif((wb_snk_i.cyc xor snk_cyc_d0) = '1') then
+--    elsif(wb_snk_i.cyc = '1' and snk_cyc_d0 = '0') then -- ML: do it only at the SOF, not EOF
+--      wb_out.stall <= '1';              -- /block for 1 cycle right upon
+                                        -- detection of a packet, so the FSM
+                                        -- has time to catch up
+    
+    -- stall at EOF - the SWcore should not send anything, but just in case, not to miss
+    -- SOF... the next cycle will be TXF_GAP (also stalling) or TXF_IDLE (can accept new frames)
+    elsif(eof_p1 = '1') then -- accept OOB as is      
+      wb_out.stall <= '1';
+      
+    -- when data is flowing (TXF_DATA) or we expect data (TXF_IDLE) stall only when no dreq_i 
+    -- from other modules
+---------------------------------------------------------------------------------------------
+-- ML: when error at the very end of the frame (e.g. due to jambo frame), stall happenend
+-- at the last cycle before cyc DOWN, subsequently, cycle did not finish and switch hanged
+---------------------------------------------------------------------------------------------
+--     elsif(src_dreq_i = '1' and state /= TXF_GAP and state /= TXF_ABORT and state /= TXF_DELAYED_SOF and state /= TXF_STORE_TSTAMP) then
+---------------------------------------------------------------------------------------------
+    elsif(src_dreq_i = '1' and state /= TXF_PAD and state /= TXF_GAP  and state /= TXF_DELAYED_SOF and state /= TXF_STORE_TSTAMP) then
+      wb_out.stall <= '0';              -- during data/header phase - whenever
+                                        -- the sink is ready to accept data
+    
+    -- when we receive OOB, there we have always resources/possibilties to accept it
+    -- since it is dumped in here, so we prevent dreq_i going LOW from stopping
+    -- to receive OOB
+    elsif(wb_snk_i.adr = c_WRF_OOB and wb_snk_i.cyc = '1') then -- accept OOB as is
+      wb_out.stall <= '0';              
+
+    -- one other option renderds stall 
+    else
+      wb_out.stall <= '1';
+    end if;
+  end process;
+
+  p_gen_ack : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      wb_out.ack <= snk_valid;
+    end if;
+  end process;
+
+  -- in theory, this should not happen: we don't send frames to ports which are DOWN, but..
+  -- we make sure that we don't start sending frames on the PHY in the middle of the frame...
+  -- the TX is enabled only when we don't receive any frames from SWcore
+  p_ctrl: process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i = '0') then
+        ep_ctrl  <= '1';
+      else
+        if(ep_ctrl_i = '0') then
+          ep_ctrl <= '0';
+        elsif(ep_ctrl_i = '1' and wb_snk_i.cyc = '0') then
+          ep_ctrl <= '1';
+        end if; --ep_ctr
+      end if;-- rst
+    end if;  -- clk   
+  end process;
+
+  wb_snk_o <= wb_out;
+
+end behavioral;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_inject_ctrl.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_inject_ctrl.vhd
new file mode 100644
index 000000000..766de7613
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_inject_ctrl.vhd
@@ -0,0 +1,235 @@
+-------------------------------------------------------------------------------
+-- Title      : Controller of
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_tx_inject_ctrl.vhd
+-- Author     : Maciej Lipinski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2014-01-16
+-- Last update: 2014-01-16
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: this module enables to control HW packet injection in order
+-- to turn the Endpoint into simple traffic generator for testing purposes
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2014 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wr_fabric_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+
+entity ep_tx_inject_ctrl is
+
+  generic(
+    g_min_if_gap_length     : integer
+    );
+
+  port (
+    clk_sys_i             : in  std_logic;
+    rst_n_i               : in  std_logic;
+
+    snk_fab_i             : in  t_ep_internal_fabric;
+    snk_dreq_o            : out std_logic;
+
+    src_fab_o             : out t_ep_internal_fabric;
+    src_dreq_i            : in  std_logic;
+
+    inject_req_o          : out std_logic;
+    inject_ready_i        : in  std_logic;
+    inject_packet_sel_o   : out std_logic_vector(2 downto 0);
+    inject_user_value_o   : out std_logic_vector(15 downto 0);
+    inject_ctr_ena_o      : out std_logic;
+    inject_ctr_mode_o     : out std_logic_vector(1 downto 0);
+
+    regs_i                : in  t_ep_out_registers;
+    regs_o                : out t_ep_in_registers
+    );
+end ep_tx_inject_ctrl;
+
+architecture rtl of ep_tx_inject_ctrl is
+
+  -- there a lag between setting inject_req and SOF, this nees to be included
+  constant if_gap_offset : unsigned(15 downto 0) := x"0000"; -- unused
+  constant src_fab_null  : t_ep_internal_fabric := (
+    sof                => '0',
+    eof                => '0',
+    error              => '0',
+    dvalid             => '0',
+    bytesel            => '0',
+    has_rx_timestamp   => '0',
+    rx_timestamp_valid => '0',
+    data               => (others => '0'),
+    addr               => (others => '0'));
+  type t_state is (IDLE, INJECT_REQ, INJECT, IFG, END_GEN);
+  
+  -- Wishbone settings
+  signal if_gap_value  : unsigned(15 downto 0);
+  signal pck_sel       : std_logic_vector(2  downto 0);
+  signal gen_ena       : std_logic;
+  signal inj_mode      : std_logic_vector(1 downto 0);
+
+  signal if_gap_cnt    : unsigned(15 downto 0);
+  signal frame_id_cnt  : unsigned(15 downto 0);
+  signal within_packet : std_logic;
+  signal state         : t_state;
+
+  -- translation betwen if_gap_value and real IFG:
+  -- | ----------------------------------------- |
+  -- | if_gap_value | gap in words | gap in time |
+  -- |   0          |     7        |   112 ns    | disallowed 
+  -- | ......................................... |
+  -- |   5          |     12       |   192 ns    | minimal leagal
+  -- |   6          |     13       |   208 ns    | 
+  -- | ......................................... |
+  -- |   65536      |     65546    |   1.048ms   | maximum allowed due to register size (16 bits)
+  -- | ----------------------------------------- |
+begin  -- rtl
+
+  p_detect_within : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        within_packet <= '0';
+      else
+        if(snk_fab_i.sof = '1')then
+          within_packet <= '1';
+        elsif(snk_fab_i.eof = '1' or snk_fab_i.error = '1') then
+          within_packet <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_config_reg: process(clk_sys_i)
+  begin
+   if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+          if_gap_value <= (others=>'0');
+          pck_sel      <= (others=>'0');
+          gen_ena      <= '0';
+          inj_mode     <= (others=>'0');
+      else
+        if(regs_i.inj_ctrl_pic_ena_load_o = '1') then  -- writing the register
+          if (regs_i.inj_ctrl_pic_conf_valid_o  = '1') then
+            if_gap_value <= unsigned(regs_i.inj_ctrl_pic_conf_ifg_o);
+            pck_sel      <= regs_i.inj_ctrl_pic_conf_sel_o;
+          end if;
+          if(regs_i.inj_ctrl_pic_mode_valid_o = '1') then
+            inj_mode     <= regs_i.inj_ctrl_pic_mode_id_o(1 downto 0);
+          end if;
+          gen_ena        <= regs_i.inj_ctrl_pic_ena_o;
+        end if;
+      end if;
+    end if;
+  end process;  
+
+  p_ctrl_fsm : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state           <= IDLE;
+        inject_req_o    <= '0';
+        if_gap_cnt      <= (others => '0');
+        frame_id_cnt    <= (others => '0');
+      else
+        case state is
+          when IDLE =>
+            
+            --  start when 
+            --  1) inject enabled, and 
+            --  2) no packet being received from SWcore and 
+            --  3) no packet being just started (otherwise, we could have two SOFs
+            if(gen_ena = '1' and within_packet = '0' and snk_fab_i.sof = '0') then 
+              inject_req_o   <= '1';                                
+              if_gap_cnt     <= if_gap_offset;
+              frame_id_cnt   <= (others => '0');
+              state          <= INJECT_REQ;
+            end if;
+            
+          when INJECT_REQ =>
+            
+            inject_req_o <= '0';
+            state        <= INJECT;
+            
+          when INJECT =>
+          
+            if(inject_ready_i = '1') then
+              frame_id_cnt <= frame_id_cnt + 1;
+              state        <= IFG;
+            end if;
+          
+          when IFG =>
+            
+            if(gen_ena = '0' ) then --gen disabled
+              if_gap_cnt      <= (others => '0');
+              frame_id_cnt    <= (others => '0');             
+              if(within_packet = '0') then  -- if there is no frame being currently dumped
+                state           <= IDLE;    -- go to idle state          
+              else                          -- if there is a frame being dumped, 
+                state           <= END_GEN; -- wait until it finishes
+              end if;
+            elsif(if_gap_cnt < if_gap_value) then
+              if_gap_cnt <= if_gap_cnt + 1;
+            else
+              inject_req_o   <= '1';
+              if_gap_cnt     <= if_gap_offset;
+              state          <= INJECT_REQ;          
+            end if;
+            
+          when END_GEN =>
+          
+            if(within_packet = '0') then -- now we can gracefully come back to normal functing
+              state           <= IDLE; 
+            end if;
+          
+          when others =>
+
+            state           <= IDLE;
+            if_gap_cnt      <= (others => '0');
+            frame_id_cnt    <= (others => '0');              
+
+        end case;
+      end if;
+    end if;
+  end process;
+
+  inject_user_value_o            <= std_logic_vector(frame_id_cnt);
+  inject_packet_sel_o            <= pck_sel;
+  inject_ctr_ena_o               <= gen_ena;
+  inject_ctr_mode_o              <= inj_mode;
+  snk_dreq_o                     <= src_dreq_i when (state = IDLE) else '1';         -- dev/null if gen
+  src_fab_o                      <= snk_fab_i  when (state = IDLE) else src_fab_null;-- dev/null if gen
+  regs_o.inj_ctrl_pic_conf_ifg_i <= std_logic_vector(if_gap_value);
+  regs_o.inj_ctrl_pic_conf_sel_i <= pck_sel;
+  regs_o.inj_ctrl_pic_conf_valid_i  <= '0';
+  regs_o.inj_ctrl_pic_ena_i      <= gen_ena;
+  regs_o.inj_ctrl_pic_mode_id_i  <= '0' & inj_mode;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_packet_injection.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_packet_injection.vhd
new file mode 100644
index 000000000..08e40970c
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_packet_injection.vhd
@@ -0,0 +1,251 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000base-X MAC/Endpoint - TX packet injection unit
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : ep_tx_packet_injection.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-11-01
+-- Last update: 2013-03-12
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Asynchronously sends pre-defined packets upon a hardware request.
+-- Packet contents are defined in a buffer accessible via Wishbone. The buffer
+-- is shared with the TX VLAN unit and can contain templates of up to 8 packets
+-- of up to 128 bytes of size. It is possible to replace a selected 16-bit word
+-- within each template with a user-provided value.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2012-11-01  1.0      twlostow          Created
+-- 2013-03-12  1.1      mlipinsk          added empty-template protaciton 
+--                                        prepared signals for RMON
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+
+entity ep_tx_packet_injection is
+
+  port
+    (
+      clk_sys_i : in std_logic;
+      rst_n_i   : in std_logic;
+
+      snk_fab_i  : in  t_ep_internal_fabric;
+      snk_dreq_o : out std_logic;
+
+      src_fab_o  : out t_ep_internal_fabric;
+      src_dreq_i : in  std_logic;
+
+      inject_req_i        : in  std_logic;
+      inject_ready_o      : out std_logic;
+      inject_packet_sel_i : in  std_logic_vector(2 downto 0);
+      inject_user_value_i : in  std_logic_vector(15 downto 0);
+      inject_mode_i       : in  std_logic_vector(1 downto 0);
+      -- 0 : default
+      -- 1 : corrupt
+      -- 2 : unused
+      -- 3 : unused
+
+      mem_addr_o : out std_logic_vector(9 downto 0);
+      mem_data_i : in  std_logic_vector(17 downto 0)
+      );
+
+end ep_tx_packet_injection;
+
+architecture rtl of ep_tx_packet_injection is
+
+  type t_state is (WAIT_IDLE, SOF, DO_INJECT, EOF);
+
+  alias template_last  : std_logic is mem_data_i(16);
+  alias template_first : std_logic is mem_data_i(16);
+  alias template_user  : std_logic is mem_data_i(17);
+
+  signal state   : t_state;
+  signal counter : unsigned(8 downto 0);
+
+  signal within_packet : std_logic;
+  signal select_inject : std_logic;
+
+  signal inj_src            : t_ep_internal_fabric;
+  signal inject_req_latched : std_logic;
+  signal first_word         : std_logic; -- ML: used for masking the first word (we use the 
+                                         --     same bit for SOF and EOF
+  -- ML: singals for RMON counters
+  signal no_template_error  : std_logic; -- ML: indicates that injection was attempted with no valid template
+  signal inject_done        : std_logic; -- ML: indicates that requrested injection was successful
+  
+begin  -- rtl
+
+  snk_dreq_o  <= '0' when (state = DO_INJECT) else src_dreq_i;
+  inject_done <= '1' when (state = EOF and src_dreq_i = '1') else '0';
+  
+  p_detect_within : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        within_packet <= '0';
+      else
+        if(snk_fab_i.sof = '1')then
+          within_packet <= '1';
+        end if;
+
+        if(snk_fab_i.eof = '1' or snk_fab_i.error = '1') then
+          within_packet <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_injection_request_ready : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        inject_ready_o     <= '1';
+        inject_req_latched <= '0';
+      else
+        if(inject_req_i = '1') then
+          inject_ready_o     <= '0';
+          inject_req_latched <= '1';
+        elsif(state = EOF and src_dreq_i = '1' ) then                     
+          inject_ready_o     <= '1';
+          inject_req_latched <= '0';
+        elsif(no_template_error = '1') then
+          inject_ready_o     <= '1';
+          inject_req_latched <= '0';        
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_injection_fsm : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state             <= WAIT_IDLE;
+        select_inject     <= '0';
+        no_template_error <= '0';
+        inj_src.sof       <= '0';
+        inj_src.eof       <= '0';
+        inj_src.dvalid    <= '0'; 
+        inj_src.error     <= '0';
+        first_word        <= '0';    
+      else
+        case state is
+          when WAIT_IDLE =>
+            inj_src.sof       <= '0';
+            inj_src.eof       <= '0';
+            inj_src.dvalid    <= '0';
+            inj_src.error     <= '0';
+            no_template_error <= '0';
+            first_word        <= '0';
+
+            if(inject_req_i = '1') then --ML: we make sure that we remember the packet_sel_i 
+                                        --    only when req_i HIGH
+              counter(8 downto 6) <= unsigned(inject_packet_sel_i);
+              counter(5 downto 0) <= (others => '0');
+            end if;
+
+            if(within_packet = '0' and inject_req_latched = '1' and no_template_error = '0') then
+              state         <= SOF;
+              select_inject <= '1';
+            else
+              select_inject <= '0';
+            end if;
+            
+          when SOF =>
+            if(template_first = '0') then  -- ML: check that the first word is valid, abort if error
+              state             <= WAIT_IDLE;
+              no_template_error <= '1';
+            elsif(src_dreq_i = '1') then
+              first_word  <= '1';  -- since the same bit is for SOF and EOF, we need to mask SOF
+                                   -- during first word
+              inj_src.sof <= '1';
+              state       <= DO_INJECT;
+            end if;
+
+          when DO_INJECT =>
+            inj_src.sof <= '0';
+
+            if(src_dreq_i = '1') then
+
+              inj_src.dvalid <= '1';
+              counter        <= counter + 1;
+
+            else
+              inj_src.dvalid <= '0';
+            end if;
+            
+            if(first_word = '1' and template_first = '0') then -- ML: first word read
+              first_word <= '0';
+            end if;
+            
+            if(template_last = '1' and inj_src.dvalid = '1' and first_word = '0' and src_dreq_i = '1') then
+              inj_src.dvalid    <= '0';       
+              state             <= EOF;
+              if(inject_mode_i = "01") then
+                inj_src.error     <= '1';    
+              else
+                inj_src.eof       <= '1';
+              end if;
+            end if;
+            
+          when EOF =>
+            inj_src.eof       <= '0';
+            inj_src.error     <= '0';
+            if(src_dreq_i = '1') then
+              state         <= WAIT_IDLE;
+              select_inject <= '0'; 
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+--   inj_src.bytesel <= '0';
+  -- the last word cannot be user-defined as we use the user bit to indicate  odd size
+  inj_src.bytesel <= template_user when (template_last = '1' and first_word = '0') else '0';
+--   inj_src.error   <= '0';
+
+  p_inj_src_data : process(template_user, inject_user_value_i, mem_data_i,template_last,first_word)
+  begin
+    if(template_user = '1' and template_last = '0' and first_word = '0') then
+      inj_src.data <= inject_user_value_i;
+    else
+      inj_src.data <= mem_data_i(15 downto 0);
+    end if;
+  end process;
+
+  src_fab_o <= inj_src when select_inject = '1' else snk_fab_i;
+
+
+  mem_addr_o <= '1' & std_logic_vector(counter);
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_path.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_path.vhd
new file mode 100644
index 000000000..ceba9c0a2
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_path.vhd
@@ -0,0 +1,352 @@
+-------------------------------------------------------------------------------
+-- Title      : Complete Transmit Path
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_tx_path.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-11-01
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Full transmit path of the endpoint (excluding the PCS).
+-- Chains the wishbone interface and header processor, followed by the VLAN unit
+-- (optional), packet injector (optional) and CRC inserter.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009 - 2012 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.wr_fabric_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+
+entity ep_tx_path is
+
+  generic(
+    g_with_vlans            : boolean;
+    g_with_timestamper      : boolean;
+    g_with_packet_injection : boolean;
+    g_with_inj_ctrl         : boolean := true;
+    g_force_gap_length      : integer;
+    g_runt_padding          : boolean;
+    g_use_new_crc           :	boolean
+    );
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+------------------------------------------------------------------------------
+-- Physical Coding Sublayer (PCS) interface
+------------------------------------------------------------------------------
+
+    pcs_fab_o   : out t_ep_internal_fabric;
+    pcs_error_i : in  std_logic;
+    pcs_busy_i  : in  std_logic;
+    pcs_dreq_i  : in  std_logic;
+
+-------------------------------------------------------------------------------
+-- WRF Sink (see WRF specification for the details)
+-------------------------------------------------------------------------------    
+
+    snk_i : in  t_wrf_sink_in;
+    snk_o : out t_wrf_sink_out;
+
+-------------------------------------------------------------------------------
+-- Flow Control Unit signals
+-------------------------------------------------------------------------------    
+
+-- TX send pause frame - when active, the framer will send a PAUSE frame
+-- as soon as possible. The pause quanta must be provided on tx_pause_delay_i input.
+    fc_pause_req_i   : in std_logic;
+    fc_pause_delay_i : in std_logic_vector(15 downto 0);
+
+-- TX send pause acknowledge - active after the current pause send request has
+-- been completed
+    fc_pause_ready_o : out std_logic;
+
+-- When active, the framer will allow for packet transmission.
+    fc_flow_enable_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- OOB/TSU signals
+-------------------------------------------------------------------------------    
+
+-- Port ID value
+    txtsu_port_id_o      : out std_logic_vector(4 downto 0);
+-- Frame ID value
+    txtsu_fid_o          : out std_logic_vector(16 -1 downto 0);
+-- Encoded timestamps
+    txtsu_ts_value_o     : out std_logic_vector(28 + 4 - 1 downto 0);
+    txtsu_ts_incorrect_o : out std_logic;
+
+-- TX timestamp strobe: HI tells the TX timestamping unit that a timestamp is
+-- available on txtsu_ts_value_o, txtsu_fid_o andd txtsu_port_id_o. The correctness
+-- of the timestamping is indiacted on txtsu_ts_incorrect_o. Line remains HI
+-- until assertion of txtsu_ack_i.
+    txtsu_stb_o : out std_logic;
+
+-- TX timestamp acknowledge: HI indicates that TXTSU has successfully received
+-- the timestamp
+    txtsu_ack_i : in std_logic;
+
+------------------------------------------------------------------------------
+-- Timestamp input from the timestamping unit
+------------------------------------------------------------------------------
+    txts_timestamp_i       : in std_logic_vector(31 downto 0);
+    txts_timestamp_valid_i : in std_logic;
+
+------------------------------------------------------------------------------
+-- Packet Injector (for TRU & HW-RSTP)
+------------------------------------------------------------------------------
+
+    inject_req_i        : in  std_logic                     := '0';
+    inject_ready_o      : out std_logic;
+    inject_packet_sel_i : in  std_logic_vector(2 downto 0)  := "000";
+    inject_user_value_i : in  std_logic_vector(15 downto 0) := x"0000";
+
+
+-------------------------------------------------------------------------------
+-- Control registers
+-------------------------------------------------------------------------------
+    ep_ctrl_i           : in std_logic :='1';
+    regs_i : in t_ep_out_registers;
+    regs_o : out t_ep_in_registers;
+    dbg_o          : out std_logic_vector(33 downto 0)
+    );
+
+
+end ep_tx_path;
+
+architecture rtl of ep_tx_path is
+
+  type t_fab_pipe is array(integer range <>) of t_ep_internal_fabric;
+
+  signal fab_pipe  : t_fab_pipe(4 downto 0);
+  signal dreq_pipe : std_logic_vector(4 downto 0);
+
+  signal vlan_mem_addr : std_logic_vector(9 downto 0);
+  signal vlan_mem_data : std_logic_vector(17 downto 0);
+  
+  signal txtsu_stb     : std_logic;
+
+  signal inject_req            : std_logic;
+  signal inject_ready          : std_logic;
+  signal inject_packet_sel     : std_logic_vector(2 downto 0);
+  signal inject_user_value     : std_logic_vector(15 downto 0);
+  signal inject_mode           : std_logic_vector( 1 downto 0);
+
+  signal inj_ctr_req            : std_logic;
+  signal inj_ctr_packet_sel     : std_logic_vector(2 downto 0);
+  signal inj_ctr_user_value     : std_logic_vector(15 downto 0);
+  signal inj_ctr_ena            : std_logic;
+  signal inj_ctr_mode           : std_logic_vector( 1 downto 0);
+
+
+begin  -- rtl
+
+  U_Header_Processor : ep_tx_header_processor
+    generic map (
+      g_with_packet_injection => g_with_packet_injection,
+      g_with_timestamper      => g_with_timestamper,
+      g_force_gap_length      => g_force_gap_length,
+      g_runt_padding          => g_runt_padding)
+    port map (
+      clk_sys_i              => clk_sys_i,
+      rst_n_i                => rst_n_i,
+      src_fab_o              => fab_pipe(0),
+      src_dreq_i             => dreq_pipe(0),
+      pcs_busy_i             => pcs_busy_i,
+      pcs_error_i            => pcs_error_i,
+      wb_snk_i               => snk_i,
+      wb_snk_o               => snk_o,
+      fc_pause_req_i         => fc_pause_req_i,
+      fc_pause_delay_i       => fc_pause_delay_i,
+      fc_pause_ready_o       => fc_pause_ready_o,
+      fc_flow_enable_i       => fc_flow_enable_i,
+      txtsu_port_id_o        => txtsu_port_id_o,
+      txtsu_fid_o            => txtsu_fid_o,
+      txtsu_ts_value_o       => txtsu_ts_value_o,
+      txtsu_ts_incorrect_o   => txtsu_ts_incorrect_o,
+      txtsu_stb_o            => txtsu_stb, --txtsu_stb_o,
+      txtsu_ack_i            => txtsu_ack_i,
+      txts_timestamp_i       => txts_timestamp_i,
+      txts_timestamp_valid_i => txts_timestamp_valid_i,
+      ep_ctrl_i              => ep_ctrl_i,
+      regs_i                 => regs_i);
+
+  txtsu_stb_o <= txtsu_stb;
+
+  assert not (g_with_packet_injection and not g_with_vlans)
+    report "wr_endpoint: packet injection requires VLAN support to be enabled" severity failure;
+
+  gen_with_inj_ctrl: if(g_with_inj_ctrl and g_with_packet_injection) generate
+    -- the injector control has two main purposes:
+    -- 1) control ep_tx_packet_injector so that it continuously generatres frames with
+    --    desired interframe gap
+    -- 2) block the possible traffic coming from SWcore 
+    --    - so that it does not disturb generation which is done only between frames from SWcore
+    --    - each frame coming from SWcore is "scanned" by Ethertype in the RAM which is used
+    --      for generation -> if ep_tx_vlan_unit is used (if dev/null was done after this module)
+    --      when ep_tx_packet_injection is used to genrate frame... we have problem cause two
+    --      modules read from the same RAM
+    U_Injector_ctr: ep_tx_inject_ctrl
+      generic map (
+        g_min_if_gap_length   => 5)
+      port map (
+        clk_sys_i             => clk_sys_i,
+        rst_n_i               => rst_n_i,
+        snk_fab_i             => fab_pipe(0),
+        snk_dreq_o            => dreq_pipe(0),
+        src_fab_o             => fab_pipe(1),
+        src_dreq_i            => dreq_pipe(1),
+        inject_req_o          => inj_ctr_req,
+        inject_ready_i        => inject_ready,
+        inject_packet_sel_o   => inj_ctr_packet_sel,
+        inject_user_value_o   => inj_ctr_user_value,
+        inject_ctr_ena_o      => inj_ctr_ena,
+        inject_ctr_mode_o     => inj_ctr_mode,
+        regs_i                => regs_i,
+        regs_o                => regs_o);
+  end generate gen_with_inj_ctrl;
+
+  inject_req        <= inj_ctr_req        when (inj_ctr_ena ='1') else inject_req_i;
+  inject_packet_sel <= inj_ctr_packet_sel when (inj_ctr_ena ='1') else inject_packet_sel_i;
+  inject_ready_o    <= inject_ready;
+
+  gen_without_inj_ctrl: if((not g_with_inj_ctrl) or (not g_with_packet_injection)) generate
+    fab_pipe(1)        <= fab_pipe(0);
+    dreq_pipe(0)       <= dreq_pipe(1);   
+    inj_ctr_req        <= '0';
+    inj_ctr_mode       <= (others => '0');
+    inj_ctr_packet_sel <= (others => '0');
+    inj_ctr_user_value <= (others => '0');
+    inj_ctr_ena        <= '0';
+    regs_o             <= c_ep_in_registers_init_value;
+  end generate gen_without_inj_ctrl;
+
+  gen_with_vlan_unit : if(g_with_vlans) generate
+    U_VLAN_Unit : ep_tx_vlan_unit
+      port map (
+        clk_sys_i         => clk_sys_i,
+        rst_n_i           => rst_n_i,
+        snk_fab_i         => fab_pipe(1),
+        snk_dreq_o        => dreq_pipe(1),
+        src_fab_o         => fab_pipe(2),
+        src_dreq_i        => dreq_pipe(2),
+        inject_mem_addr_i => vlan_mem_addr,
+        inject_mem_data_o => vlan_mem_data,
+        uram_offset_wr_i  => regs_i.vcr1_offset_wr_o,
+        uram_offset_i     => regs_i.vcr1_offset_o,
+        uram_data_i       => regs_i.vcr1_data_o);
+  end generate gen_with_vlan_unit;
+
+  gen_without_vlan_unit : if(not g_with_vlans) generate
+    fab_pipe(2)  <= fab_pipe(1);
+    dreq_pipe(1) <= dreq_pipe(2);
+  end generate gen_without_vlan_unit;
+
+  gen_with_injection : if(g_with_packet_injection) generate
+
+    inject_user_value <= inj_ctr_user_value when (inj_ctr_ena ='1') else inject_user_value_i;
+    inject_mode       <= inj_ctr_mode       when (inj_ctr_ena ='1') else "00";
+
+    U_Injector : ep_tx_packet_injection
+      port map (
+        clk_sys_i           => clk_sys_i,
+        rst_n_i             => rst_n_i,
+        snk_fab_i           => fab_pipe(2),
+        snk_dreq_o          => dreq_pipe(2),
+        src_fab_o           => fab_pipe(3),
+        src_dreq_i          => dreq_pipe(3),
+        inject_req_i        => inject_req,
+        inject_ready_o      => inject_ready,
+        inject_packet_sel_i => inject_packet_sel,
+        inject_user_value_i => inject_user_value,
+        inject_mode_i       => inject_mode,
+        mem_addr_o          => vlan_mem_addr,
+        mem_data_i          => vlan_mem_data);
+  end generate gen_with_injection;
+
+  gen_without_injection : if (not g_with_packet_injection) generate
+    fab_pipe(3)  <= fab_pipe(2);
+    dreq_pipe(2) <= dreq_pipe(3);
+    inject_ready <= '0';
+  end generate gen_without_injection;
+
+  U_Insert_CRC : ep_tx_crc_inserter
+    generic map(
+      g_use_new_crc => g_use_new_crc)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      snk_fab_i  => fab_pipe(3),
+      snk_dreq_o => dreq_pipe(3),
+      src_fab_o  => fab_pipe(4),
+      src_dreq_i => dreq_pipe(4),
+      dbg_o      => dbg_o(33 downto 31));
+
+  pcs_fab_o    <= fab_pipe(4);
+  dreq_pipe(4) <= pcs_dreq_i;
+
+--   GEN_DBG: for i in 0 to 3 generate
+--     dbg_o(i)    <= fab_pipe(i).sof;
+--     dbg_o(i+4)  <= fab_pipe(i).eof;
+--   end generate GEN_DBG;
+
+    dbg_o(0)    <= fab_pipe(0).sof;             -- 64
+    dbg_o(1)    <= fab_pipe(2).sof;             -- 65
+    dbg_o(2)    <= fab_pipe(3).sof;             -- 66
+    dbg_o(3)    <= fab_pipe(4).sof;             -- 67
+    dbg_o(4)    <= fab_pipe(0).eof;             -- 68
+    dbg_o(5)    <= fab_pipe(2).eof;             -- 69
+    dbg_o(6)    <= fab_pipe(3).eof;             -- 70
+    dbg_o(7)    <= fab_pipe(4).eof;             -- 71
+
+    dbg_o(8)    <= dreq_pipe(0);                -- 72
+    dbg_o(9)    <= dreq_pipe(2);                -- 73
+    dbg_o(10)   <= dreq_pipe(3);                -- 74 
+    dbg_o(11)   <= fab_pipe(0).dvalid;          -- 75
+    dbg_o(12)   <= fab_pipe(4).dvalid;          -- 32
+    -- new 4 bits
+    dbg_o(13)   <= dreq_pipe(4);                -- 33
+    dbg_o(14)   <= txtsu_stb;                   -- 34
+    dbg_o(15)   <= txtsu_ack_i;                 -- 35
+    dbg_o(16)   <= fab_pipe(2).dvalid;          -- 36
+--     dbg_o(28 downto 13) <= fab_pipe(2).data;
+    dbg_o(17)   <= inj_ctr_req;                 -- 37    
+    dbg_o(18)   <= inject_req;                  -- 38
+    dbg_o(19)   <= inject_ready;                -- 39                inj_ctr_user_value;
+    dbg_o(20)   <= inj_ctr_ena;                 -- 40
+    dbg_o(23 downto 21) <= inject_packet_sel;   -- 41-43
+    dbg_o(24)   <= inject_req_i;                -- 43
+    dbg_o(28 downto 25) <= fab_pipe(3).data(3 downto 0);
+--     dbg_o(28 downto 17) <= fab_pipe(3).data(11 downto 0);
+    dbg_o(30 downto 29) <= fab_pipe(3).addr;
+    
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_pcs_16bit.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
new file mode 100644
index 000000000..0bc801ee2
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
@@ -0,0 +1,546 @@
+-------------------------------------------------------------------------------
+-- Title      : 16-bit transmit path for 1000Base-X PCS
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_tx_pcs_16bit.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT section
+-- Created    : 2009-06-16
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Module implements a 16-bit transmit path for 802.3z 1000BaseX PCS.
+-- This block interfaces the Ethernet framer to TX PMA (Physical Medium Attachment).
+-- It performs preamble generation, insertion of idle patterns, all the low-level
+-- signalling. Strobing signal for taking TX timestamps is also generated.
+--
+-- Module uses two separate clocks: 62.5 MHz phy_tx_clk_i
+-- (Transmit clock for PHY) which clocks 8b10b signalling layer, and an async
+-- (clk_sys_i) which is used for data exchange with the rest of MAC data path. Data
+-- exchange between these clock domains is done using an async FIFO.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011-2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author   Description
+-- 2011-10-15  0.2      twlostow 16-bit version for Virtex 6 GTX
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+
+
+entity ep_tx_pcs_16bit is
+
+  port (
+-- reset (synchronous to clk_sys_i, active LO)
+    rst_n_i : in std_logic;
+
+-- system clock (faster than reference)
+    clk_sys_i : in std_logic;
+
+-- reset (phy_tx_clk_i sync)
+    rst_txclk_n_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- TX Framer inteface
+-------------------------------------------------------------------------------    
+
+-- TX Fabric input
+    pcs_fab_i : in t_ep_internal_fabric;
+
+-- HI pulse indicates an error during transmission of a frame (buffer underrun)
+    pcs_error_o : out std_logic;
+
+-- HI indicates that the PCS is busy (transmitting a frame or during autonegotiation)
+    pcs_busy_o : out std_logic;
+
+-- HI indicates that PCS FIFO is almost full.
+    pcs_dreq_o : out std_logic;
+
+-------------------------------------------------------------------------------
+-- WB controller control signals
+-------------------------------------------------------------------------------
+
+    mdio_mcr_reset_i      : in std_logic;
+-- Transmit Control Register, EN_PCS field
+    mdio_mcr_pdown_i      : in std_logic;
+-- Transmit Control Register, TX_CAL field
+    mdio_wr_spec_tx_cal_i : in std_logic;
+
+-- autonegotiation control
+    an_tx_en_i  : in std_logic;
+    an_tx_val_i : in std_logic_vector(15 downto 0);
+
+-- Timestamp strobe
+    timestamp_trigger_p_a_o : out std_logic;
+
+-- RMON events
+    rmon_tx_underrun : out std_logic;
+
+-------------------------------------------------------------------------------
+-- PHY Interface
+-------------------------------------------------------------------------------
+
+    phy_tx_clk_i       : in  std_logic;
+    phy_tx_data_o      : out std_logic_vector(15 downto 0);
+    phy_tx_k_o         : out std_logic_vector(1 downto 0);
+    phy_tx_disparity_i : in  std_logic;
+    phy_tx_enc_err_i   : in  std_logic;
+    
+    dbg_wr_count_o     : out std_logic_vector(5+4 downto 0);
+    dbg_rd_count_o     : out std_logic_vector(5+4 downto 0)
+    );
+
+end ep_tx_pcs_16bit;
+
+
+architecture behavioral of ep_tx_pcs_16bit is
+
+-- TX state machine definitions
+  type t_tbif_tx_state is (TX_COMMA_IDLE, TX_CAL, TX_CR12, TX_CR34, TX_SPD_PREAMBLE, TX_DATA, TX_PREAMBLE, TX_SFD, TX_EPD, TX_EXTEND, TX_GEN_ERROR);
+
+-- TX state machine signals
+
+  signal tx_is_k            : std_logic_vector(1 downto 0);
+  signal tx_odata_reg       : std_logic_vector(15 downto 0);
+  signal tx_catch_disparity : std_logic;
+  signal tx_state           : t_tbif_tx_state;
+  signal tx_cntr            : unsigned(3 downto 0);
+  signal tx_cr_alternate    : std_logic;
+
+-- TX clock alignment FIFO signals
+  signal fifo_packed_in, fifo_packed_out : std_logic_vector(17 downto 0);
+  signal fifo_empty                      : std_logic;
+  signal fifo_almost_empty               : std_logic;
+  signal fifo_almost_full                : std_logic;
+  signal fifo_enough_data                : std_logic;
+  signal fifo_wr                         : std_logic;
+  signal fifo_rd                         : std_logic := '0';
+  signal fifo_ready                      : std_logic;
+  signal fifo_clear_n, fifo_clear_n_d0, fifo_clear_n_d1, fifo_clear_n_d2, fifo_clear_n_d3, fifo_clear_n_d4 : std_logic;
+  signal fifo_read_int                   : std_logic;
+  signal fifo_fab                        : t_ep_internal_fabric;
+
+  signal tx_busy  : std_logic;
+  signal tx_error : std_logic;
+  signal rst_n_tx : std_logic;
+
+  signal mdio_mcr_reset_synced : std_logic;
+  signal mdio_mcr_pdown_synced : std_logic;
+
+  signal an_tx_en_synced : std_logic;
+  signal wr_count       :  std_logic_vector(6 downto 0);
+  signal rd_count       :  std_logic_vector(6 downto 0);
+  
+  constant tx_interframe_gap: unsigned(3 downto 0) := x"2"; --ML changed from "1000" to 0010
+  -- effectively it is 6 cycles for IFG:
+  -- last data (CRC) of the previous frame
+  -- -----------------------------------------
+  -- 3 cycles for count down (2 downto 0)
+  -- 1 cycle fifo_rd
+  -- 1 read SOF from FIFO
+  -- 1 cycle in TX_SPD_PREAMBLE
+  -- -----------------------------------------
+  -- just now we send Preamble
+  -- 
+begin
+
+  U_sync_pcs_busy_o : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => tx_busy,
+      synced_o => pcs_busy_o);
+
+  U_sync_pcs_error_o : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => tx_error,
+      ppulse_o => pcs_error_o);
+
+  U_sync_an_tx_en : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_tx_clk_i,
+      rst_n_i  => rst_n_i,
+      data_i   => an_tx_en_i,
+      synced_o => an_tx_en_synced);
+
+  U_sync_mcr_reset : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_tx_clk_i,
+      rst_n_i  => '1',
+      data_i   => mdio_mcr_reset_i,
+      synced_o => mdio_mcr_reset_synced,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_power_down : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_tx_clk_i,
+      rst_n_i  => '1',
+      data_i   => mdio_mcr_pdown_i,
+      synced_o => mdio_mcr_pdown_synced);
+
+  phy_tx_data_o <= tx_odata_reg;
+  phy_tx_k_o    <= tx_is_k;
+
+  rst_n_tx <= rst_txclk_n_i and not mdio_mcr_reset_synced;
+
+-------------------------------------------------------------------------------
+-- Clock alignment FIFO
+-------------------------------------------------------------------------------  
+
+
+ -------------------------------------------------------------------------------------------
+ -- some hacks to make pdown (in particular killing the link) work with Xilix native FIFOs
+ -- (the rst signal can be set (LOW) only after 4 cycles after rd_i is "unset" (LOW)
+ -------------------------------------------------------------------------------------------
+ fifo_clear_n_d0 <= '0' when (rst_n_i = '0') or (mdio_mcr_pdown_synced = '1') else '1';
+ p_fifo_clean : process(phy_tx_clk_i)
+  begin
+    if rising_edge(phy_tx_clk_i) then
+      fifo_clear_n_d1 <= fifo_clear_n_d0;
+      fifo_clear_n_d2 <= fifo_clear_n_d1;
+      fifo_clear_n_d3 <= fifo_clear_n_d2;
+      fifo_clear_n_d4 <= fifo_clear_n_d3;
+     end if;
+  end process;
+
+  fifo_clear_n <= fifo_clear_n_d4 when (fifo_clear_n_d0 = '0') else
+                  fifo_clear_n_d0;
+  fifo_read_int <= fifo_rd and not (fifo_fab.eof or fifo_fab.error or fifo_fab.sof) and
+                   fifo_clear_n_d0;
+  -------------------------------------------------------------------------------------------
+  f_pack_fifo_contents(pcs_fab_i, fifo_packed_in, fifo_wr, true);
+
+
+
+  U_TX_FIFO : generic_async_fifo
+    generic map (
+      g_data_width             => 18,
+      g_size                   => 128,--64,
+      g_with_rd_empty          => true,
+      g_with_rd_almost_empty   => true,
+      g_with_wr_almost_full    => true,
+      g_almost_empty_threshold => 20, -- must be not more/equal then mini-frame size (so 64/2), 
+                                      -- therwise frames get stuck in PCS 40,
+
+      -- ML this is a hack: we have a problem, the native FIFO that was used here
+      --    is not working ocrrectly (probably something with full/empty/etc signals
+      --    If this flags here are defined, another fifo (v6_hwfifo) is used, it is
+      --    not the best for resources... but works. We tried increaseing the size
+      --    of the FIFO, changing thresholds... not works very well. 
+      --    The native FIFO works somehow better with the following parameters
+      --        g_size = 1000
+      --        g_almost_full_threshold = 900
+      --     but it is still not good enough to use it
+      --     
+      g_with_rd_count          => true, -- ML debug
+      g_with_wr_count          => true, -- ML debug
+      
+      g_almost_full_threshold  => 100) -- fixme: make this a generic (or WB register)
+    port map (
+      rst_n_i           => fifo_clear_n,
+      clk_wr_i          => clk_sys_i,
+      d_i               => fifo_packed_in,
+      we_i              => fifo_wr,
+      wr_empty_o        => dbg_wr_count_o(0), --open,
+      wr_full_o         => dbg_wr_count_o(1), --open,
+      wr_almost_empty_o => dbg_wr_count_o(2), --open,
+      wr_almost_full_o  => fifo_almost_full,
+      wr_count_o        => wr_count,
+      clk_rd_i          => phy_tx_clk_i,
+      q_o               => fifo_packed_out,
+      rd_i              => fifo_read_int,
+      rd_empty_o        => fifo_empty,
+      rd_full_o         => dbg_rd_count_o(1) ,--open,
+      rd_almost_empty_o => fifo_almost_empty,
+      rd_almost_full_o  => dbg_rd_count_o(3),
+      rd_count_o        => rd_count); --rd_count);--dbg_rd_count_o); --open);
+
+      dbg_wr_count_o(3) <= fifo_almost_full;
+      dbg_rd_count_o(0) <= fifo_empty;
+      dbg_rd_count_o(2) <= fifo_almost_empty;
+      
+      dbg_wr_count_o(9 downto 4) <= wr_count(5 downto 0);
+      dbg_rd_count_o(9 downto 4) <= rd_count(5 downto 0);
+
+  fifo_enough_data <= not fifo_almost_empty;
+
+  p_gen_fifo_ready_flag : process(phy_tx_clk_i)
+  begin
+    if rising_edge(phy_tx_clk_i) then
+      fifo_ready <= fifo_read_int;
+    end if;
+  end process;
+
+  f_unpack_fifo_contents(fifo_packed_out, fifo_ready, fifo_fab, true);
+
+  -----------------------------------------------------------------------------
+  -- TX PCS state machine
+  -----------------------------------------------------------------------------
+  p_tx_fsm : process (phy_tx_clk_i)
+  begin
+    
+    if rising_edge(phy_tx_clk_i) then
+
+-- The PCS is reset or disabled
+      if(rst_n_tx = '0' or mdio_mcr_pdown_synced = '1') then
+        tx_state                <= TX_COMMA_IDLE;
+        timestamp_trigger_p_a_o <= '0';
+        fifo_rd                 <= '0';
+        tx_error                <= '0';
+        tx_odata_reg            <= (others => '0');
+        tx_is_k                 <= "00";
+        tx_cr_alternate         <= '0';
+        tx_catch_disparity      <= '0';
+        tx_cntr                 <= (others => '0');
+        rmon_tx_underrun        <= '0';
+      else
+        case tx_state is
+-------------------------------------------------------------------------------
+-- State COMMA: sends the /I/ sequence (K28.5 + D5.6/D16.2)
+-------------------------------------------------------------------------------            
+          when TX_COMMA_IDLE =>
+
+            -- clear the RMON/error pulse after 2 cycles (DATA->COMMA->IDLE) to
+            -- make sure is't long enough to trigger the event counter
+            rmon_tx_underrun <= '0';
+            tx_error         <= '0';
+
+            tx_is_k                   <= "10";
+            tx_odata_reg(15 downto 8) <= c_K28_5;
+
+            if (phy_tx_disparity_i = '1' and tx_catch_disparity = '1') then
+              tx_odata_reg(7 downto 0) <= c_d5_6;
+            else
+              tx_odata_reg(7 downto 0) <= c_d16_2;
+            end if;
+
+
+-- endpoint wants to send Config_Reg
+            if(an_tx_en_synced = '1') then
+              tx_state        <= TX_CR12;
+              tx_cr_alternate <= '0';
+              fifo_rd         <= '0';
+
+-- we've got a new frame in the FIFO
+            elsif (fifo_fab.sof = '1' and fifo_ready = '1' and tx_cntr = "0000")then
+              fifo_rd  <= '0';
+              tx_state <= TX_SPD_PREAMBLE;
+              tx_cntr  <= "0001";
+
+-- host requested a calibration pattern
+            elsif(mdio_wr_spec_tx_cal_i = '1') then
+              tx_state        <= TX_CAL;
+              fifo_rd         <= '0';
+              tx_cr_alternate <= '0';
+            else
+-- continue sending idle sequences and checking if something has arrived in the
+-- FIFO
+              if(tx_cntr /= "0000") then
+                fifo_rd <= '0';
+              else
+                fifo_rd <= (not fifo_empty) and fifo_enough_data;
+              end if;
+              tx_state <= TX_COMMA_IDLE;
+            end if;
+
+            tx_catch_disparity <= '0';
+
+            if(tx_cntr /= "0000") then
+              tx_cntr <= tx_cntr - 1;
+            end if;
+-------------------------------------------------------------------------------
+-- State: CAL: transmit the calibration sequence
+-------------------------------------------------------------------------------
+
+          when TX_CAL =>
+            tx_is_k         <= "11";
+            tx_odata_reg    <= c_k28_7 & c_k28_7;
+            tx_cr_alternate <= '1';
+            if(mdio_wr_spec_tx_cal_i = '0' and tx_cr_alternate = '1') then
+              tx_state <= TX_COMMA_IDLE;
+            end if;
+
+-------------------------------------------------------------------------------
+-- States: CR1, CR2, CR3, CR4: send the /C/ Configuration code set
+-------------------------------------------------------------------------------
+
+          when TX_CR12 =>
+            fifo_rd <= not fifo_empty;
+
+            tx_is_k                   <= "10";
+            tx_odata_reg(15 downto 8) <= c_k28_5;
+
+            if (tx_cr_alternate = '1') then
+              tx_odata_reg(7 downto 0) <= c_d21_5;
+            else
+              tx_odata_reg(7 downto 0) <= c_d2_2;
+            end if;
+
+            tx_cr_alternate <= not tx_cr_alternate;
+            tx_state        <= TX_CR34;
+
+          when TX_CR34 =>
+            fifo_rd <= not fifo_empty;
+
+            tx_is_k                   <= "00";
+            tx_odata_reg(15 downto 8) <= an_tx_val_i(7 downto 0);
+            tx_odata_reg(7 downto 0)  <= an_tx_val_i(15 downto 8);
+
+            if(an_tx_en_synced = '1') then
+              tx_state <= TX_CR12;
+            else
+              tx_state <= TX_COMMA_IDLE;
+            end if;
+
+
+-------------------------------------------------------------------------------
+-- State SPD: sends a start-of-packet delimeter
+-------------------------------------------------------------------------------
+          when TX_SPD_PREAMBLE =>
+            fifo_rd      <= '0';
+            tx_is_k      <= "10";
+            tx_odata_reg <= c_k27_7 & c_preamble_char;
+            tx_state     <= TX_PREAMBLE;
+
+-------------------------------------------------------------------------------
+-- State PREAMBLE: produces an Ethernet preamble
+-------------------------------------------------------------------------------
+          when TX_PREAMBLE =>
+            tx_is_k      <= "00";
+            tx_odata_reg <= c_preamble_char & c_preamble_char;
+
+            if (tx_cntr = "0000") then
+              tx_state <= TX_SFD;
+              fifo_rd  <= '1';
+            end if;
+
+            tx_cntr <= tx_cntr - 1;
+
+-------------------------------------------------------------------------------
+-- State SFD: outputs the start-of-frame delimeter (last byte of the preamble)
+-------------------------------------------------------------------------------            
+          when TX_SFD =>
+            tx_is_k                 <= "00";
+            tx_odata_reg            <= c_preamble_char & c_preamble_sfd;
+            timestamp_trigger_p_a_o <= '1';
+            tx_state                <= TX_DATA;
+
+          when TX_DATA =>
+
+            if((fifo_empty = '1' or fifo_fab.error = '1') and fifo_fab.eof = '0') then  -- FIFO underrun?
+              tx_odata_reg     <= c_k30_7 & c_k23_7;  -- emit error propagation code
+              tx_is_k          <= "11";
+              tx_state         <= TX_GEN_ERROR;
+              tx_error         <= not fifo_fab.error;
+              rmon_tx_underrun <= '1';
+              fifo_rd          <= '0';
+            else
+
+              if(fifo_fab.bytesel = '1') then
+                tx_odata_reg <= fifo_fab.DATA(15 downto 8) & c_k29_7;
+                tx_is_k      <= "01";
+              else
+                tx_odata_reg <= fifo_fab.DATA;
+                tx_is_k      <= "00";
+              end if;
+
+              if (fifo_fab.eof = '1') then
+                if(fifo_fab.bytesel = '1') then
+                  tx_state <= TX_EXTEND;
+                else
+                  tx_state <= TX_EPD;
+                end if;
+                fifo_rd <= '0';
+              end if;
+            end if;
+
+-------------------------------------------------------------------------------
+-- State EPD: send End-of-frame delimeter
+-------------------------------------------------------------------------------
+          when TX_EPD =>
+            timestamp_trigger_p_a_o <= '0';
+            tx_is_k                 <= "11";
+            tx_odata_reg            <= c_k29_7 & c_k23_7;
+            tx_catch_disparity      <= '1';
+            tx_cntr                 <= tx_interframe_gap;
+            tx_state                <= TX_COMMA_IDLE;
+
+--------------------------------------------------------------------------------
+-- State EXTEND: send the carrier extension
+-------------------------------------------------------------------------------
+          when TX_EXTEND =>
+            timestamp_trigger_p_a_o <= '0';
+            tx_is_k                 <= "11";
+            tx_odata_reg            <= c_k23_7 & c_k23_7;
+            tx_catch_disparity      <= '1';
+            tx_cntr                 <= tx_interframe_gap-1;--"0100";
+            tx_state                <= TX_COMMA_IDLE;
+
+-------------------------------------------------------------------------------
+-- State GEN_ERROR: entered when an error occured. Just terminates the frame.
+-------------------------------------------------------------------------------            
+          when TX_GEN_ERROR =>
+            tx_state <= TX_EPD;
+
+        end case;
+      end if;
+    end if;
+  end process;
+
+  process(phy_tx_clk_i)
+  begin
+    if rising_edge(phy_tx_clk_i) then
+      if fifo_empty = '0' or (tx_state /= TX_CR12 and tx_state /= TX_CR34 and tx_state /= TX_COMMA_IDLE) then
+        tx_busy <= '1';
+      else
+        tx_busy <= '0';
+      end if;
+    end if;
+  end process;
+
+  pcs_dreq_o <= not fifo_almost_full;
+  
+end behavioral;
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_pcs_8bit.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
new file mode 100644
index 000000000..db19a419a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
@@ -0,0 +1,514 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000BaseT/X MAC Endpoint - receive path PCS for 1000BaseX
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : ep_tx_pcs_tbi.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2009-06-16
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Module implements the transmit path for 802.3z 1000BaseX PCS.
+-- This block interfaces the Ethernet framer to TX PMA (Physical Medium Attachment).
+-- It performs preamble generation, insertion of idle patterns, all the low-level
+-- signalling (including 8b10b coding). Strobing signal for taking TX timestamps
+-- is also generated.
+--
+-- Module uses two separate clocks: 125 MHz tbi_tx_clk (or gtp_tx_clk)
+-- (Transmit clock for PHY) which clocks 8b10b signalling layer, and 62.5 MHz
+-- (clk_sys_i) which is used for data exchange with the rest of switch. Data
+-- exchange between these clock domains  is done using an async FIFO.
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author   Description
+-- 2009-06-16  0.1      twlostow Created (no error propagation supported yet)
+-- 2010-04-06  0.2      twlostow Cleanup, new timestamping/LCR scheme
+-- 2010-07-30  0.2      twlostow Fixed preamble length bug
+-- 2010-11-18  0.4      twlostow Added support for Xilinx GTP transceivers.
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+
+
+entity ep_tx_pcs_8bit is
+
+  port (
+-- reset (synchronous to refclk2, active LO)
+    rst_n_i : in std_logic;
+
+-- 62.5 MHz clock (refclk/2)
+    clk_sys_i : in std_logic;
+
+-- reset (phy_tx_clk_i sync)
+    rst_txclk_n_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- TX Framer inteface
+-------------------------------------------------------------------------------
+
+-- TX Fabric input
+    pcs_fab_i : in t_ep_internal_fabric;
+
+-- HI pulse indicates an error during transmission of a frame (buffer underrun)
+    pcs_error_o : out std_logic;
+
+-- HI indicates that the PCS is busy (transmitting a frame or during autonegotiation)
+    pcs_busy_o : out std_logic;
+
+-- HI indicates that PCS FIFO is almost full.
+    pcs_dreq_o : out std_logic;
+
+-------------------------------------------------------------------------------
+-- WB controller control signals
+-------------------------------------------------------------------------------
+
+    mdio_mcr_reset_i      : in std_logic;
+-- Transmit Control Register, EN_PCS field
+    mdio_mcr_pdown_i      : in std_logic;
+-- Transmit Control Register, TX_CAL field
+    mdio_wr_spec_tx_cal_i : in std_logic;
+
+-- autonegotiation control
+    an_tx_en_i  : in std_logic;
+    an_tx_val_i : in std_logic_vector(15 downto 0);
+
+-- Timestamp strobe
+    timestamp_trigger_p_a_o : out std_logic;
+
+-- RMON events
+    rmon_tx_underrun : out std_logic;
+
+-------------------------------------------------------------------------------
+-- PHY Interface
+-------------------------------------------------------------------------------
+
+    phy_tx_clk_i       : in  std_logic;
+    phy_tx_data_o      : out std_logic_vector(7 downto 0);
+    phy_tx_k_o         : out std_logic;
+    phy_tx_disparity_i : in  std_logic;
+    phy_tx_enc_err_i   : in  std_logic
+    );
+
+end ep_tx_pcs_8bit;
+
+
+architecture behavioral of ep_tx_pcs_8bit is
+
+-- TX state machine definitions
+  type t_tbif_tx_state is (TX_COMMA, TX_CAL, TX_CR1, TX_CR2, TX_CR3, TX_CR4, TX_SPD, TX_IDLE, TX_DATA, TX_PREAMBLE, TX_SFD, TX_EPD, TX_EXTEND, TX_GOTO_COMMA, TX_GEN_ERROR);
+
+-- TX state machine signals
+
+  signal tx_is_k            : std_logic;
+  signal tx_catch_disparity : std_logic;
+  signal tx_odata_reg       : std_logic_vector(7 downto 0);
+  signal tx_state           : t_tbif_tx_state;
+  signal tx_cntr            : unsigned(3 downto 0);
+  signal tx_cr_alternate    : std_logic;
+
+-- TX clock alignment FIFO signals
+  signal fifo_packed_in, fifo_packed_out : std_logic_vector(17 downto 0);
+  signal fifo_empty                      : std_logic;
+  signal fifo_almost_empty               : std_logic;
+  signal fifo_almost_full                : std_logic;
+  signal fifo_enough_data                : std_logic;
+  signal fifo_wr                         : std_logic;
+  signal fifo_rd                         : std_logic;
+  signal fifo_ready                      : std_logic;
+  signal fifo_clear_n                    : std_logic;
+  signal fifo_fab                        : t_ep_internal_fabric;
+
+  signal tx_rdreq_toggle : std_logic;
+  signal tx_odd_length   : std_logic;
+
+  signal tx_busy  : std_logic;
+  signal tx_error : std_logic;
+  signal rst_n_tx : std_logic;
+
+  signal mdio_mcr_reset_synced : std_logic;
+  signal mdio_mcr_pdown_synced : std_logic;
+  signal an_tx_en_synced       : std_logic;
+
+begin
+
+  U_sync_pcs_busy_o : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => tx_busy,
+      synced_o => pcs_busy_o);
+
+  U_sync_pcs_error_o : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => tx_error,
+      ppulse_o => pcs_error_o);
+
+  U_sync_an_tx_en : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_tx_clk_i,
+      rst_n_i  => '1',
+      data_i   => an_tx_en_i,
+      synced_o => an_tx_en_synced);
+
+  U_sync_mcr_reset : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_tx_clk_i,
+      rst_n_i  => '1',
+      data_i   => mdio_mcr_reset_i,
+      synced_o => mdio_mcr_reset_synced,
+      npulse_o => open,
+      ppulse_o => open);
+
+  U_sync_power_down : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_tx_clk_i,
+      rst_n_i  => '1',
+      data_i   => mdio_mcr_pdown_i,
+      synced_o => mdio_mcr_pdown_synced);
+
+  phy_tx_data_o <= tx_odata_reg;
+  phy_tx_k_o    <= tx_is_k;
+
+  rst_n_tx <= rst_txclk_n_i and not mdio_mcr_reset_synced;
+
+-------------------------------------------------------------------------------
+-- Clock alignment FIFO
+-------------------------------------------------------------------------------
+
+  fifo_clear_n <= '0' when (rst_n_i = '0') or (mdio_mcr_pdown_synced = '1') else '1';
+
+  f_pack_fifo_contents(pcs_fab_i, fifo_packed_in, fifo_wr, true);
+
+  U_TX_FIFO : generic_async_fifo
+    generic map (
+      g_data_width             => 18,
+      g_size                   => 64,
+      g_with_rd_empty          => true,
+      g_with_rd_almost_empty   => true,
+      g_with_rd_count          => true,
+      g_with_wr_almost_full    => true,
+      g_almost_empty_threshold => 16,
+      g_almost_full_threshold  => 56)  -- fixme: make this a generic (or WB register)
+    port map (
+      rst_n_i           => fifo_clear_n,
+      clk_wr_i          => clk_sys_i,
+      d_i               => fifo_packed_in,
+      we_i              => fifo_wr,
+      wr_empty_o        => open,
+      wr_full_o         => open,
+      wr_almost_empty_o => open,
+      wr_almost_full_o  => fifo_almost_full,
+      wr_count_o        => open,
+      clk_rd_i          => phy_tx_clk_i,
+      q_o               => fifo_packed_out,
+      rd_i              => fifo_rd,
+      rd_empty_o        => fifo_empty,
+      rd_full_o         => open,
+      rd_almost_empty_o => fifo_almost_empty,
+      rd_almost_full_o  => open,
+      rd_count_o        => open);
+
+  fifo_enough_data <= not fifo_almost_empty;
+
+  f_unpack_fifo_contents(fifo_packed_out, '1', fifo_fab, true);
+
+  -----------------------------------------------------------------------------
+  -- TX PCS state machine
+  -----------------------------------------------------------------------------
+
+  p_tx_fsm : process (phy_tx_clk_i)
+  begin
+
+    if rising_edge(phy_tx_clk_i) then
+
+-- The PCS is reset or disabled
+      if(rst_n_tx = '0' or mdio_mcr_pdown_synced = '1') then
+        tx_state                <= TX_COMMA;
+        timestamp_trigger_p_a_o <= '0';
+        fifo_rd                 <= '0';
+        tx_error                <= '0';
+        tx_odata_reg            <= (others => '0');
+        tx_is_k                 <= '0';
+        tx_cr_alternate         <= '0';
+        tx_catch_disparity      <= '0';
+        tx_cntr                 <= (others => '0');
+        tx_odd_length           <= '0';
+        tx_rdreq_toggle         <= '0';
+        rmon_tx_underrun        <= '0';
+
+      else
+
+        case tx_state is
+
+-------------------------------------------------------------------------------
+-- State COMMA: sends K28.5 comma character (first byte of /I/ sequence)
+-------------------------------------------------------------------------------
+          when TX_COMMA =>
+            tx_is_k      <= '1';
+            tx_odata_reg <= c_K28_5;
+            tx_state     <= TX_IDLE;
+            fifo_rd      <= '0';
+            fifo_ready   <= fifo_rd;
+
+-------------------------------------------------------------------------------
+-- State IDLE: sends the second code of the /I/ sequence with proper disparity\
+-------------------------------------------------------------------------------
+          when TX_IDLE =>
+
+            -- clear the RMON/error pulse after 2 cycles (DATA->COMMA->IDLE) to
+            -- make sure is't long enough to trigger the event counter
+            rmon_tx_underrun <= '0';
+            tx_error         <= '0';
+
+-- endpoint wants to send Config_Reg
+            if(an_tx_en_synced = '1') then
+              tx_state        <= TX_CR1;
+              tx_cr_alternate <= '0';
+              fifo_rd         <= '0';
+
+-- we've got a new frame in the FIFO
+            elsif (fifo_fab.sof = '1' and fifo_ready = '1' and tx_cntr = "0000")then
+              fifo_rd  <= '1';
+              tx_state <= TX_SPD;
+              tx_cntr  <= "0101";
+
+-- host requested a calibration pattern
+            elsif(mdio_wr_spec_tx_cal_i = '1') then
+              tx_state        <= TX_CAL;
+              fifo_rd         <= '0';
+              tx_cr_alternate <= '0';
+            else
+-- continue sending idle sequences and checking if something has arrived in the
+-- FIFO
+              if(tx_cntr /= "0000") then
+                fifo_rd <= '0';
+              else
+                fifo_rd <= (not fifo_empty) and fifo_enough_data;
+              end if;
+              tx_state <= TX_COMMA;
+            end if;
+
+            tx_is_k <= '0';
+
+-- check the disparity of the previously emitted code and choose whether to send
+-- /I1/ or /I2/
+            if (phy_tx_disparity_i = '1' and tx_catch_disparity = '1') then
+              tx_odata_reg <= c_d5_6;
+            else
+              tx_odata_reg <= c_d16_2;
+            end if;
+
+            tx_catch_disparity <= '0';
+
+            if(tx_cntr /= "0000") then
+              tx_cntr <= tx_cntr - 1;
+            end if;
+-------------------------------------------------------------------------------
+-- State: CAL: transmit the calibration sequence
+-------------------------------------------------------------------------------
+
+          when TX_CAL =>
+            tx_odata_reg <= c_k28_7;
+            tx_is_k      <= '1';
+            if(mdio_wr_spec_tx_cal_i = '0' and tx_cr_alternate = '1') then
+              tx_state <= TX_COMMA;
+            end if;
+
+            tx_cr_alternate <= not tx_cr_alternate;
+
+-------------------------------------------------------------------------------
+-- States: CR1, CR2, CR3, CR4: send the /C/ Configuration code set
+-------------------------------------------------------------------------------
+
+          when TX_CR1 =>
+            tx_is_k      <= '1';
+            tx_odata_reg <= c_k28_5;
+            tx_state     <= TX_CR2;
+
+          when TX_CR2 =>
+            tx_is_k <= '0';
+            if (tx_cr_alternate = '1') then
+              tx_odata_reg <= c_d21_5;
+            else
+              tx_odata_reg <= c_d2_2;
+            end if;
+            tx_cr_alternate <= not tx_cr_alternate;
+            tx_state        <= TX_CR3;
+
+          when TX_CR3 =>
+            tx_odata_reg <= an_tx_val_i(7 downto 0);
+            tx_state     <= TX_CR4;
+
+          when TX_CR4 =>
+            tx_odata_reg <= an_tx_val_i(15 downto 8);
+
+-- check if the autonegotiation control still wants the Config_Reg to be sent
+            if(an_tx_en_synced = '1') then
+              tx_state <= TX_CR1;
+            else
+              tx_state <= TX_COMMA;
+            end if;
+
+-------------------------------------------------------------------------------
+-- State SPD: sends a start-of-packet delimeter
+-------------------------------------------------------------------------------
+          when TX_SPD =>
+            fifo_rd      <= '0';
+            tx_is_k      <= '1';
+            tx_odata_reg <= c_k27_7;
+            tx_state     <= TX_PREAMBLE;
+
+-------------------------------------------------------------------------------
+-- State PREAMBLE: produces an Ethernet preamble
+-------------------------------------------------------------------------------
+          when TX_PREAMBLE =>
+            tx_is_k      <= '0';
+            tx_odata_reg <= c_preamble_char;
+
+            if (tx_cntr = "0000") then
+              tx_state        <= TX_SFD;
+              tx_rdreq_toggle <= '1';
+            end if;
+
+            tx_cntr <= tx_cntr - 1;
+
+
+-------------------------------------------------------------------------------
+-- State SFD: outputs the start-of-frame delimeter (last byte of the preamble)
+-------------------------------------------------------------------------------
+          when TX_SFD =>
+
+            tx_odata_reg            <= c_preamble_sfd;
+            tx_rdreq_toggle         <= '1';
+            tx_state                <= TX_DATA;
+            timestamp_trigger_p_a_o <= '1';
+
+          when TX_DATA =>
+
+
+            -- toggle the TX FIFO request line, so we read a 16-bit word
+            -- every 2 phy_tx_clk_i periods
+
+            fifo_rd <= tx_rdreq_toggle and not (fifo_empty or fifo_fab.eof);
+
+            if((fifo_empty = '1' or fifo_fab.error = '1') and fifo_fab.eof = '0') then  --
+              -- FIFO underrun?
+              tx_odata_reg     <= c_k30_7;  -- emit error propagation code
+              tx_is_k          <= '1';
+              tx_state         <= TX_GEN_ERROR;
+              tx_error         <= not fifo_fab.error;
+              rmon_tx_underrun <= '1';
+            else
+
+              if tx_rdreq_toggle = '1' then  -- send 16-bit word MSB or LSB
+                tx_odata_reg <= fifo_fab.data(15 downto 8);
+              else
+                tx_odata_reg <= fifo_fab.data(7 downto 0);
+              end if;
+
+              tx_rdreq_toggle <= not tx_rdreq_toggle;
+
+              -- handle the end of frame both for even- and odd-length frames
+              tx_odd_length <= fifo_fab.bytesel;
+
+              if (fifo_fab.eof = '1' and (tx_rdreq_toggle = '0' or (tx_rdreq_toggle = '1' and fifo_fab.bytesel = '1'))) then
+                tx_state <= TX_EPD;
+                fifo_rd  <= '0';
+              end if;
+            end if;
+
+-------------------------------------------------------------------------------
+-- State EPD: send End-of-frame delimeter
+-------------------------------------------------------------------------------
+          when TX_EPD =>
+            timestamp_trigger_p_a_o <= '0';
+
+            tx_is_k      <= '1';
+            tx_odata_reg <= c_k29_7;
+            tx_state     <= TX_EXTEND;
+
+--------------------------------------------------------------------------------
+-- State EXTEND: send the carrier extension
+-------------------------------------------------------------------------------
+          when TX_EXTEND =>
+            tx_odata_reg <= c_k23_7;
+            if(tx_odd_length = '0')then
+              tx_state           <= TX_COMMA;
+              tx_catch_disparity <= '1';
+            else
+              tx_odd_length <= '0';
+            end if;
+
+            tx_cntr <= "1000";
+
+-------------------------------------------------------------------------------
+-- State GEN_ERROR: entered when an error occured. Just terminates the frame.
+-------------------------------------------------------------------------------
+          when TX_GEN_ERROR =>
+            tx_state <= TX_EPD;
+
+          when others => null;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  process(phy_tx_clk_i)
+  begin
+    if rising_edge(phy_tx_clk_i) then
+      if fifo_empty = '0' or (tx_state /= TX_IDLE and tx_state /= TX_COMMA) then
+        tx_busy <= '1';
+      else
+        tx_busy <= '0';
+      end if;
+    end if;
+  end process;
+
+  pcs_dreq_o <= not fifo_almost_full;
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_vlan_unit.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_vlan_unit.vhd
new file mode 100644
index 000000000..97e1355ea
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_tx_vlan_unit.vhd
@@ -0,0 +1,305 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000base-X MAC/Endpoint - TX VLAN unit
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : ep_tx_vlan_unit.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-11-01
+-- Last update: 2012-11-16
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Performs VLAN untagging, if the VID of the egress packet is in
+-- the VLAN untagged set.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- FIXME: redo ram split between VLAN/PCK_INJ to use the unused 256 words and
+--        enable storing full-size frame (now max is 1024 bits, if we add 2x256
+--        bytes it will be exactly what we need) -> this requires chagnes in 
+--        HDL+SW+SV 
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2012-11-01  1.0      twlostow	    Created
+-- 2013-04-24  1.1      mlipinsk	    corrected VLAN untagging
+-- 2013-09-02  1.2      mlipinsk	    optimized by 1-cycle
+-- 2014-02-14  1.3      greg.d        Bufixed to use in WRSW NIC
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+
+entity ep_tx_vlan_unit is
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    snk_fab_i  : in  t_ep_internal_fabric;
+    snk_dreq_o : out std_logic;
+
+    src_fab_o  : out t_ep_internal_fabric;
+    src_dreq_i : in  std_logic;
+
+-- Shared buffer interface to the packet injection unit
+    inject_mem_addr_i : in  std_logic_vector(9 downto 0);
+    inject_mem_data_o : out std_logic_vector(17 downto 0);
+
+    uram_offset_wr_i  : in std_logic;
+    uram_offset_i     : in std_logic_vector(9 downto 0);
+    uram_data_i       : in std_logic_vector(17 downto 0)
+    );
+
+
+end ep_tx_vlan_unit;
+
+architecture behavioral of ep_tx_vlan_unit is
+
+
+  type t_state is (IDLE, CHECK_ETHERTYPE, PUSH_QHEADER_1, POP_QHEADER_2, POP_QHEADER_3, POP_ETHERTYPE);
+
+-- general signals
+  signal state   : t_state;
+  signal counter : unsigned(2 downto 0);
+
+  signal vut_rd_vid : std_logic_vector(11 downto 0);
+  signal vut_wr_vid : std_logic_vector(11 downto 0);
+  signal vut_untag, vut_untag_reg  : std_logic;
+
+  signal vut_stored_tag       : std_logic_vector(15 downto 0);
+  signal vut_stored_ethertype : std_logic_vector(15 downto 0);
+  signal flush_ethertype : std_logic;
+  signal flushed         : std_logic;
+
+  signal mem_addr_muxed : std_logic_vector(9 downto 0);
+  signal mem_rdata      : std_logic_vector(17 downto 0);
+  signal src_dreq_d0    : std_logic;
+
+begin  -- behavioral
+
+  vut_rd_vid <= snk_fab_i.data(11 downto 0);
+
+  -- FIXME:
+  -- ML: currently 256 words of the ram are not used and we don't have space to store 
+  --     max size frame (max tempalte is 512x2bytes = 1024 bytes)
+  --     we can use the unused bytes, just that some changes to sw+hw are needed
+  mem_addr_muxed <= ("00" & vut_rd_vid(11 downto 4)) when state /= IDLE else inject_mem_addr_i;
+
+  U_Untagged_Set_RAM : generic_dpram
+    generic map (
+      g_data_width => 18,
+      g_size       => 1024,
+      g_dual_clock => false)
+    port map (
+      rst_n_i => rst_n_i,
+      clka_i  => clk_sys_i,
+      clkb_i  => '0',
+      wea_i   => '0',
+      aa_i    => mem_addr_muxed,
+      qa_o    => mem_rdata,
+      web_i   => uram_offset_wr_i,
+      ab_i    => uram_offset_i,
+      db_i    => uram_data_i);
+
+  inject_mem_data_o <= mem_rdata;
+
+  vut_untag <= mem_rdata(to_integer(unsigned(vut_stored_tag(3 downto 0))));
+
+  p_delay_signals : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      src_dreq_d0 <= src_dreq_i;
+      
+    end if;
+  end process;
+
+  p_main_fsm : process (clk_sys_i)
+  begin  -- process
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state <= IDLE;
+      else
+        case state is
+          when IDLE =>
+            flushed <= '0';
+            if(snk_fab_i.sof = '1') then
+              counter <= (others => '0');
+            end if;
+            if(snk_fab_i.dvalid = '1' and snk_fab_i.addr = c_WRF_DATA and counter /= 6) then
+              counter <= counter + 1;
+            end if;
+            if(src_dreq_i='1') then
+              flush_ethertype <= '0';
+            end if;
+
+            if(snk_fab_i.dvalid = '1' and counter = 5) then
+              state <= CHECK_ETHERTYPE;
+            end if;
+
+          when CHECK_ETHERTYPE =>
+            vut_stored_ethertype <= snk_fab_i.data;
+
+            if(snk_fab_i.dvalid = '1') then
+
+              if(snk_fab_i.data = x"8100") then
+                state <= PUSH_QHEADER_1;
+              else
+                state <= IDLE;
+              end if;
+            end if;
+
+          when PUSH_QHEADER_1 =>
+            vut_untag_reg <= '0';
+
+            if(snk_fab_i.dvalid = '1') then
+              vut_stored_tag <= snk_fab_i.data;
+              state          <= POP_ETHERTYPE;
+            end if;
+
+          when POP_ETHERTYPE =>
+            if(vut_untag = '1') then
+              vut_untag_reg <= '1';
+            end if;
+            if(snk_fab_i.dvalid = '1') then
+              vut_stored_ethertype <= snk_fab_i.data; 
+            end if;
+            -- if dreq is '1' in POP_ETHERTYPE, that means we have passed
+            -- ethertype to src_fab_o and we don't need to do it after going to
+            -- IDLE.
+            if(src_dreq_d0 = '1') then
+              flush_ethertype <= '0';
+            elsif(src_dreq_i = '0' and flushed = '0') then
+              flush_ethertype <= '1';
+            end if;
+            if(src_dreq_d0 = '1') then
+              flushed <= '1';
+            end if;
+            if( (vut_untag = '1' or vut_untag_reg = '1') and src_dreq_i = '1') then
+              state <= IDLE; 
+            end if;
+            if(vut_untag='0' and vut_untag_reg='0' and src_dreq_d0='1') then
+              state <= POP_QHEADER_2;
+            end if;
+
+          when POP_QHEADER_2 =>
+            if(src_dreq_d0 = '1') then
+              state <= POP_QHEADER_3;
+            end if;
+
+          when POP_QHEADER_3 =>
+            if(src_dreq_d0 = '1') then
+              state <= IDLE;
+            end if;
+
+        end case;
+      end if;
+    end if;
+  end process;
+
+
+--   p_main_fsm_comb : process(snk_fab_i, src_dreq_d0, state, vut_stored_tag, vut_stored_ethertype, counter,vut_untag)
+  p_main_fsm_comb : process(snk_fab_i,src_dreq_i, src_dreq_d0, state, vut_stored_tag, vut_stored_ethertype, counter,vut_untag, flush_ethertype)
+  begin
+
+    case state is
+      when IDLE =>
+        src_fab_o.sof     <= snk_fab_i.sof;
+        src_fab_o.eof     <= snk_fab_i.eof;
+        src_fab_o.error   <= snk_fab_i.error;
+        src_fab_o.bytesel <= snk_fab_i.bytesel;
+      when others =>
+        src_fab_o.sof     <= '0';
+        src_fab_o.eof     <= '0';
+        src_fab_o.error   <= '0';
+        src_fab_o.bytesel <= '0';
+    end case;
+
+    case state is
+      when IDLE =>
+        snk_dreq_o       <= src_dreq_i;
+        -- validate Ethertype from POP_ETHERTYPE state if dreq was high
+        src_fab_o.dvalid <= snk_fab_i.dvalid or flush_ethertype;
+        src_fab_o.addr   <= snk_fab_i.addr;
+        if(flush_ethertype = '1') then
+          src_fab_o.data   <= vut_stored_ethertype;
+        else
+          src_fab_o.data   <= snk_fab_i.data;
+        end if;
+
+      when CHECK_ETHERTYPE =>
+        snk_dreq_o <= src_dreq_i;
+        if(snk_fab_i.data /= x"8100") then
+          src_fab_o.dvalid <= snk_fab_i.dvalid;
+        else
+          src_fab_o.dvalid <= '0';
+        end if;
+        src_fab_o.data <= snk_fab_i.data;
+        src_fab_o.addr <= snk_fab_i.addr;
+        
+      when PUSH_QHEADER_1 =>
+        snk_dreq_o       <= '1';
+        src_fab_o.dvalid <= '0';
+        src_fab_o.data   <= (others => 'X');
+        src_fab_o.addr   <= c_WRF_DATA;
+--       when CHECK_UNTAG =>
+--         snk_dreq_o       <= '0';
+--         src_fab_o.dvalid <= '0';
+--         src_fab_o.data   <= (others => 'X');
+        
+      when POP_ETHERTYPE =>
+        if(vut_untag = '1') then
+          snk_dreq_o       <= src_dreq_i       and src_dreq_d0;
+          src_fab_o.dvalid <= snk_fab_i.dvalid and src_dreq_d0;
+          src_fab_o.data   <= snk_fab_i.data;
+        else
+          src_fab_o.data   <= x"8100";
+          snk_dreq_o       <= '0';
+          src_fab_o.dvalid <= src_dreq_d0;          
+        end if;
+        src_fab_o.addr   <= c_WRF_DATA;
+
+      when POP_QHEADER_2 =>
+        snk_dreq_o       <= '0';
+        src_fab_o.dvalid <= src_dreq_d0;
+        src_fab_o.data   <= vut_stored_tag;--vut_stored_ethertype;
+        src_fab_o.addr   <= c_WRF_DATA;
+
+      when POP_QHEADER_3 =>
+        snk_dreq_o       <= src_dreq_i and src_dreq_d0;
+        src_fab_o.dvalid <= src_dreq_d0;
+        src_fab_o.data   <= vut_stored_ethertype; --vut_stored_tag;
+        src_fab_o.addr   <= c_WRF_DATA;
+    end case;
+  end process;
+  
+end behavioral;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_wishbone_controller.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_wishbone_controller.vhd
new file mode 100644
index 000000000..b58e0cfdc
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ep_wishbone_controller.vhd
@@ -0,0 +1,861 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR switch endpoint controller
+---------------------------------------------------------------------------------------
+-- File           : ep_wishbone_controller.vhd
+-- Author         : auto-generated by wbgen2 from ep_wishbone_controller.wb
+-- Created        : Wed Aug 16 22:43:41 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.ep_wbgen2_pkg.all;
+
+
+entity ep_wishbone_controller is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(4 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    tx_clk_i                                 : in     std_logic;
+    rx_clk_i                                 : in     std_logic;
+    regs_i                                   : in     t_ep_in_registers;
+    regs_o                                   : out    t_ep_out_registers
+  );
+end ep_wishbone_controller;
+
+architecture syn of ep_wishbone_controller is
+
+signal ep_ecr_portid_int                        : std_logic_vector(4 downto 0);
+signal ep_ecr_rst_cnt_dly0                      : std_logic      ;
+signal ep_ecr_rst_cnt_int                       : std_logic      ;
+signal ep_ecr_tx_en_int                         : std_logic      ;
+signal ep_ecr_rx_en_int                         : std_logic      ;
+signal ep_tscr_en_txts_int                      : std_logic      ;
+signal ep_tscr_en_rxts_int                      : std_logic      ;
+signal ep_tscr_cs_start_int                     : std_logic      ;
+signal ep_tscr_cs_start_int_delay               : std_logic      ;
+signal ep_tscr_cs_start_sync0                   : std_logic      ;
+signal ep_tscr_cs_start_sync1                   : std_logic      ;
+signal ep_tscr_cs_start_sync2                   : std_logic      ;
+signal ep_tscr_cs_done_sync0                    : std_logic      ;
+signal ep_tscr_cs_done_sync1                    : std_logic      ;
+signal ep_tscr_rx_cal_start_int                 : std_logic      ;
+signal ep_tscr_rx_cal_start_int_delay           : std_logic      ;
+signal ep_tscr_rx_cal_start_sync0               : std_logic      ;
+signal ep_tscr_rx_cal_start_sync1               : std_logic      ;
+signal ep_tscr_rx_cal_start_sync2               : std_logic      ;
+signal ep_rfcr_a_runt_int                       : std_logic      ;
+signal ep_rfcr_a_giant_int                      : std_logic      ;
+signal ep_rfcr_a_hp_int                         : std_logic      ;
+signal ep_rfcr_keep_crc_int                     : std_logic      ;
+signal ep_rfcr_hpap_int                         : std_logic_vector(7 downto 0);
+signal ep_rfcr_mru_int                          : std_logic_vector(13 downto 0);
+signal ep_vcr0_qmode_int                        : std_logic_vector(1 downto 0);
+signal ep_vcr0_fix_prio_int                     : std_logic      ;
+signal ep_vcr0_prio_val_int                     : std_logic_vector(2 downto 0);
+signal ep_vcr0_pvid_int                         : std_logic_vector(11 downto 0);
+signal ep_pfcr0_enable_int                      : std_logic      ;
+signal ep_fcr_rxpause_int                       : std_logic      ;
+signal ep_fcr_txpause_int                       : std_logic      ;
+signal ep_fcr_rxpause_802_1q_int                : std_logic      ;
+signal ep_fcr_txpause_802_1q_int                : std_logic      ;
+signal ep_fcr_tx_thr_int                        : std_logic_vector(7 downto 0);
+signal ep_fcr_tx_quanta_int                     : std_logic_vector(15 downto 0);
+signal ep_mach_int                              : std_logic_vector(15 downto 0);
+signal ep_macl_int                              : std_logic_vector(31 downto 0);
+signal ep_mdio_cr_addr_int                      : std_logic_vector(7 downto 0);
+signal ep_mdio_cr_rw_int                        : std_logic      ;
+signal ep_mdio_asr_phyad_int                    : std_logic_vector(7 downto 0);
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal rwaddr_reg                               : std_logic_vector(4 downto 0);
+signal ack_in_progress                          : std_logic      ;
+
+begin
+-- Some internal signals assignments
+  wrdata_reg <= wb_dat_i;
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      ep_ecr_portid_int <= "00000";
+      ep_ecr_rst_cnt_int <= '0';
+      ep_ecr_tx_en_int <= '0';
+      ep_ecr_rx_en_int <= '0';
+      ep_tscr_en_txts_int <= '0';
+      ep_tscr_en_rxts_int <= '0';
+      ep_tscr_cs_start_int <= '0';
+      ep_tscr_cs_start_int_delay <= '0';
+      ep_tscr_rx_cal_start_int <= '0';
+      ep_tscr_rx_cal_start_int_delay <= '0';
+      ep_rfcr_a_runt_int <= '0';
+      ep_rfcr_a_giant_int <= '0';
+      ep_rfcr_a_hp_int <= '0';
+      ep_rfcr_keep_crc_int <= '0';
+      ep_rfcr_hpap_int <= "00000000";
+      ep_rfcr_mru_int <= "00000000000000";
+      ep_vcr0_qmode_int <= "00";
+      ep_vcr0_fix_prio_int <= '0';
+      ep_vcr0_prio_val_int <= "000";
+      ep_vcr0_pvid_int <= "000000000000";
+      regs_o.vcr1_offset_wr_o <= '0';
+      regs_o.vcr1_data_wr_o <= '0';
+      regs_o.pfcr0_mm_addr_wr_o <= '0';
+      regs_o.pfcr0_mm_write_wr_o <= '0';
+      ep_pfcr0_enable_int <= '0';
+      regs_o.pfcr0_mm_data_msb_wr_o <= '0';
+      regs_o.pfcr1_mm_data_lsb_wr_o <= '0';
+      regs_o.tcar_pcp_map_load_o <= '0';
+      ep_fcr_rxpause_int <= '0';
+      ep_fcr_txpause_int <= '0';
+      ep_fcr_rxpause_802_1q_int <= '0';
+      ep_fcr_txpause_802_1q_int <= '0';
+      ep_fcr_tx_thr_int <= "00000000";
+      ep_fcr_tx_quanta_int <= "0000000000000000";
+      ep_mach_int <= "0000000000000000";
+      ep_macl_int <= "00000000000000000000000000000000";
+      regs_o.mdio_cr_data_wr_o <= '0';
+      ep_mdio_cr_addr_int <= "00000000";
+      ep_mdio_cr_rw_int <= '0';
+      ep_mdio_asr_phyad_int <= "00000000";
+      regs_o.dsr_lact_load_o <= '0';
+      regs_o.dmcr_en_load_o <= '0';
+      regs_o.dmcr_n_avg_load_o <= '0';
+      regs_o.dmsr_ps_rdy_load_o <= '0';
+      regs_o.inj_ctrl_pic_conf_ifg_load_o <= '0';
+      regs_o.inj_ctrl_pic_conf_sel_load_o <= '0';
+      regs_o.inj_ctrl_pic_conf_valid_load_o <= '0';
+      regs_o.inj_ctrl_pic_mode_id_load_o <= '0';
+      regs_o.inj_ctrl_pic_mode_valid_load_o <= '0';
+      regs_o.inj_ctrl_pic_ena_load_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          ep_ecr_rst_cnt_int <= '0';
+          regs_o.vcr1_offset_wr_o <= '0';
+          regs_o.vcr1_data_wr_o <= '0';
+          regs_o.pfcr0_mm_addr_wr_o <= '0';
+          regs_o.pfcr0_mm_write_wr_o <= '0';
+          regs_o.pfcr0_mm_data_msb_wr_o <= '0';
+          regs_o.pfcr1_mm_data_lsb_wr_o <= '0';
+          regs_o.tcar_pcp_map_load_o <= '0';
+          regs_o.mdio_cr_data_wr_o <= '0';
+          regs_o.dsr_lact_load_o <= '0';
+          regs_o.dmcr_en_load_o <= '0';
+          regs_o.dmcr_n_avg_load_o <= '0';
+          regs_o.dmsr_ps_rdy_load_o <= '0';
+          regs_o.inj_ctrl_pic_conf_ifg_load_o <= '0';
+          regs_o.inj_ctrl_pic_conf_sel_load_o <= '0';
+          regs_o.inj_ctrl_pic_conf_valid_load_o <= '0';
+          regs_o.inj_ctrl_pic_mode_id_load_o <= '0';
+          regs_o.inj_ctrl_pic_mode_valid_load_o <= '0';
+          regs_o.inj_ctrl_pic_ena_load_o <= '0';
+          ack_in_progress <= '0';
+        else
+          ep_tscr_cs_start_int <= ep_tscr_cs_start_int_delay;
+          ep_tscr_cs_start_int_delay <= '0';
+          ep_tscr_rx_cal_start_int <= ep_tscr_rx_cal_start_int_delay;
+          ep_tscr_rx_cal_start_int_delay <= '0';
+          regs_o.vcr1_offset_wr_o <= '0';
+          regs_o.vcr1_data_wr_o <= '0';
+          regs_o.pfcr0_mm_addr_wr_o <= '0';
+          regs_o.pfcr0_mm_write_wr_o <= '0';
+          regs_o.pfcr0_mm_data_msb_wr_o <= '0';
+          regs_o.pfcr1_mm_data_lsb_wr_o <= '0';
+          regs_o.tcar_pcp_map_load_o <= '0';
+          regs_o.mdio_cr_data_wr_o <= '0';
+          regs_o.dsr_lact_load_o <= '0';
+          regs_o.dmcr_en_load_o <= '0';
+          regs_o.dmcr_n_avg_load_o <= '0';
+          regs_o.dmsr_ps_rdy_load_o <= '0';
+          regs_o.inj_ctrl_pic_conf_ifg_load_o <= '0';
+          regs_o.inj_ctrl_pic_conf_sel_load_o <= '0';
+          regs_o.inj_ctrl_pic_conf_valid_load_o <= '0';
+          regs_o.inj_ctrl_pic_mode_id_load_o <= '0';
+          regs_o.inj_ctrl_pic_mode_valid_load_o <= '0';
+          regs_o.inj_ctrl_pic_ena_load_o <= '0';
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(4 downto 0) is
+          when "00000" => 
+            if (wb_we_i = '1') then
+              ep_ecr_portid_int <= wrdata_reg(4 downto 0);
+              ep_ecr_rst_cnt_int <= wrdata_reg(5);
+              ep_ecr_tx_en_int <= wrdata_reg(6);
+              ep_ecr_rx_en_int <= wrdata_reg(7);
+            end if;
+            rddata_reg(4 downto 0) <= ep_ecr_portid_int;
+            rddata_reg(5) <= '0';
+            rddata_reg(6) <= ep_ecr_tx_en_int;
+            rddata_reg(7) <= ep_ecr_rx_en_int;
+            rddata_reg(24) <= regs_i.ecr_feat_vlan_i;
+            rddata_reg(25) <= regs_i.ecr_feat_dmtd_i;
+            rddata_reg(26) <= regs_i.ecr_feat_ptp_i;
+            rddata_reg(27) <= regs_i.ecr_feat_dpi_i;
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(2) <= '1';
+            ack_in_progress <= '1';
+          when "00001" => 
+            if (wb_we_i = '1') then
+              ep_tscr_en_txts_int <= wrdata_reg(0);
+              ep_tscr_en_rxts_int <= wrdata_reg(1);
+              ep_tscr_cs_start_int <= wrdata_reg(2);
+              ep_tscr_cs_start_int_delay <= wrdata_reg(2);
+              ep_tscr_rx_cal_start_int <= wrdata_reg(4);
+              ep_tscr_rx_cal_start_int_delay <= wrdata_reg(4);
+            end if;
+            rddata_reg(0) <= ep_tscr_en_txts_int;
+            rddata_reg(1) <= ep_tscr_en_rxts_int;
+            rddata_reg(2) <= '0';
+            rddata_reg(3) <= ep_tscr_cs_done_sync1;
+            rddata_reg(4) <= '0';
+            rddata_reg(5) <= regs_i.tscr_rx_cal_result_i;
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(4) <= '1';
+            ack_in_progress <= '1';
+          when "00010" => 
+            if (wb_we_i = '1') then
+              ep_rfcr_a_runt_int <= wrdata_reg(0);
+              ep_rfcr_a_giant_int <= wrdata_reg(1);
+              ep_rfcr_a_hp_int <= wrdata_reg(2);
+              ep_rfcr_keep_crc_int <= wrdata_reg(3);
+              ep_rfcr_hpap_int <= wrdata_reg(11 downto 4);
+              ep_rfcr_mru_int <= wrdata_reg(25 downto 12);
+            end if;
+            rddata_reg(0) <= ep_rfcr_a_runt_int;
+            rddata_reg(1) <= ep_rfcr_a_giant_int;
+            rddata_reg(2) <= ep_rfcr_a_hp_int;
+            rddata_reg(3) <= ep_rfcr_keep_crc_int;
+            rddata_reg(11 downto 4) <= ep_rfcr_hpap_int;
+            rddata_reg(25 downto 12) <= ep_rfcr_mru_int;
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00011" => 
+            if (wb_we_i = '1') then
+              ep_vcr0_qmode_int <= wrdata_reg(1 downto 0);
+              ep_vcr0_fix_prio_int <= wrdata_reg(2);
+              ep_vcr0_prio_val_int <= wrdata_reg(6 downto 4);
+              ep_vcr0_pvid_int <= wrdata_reg(27 downto 16);
+            end if;
+            rddata_reg(1 downto 0) <= ep_vcr0_qmode_int;
+            rddata_reg(2) <= ep_vcr0_fix_prio_int;
+            rddata_reg(6 downto 4) <= ep_vcr0_prio_val_int;
+            rddata_reg(27 downto 16) <= ep_vcr0_pvid_int;
+            rddata_reg(3) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00100" => 
+            if (wb_we_i = '1') then
+              regs_o.vcr1_offset_wr_o <= '1';
+              regs_o.vcr1_data_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00101" => 
+            if (wb_we_i = '1') then
+              regs_o.pfcr0_mm_addr_wr_o <= '1';
+              regs_o.pfcr0_mm_write_wr_o <= '1';
+              ep_pfcr0_enable_int <= wrdata_reg(7);
+              regs_o.pfcr0_mm_data_msb_wr_o <= '1';
+            end if;
+            rddata_reg(7) <= ep_pfcr0_enable_int;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00110" => 
+            if (wb_we_i = '1') then
+              regs_o.pfcr1_mm_data_lsb_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00111" => 
+            if (wb_we_i = '1') then
+              regs_o.tcar_pcp_map_load_o <= '1';
+            end if;
+            rddata_reg(23 downto 0) <= regs_i.tcar_pcp_map_i;
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01000" => 
+            if (wb_we_i = '1') then
+              ep_fcr_rxpause_int <= wrdata_reg(0);
+              ep_fcr_txpause_int <= wrdata_reg(1);
+              ep_fcr_rxpause_802_1q_int <= wrdata_reg(2);
+              ep_fcr_txpause_802_1q_int <= wrdata_reg(3);
+              ep_fcr_tx_thr_int <= wrdata_reg(15 downto 8);
+              ep_fcr_tx_quanta_int <= wrdata_reg(31 downto 16);
+            end if;
+            rddata_reg(0) <= ep_fcr_rxpause_int;
+            rddata_reg(1) <= ep_fcr_txpause_int;
+            rddata_reg(2) <= ep_fcr_rxpause_802_1q_int;
+            rddata_reg(3) <= ep_fcr_txpause_802_1q_int;
+            rddata_reg(15 downto 8) <= ep_fcr_tx_thr_int;
+            rddata_reg(31 downto 16) <= ep_fcr_tx_quanta_int;
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01001" => 
+            if (wb_we_i = '1') then
+              ep_mach_int <= wrdata_reg(15 downto 0);
+            end if;
+            rddata_reg(15 downto 0) <= ep_mach_int;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01010" => 
+            if (wb_we_i = '1') then
+              ep_macl_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= ep_macl_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01011" => 
+            if (wb_we_i = '1') then
+              regs_o.mdio_cr_data_wr_o <= '1';
+              ep_mdio_cr_addr_int <= wrdata_reg(23 downto 16);
+              ep_mdio_cr_rw_int <= wrdata_reg(31);
+            end if;
+            rddata_reg(23 downto 16) <= ep_mdio_cr_addr_int;
+            rddata_reg(31) <= ep_mdio_cr_rw_int;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01100" => 
+            if (wb_we_i = '1') then
+              ep_mdio_asr_phyad_int <= wrdata_reg(23 downto 16);
+            end if;
+            rddata_reg(15 downto 0) <= regs_i.mdio_asr_rdata_i;
+            rddata_reg(23 downto 16) <= ep_mdio_asr_phyad_int;
+            rddata_reg(31) <= regs_i.mdio_asr_ready_i;
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= "11001010111111101011101010111110";
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01110" => 
+            if (wb_we_i = '1') then
+              regs_o.dsr_lact_load_o <= '1';
+            end if;
+            rddata_reg(0) <= regs_i.dsr_lstatus_i;
+            rddata_reg(1) <= regs_i.dsr_lact_i;
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01111" => 
+            if (wb_we_i = '1') then
+              regs_o.dmcr_en_load_o <= '1';
+              regs_o.dmcr_n_avg_load_o <= '1';
+            end if;
+            rddata_reg(0) <= regs_i.dmcr_en_i;
+            rddata_reg(27 downto 16) <= regs_i.dmcr_n_avg_i;
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10000" => 
+            if (wb_we_i = '1') then
+              regs_o.dmsr_ps_rdy_load_o <= '1';
+            end if;
+            rddata_reg(23 downto 0) <= regs_i.dmsr_ps_val_i;
+            rddata_reg(24) <= regs_i.dmsr_ps_rdy_i;
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10001" => 
+            if (wb_we_i = '1') then
+              regs_o.inj_ctrl_pic_conf_ifg_load_o <= '1';
+              regs_o.inj_ctrl_pic_conf_sel_load_o <= '1';
+              regs_o.inj_ctrl_pic_conf_valid_load_o <= '1';
+              regs_o.inj_ctrl_pic_mode_id_load_o <= '1';
+              regs_o.inj_ctrl_pic_mode_valid_load_o <= '1';
+              regs_o.inj_ctrl_pic_ena_load_o <= '1';
+            end if;
+            rddata_reg(15 downto 0) <= regs_i.inj_ctrl_pic_conf_ifg_i;
+            rddata_reg(18 downto 16) <= regs_i.inj_ctrl_pic_conf_sel_i;
+            rddata_reg(19) <= regs_i.inj_ctrl_pic_conf_valid_i;
+            rddata_reg(22 downto 20) <= regs_i.inj_ctrl_pic_mode_id_i;
+            rddata_reg(23) <= regs_i.inj_ctrl_pic_mode_valid_i;
+            rddata_reg(24) <= regs_i.inj_ctrl_pic_ena_i;
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- Port identifier
+  regs_o.ecr_portid_o <= ep_ecr_portid_int;
+-- Reset event counters
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ep_ecr_rst_cnt_dly0 <= '0';
+      regs_o.ecr_rst_cnt_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      ep_ecr_rst_cnt_dly0 <= ep_ecr_rst_cnt_int;
+      regs_o.ecr_rst_cnt_o <= ep_ecr_rst_cnt_int and (not ep_ecr_rst_cnt_dly0);
+    end if;
+  end process;
+  
+  
+-- Transmit path enable
+  regs_o.ecr_tx_en_o <= ep_ecr_tx_en_int;
+-- Receive path enable
+  regs_o.ecr_rx_en_o <= ep_ecr_rx_en_int;
+-- Feature present: VLAN tagging
+-- Feature present: DDMTD phase measurement
+-- Feature present: IEEE1588 timestamper
+-- Feature present: DPI packet classifier
+-- Transmit timestamping enable
+  regs_o.tscr_en_txts_o <= ep_tscr_en_txts_int;
+-- Receive timestamping enable
+  regs_o.tscr_en_rxts_o <= ep_tscr_en_rxts_int;
+-- Timestamping counter synchronization start
+  process (tx_clk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      regs_o.tscr_cs_start_o <= '0';
+      ep_tscr_cs_start_sync0 <= '0';
+      ep_tscr_cs_start_sync1 <= '0';
+      ep_tscr_cs_start_sync2 <= '0';
+    elsif rising_edge(tx_clk_i) then
+      ep_tscr_cs_start_sync0 <= ep_tscr_cs_start_int;
+      ep_tscr_cs_start_sync1 <= ep_tscr_cs_start_sync0;
+      ep_tscr_cs_start_sync2 <= ep_tscr_cs_start_sync1;
+      regs_o.tscr_cs_start_o <= ep_tscr_cs_start_sync2 and (not ep_tscr_cs_start_sync1);
+    end if;
+  end process;
+  
+  
+-- Timestamping counter synchronization done
+-- synchronizer chain for field : Timestamping counter synchronization done (type RO/WO, tx_clk_i -> clk_sys_i)
+  process (tx_clk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ep_tscr_cs_done_sync0 <= '0';
+      ep_tscr_cs_done_sync1 <= '0';
+    elsif rising_edge(tx_clk_i) then
+      ep_tscr_cs_done_sync0 <= regs_i.tscr_cs_done_i;
+      ep_tscr_cs_done_sync1 <= ep_tscr_cs_done_sync0;
+    end if;
+  end process;
+  
+  
+-- Start calibration of RX timestamper
+  process (rx_clk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      regs_o.tscr_rx_cal_start_o <= '0';
+      ep_tscr_rx_cal_start_sync0 <= '0';
+      ep_tscr_rx_cal_start_sync1 <= '0';
+      ep_tscr_rx_cal_start_sync2 <= '0';
+    elsif rising_edge(rx_clk_i) then
+      ep_tscr_rx_cal_start_sync0 <= ep_tscr_rx_cal_start_int;
+      ep_tscr_rx_cal_start_sync1 <= ep_tscr_rx_cal_start_sync0;
+      ep_tscr_rx_cal_start_sync2 <= ep_tscr_rx_cal_start_sync1;
+      regs_o.tscr_rx_cal_start_o <= ep_tscr_rx_cal_start_sync2 and (not ep_tscr_rx_cal_start_sync1);
+    end if;
+  end process;
+  
+  
+-- RX timestamper calibration result flag
+-- RX accept runts
+  regs_o.rfcr_a_runt_o <= ep_rfcr_a_runt_int;
+-- RX accept giants
+  regs_o.rfcr_a_giant_o <= ep_rfcr_a_giant_int;
+-- RX accept HP
+  regs_o.rfcr_a_hp_o <= ep_rfcr_a_hp_int;
+-- RX keep CRC
+  regs_o.rfcr_keep_crc_o <= ep_rfcr_keep_crc_int;
+-- RX Fiter HP Priorities
+  regs_o.rfcr_hpap_o <= ep_rfcr_hpap_int;
+-- Maximum receive unit (MRU)
+  regs_o.rfcr_mru_o <= ep_rfcr_mru_int;
+-- RX 802.1q port mode
+  regs_o.vcr0_qmode_o <= ep_vcr0_qmode_int;
+-- Force 802.1q priority
+  regs_o.vcr0_fix_prio_o <= ep_vcr0_fix_prio_int;
+-- Port-assigned 802.1q priority
+  regs_o.vcr0_prio_val_o <= ep_vcr0_prio_val_int;
+-- Port-assigned VID
+  regs_o.vcr0_pvid_o <= ep_vcr0_pvid_int;
+-- VLAN Untagged Set/Injection Buffer offset
+-- pass-through field: VLAN Untagged Set/Injection Buffer offset in register: VLAN Control Register 1
+  regs_o.vcr1_offset_o <= wrdata_reg(9 downto 0);
+-- VLAN Untagged Set/Injection Buffer value
+-- pass-through field: VLAN Untagged Set/Injection Buffer value in register: VLAN Control Register 1
+  regs_o.vcr1_data_o <= wrdata_reg(27 downto 10);
+-- Microcode Memory Address
+-- pass-through field: Microcode Memory Address in register: Packet Filter Control Register 0
+  regs_o.pfcr0_mm_addr_o <= wrdata_reg(5 downto 0);
+-- Microcode Memory Write Enable
+-- pass-through field: Microcode Memory Write Enable in register: Packet Filter Control Register 0
+  regs_o.pfcr0_mm_write_o <= wrdata_reg(6);
+-- Packet Filter Enable
+  regs_o.pfcr0_enable_o <= ep_pfcr0_enable_int;
+-- Microcode Memory Data (24 MSBs)
+-- pass-through field: Microcode Memory Data (24 MSBs) in register: Packet Filter Control Register 0
+  regs_o.pfcr0_mm_data_msb_o <= wrdata_reg(31 downto 8);
+-- Microcode Memory Data (12 LSBs)
+-- pass-through field: Microcode Memory Data (12 LSBs) in register: Packet Filter Control Register 1
+  regs_o.pfcr1_mm_data_lsb_o <= wrdata_reg(11 downto 0);
+-- 802.1Q priority tag to Traffic Class map
+  regs_o.tcar_pcp_map_o <= wrdata_reg(23 downto 0);
+-- RX Pause 802.3 enable
+  regs_o.fcr_rxpause_o <= ep_fcr_rxpause_int;
+-- TX Pause 802.3 enable
+  regs_o.fcr_txpause_o <= ep_fcr_txpause_int;
+-- Rx Pause 802.1Q enable
+  regs_o.fcr_rxpause_802_1q_o <= ep_fcr_rxpause_802_1q_int;
+-- Tx Pause 802.1Q enable (not implemented)
+  regs_o.fcr_txpause_802_1q_o <= ep_fcr_txpause_802_1q_int;
+-- TX pause threshold
+  regs_o.fcr_tx_thr_o <= ep_fcr_tx_thr_int;
+-- TX pause quanta
+  regs_o.fcr_tx_quanta_o <= ep_fcr_tx_quanta_int;
+-- MAC Address
+  regs_o.mach_o <= ep_mach_int;
+-- MAC Address
+  regs_o.macl_o <= ep_macl_int;
+-- MDIO Register Value
+-- pass-through field: MDIO Register Value in register: MDIO Control Register
+  regs_o.mdio_cr_data_o <= wrdata_reg(15 downto 0);
+-- MDIO Register Address
+  regs_o.mdio_cr_addr_o <= ep_mdio_cr_addr_int;
+-- MDIO Read/Write select
+  regs_o.mdio_cr_rw_o <= ep_mdio_cr_rw_int;
+-- MDIO Read Value
+-- MDIO PHY Address
+  regs_o.mdio_asr_phyad_o <= ep_mdio_asr_phyad_int;
+-- MDIO Ready
+-- Link status
+-- Link activity
+  regs_o.dsr_lact_o <= wrdata_reg(1);
+-- DMTD Phase measurement enable
+  regs_o.dmcr_en_o <= wrdata_reg(0);
+-- DMTD averaging samples
+  regs_o.dmcr_n_avg_o <= wrdata_reg(27 downto 16);
+-- DMTD Phase shift value
+-- DMTD Phase shift value ready
+  regs_o.dmsr_ps_rdy_o <= wrdata_reg(24);
+-- Config: Interframe GAP
+  regs_o.inj_ctrl_pic_conf_ifg_o <= wrdata_reg(15 downto 0);
+-- Config: packet pattern sel id
+  regs_o.inj_ctrl_pic_conf_sel_o <= wrdata_reg(18 downto 16);
+-- Config: valid
+  regs_o.inj_ctrl_pic_conf_valid_o <= wrdata_reg(19);
+-- Mode: packet generate mode
+  regs_o.inj_ctrl_pic_mode_id_o <= wrdata_reg(22 downto 20);
+-- Mode: valid
+  regs_o.inj_ctrl_pic_mode_valid_o <= wrdata_reg(23);
+-- Frame Generation Enabled
+  regs_o.inj_ctrl_pic_ena_o <= wrdata_reg(24);
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/wr_endpoint.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/wr_endpoint.vhd
new file mode 100644
index 000000000..f014eab9f
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/wr_endpoint.vhd
@@ -0,0 +1,1001 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000base-X MAC/Endpoint
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : wr_endpoint.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-04-26
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description: Module implements the top level for the White Rabbit Endpoint
+-- It's basically an extended Ethernet MAC providing extra timing/switch-specific
+-- features such as:
+-- - VLANs: inserting/removing tags (for ACCESS/TRUNK port support)
+-- - RX/TX precise timestaping
+-- - full PCS for optical Gigabit Ethernet 
+-- - decodes MAC addresses, VIDs and priorities and passes them to the RTU.
+-- Refer to the manual for more details.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 - 2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+use work.gencores_pkg.all;
+use work.endpoint_private_pkg.all;
+use work.endpoint_pkg.all;
+use work.ep_wbgen2_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.wishbone_pkg.all;
+
+entity wr_endpoint is
+  
+  generic (
+    g_interface_mode        : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity   : t_wishbone_address_granularity := WORD;
+    g_tx_force_gap_length   : integer                        := 0;
+    g_tx_runt_padding       : boolean                        := true;
+    g_simulation            : boolean                        := false;
+    g_pcs_16bit             : boolean                        := true;
+    g_rx_buffer_size        : integer                        := 1024;
+    g_with_rx_buffer        : boolean                        := true;
+    g_with_flow_control     : boolean                        := true;
+    g_with_timestamper      : boolean                        := true;
+    g_with_dpi_classifier   : boolean                        := false;
+    g_with_vlans            : boolean                        := true;
+    g_with_rtu              : boolean                        := true;
+    g_with_leds             : boolean                        := true;
+    g_with_dmtd             : boolean                        := false;
+    g_with_packet_injection : boolean                        := false;
+    g_use_new_rxcrc         : boolean                        := false;
+    g_use_new_txcrc         : boolean                        := false;
+    g_with_stop_traffic     : boolean                        := false
+    );
+  port (
+
+-------------------------------------------------------------------------------
+-- Clocks
+-------------------------------------------------------------------------------
+
+-- Endpoint transmit reference clock. Must be 125 MHz +- 100 ppm
+    clk_ref_i : in std_logic;
+
+-- reference clock / 2 (62.5 MHz, in-phase with refclk)
+    clk_sys_i : in std_logic;
+
+-- DMTD offset clock for phase tracking - used only if g_with_dmtd == true
+    clk_dmtd_i : in std_logic;
+
+-- resets for various clock domains
+    rst_sys_n_i   : in std_logic;
+    rst_ref_n_i   : in std_logic;
+    rst_dmtd_n_i  : in std_logic;
+    rst_txclk_n_i : in std_logic;
+    rst_rxclk_n_i : in std_logic;
+
+-- PPS input (1 clk_ref_i cycle HI) for synchronizing timestamp counter
+    pps_csync_p1_i : in std_logic;
+
+-- PPS valid input (clk_ref_i domain), when 1, the external PPS generator/servo
+-- is not adjusting the time scale, so we can safely timestamp.
+    pps_valid_i : in std_logic := '1';
+
+-------------------------------------------------------------------------------
+-- PHY Interace (8/16 bit PCS)
+-------------------------------------------------------------------------------    
+
+    phy_rst_o            : out std_logic;
+    phy_loopen_o         : out std_logic;
+    phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+    phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+    phy_sfp_tx_fault_i   : in  std_logic;
+    phy_sfp_los_i        : in  std_logic;
+    phy_sfp_tx_disable_o : out std_logic;
+    phy_rdy_i            : in  std_logic;
+
+    phy_ref_clk_i      : in  std_logic;
+    phy_tx_data_o      : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    phy_tx_k_o         : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+    phy_tx_disparity_i : in  std_logic;
+    phy_tx_enc_err_i   : in  std_logic;
+
+    phy_rx_data_i     : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    phy_rx_clk_i      : in std_logic;
+    phy_rx_k_i        : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+    phy_rx_enc_err_i  : in std_logic;
+    phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
+
+-------------------------------------------------------------------------------
+-- GMII Interface (8-bit)
+-------------------------------------------------------------------------------
+
+    gmii_tx_clk_i : in  std_logic := '0';
+    gmii_txd_o    : out std_logic_vector(7 downto 0);
+    gmii_tx_en_o  : out std_logic;
+    gmii_tx_er_o  : out std_logic;
+
+    gmii_rx_clk_i : in std_logic                    := '0';
+    gmii_rxd_i    : in std_logic_vector(7 downto 0) := x"00";
+    gmii_rx_er_i  : in std_logic                    := '0';
+    gmii_rx_dv_i  : in std_logic                    := '0';
+
+    ---------------------------------------------------------------------------
+    -- Wishbone I/O
+    ---------------------------------------------------------------------------
+
+    src_dat_o   : out std_logic_vector(15 downto 0);
+    src_adr_o   : out std_logic_vector(1 downto 0);
+    src_sel_o   : out std_logic_vector(1 downto 0);
+    src_cyc_o   : out std_logic;
+    src_stb_o   : out std_logic;
+    src_we_o    : out std_logic;
+    src_stall_i : in  std_logic;
+    src_ack_i   : in  std_logic;
+    src_err_i   : in  std_logic;
+
+    snk_dat_i   : in  std_logic_vector(15 downto 0);
+    snk_adr_i   : in  std_logic_vector(1 downto 0);
+    snk_sel_i   : in  std_logic_vector(1 downto 0);
+    snk_cyc_i   : in  std_logic;
+    snk_stb_i   : in  std_logic;
+    snk_we_i    : in  std_logic;
+    snk_stall_o : out std_logic;
+    snk_ack_o   : out std_logic;
+    snk_err_o   : out std_logic;
+    snk_rty_o   : out std_logic;
+
+-------------------------------------------------------------------------------
+-- TX timestamping unit interface
+-------------------------------------------------------------------------------  
+
+-- Port ID value
+    txtsu_port_id_o  : out std_logic_vector(4 downto 0);
+-- Frame ID value
+    txtsu_frame_id_o : out std_logic_vector(16 -1 downto 0);
+
+-- TX Timestamp and correctness info
+    txtsu_ts_value_o     : out std_logic_vector(28 + 4 - 1 downto 0);
+    txtsu_ts_incorrect_o : out std_logic;
+
+-- TX timestamp strobe: HI tells the TX timestamping unit that a timestamp is
+-- available on txtsu_ts_value_o, txtsu_fid_o andd txtsu_port_id_o. The correctness
+-- of the timestamping is indiacted on txtsu_ts_incorrect_o. Line remains HI
+-- until assertion of txtsu_ack_i.
+    txtsu_stb_o : out std_logic;
+
+-- TX timestamp acknowledge: HI indicates that TXTSU has successfully received
+-- the timestamp
+    txtsu_ack_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- RTU interface
+-------------------------------------------------------------------------------
+
+-- 1 indicates that coresponding RTU port is full.
+    rtu_full_i : in std_logic;
+
+-- 1 indicates that coresponding RTU port is almost full.
+    rtu_almost_full_i : in std_logic;
+
+-- request strobe, single HI pulse begins evaluation of the request. 
+    rtu_rq_strobe_p1_o : out std_logic;
+    
+    rtu_rq_abort_o : out std_logic;
+
+-- source and destination MAC addresses extracted from the packet header
+    rtu_rq_smac_o : out std_logic_vector(48 - 1 downto 0);
+    rtu_rq_dmac_o : out std_logic_vector(48 - 1 downto 0);
+
+-- VLAN id (extracted from the header for TRUNK ports and assigned by the port
+-- for ACCESS ports)
+    rtu_rq_vid_o : out std_logic_vector(12 - 1 downto 0);
+
+-- HI means that packet has valid assigned a valid VID (low - packet is untagged)
+    rtu_rq_has_vid_o : out std_logic;
+
+-- packet priority (either extracted from the header or assigned per port).
+    rtu_rq_prio_o : out std_logic_vector(3 - 1 downto 0);
+
+-- HI indicates that packet has assigned priority.
+    rtu_rq_has_prio_o : out std_logic;
+
+-------------------------------------------------------------------------------   
+-- Wishbone bus
+-------------------------------------------------------------------------------
+
+    wb_cyc_i   : in  std_logic;
+    wb_stb_i   : in  std_logic;
+    wb_we_i    : in  std_logic;
+    wb_sel_i   : in  std_logic_vector(3 downto 0);
+    wb_adr_i   : in  std_logic_vector(7 downto 0);
+    wb_dat_i   : in  std_logic_vector(31 downto 0);
+    wb_dat_o   : out std_logic_vector(31 downto 0);
+    wb_ack_o   : out std_logic;
+    wb_stall_o : out std_logic;
+
+-------------------------------------------------------------------------------
+-- direct output of packet filter  (for TRU/HW-RSTP)
+-------------------------------------------------------------------------------
+
+   pfilter_pclass_o : out std_logic_vector(7 downto 0);
+   pfilter_drop_o   : out std_logic;
+   pfilter_done_o   : out std_logic;
+
+-------------------------------------------------------------------------------
+-- control of PAUSE sending (ML: not used and not tested... TRU uses packet injection) -- 
+-------------------------------------------------------------------------------
+
+   fc_tx_pause_req_i   : in  std_logic                     := '0';
+   fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+   fc_tx_pause_ready_o : out std_logic;
+
+-------------------------------------------------------------------------------
+-- information about received PAUSE (for SWcore)
+-------------------------------------------------------------------------------
+
+   fc_rx_pause_start_p_o   : out std_logic;
+   fc_rx_pause_quanta_o    : out std_logic_vector(15 downto 0);
+   fc_rx_pause_prio_mask_o : out std_logic_vector(7 downto 0);
+   fc_rx_buffer_occupation_o : out std_logic_vector(7 downto 0);
+-------------------------------------------------------------------------------
+-- Packet Injection Interface (for TRU/HW-RSTP)
+-------------------------------------------------------------------------------
+
+-- injection request: triggers transmission of the packet to be injected,
+-- allowed when inject_ready = 1
+    inject_req_i : in std_logic := '0';
+
+-- injection ready flag: when true, user application can request asynchronous
+-- injection of a predefined packet
+    inject_ready_o : out std_logic;
+
+-- injection template selection (8 available)
+    inject_packet_sel_i : in std_logic_vector(2 downto 0) := "000";
+
+-- user-defined value to be embedded in the injected packet at a predefined
+-- location
+    inject_user_value_i : in std_logic_vector(15 downto 0) := x"0000";
+
+-------------------------------------------------------------------------------
+-- Misc stuff
+-------------------------------------------------------------------------------
+    rmon_events_o : out std_logic_vector(c_epevents_sz-1 downto 0);
+
+    txts_o     : out std_logic; 		                -- 2013-Nov-28 peterj added for debugging/calibration
+    rxts_o     : out std_logic; 		                -- 2013-Nov-28 peterj added for debugging/calibration
+
+    led_link_o : out std_logic;
+    led_act_o  : out std_logic;
+
+-- HI physically kills the link (turn of laser)
+    link_kill_i : in std_logic := '0';
+
+-- HI indicates that link is up (so cable connected), LOW indicates that link is faulty 
+-- (e.g.: cable disconnected)
+    link_up_o : out std_logic;
+
+    stop_traffic_i : in std_logic := '0';
+
+    dbg_tx_pcs_wr_count_o     : out std_logic_vector(5+4 downto 0);
+    dbg_tx_pcs_rd_count_o     : out std_logic_vector(5+4 downto 0);
+    nice_dbg_o  : out t_dbg_ep
+    );
+
+end wr_endpoint;
+
+architecture syn of wr_endpoint is
+
+  constant c_zeros : std_logic_vector(63 downto 0) := (others => '0');
+  constant c_ones  : std_logic_vector(63 downto 0) := (others => '0');
+
+-------------------------------------------------------------------------------
+  component dmtd_phase_meas
+    generic (
+      g_deglitcher_threshold : integer;
+      g_counter_bits         : integer);
+    port (
+      rst_sys_n_i    : in  std_logic;
+      rst_dmtd_n_i   : in  std_logic;
+      clk_sys_i      : in  std_logic;
+      clk_a_i        : in  std_logic;
+      clk_b_i        : in  std_logic;
+      clk_dmtd_i     : in  std_logic;
+      en_i           : in  std_logic;
+      navg_i         : in  std_logic_vector(11 downto 0);
+      phase_meas_o   : out std_logic_vector(31 downto 0);
+      phase_meas_p_o : out std_logic);
+  end component;
+
+-------------------------------------------------------------------------------
+-- TX FRAMER -> TX PCS signals
+-------------------------------------------------------------------------------
+
+  signal txpcs_fab   : t_ep_internal_fabric;
+  signal txpcs_dreq  : std_logic;
+  signal txpcs_error : std_logic;
+  signal txpcs_busy  : std_logic;
+
+-------------------------------------------------------------------------------
+-- Timestamping/OOB signals
+-------------------------------------------------------------------------------
+
+  signal txoob_fid_value : std_logic_vector(15 downto 0);
+  signal txoob_fid_stb   : std_logic;
+
+  signal txpcs_timestamp_trigger_p_a : std_logic;
+
+  signal txts_timestamp_stb   : std_logic;
+  signal txts_timestamp_valid : std_logic;
+  signal txts_timestamp_value : std_logic_vector(31 downto 0);
+
+
+  signal rxpcs_timestamp_stb         : std_logic;
+  signal rxpcs_timestamp_trigger_p_a : std_logic;
+  signal rxpcs_timestamp_valid       : std_logic;
+  signal rxpcs_timestamp_value       : std_logic_vector(31 downto 0);
+
+
+-------------------------------------------------------------------------------
+-- RX PCS -> RX DEFRAMER signals
+-------------------------------------------------------------------------------
+
+  signal rxpcs_fab             : t_ep_internal_fabric;
+  signal rxpath_fab            : t_ep_internal_fabric;
+  signal rxpcs_busy            : std_logic;
+  signal rxpcs_fifo_almostfull : std_logic;
+
+-------------------------------------------------------------------------------
+-- WB slave signals
+-------------------------------------------------------------------------------
+
+  signal regs_fromwb     : t_ep_out_registers;
+  signal regs_towb       : t_ep_in_registers;
+  signal regs_towb_ep    : t_ep_in_registers;
+  signal regs_towb_tsu   : t_ep_in_registers;
+  signal regs_towb_rpath : t_ep_in_registers;
+  signal regs_towb_tpath : t_ep_in_registers;
+  signal regs_towb_dmtd  : t_ep_in_registers;
+
+-------------------------------------------------------------------------------
+-- flow control signals
+-------------------------------------------------------------------------------
+
+  signal txfra_flow_enable : std_logic;
+  signal rxfra_pause_p     : std_logic;
+  signal rxfra_pause_delay : std_logic_vector(15 downto 0);
+
+  signal txfra_pause_req   : std_logic;
+  signal txfra_pause_ready : std_logic;
+  signal txfra_pause_delay : std_logic_vector(15 downto 0);
+
+  signal link_ok : std_logic;
+
+  signal txfra_enable : std_logic;
+  signal mdio_addr    : std_logic_vector(15 downto 0);
+
+  signal sink_in  : t_wrf_sink_in;
+  signal sink_out : t_wrf_sink_out;
+
+  signal src_in  : t_wrf_source_in;
+  signal src_out : t_wrf_source_out;
+
+  signal rst_n_rx : std_logic;
+
+  signal wb_in  : t_wishbone_slave_in;
+  signal wb_out : t_wishbone_slave_out;
+
+  signal extended_ADDR : std_logic_vector(c_wishbone_address_width-1 downto 0);
+
+  signal phase_meas    : std_logic_vector(31 downto 0);
+  signal phase_meas_p  : std_logic;
+  signal validity_cntr : unsigned(1 downto 0);
+  signal r_dmcr_en     : std_logic;
+  signal r_dmcr_n_avg  : std_logic_vector(11 downto 0);
+
+
+  signal rtu_rq               : t_ep_internal_rtu_request;
+  signal dvalid_tx, dvalid_rx : std_logic;
+
+-------------------------------------------------------------------------------
+-- TRU stuff
+-------------------------------------------------------------------------------
+  signal ep_ctrl        : std_logic;
+  signal pfilter_pclass : std_logic_vector(7 downto 0);
+  signal pfilter_drop   : std_logic;
+  signal pfilter_done   : std_logic;
+  signal tx_pclass      : std_logic_vector(7 downto 0);
+
+-------------------------------------------------------------------------------
+-- RMON signals
+-------------------------------------------------------------------------------
+  signal pcs_rmon     : t_rmon_triggers;
+  signal rx_path_rmon : t_rmon_triggers;
+  signal rmon         : t_rmon_triggers;
+ 
+-------------------------------------------------------------------------------
+-- chipscope (for desperates)
+-------------------------------------------------------------------------------
+  signal CONTROL0                   : std_logic_vector(35 downto 0);
+  signal TRIG0, TRIG1, TRIG2, TRIG3 : std_logic_vector(31 downto 0);
+
+  component chipscope_icon
+    port (
+      CONTROL0 : inout std_logic_vector(35 downto 0));
+  end component;
+
+  component chipscope_ila
+    port (
+      CONTROL : inout std_logic_vector(35 downto 0);
+      CLK     : in    std_logic;
+      TRIG0   : in    std_logic_vector(31 downto 0);
+      TRIG1   : in    std_logic_vector(31 downto 0);
+      TRIG2   : in    std_logic_vector(31 downto 0);
+      TRIG3   : in    std_logic_vector(31 downto 0));
+  end component;
+
+begin
+
+  rst_n_rx  <= rst_rxclk_n_i and phy_rdy_i;
+
+-------------------------------------------------------------------------------
+-- 1000Base-X PCS
+-------------------------------------------------------------------------------
+
+  mdio_addr <= regs_fromwb.mdio_asr_phyad_o & regs_fromwb.mdio_cr_addr_o;
+
+  U_PCS_1000BASEX : ep_1000basex_pcs
+    generic map (
+      g_simulation => g_simulation,
+      g_16bit      => g_pcs_16bit)
+    port map (
+      rst_sys_n_i   => rst_sys_n_i,
+      rst_rxclk_n_i => rst_rxclk_n_i,
+      rst_txclk_n_i => rst_txclk_n_i,
+      clk_sys_i     => clk_sys_i,
+
+      rxpcs_fab_o             => rxpcs_fab,
+      rxpcs_busy_o            => rxpcs_busy,
+      rxpcs_fifo_almostfull_i => rxpcs_fifo_almostfull,
+
+      rxpcs_timestamp_trigger_p_a_o => rxpcs_timestamp_trigger_p_a,
+      rxpcs_timestamp_i             => rxpcs_timestamp_value,
+      rxpcs_timestamp_stb_i         => rxpcs_timestamp_stb,
+      rxpcs_timestamp_valid_i       => rxpcs_timestamp_valid,
+
+      txpcs_fab_i   => txpcs_fab,
+      txpcs_busy_o  => txpcs_busy,
+      txpcs_dreq_o  => txpcs_dreq,
+      txpcs_error_o => txpcs_error,
+
+      txpcs_timestamp_trigger_p_a_o => txpcs_timestamp_trigger_p_a,
+
+      link_ok_o  => link_ok,
+      link_ctr_i => ep_ctrl,
+
+      serdes_rst_o             => phy_rst_o,
+      serdes_loopen_o          => phy_loopen_o,
+      serdes_loopen_vec_o      => phy_loopen_vec_o,
+      serdes_tx_prbs_sel_o     => phy_tx_prbs_sel_o,
+      serdes_sfp_tx_fault_i    => phy_sfp_tx_fault_i,
+      serdes_sfp_los_i         => phy_sfp_los_i,
+      serdes_sfp_tx_disable_o  => phy_sfp_tx_disable_o,
+      serdes_rdy_i             => phy_rdy_i,
+
+      serdes_tx_clk_i       => phy_ref_clk_i,
+      serdes_tx_data_o      => phy_tx_data_o,
+      serdes_tx_k_o         => phy_tx_k_o,
+      serdes_tx_disparity_i => phy_tx_disparity_i,
+      serdes_tx_enc_err_i   => phy_tx_enc_err_i,
+      serdes_rx_data_i      => phy_rx_data_i,
+      serdes_rx_clk_i       => phy_rx_clk_i,
+      serdes_rx_k_i         => phy_rx_k_i,
+      serdes_rx_enc_err_i   => phy_rx_enc_err_i,
+      serdes_rx_bitslide_i  => phy_rx_bitslide_i,
+
+      rmon_o => pcs_rmon,
+
+      mdio_addr_i  => mdio_addr,
+      mdio_data_i  => regs_fromwb.mdio_cr_data_o,
+      mdio_data_o  => regs_towb_ep.mdio_asr_rdata_i,
+      mdio_stb_i   => regs_fromwb.mdio_cr_data_wr_o,
+      mdio_rw_i    => regs_fromwb.mdio_cr_rw_o,
+      mdio_ready_o => regs_towb_ep.mdio_asr_ready_i,
+      dbg_tx_pcs_wr_count_o => dbg_tx_pcs_wr_count_o,
+      dbg_tx_pcs_rd_count_o => dbg_tx_pcs_rd_count_o,
+      nice_dbg_o   => nice_dbg_o.pcs);
+
+
+-------------------------------------------------------------------------------
+-- TX FRAMER
+-------------------------------------------------------------------------------
+
+--  txfra_enable <= link_ok and regs_fromwb.ecr_tx_en_o;
+
+--   txfra_pause_req <= '0';
+
+  U_Tx_Path : ep_tx_path
+    generic map (
+      g_with_packet_injection => g_with_packet_injection,
+      g_with_vlans            => g_with_vlans,
+      g_with_timestamper      => g_with_timestamper,
+      g_force_gap_length      => g_tx_force_gap_length,
+      g_runt_padding          => g_tx_runt_padding,
+      g_use_new_crc           => g_use_new_txcrc)
+    port map (
+      clk_sys_i        => clk_sys_i,
+      rst_n_i          => rst_sys_n_i,
+      pcs_error_i      => txpcs_error,
+      pcs_busy_i       => txpcs_busy,
+      pcs_fab_o        => txpcs_fab,
+      pcs_dreq_i       => txpcs_dreq,
+      snk_i            => sink_in,
+      snk_o            => sink_out,
+      fc_pause_req_i   => txfra_pause_req,
+      fc_pause_ready_o => txfra_pause_ready,
+      fc_pause_delay_i => txfra_pause_delay,
+      fc_flow_enable_i => txfra_flow_enable,
+      ep_ctrl_i        => ep_ctrl,
+      regs_i           => regs_fromwb,
+      regs_o           => regs_towb_tpath,
+
+      txts_timestamp_i       => txts_timestamp_value,
+      txts_timestamp_valid_i => txts_timestamp_valid,
+
+      txtsu_port_id_o      => txtsu_port_id_o,
+      txtsu_fid_o          => txtsu_frame_id_o,
+      txtsu_ts_value_o     => txtsu_ts_value_o,
+      txtsu_ts_incorrect_o => txtsu_ts_incorrect_o,
+      txtsu_stb_o          => txtsu_stb_o,
+      txtsu_ack_i          => txtsu_ack_i,
+
+      inject_req_i        => inject_req_i,
+      inject_user_value_i => inject_user_value_i,
+      inject_packet_sel_i => inject_packet_sel_i,
+      inject_ready_o      => inject_ready_o);
+
+
+  txfra_flow_enable <= '1';
+
+  sink_in.dat <= snk_dat_i;
+  sink_in.adr <= snk_adr_i;
+  sink_in.sel <= snk_sel_i;
+  sink_in.cyc <= snk_cyc_i;
+  sink_in.stb <= snk_stb_i;
+  sink_in.we  <= snk_we_i;
+  snk_stall_o <= sink_out.stall;
+  snk_ack_o   <= sink_out.ack;
+  snk_err_o   <= sink_out.err;
+  snk_rty_o   <= sink_out.rty;
+
+
+-------------------------------------------------------------------------------
+-- RX deframer
+-------------------------------------------------------------------------------
+
+  U_Rx_Path : ep_rx_path
+    generic map (
+      g_with_vlans          => g_with_vlans,
+      g_with_dpi_classifier => g_with_dpi_classifier,
+      g_with_rtu            => g_with_rtu,
+      g_with_rx_buffer      => g_with_rx_buffer,
+      g_rx_buffer_size      => g_rx_buffer_size,
+      g_use_new_crc         => g_use_new_rxcrc)
+    port map (
+      clk_sys_i => clk_sys_i,
+      clk_rx_i  => phy_rx_clk_i,
+
+      rst_n_sys_i => rst_sys_n_i,
+      rst_n_rx_i  => rst_n_rx,
+
+      pcs_fab_i             => rxpath_fab,
+      pcs_fifo_almostfull_o => rxpcs_fifo_almostfull,
+      pcs_busy_i            => rxpcs_busy,
+
+      fc_pause_p_o         => fc_rx_pause_start_p_o,  --rxfra_pause_p,
+      fc_pause_quanta_o    => fc_rx_pause_quanta_o,   --rxfra_pause_delay,
+      fc_pause_prio_mask_o => fc_rx_pause_prio_mask_o,
+      fc_buffer_occupation_o => fc_rx_buffer_occupation_o,
+
+      rmon_o => rx_path_rmon,
+      regs_i => regs_fromwb,
+      regs_o => regs_towb_rpath,
+
+      pfilter_pclass_o => pfilter_pclass,
+      pfilter_drop_o   => pfilter_drop,
+      pfilter_done_o   => pfilter_done,
+
+      rtu_full_i     => rtu_full_i,
+      rtu_rq_o       => rtu_rq,
+      rtu_rq_valid_o => rtu_rq_strobe_p1_o,
+      rtu_rq_abort_o => rtu_rq_abort_o,
+      src_wb_o       => src_out,
+      src_wb_i       => src_in,
+      nice_dbg_o     => nice_dbg_o.rxpath);
+
+
+  rtu_rq_smac_o     <= rtu_rq.smac;
+  rtu_rq_dmac_o     <= rtu_rq.dmac;
+  rtu_rq_vid_o      <= rtu_rq.vid;
+  rtu_rq_prio_o     <= rtu_rq.prio;
+  rtu_rq_has_vid_o  <= rtu_rq.has_vid;
+  rtu_rq_has_prio_o <= rtu_rq.has_prio;
+
+  src_dat_o    <= src_out.dat;
+  src_adr_o    <= src_out.adr;
+  src_sel_o    <= src_out.sel;
+  src_cyc_o    <= src_out.cyc;
+  src_stb_o    <= src_out.stb;
+  src_we_o     <= src_out.we;
+  src_in.stall <= src_stall_i;
+  src_in.ack   <= src_ack_i;
+  src_in.err   <= src_err_i;
+  src_in.rty   <= '0';
+
+-------------------------------------------------------------------------------
+-- Flow control unit
+-------------------------------------------------------------------------------
+
+  --U_FLOW_CTL : ep_flow_control
+  --  port map (
+  --    clk_sys_i => clk_sys_i,
+  --    rst_n_i   => rst_n_i,
+
+  --    rx_pause_p1_i    => rxfra_pause_p,
+  --    rx_pause_delay_i => rxfra_pause_delay,
+
+  --    tx_pause_o       => txfra_pause,
+  --    tx_pause_delay_o => txfra_pause_delay,
+  --    tx_pause_ack_i   => txfra_pause_ack,
+
+  --    tx_flow_enable_o => txfra_flow_enable,
+
+  --    rx_buffer_used_i => rx_buffer_used,
+
+  --    ep_fcr_txpause_i   => regs.fcr_txpause_o,
+  --    ep_fcr_rxpause_i   => regs.fcr_rxpause_o,
+  --    ep_fcr_tx_thr_i    => regs.fcr_tx_thr_o,
+  --    ep_fcr_tx_quanta_i => regs.fcr_tx_quanta_o,
+  --    rmon_rcvd_pause_o  => rmon.rx_pause,
+  --    rmon_sent_pause_o  => rmon.tx_pause
+  --    );
+
+-------------------------------------------------------------------------------
+-- Timestamping unit
+-------------------------------------------------------------------------------
+
+  U_EP_TSU : ep_timestamping_unit
+    generic map (
+      g_timestamp_bits_r => 28,
+      g_timestamp_bits_f => 4,
+      g_ref_clock_rate   => f_pcs_clock_rate(g_pcs_16bit))
+    port map (
+      clk_ref_i      => clk_ref_i,
+      clk_rx_i       => phy_rx_clk_i,
+      clk_sys_i      => clk_sys_i,
+      rst_n_rx_i     => rst_rxclk_n_i,
+      rst_n_sys_i    => rst_sys_n_i,
+      rst_n_ref_i    => rst_ref_n_i,
+      pps_csync_p1_i => pps_csync_p1_i,
+      pps_valid_i    => pps_valid_i,
+
+      tx_timestamp_trigger_p_a_i => txpcs_timestamp_trigger_p_a,
+      rx_timestamp_trigger_p_a_i => rxpcs_timestamp_trigger_p_a,
+
+      rxts_timestamp_o       => rxpcs_timestamp_value,
+      rxts_timestamp_valid_o => rxpcs_timestamp_valid,
+      rxts_timestamp_stb_o   => rxpcs_timestamp_stb,
+
+      txts_timestamp_o       => txts_timestamp_value,
+      txts_timestamp_valid_o => txts_timestamp_valid,
+
+      txts_o                 => txts_o,                   -- 2013-Nov-28 peterj added for debugging/calibration
+      rxts_o                 => rxts_o, 		              -- 2013-Nov-28 peterj added for debugging/calibration
+
+      regs_i => regs_fromwb,
+      regs_o => regs_towb_tsu);
+
+
+-------------------------------------------------------------------------------
+-- Wishbone controller & IO registers
+-------------------------------------------------------------------------------
+
+  extended_ADDR <= std_logic_vector(resize(unsigned(wb_adr_i), c_wishbone_address_width));
+
+  U_Slave_adapter : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => false,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_sys_n_i,
+      sl_adr_i   => extended_ADDR,
+      sl_dat_i   => wb_dat_i,
+      sl_sel_i   => wb_sel_i,
+      sl_cyc_i   => wb_cyc_i,
+      sl_stb_i   => wb_stb_i,
+      sl_we_i    => wb_we_i,
+      sl_dat_o   => wb_dat_o,
+      sl_ack_o   => wb_ack_o,
+      sl_stall_o => wb_stall_o,
+      master_i   => wb_out,
+      master_o   => wb_in);
+
+  U_WB_SLAVE : ep_wishbone_controller
+    port map (
+      rst_n_i    => rst_sys_n_i,
+      clk_sys_i  => clk_sys_i,
+      wb_adr_i   => wb_in.adr(4 downto 0),
+      wb_dat_i   => wb_in.dat,
+      wb_dat_o   => wb_out.dat,
+      wb_cyc_i   => wb_in.cyc,
+      wb_sel_i   => wb_in.sel,
+      wb_stb_i   => wb_in.stb,
+      wb_we_i    => wb_in.we,
+      wb_ack_o   => wb_out.ack,
+      wb_stall_o => open,
+
+      tx_clk_i => clk_ref_i,
+      rx_clk_i => phy_rx_clk_i,
+
+      regs_o => regs_fromwb,
+      regs_i => regs_towb
+      );     
+
+  wb_out.stall <= '0';
+  wb_out.rty   <= '0';
+  wb_out.err   <= '0';
+  wb_out.int   <= '0';
+
+  regs_towb <= regs_towb_ep or regs_towb_tsu or regs_towb_rpath or regs_towb_tpath or regs_towb_dmtd;
+
+
+  p_link_activity : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+
+      if(rst_sys_n_i = '0') or
+        (regs_fromwb.dsr_lact_o = '1' and regs_fromwb.dsr_lact_load_o = '1') then
+        regs_towb_ep.dsr_lact_i <= '0';
+      else
+        regs_towb_ep.dsr_lact_i <= dvalid_rx or dvalid_tx;
+      end if;
+    end if;
+  end process;
+
+  -- drive unused regs_towb_ep signals
+  regs_towb_ep.ecr_feat_vlan_i           <= '0';
+  regs_towb_ep.ecr_feat_dmtd_i           <= '0';
+  regs_towb_ep.ecr_feat_ptp_i            <= '0';
+  regs_towb_ep.ecr_feat_dpi_i            <= '0';
+  regs_towb_ep.tscr_cs_done_i            <= '0';
+  regs_towb_ep.tscr_rx_cal_result_i      <= '0';
+  regs_towb_ep.tcar_pcp_map_i            <= (others => '0');
+  regs_towb_ep.dsr_lstatus_i             <= '0';
+  regs_towb_ep.dmcr_en_i                 <= '0';
+  regs_towb_ep.dmcr_n_avg_i              <= (others => '0');
+  regs_towb_ep.inj_ctrl_pic_conf_ifg_i   <= (others => '0');
+  regs_towb_ep.inj_ctrl_pic_conf_sel_i   <= (others => '0');
+  regs_towb_ep.inj_ctrl_pic_conf_valid_i <= '0';
+  regs_towb_ep.inj_ctrl_pic_mode_id_i    <= (others => '0');
+  regs_towb_ep.inj_ctrl_pic_mode_valid_i <= '0';
+  regs_towb_ep.inj_ctrl_pic_ena_i        <= '0';
+
+-------------------------------------------------------------------------------
+-- DMTD phase meter
+------------------------------------------------------------------------------  
+
+  gen_with_dmtd : if(g_with_dmtd) generate
+    U_DMTD : dmtd_phase_meas
+      generic map (
+        g_counter_bits         => 14,
+        g_deglitcher_threshold => 1000)
+      port map (
+        clk_sys_i => clk_sys_i,
+
+        clk_a_i    => phy_ref_clk_i,
+        clk_b_i    => phy_rx_clk_i,
+        clk_dmtd_i => clk_dmtd_i,
+
+        rst_sys_n_i  => rst_sys_n_i,
+        rst_dmtd_n_i => rst_dmtd_n_i,
+
+        en_i           => r_dmcr_en,
+        navg_i         => r_dmcr_n_avg,
+        phase_meas_o   => phase_meas,
+        phase_meas_p_o => phase_meas_p);
+
+
+
+    regs_towb_dmtd.dmcr_en_i    <= r_dmcr_en;
+    regs_towb_dmtd.dmcr_n_avg_i <= r_dmcr_n_avg;
+
+    p_dmtd_update : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_sys_n_i = '0' then
+          validity_cntr              <= (others => '0');
+          regs_towb_ep.dmsr_ps_rdy_i <= '0';
+        else
+
+          if(regs_fromwb.dmcr_en_load_o = '1') then
+            r_dmcr_en    <= regs_fromwb.dmcr_en_o;
+            r_dmcr_n_avg <= regs_fromwb.dmcr_n_avg_o;
+          end if;
+
+          if(r_dmcr_en = '0') then
+            validity_cntr              <= (others => '0');
+            regs_towb_ep.dmsr_ps_rdy_i <= '0';
+          elsif(regs_fromwb.dmsr_ps_rdy_o = '1' and regs_fromwb.dmsr_ps_rdy_load_o = '1') then
+            regs_towb_ep.dmsr_ps_rdy_i <= '0';
+          elsif(phase_meas_p = '1') then
+
+            if(validity_cntr = "11") then
+              regs_towb_ep.dmsr_ps_rdy_i <= '1';
+              regs_towb_ep.dmsr_ps_val_i <= phase_meas(23 downto 0);  -- discard few
+            else
+              regs_towb_ep.dmsr_ps_rdy_i <= '0';
+              validity_cntr              <= validity_cntr + 1;
+            end if;
+          end if;
+        end if;
+      end if;
+    end process;
+
+  end generate gen_with_dmtd;
+
+  gen_without_dmtd : if(not g_with_dmtd) generate
+    regs_towb_ep.dmsr_ps_rdy_i <= '0';
+    regs_towb_ep.dmsr_ps_val_i <= (others => 'X');
+    regs_towb_dmtd             <= c_ep_in_registers_init_value;
+  end generate gen_without_dmtd;
+
+  dvalid_tx <= snk_cyc_i and snk_stb_i and link_ok;
+  dvalid_rx <= src_out.cyc and src_out.stb and link_ok;
+
+  gen_leds : if g_with_leds generate
+    U_Led_Ctrl : ep_leds_controller
+      generic map (
+        g_blink_period_log2 => 22)
+      port map (
+        clk_sys_i   => clk_sys_i,
+        rst_n_i     => rst_sys_n_i,
+        dvalid_tx_i => dvalid_tx,
+        dvalid_rx_i => dvalid_rx,
+        link_ok_i   => link_ok,
+        led_link_o  => led_link_o,
+        led_act_o   => led_act_o);
+  end generate gen_leds;
+
+  -------------------------- TRU stuff -----------------------------------
+  link_up_o <= link_ok;                 -- indicates that link is UP
+
+  pfilter_pclass_o <= pfilter_pclass;
+  pfilter_done_o   <= pfilter_done;
+  pfilter_drop_o   <= pfilter_drop;
+
+  txfra_pause_req     <= fc_tx_pause_req_i;
+  fc_tx_pause_ready_o <= txfra_pause_ready;
+  txfra_pause_delay   <= fc_tx_pause_delay_i;
+
+  -- TRU needs to be able to share the control of ouput path, i.e. turn off the laser
+  p_ep_ctrl : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_sys_n_i = '0' then
+        ep_ctrl <= '1';
+      else
+        ep_ctrl <= not link_kill_i;
+      end if;
+    end if;
+  end process;
+
+  GEN_STOP: if(g_with_stop_traffic) generate
+    rxpath_fab.sof    <= rxpcs_fab.sof    when(stop_traffic_i='0') else '0';
+    rxpath_fab.dvalid <= rxpcs_fab.dvalid when(stop_traffic_i='0') else '0';
+    rxpath_fab.eof   <= rxpcs_fab.eof;
+    rxpath_fab.error <= rxpcs_fab.error;
+    rxpath_fab.bytesel <= rxpcs_fab.bytesel;
+    rxpath_fab.has_rx_timestamp <= rxpcs_fab.has_rx_timestamp;
+    rxpath_fab.rx_timestamp_valid <= rxpcs_fab.rx_timestamp_valid;
+    rxpath_fab.data <= rxpcs_fab.data;
+    rxpath_fab.addr <= rxpcs_fab.addr;
+  end generate;
+
+  GEN_NO_STOP: if(not g_with_stop_traffic) generate
+    rxpath_fab <= rxpcs_fab;
+  end generate;
+
+  -------------------------- RMON events -----------------------------------
+  rmon.rx_pcs_err      <= rx_path_rmon.rx_pcs_err;  --from ep_rx_path
+  rmon.rx_giant        <= rx_path_rmon.rx_giant;
+  rmon.rx_runt         <= rx_path_rmon.rx_runt;
+  rmon.rx_crc_err      <= rx_path_rmon.rx_crc_err;
+  rmon.rx_pause        <= rx_path_rmon.rx_pause;
+  rmon.rx_pfilter_drop <= rx_path_rmon.rx_pfilter_drop;
+  rmon.rx_pclass       <= rx_path_rmon.rx_pclass;
+  rmon.rx_tclass       <= rx_path_rmon.rx_tclass;
+  rmon.rx_drop_at_rtu_full <= rx_path_rmon.rx_drop_at_rtu_full;
+  rmon.tx_underrun     <= pcs_rmon.tx_underrun;
+  rmon.rx_overrun      <= pcs_rmon.rx_overrun;
+  rmon.rx_invalid_code <= pcs_rmon.rx_invalid_code;
+  rmon.rx_sync_lost    <= pcs_rmon.rx_sync_lost;
+
+
+  rmon_event_tx : gc_sync_ffs
+    generic map(
+      g_sync_edge => "negative")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_sys_n_i,
+      data_i   => txpcs_timestamp_trigger_p_a,
+      synced_o => open,
+      npulse_o => open,
+      ppulse_o => rmon.tx_frame);
+
+  rmon_event_rx : gc_sync_ffs
+    generic map(
+      g_sync_edge => "negative")
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_sys_n_i,
+      data_i   => rxpcs_timestamp_trigger_p_a,
+      synced_o => open,
+      npulse_o => open,
+      ppulse_o => rmon.rx_frame);
+
+  f_pack_rmon_triggers(rmon, rmon_events_o(c_epevents_sz-1 downto 0));
+
+--   CS_ICON : chipscope_icon
+--    port map (
+--     CONTROL0 => CONTROL0);
+--   CS_ILA : chipscope_ila
+--    port map (
+--      CONTROL => CONTROL0,
+--      CLK     => phy_ref_clk_i,
+--      TRIG0   => TRIG0,
+--      TRIG1   => TRIG1,
+--      TRIG2   => TRIG2,
+--      TRIG3   => TRIG3);
+-- 
+--   TRIG0(15    downto   0) <= phy_rx_data_i;
+--   TRIG0(17    downto  16) <= phy_rx_k_i;
+--   TRIG0(              18) <= phy_rx_enc_err_i;
+--   TRIG0(23    downto  19) <= phy_rx_bitslide_i;
+
+  -- Drive unsued GMII outputs
+  gmii_txd_o   <= (others => '0');
+  gmii_tx_en_o <= '0';
+  gmii_tx_er_o <= '0';
+
+end syn;
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/xwr_endpoint.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/xwr_endpoint.vhd
new file mode 100644
index 000000000..b5d64008a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/xwr_endpoint.vhd
@@ -0,0 +1,533 @@
+-------------------------------------------------------------------------------
+-- Title      : 1000base-X MAC/Endpoint - top level
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : xwr_endpoint.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-04-26
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description: Struct-ized wrapper for WR Endpoint.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 - 2012 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+use work.endpoint_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.wishbone_pkg.all;
+
+entity xwr_endpoint is
+  
+  generic (
+    g_interface_mode        : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity   : t_wishbone_address_granularity := WORD;
+    g_simulation            : boolean                        := false;
+    g_tx_force_gap_length   : integer                        := 0;
+    g_tx_runt_padding       : boolean                        := false;
+    g_pcs_16bit             : boolean                        := false;
+    g_records_for_phy       : boolean                        := false;
+    g_rx_buffer_size        : integer                        := 1024;
+    g_with_rx_buffer        : boolean                        := true;
+    g_with_flow_control     : boolean                        := true;
+    g_with_timestamper      : boolean                        := true;
+    g_with_dpi_classifier   : boolean                        := true;
+    g_with_vlans            : boolean                        := true;
+    g_with_rtu              : boolean                        := true;
+    g_with_leds             : boolean                        := true;
+    g_with_dmtd             : boolean                        := true;
+    g_with_packet_injection : boolean                        := false;
+    g_use_new_rxcrc         : boolean                        := false;
+    g_use_new_txcrc         : boolean                        := false;
+    g_with_stop_traffic     : boolean                        := false
+    );
+  port (
+
+-------------------------------------------------------------------------------
+-- Clocks
+-------------------------------------------------------------------------------
+
+-- Endpoint transmit reference clock. Must be 125 MHz +- 100 ppm
+    clk_ref_i : in std_logic;
+
+-- reference clock / 2 (62.5 MHz, in-phase with refclk)
+    clk_sys_i : in std_logic;
+
+    clk_dmtd_i : in std_logic := '0';
+
+-- resets for various clock domains
+    rst_sys_n_i   : in std_logic;
+    rst_ref_n_i   : in std_logic;
+    rst_dmtd_n_i  : in std_logic;
+    rst_txclk_n_i : in std_logic;
+    rst_rxclk_n_i : in std_logic;
+
+-- PPS input (1 clk_ref_i cycle HI) for synchronizing timestamp counter
+    pps_csync_p1_i : in std_logic := '0';
+
+-- PPS valid input (clk_ref_i domain), when 1, the external PPS generator/servo
+-- is not adjusting the time scale, so we can safely timestamp.
+    pps_valid_i : in std_logic := '1';
+
+-------------------------------------------------------------------------------
+-- PHY Interace (8/16 bit PCS)
+-------------------------------------------------------------------------------    
+
+    -- 1st option is to use std_logic based I/Os
+    phy_rst_o            : out std_logic;
+    phy_loopen_o         : out std_logic;
+    phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+    phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+    phy_sfp_tx_fault_i   : in std_logic;
+    phy_sfp_los_i        : in std_logic;
+    phy_sfp_tx_disable_o : out std_logic;
+    phy_rdy_i            : in  std_logic;
+
+    phy_ref_clk_i      : in  std_logic := '0';
+    phy_tx_data_o      : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    phy_tx_k_o         : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+    phy_tx_disparity_i : in  std_logic := '0';
+    phy_tx_enc_err_i   : in  std_logic := '0';
+
+    phy_rx_data_i     : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+    phy_rx_clk_i      : in std_logic                     := '0';
+    phy_rx_k_i        : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+    phy_rx_enc_err_i  : in std_logic                     := '0';
+    phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+
+    -- 2nd option is to use record-based I/Os
+    phy8_o            : out t_phy_8bits_from_wrc;
+    phy8_i            : in  t_phy_8bits_to_wrc;
+    phy16_o           : out t_phy_16bits_from_wrc;
+    phy16_i           : in  t_phy_16bits_to_wrc;
+
+-------------------------------------------------------------------------------
+-- GMII Interface (8-bit)
+-------------------------------------------------------------------------------
+
+    gmii_tx_clk_i : in  std_logic := '0';
+    gmii_txd_o    : out std_logic_vector(7 downto 0);
+    gmii_tx_en_o  : out std_logic;
+    gmii_tx_er_o  : out std_logic;
+
+    gmii_rx_clk_i : in std_logic                    := '0';
+    gmii_rxd_i    : in std_logic_vector(7 downto 0) := x"00";
+    gmii_rx_er_i  : in std_logic                    := '0';
+    gmii_rx_dv_i  : in std_logic                    := '0';
+
+    ---------------------------------------------------------------------------
+    -- Wishbone I/O
+    ---------------------------------------------------------------------------
+
+    src_o : out t_wrf_source_out;
+    src_i : in  t_wrf_source_in;
+
+    snk_o : out t_wrf_sink_out;
+    snk_i : in  t_wrf_sink_in;
+
+-------------------------------------------------------------------------------
+-- TX timestamping unit interface
+-------------------------------------------------------------------------------  
+
+-- Port ID value
+    txtsu_port_id_o  : out std_logic_vector(4 downto 0);
+-- Frame ID value
+    txtsu_frame_id_o : out std_logic_vector(16 -1 downto 0);
+
+-- TX Timestamp and correctness info
+    txtsu_ts_value_o     : out std_logic_vector(28 + 4 - 1 downto 0);
+    txtsu_ts_incorrect_o : out std_logic;
+
+-- TX timestamp strobe: HI tells the TX timestamping unit that a timestamp is
+-- available on txtsu_ts_value_o, txtsu_fid_o andd txtsu_port_id_o. The correctness
+-- of the timestamping is indiacted on txtsu_ts_incorrect_o. Line remains HI
+-- until assertion of txtsu_ack_i.
+    txtsu_stb_o : out std_logic;
+
+-- TX timestamp acknowledge: HI indicates that TXTSU has successfully received
+-- the timestamp
+    txtsu_ack_i : in std_logic := '1';
+
+-------------------------------------------------------------------------------
+-- RTU interface
+-------------------------------------------------------------------------------
+
+-- 1 indicates that coresponding RTU port is full.
+    rtu_full_i : in std_logic := '0';
+
+-- 1 indicates that coresponding RTU port is almost full.
+    rtu_almost_full_i : in std_logic := '0';
+
+-- request strobe, single HI pulse begins evaluation of the request. 
+    rtu_rq_strobe_p1_o : out std_logic;
+    rtu_rq_abort_o         : out std_logic;
+
+-- source and destination MAC addresses extracted from the packet header
+    rtu_rq_smac_o : out std_logic_vector(48 - 1 downto 0);
+    rtu_rq_dmac_o : out std_logic_vector(48 - 1 downto 0);
+
+-- VLAN id (extracted from the header for TRUNK ports and assigned by the port
+-- for ACCESS ports)
+    rtu_rq_vid_o : out std_logic_vector(12 - 1 downto 0);
+
+-- HI means that packet has valid assigned a valid VID (low - packet is untagged)
+    rtu_rq_has_vid_o : out std_logic;
+
+-- packet priority (either extracted from the header or assigned per port).
+    rtu_rq_prio_o : out std_logic_vector(3 - 1 downto 0);
+
+-- HI indicates that packet has assigned priority.
+    rtu_rq_has_prio_o : out std_logic;
+
+-------------------------------------------------------------------------------   
+-- Wishbone bus
+-------------------------------------------------------------------------------
+
+    wb_i : in  t_wishbone_slave_in;
+    wb_o : out t_wishbone_slave_out;
+
+-------------------------------------------------------------------------------
+-- direct output of packet filter  (for TRU/HW-RSTP)
+-------------------------------------------------------------------------------
+   
+   pfilter_pclass_o       : out   std_logic_vector(7 downto 0);
+   pfilter_drop_o         : out   std_logic;
+   pfilter_done_o         : out   std_logic;
+
+-------------------------------------------------------------------------------
+-- control of PAUSE sending (ML: not used and not tested... TRU uses packet injection) -- 
+-------------------------------------------------------------------------------
+   
+   fc_tx_pause_req_i   : in std_logic := '0';
+   fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
+   fc_tx_pause_ready_o : out std_logic;
+
+-------------------------------------------------------------------------------
+-- information about received PAUSE (for SWcore)
+-------------------------------------------------------------------------------
+
+   fc_rx_pause_start_p_o     : out std_logic;
+   fc_rx_pause_quanta_o      : out std_logic_vector(15 downto 0);
+   fc_rx_pause_prio_mask_o   : out std_logic_vector(7 downto 0);
+   fc_rx_buffer_occupation_o : out std_logic_vector(7 downto 0);
+-------------------------------------------------------------------------------
+-- Packet Injection Interface (for TRU/HW-RSTP)
+-------------------------------------------------------------------------------
+
+-- injection request: triggers transmission of the packet to be injected,
+-- allowed when inject_ready = 1
+    inject_req_i : in std_logic := '0';
+
+-- injection ready flag: when true, user application can request asynchronous
+-- injection of a predefined packet
+    inject_ready_o : out std_logic;
+
+-- injection template selection (8 available)
+    inject_packet_sel_i : in std_logic_vector(2 downto 0) := "000";
+
+-- user-defined value to be embedded in the injected packet at a predefined
+-- location
+    inject_user_value_i : in std_logic_vector(15 downto 0) := x"0000";
+
+-------------------------------------------------------------------------------
+-- Misc stuff
+-------------------------------------------------------------------------------
+    rmon_events_o        : out std_logic_vector(c_epevents_sz-1 downto 0);
+
+    txts_o     : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+    rxts_o     : out std_logic; 		-- 2013-Nov-28 peterj added for debugging/calibration
+
+    led_link_o : out std_logic;
+    led_act_o  : out std_logic;
+
+    link_kill_i : in  std_logic := '0';
+    link_up_o   : out std_logic;
+    stop_traffic_i : in std_logic := '0';
+    dbg_tx_pcs_wr_count_o     : out std_logic_vector(5+4 downto 0);
+    dbg_tx_pcs_rd_count_o     : out std_logic_vector(5+4 downto 0);
+    nice_dbg_o  : out t_dbg_ep);
+
+end xwr_endpoint;
+
+architecture syn of xwr_endpoint is
+
+  signal phy_rst          : std_logic;
+  signal phy_loopen       : std_logic;
+  signal phy_loopen_vec   : std_logic_vector(2 downto 0);
+  signal phy_tx_data      : std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+  signal phy_tx_k         : std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+  signal phy_tx_prbs_sel  : std_logic_vector(2 downto 0);
+  signal sfp_tx_disable   : std_logic;
+  signal phy_tx_clk       : std_logic;
+
+  signal phy_tx_disparity : std_logic;
+  signal phy_tx_enc_err   : std_logic;
+  signal phy_rx_data      : std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+  signal phy_rx_clk       : std_logic;
+  signal phy_rx_k         : std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+  signal phy_rx_enc_err   : std_logic;
+  signal phy_rx_bts       : std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
+  signal phy_rdy          : std_logic;
+  signal sfp_tx_fault     : std_logic;
+  signal sfp_los          : std_logic;
+
+begin
+
+  U_Wrapped_Endpoint : wr_endpoint
+    generic map (
+      g_interface_mode      => g_interface_mode,
+      g_address_granularity => g_address_granularity,
+      g_tx_force_gap_length => g_tx_force_gap_length,
+      g_tx_runt_padding     => g_tx_runt_padding,
+      g_simulation            => g_simulation,
+      g_pcs_16bit             => g_pcs_16bit,
+      g_rx_buffer_size        => g_rx_buffer_size,
+      g_with_rx_buffer        => g_with_rx_buffer,
+      g_with_flow_control     => g_with_flow_control,
+      g_with_timestamper      => g_with_timestamper,
+      g_with_dpi_classifier   => g_with_dpi_classifier,
+      g_with_vlans            => g_with_vlans,
+      g_with_rtu              => g_with_rtu,
+      g_with_leds             => g_with_leds,
+      g_with_dmtd             => g_with_dmtd,
+      g_with_packet_injection => g_with_packet_injection,
+      g_use_new_rxcrc         => g_use_new_rxcrc,
+      g_use_new_txcrc         => g_use_new_txcrc,
+      g_with_stop_traffic     => g_with_stop_traffic)
+    port map (
+      clk_ref_i            => clk_ref_i,
+      clk_sys_i            => clk_sys_i,
+      clk_dmtd_i           => clk_dmtd_i,
+      rst_sys_n_i          => rst_sys_n_i,
+      rst_ref_n_i          => rst_ref_n_i,
+      rst_dmtd_n_i         => rst_dmtd_n_i,
+      rst_txclk_n_i        => rst_txclk_n_i,
+      rst_rxclk_n_i        => rst_rxclk_n_i,
+      pps_csync_p1_i       => pps_csync_p1_i,
+      pps_valid_i          => pps_valid_i,
+
+      phy_rst_o            => phy_rst,
+      phy_loopen_o         => phy_loopen,
+      phy_loopen_vec_o     => phy_loopen_vec,
+      phy_tx_prbs_sel_o    => phy_tx_prbs_sel,
+      phy_rdy_i            => phy_rdy,
+
+      phy_sfp_tx_fault_i   => sfp_tx_fault,
+      phy_sfp_los_i        => sfp_los,
+      phy_sfp_tx_disable_o => sfp_tx_disable,
+
+      phy_ref_clk_i        => phy_tx_clk,
+      phy_tx_data_o        => phy_tx_data,
+      phy_tx_k_o           => phy_tx_k,
+      phy_tx_disparity_i   => phy_tx_disparity,
+      phy_tx_enc_err_i     => phy_tx_enc_err,
+      phy_rx_data_i        => phy_rx_data,
+      phy_rx_clk_i         => phy_rx_clk,
+      phy_rx_k_i           => phy_rx_k,
+      phy_rx_enc_err_i     => phy_rx_enc_err,
+      phy_rx_bitslide_i    => phy_rx_bts,
+
+      gmii_tx_clk_i        => gmii_tx_clk_i,
+      gmii_txd_o           => gmii_txd_o,
+      gmii_tx_en_o         => gmii_tx_en_o,
+      gmii_tx_er_o         => gmii_tx_er_o,
+      gmii_rx_clk_i        => gmii_rx_clk_i,
+      gmii_rxd_i           => gmii_rxd_i,
+      gmii_rx_er_i         => gmii_rx_er_i,
+      gmii_rx_dv_i         => gmii_rx_dv_i,
+      src_dat_o            => src_o.dat,
+      src_adr_o            => src_o.adr,
+      src_sel_o            => src_o.sel,
+      src_cyc_o            => src_o.cyc,
+      src_stb_o            => src_o.stb,
+      src_we_o             => src_o.we,
+      src_stall_i          => src_i.stall,
+      src_ack_i            => src_i.ack,
+      src_err_i            => src_i.err,
+      snk_dat_i            => snk_i.dat,
+      snk_adr_i            => snk_i.adr,
+      snk_sel_i            => snk_i.sel,
+      snk_cyc_i            => snk_i.cyc,
+      snk_stb_i            => snk_i.stb,
+      snk_we_i             => snk_i.we,
+      snk_stall_o          => snk_o.stall,
+      snk_ack_o            => snk_o.ack,
+      snk_err_o            => snk_o.err,
+      snk_rty_o            => snk_o.rty,
+      txtsu_port_id_o      => txtsu_port_id_o,
+      txtsu_frame_id_o     => txtsu_frame_id_o,
+      txtsu_ts_value_o     => txtsu_ts_value_o,
+      txtsu_ts_incorrect_o => txtsu_ts_incorrect_o,
+      txtsu_stb_o          => txtsu_stb_o,
+      txtsu_ack_i          => txtsu_ack_i,
+      rtu_full_i           => rtu_full_i,
+      rtu_almost_full_i    => rtu_almost_full_i,
+      rtu_rq_strobe_p1_o   => rtu_rq_strobe_p1_o,
+      rtu_rq_abort_o       => rtu_rq_abort_o,
+      rtu_rq_smac_o        => rtu_rq_smac_o,
+      rtu_rq_dmac_o        => rtu_rq_dmac_o,
+      rtu_rq_vid_o         => rtu_rq_vid_o,
+      rtu_rq_has_vid_o     => rtu_rq_has_vid_o,
+      rtu_rq_prio_o        => rtu_rq_prio_o,
+      rtu_rq_has_prio_o    => rtu_rq_has_prio_o,
+      wb_cyc_i             => wb_i.cyc,
+      wb_stb_i             => wb_i.stb,
+      wb_we_i              => wb_i.we,
+      wb_sel_i             => wb_i.sel,
+      wb_adr_i             => wb_i.adr(7 downto 0),
+      wb_dat_i             => wb_i.dat,
+      wb_dat_o             => wb_o.dat,
+      wb_ack_o             => wb_o.ack,
+      wb_stall_o           => wb_o.stall,
+      rmon_events_o        => rmon_events_o,
+      txts_o               => txts_o, 		-- 2013-Nov-28 peterj added for debugging/calibration
+      rxts_o               => rxts_o, 		-- 2013-Nov-28 peterj added for debugging/calibration
+      led_link_o           => led_link_o,
+      led_act_o            => led_act_o,
+      link_up_o            => link_up_o,
+      link_kill_i          => link_kill_i,
+      pfilter_pclass_o     => pfilter_pclass_o,
+      pfilter_drop_o       => pfilter_drop_o,
+      pfilter_done_o       => pfilter_done_o,
+      fc_tx_pause_req_i    => fc_tx_pause_req_i,
+      fc_tx_pause_delay_i  => fc_tx_pause_delay_i,
+      fc_tx_pause_ready_o  => fc_tx_pause_ready_o,
+      fc_rx_pause_start_p_o   => fc_rx_pause_start_p_o,
+      fc_rx_pause_quanta_o    => fc_rx_pause_quanta_o,
+      fc_rx_pause_prio_mask_o => fc_rx_pause_prio_mask_o,
+      fc_rx_buffer_occupation_o =>fc_rx_buffer_occupation_o,
+      inject_req_i         => inject_req_i,
+      inject_user_value_i  => inject_user_value_i,
+      inject_packet_sel_i  => inject_packet_sel_i,
+      inject_ready_o       => inject_ready_o,
+      stop_traffic_i       => stop_traffic_i,
+      dbg_tx_pcs_wr_count_o=>dbg_tx_pcs_wr_count_o,
+      dbg_tx_pcs_rd_count_o=>dbg_tx_pcs_rd_count_o,
+      nice_dbg_o           => nice_dbg_o);
+
+  wb_o.err <= '0';
+  wb_o.rty <= '0';
+  wb_o.int <= '0';
+
+
+  -- Record-based PHY connections, depending on 8/16-bit PCS
+  GEN_16BIT_IF: if g_pcs_16bit and g_records_for_phy generate
+    phy16_o.rst            <= phy_rst;
+    phy16_o.loopen         <= phy_loopen;
+    phy16_o.loopen_vec     <= phy_loopen_vec;
+    phy16_o.tx_data        <= phy_tx_data;
+    phy16_o.tx_k           <= phy_tx_k;
+    phy16_o.tx_prbs_sel    <= phy_tx_prbs_sel;
+    phy16_o.sfp_tx_disable <= sfp_tx_disable;
+
+    phy_tx_clk       <= phy16_i.ref_clk;
+    phy_tx_disparity <= phy16_i.tx_disparity;
+    phy_tx_enc_err   <= phy16_i.tx_enc_err;
+    phy_rx_data      <= phy16_i.rx_data;
+    phy_rx_clk       <= phy16_i.rx_clk;
+    phy_rx_k         <= phy16_i.rx_k;
+    phy_rx_enc_err   <= phy16_i.rx_enc_err;
+    phy_rx_bts       <= phy16_i.rx_bitslide;
+    phy_rdy          <= phy16_i.rdy;
+    sfp_tx_fault     <= phy16_i.sfp_tx_fault;
+    sfp_los          <= phy16_i.sfp_los;
+
+    -- drive unused ports with dummy values
+    phy8_o               <= c_dummy_phy8_from_wrc;
+    phy_rst_o            <= '0';
+    phy_loopen_o         <= '0';
+    phy_tx_data_o        <= (others => '0');
+    phy_tx_k_o           <= (others => '0');
+    phy_loopen_vec_o     <= (others => '0');
+    phy_tx_prbs_sel_o    <= (others => '0');
+    phy_sfp_tx_disable_o <= '0';
+  end generate;
+
+  GEN_8BIT_IF: if not g_pcs_16bit and g_records_for_phy generate
+    phy8_o.rst            <= phy_rst;
+    phy8_o.loopen         <= phy_loopen;
+    phy8_o.loopen_vec     <= phy_loopen_vec;
+    phy8_o.tx_data        <= phy_tx_data;
+    phy8_o.tx_k           <= phy_tx_k;
+    phy8_o.tx_prbs_sel    <= phy_tx_prbs_sel;
+    phy8_o.sfp_tx_disable <= sfp_tx_disable;
+
+    phy_tx_clk       <= phy8_i.ref_clk;
+    phy_tx_disparity <= phy8_i.tx_disparity;
+    phy_tx_enc_err   <= phy8_i.tx_enc_err;
+    phy_rx_data      <= phy8_i.rx_data;
+    phy_rx_clk       <= phy8_i.rx_clk;
+    phy_rx_k         <= phy8_i.rx_k;
+    phy_rx_enc_err   <= phy8_i.rx_enc_err;
+    phy_rx_bts       <= phy8_i.rx_bitslide;
+    phy_rdy          <= phy8_i.rdy;
+    sfp_tx_fault     <= phy8_i.sfp_tx_fault;
+    sfp_los          <= phy8_i.sfp_los;
+
+    -- drive unused ports with dummy values
+    phy16_o              <= c_dummy_phy16_from_wrc;
+    phy_rst_o            <= '0';
+    phy_loopen_o         <= '0';
+    phy_tx_data_o        <= (others => '0');
+    phy_tx_k_o           <= (others => '0');
+    phy_loopen_vec_o     <= (others => '0');
+    phy_tx_prbs_sel_o    <= (others => '0');
+    phy_sfp_tx_disable_o <= '0';
+  end generate;
+
+  -- backwards compatibility
+  GEN_STD_IF: if not g_records_for_phy generate
+    phy_rst_o            <= phy_rst;
+    phy_loopen_o         <= phy_loopen;
+    phy_loopen_vec_o     <= phy_loopen_vec;
+    phy_tx_data_o        <= phy_tx_data;
+    phy_tx_k_o           <= phy_tx_k;
+    phy_tx_prbs_sel_o    <= phy_tx_prbs_sel;
+    phy_sfp_tx_disable_o <= sfp_tx_disable;
+
+    phy_tx_clk       <= phy_ref_clk_i;
+    phy_tx_disparity <= phy_tx_disparity_i;
+    phy_tx_enc_err   <= phy_tx_enc_err_i;
+    phy_rx_data      <= phy_rx_data_i;
+    phy_rx_clk       <= phy_rx_clk_i;
+    phy_rx_k         <= phy_rx_k_i;
+    phy_rx_enc_err   <= phy_rx_enc_err_i;
+    phy_rx_bts       <= phy_rx_bitslide_i;
+    phy_rdy          <= phy_rdy_i;
+    sfp_tx_fault     <= phy_sfp_tx_fault_i;
+    sfp_los          <= phy_sfp_los_i;
+
+    -- drive unused ports with dummy values
+    phy8_o  <= c_dummy_phy8_from_wrc;
+    phy16_o <= c_dummy_phy16_from_wrc;
+  end generate;
+  
+end syn;
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/minic_wb_slave.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/minic_wb_slave.vhd
new file mode 100644
index 000000000..1a2db96a2
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/minic_wb_slave.vhd
@@ -0,0 +1,602 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for Mini NIC for WhiteRabbit
+---------------------------------------------------------------------------------------
+-- File           : minic_wb_slave.vhd
+-- Author         : auto-generated by wbgen2 from mini_nic.wb
+-- Created        : Wed Aug 16 22:41:57 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wbgen2_pkg.all;
+
+use work.minic_wbgen2_pkg.all;
+
+
+entity minic_wb_slave is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(4 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    wb_int_o                                 : out    std_logic;
+    tx_ts_read_ack_o                         : out    std_logic;
+    irq_tx_i                                 : in     std_logic;
+    irq_tx_ack_o                             : out    std_logic;
+    irq_tx_mask_o                            : out    std_logic;
+    irq_rx_i                                 : in     std_logic;
+    irq_rx_ack_o                             : out    std_logic;
+    irq_txts_i                               : in     std_logic;
+    regs_i                                   : in     t_minic_in_registers;
+    regs_o                                   : out    t_minic_out_registers
+  );
+end minic_wb_slave;
+
+architecture syn of minic_wb_slave is
+
+signal minic_mcr_tx_start_dly0                  : std_logic      ;
+signal minic_mcr_tx_start_int                   : std_logic      ;
+signal minic_mcr_rx_en_int                      : std_logic      ;
+signal minic_mcr_rx_class_int                   : std_logic_vector(7 downto 0);
+signal minic_mprot_lo_int                       : std_logic_vector(15 downto 0);
+signal minic_mprot_hi_int                       : std_logic_vector(15 downto 0);
+signal eic_idr_int                              : std_logic_vector(2 downto 0);
+signal eic_idr_write_int                        : std_logic      ;
+signal eic_ier_int                              : std_logic_vector(2 downto 0);
+signal eic_ier_write_int                        : std_logic      ;
+signal eic_imr_int                              : std_logic_vector(2 downto 0);
+signal eic_isr_clear_int                        : std_logic_vector(2 downto 0);
+signal eic_isr_status_int                       : std_logic_vector(2 downto 0);
+signal eic_irq_ack_int                          : std_logic_vector(2 downto 0);
+signal eic_isr_write_int                        : std_logic      ;
+signal irq_inputs_vector_int                    : std_logic_vector(2 downto 0);
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal rwaddr_reg                               : std_logic_vector(4 downto 0);
+signal ack_in_progress                          : std_logic      ;
+
+begin
+-- Some internal signals assignments
+  wrdata_reg <= wb_dat_i;
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      minic_mcr_tx_start_int <= '0';
+      minic_mcr_rx_en_int <= '0';
+      minic_mcr_rx_class_int <= "00000000";
+      regs_o.tx_fifo_dat_wr_o <= '0';
+      regs_o.tx_fifo_type_wr_o <= '0';
+      tx_ts_read_ack_o <= '0';
+      minic_mprot_lo_int <= "0000000000000000";
+      minic_mprot_hi_int <= "0000000000000000";
+      eic_idr_write_int <= '0';
+      eic_ier_write_int <= '0';
+      eic_isr_write_int <= '0';
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          minic_mcr_tx_start_int <= '0';
+          regs_o.tx_fifo_dat_wr_o <= '0';
+          regs_o.tx_fifo_type_wr_o <= '0';
+          tx_ts_read_ack_o <= '0';
+          eic_idr_write_int <= '0';
+          eic_ier_write_int <= '0';
+          eic_isr_write_int <= '0';
+          ack_in_progress <= '0';
+        else
+          regs_o.tx_fifo_dat_wr_o <= '0';
+          regs_o.tx_fifo_type_wr_o <= '0';
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(4 downto 0) is
+          when "00000" => 
+            if (wb_we_i = '1') then
+              minic_mcr_tx_start_int <= wrdata_reg(0);
+              minic_mcr_rx_en_int <= wrdata_reg(10);
+              minic_mcr_rx_class_int <= wrdata_reg(23 downto 16);
+            end if;
+            rddata_reg(0) <= '0';
+            rddata_reg(1) <= regs_i.mcr_tx_idle_i;
+            rddata_reg(2) <= regs_i.mcr_tx_error_i;
+            rddata_reg(3) <= regs_i.mcr_tx_empty_i;
+            rddata_reg(4) <= regs_i.mcr_tx_full_i;
+            rddata_reg(8) <= regs_i.mcr_rx_ready_i;
+            rddata_reg(9) <= regs_i.mcr_rx_error_i;
+            rddata_reg(10) <= minic_mcr_rx_en_int;
+            rddata_reg(11) <= regs_i.mcr_tx_ts_ready_i;
+            rddata_reg(12) <= regs_i.mcr_rx_empty_i;
+            rddata_reg(13) <= regs_i.mcr_rx_full_i;
+            rddata_reg(23 downto 16) <= minic_mcr_rx_class_int;
+            rddata_reg(27 downto 24) <= regs_i.mcr_ver_i;
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(2) <= '1';
+            ack_in_progress <= '1';
+          when "00001" => 
+            if (wb_we_i = '1') then
+              regs_o.tx_fifo_dat_wr_o <= '1';
+              regs_o.tx_fifo_type_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00010" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(15 downto 0) <= regs_i.rx_fifo_dat_i;
+            rddata_reg(17 downto 16) <= regs_i.rx_fifo_type_i;
+            rddata_reg(30) <= regs_i.rx_fifo_empty_i;
+            rddata_reg(31) <= regs_i.rx_fifo_full_i;
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00100" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(0) <= regs_i.tsr0_valid_i;
+            rddata_reg(5 downto 1) <= regs_i.tsr0_pid_i;
+            rddata_reg(21 downto 6) <= regs_i.tsr0_fid_i;
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00110" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.tsr1_tsval_i;
+            tx_ts_read_ack_o <= '1';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00111" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(23 downto 0) <= regs_i.dbgr_irq_cnt_i;
+            rddata_reg(24) <= regs_i.dbgr_wb_irq_val_i;
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01000" => 
+            if (wb_we_i = '1') then
+              minic_mprot_lo_int <= wrdata_reg(15 downto 0);
+              minic_mprot_hi_int <= wrdata_reg(31 downto 16);
+            end if;
+            rddata_reg(15 downto 0) <= minic_mprot_lo_int;
+            rddata_reg(31 downto 16) <= minic_mprot_hi_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10000" => 
+            if (wb_we_i = '1') then
+              eic_idr_write_int <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10001" => 
+            if (wb_we_i = '1') then
+              eic_ier_write_int <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10010" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(2 downto 0) <= eic_imr_int(2 downto 0);
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10011" => 
+            if (wb_we_i = '1') then
+              eic_isr_write_int <= '1';
+            end if;
+            rddata_reg(2 downto 0) <= eic_isr_status_int(2 downto 0);
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- TX DMA start
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      minic_mcr_tx_start_dly0 <= '0';
+      regs_o.mcr_tx_start_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      minic_mcr_tx_start_dly0 <= minic_mcr_tx_start_int;
+      regs_o.mcr_tx_start_o <= minic_mcr_tx_start_int and (not minic_mcr_tx_start_dly0);
+    end if;
+  end process;
+  
+  
+-- TX DMA idle
+-- TX DMA error
+-- TX_FIFO_EMPTY
+-- TX_FIFO_FULL
+-- RX DMA ready
+-- RX DMA error
+-- RX DMA enable
+  regs_o.mcr_rx_en_o <= minic_mcr_rx_en_int;
+-- TX TS ready
+-- RX_FIFO_EMPTY
+-- RX_FIFO_FULL
+-- RX Accepted Packet Classes
+  regs_o.mcr_rx_class_o <= minic_mcr_rx_class_int;
+-- Regs map version
+-- Data to send
+-- pass-through field: Data to send in register: TX FIFO Register
+  regs_o.tx_fifo_dat_o <= wrdata_reg(15 downto 0);
+-- Data type
+-- pass-through field: Data type in register: TX FIFO Register
+  regs_o.tx_fifo_type_o <= wrdata_reg(17 downto 16);
+-- Data to send
+-- Data type
+-- RX_FIFO_EMPTY
+-- RX_FIFO_FULL
+-- Timestamp valid
+-- Port ID
+-- Frame ID
+-- Timestamp value
+-- interrupt counter
+-- status of wb_irq_o line
+-- address range lo
+  regs_o.mprot_lo_o <= minic_mprot_lo_int;
+-- address range hi
+  regs_o.mprot_hi_o <= minic_mprot_hi_int;
+-- extra code for reg/fifo/mem: Interrupt disable register
+  eic_idr_int(2 downto 0) <= wrdata_reg(2 downto 0);
+-- extra code for reg/fifo/mem: Interrupt enable register
+  eic_ier_int(2 downto 0) <= wrdata_reg(2 downto 0);
+-- extra code for reg/fifo/mem: Interrupt status register
+  eic_isr_clear_int(2 downto 0) <= wrdata_reg(2 downto 0);
+-- extra code for reg/fifo/mem: IRQ_CONTROLLER
+  eic_irq_controller_inst : wbgen2_eic
+    generic map (
+      g_num_interrupts     => 3,
+      g_irq00_mode         => 3,
+      g_irq01_mode         => 3,
+      g_irq02_mode         => 3,
+      g_irq03_mode         => 0,
+      g_irq04_mode         => 0,
+      g_irq05_mode         => 0,
+      g_irq06_mode         => 0,
+      g_irq07_mode         => 0,
+      g_irq08_mode         => 0,
+      g_irq09_mode         => 0,
+      g_irq0a_mode         => 0,
+      g_irq0b_mode         => 0,
+      g_irq0c_mode         => 0,
+      g_irq0d_mode         => 0,
+      g_irq0e_mode         => 0,
+      g_irq0f_mode         => 0,
+      g_irq10_mode         => 0,
+      g_irq11_mode         => 0,
+      g_irq12_mode         => 0,
+      g_irq13_mode         => 0,
+      g_irq14_mode         => 0,
+      g_irq15_mode         => 0,
+      g_irq16_mode         => 0,
+      g_irq17_mode         => 0,
+      g_irq18_mode         => 0,
+      g_irq19_mode         => 0,
+      g_irq1a_mode         => 0,
+      g_irq1b_mode         => 0,
+      g_irq1c_mode         => 0,
+      g_irq1d_mode         => 0,
+      g_irq1e_mode         => 0,
+      g_irq1f_mode         => 0
+    )
+    port map (
+      clk_i                => clk_sys_i,
+      rst_n_i              => rst_n_i,
+      irq_i                => irq_inputs_vector_int,
+      irq_ack_o            => eic_irq_ack_int,
+      reg_imr_o            => eic_imr_int,
+      reg_ier_i            => eic_ier_int,
+      reg_ier_wr_stb_i     => eic_ier_write_int,
+      reg_idr_i            => eic_idr_int,
+      reg_idr_wr_stb_i     => eic_idr_write_int,
+      reg_isr_o            => eic_isr_status_int,
+      reg_isr_i            => eic_isr_clear_int,
+      reg_isr_wr_stb_i     => eic_isr_write_int,
+      wb_irq_o             => wb_int_o
+    );
+  
+  irq_inputs_vector_int(0) <= irq_tx_i;
+  irq_tx_ack_o <= eic_irq_ack_int(0);
+  irq_tx_mask_o <= eic_imr_int(0);
+  irq_inputs_vector_int(1) <= irq_rx_i;
+  irq_rx_ack_o <= eic_irq_ack_int(1);
+  irq_inputs_vector_int(2) <= irq_txts_i;
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/minic_wbgen2_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
new file mode 100644
index 000000000..585a0513d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
@@ -0,0 +1,145 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for Mini NIC for WhiteRabbit
+---------------------------------------------------------------------------------------
+-- File           : minic_wbgen2_pkg.vhd
+-- Author         : auto-generated by wbgen2 from mini_nic.wb
+-- Created        : Wed Aug 16 22:41:57 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wbgen2_pkg.all;
+
+package minic_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_minic_in_registers is record
+    mcr_tx_idle_i                            : std_logic;
+    mcr_tx_error_i                           : std_logic;
+    mcr_tx_empty_i                           : std_logic;
+    mcr_tx_full_i                            : std_logic;
+    mcr_rx_ready_i                           : std_logic;
+    mcr_rx_error_i                           : std_logic;
+    mcr_tx_ts_ready_i                        : std_logic;
+    mcr_rx_empty_i                           : std_logic;
+    mcr_rx_full_i                            : std_logic;
+    mcr_ver_i                                : std_logic_vector(3 downto 0);
+    rx_fifo_dat_i                            : std_logic_vector(15 downto 0);
+    rx_fifo_type_i                           : std_logic_vector(1 downto 0);
+    rx_fifo_empty_i                          : std_logic;
+    rx_fifo_full_i                           : std_logic;
+    tsr0_valid_i                             : std_logic;
+    tsr0_pid_i                               : std_logic_vector(4 downto 0);
+    tsr0_fid_i                               : std_logic_vector(15 downto 0);
+    tsr1_tsval_i                             : std_logic_vector(31 downto 0);
+    dbgr_irq_cnt_i                           : std_logic_vector(23 downto 0);
+    dbgr_wb_irq_val_i                        : std_logic;
+    end record;
+  
+  constant c_minic_in_registers_init_value: t_minic_in_registers := (
+    mcr_tx_idle_i => '0',
+    mcr_tx_error_i => '0',
+    mcr_tx_empty_i => '0',
+    mcr_tx_full_i => '0',
+    mcr_rx_ready_i => '0',
+    mcr_rx_error_i => '0',
+    mcr_tx_ts_ready_i => '0',
+    mcr_rx_empty_i => '0',
+    mcr_rx_full_i => '0',
+    mcr_ver_i => (others => '0'),
+    rx_fifo_dat_i => (others => '0'),
+    rx_fifo_type_i => (others => '0'),
+    rx_fifo_empty_i => '0',
+    rx_fifo_full_i => '0',
+    tsr0_valid_i => '0',
+    tsr0_pid_i => (others => '0'),
+    tsr0_fid_i => (others => '0'),
+    tsr1_tsval_i => (others => '0'),
+    dbgr_irq_cnt_i => (others => '0'),
+    dbgr_wb_irq_val_i => '0'
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_minic_out_registers is record
+      mcr_tx_start_o                           : std_logic;
+      mcr_rx_en_o                              : std_logic;
+      mcr_rx_class_o                           : std_logic_vector(7 downto 0);
+      tx_fifo_dat_o                            : std_logic_vector(15 downto 0);
+      tx_fifo_dat_wr_o                         : std_logic;
+      tx_fifo_type_o                           : std_logic_vector(1 downto 0);
+      tx_fifo_type_wr_o                        : std_logic;
+      mprot_lo_o                               : std_logic_vector(15 downto 0);
+      mprot_hi_o                               : std_logic_vector(15 downto 0);
+      end record;
+    
+    constant c_minic_out_registers_init_value: t_minic_out_registers := (
+      mcr_tx_start_o => '0',
+      mcr_rx_en_o => '0',
+      mcr_rx_class_o => (others => '0'),
+      tx_fifo_dat_o => (others => '0'),
+      tx_fifo_dat_wr_o => '0',
+      tx_fifo_type_o => (others => '0'),
+      tx_fifo_type_wr_o => '0',
+      mprot_lo_o => (others => '0'),
+      mprot_hi_o => (others => '0')
+      );
+    function "or" (left, right: t_minic_in_registers) return t_minic_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body minic_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if x(i) = '1' then
+tmp(i):= '1';
+else
+tmp(i):= '0';
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_minic_in_registers) return t_minic_in_registers is
+variable tmp: t_minic_in_registers;
+begin
+tmp.mcr_tx_idle_i := f_x_to_zero(left.mcr_tx_idle_i) or f_x_to_zero(right.mcr_tx_idle_i);
+tmp.mcr_tx_error_i := f_x_to_zero(left.mcr_tx_error_i) or f_x_to_zero(right.mcr_tx_error_i);
+tmp.mcr_tx_empty_i := f_x_to_zero(left.mcr_tx_empty_i) or f_x_to_zero(right.mcr_tx_empty_i);
+tmp.mcr_tx_full_i := f_x_to_zero(left.mcr_tx_full_i) or f_x_to_zero(right.mcr_tx_full_i);
+tmp.mcr_rx_ready_i := f_x_to_zero(left.mcr_rx_ready_i) or f_x_to_zero(right.mcr_rx_ready_i);
+tmp.mcr_rx_error_i := f_x_to_zero(left.mcr_rx_error_i) or f_x_to_zero(right.mcr_rx_error_i);
+tmp.mcr_tx_ts_ready_i := f_x_to_zero(left.mcr_tx_ts_ready_i) or f_x_to_zero(right.mcr_tx_ts_ready_i);
+tmp.mcr_rx_empty_i := f_x_to_zero(left.mcr_rx_empty_i) or f_x_to_zero(right.mcr_rx_empty_i);
+tmp.mcr_rx_full_i := f_x_to_zero(left.mcr_rx_full_i) or f_x_to_zero(right.mcr_rx_full_i);
+tmp.mcr_ver_i := f_x_to_zero(left.mcr_ver_i) or f_x_to_zero(right.mcr_ver_i);
+tmp.rx_fifo_dat_i := f_x_to_zero(left.rx_fifo_dat_i) or f_x_to_zero(right.rx_fifo_dat_i);
+tmp.rx_fifo_type_i := f_x_to_zero(left.rx_fifo_type_i) or f_x_to_zero(right.rx_fifo_type_i);
+tmp.rx_fifo_empty_i := f_x_to_zero(left.rx_fifo_empty_i) or f_x_to_zero(right.rx_fifo_empty_i);
+tmp.rx_fifo_full_i := f_x_to_zero(left.rx_fifo_full_i) or f_x_to_zero(right.rx_fifo_full_i);
+tmp.tsr0_valid_i := f_x_to_zero(left.tsr0_valid_i) or f_x_to_zero(right.tsr0_valid_i);
+tmp.tsr0_pid_i := f_x_to_zero(left.tsr0_pid_i) or f_x_to_zero(right.tsr0_pid_i);
+tmp.tsr0_fid_i := f_x_to_zero(left.tsr0_fid_i) or f_x_to_zero(right.tsr0_fid_i);
+tmp.tsr1_tsval_i := f_x_to_zero(left.tsr1_tsval_i) or f_x_to_zero(right.tsr1_tsval_i);
+tmp.dbgr_irq_cnt_i := f_x_to_zero(left.dbgr_irq_cnt_i) or f_x_to_zero(right.dbgr_irq_cnt_i);
+tmp.dbgr_wb_irq_val_i := f_x_to_zero(left.dbgr_wb_irq_val_i) or f_x_to_zero(right.dbgr_wb_irq_val_i);
+return tmp;
+end function;
+end package body;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/wr_mini_nic.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/wr_mini_nic.vhd
new file mode 100644
index 000000000..3ca72931f
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/wr_mini_nic.vhd
@@ -0,0 +1,817 @@
+-------------------------------------------------------------------------------
+-- Title      : Mini Embedded DMA Network Interface Controller
+-- Project    : WhiteRabbit Core
+-------------------------------------------------------------------------------
+-- File       : wrsw_mini_nic.vhd
+-- Author     : Grzegorz Daniluk, Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-07-26
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generic
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description: Module implements a simple NIC with DMA controller. It
+-- sends/receives the packets using WR switch fabric interface (see the
+-- wrsw_endpoint.vhd for the details). Packets are stored and read from the
+-- system memory via simple memory bus. WR endpoint-compatible TX timestamping
+-- unit is also included.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010-2016 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2010-07-26  1.0      twlostow        Created
+-- 2010-08-16  1.0      twlostow        Bugfixes, linux compatibility added
+-- 2011-08-03  2.0      greg.d          rewritten to use pipelined Wishbone
+-- 2011-10-45  2.1      twlostow        bugfixes...
+-- 2016-10-27  3.0      greg.d          rewritten with Tx/Rx FIFOs
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wr_fabric_pkg.all;
+use work.wishbone_pkg.all;
+use work.genram_pkg.all;
+use work.minic_wbgen2_pkg.all;
+
+
+entity wr_mini_nic is
+
+  generic (
+    g_interface_mode       : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity  : t_wishbone_address_granularity := WORD;
+    g_tx_fifo_size         : integer                        := 1024;
+    g_rx_fifo_size         : integer                        := 2048;
+    g_buffer_little_endian : boolean                        := false);
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+-------------------------------------------------------------------------------
+-- Pipelined Wishbone interface
+-------------------------------------------------------------------------------
+
+    -- WBP Master (TX)
+    src_dat_o   : out std_logic_vector(15 downto 0);
+    src_adr_o   : out std_logic_vector(1 downto 0);
+    src_sel_o   : out std_logic_vector(1 downto 0);
+    src_cyc_o   : out std_logic;
+    src_stb_o   : out std_logic;
+    src_we_o    : out std_logic;
+    src_stall_i : in  std_logic;
+    src_err_i   : in  std_logic;
+    src_ack_i   : in  std_logic;
+
+    -- WBP Slave (RX)
+    snk_dat_i   : in  std_logic_vector(15 downto 0);
+    snk_adr_i   : in  std_logic_vector(1 downto 0);
+    snk_sel_i   : in  std_logic_vector(1 downto 0);
+    snk_cyc_i   : in  std_logic;
+    snk_stb_i   : in  std_logic;
+    snk_we_i    : in  std_logic;
+    snk_stall_o : out std_logic;
+    snk_err_o   : out std_logic;
+    snk_ack_o   : out std_logic;
+
+-------------------------------------------------------------------------------
+-- TXTSU i/f
+-------------------------------------------------------------------------------
+
+    txtsu_port_id_i     : in  std_logic_vector(4 downto 0);
+    txtsu_frame_id_i    : in  std_logic_vector(16 - 1 downto 0);
+    txtsu_tsval_i       : in  std_logic_vector(28 + 4 - 1 downto 0);
+    txtsu_tsincorrect_i : in  std_logic;
+    txtsu_stb_i         : in  std_logic;
+    txtsu_ack_o         : out std_logic;
+
+-------------------------------------------------------------------------------
+-- Wishbone slave
+-------------------------------------------------------------------------------    
+
+    wb_cyc_i   : in  std_logic;
+    wb_stb_i   : in  std_logic;
+    wb_we_i    : in  std_logic;
+    wb_sel_i   : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+    wb_adr_i   : in  std_logic_vector(c_wishbone_address_width-1 downto 0);
+    wb_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_ack_o   : out std_logic;
+    wb_stall_o : out std_logic;
+    wb_int_o   : out std_logic
+    );
+end wr_mini_nic;
+
+architecture behavioral of wr_mini_nic is
+
+  constant c_NTX_TIMEOUT : integer := 100;
+  constant c_WRF_BYTESEL : std_logic_vector(1 downto 0) := "11";
+
+  component minic_wb_slave
+    port (
+      rst_n_i          : in  std_logic;
+      clk_sys_i        : in  std_logic;
+      wb_adr_i         : in  std_logic_vector(4 downto 0);
+      wb_dat_i         : in  std_logic_vector(31 downto 0);
+      wb_dat_o         : out std_logic_vector(31 downto 0);
+      wb_cyc_i         : in  std_logic;
+      wb_sel_i         : in  std_logic_vector(3 downto 0);
+      wb_stb_i         : in  std_logic;
+      wb_we_i          : in  std_logic;
+      wb_ack_o         : out std_logic;
+      wb_stall_o       : out std_logic;
+      wb_int_o         : out std_logic;
+      tx_ts_read_ack_o : out std_logic;
+      irq_tx_i         : in  std_logic;
+      irq_tx_ack_o     : out std_logic;
+      irq_tx_mask_o    : out std_logic;
+      irq_rx_i         : in  std_logic;
+      irq_rx_ack_o     : out std_logic;
+      irq_txts_i       : in  std_logic;
+      regs_i           : in  t_minic_in_registers;
+      regs_o           : out t_minic_out_registers
+    );
+  end component;
+
+  function f_swap_endian_16
+    (
+      data : std_logic_vector(15 downto 0)
+      ) return std_logic_vector is
+  begin
+    if(g_buffer_little_endian = true) then
+      return data(7 downto 0) & data(15 downto 8);
+    else
+      return data;
+    end if;
+  end function f_swap_endian_16;
+
+
+  signal src_cyc_int   : std_logic;
+  signal src_stb_int   : std_logic;
+  signal snk_stall_int : std_logic;
+
+
+-----------------------------------------------------------------------------
+-- FIFO interface signals
+-----------------------------------------------------------------------------
+
+  signal tx_fifo_d : std_logic_vector(17 downto 0);
+  signal tx_fifo_q : std_logic_vector(17 downto 0);
+  alias  txf_type is tx_fifo_q(17 downto 16);
+  alias  txf_data is tx_fifo_q(15 downto 0);
+  signal tx_fifo_we, tx_fifo_rd : std_logic;
+  signal tx_fifo_empty, tx_fifo_full : std_logic;
+  signal rx_fifo_d : std_logic_vector(17 downto 0);
+  signal rx_fifo_q : std_logic_vector(17 downto 0);
+  signal rx_fifo_we, rx_fifo_rd : std_logic;
+  signal rx_fifo_empty, rx_fifo_full : std_logic;
+  signal rx_fifo_afull : std_logic;
+
+  signal txf_ferror : std_logic;
+  signal txf_fnew   : std_logic;
+  signal tx_status_word : t_wrf_status_reg;
+
+
+-------------------------------------------------------------------------------
+-- TX FSM stuff
+-------------------------------------------------------------------------------
+
+  type t_tx_fsm_state is (TX_IDLE, TX_STATUS, TX_PACKET, TX_FLUSH, TX_END_PACKET);
+
+  signal ntx_timeout_is_zero : std_logic;
+  signal ntx_timeout         : unsigned(7 downto 0);
+
+  signal ntx_ack_count     : unsigned(2 downto 0);
+
+  signal ntx_state         : t_tx_fsm_state;
+  signal ntx_rst_ts_ready  : std_logic;
+
+  signal ntx_stored_dat : std_logic_vector(15 downto 0);
+  signal ntx_stored_type : std_logic_vector(1 downto 0);
+  signal ntx_flush_last  : std_logic;
+
+-------------------------------------------------------------------------------
+-- RX FSM stuff
+-------------------------------------------------------------------------------  
+
+  signal snk_cyc_d0 : std_logic;
+  signal nrx_sof : std_logic;
+  signal nrx_eof : std_logic;
+  alias rxf_type is rx_fifo_d(17 downto 16);
+  alias rxf_data is rx_fifo_d(15 downto 0);
+
+  type t_rx_fsm_state is (RX_WAIT_FRAME, RX_FRAME, RX_FULL);
+  signal nrx_state    : t_rx_fsm_state;
+
+-------------------------------------------------------------------------------
+-- Classic Wishbone slave signals
+-------------------------------------------------------------------------------  
+
+  signal regs_in  : t_minic_in_registers;
+  signal regs_out : t_minic_out_registers;
+
+  signal wb_in  : t_wishbone_master_in;
+  signal wb_out : t_wishbone_master_out;
+
+  signal irq_tx     : std_logic;
+  signal irq_rx_ack : std_logic;
+  signal irq_rx     : std_logic;
+
+  signal nrx_newpacket, nrx_newpacket_d0 : std_logic;
+  signal ntx_newpacket, ntx_newpacket_d0 : std_logic;
+
+  signal irq_txts    : std_logic;
+  signal irq_tx_ack  : std_logic;
+  signal irq_tx_mask : std_logic;
+
+
+  --component chipscope_ila
+  --  port (
+  --    CONTROL : inout std_logic_vector(35 downto 0);
+  --    CLK     : in    std_logic;
+  --    TRIG0   : in    std_logic_vector(31 downto 0);
+  --    TRIG1   : in    std_logic_vector(31 downto 0);
+  --    TRIG2   : in    std_logic_vector(31 downto 0);
+  --    TRIG3   : in    std_logic_vector(31 downto 0));
+  --end component;
+
+  --signal CONTROL : std_logic_vector(35 downto 0);
+  --signal CLK     : std_logic;
+  --signal TRIG0   : std_logic_vector(31 downto 0);
+  --signal TRIG1   : std_logic_vector(31 downto 0);
+  --signal TRIG2   : std_logic_vector(31 downto 0);
+  --signal TRIG3   : std_logic_vector(31 downto 0);
+
+  --component chipscope_icon
+  --  port (
+  --    CONTROL0 : inout std_logic_vector (35 downto 0));
+  --end component;
+
+begin  -- behavioral
+
+  --chipscope_ila_1 : chipscope_ila
+  --  port map (
+  --    CONTROL => CONTROL,
+  --    CLK     => clk_sys_i,
+  --    TRIG0   => TRIG0,
+  --    TRIG1   => TRIG1,
+  --    TRIG2   => TRIG2,
+  --    TRIG3   => TRIG3);
+
+  --chipscope_icon_1 : chipscope_icon
+  --  port map (
+  --    CONTROL0 => CONTROL);
+
+  regs_in.mcr_ver_i         <= x"1";
+  regs_in.dbgr_irq_cnt_i    <= (others => '0');
+  regs_in.dbgr_wb_irq_val_i <= '0';
+
+-------------------------------------------------------------------------------
+-- Tx / Rx FIFO
+-----------------------------------------------------------------------------
+  TX_FIFO: generic_sync_fifo
+    generic map(
+      g_data_width => 18, 
+      g_size       => g_tx_fifo_size,
+      g_with_almost_empty => false,
+      g_with_almost_full  => false,
+      g_with_count        => false,
+      g_show_ahead        => true)
+    port map (
+      rst_n_i => rst_n_i,
+      clk_i   => clk_sys_i,
+      d_i     => tx_fifo_d,
+      we_i    => tx_fifo_we,
+      q_o     => tx_fifo_q,
+      rd_i    => tx_fifo_rd,
+      empty_o => tx_fifo_empty,
+      full_o  => tx_fifo_full);
+
+  RX_FIFO: generic_sync_fifo
+    generic map(
+      g_data_width => 18, 
+      g_size       => g_rx_fifo_size,
+      g_with_almost_empty => false,
+      g_with_almost_full  => true,
+      g_with_count        => false,
+      g_almost_full_threshold => g_rx_fifo_size/2,
+      g_show_ahead        => true)
+    port map (
+      rst_n_i => rst_n_i,
+      clk_i   => clk_sys_i,
+      d_i     => rx_fifo_d,
+      we_i    => rx_fifo_we,
+      q_o     => rx_fifo_q,
+      rd_i    => rx_fifo_rd,
+      empty_o => rx_fifo_empty,
+      full_o  => rx_fifo_full,
+      almost_full_o => rx_fifo_afull);
+
+  tx_fifo_d  <= regs_out.tx_fifo_type_o & regs_out.tx_fifo_dat_o;
+  tx_fifo_we <= regs_out.tx_fifo_dat_wr_o and regs_out.tx_fifo_type_wr_o;
+  regs_in.mcr_tx_empty_i <= tx_fifo_empty;
+  regs_in.mcr_tx_full_i  <= tx_fifo_full;
+
+  regs_in.mcr_rx_empty_i  <= rx_fifo_empty;
+  regs_in.rx_fifo_empty_i <= rx_fifo_empty;
+  regs_in.mcr_rx_full_i   <= rx_fifo_full;
+  regs_in.rx_fifo_full_i  <= rx_fifo_full;
+  regs_in.rx_fifo_type_i  <= rx_fifo_q(17 downto 16);
+  regs_in.rx_fifo_dat_i   <= rx_fifo_q(15 downto 0);
+
+  -- sniff wb access to generate rx_fifo_rd every time the RX_FIFO register is
+  -- read
+  rx_fifo_rd <= '1' when(wb_out.cyc='1' and wb_out.stb='1' and wb_out.adr(7 downto 0)=x"02" and wb_in.ack='1') else
+                '0';
+
+-------------------------------------------------------------------------------
+-- TX Path  (Host -> Fabric)
+-------------------------------------------------------------------------------  
+
+-- helper signals to avoid big IF conditions in the FSM
+  ntx_timeout_is_zero <= '1' when (ntx_timeout = to_unsigned(0, ntx_timeout'length)) else '0';
+
+  p_count_acks : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' or src_cyc_int = '0' or src_err_i = '1' then
+        ntx_ack_count <= (others => '0');
+      else
+        if(src_stb_int = '1' and src_stall_i = '0' and src_ack_i = '0') then
+          ntx_ack_count <= ntx_ack_count + 1;
+        elsif(src_ack_i = '1' and not(src_stb_int = '1' and src_stall_i = '0')) then
+          ntx_ack_count <= ntx_ack_count - 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  tx_status_word <= f_unmarshall_wrf_status(tx_fifo_q(15 downto 0));
+  -- signals error in transmitted frame (set by software
+  -- by writing again status register to TX Fifo
+  txf_ferror <= '1' when (tx_fifo_empty = '0' and txf_type = c_WRF_STATUS and tx_status_word.error = '1') else
+                '0';
+  txf_fnew   <= '1' when (tx_fifo_empty = '0' and txf_type = c_WRF_STATUS and tx_status_word.error = '0') else
+                '0';
+
+  p_tx_fsm: process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if (rst_n_i = '0') then
+        src_cyc_int <= '0';
+        src_stb_int <= '0';
+        src_sel_o   <= "11";
+        src_adr_o   <= c_WRF_DATA;
+        tx_fifo_rd  <= '0';
+        ntx_rst_ts_ready <= '0';
+        ntx_state   <= TX_IDLE;
+        ntx_stored_dat <= (others=>'0');
+        ntx_stored_type <= (others=>'0');
+        ntx_flush_last <= '0';
+        ntx_newpacket  <= '0';
+      else
+        case ntx_state is
+          when TX_IDLE =>
+            regs_in.mcr_tx_error_i <= '0';
+            src_cyc_int <= '0';
+            src_stb_int <= '0';
+            src_sel_o   <= "11";
+            src_adr_o   <= txf_type;
+            ntx_timeout <= to_unsigned(c_NTX_TIMEOUT, ntx_timeout'length);
+            ntx_flush_last <= '0';
+            ntx_newpacket  <= '0';
+            if (tx_fifo_empty = '0' and txf_fnew = '0') then
+              -- if there is something in the fifo but it's not a status word,
+              -- we read until we find a valid status. In this case we indicate
+              -- that Minic is busy by driving wbreg bit tx_idle to 0.
+              tx_fifo_rd <= '1';
+              ntx_rst_ts_ready <= '0';
+              regs_in.mcr_tx_idle_i  <= '0';
+            elsif (tx_fifo_empty = '0' and txf_fnew = '1' and regs_out.mcr_tx_start_o = '1') then
+              -- we have a new frame to be sent, proceed..
+              src_cyc_int <= '1';
+              tx_fifo_rd <= '1';
+              ntx_rst_ts_ready <= '1';
+              regs_in.mcr_tx_idle_i  <= '0';
+              ntx_state  <= TX_STATUS;
+            else
+              -- wait quietly for something to be written to FIFO
+              tx_fifo_rd <= '0';
+              ntx_rst_ts_ready <= '0';
+              regs_in.mcr_tx_idle_i  <= '1';
+            end if;
+
+          when TX_STATUS =>
+            -- read first word of the frame from fifo and start transmission
+            regs_in.mcr_tx_idle_i <= '0';
+            ntx_rst_ts_ready      <= '0';
+            src_cyc_int <= '1';
+            src_stb_int <= '1';
+            src_sel_o   <= "11";
+            src_adr_o   <= c_WRF_STATUS;
+            src_dat_o   <= f_swap_endian_16(txf_data);
+            tx_fifo_rd <= '1';
+            ntx_flush_last <= '0';
+            ntx_newpacket  <= '0';
+            ntx_state <= TX_PACKET;
+
+          when TX_PACKET =>
+            regs_in.mcr_tx_idle_i <= '0';
+            ntx_rst_ts_ready      <= '0';
+            src_cyc_int <= '1';
+            ntx_newpacket  <= '0';
+            if (tx_fifo_empty = '0' and src_stall_i = '0' and txf_ferror = '0' and txf_type = c_WRF_DATA) then
+              -- normal situation, we send the payload of a frame
+              src_adr_o   <= c_WRF_DATA;
+              src_dat_o   <= f_swap_endian_16(txf_data);
+              src_sel_o   <= "11";
+              src_stb_int <= '1';
+              tx_fifo_rd  <= '1';
+              ntx_flush_last <= '0';
+            elsif (tx_fifo_empty = '0' and src_stall_i = '0' and txf_ferror = '0' and txf_type = c_WRF_BYTESEL) then
+              -- almost normal situation, only one byte of data is valid
+              src_adr_o   <= c_WRF_DATA;
+              src_dat_o   <= f_swap_endian_16(txf_data);
+              src_sel_o   <= "10";
+              src_stb_int <= '1';
+              tx_fifo_rd  <= '1';
+              ntx_flush_last <= '0';
+            elsif (tx_fifo_empty = '0' and src_stall_i = '0' and txf_ferror = '0' and txf_type = c_WRF_OOB) then
+              -- we got OOB in TXed frame, let's send it
+              src_adr_o   <= c_WRF_OOB;
+              src_dat_o   <= f_swap_endian_16(txf_data);
+              src_sel_o   <= "11";
+              src_stb_int <= '1';
+              tx_fifo_rd  <= '1';
+              ntx_flush_last <= '0';
+            elsif ((tx_fifo_empty = '1' or txf_fnew = '1') and src_stall_i = '0') then
+              -- we done with this frame
+              src_adr_o   <= c_WRF_DATA;
+              src_dat_o   <= f_swap_endian_16(txf_data);
+              src_stb_int <= '0';
+              src_sel_o   <= "11";
+              tx_fifo_rd  <= '0';
+              ntx_flush_last <= '0';
+              ntx_state   <= TX_END_PACKET;
+            else
+              -- e.g. snk is stalling, we wait
+              tx_fifo_rd  <= '0';
+              src_stb_int <= '1';
+              ntx_stored_dat <= txf_data;
+              ntx_stored_type <= txf_type;
+              if (tx_fifo_empty = '1') then
+                ntx_flush_last <= '1';
+              else
+                ntx_flush_last <= '0';
+              end if;
+              ntx_state   <= TX_FLUSH;
+            end if;
+
+          when TX_FLUSH =>
+            regs_in.mcr_tx_idle_i <= '0';
+            ntx_rst_ts_ready      <= '0';
+            src_cyc_int <= '1';
+            ntx_newpacket  <= '0';
+            if (src_stall_i = '0' and (ntx_stored_type = c_WRF_DATA or ntx_stored_type = c_WRF_OOB)) then
+              src_adr_o   <= ntx_stored_type;
+              src_dat_o   <= f_swap_endian_16(ntx_stored_dat);
+              src_sel_o   <= "11";
+            elsif (src_stall_i = '0' and ntx_stored_type = c_WRF_BYTESEL) then
+              src_adr_o   <= c_WRF_DATA;
+              src_dat_o   <= f_swap_endian_16(ntx_stored_dat);
+              src_sel_o   <= "10";
+            else
+              src_stb_int <= '1';
+              tx_fifo_rd  <= '0';
+            end if;
+
+            if (ntx_flush_last = '0' and src_stall_i = '0') then
+              src_stb_int <= '1';
+              tx_fifo_rd  <= '1';
+              ntx_state   <= TX_PACKET;
+            elsif (ntx_flush_last = '1' and src_stall_i = '0') then
+              src_stb_int <= '0';
+              tx_fifo_rd  <= '0';
+              ntx_state   <= TX_END_PACKET;
+            else
+              src_stb_int <= '1';
+              tx_fifo_rd  <= '0';
+              ntx_state   <= TX_FLUSH;
+            end if;
+
+          when TX_END_PACKET =>
+            regs_in.mcr_tx_idle_i <= '0';
+            ntx_rst_ts_ready      <= '0';
+            src_stb_int <= '0';
+            -- timeout counter in case we never get all ACKs.
+            ntx_timeout <= ntx_timeout - 1;
+            if (ntx_ack_count = 0 or ntx_timeout_is_zero = '1') then
+              regs_in.mcr_tx_error_i <= ntx_timeout_is_zero;
+              src_cyc_int <= '0';
+              src_sel_o   <= "11";
+              tx_fifo_rd  <= '0';
+              ntx_newpacket <= '1';
+              ntx_state   <= TX_IDLE;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+-- these are never used:
+  src_we_o  <= '1';
+  src_stb_o <= src_stb_int;
+  src_cyc_o <= src_cyc_int;
+
+-------------------------------------------------------------------------------
+-- RX Path (Fabric ->  Host)
+-------------------------------------------------------------------------------  
+
+  p_rx_gen_ack : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        snk_ack_o <= '0';
+      else
+        if(snk_cyc_i = '1' and snk_stb_i = '1' and snk_stall_int = '0') then
+          snk_ack_o <= '1';
+        else
+          snk_ack_o <= '0';
+        end if;
+      end if;
+    end if;
+
+  end process;
+
+  nrx_sof <= '1' when(snk_cyc_d0 = '0' and snk_cyc_i = '1') else
+             '0';
+  nrx_eof <= '1' when(snk_cyc_d0 = '1' and snk_cyc_i = '0') else
+             '0';
+
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if (rst_n_i = '0') then
+        snk_cyc_d0 <= '0';
+        rx_fifo_we <= '0';
+        rxf_type   <= (others=>'0');
+        rxf_data   <= (others=>'0');
+        snk_stall_int <= '0';
+        regs_in.mcr_rx_ready_i <= '0';
+        nrx_newpacket <= '0';
+        nrx_state  <= RX_WAIT_FRAME;
+
+      else
+        snk_cyc_d0 <= snk_cyc_i;
+
+        case nrx_state is
+          when RX_WAIT_FRAME =>
+            rx_fifo_we <= '0';
+            rxf_type   <= (others=>'0');
+            rxf_data   <= (others=>'0');
+            regs_in.mcr_rx_error_i  <= '0';
+            nrx_newpacket <= '0';
+            if (regs_out.mcr_rx_en_o = '1') then
+              snk_stall_int <= not nrx_sof;
+            else
+              -- RX path is disabled, don't stall any traffic
+              snk_stall_int <= '0';
+            end if;
+
+            -- wait for software to enable RX path and a start of new frame
+            if (regs_out.mcr_rx_en_o = '1' and nrx_sof = '1' and rx_fifo_full = '0') then
+              nrx_state <= RX_FRAME;
+            end if;
+
+          when RX_FRAME =>
+            snk_stall_int <= '0';
+            -- receive frame, write it to FIFO
+            if (snk_stb_i = '1' and snk_sel_i = "11") then
+              rxf_type   <= snk_adr_i;
+              rxf_data   <= f_swap_endian_16(snk_dat_i);
+              rx_fifo_we <= '1';
+            elsif (snk_stb_i = '1' and snk_sel_i = "10") then
+              rxf_type   <= c_WRF_BYTESEL;
+              rxf_data   <= f_swap_endian_16(snk_dat_i);
+              rx_fifo_we <= '1';
+            else
+              rxf_type   <= (others=>'0');
+              rxf_data   <= (others=>'0');
+              rx_fifo_we <= '0';
+            end if;
+
+            if ((regs_out.mcr_rx_en_o = '0' or nrx_eof = '1') and rx_fifo_full = '0') then
+              -- stop writing FIFO if sw disables RX path
+              -- or if we're done with current frame
+              regs_in.mcr_rx_ready_i <= '1';
+              regs_in.mcr_rx_error_i  <= '0';
+              nrx_newpacket <= '1';
+              nrx_state              <= RX_WAIT_FRAME;
+            elsif ((regs_out.mcr_rx_en_o = '0' or nrx_eof = '1') and rx_fifo_full = '1') then
+              -- the difference with the previous condition is that if the fifo
+              -- is full on the last word, we don't set rx_error, because the
+              -- frame was not cut (it fits in the FIFO). Besides that, we have
+              -- to go to RX_FULL state to wait for the FIFO to be half-empty
+              -- and receive more frames.
+              regs_in.mcr_rx_ready_i <= '1';
+              regs_in.mcr_rx_error_i  <= '0';
+              nrx_newpacket <= '1';
+              nrx_state              <= RX_FULL;
+            elsif (rx_fifo_full = '1') then
+              -- error if fifo gets full needs to be recovered
+              regs_in.mcr_rx_ready_i <= '1';
+              regs_in.mcr_rx_error_i  <= '1';
+              nrx_newpacket <= '1';
+              nrx_state <= RX_FULL;
+            else
+              regs_in.mcr_rx_ready_i <= '0';
+              regs_in.mcr_rx_error_i  <= '0';
+              nrx_newpacket <= '0';
+
+            end if;
+
+          when RX_FULL =>
+            snk_stall_int <= '0';
+            rx_fifo_we <= '0';
+            rxf_type   <= (others=>'0');
+            rxf_data   <= (others=>'0');
+            nrx_newpacket <= '0';
+
+            -- recovering means disabling RX path and reading everything from
+            -- the FIFO
+            --if (regs_out.mcr_rx_en_o = '0' and rx_fifo_empty = '1') then
+            --  nrx_state <= RX_WAIT_FRAME;
+            --end if;
+            if (snk_cyc_i = '0' and rx_fifo_afull = '0') then
+              nrx_state <= RX_WAIT_FRAME;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+
+  snk_stall_o <= snk_stall_int;
+  snk_err_o   <= '0';
+
+-------------------------------------------------------------------------------
+-- TX Timestamping unit
+-------------------------------------------------------------------------------  
+  tsu_fsm : process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i = '0') then
+        regs_in.mcr_tx_ts_ready_i <= '0';
+        regs_in.tsr0_valid_i <= '0';
+        regs_in.tsr0_pid_i   <= (others => '0');
+        regs_in.tsr0_fid_i   <= (others => '0');
+        regs_in.tsr1_tsval_i <= (others => '0');
+        txtsu_ack_o          <= '0';
+      else
+        -- Make sure the timestamp is written to the FIFO only once.
+
+        if(ntx_rst_ts_ready = '1') then
+          regs_in.mcr_tx_ts_ready_i <= '0';
+        elsif(txtsu_stb_i = '1') then
+          regs_in.mcr_tx_ts_ready_i <= '1';
+          regs_in.tsr0_valid_i <= not txtsu_tsincorrect_i;
+          regs_in.tsr0_fid_i   <= txtsu_frame_id_i;
+          regs_in.tsr0_pid_i   <= txtsu_port_id_i;
+          regs_in.tsr1_tsval_i <= txtsu_tsval_i;
+          txtsu_ack_o          <= '1';
+        else
+          txtsu_ack_o <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  handle_irqs: process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        irq_tx           <= '0';
+        irq_rx           <= '0';
+        ntx_newpacket_d0 <= '0';
+        nrx_newpacket_d0 <= '0';
+      else
+        ntx_newpacket_d0 <= ntx_newpacket;
+        nrx_newpacket_d0 <= nrx_newpacket;
+
+        if (ntx_newpacket_d0 = '0' and ntx_newpacket = '1' and irq_tx_mask = '1') then
+          irq_tx <= '1';
+        elsif (irq_tx_mask = '0' or irq_tx_ack = '1') then
+          irq_tx <= '0';
+        end if;
+
+        if (nrx_newpacket_d0 = '0' and nrx_newpacket = '1') then
+          irq_rx <= '1';
+        elsif (irq_rx_ack = '1') then
+          irq_rx <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  irq_txts <= '0';
+
+  U_Slave_Adapter : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => false,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      sl_adr_i   => wb_adr_i,
+      sl_dat_i   => wb_dat_i,
+      sl_sel_i   => wb_sel_i,
+      sl_cyc_i   => wb_cyc_i,
+      sl_stb_i   => wb_stb_i,
+      sl_we_i    => wb_we_i,
+      sl_dat_o   => wb_dat_o,
+      sl_ack_o   => wb_ack_o,
+      sl_stall_o => wb_stall_o,
+      master_i   => wb_in,
+      master_o   => wb_out);
+
+  U_WB_Slave : minic_wb_slave
+    port map (
+      rst_n_i          => rst_n_i,
+      clk_sys_i        => clk_sys_i,
+      wb_adr_i         => wb_out.adr(4 downto 0),
+      wb_dat_i         => wb_out.dat,
+      wb_dat_o         => wb_in.dat,
+      wb_cyc_i         => wb_out.cyc,
+      wb_sel_i         => wb_out.sel,
+      wb_stb_i         => wb_out.stb,
+      wb_we_i          => wb_out.we,
+      wb_ack_o         => wb_in.ack,
+      wb_stall_o       => wb_in.stall,
+      wb_int_o         => wb_int_o,
+      regs_i           => regs_in,
+      regs_o           => regs_out,
+      tx_ts_read_ack_o => open,
+      irq_tx_i         => irq_tx,
+      irq_tx_ack_o     => irq_tx_ack,
+      irq_tx_mask_o    => irq_tx_mask,
+      irq_rx_i         => irq_rx,
+      irq_rx_ack_o     => irq_rx_ack,
+      irq_txts_i       => irq_txts);
+
+  wb_in.err <= '0';
+  wb_in.rty <= '0';
+  wb_in.int <= '0';
+
+  --TRIG0(0) <= regs_out.mcr_rx_en_o;
+  --TRIG0(1) <= rx_fifo_empty;
+  --TRIG0(2) <= rx_fifo_full;
+  --TRIG0(3) <= rx_fifo_rd;
+  --TRIG0(4) <= rx_fifo_we;
+  --TRIG0(6 downto 5)  <= rx_fifo_q(17 downto 16);
+  --TRIG0(22 downto 7) <= rx_fifo_q(15 downto 0);
+  --TRIG0(24 downto 23) <= "00" when(nrx_state = RX_WAIT_FRAME) else
+  --                       "01" when(nrx_state = RX_FRAME) else
+  --                       "10" when(nrx_state = RX_FULL) else
+  --                       "11";
+  --TRIG0(25) <= nrx_sof;
+  --TRIG0(26) <= nrx_eof;
+  --TRIG0(27) <= snk_cyc_i;
+  --TRIG0(28) <= snk_stb_i;
+  --TRIG0(29) <= snk_stall_int;
+  --TRIG0(31 downto 30) <= snk_adr_i;
+
+  --TRIG1(15 downto 0) <= snk_dat_i;
+  --TRIG1(16) <= rx_fifo_afull;
+  --TRIG1(17) <= wb_out.cyc;
+  --TRIG1(18) <= wb_out.stb;
+  --TRIG1(19) <= wb_in.ack;
+  --TRIG1(20) <= irq_rx;
+
+  --TRIG2(31 downto 0) <= wb_out.adr;
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/xwr_mini_nic.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/xwr_mini_nic.vhd
new file mode 100644
index 000000000..1cbbe9dfe
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/xwr_mini_nic.vhd
@@ -0,0 +1,186 @@
+-------------------------------------------------------------------------------
+-- Title      : Mini Embedded DMA Network Interface Controller
+-- Project    : WhiteRabbit Core
+-------------------------------------------------------------------------------
+-- File       : xwrsw_mini_nic.vhd
+-- Author     : Grzegorz Daniluk, Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-07-26
+-- Last update: 2017-02-03
+-- Platform   : FPGA-generic
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010-2016 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.wr_fabric_pkg.all;
+use work.wishbone_pkg.all;
+
+entity xwr_mini_nic is
+
+  generic (
+    g_interface_mode       : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity  : t_wishbone_address_granularity := WORD;
+    g_tx_fifo_size         : integer                        := 1024;
+    g_rx_fifo_size         : integer                        := 2048;
+    g_buffer_little_endian : boolean                        := false);
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+-------------------------------------------------------------------------------
+-- Pipelined Wishbone interface
+-------------------------------------------------------------------------------
+
+    -- WBP Master (TX)
+    src_o : out t_wrf_source_out;
+    src_i : in  t_wrf_source_in;
+
+    -- WBP Slave (RX)
+    snk_o : out t_wrf_sink_out;
+    snk_i : in  t_wrf_sink_in;
+
+-------------------------------------------------------------------------------
+-- TXTSU i/f
+-------------------------------------------------------------------------------
+
+    txtsu_port_id_i     : in  std_logic_vector(4 downto 0);
+    txtsu_frame_id_i    : in  std_logic_vector(16 - 1 downto 0);
+    txtsu_tsval_i       : in  std_logic_vector(28 + 4 - 1 downto 0);
+    txtsu_tsincorrect_i : in  std_logic;
+    txtsu_stb_i         : in  std_logic;
+    txtsu_ack_o         : out std_logic;
+
+-------------------------------------------------------------------------------
+-- Wishbone slave
+-------------------------------------------------------------------------------    
+
+  wb_i : in  t_wishbone_slave_in;
+  wb_o : out t_wishbone_slave_out
+    );
+end xwr_mini_nic;
+
+architecture wrapper of xwr_mini_nic is
+
+  component wr_mini_nic
+    generic (
+      g_interface_mode       : t_wishbone_interface_mode;
+      g_address_granularity  : t_wishbone_address_granularity;
+      g_tx_fifo_size         : integer;
+      g_rx_fifo_size         : integer;
+      g_buffer_little_endian : boolean);
+    port (
+      clk_sys_i           : in  std_logic;
+      rst_n_i             : in  std_logic;
+      src_dat_o           : out std_logic_vector(15 downto 0);
+      src_adr_o           : out std_logic_vector(1 downto 0);
+      src_sel_o           : out std_logic_vector(1 downto 0);
+      src_cyc_o           : out std_logic;
+      src_stb_o           : out std_logic;
+      src_we_o            : out std_logic;
+      src_stall_i         : in  std_logic;
+      src_err_i           : in  std_logic;
+      src_ack_i           : in  std_logic;
+      snk_dat_i           : in  std_logic_vector(15 downto 0);
+      snk_adr_i           : in  std_logic_vector(1 downto 0);
+      snk_sel_i           : in  std_logic_vector(1 downto 0);
+      snk_cyc_i           : in  std_logic;
+      snk_stb_i           : in  std_logic;
+      snk_we_i            : in  std_logic;
+      snk_stall_o         : out std_logic;
+      snk_err_o           : out std_logic;
+      snk_ack_o           : out std_logic;
+      txtsu_port_id_i     : in  std_logic_vector(4 downto 0);
+      txtsu_frame_id_i    : in  std_logic_vector(16 - 1 downto 0);
+      txtsu_tsval_i       : in  std_logic_vector(28 + 4 - 1 downto 0);
+      txtsu_tsincorrect_i : in  std_logic;
+      txtsu_stb_i         : in  std_logic;
+      txtsu_ack_o         : out std_logic;
+      wb_cyc_i            : in  std_logic;
+      wb_stb_i            : in  std_logic;
+      wb_we_i             : in  std_logic;
+      wb_sel_i            : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+      wb_adr_i            : in  std_logic_vector(c_wishbone_address_width-1 downto 0);
+      wb_dat_i            : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_dat_o            : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_ack_o            : out std_logic;
+      wb_stall_o          : out std_logic;
+      wb_int_o            : out std_logic);
+  end component;
+  
+begin  -- wrapper
+
+  U_Wrapped_Minic : wr_mini_nic
+    generic map (
+      g_interface_mode       => g_interface_mode,
+      g_address_granularity  => g_address_granularity,
+      g_tx_fifo_size         => g_tx_fifo_size,
+      g_rx_fifo_size         => g_rx_fifo_size,
+      g_buffer_little_endian => g_buffer_little_endian)
+    port map (
+      clk_sys_i           => clk_sys_i,
+      rst_n_i             => rst_n_i,
+      src_dat_o           => src_o.dat,
+      src_adr_o           => src_o.adr,
+      src_sel_o           => src_o.sel,
+      src_cyc_o           => src_o.cyc,
+      src_stb_o           => src_o.stb,
+      src_we_o            => src_o.we,
+      src_stall_i         => src_i.stall,
+      src_err_i           => src_i.err,
+      src_ack_i           => src_i.ack,
+      snk_dat_i           => snk_i.dat,
+      snk_adr_i           => snk_i.adr,
+      snk_sel_i           => snk_i.sel,
+      snk_cyc_i           => snk_i.cyc,
+      snk_stb_i           => snk_i.stb,
+      snk_we_i            => snk_i.we,
+      snk_stall_o         => snk_o.stall,
+      snk_err_o           => snk_o.err,
+      snk_ack_o           => snk_o.ack,
+      txtsu_port_id_i     => txtsu_port_id_i,
+      txtsu_frame_id_i    => txtsu_frame_id_i,
+      txtsu_tsval_i       => txtsu_tsval_i,
+      txtsu_tsincorrect_i => txtsu_tsincorrect_i,
+      txtsu_stb_i         => txtsu_stb_i,
+      txtsu_ack_o         => txtsu_ack_o,
+      wb_cyc_i            => wb_i.cyc,
+      wb_stb_i            => wb_i.stb,
+      wb_we_i             => wb_i.we,
+      wb_sel_i            => wb_i.sel,
+      wb_adr_i            => wb_i.adr,
+      wb_dat_i            => wb_i.dat,
+      wb_dat_o            => wb_o.dat,
+      wb_ack_o            => wb_o.ack,
+      wb_stall_o          => wb_o.stall,
+      wb_int_o            => wb_o.int);
+
+
+  wb_o.err <= '0';
+  wb_o.rty <= '0';
+  
+  snk_o.rty <= '0';
+
+end wrapper;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/pps_gen_wb.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/pps_gen_wb.vhd
new file mode 100644
index 000000000..d9866aeab
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/pps_gen_wb.vhd
@@ -0,0 +1,820 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Switch PPS generator and RTC
+---------------------------------------------------------------------------------------
+-- File           : pps_gen_wb.vhd
+-- Author         : auto-generated by wbgen2 from pps_gen_wb.wb
+-- Created        : Wed Aug 16 22:41:09 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity pps_gen_wb is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(2 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    refclk_i                                 : in     std_logic;
+-- Port for asynchronous (clock: refclk_i) MONOSTABLE field: 'Reset counter' in reg: 'Control Register'
+    ppsg_cr_cnt_rst_o                        : out    std_logic;
+-- Port for asynchronous (clock: refclk_i) BIT field: 'Enable counter' in reg: 'Control Register'
+    ppsg_cr_cnt_en_o                         : out    std_logic;
+-- Ports for asynchronous (clock: refclk_i) RW/RW BIT field: 'Adjust offset' in reg: 'Control Register'
+    ppsg_cr_cnt_adj_o                        : out    std_logic;
+    ppsg_cr_cnt_adj_i                        : in     std_logic;
+    ppsg_cr_cnt_adj_load_o                   : out    std_logic;
+-- Port for asynchronous (clock: refclk_i) MONOSTABLE field: 'Set time' in reg: 'Control Register'
+    ppsg_cr_cnt_set_o                        : out    std_logic;
+-- Port for asynchronous (clock: refclk_i) std_logic_vector field: 'PPS Pulse width' in reg: 'Control Register'
+    ppsg_cr_pwidth_o                         : out    std_logic_vector(27 downto 0);
+-- Port for asynchronous (clock: refclk_i) std_logic_vector field: 'Nanosecond counter' in reg: 'Nanosecond counter register'
+    ppsg_cntr_nsec_i                         : in     std_logic_vector(27 downto 0);
+-- Port for asynchronous (clock: refclk_i) std_logic_vector field: 'UTC Counter' in reg: 'UTC Counter register (least-significant part)'
+    ppsg_cntr_utclo_i                        : in     std_logic_vector(31 downto 0);
+-- Port for asynchronous (clock: refclk_i) std_logic_vector field: 'UTC Counter' in reg: 'UTC Counter register (most-significant part)'
+    ppsg_cntr_utchi_i                        : in     std_logic_vector(7 downto 0);
+-- Ports for PASS_THROUGH field: 'Nanosecond adjustment' in reg: 'Nanosecond adjustment register'
+    ppsg_adj_nsec_o                          : out    std_logic_vector(27 downto 0);
+    ppsg_adj_nsec_wr_o                       : out    std_logic;
+-- Ports for PASS_THROUGH field: 'UTC Counter adjustment' in reg: 'UTC Adjustment register (least-significant part)'
+    ppsg_adj_utclo_o                         : out    std_logic_vector(31 downto 0);
+    ppsg_adj_utclo_wr_o                      : out    std_logic;
+-- Ports for PASS_THROUGH field: 'UTC Counter adjustment' in reg: 'UTC Adjustment register (most-significant part)'
+    ppsg_adj_utchi_o                         : out    std_logic_vector(7 downto 0);
+    ppsg_adj_utchi_wr_o                      : out    std_logic;
+-- Ports for asynchronous (clock: refclk_i) RW/RW BIT field: 'Sync to external PPS input' in reg: 'External sync control register'
+    ppsg_escr_sync_o                         : out    std_logic;
+    ppsg_escr_sync_i                         : in     std_logic;
+    ppsg_escr_sync_load_o                    : out    std_logic;
+-- Port for asynchronous (clock: refclk_i) BIT field: 'PPS unmask output' in reg: 'External sync control register'
+    ppsg_escr_pps_unmask_o                   : out    std_logic;
+-- Port for asynchronous (clock: refclk_i) BIT field: 'PPS output valid' in reg: 'External sync control register'
+    ppsg_escr_pps_valid_o                    : out    std_logic;
+-- Port for asynchronous (clock: refclk_i) BIT field: 'Timecode output(UTC+cycles) valid' in reg: 'External sync control register'
+    ppsg_escr_tm_valid_o                     : out    std_logic;
+-- Port for asynchronous (clock: refclk_i) MONOSTABLE field: 'Set seconds counter' in reg: 'External sync control register'
+    ppsg_escr_sec_set_o                      : out    std_logic;
+-- Port for asynchronous (clock: refclk_i) MONOSTABLE field: 'Set nanoseconds counter' in reg: 'External sync control register'
+    ppsg_escr_nsec_set_o                     : out    std_logic
+  );
+end pps_gen_wb;
+
+architecture syn of pps_gen_wb is
+
+signal ppsg_cr_cnt_rst_int                      : std_logic      ;
+signal ppsg_cr_cnt_rst_int_delay                : std_logic      ;
+signal ppsg_cr_cnt_rst_sync0                    : std_logic      ;
+signal ppsg_cr_cnt_rst_sync1                    : std_logic      ;
+signal ppsg_cr_cnt_rst_sync2                    : std_logic      ;
+signal ppsg_cr_cnt_en_int                       : std_logic      ;
+signal ppsg_cr_cnt_en_sync0                     : std_logic      ;
+signal ppsg_cr_cnt_en_sync1                     : std_logic      ;
+signal ppsg_cr_cnt_adj_int_read                 : std_logic      ;
+signal ppsg_cr_cnt_adj_int_write                : std_logic      ;
+signal ppsg_cr_cnt_adj_lw                       : std_logic      ;
+signal ppsg_cr_cnt_adj_lw_delay                 : std_logic      ;
+signal ppsg_cr_cnt_adj_lw_read_in_progress      : std_logic      ;
+signal ppsg_cr_cnt_adj_lw_s0                    : std_logic      ;
+signal ppsg_cr_cnt_adj_lw_s1                    : std_logic      ;
+signal ppsg_cr_cnt_adj_lw_s2                    : std_logic      ;
+signal ppsg_cr_cnt_adj_rwsel                    : std_logic      ;
+signal ppsg_cr_cnt_set_int                      : std_logic      ;
+signal ppsg_cr_cnt_set_int_delay                : std_logic      ;
+signal ppsg_cr_cnt_set_sync0                    : std_logic      ;
+signal ppsg_cr_cnt_set_sync1                    : std_logic      ;
+signal ppsg_cr_cnt_set_sync2                    : std_logic      ;
+signal ppsg_cr_pwidth_int                       : std_logic_vector(27 downto 0);
+signal ppsg_cr_pwidth_swb                       : std_logic      ;
+signal ppsg_cr_pwidth_swb_delay                 : std_logic      ;
+signal ppsg_cr_pwidth_swb_s0                    : std_logic      ;
+signal ppsg_cr_pwidth_swb_s1                    : std_logic      ;
+signal ppsg_cr_pwidth_swb_s2                    : std_logic      ;
+signal ppsg_cntr_nsec_int                       : std_logic_vector(27 downto 0);
+signal ppsg_cntr_nsec_lwb                       : std_logic      ;
+signal ppsg_cntr_nsec_lwb_delay                 : std_logic      ;
+signal ppsg_cntr_nsec_lwb_in_progress           : std_logic      ;
+signal ppsg_cntr_nsec_lwb_s0                    : std_logic      ;
+signal ppsg_cntr_nsec_lwb_s1                    : std_logic      ;
+signal ppsg_cntr_nsec_lwb_s2                    : std_logic      ;
+signal ppsg_cntr_utclo_int                      : std_logic_vector(31 downto 0);
+signal ppsg_cntr_utclo_lwb                      : std_logic      ;
+signal ppsg_cntr_utclo_lwb_delay                : std_logic      ;
+signal ppsg_cntr_utclo_lwb_in_progress          : std_logic      ;
+signal ppsg_cntr_utclo_lwb_s0                   : std_logic      ;
+signal ppsg_cntr_utclo_lwb_s1                   : std_logic      ;
+signal ppsg_cntr_utclo_lwb_s2                   : std_logic      ;
+signal ppsg_cntr_utchi_int                      : std_logic_vector(7 downto 0);
+signal ppsg_cntr_utchi_lwb                      : std_logic      ;
+signal ppsg_cntr_utchi_lwb_delay                : std_logic      ;
+signal ppsg_cntr_utchi_lwb_in_progress          : std_logic      ;
+signal ppsg_cntr_utchi_lwb_s0                   : std_logic      ;
+signal ppsg_cntr_utchi_lwb_s1                   : std_logic      ;
+signal ppsg_cntr_utchi_lwb_s2                   : std_logic      ;
+signal ppsg_escr_sync_int_read                  : std_logic      ;
+signal ppsg_escr_sync_int_write                 : std_logic      ;
+signal ppsg_escr_sync_lw                        : std_logic      ;
+signal ppsg_escr_sync_lw_delay                  : std_logic      ;
+signal ppsg_escr_sync_lw_read_in_progress       : std_logic      ;
+signal ppsg_escr_sync_lw_s0                     : std_logic      ;
+signal ppsg_escr_sync_lw_s1                     : std_logic      ;
+signal ppsg_escr_sync_lw_s2                     : std_logic      ;
+signal ppsg_escr_sync_rwsel                     : std_logic      ;
+signal ppsg_escr_pps_unmask_int                 : std_logic      ;
+signal ppsg_escr_pps_unmask_sync0               : std_logic      ;
+signal ppsg_escr_pps_unmask_sync1               : std_logic      ;
+signal ppsg_escr_pps_valid_int                  : std_logic      ;
+signal ppsg_escr_pps_valid_sync0                : std_logic      ;
+signal ppsg_escr_pps_valid_sync1                : std_logic      ;
+signal ppsg_escr_tm_valid_int                   : std_logic      ;
+signal ppsg_escr_tm_valid_sync0                 : std_logic      ;
+signal ppsg_escr_tm_valid_sync1                 : std_logic      ;
+signal ppsg_escr_sec_set_int                    : std_logic      ;
+signal ppsg_escr_sec_set_int_delay              : std_logic      ;
+signal ppsg_escr_sec_set_sync0                  : std_logic      ;
+signal ppsg_escr_sec_set_sync1                  : std_logic      ;
+signal ppsg_escr_sec_set_sync2                  : std_logic      ;
+signal ppsg_escr_nsec_set_int                   : std_logic      ;
+signal ppsg_escr_nsec_set_int_delay             : std_logic      ;
+signal ppsg_escr_nsec_set_sync0                 : std_logic      ;
+signal ppsg_escr_nsec_set_sync1                 : std_logic      ;
+signal ppsg_escr_nsec_set_sync2                 : std_logic      ;
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal rwaddr_reg                               : std_logic_vector(2 downto 0);
+signal ack_in_progress                          : std_logic      ;
+
+begin
+-- Some internal signals assignments
+  wrdata_reg <= wb_dat_i;
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      ppsg_cr_cnt_rst_int <= '0';
+      ppsg_cr_cnt_rst_int_delay <= '0';
+      ppsg_cr_cnt_en_int <= '0';
+      ppsg_cr_cnt_adj_lw <= '0';
+      ppsg_cr_cnt_adj_lw_delay <= '0';
+      ppsg_cr_cnt_adj_lw_read_in_progress <= '0';
+      ppsg_cr_cnt_adj_rwsel <= '0';
+      ppsg_cr_cnt_adj_int_write <= '0';
+      ppsg_cr_cnt_set_int <= '0';
+      ppsg_cr_cnt_set_int_delay <= '0';
+      ppsg_cr_pwidth_int <= "0000000000000000000000000000";
+      ppsg_cr_pwidth_swb <= '0';
+      ppsg_cr_pwidth_swb_delay <= '0';
+      ppsg_cntr_nsec_lwb <= '0';
+      ppsg_cntr_nsec_lwb_delay <= '0';
+      ppsg_cntr_nsec_lwb_in_progress <= '0';
+      ppsg_cntr_utclo_lwb <= '0';
+      ppsg_cntr_utclo_lwb_delay <= '0';
+      ppsg_cntr_utclo_lwb_in_progress <= '0';
+      ppsg_cntr_utchi_lwb <= '0';
+      ppsg_cntr_utchi_lwb_delay <= '0';
+      ppsg_cntr_utchi_lwb_in_progress <= '0';
+      ppsg_adj_nsec_wr_o <= '0';
+      ppsg_adj_utclo_wr_o <= '0';
+      ppsg_adj_utchi_wr_o <= '0';
+      ppsg_escr_sync_lw <= '0';
+      ppsg_escr_sync_lw_delay <= '0';
+      ppsg_escr_sync_lw_read_in_progress <= '0';
+      ppsg_escr_sync_rwsel <= '0';
+      ppsg_escr_sync_int_write <= '0';
+      ppsg_escr_pps_unmask_int <= '0';
+      ppsg_escr_pps_valid_int <= '0';
+      ppsg_escr_tm_valid_int <= '0';
+      ppsg_escr_sec_set_int <= '0';
+      ppsg_escr_sec_set_int_delay <= '0';
+      ppsg_escr_nsec_set_int <= '0';
+      ppsg_escr_nsec_set_int_delay <= '0';
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          ppsg_adj_nsec_wr_o <= '0';
+          ppsg_adj_utclo_wr_o <= '0';
+          ppsg_adj_utchi_wr_o <= '0';
+          ack_in_progress <= '0';
+        else
+          ppsg_cr_cnt_rst_int <= ppsg_cr_cnt_rst_int_delay;
+          ppsg_cr_cnt_rst_int_delay <= '0';
+          ppsg_cr_cnt_adj_lw <= ppsg_cr_cnt_adj_lw_delay;
+          ppsg_cr_cnt_adj_lw_delay <= '0';
+          if ((ack_sreg(1) = '1') and (ppsg_cr_cnt_adj_lw_read_in_progress = '1')) then
+            rddata_reg(2) <= ppsg_cr_cnt_adj_int_read;
+            ppsg_cr_cnt_adj_lw_read_in_progress <= '0';
+          end if;
+          ppsg_cr_cnt_set_int <= ppsg_cr_cnt_set_int_delay;
+          ppsg_cr_cnt_set_int_delay <= '0';
+          ppsg_cr_pwidth_swb <= ppsg_cr_pwidth_swb_delay;
+          ppsg_cr_pwidth_swb_delay <= '0';
+          ppsg_cntr_nsec_lwb <= ppsg_cntr_nsec_lwb_delay;
+          ppsg_cntr_nsec_lwb_delay <= '0';
+          if ((ack_sreg(1) = '1') and (ppsg_cntr_nsec_lwb_in_progress = '1')) then
+            rddata_reg(27 downto 0) <= ppsg_cntr_nsec_int;
+            ppsg_cntr_nsec_lwb_in_progress <= '0';
+          end if;
+          ppsg_cntr_utclo_lwb <= ppsg_cntr_utclo_lwb_delay;
+          ppsg_cntr_utclo_lwb_delay <= '0';
+          if ((ack_sreg(1) = '1') and (ppsg_cntr_utclo_lwb_in_progress = '1')) then
+            rddata_reg(31 downto 0) <= ppsg_cntr_utclo_int;
+            ppsg_cntr_utclo_lwb_in_progress <= '0';
+          end if;
+          ppsg_cntr_utchi_lwb <= ppsg_cntr_utchi_lwb_delay;
+          ppsg_cntr_utchi_lwb_delay <= '0';
+          if ((ack_sreg(1) = '1') and (ppsg_cntr_utchi_lwb_in_progress = '1')) then
+            rddata_reg(7 downto 0) <= ppsg_cntr_utchi_int;
+            ppsg_cntr_utchi_lwb_in_progress <= '0';
+          end if;
+          ppsg_adj_nsec_wr_o <= '0';
+          ppsg_adj_utclo_wr_o <= '0';
+          ppsg_adj_utchi_wr_o <= '0';
+          ppsg_escr_sync_lw <= ppsg_escr_sync_lw_delay;
+          ppsg_escr_sync_lw_delay <= '0';
+          if ((ack_sreg(1) = '1') and (ppsg_escr_sync_lw_read_in_progress = '1')) then
+            rddata_reg(0) <= ppsg_escr_sync_int_read;
+            ppsg_escr_sync_lw_read_in_progress <= '0';
+          end if;
+          ppsg_escr_sec_set_int <= ppsg_escr_sec_set_int_delay;
+          ppsg_escr_sec_set_int_delay <= '0';
+          ppsg_escr_nsec_set_int <= ppsg_escr_nsec_set_int_delay;
+          ppsg_escr_nsec_set_int_delay <= '0';
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(2 downto 0) is
+          when "000" => 
+            if (wb_we_i = '1') then
+              ppsg_cr_cnt_rst_int <= wrdata_reg(0);
+              ppsg_cr_cnt_rst_int_delay <= wrdata_reg(0);
+              ppsg_cr_cnt_en_int <= wrdata_reg(1);
+              ppsg_cr_cnt_adj_int_write <= wrdata_reg(2);
+              ppsg_cr_cnt_adj_lw <= '1';
+              ppsg_cr_cnt_adj_lw_delay <= '1';
+              ppsg_cr_cnt_adj_lw_read_in_progress <= '0';
+              ppsg_cr_cnt_adj_rwsel <= '1';
+              ppsg_cr_cnt_set_int <= wrdata_reg(3);
+              ppsg_cr_cnt_set_int_delay <= wrdata_reg(3);
+              ppsg_cr_pwidth_int <= wrdata_reg(31 downto 4);
+              ppsg_cr_pwidth_swb <= '1';
+              ppsg_cr_pwidth_swb_delay <= '1';
+            end if;
+            rddata_reg(0) <= '0';
+            rddata_reg(1) <= ppsg_cr_cnt_en_int;
+            if (wb_we_i = '0') then
+              rddata_reg(2) <= 'X';
+              ppsg_cr_cnt_adj_lw <= '1';
+              ppsg_cr_cnt_adj_lw_delay <= '1';
+              ppsg_cr_cnt_adj_lw_read_in_progress <= '1';
+              ppsg_cr_cnt_adj_rwsel <= '0';
+            end if;
+            rddata_reg(3) <= '0';
+            rddata_reg(31 downto 4) <= ppsg_cr_pwidth_int;
+            ack_sreg(5) <= '1';
+            ack_in_progress <= '1';
+          when "001" => 
+            if (wb_we_i = '1') then
+            end if;
+            if (wb_we_i = '0') then
+              ppsg_cntr_nsec_lwb <= '1';
+              ppsg_cntr_nsec_lwb_delay <= '1';
+              ppsg_cntr_nsec_lwb_in_progress <= '1';
+            end if;
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(5) <= '1';
+            ack_in_progress <= '1';
+          when "010" => 
+            if (wb_we_i = '1') then
+            end if;
+            if (wb_we_i = '0') then
+              ppsg_cntr_utclo_lwb <= '1';
+              ppsg_cntr_utclo_lwb_delay <= '1';
+              ppsg_cntr_utclo_lwb_in_progress <= '1';
+            end if;
+            ack_sreg(5) <= '1';
+            ack_in_progress <= '1';
+          when "011" => 
+            if (wb_we_i = '1') then
+            end if;
+            if (wb_we_i = '0') then
+              ppsg_cntr_utchi_lwb <= '1';
+              ppsg_cntr_utchi_lwb_delay <= '1';
+              ppsg_cntr_utchi_lwb_in_progress <= '1';
+            end if;
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(5) <= '1';
+            ack_in_progress <= '1';
+          when "100" => 
+            if (wb_we_i = '1') then
+              ppsg_adj_nsec_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "101" => 
+            if (wb_we_i = '1') then
+              ppsg_adj_utclo_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "110" => 
+            if (wb_we_i = '1') then
+              ppsg_adj_utchi_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "111" => 
+            if (wb_we_i = '1') then
+              ppsg_escr_sync_int_write <= wrdata_reg(0);
+              ppsg_escr_sync_lw <= '1';
+              ppsg_escr_sync_lw_delay <= '1';
+              ppsg_escr_sync_lw_read_in_progress <= '0';
+              ppsg_escr_sync_rwsel <= '1';
+              ppsg_escr_pps_unmask_int <= wrdata_reg(1);
+              ppsg_escr_pps_valid_int <= wrdata_reg(2);
+              ppsg_escr_tm_valid_int <= wrdata_reg(3);
+              ppsg_escr_sec_set_int <= wrdata_reg(4);
+              ppsg_escr_sec_set_int_delay <= wrdata_reg(4);
+              ppsg_escr_nsec_set_int <= wrdata_reg(5);
+              ppsg_escr_nsec_set_int_delay <= wrdata_reg(5);
+            end if;
+            if (wb_we_i = '0') then
+              rddata_reg(0) <= 'X';
+              ppsg_escr_sync_lw <= '1';
+              ppsg_escr_sync_lw_delay <= '1';
+              ppsg_escr_sync_lw_read_in_progress <= '1';
+              ppsg_escr_sync_rwsel <= '0';
+            end if;
+            rddata_reg(1) <= ppsg_escr_pps_unmask_int;
+            rddata_reg(2) <= ppsg_escr_pps_valid_int;
+            rddata_reg(3) <= ppsg_escr_tm_valid_int;
+            rddata_reg(4) <= '0';
+            rddata_reg(5) <= '0';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(5) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- Reset counter
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_cr_cnt_rst_o <= '0';
+      ppsg_cr_cnt_rst_sync0 <= '0';
+      ppsg_cr_cnt_rst_sync1 <= '0';
+      ppsg_cr_cnt_rst_sync2 <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_cr_cnt_rst_sync0 <= ppsg_cr_cnt_rst_int;
+      ppsg_cr_cnt_rst_sync1 <= ppsg_cr_cnt_rst_sync0;
+      ppsg_cr_cnt_rst_sync2 <= ppsg_cr_cnt_rst_sync1;
+      ppsg_cr_cnt_rst_o <= ppsg_cr_cnt_rst_sync2 and (not ppsg_cr_cnt_rst_sync1);
+    end if;
+  end process;
+  
+  
+-- Enable counter
+-- synchronizer chain for field : Enable counter (type RW/RO, clk_sys_i <-> refclk_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_cr_cnt_en_o <= '0';
+      ppsg_cr_cnt_en_sync0 <= '0';
+      ppsg_cr_cnt_en_sync1 <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_cr_cnt_en_sync0 <= ppsg_cr_cnt_en_int;
+      ppsg_cr_cnt_en_sync1 <= ppsg_cr_cnt_en_sync0;
+      ppsg_cr_cnt_en_o <= ppsg_cr_cnt_en_sync1;
+    end if;
+  end process;
+  
+  
+-- Adjust offset
+-- asynchronous BIT register : Adjust offset (type RW/WO, refclk_i <-> clk_sys_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_cr_cnt_adj_lw_s0 <= '0';
+      ppsg_cr_cnt_adj_lw_s1 <= '0';
+      ppsg_cr_cnt_adj_lw_s2 <= '0';
+      ppsg_cr_cnt_adj_int_read <= '0';
+      ppsg_cr_cnt_adj_load_o <= '0';
+      ppsg_cr_cnt_adj_o <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_cr_cnt_adj_lw_s0 <= ppsg_cr_cnt_adj_lw;
+      ppsg_cr_cnt_adj_lw_s1 <= ppsg_cr_cnt_adj_lw_s0;
+      ppsg_cr_cnt_adj_lw_s2 <= ppsg_cr_cnt_adj_lw_s1;
+      if ((ppsg_cr_cnt_adj_lw_s2 = '0') and (ppsg_cr_cnt_adj_lw_s1 = '1')) then
+        if (ppsg_cr_cnt_adj_rwsel = '1') then
+          ppsg_cr_cnt_adj_o <= ppsg_cr_cnt_adj_int_write;
+          ppsg_cr_cnt_adj_load_o <= '1';
+        else
+          ppsg_cr_cnt_adj_load_o <= '0';
+          ppsg_cr_cnt_adj_int_read <= ppsg_cr_cnt_adj_i;
+        end if;
+      else
+        ppsg_cr_cnt_adj_load_o <= '0';
+      end if;
+    end if;
+  end process;
+  
+  
+-- Set time
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_cr_cnt_set_o <= '0';
+      ppsg_cr_cnt_set_sync0 <= '0';
+      ppsg_cr_cnt_set_sync1 <= '0';
+      ppsg_cr_cnt_set_sync2 <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_cr_cnt_set_sync0 <= ppsg_cr_cnt_set_int;
+      ppsg_cr_cnt_set_sync1 <= ppsg_cr_cnt_set_sync0;
+      ppsg_cr_cnt_set_sync2 <= ppsg_cr_cnt_set_sync1;
+      ppsg_cr_cnt_set_o <= ppsg_cr_cnt_set_sync2 and (not ppsg_cr_cnt_set_sync1);
+    end if;
+  end process;
+  
+  
+-- PPS Pulse width
+-- asynchronous std_logic_vector register : PPS Pulse width (type RW/RO, refclk_i <-> clk_sys_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_cr_pwidth_swb_s0 <= '0';
+      ppsg_cr_pwidth_swb_s1 <= '0';
+      ppsg_cr_pwidth_swb_s2 <= '0';
+      ppsg_cr_pwidth_o <= "0000000000000000000000000000";
+    elsif rising_edge(refclk_i) then
+      ppsg_cr_pwidth_swb_s0 <= ppsg_cr_pwidth_swb;
+      ppsg_cr_pwidth_swb_s1 <= ppsg_cr_pwidth_swb_s0;
+      ppsg_cr_pwidth_swb_s2 <= ppsg_cr_pwidth_swb_s1;
+      if ((ppsg_cr_pwidth_swb_s2 = '0') and (ppsg_cr_pwidth_swb_s1 = '1')) then
+        ppsg_cr_pwidth_o <= ppsg_cr_pwidth_int;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Nanosecond counter
+-- asynchronous std_logic_vector register : Nanosecond counter (type RO/WO, refclk_i <-> clk_sys_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_cntr_nsec_lwb_s0 <= '0';
+      ppsg_cntr_nsec_lwb_s1 <= '0';
+      ppsg_cntr_nsec_lwb_s2 <= '0';
+      ppsg_cntr_nsec_int <= "0000000000000000000000000000";
+    elsif rising_edge(refclk_i) then
+      ppsg_cntr_nsec_lwb_s0 <= ppsg_cntr_nsec_lwb;
+      ppsg_cntr_nsec_lwb_s1 <= ppsg_cntr_nsec_lwb_s0;
+      ppsg_cntr_nsec_lwb_s2 <= ppsg_cntr_nsec_lwb_s1;
+      if ((ppsg_cntr_nsec_lwb_s1 = '1') and (ppsg_cntr_nsec_lwb_s2 = '0')) then
+        ppsg_cntr_nsec_int <= ppsg_cntr_nsec_i;
+      end if;
+    end if;
+  end process;
+  
+  
+-- UTC Counter
+-- asynchronous std_logic_vector register : UTC Counter (type RO/WO, refclk_i <-> clk_sys_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_cntr_utclo_lwb_s0 <= '0';
+      ppsg_cntr_utclo_lwb_s1 <= '0';
+      ppsg_cntr_utclo_lwb_s2 <= '0';
+      ppsg_cntr_utclo_int <= "00000000000000000000000000000000";
+    elsif rising_edge(refclk_i) then
+      ppsg_cntr_utclo_lwb_s0 <= ppsg_cntr_utclo_lwb;
+      ppsg_cntr_utclo_lwb_s1 <= ppsg_cntr_utclo_lwb_s0;
+      ppsg_cntr_utclo_lwb_s2 <= ppsg_cntr_utclo_lwb_s1;
+      if ((ppsg_cntr_utclo_lwb_s1 = '1') and (ppsg_cntr_utclo_lwb_s2 = '0')) then
+        ppsg_cntr_utclo_int <= ppsg_cntr_utclo_i;
+      end if;
+    end if;
+  end process;
+  
+  
+-- UTC Counter
+-- asynchronous std_logic_vector register : UTC Counter (type RO/WO, refclk_i <-> clk_sys_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_cntr_utchi_lwb_s0 <= '0';
+      ppsg_cntr_utchi_lwb_s1 <= '0';
+      ppsg_cntr_utchi_lwb_s2 <= '0';
+      ppsg_cntr_utchi_int <= "00000000";
+    elsif rising_edge(refclk_i) then
+      ppsg_cntr_utchi_lwb_s0 <= ppsg_cntr_utchi_lwb;
+      ppsg_cntr_utchi_lwb_s1 <= ppsg_cntr_utchi_lwb_s0;
+      ppsg_cntr_utchi_lwb_s2 <= ppsg_cntr_utchi_lwb_s1;
+      if ((ppsg_cntr_utchi_lwb_s1 = '1') and (ppsg_cntr_utchi_lwb_s2 = '0')) then
+        ppsg_cntr_utchi_int <= ppsg_cntr_utchi_i;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Nanosecond adjustment
+-- pass-through field: Nanosecond adjustment in register: Nanosecond adjustment register
+  ppsg_adj_nsec_o <= wrdata_reg(27 downto 0);
+-- UTC Counter adjustment
+-- pass-through field: UTC Counter adjustment in register: UTC Adjustment register (least-significant part)
+  ppsg_adj_utclo_o <= wrdata_reg(31 downto 0);
+-- UTC Counter adjustment
+-- pass-through field: UTC Counter adjustment in register: UTC Adjustment register (most-significant part)
+  ppsg_adj_utchi_o <= wrdata_reg(7 downto 0);
+-- Sync to external PPS input
+-- asynchronous BIT register : Sync to external PPS input (type RW/WO, refclk_i <-> clk_sys_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_escr_sync_lw_s0 <= '0';
+      ppsg_escr_sync_lw_s1 <= '0';
+      ppsg_escr_sync_lw_s2 <= '0';
+      ppsg_escr_sync_int_read <= '0';
+      ppsg_escr_sync_load_o <= '0';
+      ppsg_escr_sync_o <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_escr_sync_lw_s0 <= ppsg_escr_sync_lw;
+      ppsg_escr_sync_lw_s1 <= ppsg_escr_sync_lw_s0;
+      ppsg_escr_sync_lw_s2 <= ppsg_escr_sync_lw_s1;
+      if ((ppsg_escr_sync_lw_s2 = '0') and (ppsg_escr_sync_lw_s1 = '1')) then
+        if (ppsg_escr_sync_rwsel = '1') then
+          ppsg_escr_sync_o <= ppsg_escr_sync_int_write;
+          ppsg_escr_sync_load_o <= '1';
+        else
+          ppsg_escr_sync_load_o <= '0';
+          ppsg_escr_sync_int_read <= ppsg_escr_sync_i;
+        end if;
+      else
+        ppsg_escr_sync_load_o <= '0';
+      end if;
+    end if;
+  end process;
+  
+  
+-- PPS unmask output
+-- synchronizer chain for field : PPS unmask output (type RW/RO, clk_sys_i <-> refclk_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_escr_pps_unmask_o <= '0';
+      ppsg_escr_pps_unmask_sync0 <= '0';
+      ppsg_escr_pps_unmask_sync1 <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_escr_pps_unmask_sync0 <= ppsg_escr_pps_unmask_int;
+      ppsg_escr_pps_unmask_sync1 <= ppsg_escr_pps_unmask_sync0;
+      ppsg_escr_pps_unmask_o <= ppsg_escr_pps_unmask_sync1;
+    end if;
+  end process;
+  
+  
+-- PPS output valid
+-- synchronizer chain for field : PPS output valid (type RW/RO, clk_sys_i <-> refclk_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_escr_pps_valid_o <= '0';
+      ppsg_escr_pps_valid_sync0 <= '0';
+      ppsg_escr_pps_valid_sync1 <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_escr_pps_valid_sync0 <= ppsg_escr_pps_valid_int;
+      ppsg_escr_pps_valid_sync1 <= ppsg_escr_pps_valid_sync0;
+      ppsg_escr_pps_valid_o <= ppsg_escr_pps_valid_sync1;
+    end if;
+  end process;
+  
+  
+-- Timecode output(UTC+cycles) valid
+-- synchronizer chain for field : Timecode output(UTC+cycles) valid (type RW/RO, clk_sys_i <-> refclk_i)
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_escr_tm_valid_o <= '0';
+      ppsg_escr_tm_valid_sync0 <= '0';
+      ppsg_escr_tm_valid_sync1 <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_escr_tm_valid_sync0 <= ppsg_escr_tm_valid_int;
+      ppsg_escr_tm_valid_sync1 <= ppsg_escr_tm_valid_sync0;
+      ppsg_escr_tm_valid_o <= ppsg_escr_tm_valid_sync1;
+    end if;
+  end process;
+  
+  
+-- Set seconds counter
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_escr_sec_set_o <= '0';
+      ppsg_escr_sec_set_sync0 <= '0';
+      ppsg_escr_sec_set_sync1 <= '0';
+      ppsg_escr_sec_set_sync2 <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_escr_sec_set_sync0 <= ppsg_escr_sec_set_int;
+      ppsg_escr_sec_set_sync1 <= ppsg_escr_sec_set_sync0;
+      ppsg_escr_sec_set_sync2 <= ppsg_escr_sec_set_sync1;
+      ppsg_escr_sec_set_o <= ppsg_escr_sec_set_sync2 and (not ppsg_escr_sec_set_sync1);
+    end if;
+  end process;
+  
+  
+-- Set nanoseconds counter
+  process (refclk_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ppsg_escr_nsec_set_o <= '0';
+      ppsg_escr_nsec_set_sync0 <= '0';
+      ppsg_escr_nsec_set_sync1 <= '0';
+      ppsg_escr_nsec_set_sync2 <= '0';
+    elsif rising_edge(refclk_i) then
+      ppsg_escr_nsec_set_sync0 <= ppsg_escr_nsec_set_int;
+      ppsg_escr_nsec_set_sync1 <= ppsg_escr_nsec_set_sync0;
+      ppsg_escr_nsec_set_sync2 <= ppsg_escr_nsec_set_sync1;
+      ppsg_escr_nsec_set_o <= ppsg_escr_nsec_set_sync2 and (not ppsg_escr_nsec_set_sync1);
+    end if;
+  end process;
+  
+  
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/wr_pps_gen.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/wr_pps_gen.vhd
new file mode 100644
index 000000000..f79dd0641
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/wr_pps_gen.vhd
@@ -0,0 +1,518 @@
+-------------------------------------------------------------------------------
+-- Title      : PPS Generator & UTC Realtime clock
+-- Project    : WhiteRabbit Switch
+-------------------------------------------------------------------------------
+-- File       : wr_pps_gen.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2010-09-02
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010-2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2010-09-02  1.0      twlostow        Created
+-- 2011-05-09  1.1      twlostow        Added external PPS input
+-- 2011-10-26  1.2      greg.d          Added wb slave adapter
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.wishbone_pkg.all;
+
+entity wr_pps_gen is
+  generic(
+    g_interface_mode       : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity  : t_wishbone_address_granularity := WORD;
+    g_ref_clock_rate       : integer                        := 125000000;
+    g_ext_clock_rate       : integer                        := 10000000;
+    g_with_ext_clock_input : boolean                        := false
+    );
+  port (
+    clk_ref_i   : in std_logic;
+    clk_sys_i   : in std_logic;
+    rst_ref_n_i : in std_logic;
+    rst_sys_n_i : in std_logic;
+
+    wb_adr_i   : in  std_logic_vector(4 downto 0);
+    wb_dat_i   : in  std_logic_vector(31 downto 0);
+    wb_dat_o   : out std_logic_vector(31 downto 0);
+    wb_cyc_i   : in  std_logic;
+    wb_sel_i   : in  std_logic_vector(3 downto 0);
+    wb_stb_i   : in  std_logic;
+    wb_we_i    : in  std_logic;
+    wb_ack_o   : out std_logic;
+    wb_stall_o : out std_logic;
+
+    -- Link status indicator (used for fast masking of PPS output when link
+    -- goes down
+    link_ok_i : in std_logic;
+
+    -- External PPS input. Warning! This signal is treated as synchronous to
+    -- the clk_ref_i (or the external 10 MHz reference) to prevent sync chain
+    -- delay uncertainities. Setup/hold times must be respected!
+    pps_in_i : in std_logic;
+
+    -- Single-pulse PPS output for synchronizing endpoints to
+    pps_csync_o : out std_logic;
+    pps_out_o   : out std_logic;
+    pps_led_o   : out std_logic;
+
+    pps_valid_o : out std_logic;
+
+    tm_utc_o        : out std_logic_vector(39 downto 0);
+    tm_cycles_o     : out std_logic_vector(27 downto 0);
+    tm_time_valid_o : out std_logic
+    );
+end wr_pps_gen;
+
+architecture behavioral of wr_pps_gen is
+
+  alias rst_n_i : std_logic is rst_sys_n_i;
+
+  constant c_PERIOD : integer := g_ref_clock_rate;
+
+  component pps_gen_wb is
+    port (
+      rst_n_i                : in  std_logic;
+      clk_sys_i              : in  std_logic;
+      wb_adr_i               : in  std_logic_vector(2 downto 0);
+      wb_dat_i               : in  std_logic_vector(31 downto 0);
+      wb_dat_o               : out std_logic_vector(31 downto 0);
+      wb_cyc_i               : in  std_logic;
+      wb_sel_i               : in  std_logic_vector(3 downto 0);
+      wb_stb_i               : in  std_logic;
+      wb_we_i                : in  std_logic;
+      wb_ack_o               : out std_logic;
+      wb_stall_o             : out std_logic;
+      refclk_i               : in  std_logic;
+      ppsg_cr_cnt_rst_o      : out std_logic;
+      ppsg_cr_cnt_en_o       : out std_logic;
+      ppsg_cr_cnt_adj_o      : out std_logic;
+      ppsg_cr_cnt_adj_i      : in  std_logic;
+      ppsg_cr_cnt_adj_load_o : out std_logic;
+      ppsg_cr_cnt_set_o      : out std_logic;
+      ppsg_cr_pwidth_o       : out std_logic_vector(27 downto 0);
+      ppsg_cntr_nsec_i       : in  std_logic_vector(27 downto 0);
+      ppsg_cntr_utclo_i      : in  std_logic_vector(31 downto 0);
+      ppsg_cntr_utchi_i      : in  std_logic_vector(7 downto 0);
+      ppsg_adj_nsec_o        : out std_logic_vector(27 downto 0);
+      ppsg_adj_nsec_wr_o     : out std_logic;
+      ppsg_adj_utclo_o       : out std_logic_vector(31 downto 0);
+      ppsg_adj_utclo_wr_o    : out std_logic;
+      ppsg_adj_utchi_o       : out std_logic_vector(7 downto 0);
+      ppsg_adj_utchi_wr_o    : out std_logic;
+      ppsg_escr_sync_o       : out std_logic;
+      ppsg_escr_sync_i       : in  std_logic;
+      ppsg_escr_sync_load_o  : out std_logic;
+      ppsg_escr_pps_valid_o  : out std_logic;
+      ppsg_escr_tm_valid_o   : out std_logic;
+      ppsg_escr_sec_set_o    : out std_logic;
+      ppsg_escr_nsec_set_o   : out std_logic;
+      ppsg_escr_pps_unmask_o : out std_logic);
+  end component pps_gen_wb;
+
+-- Wisbone slave signals
+  signal ppsg_cr_cnt_rst : std_logic;
+  signal ppsg_cr_cnt_en  : std_logic;
+
+  signal ppsg_cr_cnt_adj_o    : std_logic;
+  signal ppsg_cr_cnt_adj_i    : std_logic;
+  signal ppsg_cr_cnt_adj_load : std_logic;
+
+  signal ppsg_cr_cnt_set_p : std_logic;
+  signal ppsg_cr_pwidth    : std_logic_vector(27 downto 0);
+
+  signal ppsg_cntr_nsec  : std_logic_vector(27 downto 0);
+  signal ppsg_cntr_utclo : std_logic_vector(31 downto 0);
+  signal ppsg_cntr_utchi : std_logic_vector(7 downto 0);
+
+  signal ppsg_adj_nsec       : std_logic_vector(27 downto 0);
+  signal ppsg_adj_nsec_wr    : std_logic;
+  signal ppsg_adj_utclo      : std_logic_vector(31 downto 0);
+  signal ppsg_adj_utclo_wr   : std_logic;
+  signal ppsg_adj_utchi      : std_logic_vector(7 downto 0);
+  signal ppsg_adj_utchi_wr   : std_logic;
+  signal ppsg_escr_sync_load : std_logic;
+  signal ppsg_escr_sync_in   : std_logic;
+  signal ppsg_escr_sync_out  : std_logic;
+  signal ppsg_escr_sec_set   : std_logic;
+  signal ppsg_escr_nsec_set  : std_logic;
+
+  signal ppsg_escr_pps_valid  : std_logic;
+  signal ppsg_escr_tm_valid   : std_logic;
+  signal ppsg_escr_pps_unmask : std_logic;
+
+  signal cntr_nsec    : unsigned (27 downto 0);
+  signal cntr_utc     : unsigned (39 downto 0);
+  signal cntr_pps_ext : unsigned (24 downto 0);
+
+  signal ns_overflow     : std_logic;
+  signal ns_overflow_adv : std_logic;
+  signal cntr_adjust_p   : std_logic;
+
+  signal adj_nsec : unsigned(27 downto 0);
+  signal adj_utc  : unsigned(39 downto 0);
+
+  signal adjust_in_progress_nsec : std_logic;
+
+  signal adjust_in_progress_utc : std_logic;
+
+  signal width_cntr : unsigned(27 downto 0);
+
+  signal sync_in_progress : std_logic;
+  signal ext_sync_p       : std_logic;
+
+  signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
+  signal wb_out       : t_wishbone_slave_out;
+  signal wb_in        : t_wishbone_slave_in;
+
+  signal ns_overflow_2nd       : std_logic;
+  signal pps_in_d0, pps_ext_d0 : std_logic;
+
+  signal retime_counter : unsigned(4 downto 0);
+  signal pps_valid_int  : std_logic;
+
+  signal pps_out_int   : std_logic;
+  signal pps_in_refclk : std_logic;
+
+
+
+begin  -- behavioral
+
+
+  resized_addr(4 downto 0)                          <= wb_adr_i;
+  resized_addr(c_wishbone_address_width-1 downto 5) <= (others => '0');
+
+  U_Adapter : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => false,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      master_i   => wb_out,
+      master_o   => wb_in,
+      sl_adr_i   => resized_addr,
+      sl_dat_i   => wb_dat_i,
+      sl_sel_i   => wb_sel_i,
+      sl_cyc_i   => wb_cyc_i,
+      sl_stb_i   => wb_stb_i,
+      sl_we_i    => wb_we_i,
+      sl_dat_o   => wb_dat_o,
+      sl_ack_o   => wb_ack_o,
+      sl_stall_o => wb_stall_o);
+
+
+  U_Sync_pps_refclk : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_ref_i,
+      rst_n_i  => '1',
+      data_i   => pps_in_i,
+      ppulse_o => pps_in_refclk);
+
+
+  ppsg_cntr_nsec  <= std_logic_vector(cntr_nsec);
+  ppsg_cntr_utclo <= std_logic_vector(cntr_utc(31 downto 0));
+  ppsg_cntr_utchi <= std_logic_vector(cntr_utc(39 downto 32));
+
+
+  -- loads adjustment values into internal regsiters
+  p_wishbone_loads : process(clk_sys_i, rst_n_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        adj_nsec <= (others => '0');
+        adj_utc  <= (others => '0');
+      else
+        if(ppsg_adj_utchi_wr = '1') then
+          adj_utc(39 downto 32) <= unsigned(ppsg_adj_utchi);
+        end if;
+
+        if(ppsg_adj_utclo_wr = '1') then
+          adj_utc(31 downto 0) <= unsigned(ppsg_adj_utclo);
+        end if;
+
+        if(ppsg_adj_nsec_wr = '1') then
+          adj_nsec <= unsigned(ppsg_adj_nsec);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  gen_without_external_clock_input : if(not g_with_ext_clock_input) generate
+    ext_sync_p        <= '0';
+    sync_in_progress  <= '0';
+    ppsg_escr_sync_in <= '0';
+  end generate gen_without_external_clock_input;
+
+  gen_with_external_clock_input : if(g_with_ext_clock_input) generate
+
+    p_external_sync : process(clk_ref_i)
+    begin
+      if falling_edge(clk_ref_i) then
+        if(rst_ref_n_i = '0') then
+          sync_in_progress  <= '0';
+          ppsg_escr_sync_in <= '0';
+        else
+          if(ppsg_escr_sync_load = '1') then
+            sync_in_progress  <= ppsg_escr_sync_out;
+            ppsg_escr_sync_in <= '0';
+          else
+            if(sync_in_progress = '1' and pps_in_refclk = '1')
+            then
+              ext_sync_p        <= '1';
+              sync_in_progress  <= '0';
+              ppsg_escr_sync_in <= '1';
+            else
+              ext_sync_p <= '0';
+            end if;
+          end if;
+        end if;
+      end if;
+    end process;
+
+  end generate gen_with_external_clock_input;
+-- Nanosecond counter. Counts from 0 to c_PERIOD-1 every clk_ref_i cycle.
+
+  p_count_nsec : process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      if rst_ref_n_i = '0' or ppsg_cr_cnt_rst = '1' then
+        cntr_nsec               <= (others => '0');
+        ns_overflow             <= '0';
+        ns_overflow_adv         <= '0';
+        adjust_in_progress_nsec <= '0';
+
+        -- counter is enabled?
+      elsif(ppsg_cr_cnt_en = '1') then
+
+        -- got ADJUST OFFSET command
+        if(cntr_adjust_p = '1') then
+
+-- start waiting for next counter overflow
+          adjust_in_progress_nsec <= '1';
+        end if;
+
+-- got SET TIME command - load the counter with new value
+        if(ppsg_cr_cnt_set_p = '1' or ext_sync_p = '1' or ppsg_escr_nsec_set = '1') then
+          cntr_nsec        <= adj_nsec;
+          ns_overflow      <= '0';
+          ns_overflow_adv  <= '0';
+
+-- got counter overflow:
+        elsif(cntr_nsec = to_unsigned(c_PERIOD-3, cntr_nsec'length)) then
+          ns_overflow     <= '0';
+          ns_overflow_adv <= '1';
+          cntr_nsec       <= cntr_nsec + 1;
+        elsif(cntr_nsec = to_unsigned(c_PERIOD-2, cntr_nsec'length)) then
+          ns_overflow     <= '1';
+          ns_overflow_adv <= '0';
+          cntr_nsec       <= cntr_nsec + 1;
+        elsif(cntr_nsec = to_unsigned(c_PERIOD-1, cntr_nsec'length)) then
+          ns_overflow     <= '0';
+          ns_overflow_adv <= '0';
+          -- we're in the middle of offset adjustment - load the counter with
+          -- offset value instead of resetting it. This equals to subtracting the offset
+          -- but takes less logic.
+          if(adjust_in_progress_nsec = '1') then
+            cntr_nsec               <= adj_nsec;
+            adjust_in_progress_nsec <= '0';
+          else
+            -- normal counter reset. Generate overflow pulse.
+            cntr_nsec <= (others => '0');
+          end if;
+        else
+          ns_overflow     <= '0';
+          ns_overflow_adv <= '0';
+          cntr_nsec       <= cntr_nsec + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+  p_drive_pps_valid : process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      if rst_ref_n_i = '0' or ppsg_cr_cnt_rst = '1' then
+        pps_valid_int   <= '0';
+        ns_overflow_2nd <= '0';
+      else
+        if(sync_in_progress = '1' or adjust_in_progress_nsec = '1' or adjust_in_progress_utc = '1') then
+          pps_valid_int   <= '0';
+          ns_overflow_2nd <= '0';
+        elsif(adjust_in_progress_utc = '0' and adjust_in_progress_nsec = '0' and sync_in_progress = '0') then
+
+          if(ns_overflow = '1') then
+            ns_overflow_2nd <= '1';
+            if(ns_overflow_2nd = '1') then
+              pps_valid_int <= '1';
+            end if;
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_count_utc : process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      if rst_ref_n_i = '0' or ppsg_cr_cnt_rst = '1' then
+        cntr_utc               <= (others => '0');
+        adjust_in_progress_utc <= '0';
+      elsif(ppsg_cr_cnt_en = '1') then
+
+        if(ppsg_cr_cnt_set_p = '1' or ppsg_escr_sec_set = '1') then
+          cntr_utc        <= adj_utc;
+        elsif(cntr_adjust_p = '1') then
+          adjust_in_progress_utc <= '1';
+
+          if(ns_overflow = '1') then
+            cntr_utc <= cntr_utc +1;
+          end if;
+
+        elsif(adjust_in_progress_utc = '1' and ns_overflow = '1') then
+          cntr_utc               <= cntr_utc + adj_utc + 1;
+          adjust_in_progress_utc <= '0';
+        elsif(ns_overflow = '1') then
+          cntr_utc <= cntr_utc + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+-- generate single-cycle PPS pulses for synchronizing endpoint TS counters
+  pps_csync_o <= ns_overflow;
+
+  -- generates variable-width PPS pulses for PPS external output
+  p_gen_pps_out : process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      if rst_ref_n_i = '0' then
+        pps_out_int <= '0';
+        pps_led_o   <= '0';
+        width_cntr  <= (others => '0');
+      else
+
+        if(ns_overflow_adv = '1') then
+          pps_out_int <= ppsg_escr_pps_valid and
+                         (link_ok_i or ppsg_escr_pps_unmask);
+          width_cntr  <= unsigned(ppsg_cr_pwidth);
+        elsif(ns_overflow = '1') then
+          pps_led_o <= ppsg_escr_pps_valid;
+        else
+          if(width_cntr = to_unsigned(0, width_cntr'length)) then
+            pps_out_int <= '0';
+            pps_led_o   <= '0';
+          else
+            width_cntr <= width_cntr -1;
+          end if;
+        end if;
+      end if;
+    end if;
+
+  end process;
+
+  process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      if rst_ref_n_i = '0' then
+        pps_out_o <= '0';
+      else
+        pps_out_o <= pps_out_int;
+      end if;
+    end if;
+  end process;
+
+  Uwb_slave : pps_gen_wb
+    port map (
+      rst_n_i                => rst_n_i,
+      clk_sys_i              => clk_sys_i,
+      wb_adr_i               => wb_in.adr(2 downto 0),
+      wb_dat_i               => wb_in.dat,
+      wb_dat_o               => wb_out.dat,
+      wb_cyc_i               => wb_in.cyc,
+      wb_sel_i               => wb_in.sel,
+      wb_stb_i               => wb_in.stb,
+      wb_we_i                => wb_in.we,
+      wb_ack_o               => wb_out.ack,
+      refclk_i               => clk_ref_i,
+      ppsg_cr_cnt_rst_o      => ppsg_cr_cnt_rst,
+      ppsg_cr_cnt_en_o       => ppsg_cr_cnt_en,
+      ppsg_cr_cnt_adj_o      => ppsg_cr_cnt_adj_o,
+      ppsg_cr_cnt_adj_i      => ppsg_cr_cnt_adj_i,
+      ppsg_cr_cnt_adj_load_o => ppsg_cr_cnt_adj_load,
+      ppsg_escr_sync_o       => ppsg_escr_sync_out,
+      ppsg_escr_sync_i       => ppsg_escr_sync_in,
+      ppsg_escr_sync_load_o  => ppsg_escr_sync_load,
+      ppsg_cr_cnt_set_o      => ppsg_cr_cnt_set_p,
+      ppsg_cr_pwidth_o       => ppsg_cr_pwidth,
+      ppsg_cntr_nsec_i       => ppsg_cntr_nsec,
+      ppsg_cntr_utclo_i      => ppsg_cntr_utclo,
+      ppsg_cntr_utchi_i      => ppsg_cntr_utchi,
+      ppsg_adj_nsec_o        => ppsg_adj_nsec,
+      ppsg_adj_nsec_wr_o     => ppsg_adj_nsec_wr,
+      ppsg_adj_utclo_o       => ppsg_adj_utclo,
+      ppsg_adj_utclo_wr_o    => ppsg_adj_utclo_wr,
+      ppsg_adj_utchi_o       => ppsg_adj_utchi,
+      ppsg_adj_utchi_wr_o    => ppsg_adj_utchi_wr,
+      ppsg_escr_pps_valid_o  => ppsg_escr_pps_valid,
+      ppsg_escr_tm_valid_o   => ppsg_escr_tm_valid,
+      ppsg_escr_sec_set_o    => ppsg_escr_sec_set,
+      ppsg_escr_nsec_set_o   => ppsg_escr_nsec_set,
+      ppsg_escr_pps_unmask_o => ppsg_escr_pps_unmask);
+
+-- drive unused signals
+  wb_out.rty   <= '0';
+  wb_out.stall <= '0';
+  wb_out.int   <= '0';
+  wb_out.err   <= '0';
+
+-- start the adjustment upon write of 1 to CNT_ADJ bit
+  cntr_adjust_p <= ppsg_cr_cnt_adj_load and ppsg_cr_cnt_adj_o;
+
+-- drive the readout value of CNT_ADJ to 1 when the adjustment is over
+  ppsg_cr_cnt_adj_i <= pps_valid_int;
+
+  pps_valid_o <= pps_valid_int;
+
+  tm_utc_o        <= std_logic_vector(cntr_utc);
+  tm_cycles_o     <= std_logic_vector(cntr_nsec);
+  tm_time_valid_o <= ppsg_escr_tm_valid;
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/xwr_pps_gen.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/xwr_pps_gen.vhd
new file mode 100644
index 000000000..547a19ab9
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/xwr_pps_gen.vhd
@@ -0,0 +1,162 @@
+-------------------------------------------------------------------------------
+-- Title      : PPS Generator & UTC Realtime clock
+-- Project    : WhiteRabbit Switch
+-------------------------------------------------------------------------------
+-- File       : xwb_pps_gen.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2010-09-02
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010-2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2010-09-02  1.0      twlostow        Created
+-- 2011-05-09  1.1      twlostow        Added external PPS input
+-- 2011-10-26  1.2      greg.d          xwb module
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+
+entity xwr_pps_gen is
+  generic(
+    g_interface_mode       : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity  : t_wishbone_address_granularity := WORD;
+    g_ref_clock_rate       : integer                        := 125000000;
+    g_ext_clock_rate       : integer                        := 10000000;
+    g_with_ext_clock_input : boolean                        := FALSE
+    );
+  port (
+    clk_ref_i   : in std_logic;
+    clk_sys_i   : in std_logic;
+    rst_ref_n_i : in std_logic;
+    rst_sys_n_i : in std_logic;
+
+    slave_i : in  t_wishbone_slave_in;
+    slave_o : out t_wishbone_slave_out;
+
+    link_ok_i : in std_logic;
+
+    pps_in_i : in std_logic;
+
+    -- Single-pulse PPS output for synchronizing endpoints to
+    pps_csync_o : out std_logic;
+    pps_out_o   : out std_logic;
+    pps_led_o   : out std_logic;
+
+    pps_valid_o : out std_logic;
+
+    tm_utc_o        : out std_logic_vector(39 downto 0);
+    tm_cycles_o     : out std_logic_vector(27 downto 0);
+    tm_time_valid_o : out std_logic
+
+    );
+end xwr_pps_gen;
+
+architecture behavioral of xwr_pps_gen is
+
+  component wr_pps_gen is
+    generic(
+      g_interface_mode       : t_wishbone_interface_mode;
+      g_address_granularity  : t_wishbone_address_granularity;
+      g_ref_clock_rate       : integer;
+      g_ext_clock_rate       : integer := 10000000;
+      g_with_ext_clock_input : boolean := FALSE
+      );
+    port (
+      clk_ref_i       : in  std_logic;
+      clk_sys_i       : in  std_logic;
+      rst_ref_n_i     : in  std_logic;
+      rst_sys_n_i     : in  std_logic;
+      wb_adr_i        : in  std_logic_vector(4 downto 0);
+      wb_dat_i        : in  std_logic_vector(31 downto 0);
+      wb_dat_o        : out std_logic_vector(31 downto 0);
+      wb_cyc_i        : in  std_logic;
+      wb_sel_i        : in  std_logic_vector(3 downto 0);
+      wb_stb_i        : in  std_logic;
+      wb_we_i         : in  std_logic;
+      wb_ack_o        : out std_logic;
+      wb_stall_o      : out std_logic;
+      link_ok_i       : in  std_logic;
+      pps_in_i        : in  std_logic;
+      pps_csync_o     : out std_logic;
+      pps_out_o       : out std_logic;
+      pps_led_o       : out std_logic;
+      pps_valid_o     : out std_logic;
+      tm_utc_o        : out std_logic_vector(39 downto 0);
+      tm_cycles_o     : out std_logic_vector(27 downto 0);
+      tm_time_valid_o : out std_logic
+      );
+  end component;
+
+begin  -- behavioral
+
+
+  WRAPPED_PPSGEN : wr_pps_gen
+    generic map(
+      g_interface_mode       => g_interface_mode,
+      g_address_granularity  => g_address_granularity,
+      g_ref_clock_rate       => g_ref_clock_rate,
+      g_ext_clock_rate       => g_ext_clock_rate,
+      g_with_ext_clock_input => g_with_ext_clock_input
+      )
+    port map(
+      clk_ref_i       => clk_ref_i,
+      clk_sys_i       => clk_sys_i,
+      rst_ref_n_i     => rst_ref_n_i,
+      rst_sys_n_i     => rst_sys_n_i,
+      wb_adr_i        => slave_i.adr(4 downto 0),
+      wb_dat_i        => slave_i.dat,
+      wb_dat_o        => slave_o.dat,
+      wb_cyc_i        => slave_i.cyc,
+      wb_sel_i        => slave_i.sel,
+      wb_stb_i        => slave_i.stb,
+      wb_we_i         => slave_i.we,
+      wb_ack_o        => slave_o.ack,
+      wb_stall_o      => slave_o.stall,
+      link_ok_i       => link_ok_i,
+      pps_in_i        => pps_in_i,
+      pps_csync_o     => pps_csync_o,
+      pps_out_o       => pps_out_o,
+      pps_led_o       => pps_led_o,
+      pps_valid_o     => pps_valid_o,
+      tm_utc_o        => tm_utc_o,
+      tm_cycles_o     => tm_cycles_o,
+      tm_time_valid_o => tm_time_valid_o
+      );
+
+
+  slave_o.err <= '0';
+  slave_o.rty <= '0';
+  slave_o.int <= '0';
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/softpll_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/softpll_pkg.vhd
new file mode 100644
index 000000000..0fdac142b
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/softpll_pkg.vhd
@@ -0,0 +1,31 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package softpll_pkg is
+
+  constant c_softpll_max_aux_clocks : integer := 8;
+
+  type t_softpll_phase_detector_type is (CH_DDMTD, CH_BANGBANG);
+
+  type t_softpll_channel_config_array is array(0 to c_softpll_max_aux_clocks-1) of t_softpll_phase_detector_type;
+
+  constant c_softpll_default_channel_config : t_softpll_channel_config_array := (others => CH_DDMTD);
+
+  -- External 10 MHz input divider parameters. 
+  constant c_softpll_ext_div_ref     : integer := 8;
+  constant c_softpll_ext_div_fb      : integer := 50;
+  constant c_softpll_ext_log2_gating : integer := 13;
+
+  constant c_softpll_out_status_off      : std_logic_vector(3 downto 0) := "0000";
+  constant c_softpll_out_status_locking  : std_logic_vector(3 downto 0) := "0001";
+  constant c_softpll_out_status_locked   : std_logic_vector(3 downto 0) := "0010";
+  constant c_softpll_out_status_aligning : std_logic_vector(3 downto 0) := "0011";
+  constant c_softpll_out_status_holdover : std_logic_vector(3 downto 0) := "0100";
+  
+end package;
+
+package body softpll_pkg is
+
+end softpll_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_aligner.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_aligner.vhd
new file mode 100644
index 000000000..941279c02
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_aligner.vhd
@@ -0,0 +1,180 @@
+-------------------------------------------------------------------------------
+-- Title      : White Rabbit Softcore PLL (new generation) - SoftPLL-ng
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : spll_aligner.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.gencores_pkg.all;
+
+entity spll_aligner is
+  generic (
+    g_counter_width  : integer := 28;
+    g_ref_clock_rate : integer := 125000000;
+    g_in_clock_rate  : integer := 10000000;
+    g_sample_rate    : integer := 100
+    );
+  port (
+    clk_sys_i : in std_logic;
+    clk_in_i  : in std_logic;
+    clk_ref_i : in std_logic;
+
+    rst_n_sys_i    : in std_logic;
+    rst_n_ref_i    : in  std_logic;
+    rst_n_ext_i    : in  std_logic;
+
+    pps_ext_a_i    : in std_logic;
+    pps_csync_p1_i : in std_logic;
+
+    sample_cref_o  : out std_logic_vector(g_counter_width-1 downto 0);
+    sample_cin_o   : out std_logic_vector(g_counter_width-1 downto 0);
+    sample_valid_o : out std_logic;
+    sample_ack_i   : in  std_logic
+    );
+
+end spll_aligner;
+
+architecture rtl of spll_aligner is
+
+  constant c_div_ticks : integer := g_ref_clock_rate / g_sample_rate;
+
+  signal cnt_ref_bin, cnt_in_bin, cnt_in_bin_x      : unsigned(g_counter_width-1 downto 0);
+  signal cnt_in_gray, cnt_in_gray_x, cnt_in_gray_xd : std_logic_vector(g_counter_width-1 downto 0);
+
+  signal cnt_ref_div           : unsigned(g_counter_width-1 downto 0);
+  signal pps_ext_p, pps_ext_d0 : std_logic;
+  signal ref_div_p             : std_logic;
+  signal sample_ready_p        : std_logic;
+begin
+
+  p_ref_counter : process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      if pps_csync_p1_i = '1' or rst_n_ref_i = '0' then
+        cnt_ref_bin <= to_unsigned(0, g_counter_width);
+      elsif(cnt_ref_bin = g_ref_clock_rate - 1) then
+        cnt_ref_bin <= (others => '0');
+      else
+        cnt_ref_bin <= cnt_ref_bin + 1;
+      end if;
+    end if;
+  end process;
+
+  p_samplerate_divider : process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      if pps_csync_p1_i = '1' or rst_n_ref_i = '0' then
+        ref_div_p   <= '0';
+        cnt_ref_div <= to_unsigned(0, g_counter_width);
+      elsif (cnt_ref_div = c_div_ticks - 2) then
+        ref_div_p   <= '1';
+        cnt_ref_div <= cnt_ref_div + 1;
+      elsif (cnt_ref_div = c_div_ticks - 1) then
+        ref_div_p   <= '0';
+        cnt_ref_div <= (others => '0');
+      else
+        ref_div_p   <= '0';
+        cnt_ref_div <= cnt_ref_div + 1;
+      end if;
+    end if;
+  end process;
+
+  p_delay_ext_pps : process(clk_in_i)
+  begin
+    if rising_edge(clk_in_i) then
+      pps_ext_d0 <= pps_ext_a_i;
+    end if;
+  end process;
+
+  pps_ext_p <= not pps_ext_d0 and pps_ext_a_i;
+
+  p_in_counter : process(clk_in_i)
+  begin
+    if rising_edge(clk_in_i) then
+      if pps_ext_p = '1' or rst_n_ext_i = '0' then
+        cnt_in_bin <= to_unsigned(2, g_counter_width);
+      elsif(cnt_in_bin = g_in_clock_rate - 1) then
+        cnt_in_bin <= (others => '0');
+      else
+        cnt_in_bin <= cnt_in_bin + 1;
+      end if;
+    end if;
+  end process;
+
+  p_in_bin2gray : process (clk_in_i)
+  begin
+    if rising_edge(clk_in_i) then
+      cnt_in_gray <= f_gray_encode (std_logic_vector(cnt_in_bin));
+    end if;
+  end process;
+
+  p_sample_difference : process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      cnt_in_gray_x  <= cnt_in_gray;
+      cnt_in_gray_xd <= cnt_in_gray_x;
+
+      if(ref_div_p = '1') then
+        sample_cin_o  <= f_gray_decode(cnt_in_gray_xd, 1);
+        sample_cref_o <= std_logic_vector (cnt_ref_bin);
+      end if;
+    end if;
+  end process;
+
+  U_sync_sampling : gc_pulse_synchronizer2
+    port map (
+      clk_in_i    => clk_ref_i,
+      rst_in_n_i  => rst_n_ref_i,
+      clk_out_i   => clk_sys_i,
+      rst_out_n_i => rst_n_sys_i,
+      d_p_i       => ref_div_p,
+      q_p_o       => sample_ready_p);
+
+
+  p_gen_sample_valid : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_sys_i = '0' then
+        sample_valid_o <= '0';
+      else
+        if sample_ready_p = '1' then
+          sample_valid_o <= '1';
+        elsif sample_ack_i = '1' then
+          sample_valid_o <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+end rtl;
+
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_wb_slave.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_wb_slave.vhd
new file mode 100644
index 000000000..11a8687b7
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_wb_slave.vhd
@@ -0,0 +1,939 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Softcore PLL
+---------------------------------------------------------------------------------------
+-- File           : spll_wb_slave.vhd
+-- Author         : auto-generated by wbgen2 from spll_wb_slave.wb
+-- Created        : Wed Aug 16 22:42:41 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wbgen2_pkg.all;
+
+use work.spll_wbgen2_pkg.all;
+
+
+entity spll_wb_slave is
+  generic (
+        g_with_debug_fifo : integer := 1    );
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(5 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    wb_int_o                                 : out    std_logic;
+    irq_tag_i                                : in     std_logic;
+    regs_i                                   : in     t_spll_in_registers;
+    regs_o                                   : out    t_spll_out_registers
+  );
+end spll_wb_slave;
+
+architecture syn of spll_wb_slave is
+
+signal spll_eccr_ext_en_int                     : std_logic      ;
+signal spll_eccr_ext_ref_pllrst_int             : std_logic      ;
+signal spll_occr_out_lock_int                   : std_logic_vector(7 downto 0);
+signal spll_deglitch_thr_int                    : std_logic_vector(15 downto 0);
+signal spll_dfr_host_rst_n                      : std_logic      ;
+signal spll_dfr_host_in_int                     : std_logic_vector(47 downto 0);
+signal spll_dfr_host_out_int                    : std_logic_vector(47 downto 0);
+signal spll_dfr_host_rdreq_int                  : std_logic      ;
+signal spll_dfr_host_rdreq_int_d0               : std_logic      ;
+signal spll_trr_rst_n                           : std_logic      ;
+signal spll_trr_in_int                          : std_logic_vector(31 downto 0);
+signal spll_trr_out_int                         : std_logic_vector(31 downto 0);
+signal spll_trr_rdreq_int                       : std_logic      ;
+signal spll_trr_rdreq_int_d0                    : std_logic      ;
+signal eic_idr_int                              : std_logic_vector(0 downto 0);
+signal eic_idr_write_int                        : std_logic      ;
+signal eic_ier_int                              : std_logic_vector(0 downto 0);
+signal eic_ier_write_int                        : std_logic      ;
+signal eic_imr_int                              : std_logic_vector(0 downto 0);
+signal eic_isr_clear_int                        : std_logic_vector(0 downto 0);
+signal eic_isr_status_int                       : std_logic_vector(0 downto 0);
+signal eic_irq_ack_int                          : std_logic_vector(0 downto 0);
+signal eic_isr_write_int                        : std_logic      ;
+signal spll_dfr_host_full_int                   : std_logic      ;
+signal spll_dfr_host_empty_int                  : std_logic      ;
+signal spll_dfr_host_usedw_int                  : std_logic_vector(12 downto 0);
+signal spll_trr_empty_int                       : std_logic      ;
+signal irq_inputs_vector_int                    : std_logic_vector(0 downto 0);
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal rwaddr_reg                               : std_logic_vector(5 downto 0);
+signal ack_in_progress                          : std_logic      ;
+
+begin
+-- Some internal signals assignments
+  wrdata_reg <= wb_dat_i;
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      spll_eccr_ext_en_int <= '0';
+      spll_eccr_ext_ref_pllrst_int <= '0';
+      regs_o.al_cr_valid_load_o <= '0';
+      regs_o.f_dmtd_valid_load_o <= '0';
+      regs_o.f_ref_valid_load_o <= '0';
+      regs_o.f_ext_valid_load_o <= '0';
+      spll_occr_out_lock_int <= "00000000";
+      regs_o.rcer_load_o <= '0';
+      regs_o.ocer_load_o <= '0';
+      regs_o.dac_hpll_wr_o <= '0';
+      regs_o.dac_main_value_wr_o <= '0';
+      regs_o.dac_main_dac_sel_wr_o <= '0';
+      spll_deglitch_thr_int <= "0000000000000000";
+      regs_o.dfr_spll_value_wr_o <= '0';
+      regs_o.dfr_spll_eos_wr_o <= '0';
+      eic_idr_write_int <= '0';
+      eic_ier_write_int <= '0';
+      eic_isr_write_int <= '0';
+      spll_dfr_host_rdreq_int <= '0';
+      spll_trr_rdreq_int <= '0';
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          regs_o.al_cr_valid_load_o <= '0';
+          regs_o.f_dmtd_valid_load_o <= '0';
+          regs_o.f_ref_valid_load_o <= '0';
+          regs_o.f_ext_valid_load_o <= '0';
+          regs_o.rcer_load_o <= '0';
+          regs_o.ocer_load_o <= '0';
+          regs_o.dac_hpll_wr_o <= '0';
+          regs_o.dac_main_value_wr_o <= '0';
+          regs_o.dac_main_dac_sel_wr_o <= '0';
+          regs_o.dfr_spll_value_wr_o <= '0';
+          regs_o.dfr_spll_eos_wr_o <= '0';
+          eic_idr_write_int <= '0';
+          eic_ier_write_int <= '0';
+          eic_isr_write_int <= '0';
+          ack_in_progress <= '0';
+        else
+          regs_o.al_cr_valid_load_o <= '0';
+          regs_o.f_dmtd_valid_load_o <= '0';
+          regs_o.f_ref_valid_load_o <= '0';
+          regs_o.f_ext_valid_load_o <= '0';
+          regs_o.rcer_load_o <= '0';
+          regs_o.ocer_load_o <= '0';
+          regs_o.dac_hpll_wr_o <= '0';
+          regs_o.dac_main_value_wr_o <= '0';
+          regs_o.dac_main_dac_sel_wr_o <= '0';
+          regs_o.dfr_spll_value_wr_o <= '0';
+          regs_o.dfr_spll_eos_wr_o <= '0';
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(5 downto 0) is
+          when "000000" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(13 downto 8) <= "000000";
+            rddata_reg(21 downto 16) <= regs_i.csr_n_ref_i;
+            rddata_reg(26 downto 24) <= regs_i.csr_n_out_i;
+            rddata_reg(27) <= regs_i.csr_dbg_supported_i;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000001" => 
+            if (wb_we_i = '1') then
+              spll_eccr_ext_en_int <= wrdata_reg(0);
+              spll_eccr_ext_ref_pllrst_int <= wrdata_reg(31);
+            end if;
+            rddata_reg(0) <= spll_eccr_ext_en_int;
+            rddata_reg(1) <= regs_i.eccr_ext_supported_i;
+            rddata_reg(2) <= regs_i.eccr_ext_ref_locked_i;
+            rddata_reg(3) <= regs_i.eccr_ext_ref_stopped_i;
+            rddata_reg(31) <= spll_eccr_ext_ref_pllrst_int;
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000010" => 
+            if (wb_we_i = '1') then
+              regs_o.al_cr_valid_load_o <= '1';
+            end if;
+            rddata_reg(8 downto 0) <= regs_i.al_cr_valid_i;
+            rddata_reg(17 downto 9) <= regs_i.al_cr_required_i;
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.al_cref_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000100" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.al_cin_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000101" => 
+            if (wb_we_i = '1') then
+              regs_o.f_dmtd_valid_load_o <= '1';
+            end if;
+            rddata_reg(27 downto 0) <= regs_i.f_dmtd_freq_i;
+            rddata_reg(28) <= regs_i.f_dmtd_valid_i;
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000110" => 
+            if (wb_we_i = '1') then
+              regs_o.f_ref_valid_load_o <= '1';
+            end if;
+            rddata_reg(27 downto 0) <= regs_i.f_ref_freq_i;
+            rddata_reg(28) <= regs_i.f_ref_valid_i;
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000111" => 
+            if (wb_we_i = '1') then
+              regs_o.f_ext_valid_load_o <= '1';
+            end if;
+            rddata_reg(27 downto 0) <= regs_i.f_ext_freq_i;
+            rddata_reg(28) <= regs_i.f_ext_valid_i;
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001000" => 
+            if (wb_we_i = '1') then
+              spll_occr_out_lock_int <= wrdata_reg(23 downto 16);
+            end if;
+            rddata_reg(15 downto 8) <= regs_i.occr_out_en_i;
+            rddata_reg(23 downto 16) <= spll_occr_out_lock_int;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001001" => 
+            if (wb_we_i = '1') then
+              regs_o.rcer_load_o <= '1';
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rcer_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001010" => 
+            if (wb_we_i = '1') then
+              regs_o.ocer_load_o <= '1';
+            end if;
+            rddata_reg(7 downto 0) <= regs_i.ocer_i;
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010000" => 
+            if (wb_we_i = '1') then
+              regs_o.dac_hpll_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010001" => 
+            if (wb_we_i = '1') then
+              regs_o.dac_main_value_wr_o <= '1';
+              regs_o.dac_main_dac_sel_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010010" => 
+            if (wb_we_i = '1') then
+              spll_deglitch_thr_int <= wrdata_reg(15 downto 0);
+            end if;
+            rddata_reg(15 downto 0) <= spll_deglitch_thr_int;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010011" => 
+            if (wb_we_i = '1') then
+              regs_o.dfr_spll_value_wr_o <= '1';
+              regs_o.dfr_spll_eos_wr_o <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011000" => 
+            if (wb_we_i = '1') then
+              eic_idr_write_int <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011001" => 
+            if (wb_we_i = '1') then
+              eic_ier_write_int <= '1';
+            end if;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011010" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(0) <= eic_imr_int(0);
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011011" => 
+            if (wb_we_i = '1') then
+              eic_isr_write_int <= '1';
+            end if;
+            rddata_reg(0) <= eic_isr_status_int(0);
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011100" => 
+            if (wb_we_i = '1') then
+            end if;
+            if (spll_dfr_host_rdreq_int_d0 = '0') then
+              spll_dfr_host_rdreq_int <= not spll_dfr_host_rdreq_int;
+            else
+              rddata_reg(31 downto 0) <= spll_dfr_host_out_int(31 downto 0);
+              ack_in_progress <= '1';
+              ack_sreg(0) <= '1';
+            end if;
+          when "011101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(15 downto 0) <= spll_dfr_host_out_int(47 downto 32);
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011110" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(16) <= spll_dfr_host_full_int;
+            rddata_reg(17) <= spll_dfr_host_empty_int;
+            rddata_reg(12 downto 0) <= spll_dfr_host_usedw_int;
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011111" => 
+            if (wb_we_i = '1') then
+            end if;
+            if (spll_trr_rdreq_int_d0 = '0') then
+              spll_trr_rdreq_int <= not spll_trr_rdreq_int;
+            else
+              rddata_reg(23 downto 0) <= spll_trr_out_int(23 downto 0);
+              rddata_reg(30 downto 24) <= spll_trr_out_int(30 downto 24);
+              rddata_reg(31) <= spll_trr_out_int(31);
+              ack_in_progress <= '1';
+              ack_sreg(0) <= '1';
+            end if;
+          when "100000" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(17) <= spll_trr_empty_int;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- Number of reference channels (max: 32)
+-- Number of output channels (max: 8)
+-- Debug queue supported
+-- Enable External Clock PLL
+  regs_o.eccr_ext_en_o <= spll_eccr_ext_en_int;
+-- External Clock Input Available
+-- External Clock Reference Present
+-- EXT_REF_STOPPED
+-- EXT_PLL_RST
+  regs_o.eccr_ext_ref_pllrst_o <= spll_eccr_ext_ref_pllrst_int;
+-- Aligner sample valid/select on channel
+  regs_o.al_cr_valid_o <= wrdata_reg(8 downto 0);
+-- Aligner required on channel
+-- Aligner reference counter
+-- Aligner reference counter
+-- FREQ
+-- VALID
+  regs_o.f_dmtd_valid_o <= wrdata_reg(28);
+-- FREQ
+-- VALID
+  regs_o.f_ref_valid_o <= wrdata_reg(28);
+-- FREQ
+-- VALID
+  regs_o.f_ext_valid_o <= wrdata_reg(28);
+-- Output Channel HW enable flag
+-- Output Channel locked flag
+  regs_o.occr_out_lock_o <= spll_occr_out_lock_int;
+-- Reference Channel Enable
+  regs_o.rcer_o <= wrdata_reg(31 downto 0);
+-- Output Channel Enable
+  regs_o.ocer_o <= wrdata_reg(7 downto 0);
+-- DAC value
+-- pass-through field: DAC value in register: Helper DAC Output
+  regs_o.dac_hpll_o <= wrdata_reg(15 downto 0);
+-- DAC value
+-- pass-through field: DAC value in register: Main DAC Output
+  regs_o.dac_main_value_o <= wrdata_reg(15 downto 0);
+-- DAC select
+-- pass-through field: DAC select in register: Main DAC Output
+  regs_o.dac_main_dac_sel_o <= wrdata_reg(19 downto 16);
+-- Threshold
+  regs_o.deglitch_thr_o <= spll_deglitch_thr_int;
+-- Debug Value
+-- pass-through field: Debug Value in register: Debug FIFO Register - SPLL side
+  regs_o.dfr_spll_value_o <= wrdata_reg(30 downto 0);
+-- End-of-Sample
+-- pass-through field: End-of-Sample in register: Debug FIFO Register - SPLL side
+  regs_o.dfr_spll_eos_o <= wrdata_reg(31);
+  genblock_0: if (not (g_with_debug_fifo = 0)) generate
+-- extra code for reg/fifo/mem: Debug FIFO Register - Host side
+    spll_dfr_host_in_int(31 downto 0) <= regs_i.dfr_host_value_i;
+    spll_dfr_host_in_int(47 downto 32) <= regs_i.dfr_host_seq_id_i;
+    spll_dfr_host_rst_n <= rst_n_i;
+    spll_dfr_host_INST : wbgen2_fifo_sync
+      generic map (
+        g_size               => 8192,
+        g_width              => 48,
+        g_usedw_size         => 13
+      )
+      port map (
+        wr_req_i             => regs_i.dfr_host_wr_req_i,
+        wr_full_o            => regs_o.dfr_host_wr_full_o,
+        wr_empty_o           => regs_o.dfr_host_wr_empty_o,
+        wr_usedw_o           => regs_o.dfr_host_wr_usedw_o,
+        rd_full_o            => spll_dfr_host_full_int,
+        rd_empty_o           => spll_dfr_host_empty_int,
+        rd_usedw_o           => spll_dfr_host_usedw_int,
+        rd_req_i             => spll_dfr_host_rdreq_int,
+        rst_n_i              => spll_dfr_host_rst_n,
+        clk_i                => clk_sys_i,
+        wr_data_i            => spll_dfr_host_in_int,
+        rd_data_o            => spll_dfr_host_out_int
+      );
+    
+  end generate genblock_0;
+  genblock_1: if (g_with_debug_fifo = 0) generate
+    regs_o.dfr_host_wr_full_o <= '0';
+    regs_o.dfr_host_wr_empty_o <= '0';
+    regs_o.dfr_host_wr_usedw_o <= "0000000000000";
+  end generate genblock_1;
+-- extra code for reg/fifo/mem: Tag Readout Register
+  spll_trr_in_int(23 downto 0) <= regs_i.trr_value_i;
+  spll_trr_in_int(30 downto 24) <= regs_i.trr_chan_id_i;
+  spll_trr_in_int(31) <= regs_i.trr_disc_i;
+  spll_trr_rst_n <= rst_n_i;
+  spll_trr_INST : wbgen2_fifo_sync
+    generic map (
+      g_size               => 32,
+      g_width              => 32,
+      g_usedw_size         => 5
+    )
+    port map (
+      wr_req_i             => regs_i.trr_wr_req_i,
+      wr_full_o            => regs_o.trr_wr_full_o,
+      wr_empty_o           => regs_o.trr_wr_empty_o,
+      rd_empty_o           => spll_trr_empty_int,
+      rd_req_i             => spll_trr_rdreq_int,
+      rst_n_i              => spll_trr_rst_n,
+      clk_i                => clk_sys_i,
+      wr_data_i            => spll_trr_in_int,
+      rd_data_o            => spll_trr_out_int
+    );
+  
+-- extra code for reg/fifo/mem: Interrupt disable register
+  eic_idr_int(0) <= wrdata_reg(0);
+-- extra code for reg/fifo/mem: Interrupt enable register
+  eic_ier_int(0) <= wrdata_reg(0);
+-- extra code for reg/fifo/mem: Interrupt status register
+  eic_isr_clear_int(0) <= wrdata_reg(0);
+-- extra code for reg/fifo/mem: IRQ_CONTROLLER
+  eic_irq_controller_inst : wbgen2_eic
+    generic map (
+      g_num_interrupts     => 1,
+      g_irq00_mode         => 3,
+      g_irq01_mode         => 0,
+      g_irq02_mode         => 0,
+      g_irq03_mode         => 0,
+      g_irq04_mode         => 0,
+      g_irq05_mode         => 0,
+      g_irq06_mode         => 0,
+      g_irq07_mode         => 0,
+      g_irq08_mode         => 0,
+      g_irq09_mode         => 0,
+      g_irq0a_mode         => 0,
+      g_irq0b_mode         => 0,
+      g_irq0c_mode         => 0,
+      g_irq0d_mode         => 0,
+      g_irq0e_mode         => 0,
+      g_irq0f_mode         => 0,
+      g_irq10_mode         => 0,
+      g_irq11_mode         => 0,
+      g_irq12_mode         => 0,
+      g_irq13_mode         => 0,
+      g_irq14_mode         => 0,
+      g_irq15_mode         => 0,
+      g_irq16_mode         => 0,
+      g_irq17_mode         => 0,
+      g_irq18_mode         => 0,
+      g_irq19_mode         => 0,
+      g_irq1a_mode         => 0,
+      g_irq1b_mode         => 0,
+      g_irq1c_mode         => 0,
+      g_irq1d_mode         => 0,
+      g_irq1e_mode         => 0,
+      g_irq1f_mode         => 0
+    )
+    port map (
+      clk_i                => clk_sys_i,
+      rst_n_i              => rst_n_i,
+      irq_i                => irq_inputs_vector_int,
+      irq_ack_o            => eic_irq_ack_int,
+      reg_imr_o            => eic_imr_int,
+      reg_ier_i            => eic_ier_int,
+      reg_ier_wr_stb_i     => eic_ier_write_int,
+      reg_idr_i            => eic_idr_int,
+      reg_idr_wr_stb_i     => eic_idr_write_int,
+      reg_isr_o            => eic_isr_status_int,
+      reg_isr_i            => eic_isr_clear_int,
+      reg_isr_wr_stb_i     => eic_isr_write_int,
+      wb_irq_o             => wb_int_o
+    );
+  
+  irq_inputs_vector_int(0) <= irq_tag_i;
+-- extra code for reg/fifo/mem: FIFO 'Debug FIFO Register - Host side' data output register 0
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      spll_dfr_host_rdreq_int_d0 <= '0';
+    elsif rising_edge(clk_sys_i) then
+      spll_dfr_host_rdreq_int_d0 <= spll_dfr_host_rdreq_int;
+    end if;
+  end process;
+  
+  
+-- extra code for reg/fifo/mem: FIFO 'Debug FIFO Register - Host side' data output register 1
+-- extra code for reg/fifo/mem: FIFO 'Tag Readout Register' data output register 0
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      spll_trr_rdreq_int_d0 <= '0';
+    elsif rising_edge(clk_sys_i) then
+      spll_trr_rdreq_int_d0 <= spll_trr_rdreq_int;
+    end if;
+  end process;
+  
+  
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
new file mode 100644
index 000000000..5550a3dd8
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
@@ -0,0 +1,207 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Softcore PLL
+---------------------------------------------------------------------------------------
+-- File           : spll_wbgen2_pkg.vhd
+-- Author         : auto-generated by wbgen2 from spll_wb_slave.wb
+-- Created        : Wed Aug 16 22:42:41 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wbgen2_pkg.all;
+
+package spll_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_spll_in_registers is record
+    csr_n_ref_i                              : std_logic_vector(5 downto 0);
+    csr_n_out_i                              : std_logic_vector(2 downto 0);
+    csr_dbg_supported_i                      : std_logic;
+    eccr_ext_supported_i                     : std_logic;
+    eccr_ext_ref_locked_i                    : std_logic;
+    eccr_ext_ref_stopped_i                   : std_logic;
+    al_cr_valid_i                            : std_logic_vector(8 downto 0);
+    al_cr_required_i                         : std_logic_vector(8 downto 0);
+    al_cref_i                                : std_logic_vector(31 downto 0);
+    al_cin_i                                 : std_logic_vector(31 downto 0);
+    f_dmtd_freq_i                            : std_logic_vector(27 downto 0);
+    f_dmtd_valid_i                           : std_logic;
+    f_ref_freq_i                             : std_logic_vector(27 downto 0);
+    f_ref_valid_i                            : std_logic;
+    f_ext_freq_i                             : std_logic_vector(27 downto 0);
+    f_ext_valid_i                            : std_logic;
+    occr_out_en_i                            : std_logic_vector(7 downto 0);
+    rcer_i                                   : std_logic_vector(31 downto 0);
+    ocer_i                                   : std_logic_vector(7 downto 0);
+    dfr_host_wr_req_i                        : std_logic;
+    dfr_host_value_i                         : std_logic_vector(31 downto 0);
+    dfr_host_seq_id_i                        : std_logic_vector(15 downto 0);
+    trr_wr_req_i                             : std_logic;
+    trr_value_i                              : std_logic_vector(23 downto 0);
+    trr_chan_id_i                            : std_logic_vector(6 downto 0);
+    trr_disc_i                               : std_logic;
+    end record;
+  
+  constant c_spll_in_registers_init_value: t_spll_in_registers := (
+    csr_n_ref_i => (others => '0'),
+    csr_n_out_i => (others => '0'),
+    csr_dbg_supported_i => '0',
+    eccr_ext_supported_i => '0',
+    eccr_ext_ref_locked_i => '0',
+    eccr_ext_ref_stopped_i => '0',
+    al_cr_valid_i => (others => '0'),
+    al_cr_required_i => (others => '0'),
+    al_cref_i => (others => '0'),
+    al_cin_i => (others => '0'),
+    f_dmtd_freq_i => (others => '0'),
+    f_dmtd_valid_i => '0',
+    f_ref_freq_i => (others => '0'),
+    f_ref_valid_i => '0',
+    f_ext_freq_i => (others => '0'),
+    f_ext_valid_i => '0',
+    occr_out_en_i => (others => '0'),
+    rcer_i => (others => '0'),
+    ocer_i => (others => '0'),
+    dfr_host_wr_req_i => '0',
+    dfr_host_value_i => (others => '0'),
+    dfr_host_seq_id_i => (others => '0'),
+    trr_wr_req_i => '0',
+    trr_value_i => (others => '0'),
+    trr_chan_id_i => (others => '0'),
+    trr_disc_i => '0'
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_spll_out_registers is record
+      eccr_ext_en_o                            : std_logic;
+      eccr_ext_ref_pllrst_o                    : std_logic;
+      al_cr_valid_o                            : std_logic_vector(8 downto 0);
+      al_cr_valid_load_o                       : std_logic;
+      f_dmtd_valid_o                           : std_logic;
+      f_dmtd_valid_load_o                      : std_logic;
+      f_ref_valid_o                            : std_logic;
+      f_ref_valid_load_o                       : std_logic;
+      f_ext_valid_o                            : std_logic;
+      f_ext_valid_load_o                       : std_logic;
+      occr_out_lock_o                          : std_logic_vector(7 downto 0);
+      rcer_o                                   : std_logic_vector(31 downto 0);
+      rcer_load_o                              : std_logic;
+      ocer_o                                   : std_logic_vector(7 downto 0);
+      ocer_load_o                              : std_logic;
+      dac_hpll_o                               : std_logic_vector(15 downto 0);
+      dac_hpll_wr_o                            : std_logic;
+      dac_main_value_o                         : std_logic_vector(15 downto 0);
+      dac_main_value_wr_o                      : std_logic;
+      dac_main_dac_sel_o                       : std_logic_vector(3 downto 0);
+      dac_main_dac_sel_wr_o                    : std_logic;
+      deglitch_thr_o                           : std_logic_vector(15 downto 0);
+      dfr_spll_value_o                         : std_logic_vector(30 downto 0);
+      dfr_spll_value_wr_o                      : std_logic;
+      dfr_spll_eos_o                           : std_logic;
+      dfr_spll_eos_wr_o                        : std_logic;
+      dfr_host_wr_full_o                       : std_logic;
+      dfr_host_wr_empty_o                      : std_logic;
+      dfr_host_wr_usedw_o                      : std_logic_vector(12 downto 0);
+      trr_wr_full_o                            : std_logic;
+      trr_wr_empty_o                           : std_logic;
+      end record;
+    
+    constant c_spll_out_registers_init_value: t_spll_out_registers := (
+      eccr_ext_en_o => '0',
+      eccr_ext_ref_pllrst_o => '0',
+      al_cr_valid_o => (others => '0'),
+      al_cr_valid_load_o => '0',
+      f_dmtd_valid_o => '0',
+      f_dmtd_valid_load_o => '0',
+      f_ref_valid_o => '0',
+      f_ref_valid_load_o => '0',
+      f_ext_valid_o => '0',
+      f_ext_valid_load_o => '0',
+      occr_out_lock_o => (others => '0'),
+      rcer_o => (others => '0'),
+      rcer_load_o => '0',
+      ocer_o => (others => '0'),
+      ocer_load_o => '0',
+      dac_hpll_o => (others => '0'),
+      dac_hpll_wr_o => '0',
+      dac_main_value_o => (others => '0'),
+      dac_main_value_wr_o => '0',
+      dac_main_dac_sel_o => (others => '0'),
+      dac_main_dac_sel_wr_o => '0',
+      deglitch_thr_o => (others => '0'),
+      dfr_spll_value_o => (others => '0'),
+      dfr_spll_value_wr_o => '0',
+      dfr_spll_eos_o => '0',
+      dfr_spll_eos_wr_o => '0',
+      dfr_host_wr_full_o => '0',
+      dfr_host_wr_empty_o => '0',
+      dfr_host_wr_usedw_o => (others => '0'),
+      trr_wr_full_o => '0',
+      trr_wr_empty_o => '0'
+      );
+    function "or" (left, right: t_spll_in_registers) return t_spll_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body spll_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if x(i) = '1' then
+tmp(i):= '1';
+else
+tmp(i):= '0';
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_spll_in_registers) return t_spll_in_registers is
+variable tmp: t_spll_in_registers;
+begin
+tmp.csr_n_ref_i := f_x_to_zero(left.csr_n_ref_i) or f_x_to_zero(right.csr_n_ref_i);
+tmp.csr_n_out_i := f_x_to_zero(left.csr_n_out_i) or f_x_to_zero(right.csr_n_out_i);
+tmp.csr_dbg_supported_i := f_x_to_zero(left.csr_dbg_supported_i) or f_x_to_zero(right.csr_dbg_supported_i);
+tmp.eccr_ext_supported_i := f_x_to_zero(left.eccr_ext_supported_i) or f_x_to_zero(right.eccr_ext_supported_i);
+tmp.eccr_ext_ref_locked_i := f_x_to_zero(left.eccr_ext_ref_locked_i) or f_x_to_zero(right.eccr_ext_ref_locked_i);
+tmp.eccr_ext_ref_stopped_i := f_x_to_zero(left.eccr_ext_ref_stopped_i) or f_x_to_zero(right.eccr_ext_ref_stopped_i);
+tmp.al_cr_valid_i := f_x_to_zero(left.al_cr_valid_i) or f_x_to_zero(right.al_cr_valid_i);
+tmp.al_cr_required_i := f_x_to_zero(left.al_cr_required_i) or f_x_to_zero(right.al_cr_required_i);
+tmp.al_cref_i := f_x_to_zero(left.al_cref_i) or f_x_to_zero(right.al_cref_i);
+tmp.al_cin_i := f_x_to_zero(left.al_cin_i) or f_x_to_zero(right.al_cin_i);
+tmp.f_dmtd_freq_i := f_x_to_zero(left.f_dmtd_freq_i) or f_x_to_zero(right.f_dmtd_freq_i);
+tmp.f_dmtd_valid_i := f_x_to_zero(left.f_dmtd_valid_i) or f_x_to_zero(right.f_dmtd_valid_i);
+tmp.f_ref_freq_i := f_x_to_zero(left.f_ref_freq_i) or f_x_to_zero(right.f_ref_freq_i);
+tmp.f_ref_valid_i := f_x_to_zero(left.f_ref_valid_i) or f_x_to_zero(right.f_ref_valid_i);
+tmp.f_ext_freq_i := f_x_to_zero(left.f_ext_freq_i) or f_x_to_zero(right.f_ext_freq_i);
+tmp.f_ext_valid_i := f_x_to_zero(left.f_ext_valid_i) or f_x_to_zero(right.f_ext_valid_i);
+tmp.occr_out_en_i := f_x_to_zero(left.occr_out_en_i) or f_x_to_zero(right.occr_out_en_i);
+tmp.rcer_i := f_x_to_zero(left.rcer_i) or f_x_to_zero(right.rcer_i);
+tmp.ocer_i := f_x_to_zero(left.ocer_i) or f_x_to_zero(right.ocer_i);
+tmp.dfr_host_wr_req_i := f_x_to_zero(left.dfr_host_wr_req_i) or f_x_to_zero(right.dfr_host_wr_req_i);
+tmp.dfr_host_value_i := f_x_to_zero(left.dfr_host_value_i) or f_x_to_zero(right.dfr_host_value_i);
+tmp.dfr_host_seq_id_i := f_x_to_zero(left.dfr_host_seq_id_i) or f_x_to_zero(right.dfr_host_seq_id_i);
+tmp.trr_wr_req_i := f_x_to_zero(left.trr_wr_req_i) or f_x_to_zero(right.trr_wr_req_i);
+tmp.trr_value_i := f_x_to_zero(left.trr_value_i) or f_x_to_zero(right.trr_value_i);
+tmp.trr_chan_id_i := f_x_to_zero(left.trr_chan_id_i) or f_x_to_zero(right.trr_chan_id_i);
+tmp.trr_disc_i := f_x_to_zero(left.trr_disc_i) or f_x_to_zero(right.trr_disc_i);
+return tmp;
+end function;
+end package body;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/wr_softpll_ng.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/wr_softpll_ng.vhd
new file mode 100644
index 000000000..351b60f19
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/wr_softpll_ng.vhd
@@ -0,0 +1,809 @@
+-------------------------------------------------------------------------------
+-- Title      : White Rabbit Softcore PLL (new generation) - SoftPLL-ng
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : wr_softpll_ng.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-29
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: 
+--
+-- The hardware part of the revised softcore PLL. Incorporates a user-defined
+-- number of DDMTD taggers, a FIFO allowing for sequential readout of
+-- the phase tags and ports for driving oscillator tuning DACs.
+-- The rest of the magic is done in the software.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+use work.softpll_pkg.all;
+use work.spll_wbgen2_pkg.all;
+
+entity wr_softpll_ng is
+  generic(
+-- Number of bits in phase tags produced by DDMTDs.
+-- Must be large enough to cover at least a hundred of DDMTD periods to ensure
+-- correct operation of the SoftPLL software servo algorithm - that
+-- means, for a typical DMTD frequency offset N=16384, there number of tag bits
+-- should be log2(N) + 7 == 21. Note: the value must match the TAG_BITS constant
+-- in spll_defs.h file!
+    g_tag_bits : integer;
+
+-- These two are obvious:
+    g_num_ref_inputs : integer := 1;
+    g_num_outputs    : integer := 1;
+
+-- When true, an additional FIFO is instantiated, providing a realtime record
+-- of user-selectable SoftPLL parameters (e.g. tag values, phase error, DAC drive).
+-- These values can be read by "spll_dbg_proxy" daemon for further analysis.
+    g_with_debug_fifo : boolean := false;
+
+-- When true, an additional accumulating bang-bang phase detector is instantiated
+-- for wideband locking of the local oscillator to an external stable reference
+-- (e.g. GPSDO/Cesium 10 MHz)
+    g_with_ext_clock_input : boolean := false;
+
+-- When true, DDMTD inputs are reversed (so that the DDMTD offset clocks is
+-- being sampled by the measured clock). This is functionally equivalent to
+-- "direct" operation, but may improve FPGA timing/routability.
+    g_reverse_dmtds : boolean := true;
+
+-- Divides the DDMTD clock inputs by 2, removing the "CLOCK_DEDICATED_ROUTE"
+-- errors under ISE tools, at the cost of bandwidth reduction. Advanced option
+-- use with care.
+    g_divide_input_by_2 : boolean := false;
+
+    g_ref_clock_rate : integer := 125000000;
+    g_ext_clock_rate : integer := 10000000;
+
+
+    g_interface_mode      : t_wishbone_interface_mode      := PIPELINED;
+    g_address_granularity : t_wishbone_address_granularity := WORD
+    );
+
+  port(
+    clk_sys_i    : in std_logic;
+    rst_sys_n_i  : in std_logic;
+    rst_ref_n_i  : in std_logic;
+    rst_ext_n_i  : in std_logic;
+    rst_dmtd_n_i : in std_logic;
+
+-- Reference inputs (i.e. the RX clocks recovered by the PHYs)
+    clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
+
+-- Feedback clocks (i.e. the outputs of the main or auxillary oscillator)
+-- Note: clk_fb_i(0) must be always connected to the primary board's oscillator
+-- (i.e. the one driving the PTP and Ethernet PHY) to ensure correct operation
+-- of the PTP core.
+    clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
+
+-- DMTD Offset clock
+    clk_dmtd_i : in std_logic;
+
+-- External reference clock (e.g. 10 MHz from Cesium/GPSDO). Used only if
+-- g_with_ext_clock_input == true
+    clk_ext_i : in std_logic;
+
+-- External clock, multiplied to 125 MHz using the FPGA's PLL
+    clk_ext_mul_i : in std_logic;
+    clk_ext_mul_locked_i : in std_logic := '1';
+    clk_ext_stopped_i : in std_logic := '0';
+    clk_ext_rst_o : out std_logic;
+
+-- External clock sync/alignment singnal. SoftPLL will align clk_ext_i/clk_fb_i(0)
+-- to match the edges immediately following the rising edge in sync_p_i.
+    pps_csync_p1_i : in std_logic;
+    pps_ext_a_i    : in std_logic;
+
+-- DMTD oscillator drive
+    dac_dmtd_data_o : out std_logic_vector(15 downto 0);
+-- When HI, load the data from dac_dmtd_data_o to the DAC.
+    dac_dmtd_load_o : out std_logic;
+
+-- Output channel DAC value
+    dac_out_data_o : out std_logic_vector(15 downto 0);
+-- Output channel select (0 = Output channel 0, 1 == OC 1, etc...)
+    dac_out_sel_o  : out std_logic_vector(3 downto 0);
+    dac_out_load_o : out std_logic;
+
+-- Output enable input: when HI, enables locking the output(s)
+-- to the reference clock(s)
+    out_enable_i : in  std_logic_vector(g_num_outputs-1 downto 0);
+-- When HI, the respective clock output is locked.
+    out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
+
+    wb_adr_i   : in  std_logic_vector(c_wishbone_address_width-1 downto 0);
+    wb_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_cyc_i   : in  std_logic;
+    wb_sel_i   : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+    wb_stb_i   : in  std_logic;
+    wb_we_i    : in  std_logic;
+    wb_ack_o   : out std_logic;
+    wb_stall_o : out std_logic;
+    wb_irq_o   : out std_logic;
+    debug_o    : out std_logic_vector(5 downto 0);
+
+-- Debug FIFO readout interrupt
+    dbg_fifo_irq_o : out std_logic
+    );
+
+end wr_softpll_ng;
+
+architecture rtl of wr_softpll_ng is
+
+  alias rst_n_i : std_logic is rst_sys_n_i;
+
+  constant c_log2_replication : integer := 2;
+  constant c_use_multi_dmtd   : boolean := false;
+
+  constant c_DBG_FIFO_THRESHOLD : integer := 8180;
+  constant c_DBG_FIFO_COALESCE  : integer := 100;
+  constant c_BB_ERROR_BITS      : integer := 16;
+
+  component dmtd_with_deglitcher
+    generic (
+      g_counter_bits      : natural;
+      g_divide_input_by_2 : boolean;
+			g_reverse           :	boolean);
+    port (
+      rst_n_dmtdclk_i      : in  std_logic;
+      rst_n_sysclk_i       : in  std_logic;
+      clk_in_i             : in  std_logic;
+      clk_dmtd_i           : in  std_logic;
+      clk_sys_i            : in  std_logic;
+      resync_p_a_i         : in  std_logic := '0';
+      resync_p_o           : out std_logic;
+      resync_start_p_i     : in  std_logic;
+      resync_done_o        : out std_logic;
+      shift_en_i           : in  std_logic;
+      shift_dir_i          : in  std_logic;
+      clk_dmtd_en_i        : in  std_logic := '1';
+      deglitch_threshold_i : in  std_logic_vector(15 downto 0);
+      dbg_dmtdout_o        : out std_logic;
+      tag_o                : out std_logic_vector(g_counter_bits-1 downto 0);
+      tag_stb_p1_o         : out std_logic;
+			dbg_clk_d3_o         : out std_logic);
+  end component;
+
+  component spll_wb_slave
+    generic (
+      g_with_debug_fifo : integer);
+    port (
+      rst_n_i    : in  std_logic;
+      clk_sys_i  : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(5 downto 0);
+      wb_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_dat_o   : out std_logic_vector(31 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_stall_o : out std_logic;
+      wb_int_o   : out std_logic;
+      irq_tag_i  : in  std_logic;
+      regs_i     : in  t_spll_in_registers;
+      regs_o     : out t_spll_out_registers);
+  end component;
+
+  component spll_aligner
+    generic (
+      g_counter_width  : integer;
+      g_ref_clock_rate : integer;
+      g_in_clock_rate  : integer;
+      g_sample_rate    : integer);
+    port (
+      clk_sys_i      : in  std_logic;
+      clk_in_i       : in  std_logic;
+      clk_ref_i      : in  std_logic;
+      rst_n_sys_i    : in  std_logic;
+      rst_n_ref_i    : in  std_logic;
+      rst_n_ext_i    : in  std_logic;
+      pps_ext_a_i    : in  std_logic;
+      pps_csync_p1_i : in  std_logic;
+      sample_cref_o  : out std_logic_vector(g_counter_width-1 downto 0);
+      sample_cin_o   : out std_logic_vector(g_counter_width-1 downto 0);
+      sample_valid_o : out std_logic;
+      sample_ack_i   : in  std_logic);
+  end component;
+  function f_num_total_channels
+    return integer is
+  begin
+    if(g_with_ext_clock_input) then
+      return g_num_ref_inputs + g_num_outputs + 1;
+    else
+      return g_num_ref_inputs + g_num_outputs;
+    end if;
+  end f_num_total_channels;
+
+  function f_pick (
+    cond     : boolean;
+    if_true  : std_logic;
+    if_false : std_logic
+    ) return std_logic is
+  begin
+    if(cond) then
+      return if_true;
+    else
+      return if_false;
+    end if;
+  end f_pick;
+
+  function f_pick (
+    cond     : boolean;
+    if_true  : integer;
+    if_false : integer
+    ) return integer is
+  begin
+    if(cond) then
+      return if_true;
+    else
+      return if_false;
+    end if;
+  end f_pick;
+
+  function resize(x : std_logic_vector; new_length : integer) return std_logic_vector is
+    variable tmp : std_logic_vector(new_length-1 downto 0);
+  begin
+    tmp                       := (others => '0');
+    tmp (x'length-1 downto 0) := x;
+    return tmp;
+  end resize;
+
+  type t_tag_array is array (0 to f_num_total_channels-1) of std_logic_vector(g_tag_bits-1 downto 0);
+
+  type t_phase_error_array is array(0 to g_num_outputs-1) of std_logic_vector(c_BB_ERROR_BITS-1 downto 0);
+
+  signal tags, tags_masked                          : t_tag_array;
+  signal tags_grant_p, tags_p, tags_req, tags_grant : std_logic_vector(f_num_total_channels-1 downto 0);
+  signal tag_muxed                                  : std_logic_vector(g_tag_bits-1 downto 0);
+  signal tag_src, tag_src_pre                       : std_logic_vector (5 downto 0);
+  signal tag_valid, tag_valid_pre                   : std_logic;
+
+  signal deglitch_thr_slv : std_logic_vector(15 downto 0);
+
+  signal irq_tag : std_logic;
+
+  signal rcer_int : std_logic_vector(g_num_ref_inputs-1 downto 0);
+  signal ocer_int : std_logic_vector(g_num_outputs-1 downto 0);
+
+  signal wb_irq_out : std_logic;
+
+  signal wb_out   : t_wishbone_slave_out;
+  signal wb_in    : t_wishbone_slave_in;
+  signal regs_in  : t_SPLL_out_registers;
+  signal regs_out : t_SPLL_in_registers;
+
+  -- Debug FIFO signals
+  signal dbg_fifo_almostfull   : std_logic;
+  signal dbg_seq_id            : unsigned(15 downto 0);
+  signal dbg_fifo_permit_write : std_logic;
+  signal dbg_fifo_irq          : std_logic := '0';
+
+  -- Temporary vectors for DDMTD clock selection (straight/reversed)
+  signal dmtd_ref_clk_in, dmtd_ref_clk_dmtd : std_logic_vector(g_num_ref_inputs-1 downto 0);
+  signal rst_n_dmtd_ref_clk                 : std_logic_vector(g_num_ref_inputs-1 downto 0);
+
+  signal dmtd_fb_clk_in, dmtd_fb_clk_dmtd : std_logic_vector(g_num_outputs-1 downto 0);
+  signal rst_n_dmtd_fb_clk                : std_logic_vector(g_num_outputs-1 downto 0);
+
+  signal ext_ref_present : std_logic;
+  signal fb_resync_out   : std_logic_vector(g_num_outputs-1 downto 0);
+
+  signal ref_resync_start_p : std_logic_vector(31 downto 0);
+  signal fb_resync_start_p  : std_logic_vector(15 downto 0);
+
+  type t_aligner_sample_array is array(0 to g_num_outputs) of std_logic_vector(27 downto 0);
+
+  signal aligner_sample_valid, aligner_sample_ack : std_logic_vector(g_num_outputs downto 0);
+  signal aligner_sample_cref, aligner_sample_cin  : t_aligner_sample_array;
+  
+begin  -- rtl
+
+  U_Adapter : wb_slave_adapter
+    generic map(
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => false,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      master_i   => wb_out,
+      master_o   => wb_in,
+      sl_adr_i   => wb_adr_i,
+      sl_dat_i   => wb_dat_i,
+      sl_sel_i   => wb_sel_i,
+      sl_cyc_i   => wb_cyc_i,
+      sl_stb_i   => wb_stb_i,
+      sl_we_i    => wb_we_i,
+      sl_dat_o   => wb_dat_o,
+      sl_ack_o   => wb_ack_o,
+      sl_stall_o => wb_stall_o);
+
+  U_Meas_DMTD_Freq: gc_frequency_meter
+    generic map (
+      g_with_internal_timebase => false,
+      g_clk_sys_freq           => 1,
+      g_counter_bits           => 28)
+    port map (
+      clk_sys_i    => clk_sys_i,
+      clk_in_i     => clk_dmtd_i,
+      rst_n_i      => rst_n_i,
+      pps_p1_i     => pps_ext_a_i,
+      freq_o       => regs_out.f_dmtd_freq_i,
+      freq_valid_o => open);            -- fixme
+
+  U_Meas_REF_Freq: gc_frequency_meter
+    generic map (
+      g_with_internal_timebase => false,
+      g_clk_sys_freq           => 1,
+      g_counter_bits           => 28)
+    port map (
+      clk_sys_i    => clk_sys_i,
+      clk_in_i     => clk_fb_i(0),
+      rst_n_i      => rst_n_i,
+      pps_p1_i     => pps_ext_a_i,
+      freq_o       => regs_out.f_ref_freq_i,
+      freq_valid_o => open);            -- fixme
+
+  U_Meas_EXT_Freq: gc_frequency_meter
+    generic map (
+      g_with_internal_timebase => false,
+      g_clk_sys_freq           => 1,
+      g_counter_bits           => 28)
+    port map (
+      clk_sys_i    => clk_sys_i,
+      clk_in_i     => clk_ext_i,
+      rst_n_i      => rst_n_i,
+      pps_p1_i     => pps_ext_a_i,
+      freq_o       => regs_out.f_ext_freq_i,
+      freq_valid_o => open);            -- fixme
+  
+
+  gen_ref_dmtds : for i in 0 to g_num_ref_inputs-1 generate
+
+    DMTD_REF : dmtd_with_deglitcher
+      generic map (
+        g_counter_bits      => g_tag_bits,
+        g_divide_input_by_2 => g_divide_input_by_2,
+        g_reverse	    => g_reverse_dmtds)
+      port map (
+        rst_n_dmtdclk_i => rst_dmtd_n_i,
+        rst_n_sysclk_i  => rst_n_i,
+
+        clk_dmtd_i    => clk_dmtd_i,
+        clk_dmtd_en_i => '1',
+
+        clk_sys_i => clk_sys_i,
+        clk_in_i  => clk_ref_i(i),
+
+        resync_done_o    => open,
+        resync_start_p_i => '0',
+        resync_p_a_i     => fb_resync_out(0),
+        resync_p_o       => open,
+
+        tag_o                => tags(i),
+        tag_stb_p1_o         => tags_p(i),
+        shift_en_i           => '0',
+        shift_dir_i          => '0',
+        deglitch_threshold_i => deglitch_thr_slv,
+        dbg_dmtdout_o        => open);
+
+
+  end generate gen_ref_dmtds;
+
+  gen_feedback_dmtds : for i in 0 to g_num_outputs-1 generate
+    
+    DMTD_FB : dmtd_with_deglitcher
+      generic map (
+        g_counter_bits      => g_tag_bits,
+        g_divide_input_by_2 => g_divide_input_by_2,
+        g_reverse           => g_reverse_dmtds)
+      port map (
+        rst_n_dmtdclk_i => rst_dmtd_n_i,
+        rst_n_sysclk_i  => rst_n_i,
+
+        clk_dmtd_i    => clk_dmtd_i,
+        clk_dmtd_en_i => '1',
+
+        clk_sys_i => clk_sys_i,
+        clk_in_i  => clk_fb_i(i),
+
+        resync_done_o    => open,
+        resync_start_p_i => '0',
+        resync_p_a_i     => fb_resync_out(0),
+        resync_p_o       => fb_resync_out(i),
+
+        tag_o        => tags(i+g_num_ref_inputs),
+        tag_stb_p1_o => tags_p(i+g_num_ref_inputs),
+        shift_en_i   => '0',
+        shift_dir_i  => '0',
+
+        deglitch_threshold_i => deglitch_thr_slv,
+        dbg_dmtdout_o        => open,
+				dbg_clk_d3_o         => open); --debug_o(4));
+
+
+  end generate gen_feedback_dmtds;
+
+  -- drive unused debug output
+  debug_o(4) <= '0';
+
+  gen_with_ext_clock_input : if(g_with_ext_clock_input) generate
+
+    debug_o(0) <= fb_resync_out(0);
+    debug_o(1) <= tags_p(g_num_ref_inputs + g_num_outputs);
+    debug_o(2) <= tags_p(g_num_ref_inputs);
+    
+    U_DMTD_EXT : dmtd_with_deglitcher
+      generic map (
+        g_counter_bits      => g_tag_bits,
+        g_divide_input_by_2 => g_divide_input_by_2,
+        g_reverse	    => g_reverse_dmtds)
+      port map (
+        rst_n_dmtdclk_i => rst_dmtd_n_i,
+        rst_n_sysclk_i  => rst_n_i,
+        clk_dmtd_i      => clk_dmtd_i,
+        clk_dmtd_en_i   => '1',
+
+        clk_sys_i => clk_sys_i,
+        clk_in_i  => clk_ext_mul_i,
+
+        resync_done_o    => open,
+        resync_start_p_i => '0',
+        resync_p_a_i     => fb_resync_out(0),
+        resync_p_o       => open,
+
+        tag_o        => tags(g_num_ref_inputs + g_num_outputs),
+        tag_stb_p1_o => tags_p(g_num_ref_inputs + g_num_outputs),
+        shift_en_i   => '0',
+        shift_dir_i  => '0',
+
+        deglitch_threshold_i => deglitch_thr_slv,
+        dbg_dmtdout_o        => debug_o(3),
+        dbg_clk_d3_o         => debug_o(5));
+
+    U_Aligner_EXT : spll_aligner
+      generic map (
+        g_counter_width  => 28,
+        g_ref_clock_rate => g_ref_clock_rate,
+        g_in_clock_rate  => g_ext_clock_rate,
+        g_sample_rate    => 100)
+      port map (
+        clk_sys_i      => clk_sys_i,
+        clk_in_i       => clk_ext_i,
+        clk_ref_i      => clk_fb_i(0),
+        rst_n_sys_i    => rst_n_i,
+        rst_n_ref_i    => rst_ref_n_i,
+        rst_n_ext_i    => rst_ext_n_i,
+        pps_ext_a_i    => pps_ext_a_i,
+        pps_csync_p1_i => pps_csync_p1_i,
+        sample_cref_o  => aligner_sample_cref(g_num_outputs),
+        sample_cin_o   => aligner_sample_cin(g_num_outputs),
+        sample_valid_o => aligner_sample_valid(g_num_outputs),
+        sample_ack_i   => aligner_sample_ack(g_num_outputs)
+        );
+
+    aligner_sample_valid(g_num_outputs-1 downto 0) <= (others => '0');
+
+    aligner_sample_cref(0 to g_num_outputs-1) <= (others => (others => '0'));
+    aligner_sample_cin(0 to g_num_outputs-1)  <= (others => (others => '0'));
+
+    regs_out.eccr_ext_supported_i   <= '1' when g_with_ext_clock_input else '0';
+    regs_out.eccr_ext_ref_locked_i  <= clk_ext_mul_locked_i;
+    regs_out.eccr_ext_ref_stopped_i <= clk_ext_stopped_i;
+    clk_ext_rst_o <= regs_in.eccr_ext_ref_pllrst_o;
+  end generate gen_with_ext_clock_input;
+
+  
+  gen_without_ext_clock_input : if(not g_with_ext_clock_input) generate
+    aligner_sample_valid <= (others => '0');
+    aligner_sample_cref  <= (others => (others => '0'));
+    aligner_sample_cin   <= (others => (others => '0'));
+
+    regs_out.eccr_ext_supported_i            <= '0';
+    regs_out.eccr_ext_ref_locked_i           <= '0';
+    regs_out.eccr_ext_ref_stopped_i          <= '0';
+    clk_ext_rst_o <= '0';
+    -- drive unused debug outputs
+    debug_o(0) <= '0';
+    debug_o(1) <= '0';
+    debug_o(2) <= '0';
+    debug_o(3) <= '0';
+    debug_o(5) <= '0';
+  end generate gen_without_ext_clock_input;
+
+  p_ack_aligner_samples: process(regs_in, aligner_sample_valid)
+  begin
+    regs_out.al_cr_valid_i <= (others => '0');
+    for i in 0 to g_num_outputs loop
+      aligner_sample_ack(i)     <= regs_in.al_cr_valid_o(i) and regs_in.al_cr_valid_load_o;
+      regs_out.al_cr_valid_i(i) <= aligner_sample_valid(i);
+    end loop;  -- i in 0 to g_num_outputs
+  end process;
+
+  p_mux_aligner_samples: process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        for i in 0 to g_num_outputs loop
+          if(aligner_sample_ack(i) = '1') then
+            regs_out.al_cref_i <= resize( aligner_sample_cref(i), 32 );
+            regs_out.al_cin_i <= resize( aligner_sample_cin(i), 32 );
+          end if;
+        end loop;
+      end if;
+    end process;
+
+  
+  U_WB_SLAVE : spll_wb_slave
+    generic map (
+      g_with_debug_fifo => f_pick(g_with_debug_fifo, 1, 0))
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      wb_adr_i   => wb_in.adr(5 downto 0),
+      wb_dat_i   => wb_in.dat,
+      wb_dat_o   => wb_out.dat,
+      wb_cyc_i   => wb_in.cyc,
+      wb_sel_i   => wb_in.sel,
+      wb_stb_i   => wb_in.stb,
+      wb_we_i    => wb_in.we,
+      wb_ack_o   => wb_out.ack,
+      wb_int_o   => wb_irq_out,
+      wb_stall_o => open,
+
+      regs_o => regs_in,
+      regs_i => regs_out,
+
+      irq_tag_i => irq_tag);
+
+    -- drive unused outputs
+    wb_out.err   <= '0';
+    wb_out.rty   <= '0';
+    wb_out.stall <= '0';
+    wb_out.int   <= '0';
+
+  p_ocer_rcer_regs : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        ocer_int <= (others => '0');
+        rcer_int <= (others => '0');
+      else
+        if(regs_in.ocer_load_o = '1') then
+          ocer_int <= regs_in.ocer_o(g_num_outputs -1 downto 0);
+        end if;
+
+        if(regs_in.rcer_load_o = '1') then
+          rcer_int <= regs_in.rcer_o(g_num_ref_inputs -1 downto 0);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  regs_out.ocer_i(g_num_outputs-1 downto 0) <= ocer_int;
+  regs_out.ocer_i(7 downto g_num_outputs)   <= (others => '0');
+
+  regs_out.rcer_i(g_num_ref_inputs-1 downto 0) <= rcer_int;
+  regs_out.rcer_i(31 downto g_num_ref_inputs)  <= (others => '0');
+
+  p_latch_tags : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i = '0') then
+        tags_req   <= (others => '0');
+        tags_grant <= (others => '0');
+      else
+        f_rr_arbitrate(tags_req, tags_grant, tags_grant);
+
+        for i in 0 to g_num_ref_inputs-1 loop
+          if(tags_p(i) = '1') then
+            tags_req(i) <= rcer_int(i);
+          elsif(tags_grant(i) = '1') then
+            tags_req(i) <= '0';
+          end if;
+        end loop;  -- i
+
+        for i in 0 to g_num_outputs-1 loop
+          if(tags_p(i + g_num_ref_inputs) = '1') then
+            tags_req(i + g_num_ref_inputs) <= ocer_int(i);
+          elsif(tags_grant(i + g_num_ref_inputs) = '1') then
+            tags_req(i + g_num_ref_inputs) <= '0';
+          end if;
+        end loop;  -- i
+
+        if(g_with_ext_clock_input and tags_p(f_num_total_channels-1) = '1') then
+          tags_req(f_num_total_channels-1) <= regs_in.eccr_ext_en_o;
+        elsif(g_with_ext_clock_input and tags_grant(f_num_total_channels-1) = '1') then
+          tags_req(f_num_total_channels-1) <= '0';
+        end if;
+        
+      end if;
+    end if;
+  end process;
+
+  tags_grant_p <= tags_req and tags_grant;
+
+  p_mux_tags : process(clk_sys_i)
+    variable muxed  : std_logic_vector(g_tag_bits-1 downto 0);
+    variable src_id : std_logic_vector(5 downto 0);
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        tag_muxed     <= (others => '0');
+        tag_src_pre   <= (others => '0');
+        tag_src       <= (others => '0');
+        tag_valid_pre <= '0';
+        tag_valid     <= '0';
+      else
+        
+        for i in 0 to f_num_total_channels-1 loop
+          if(tags_grant_p(i) = '1') then
+            tags_masked(i) <= tags(i);
+          else
+            tags_masked(i) <= (others => '0');
+          end if;
+        end loop;  -- i
+
+        if(unsigned(tags_grant_p) /= 0) then
+          tag_valid_pre <= '1';
+        else
+          tag_valid_pre <= '0';
+        end if;
+
+        tag_valid <= tag_valid_pre;
+
+        tag_src_pre <= f_onehot_decode(tags_grant_p, tag_src_pre'length);
+        tag_src     <= tag_src_pre;
+
+        muxed := (others => '0');
+
+        for i in 0 to f_num_total_channels-1 loop
+          muxed := muxed or tags_masked(i);
+        end loop;
+
+        tag_muxed <= muxed;
+        
+      end if;
+    end if;
+  end process;
+
+  regs_out.trr_wr_req_i  <= tag_valid and not regs_in.trr_wr_full_o;
+  regs_out.trr_chan_id_i <= '0'&tag_src;
+
+  regs_out.trr_value_i(g_tag_bits-1 downto 0) <= tag_muxed;
+  regs_out.trr_value_i(23 downto g_tag_bits)  <= (others => '0');
+  
+  regs_out.occr_out_en_i(g_num_outputs-1 downto 0) <= out_enable_i;
+  regs_out.occr_out_en_i(7 downto g_num_outputs)   <= (others => '0');
+
+  out_locked_o <= regs_in.occr_out_lock_o(g_num_outputs-1 downto 0);
+
+  irq_tag <= not regs_in.trr_wr_empty_o;
+
+  deglitch_thr_slv <= regs_in.deglitch_thr_o;
+
+
+
+  -----------------------------------------------------------------------------
+  -- Debugging FIFO
+  -----------------------------------------------------------------------------
+
+  gen_with_debug_fifo : if(g_with_debug_fifo = true) generate
+    
+    dbg_fifo_almostfull <= '1' when unsigned(regs_in.dfr_host_wr_usedw_o) > 8180 else '0';
+
+    p_request_counter : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_n_i = '0' then
+          dbg_seq_id <= (others => '0');
+        else
+          if(regs_in.dfr_spll_eos_o = '1' and regs_in.dfr_spll_eos_wr_o = '1') then
+            dbg_seq_id <= dbg_seq_id + 1;
+          end if;
+        end if;
+      end if;
+    end process;
+
+    p_fifo_permit_write : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_n_i = '0' then
+          dbg_fifo_permit_write <= '1';
+        else
+          if(dbg_fifo_almostfull = '0') then
+            dbg_fifo_permit_write <= '1';
+          elsif(regs_in.dfr_spll_eos_o = '1' and regs_in.dfr_spll_eos_wr_o = '1') then
+            dbg_fifo_permit_write <= '0';
+          end if;
+        end if;
+      end if;
+    end process;
+
+    p_coalesce_fifo_irq : process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_n_i = '0' then
+          dbg_fifo_irq <= '0';
+        else
+          if(unsigned(regs_in.dfr_host_wr_usedw_o) = 0) then
+            dbg_fifo_irq <= '0';
+          elsif(unsigned(regs_in.dfr_host_wr_usedw_o) = c_DBG_FIFO_COALESCE) then
+            dbg_fifo_irq <= '1';
+          end if;
+        end if;
+      end if;
+    end process;
+
+    regs_out.dfr_host_wr_req_i <= regs_in.dfr_spll_value_wr_o and dbg_fifo_permit_write;
+    regs_out.dfr_host_value_i  <= regs_in.dfr_spll_eos_o & regs_in.dfr_spll_value_o;
+    regs_out.dfr_host_seq_id_i <= std_logic_vector(dbg_seq_id);
+
+  end generate gen_with_debug_fifo;
+
+  gen_without_debug_fifo : if(g_with_debug_fifo = false) generate
+    dbg_fifo_irq               <= '0';
+    regs_out.dfr_host_wr_req_i <= '0';
+    regs_out.dfr_host_value_i  <= (others => '0');
+    regs_out.dfr_host_seq_id_i <= (others => '0');
+  end generate gen_without_debug_fifo;
+
+  dbg_fifo_irq_o <= dbg_fifo_irq;
+
+  -----------------------------------------------------------------------------
+  -- CSR N_OUT/N_REF fields
+  -----------------------------------------------------------------------------
+
+  regs_out.csr_n_ref_i <= std_logic_vector(to_unsigned(g_num_ref_inputs, regs_out.csr_n_ref_i'length));
+  regs_out.csr_n_out_i <= std_logic_vector(to_unsigned(g_num_outputs, regs_out.csr_n_out_i'length));
+
+  dac_dmtd_load_o <= regs_in.dac_hpll_wr_o;
+  dac_dmtd_data_o <= regs_in.dac_hpll_o;
+
+  dac_out_data_o <= regs_in.dac_main_value_o;
+  dac_out_sel_o  <= regs_in.dac_main_dac_sel_o;
+  dac_out_load_o <= regs_in.dac_main_value_wr_o;
+
+  wb_irq_o <= wb_irq_out;
+
+  regs_out.al_cr_required_i    <= (others => '0');
+  regs_out.csr_dbg_supported_i <= '0';
+  regs_out.f_dmtd_valid_i      <= '0';
+  regs_out.f_ref_valid_i       <= '0';
+  regs_out.f_ext_valid_i       <= '0';
+  regs_out.trr_disc_i          <= '0';
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/xwr_softpll_ng.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/xwr_softpll_ng.vhd
new file mode 100644
index 000000000..ea3b6ab63
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/xwr_softpll_ng.vhd
@@ -0,0 +1,244 @@
+-------------------------------------------------------------------------------
+-- Title      : White Rabbit Softcore PLL (new generation) - SoftPLL-ng
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : xwr_softpll_ng.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-29
+-- Last update: 2017-02-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: 
+--
+-- Struct'ized version of wr_softpll_ng.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wishbone_pkg.all;
+use work.softpll_pkg.all;
+
+entity xwr_softpll_ng is
+  generic(
+-- Number of bits in phase tags produced by DDMTDs.
+-- Must be large enough to cover at least a hundred of DDMTD periods to ensure
+-- correct operation of the SoftPLL software servo algorithm - that
+-- means, for a typical DMTD frequency offset N=16384, there number of tag bits
+-- should be log2(N) + 7 == 21. Note: the value must match the TAG_BITS constant
+-- in spll_defs.h file!
+    g_tag_bits : integer;
+
+-- These two are obvious:
+    g_num_ref_inputs : integer := 1;
+    g_num_outputs    : integer := 1;
+
+-- When true, an additional FIFO is instantiated, providing a realtime record
+-- of user-selectable SoftPLL parameters (e.g. tag values, phase error, DAC drive).
+-- These values can be read by "spll_dbg_proxy" daemon for further analysis.
+    g_with_debug_fifo : boolean := false;
+
+-- When true, an additional accumulating bang-bang phase detector is instantiated
+-- for wideband locking of the local oscillator to an external stable reference
+-- (e.g. GPSDO/Cesium 10 MHz)
+    g_with_ext_clock_input : boolean := false;
+
+-- When true, DDMTD inputs are reverse (so that the DDMTD offset clocks is
+-- being sampled by the measured clock). This is functionally equivalent to
+-- "direct" operation, but may improve FPGA timing/routability.
+    g_reverse_dmtds : boolean := true;
+
+-- Divides the DDMTD clock inputs by 2, removing the "CLOCK_DEDICATED_ROUTE"
+-- errors under ISE tools, at the cost of bandwidth reduction. Use with care.
+    g_divide_input_by_2 : boolean := false;
+
+    g_ref_clock_rate : integer := 125000000;
+    g_ext_clock_rate : integer := 10000000;
+
+    g_interface_mode      : t_wishbone_interface_mode      := PIPELINED;
+    g_address_granularity : t_wishbone_address_granularity := BYTE
+    );
+
+  port(
+    clk_sys_i    : in std_logic;
+    rst_sys_n_i  : in std_logic;
+    rst_ref_n_i  : in std_logic;
+    rst_ext_n_i  : in std_logic;
+    rst_dmtd_n_i : in std_logic;
+
+-- Reference inputs (i.e. the RX clocks recovered by the PHYs)
+    clk_ref_i  : in std_logic_vector(g_num_ref_inputs-1 downto 0);
+-- Feedback clocks (i.e. the outputs of the main or aux oscillator)
+    clk_fb_i   : in std_logic_vector(g_num_outputs-1 downto 0);
+-- DMTD Offset clock
+    clk_dmtd_i : in std_logic;
+
+-- External reference clock (e.g. 10 MHz from Cesium/GPSDO). Used only if
+-- g_with_ext_clock_input == true
+    clk_ext_i : in std_logic;
+
+-- External clock, multiplied to 125 MHz using the FPGA's PLL
+    clk_ext_mul_i : in std_logic;
+    clk_ext_mul_locked_i : in std_logic := '1';
+    clk_ext_stopped_i    : in std_logic := '0';
+    clk_ext_rst_o        : out std_logic;
+
+-- External clock sync/alignment singnal. SoftPLL will clk_ext_i/clk_fb_i(0)
+-- to match the edges immediately following the rising edge in sync_p_i.
+    pps_csync_p1_i : in std_logic;
+
+    pps_ext_a_i : in std_logic;
+
+-- DMTD oscillator drive
+    dac_dmtd_data_o : out std_logic_vector(15 downto 0);
+    dac_dmtd_load_o : out std_logic;
+
+-- Output channel DAC value
+    dac_out_data_o : out std_logic_vector(15 downto 0);
+-- Output channel select (0 = channel 0, etc. )
+    dac_out_sel_o  : out std_logic_vector(3 downto 0);
+    dac_out_load_o : out std_logic;
+
+    out_enable_i : in  std_logic_vector(g_num_outputs-1 downto 0);
+    out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
+
+    slave_i : in  t_wishbone_slave_in;
+    slave_o : out t_wishbone_slave_out;
+
+    debug_o        : out std_logic_vector(5 downto 0);
+    dbg_fifo_irq_o : out std_logic
+    );
+
+end xwr_softpll_ng;
+
+architecture wrapper of xwr_softpll_ng is
+  component wr_softpll_ng
+    generic (
+      g_tag_bits             : integer;
+      g_num_ref_inputs       : integer;
+      g_num_outputs          : integer;
+      g_with_debug_fifo      : boolean;
+      g_with_ext_clock_input : boolean;
+      g_reverse_dmtds        : boolean;
+      g_divide_input_by_2    : boolean;
+      g_ref_clock_rate       : integer;
+      g_ext_clock_rate       : integer;
+      g_interface_mode       : t_wishbone_interface_mode;
+      g_address_granularity  : t_wishbone_address_granularity);
+    port (
+      clk_sys_i       : in  std_logic;
+      rst_sys_n_i     : in std_logic;
+      rst_ref_n_i     : in std_logic;
+      rst_ext_n_i     : in std_logic;
+      rst_dmtd_n_i    : in std_logic;
+      clk_ref_i       : in  std_logic_vector(g_num_ref_inputs-1 downto 0);
+      clk_fb_i        : in  std_logic_vector(g_num_outputs-1 downto 0);
+      clk_dmtd_i      : in  std_logic;
+      clk_ext_i       : in  std_logic;
+      clk_ext_mul_i   : in  std_logic;
+      clk_ext_mul_locked_i : in  std_logic;
+      clk_ext_stopped_i    : in  std_logic;
+      clk_ext_rst_o        : out std_logic;
+      pps_csync_p1_i  : in  std_logic;
+      pps_ext_a_i     : in  std_logic;
+      dac_dmtd_data_o : out std_logic_vector(15 downto 0);
+      dac_dmtd_load_o : out std_logic;
+      dac_out_data_o  : out std_logic_vector(15 downto 0);
+      dac_out_sel_o   : out std_logic_vector(3 downto 0);
+      dac_out_load_o  : out std_logic;
+      out_enable_i    : in  std_logic_vector(g_num_outputs-1 downto 0);
+      out_locked_o    : out std_logic_vector(g_num_outputs-1 downto 0);
+
+      wb_adr_i   : in  std_logic_vector(c_wishbone_address_width-1 downto 0);
+      wb_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+      wb_stb_i        : in  std_logic;
+      wb_we_i         : in  std_logic;
+      wb_ack_o        : out std_logic;
+      wb_stall_o      : out std_logic;
+      wb_irq_o        : out std_logic;
+      debug_o         : out std_logic_vector(5 downto 0);
+      dbg_fifo_irq_o  : out std_logic);
+  end component;
+  
+begin  -- behavioral
+
+  U_Wrapped_Softpll : wr_softpll_ng
+    generic map (
+      g_tag_bits             => g_tag_bits,
+      g_interface_mode       => g_interface_mode,
+      g_address_granularity  => g_address_granularity,
+      g_num_ref_inputs       => g_num_ref_inputs,
+      g_num_outputs          => g_num_outputs,
+      g_with_debug_fifo      => g_with_debug_fifo,
+      g_with_ext_clock_input => g_with_ext_clock_input,
+      g_reverse_dmtds        => g_reverse_dmtds,
+      g_divide_input_by_2    => g_divide_input_by_2,
+      g_ref_clock_rate  => g_ref_clock_rate,
+      g_ext_clock_rate  => g_ext_clock_rate
+      )
+    port map (
+      clk_sys_i       => clk_sys_i,
+      rst_sys_n_i     => rst_sys_n_i,
+      rst_ref_n_i     => rst_ref_n_i,
+      rst_ext_n_i     => rst_ext_n_i,
+      rst_dmtd_n_i    => rst_dmtd_n_i,
+      clk_ref_i       => clk_ref_i,
+      clk_fb_i        => clk_fb_i,
+      clk_dmtd_i      => clk_dmtd_i,
+      clk_ext_i       => clk_ext_i,
+      clk_ext_mul_i   => clk_ext_mul_i,
+      clk_ext_mul_locked_i => clk_ext_mul_locked_i,
+      clk_ext_stopped_i => clk_ext_stopped_i,
+      clk_ext_rst_o     => clk_ext_rst_o,
+      pps_csync_p1_i  => pps_csync_p1_i,
+      pps_ext_a_i     => pps_ext_a_i,
+      dac_dmtd_data_o => dac_dmtd_data_o,
+      dac_dmtd_load_o => dac_dmtd_load_o,
+      dac_out_data_o  => dac_out_data_o,
+      dac_out_sel_o   => dac_out_sel_o,
+      dac_out_load_o  => dac_out_load_o,
+      out_enable_i    => out_enable_i,
+      out_locked_o    => out_locked_o,
+      wb_adr_i        => slave_i.adr,
+      wb_dat_i        => slave_i.dat,
+      wb_dat_o        => slave_o.dat,
+      wb_cyc_i        => slave_i.cyc,
+      wb_sel_i        => slave_i.sel,
+      wb_stb_i        => slave_i.stb,
+      wb_we_i         => slave_i.we,
+      wb_ack_o        => slave_o.ack,
+      wb_stall_o      => slave_o.stall,
+      wb_irq_o        => slave_o.int,
+      debug_o         => debug_o,
+      dbg_fifo_irq_o  => dbg_fifo_irq_o);
+
+  slave_o.err <= '0';
+  slave_o.rty <= '0';
+  
+end wrapper;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/dropping_buffer.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/dropping_buffer.vhd
new file mode 100644
index 000000000..364ba970f
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/dropping_buffer.vhd
@@ -0,0 +1,142 @@
+-------------------------------------------------------------------------------
+-- Title      : Dropping buffer
+-- Project    : WR Stramers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : dropping_buffer.vhd
+-- Author     : Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-- Created    : 2012-11-02
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- A FIFO that can be cleared fast
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.genram_pkg.all; -- needed for f_log2_size()
+
+entity dropping_buffer is
+  generic (
+    g_size       : integer;
+    g_data_width : integer);
+
+  port
+    (
+      clk_i   : in std_logic;
+      rst_n_i : in std_logic;
+
+      d_i        : in  std_logic_vector(g_data_width-1 downto 0);
+      d_req_o    : out std_logic;
+      d_drop_i   : in  std_logic;
+      d_accept_i : in  std_logic;
+      d_valid_i  : in  std_logic;
+
+      d_o       : out std_logic_vector(g_data_width-1 downto 0);
+      d_valid_o : out std_logic;
+      d_req_i   : in  std_logic);
+
+
+end dropping_buffer;
+
+architecture behavioral of dropping_buffer is
+
+  type    t_mem_array is array(0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
+  subtype t_counter is unsigned(f_log2_size(g_size)-1 downto 0);
+
+  signal wr_ptr, rd_ptr, boundary : t_counter := (others => '0');
+  signal full, empty_comb         : std_logic;
+  signal empty_reg                : std_logic := '0';
+  signal mem                      : t_mem_array;
+  
+begin  -- behavioral
+
+  p_counters : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        wr_ptr   <= (others => '0');
+        rd_ptr   <= (others => '0');
+        boundary <= (others => '0');
+      else
+        if(d_accept_i = '1') then
+          boundary <= wr_ptr;
+        end if;
+
+        if(d_drop_i = '1') then
+          wr_ptr <= boundary;
+        elsif(d_valid_i = '1' and full = '0') then
+          wr_ptr <= wr_ptr + 1;
+        end if;
+
+        if (d_req_i = '1' and empty_reg = '0' and empty_comb = '0') then
+          rd_ptr <= rd_ptr + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  empty_comb <= '1' when (boundary = rd_ptr)   else '0';
+  full       <= '1' when (wr_ptr + 1 = rd_ptr) else '0';
+
+  d_req_o <= not full;
+
+  p_empty_reg : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        empty_reg <= '1';
+      else
+        empty_reg <= empty_comb;
+      end if;
+    end if;
+  end process;
+
+
+  p_mem_read : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if(d_req_i = '1' and empty_reg = '0' and empty_comb = '0') then
+        d_o       <= mem(to_integer(rd_ptr));
+        d_valid_o <= '1';
+      else
+        d_o       <= (others => '0');
+        d_valid_o <= '0';
+      end if;
+    end if;
+  end process;
+
+  p_mem_write : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if(d_valid_i = '1') then
+        mem(to_integer(wr_ptr)) <= d_i;
+      end if;
+    end if;
+  end process;
+  
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/escape_detector.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/escape_detector.vhd
new file mode 100644
index 000000000..bdf112f7a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/escape_detector.vhd
@@ -0,0 +1,106 @@
+-------------------------------------------------------------------------------
+-- Title      : Escape detecotr
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : escape_detector.vhd
+-- Author     : Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-- Created    : 2012-10-01
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- It detects the "escape code" (e.g.0xCAFE) and removes it from the data stream.
+-- See escape_inserter for details
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity escape_detector is
+  generic(
+    g_data_width  : integer;
+    g_escape_code : std_logic_vector
+    );
+  port(
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+
+    d_i               : in  std_logic_vector(g_data_width-1 downto 0);
+    d_detect_enable_i : in  std_logic;
+    d_valid_i         : in  std_logic;
+    d_req_o           : out std_logic;
+
+    d_o        : out std_logic_vector(g_data_width-1 downto 0);
+    d_escape_o : out std_logic;
+    d_valid_o  : out std_logic;
+    d_req_i    : in  std_logic
+    );
+
+end escape_detector;
+
+architecture behavioral of escape_detector is
+
+  type t_state is (IDLE, CHECK_ESCAPE);
+
+  signal state          : t_state;
+  signal is_escape_code : std_logic;
+  
+begin  -- behavioral
+
+  d_req_o <= d_req_i;
+
+  is_escape_code <= '1' when (d_detect_enable_i = '1' and state = IDLE and d_valid_i = '1' and d_i = g_escape_code) else '0';
+
+  d_o <= g_escape_code when (state = CHECK_ESCAPE and d_i = x"0000") else d_i;
+
+  d_valid_o  <= d_valid_i and not is_escape_code;
+  d_escape_o <= '1' when (state = CHECK_ESCAPE and d_i /= x"0000") else '0';
+
+  p_fsm : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' or d_detect_enable_i = '0' then
+        state <= IDLE;
+      else
+        case state is
+          when IDLE =>
+            if(d_i = g_escape_code and d_valid_i = '1') then
+              state <= CHECK_ESCAPE;
+
+            end if;
+
+          when CHECK_ESCAPE =>
+            if(d_valid_i = '1') then
+              state <= IDLE;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+end behavioral;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/escape_inserter.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/escape_inserter.vhd
new file mode 100644
index 000000000..e289a060d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/escape_inserter.vhd
@@ -0,0 +1,141 @@
+-------------------------------------------------------------------------------
+-- Title      : Escape insertion unit
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : gc_escape_inserter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-10-01
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+------------------------------------------------------------------------------
+-- Description: Unit for inserting escaped codes in a continuous data stream.
+-- Allows for insertion of easily distinguishable control codes, such as start-
+-- or end-of-frame markers. Given an input tuple (E[d_escape_i], D[d_i]), the
+-- output (d_o) is:
+-- - D when E == 0 and D != g_escape_code
+-- - g_escape_code followed by 0 when E == 0 and D == g_escape_code
+-- - g_escape_code followed by D when E == 1.
+-- Note: When E == 1, D must not be 0.
+------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity gc_escape_inserter is
+  generic(
+    -- data path width
+    g_data_width  : integer;
+    -- unique escape character (of g_data_width bits), must not be 0.
+    g_escape_code : std_logic_vector
+    );
+  port(
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    -- data input (unescaped)
+    d_i               : in  std_logic_vector(g_data_width-1 downto 0);
+
+    -- when 1, escape insertion logic is enabled (i.e. if d_i == g_escape_code,
+    -- it's translated to g_escape_code followed by 0 instead of just being passed
+    -- through
+    d_insert_enable_i : in  std_logic;
+
+    -- when 1, d_i is treated as a escaped character
+    d_escape_i        : in  std_logic;
+
+    -- when 1, d_i and d_escape_i contain valid character
+    d_valid_i         : in  std_logic;
+
+    -- when 1, module can accept data in the following clock cycle.
+    d_req_o           : out std_logic;
+
+    -- data output
+    d_o       : out std_logic_vector (g_data_width-1 downto 0);
+
+    -- when 1, d_o contains a valid character
+    d_valid_o : out std_logic;
+
+    -- when 1, d_o/d_valid_o may output a character in the next clock cycle.
+    d_req_i   : in  std_logic
+    );
+
+end gc_escape_inserter;
+
+architecture behavioral of gc_escape_inserter is
+
+  type t_state is (IDLE, INSERT_ESCAPE);
+
+  signal d_prev     : std_logic_vector(g_data_width-1 downto 0);
+  signal d_req_prev : std_logic;
+  signal state      : t_state;
+  signal match_esc_code : std_logic;
+  
+begin  -- behavioral
+
+  match_esc_code <= '1' when d_i = g_escape_code else '0';
+
+  -- stop the traffic if we need to insert an escaped sequence. This
+  -- can happen when
+  -- - the input character is an escape code (d_escape_i = '1')
+  -- - the input character is not to be escaped, but it's equal to g_escape_code
+  d_req_o <= d_req_i and not (d_valid_i and (d_escape_i or match_esc_code));
+
+  d_o <= d_prev when (state = INSERT_ESCAPE) else
+         d_i when d_escape_i = '0' else
+         g_escape_code;
+  
+  d_valid_o <= d_valid_i when (state = IDLE) else
+               d_req_prev;
+
+  p_fsm : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' or d_insert_enable_i = '0' then
+        state      <= IDLE;
+        d_req_prev <= '0';
+      else
+        d_req_prev <= d_req_i;
+        case state is
+          when IDLE =>
+            -- case 1: escape the escape character sent as normal character
+            if(d_i = g_escape_code and d_valid_i = '1' and d_escape_i = '0') then
+              state  <= INSERT_ESCAPE;
+              d_prev <= x"0000";
+            -- case 2: send an escaped character
+            elsif(d_escape_i = '1' and d_valid_i = '1') then
+              state  <= INSERT_ESCAPE;
+              d_prev <= d_i;
+            end if;
+            
+          when INSERT_ESCAPE =>
+            if(d_req_prev = '1') then
+              state <= IDLE;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/streamers_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/streamers_pkg.vhd
new file mode 100644
index 000000000..b4fa5a289
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/streamers_pkg.vhd
@@ -0,0 +1,332 @@
+-------------------------------------------------------------------------------
+-- Title      : Package for WR Steamers
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : streamers_pkg.vhd
+-- Author     : Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-- Created    : 2012-10-01
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- Package with declaration of streamer components, types and constants.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.wr_fabric_pkg.all;
+use work.wrcore_pkg.all;
+use work.wishbone_pkg.all;  -- needed for t_wishbone_slave_in, etc
+
+package streamers_pkg is
+  type t_streamers_op_mode is (RX_ONLY, TX_ONLY, TX_AND_RX);
+  -----------------------------------------------------------------------------------------
+  -- Transmission parameters (tx)
+  -----------------------------------------------------------------------------------------
+  type t_tx_streamer_params is record
+    -- Width of data words on tx_data_i, must be multiple of 16 bits.
+    data_width            : integer;
+
+    -- Size of Tx buffer, in data words.
+    buffer_size           : integer;
+
+    -- Minimum number of data words in the TX buffer that will trigger transmission of an
+    -- Ethernet frame. It cannot be breater than g_tx_buffer_size; it is recommended that
+    -- g_tx_buffer_size = 2 * g_tx_threshold.
+    -- Note that in order for a frame to be transmitted, the buffer must conatain at
+    -- least one complete block.ransmitted, the buffer must conatain at
+    -- least one complete block.
+    threshold             : integer;
+
+    -- Maximum number of data words in a single Ethernet frame. It also defines
+    -- the maximum block size (since blocks can't be currently split across
+    -- multiple frames). It cannot be greater than g_tx_buffer_size
+    max_words_per_frame   : integer;
+
+    -- Transmission timeout (in clk_sys_i cycles), after which the contents
+    -- of TX buffer are sent regardless of the amount of data that is currently
+    -- stored in the buffer, so that data in the buffer does not get stuck.
+    timeout               : integer;
+
+    -- DO NOT USE unless you know what you are doing
+    -- legacy: the streamers initially used in Btrain did not check/insert the escape
+    -- code. This is justified if only one block of a known number of words is sent/expected
+    escape_code_disable   : boolean;
+  end record;
+
+  -----------------------------------------------------------------------------------------
+  -- Reception parameters (rx)
+  -----------------------------------------------------------------------------------------
+  type t_rx_streamer_params is record
+    -- Width of the data words, must be multiple of 16 bits. This value set to this generic
+    -- on the receviving device must be the same as the value of g_tx_data_width set on the
+    -- transmitting node. The g_rx_data_width and g_tx_data_width can be set to different
+    -- values in the same device (i.e. instantiation of xwr_transmission entity). It is the
+    -- responsibility of a network designer to make sure these parameters are properly set 
+    -- in the network.
+    data_width            : integer;
+
+    -- Size of RX buffer, in data words.
+    buffer_size           : integer;
+
+    -- DO NOT USE unless you know what you are doing
+    -- legacy: the streamers that were initially used in Btrain did not check/insert 
+    -- the escape code. This is justified if only one block of a known number of words is 
+    -- sent/expected.
+    escape_code_disable   : boolean;
+
+    -- DO NOT USE unless you know what you are doing
+    -- legacy: the streamers that were initially used in Btrain accepted only a fixed
+    -- number of words, regardless of the frame content. If this generic is set to number
+    -- other than zero, only a fixed number of words is accepted. 
+    -- In combination with the g_escape_code_disable generic set to TRUE, the behaviour of
+    -- the "Btrain streamers" can be recreated.
+    expected_words_number : integer;
+  end record;
+
+  constant c_tx_streamer_params_defaut: t_tx_streamer_params :=(
+      data_width            => 32,
+      buffer_size           => 256,
+      threshold             => 128,
+      max_words_per_frame   => 256,
+      timeout               => 1024,
+      escape_code_disable   => FALSE);
+
+  constant c_rx_streamer_params_defaut: t_rx_streamer_params :=(
+      data_width            => 32,
+      buffer_size           => 256,
+      escape_code_disable   => FALSE,
+      expected_words_number => 0);
+
+  type t_rx_streamer_cfg is record
+    -- Local MAC address. Leave at 0x0...0 when using with the WR MAC/Core, it will
+    -- insert its own source MAC.
+    mac_local              : std_logic_vector(47 downto 0);
+    -- Remote MAC address, i.e. MAC of the device from which the data should be accpated
+    mac_remote             : std_logic_vector(47 downto 0);
+    -- Ethertype of our frames. Default value is accepted by standard
+    -- configuration of the WR PTP Core
+    ethertype              : std_logic_vector(15 downto 0);
+    -- 1: accept all broadcast packets
+    -- 0: accept only unicasts
+    accept_broadcasts      : std_logic;
+    -- filtering of streamer frames on reception by source MAC address
+    -- 0: accept frames from any source
+    -- 1: accept frames only from the source MAC address defined in cfg_mac_remote_i
+    filter_remote          : std_logic;
+    -- value in cycles of fixed-latency enforced on data
+    fixed_latency          : std_logic_vector(27 downto 0);
+  end record;
+
+  type t_tx_streamer_cfg is record
+    -- Local MAC address. Leave at 0x0...0 when using with the WR MAC/Core, it will
+    -- insert its own source MAC.
+    mac_local              : std_logic_vector(47 downto 0);
+    -- Destination MAC address, i.e. MAC of a device to which data is streamed.
+    mac_target             : std_logic_vector(47 downto 0);
+    -- Ethertype of our frames. Default value is accepted by standard
+    -- configuration of the WR PTP Core
+    ethertype              : std_logic_vector(15 downto 0);
+    -- enable tagging with VLAN tags
+    qtag_ena               : std_logic;
+    ---VLAN used to tag
+    qtag_vid               : std_logic_vector(11 downto 0);
+    -- priority used to tag
+    qtag_prio              : std_logic_vector(2  downto 0);
+  end record;
+
+  constant c_rx_streamer_cfg_default: t_rx_streamer_cfg :=(
+    mac_local              => x"000000000000",
+    mac_remote             => x"000000000000",
+    ethertype              => x"dbff",
+    accept_broadcasts      => '1',
+    filter_remote          => '0',
+    fixed_latency          => x"0000000");
+
+  constant c_tx_streamer_cfg_default: t_tx_streamer_cfg :=(
+    mac_local              => x"000000000000",
+    mac_target             => x"ffffffffffff",
+    ethertype              => x"dbff",
+    qtag_ena               => '0',
+    qtag_vid               => x"000",
+    qtag_prio              => "000");
+
+  component xtx_streamer
+    generic (
+      g_data_width             : integer := 32;
+      g_tx_buffer_size         : integer := 256;
+      g_tx_threshold           : integer := 128;
+      g_tx_max_words_per_frame : integer := 256;
+      g_tx_timeout             : integer := 1024;
+      g_escape_code_disable    : boolean := FALSE;
+      g_simulation             : integer := 0;
+      g_sim_startup_cnt        : integer := 6250);--100us
+    port (
+      clk_sys_i        : in  std_logic;
+      rst_n_i          : in  std_logic;
+      src_i            : in  t_wrf_source_in;
+      src_o            : out t_wrf_source_out;
+      clk_ref_i        : in  std_logic                     := '0';
+      tm_time_valid_i  : in  std_logic                     := '0';
+      tm_tai_i         : in  std_logic_vector(39 downto 0) := x"0000000000";
+      tm_cycles_i      : in  std_logic_vector(27 downto 0) := x"0000000";
+      link_ok_i        : in  std_logic                     := '1';
+      tx_data_i        : in  std_logic_vector(g_data_width-1 downto 0);
+      tx_valid_i       : in  std_logic;
+      tx_dreq_o        : out std_logic;
+      tx_last_p1_i     : in  std_logic                     := '1';
+      tx_flush_p1_i    : in  std_logic                     := '0';
+      tx_reset_seq_i   : in  std_logic                     := '0';
+      tx_frame_p1_o    : out std_logic;
+      tx_streamer_cfg_i: in t_tx_streamer_cfg := c_tx_streamer_cfg_default);
+  end component;
+  
+  component xrx_streamer
+    generic (
+      g_data_width        : integer := 32;
+      g_buffer_size       : integer := 256;
+      g_escape_code_disable : boolean := FALSE;
+      g_expected_words_number : integer := 0);
+    port (
+      clk_sys_i               : in  std_logic;
+      rst_n_i                 : in  std_logic;
+      snk_i                   : in  t_wrf_sink_in;
+      snk_o                   : out t_wrf_sink_out;
+      clk_ref_i               : in  std_logic                     := '0';
+      tm_time_valid_i         : in  std_logic                     := '0';
+      tm_tai_i                : in  std_logic_vector(39 downto 0) := x"0000000000";
+      tm_cycles_i             : in  std_logic_vector(27 downto 0) := x"0000000";
+      rx_first_p1_o           : out std_logic;
+      rx_last_p1_o            : out std_logic;
+      rx_data_o               : out std_logic_vector(g_data_width-1 downto 0);
+      rx_valid_o              : out std_logic;
+      rx_dreq_i               : in  std_logic;
+      rx_lost_p1_o            : out std_logic := '0';
+      rx_lost_blocks_p1_o     : out std_logic := '0';
+      rx_lost_frames_p1_o     : out std_logic := '0';
+      rx_lost_frames_cnt_o    : out std_logic_vector(14 downto 0);
+      rx_latency_o            : out std_logic_vector(27 downto 0);
+      rx_latency_valid_o      : out std_logic;
+      rx_frame_p1_o           : out std_logic;
+      rx_streamer_cfg_i       : in t_rx_streamer_cfg := c_rx_streamer_cfg_default);
+  end component;
+
+  constant c_WRS_STATS_ARR_SIZE_OUT : integer := 18;
+  constant c_WRS_STATS_ARR_SIZE_IN  : integer := 1;
+
+  component xrtx_streamers_stats is
+    generic (
+      g_streamers_op_mode    : t_streamers_op_mode  := TX_AND_RX;
+      g_cnt_width            : integer := 50;
+      g_acc_width            : integer := 64
+      );
+    port (
+      clk_i                  : in std_logic;
+      rst_n_i                : in std_logic;
+      sent_frame_i           : in std_logic;
+      rcvd_frame_i           : in std_logic;
+      lost_block_i           : in std_logic;
+      lost_frame_i           : in std_logic;
+      lost_frames_cnt_i      : in std_logic_vector(14 downto 0);
+      rcvd_latency_i         : in  std_logic_vector(27 downto 0);
+      rcvd_latency_valid_i   : in  std_logic;
+      clk_ref_i              : in std_logic;
+      tm_time_valid_i        : in std_logic := '0';
+      tm_tai_i               : in std_logic_vector(39 downto 0) := x"0000000000";
+      tm_cycles_i            : in std_logic_vector(27 downto 0) := x"0000000";
+      reset_stats_i          : in std_logic;
+      snapshot_ena_i         : in std_logic := '0';
+      reset_time_tai_o       : out std_logic_vector(39 downto 0) := x"0000000000";
+      reset_time_cycles_o    : out std_logic_vector(27 downto 0) := x"0000000";
+      sent_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+      rcvd_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+      lost_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+      lost_block_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+      latency_cnt_o          : out std_logic_vector(g_cnt_width-1 downto 0);
+      latency_acc_overflow_o : out std_logic;
+      latency_acc_o          : out std_logic_vector(g_acc_width-1  downto 0);
+      latency_max_o          : out std_logic_vector(27  downto 0);
+      latency_min_o          : out std_logic_vector(27  downto 0);
+      snmp_array_o           : out t_generic_word_array(c_WRS_STATS_ARR_SIZE_OUT-1 downto 0);
+      snmp_array_i           : in  t_generic_word_array(c_WRS_STATS_ARR_SIZE_IN -1 downto 0) := (others => (others=>'0'))
+      );
+  end component;
+
+  constant c_WR_STREAMERS_ARR_SIZE_OUT : integer := c_WRS_STATS_ARR_SIZE_OUT+2;
+  constant c_WR_STREAMERS_ARR_SIZE_IN  : integer := c_WRS_STATS_ARR_SIZE_IN;
+
+  component xwr_streamers is
+  generic (
+    g_streamers_op_mode        : t_streamers_op_mode  := TX_AND_RX;
+    --tx/rx
+    g_tx_streamer_params       : t_tx_streamer_params := c_tx_streamer_params_defaut;
+    g_rx_streamer_params       : t_rx_streamer_params := c_rx_streamer_params_defaut;
+    -- stats
+    g_stats_cnt_width          : integer := 50;
+    g_stats_acc_width          : integer := 64;
+    -- WB i/f
+    g_slave_mode               : t_wishbone_interface_mode      := CLASSIC;
+    g_slave_granularity        : t_wishbone_address_granularity := BYTE;
+    g_simulation               : integer := 0
+    );
+
+  port (
+    clk_sys_i                  : in std_logic;
+    rst_n_i                    : in std_logic;
+    -- WR tx/rx interface
+    src_i                      : in  t_wrf_source_in;
+    src_o                      : out t_wrf_source_out;
+    snk_i                      : in  t_wrf_sink_in;
+    snk_o                      : out t_wrf_sink_out;
+    -- User tx interface
+    tx_data_i                  : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0);
+    tx_valid_i                 : in std_logic;
+    tx_dreq_o                  : out std_logic;
+    tx_last_p1_i               : in std_logic := '1';
+    tx_flush_p1_i              : in std_logic := '0';
+    -- User rx interface
+    rx_first_p1_o              : out std_logic;
+    rx_last_p1_o               : out std_logic;
+    rx_data_o                  : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+    rx_valid_o                 : out std_logic;
+    rx_dreq_i                  : in  std_logic;
+    -- WRC Timing interface, used for latency measurement
+    clk_ref_i                  : in std_logic := '0';
+    tm_time_valid_i            : in std_logic := '0';
+    tm_tai_i                   : in std_logic_vector(39 downto 0) := x"0000000000";
+    tm_cycles_i                : in std_logic_vector(27 downto 0) := x"0000000";
+    link_ok_i                  : in std_logic := '1';
+    wb_slave_i                 : in  t_wishbone_slave_in := cc_dummy_slave_in;
+    wb_slave_o                 : out t_wishbone_slave_out;
+    snmp_array_o               : out t_generic_word_array(c_WR_STREAMERS_ARR_SIZE_OUT-1 downto 0);
+    snmp_array_i               : in  t_generic_word_array(c_WR_STREAMERS_ARR_SIZE_IN -1 downto 0);
+    -- Transmission (tx) configuration
+    tx_streamer_cfg_i          : in  t_tx_streamer_cfg := c_tx_streamer_cfg_default;
+    rx_streamer_cfg_i          : in  t_rx_streamer_cfg := c_rx_streamer_cfg_default
+    );
+  end component;
+
+end streamers_pkg;
\ No newline at end of file
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/streamers_priv_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/streamers_priv_pkg.vhd
new file mode 100644
index 000000000..42c9aae8a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/streamers_priv_pkg.vhd
@@ -0,0 +1,201 @@
+-------------------------------------------------------------------------------
+-- Title      : WR Streamers Private Packages
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : streamers_priv_pkg.vhd
+-- Author     : Maciej Lipinski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-- Created    : 2017-04-20
+-------------------------------------------------------------------------------
+-- Description:
+-- Private package of streamers: all the components/functions used only by
+-- streamers, not useful by users/applications
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2017 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.ALL;
+use work.wishbone_pkg.all;  -- needed for t_wishbone_slave_in, etc
+use work.streamers_pkg.all;
+use work.wr_streamers_wbgen2_pkg.all;
+
+package streamers_priv_pkg is
+
+  component xtx_streamers_stats is
+    generic (
+      g_cnt_width            : integer := 32);
+    port (
+      clk_i                  : in std_logic;
+      rst_n_i                : in std_logic;
+      sent_frame_i           : in std_logic;
+      reset_stats_i          : in std_logic;
+      snapshot_ena_i         : in std_logic := '0';
+      sent_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0));
+  end component;
+
+  component xrx_streamers_stats is
+    generic (
+      g_cnt_width            : integer := 32;
+      g_acc_width            : integer := 64);
+    port (
+      clk_i                  : in std_logic;
+      rst_n_i                : in std_logic;
+      rcvd_frame_i           : in std_logic;
+      lost_block_i           : in std_logic;
+      lost_frame_i           : in std_logic;
+      lost_frames_cnt_i      : in std_logic_vector(14 downto 0);
+      rcvd_latency_i         : in  std_logic_vector(27 downto 0);
+      rcvd_latency_valid_i   : in  std_logic;
+      tm_time_valid_i        : in  std_logic;
+      snapshot_ena_i         : in std_logic := '0';
+      reset_stats_i          : in std_logic;
+      rcvd_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+      lost_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+      lost_block_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+      latency_cnt_o          : out std_logic_vector(g_cnt_width-1 downto 0);
+      latency_acc_overflow_o : out std_logic;
+      latency_acc_o          : out std_logic_vector(g_acc_width-1  downto 0);
+      latency_max_o          : out std_logic_vector(27  downto 0);
+      latency_min_o          : out std_logic_vector(27  downto 0));
+  end component;
+
+  component  wr_streamers_wb is
+    port (
+      rst_n_i                                  : in     std_logic;
+      clk_sys_i                                : in     std_logic;
+      wb_adr_i                                 : in     std_logic_vector(5 downto 0);
+      wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+      wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+      wb_cyc_i                                 : in     std_logic;
+      wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+      wb_stb_i                                 : in     std_logic;
+      wb_we_i                                  : in     std_logic;
+      wb_ack_o                                 : out    std_logic;
+      wb_stall_o                               : out    std_logic;
+      regs_i                                   : in     t_wr_streamers_in_registers;
+      regs_o                                   : out    t_wr_streamers_out_registers
+    );
+  end component;
+
+  -- component from wr-core/modules/timing
+  component pulse_stamper
+    port (
+      clk_ref_i       : in  std_logic;
+      clk_sys_i       : in  std_logic;
+      rst_n_i         : in  std_logic;
+      pulse_a_i       : in  std_logic;
+      tm_time_valid_i : in  std_logic;
+      tm_tai_i        : in  std_logic_vector(39 downto 0);
+      tm_cycles_i     : in  std_logic_vector(27 downto 0);
+      tag_tai_o       : out std_logic_vector(39 downto 0);
+      tag_cycles_o    : out std_logic_vector(27 downto 0);
+      tag_valid_o     : out std_logic);
+  end component;
+
+  type t_pipe is record
+    dvalid  : std_logic;
+    dreq    : std_logic;
+    sof     : std_logic;
+    eof     : std_logic;
+    error   : std_logic;
+    data    : std_logic_vector(15 downto 0);
+    addr    : std_logic_vector(1 downto 0);
+    bytesel : std_logic;
+  end record;
+
+  component escape_detector
+    generic (
+      g_data_width  : integer;
+      g_escape_code : std_logic_vector);
+    port (
+      clk_i             : in  std_logic;
+      rst_n_i           : in  std_logic;
+      d_i               : in  std_logic_vector(g_data_width-1 downto 0);
+      d_detect_enable_i : in  std_logic;
+      d_valid_i         : in  std_logic;
+      d_req_o           : out std_logic;
+      d_o               : out std_logic_vector(g_data_width-1 downto 0);
+      d_escape_o        : out std_logic;
+      d_valid_o         : out std_logic;
+      d_req_i           : in  std_logic);
+  end component;
+
+  component dropping_buffer
+    generic (
+      g_size       : integer;
+      g_data_width : integer);
+    port (
+      clk_i      : in  std_logic;
+      rst_n_i    : in  std_logic;
+      d_i        : in  std_logic_vector(g_data_width-1 downto 0);
+      d_req_o    : out std_logic;
+      d_drop_i   : in  std_logic;
+      d_accept_i : in  std_logic;
+      d_valid_i  : in  std_logic;
+      d_o        : out std_logic_vector(g_data_width-1 downto 0);
+      d_valid_o  : out std_logic;
+      d_req_i    : in  std_logic);
+  end component;
+
+  component gc_escape_inserter
+    generic (
+      g_data_width  : integer;
+      g_escape_code : std_logic_vector);
+    port (
+      clk_i             : in  std_logic;
+      rst_n_i           : in  std_logic;
+      d_i               : in  std_logic_vector(g_data_width-1 downto 0);
+      d_insert_enable_i : in  std_logic;
+      d_escape_i        : in  std_logic;
+      d_valid_i         : in  std_logic;
+      d_req_o           : out std_logic;
+      d_o               : out std_logic_vector (g_data_width-1 downto 0);
+      d_valid_o         : out std_logic;
+      d_req_i           : in  std_logic);
+  end component;
+  -- functions
+  function f_dbg_word_starting_at_bit(data_in, start_bit : std_logic_vector; g_data_width: integer) return std_logic_vector;
+
+end streamers_priv_pkg;
+
+package body streamers_priv_pkg is
+
+  function f_dbg_word_starting_at_bit(data_in, start_bit : std_logic_vector; g_data_width: integer) return std_logic_vector is
+    variable sb     : integer := 0;
+    variable result : std_logic_vector(31 downto 0);
+  begin
+    sb     := to_integer(unsigned(start_bit));
+    for i in 0 to 31 loop
+      if (sb + i < g_data_width) then 
+        result(i) := data_in(sb + i);
+      else 
+        result(i) := '0';
+      end if;
+    end loop;
+    return result;
+  end f_dbg_word_starting_at_bit;
+
+end streamers_priv_pkg;
\ No newline at end of file
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/wr_streamers_wb.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/wr_streamers_wb.vhd
new file mode 100644
index 000000000..c18bc310a
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/wr_streamers_wb.vhd
@@ -0,0 +1,706 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Transmission control, status and debug
+---------------------------------------------------------------------------------------
+-- File           : wr_streamers_wb.vhd
+-- Author         : auto-generated by wbgen2 from wr_streamers_wb.wb
+-- Created        : Wed Aug 16 22:45:12 2017
+-- Version        : 0x00000001
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_streamers_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wr_streamers_wbgen2_pkg.all;
+
+
+entity wr_streamers_wb is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(5 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    regs_i                                   : in     t_wr_streamers_in_registers;
+    regs_o                                   : out    t_wr_streamers_out_registers
+  );
+end wr_streamers_wb;
+
+architecture syn of wr_streamers_wb is
+
+signal wr_streamers_ver_id_int                  : std_logic_vector(31 downto 0);
+signal wr_streamers_sscr1_rst_stats_dly0        : std_logic      ;
+signal wr_streamers_sscr1_rst_stats_int         : std_logic      ;
+signal wr_streamers_sscr1_rst_seq_id_dly0       : std_logic      ;
+signal wr_streamers_sscr1_rst_seq_id_int        : std_logic      ;
+signal wr_streamers_sscr1_snapshot_stats_int    : std_logic      ;
+signal wr_streamers_tx_cfg0_ethertype_int       : std_logic_vector(15 downto 0);
+signal wr_streamers_tx_cfg1_mac_local_lsb_int   : std_logic_vector(31 downto 0);
+signal wr_streamers_tx_cfg2_mac_local_msb_int   : std_logic_vector(15 downto 0);
+signal wr_streamers_tx_cfg3_mac_target_lsb_int  : std_logic_vector(31 downto 0);
+signal wr_streamers_tx_cfg4_mac_target_msb_int  : std_logic_vector(15 downto 0);
+signal wr_streamers_tx_cfg5_qtag_ena_int        : std_logic      ;
+signal wr_streamers_tx_cfg5_qtag_vid_int        : std_logic_vector(11 downto 0);
+signal wr_streamers_tx_cfg5_qtag_prio_int       : std_logic_vector(2 downto 0);
+signal wr_streamers_rx_cfg0_ethertype_int       : std_logic_vector(15 downto 0);
+signal wr_streamers_rx_cfg0_accept_broadcast_int : std_logic      ;
+signal wr_streamers_rx_cfg0_filter_remote_int   : std_logic      ;
+signal wr_streamers_rx_cfg1_mac_local_lsb_int   : std_logic_vector(31 downto 0);
+signal wr_streamers_rx_cfg2_mac_local_msb_int   : std_logic_vector(15 downto 0);
+signal wr_streamers_rx_cfg3_mac_remote_lsb_int  : std_logic_vector(31 downto 0);
+signal wr_streamers_rx_cfg4_mac_remote_msb_int  : std_logic_vector(15 downto 0);
+signal wr_streamers_rx_cfg5_fixed_latency_int   : std_logic_vector(27 downto 0);
+signal wr_streamers_cfg_or_tx_ethtype_int       : std_logic      ;
+signal wr_streamers_cfg_or_tx_mac_loc_int       : std_logic      ;
+signal wr_streamers_cfg_or_tx_mac_tar_int       : std_logic      ;
+signal wr_streamers_cfg_or_tx_qtag_int          : std_logic      ;
+signal wr_streamers_cfg_or_rx_ethertype_int     : std_logic      ;
+signal wr_streamers_cfg_or_rx_mac_loc_int       : std_logic      ;
+signal wr_streamers_cfg_or_rx_mac_rem_int       : std_logic      ;
+signal wr_streamers_cfg_or_rx_acc_broadcast_int : std_logic      ;
+signal wr_streamers_cfg_or_rx_ftr_remote_int    : std_logic      ;
+signal wr_streamers_cfg_or_rx_fix_lat_int       : std_logic      ;
+signal wr_streamers_dbg_ctrl_mux_int            : std_logic      ;
+signal wr_streamers_dbg_ctrl_start_byte_int     : std_logic_vector(7 downto 0);
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal rwaddr_reg                               : std_logic_vector(5 downto 0);
+signal ack_in_progress                          : std_logic      ;
+
+begin
+-- Some internal signals assignments
+  wrdata_reg <= wb_dat_i;
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      wr_streamers_ver_id_int <= "00000000000000000000000000000001";
+      wr_streamers_sscr1_rst_stats_int <= '0';
+      wr_streamers_sscr1_rst_seq_id_int <= '0';
+      wr_streamers_sscr1_snapshot_stats_int <= '0';
+      wr_streamers_tx_cfg0_ethertype_int <= "0000000000000000";
+      wr_streamers_tx_cfg1_mac_local_lsb_int <= "00000000000000000000000000000000";
+      wr_streamers_tx_cfg2_mac_local_msb_int <= "0000000000000000";
+      wr_streamers_tx_cfg3_mac_target_lsb_int <= "00000000000000000000000000000000";
+      wr_streamers_tx_cfg4_mac_target_msb_int <= "0000000000000000";
+      wr_streamers_tx_cfg5_qtag_ena_int <= '0';
+      wr_streamers_tx_cfg5_qtag_vid_int <= "000000000000";
+      wr_streamers_tx_cfg5_qtag_prio_int <= "000";
+      wr_streamers_rx_cfg0_ethertype_int <= "0000000000000000";
+      wr_streamers_rx_cfg0_accept_broadcast_int <= '0';
+      wr_streamers_rx_cfg0_filter_remote_int <= '0';
+      wr_streamers_rx_cfg1_mac_local_lsb_int <= "00000000000000000000000000000000";
+      wr_streamers_rx_cfg2_mac_local_msb_int <= "0000000000000000";
+      wr_streamers_rx_cfg3_mac_remote_lsb_int <= "00000000000000000000000000000000";
+      wr_streamers_rx_cfg4_mac_remote_msb_int <= "0000000000000000";
+      wr_streamers_rx_cfg5_fixed_latency_int <= "0000000000000000000000000000";
+      wr_streamers_cfg_or_tx_ethtype_int <= '0';
+      wr_streamers_cfg_or_tx_mac_loc_int <= '0';
+      wr_streamers_cfg_or_tx_mac_tar_int <= '0';
+      wr_streamers_cfg_or_tx_qtag_int <= '0';
+      wr_streamers_cfg_or_rx_ethertype_int <= '0';
+      wr_streamers_cfg_or_rx_mac_loc_int <= '0';
+      wr_streamers_cfg_or_rx_mac_rem_int <= '0';
+      wr_streamers_cfg_or_rx_acc_broadcast_int <= '0';
+      wr_streamers_cfg_or_rx_ftr_remote_int <= '0';
+      wr_streamers_cfg_or_rx_fix_lat_int <= '0';
+      wr_streamers_dbg_ctrl_mux_int <= '0';
+      wr_streamers_dbg_ctrl_start_byte_int <= "00000000";
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          wr_streamers_sscr1_rst_stats_int <= '0';
+          wr_streamers_sscr1_rst_seq_id_int <= '0';
+          ack_in_progress <= '0';
+        else
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(5 downto 0) is
+          when "000000" => 
+            if (wb_we_i = '1') then
+              wr_streamers_ver_id_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= wr_streamers_ver_id_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000001" => 
+            if (wb_we_i = '1') then
+              wr_streamers_sscr1_rst_stats_int <= wrdata_reg(0);
+              wr_streamers_sscr1_rst_seq_id_int <= wrdata_reg(1);
+              wr_streamers_sscr1_snapshot_stats_int <= wrdata_reg(2);
+            end if;
+            rddata_reg(0) <= '0';
+            rddata_reg(1) <= '0';
+            rddata_reg(2) <= wr_streamers_sscr1_snapshot_stats_int;
+            rddata_reg(3) <= regs_i.sscr1_rx_latency_acc_overflow_i;
+            rddata_reg(31 downto 4) <= regs_i.sscr1_rst_ts_cyc_i;
+            ack_sreg(2) <= '1';
+            ack_in_progress <= '1';
+          when "000010" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.sscr2_rst_ts_tai_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(7 downto 0) <= regs_i.sscr3_rst_ts_tai_msb_i;
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000100" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(27 downto 0) <= regs_i.rx_stat0_rx_latency_max_i;
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(27 downto 0) <= regs_i.rx_stat1_rx_latency_min_i;
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000110" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.tx_stat2_tx_sent_cnt_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000111" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.tx_stat3_tx_sent_cnt_msb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001000" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat4_rx_rcvd_cnt_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001001" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat5_rx_rcvd_cnt_msb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001010" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat6_rx_loss_cnt_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat7_rx_loss_cnt_msb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001100" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat8_rx_lost_block_cnt_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat9_rx_lost_block_cnt_msb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001110" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat10_rx_latency_acc_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001111" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat11_rx_latency_acc_msb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010000" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat12_rx_latency_acc_cnt_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010001" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.rx_stat13_rx_latency_acc_cnt_msb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010010" => 
+            if (wb_we_i = '1') then
+              wr_streamers_tx_cfg0_ethertype_int <= wrdata_reg(15 downto 0);
+            end if;
+            rddata_reg(15 downto 0) <= wr_streamers_tx_cfg0_ethertype_int;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010011" => 
+            if (wb_we_i = '1') then
+              wr_streamers_tx_cfg1_mac_local_lsb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= wr_streamers_tx_cfg1_mac_local_lsb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010100" => 
+            if (wb_we_i = '1') then
+              wr_streamers_tx_cfg2_mac_local_msb_int <= wrdata_reg(15 downto 0);
+            end if;
+            rddata_reg(15 downto 0) <= wr_streamers_tx_cfg2_mac_local_msb_int;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010101" => 
+            if (wb_we_i = '1') then
+              wr_streamers_tx_cfg3_mac_target_lsb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= wr_streamers_tx_cfg3_mac_target_lsb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010110" => 
+            if (wb_we_i = '1') then
+              wr_streamers_tx_cfg4_mac_target_msb_int <= wrdata_reg(15 downto 0);
+            end if;
+            rddata_reg(15 downto 0) <= wr_streamers_tx_cfg4_mac_target_msb_int;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010111" => 
+            if (wb_we_i = '1') then
+              wr_streamers_tx_cfg5_qtag_ena_int <= wrdata_reg(0);
+              wr_streamers_tx_cfg5_qtag_vid_int <= wrdata_reg(19 downto 8);
+              wr_streamers_tx_cfg5_qtag_prio_int <= wrdata_reg(26 downto 24);
+            end if;
+            rddata_reg(0) <= wr_streamers_tx_cfg5_qtag_ena_int;
+            rddata_reg(19 downto 8) <= wr_streamers_tx_cfg5_qtag_vid_int;
+            rddata_reg(26 downto 24) <= wr_streamers_tx_cfg5_qtag_prio_int;
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011000" => 
+            if (wb_we_i = '1') then
+              wr_streamers_rx_cfg0_ethertype_int <= wrdata_reg(15 downto 0);
+              wr_streamers_rx_cfg0_accept_broadcast_int <= wrdata_reg(16);
+              wr_streamers_rx_cfg0_filter_remote_int <= wrdata_reg(17);
+            end if;
+            rddata_reg(15 downto 0) <= wr_streamers_rx_cfg0_ethertype_int;
+            rddata_reg(16) <= wr_streamers_rx_cfg0_accept_broadcast_int;
+            rddata_reg(17) <= wr_streamers_rx_cfg0_filter_remote_int;
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011001" => 
+            if (wb_we_i = '1') then
+              wr_streamers_rx_cfg1_mac_local_lsb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= wr_streamers_rx_cfg1_mac_local_lsb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011010" => 
+            if (wb_we_i = '1') then
+              wr_streamers_rx_cfg2_mac_local_msb_int <= wrdata_reg(15 downto 0);
+            end if;
+            rddata_reg(15 downto 0) <= wr_streamers_rx_cfg2_mac_local_msb_int;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011011" => 
+            if (wb_we_i = '1') then
+              wr_streamers_rx_cfg3_mac_remote_lsb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= wr_streamers_rx_cfg3_mac_remote_lsb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011100" => 
+            if (wb_we_i = '1') then
+              wr_streamers_rx_cfg4_mac_remote_msb_int <= wrdata_reg(15 downto 0);
+            end if;
+            rddata_reg(15 downto 0) <= wr_streamers_rx_cfg4_mac_remote_msb_int;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011101" => 
+            if (wb_we_i = '1') then
+              wr_streamers_rx_cfg5_fixed_latency_int <= wrdata_reg(27 downto 0);
+            end if;
+            rddata_reg(27 downto 0) <= wr_streamers_rx_cfg5_fixed_latency_int;
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011110" => 
+            if (wb_we_i = '1') then
+              wr_streamers_cfg_or_tx_ethtype_int <= wrdata_reg(0);
+              wr_streamers_cfg_or_tx_mac_loc_int <= wrdata_reg(1);
+              wr_streamers_cfg_or_tx_mac_tar_int <= wrdata_reg(2);
+              wr_streamers_cfg_or_tx_qtag_int <= wrdata_reg(3);
+              wr_streamers_cfg_or_rx_ethertype_int <= wrdata_reg(16);
+              wr_streamers_cfg_or_rx_mac_loc_int <= wrdata_reg(17);
+              wr_streamers_cfg_or_rx_mac_rem_int <= wrdata_reg(18);
+              wr_streamers_cfg_or_rx_acc_broadcast_int <= wrdata_reg(19);
+              wr_streamers_cfg_or_rx_ftr_remote_int <= wrdata_reg(20);
+              wr_streamers_cfg_or_rx_fix_lat_int <= wrdata_reg(21);
+            end if;
+            rddata_reg(0) <= wr_streamers_cfg_or_tx_ethtype_int;
+            rddata_reg(1) <= wr_streamers_cfg_or_tx_mac_loc_int;
+            rddata_reg(2) <= wr_streamers_cfg_or_tx_mac_tar_int;
+            rddata_reg(3) <= wr_streamers_cfg_or_tx_qtag_int;
+            rddata_reg(16) <= wr_streamers_cfg_or_rx_ethertype_int;
+            rddata_reg(17) <= wr_streamers_cfg_or_rx_mac_loc_int;
+            rddata_reg(18) <= wr_streamers_cfg_or_rx_mac_rem_int;
+            rddata_reg(19) <= wr_streamers_cfg_or_rx_acc_broadcast_int;
+            rddata_reg(20) <= wr_streamers_cfg_or_rx_ftr_remote_int;
+            rddata_reg(21) <= wr_streamers_cfg_or_rx_fix_lat_int;
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011111" => 
+            if (wb_we_i = '1') then
+              wr_streamers_dbg_ctrl_mux_int <= wrdata_reg(0);
+              wr_streamers_dbg_ctrl_start_byte_int <= wrdata_reg(15 downto 8);
+            end if;
+            rddata_reg(0) <= wr_streamers_dbg_ctrl_mux_int;
+            rddata_reg(15 downto 8) <= wr_streamers_dbg_ctrl_start_byte_int;
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "100000" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.dbg_data_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "100001" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.dummy_dummy_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- Version identifier
+  regs_o.ver_id_o <= wr_streamers_ver_id_int;
+-- Reset statistics
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      wr_streamers_sscr1_rst_stats_dly0 <= '0';
+      regs_o.sscr1_rst_stats_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      wr_streamers_sscr1_rst_stats_dly0 <= wr_streamers_sscr1_rst_stats_int;
+      regs_o.sscr1_rst_stats_o <= wr_streamers_sscr1_rst_stats_int and (not wr_streamers_sscr1_rst_stats_dly0);
+    end if;
+  end process;
+  
+  
+-- Reset tx seq id
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      wr_streamers_sscr1_rst_seq_id_dly0 <= '0';
+      regs_o.sscr1_rst_seq_id_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      wr_streamers_sscr1_rst_seq_id_dly0 <= wr_streamers_sscr1_rst_seq_id_int;
+      regs_o.sscr1_rst_seq_id_o <= wr_streamers_sscr1_rst_seq_id_int and (not wr_streamers_sscr1_rst_seq_id_dly0);
+    end if;
+  end process;
+  
+  
+-- Snapshot statistics
+  regs_o.sscr1_snapshot_stats_o <= wr_streamers_sscr1_snapshot_stats_int;
+-- Latency accumulator overflow
+-- Reset timestamp cycles
+-- Reset timestamp 32 LSB of TAI
+-- Reset timestamp 8 MSB of TAI
+-- WR Streamer frame latency
+-- WR Streamer frame latency
+-- WR Streamer frame sent count (LSB)
+-- WR Streamer frame sent count (MSB)
+-- WR Streamer frame received count (LSB)
+-- WR Streamer frame received count (MSB)
+-- WR Streamer frame loss count (LSB)
+-- WR Streamer frame loss count (MSB)
+-- WR Streamer block loss count (LSB)
+-- WR Streamer block loss count (MSB)
+-- WR Streamer frame latency (LSB)
+-- WR Streamer frame latency (MSB)
+-- WR Streamer frame latency counter (LSB)
+-- WR Streamer frame latency counter (MSB)
+-- Ethertype
+  regs_o.tx_cfg0_ethertype_o <= wr_streamers_tx_cfg0_ethertype_int;
+-- MAC Local LSB
+  regs_o.tx_cfg1_mac_local_lsb_o <= wr_streamers_tx_cfg1_mac_local_lsb_int;
+-- MAC Local MSB
+  regs_o.tx_cfg2_mac_local_msb_o <= wr_streamers_tx_cfg2_mac_local_msb_int;
+-- MAC Target LSB
+  regs_o.tx_cfg3_mac_target_lsb_o <= wr_streamers_tx_cfg3_mac_target_lsb_int;
+-- MAC Target MSB
+  regs_o.tx_cfg4_mac_target_msb_o <= wr_streamers_tx_cfg4_mac_target_msb_int;
+-- Enable tagging with Qtags
+  regs_o.tx_cfg5_qtag_ena_o <= wr_streamers_tx_cfg5_qtag_ena_int;
+-- VLAN ID
+  regs_o.tx_cfg5_qtag_vid_o <= wr_streamers_tx_cfg5_qtag_vid_int;
+-- Priority
+  regs_o.tx_cfg5_qtag_prio_o <= wr_streamers_tx_cfg5_qtag_prio_int;
+-- Ethertype
+  regs_o.rx_cfg0_ethertype_o <= wr_streamers_rx_cfg0_ethertype_int;
+-- Accept Broadcast
+  regs_o.rx_cfg0_accept_broadcast_o <= wr_streamers_rx_cfg0_accept_broadcast_int;
+-- Filter Remote
+  regs_o.rx_cfg0_filter_remote_o <= wr_streamers_rx_cfg0_filter_remote_int;
+-- MAC Local LSB
+  regs_o.rx_cfg1_mac_local_lsb_o <= wr_streamers_rx_cfg1_mac_local_lsb_int;
+-- MAC Local MSB
+  regs_o.rx_cfg2_mac_local_msb_o <= wr_streamers_rx_cfg2_mac_local_msb_int;
+-- MAC Remote LSB
+  regs_o.rx_cfg3_mac_remote_lsb_o <= wr_streamers_rx_cfg3_mac_remote_lsb_int;
+-- MAC Remote MSB
+  regs_o.rx_cfg4_mac_remote_msb_o <= wr_streamers_rx_cfg4_mac_remote_msb_int;
+-- Fixed Latency
+  regs_o.rx_cfg5_fixed_latency_o <= wr_streamers_rx_cfg5_fixed_latency_int;
+-- Tx Ethertype
+  regs_o.cfg_or_tx_ethtype_o <= wr_streamers_cfg_or_tx_ethtype_int;
+-- Tx MAC Local
+  regs_o.cfg_or_tx_mac_loc_o <= wr_streamers_cfg_or_tx_mac_loc_int;
+-- Tx MAC Target
+  regs_o.cfg_or_tx_mac_tar_o <= wr_streamers_cfg_or_tx_mac_tar_int;
+-- QTAG
+  regs_o.cfg_or_tx_qtag_o <= wr_streamers_cfg_or_tx_qtag_int;
+-- Rx Ethertype
+  regs_o.cfg_or_rx_ethertype_o <= wr_streamers_cfg_or_rx_ethertype_int;
+-- Rx MAC Local
+  regs_o.cfg_or_rx_mac_loc_o <= wr_streamers_cfg_or_rx_mac_loc_int;
+-- Rx MAC Remote
+  regs_o.cfg_or_rx_mac_rem_o <= wr_streamers_cfg_or_rx_mac_rem_int;
+-- Rx Accept Broadcast
+  regs_o.cfg_or_rx_acc_broadcast_o <= wr_streamers_cfg_or_rx_acc_broadcast_int;
+-- Rx Filter Remote
+  regs_o.cfg_or_rx_ftr_remote_o <= wr_streamers_cfg_or_rx_ftr_remote_int;
+-- Rx Fixed Latency 
+  regs_o.cfg_or_rx_fix_lat_o <= wr_streamers_cfg_or_rx_fix_lat_int;
+-- Debug Tx (0) or Rx (1)
+  regs_o.dbg_ctrl_mux_o <= wr_streamers_dbg_ctrl_mux_int;
+-- Debug Start byte
+  regs_o.dbg_ctrl_start_byte_o <= wr_streamers_dbg_ctrl_start_byte_int;
+-- Debug content
+-- DUMMY value to read
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
new file mode 100644
index 000000000..a39fc326b
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
@@ -0,0 +1,191 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Transmission control, status and debug
+---------------------------------------------------------------------------------------
+-- File           : wr_streamers_wbgen2_pkg.vhd
+-- Author         : auto-generated by wbgen2 from wr_streamers_wb.wb
+-- Created        : Wed Aug 16 22:45:12 2017
+-- Version        : 0x00000001
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_streamers_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package wr_streamers_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_wr_streamers_in_registers is record
+    sscr1_rx_latency_acc_overflow_i          : std_logic;
+    sscr1_rst_ts_cyc_i                       : std_logic_vector(27 downto 0);
+    sscr2_rst_ts_tai_lsb_i                   : std_logic_vector(31 downto 0);
+    sscr3_rst_ts_tai_msb_i                   : std_logic_vector(7 downto 0);
+    rx_stat0_rx_latency_max_i                : std_logic_vector(27 downto 0);
+    rx_stat1_rx_latency_min_i                : std_logic_vector(27 downto 0);
+    tx_stat2_tx_sent_cnt_lsb_i               : std_logic_vector(31 downto 0);
+    tx_stat3_tx_sent_cnt_msb_i               : std_logic_vector(31 downto 0);
+    rx_stat4_rx_rcvd_cnt_lsb_i               : std_logic_vector(31 downto 0);
+    rx_stat5_rx_rcvd_cnt_msb_i               : std_logic_vector(31 downto 0);
+    rx_stat6_rx_loss_cnt_lsb_i               : std_logic_vector(31 downto 0);
+    rx_stat7_rx_loss_cnt_msb_i               : std_logic_vector(31 downto 0);
+    rx_stat8_rx_lost_block_cnt_lsb_i         : std_logic_vector(31 downto 0);
+    rx_stat9_rx_lost_block_cnt_msb_i         : std_logic_vector(31 downto 0);
+    rx_stat10_rx_latency_acc_lsb_i           : std_logic_vector(31 downto 0);
+    rx_stat11_rx_latency_acc_msb_i           : std_logic_vector(31 downto 0);
+    rx_stat12_rx_latency_acc_cnt_lsb_i       : std_logic_vector(31 downto 0);
+    rx_stat13_rx_latency_acc_cnt_msb_i       : std_logic_vector(31 downto 0);
+    dbg_data_i                               : std_logic_vector(31 downto 0);
+    dummy_dummy_i                            : std_logic_vector(31 downto 0);
+    end record;
+  
+  constant c_wr_streamers_in_registers_init_value: t_wr_streamers_in_registers := (
+    sscr1_rx_latency_acc_overflow_i => '0',
+    sscr1_rst_ts_cyc_i => (others => '0'),
+    sscr2_rst_ts_tai_lsb_i => (others => '0'),
+    sscr3_rst_ts_tai_msb_i => (others => '0'),
+    rx_stat0_rx_latency_max_i => (others => '0'),
+    rx_stat1_rx_latency_min_i => (others => '0'),
+    tx_stat2_tx_sent_cnt_lsb_i => (others => '0'),
+    tx_stat3_tx_sent_cnt_msb_i => (others => '0'),
+    rx_stat4_rx_rcvd_cnt_lsb_i => (others => '0'),
+    rx_stat5_rx_rcvd_cnt_msb_i => (others => '0'),
+    rx_stat6_rx_loss_cnt_lsb_i => (others => '0'),
+    rx_stat7_rx_loss_cnt_msb_i => (others => '0'),
+    rx_stat8_rx_lost_block_cnt_lsb_i => (others => '0'),
+    rx_stat9_rx_lost_block_cnt_msb_i => (others => '0'),
+    rx_stat10_rx_latency_acc_lsb_i => (others => '0'),
+    rx_stat11_rx_latency_acc_msb_i => (others => '0'),
+    rx_stat12_rx_latency_acc_cnt_lsb_i => (others => '0'),
+    rx_stat13_rx_latency_acc_cnt_msb_i => (others => '0'),
+    dbg_data_i => (others => '0'),
+    dummy_dummy_i => (others => '0')
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_wr_streamers_out_registers is record
+      ver_id_o                                 : std_logic_vector(31 downto 0);
+      sscr1_rst_stats_o                        : std_logic;
+      sscr1_rst_seq_id_o                       : std_logic;
+      sscr1_snapshot_stats_o                   : std_logic;
+      tx_cfg0_ethertype_o                      : std_logic_vector(15 downto 0);
+      tx_cfg1_mac_local_lsb_o                  : std_logic_vector(31 downto 0);
+      tx_cfg2_mac_local_msb_o                  : std_logic_vector(15 downto 0);
+      tx_cfg3_mac_target_lsb_o                 : std_logic_vector(31 downto 0);
+      tx_cfg4_mac_target_msb_o                 : std_logic_vector(15 downto 0);
+      tx_cfg5_qtag_ena_o                       : std_logic;
+      tx_cfg5_qtag_vid_o                       : std_logic_vector(11 downto 0);
+      tx_cfg5_qtag_prio_o                      : std_logic_vector(2 downto 0);
+      rx_cfg0_ethertype_o                      : std_logic_vector(15 downto 0);
+      rx_cfg0_accept_broadcast_o               : std_logic;
+      rx_cfg0_filter_remote_o                  : std_logic;
+      rx_cfg1_mac_local_lsb_o                  : std_logic_vector(31 downto 0);
+      rx_cfg2_mac_local_msb_o                  : std_logic_vector(15 downto 0);
+      rx_cfg3_mac_remote_lsb_o                 : std_logic_vector(31 downto 0);
+      rx_cfg4_mac_remote_msb_o                 : std_logic_vector(15 downto 0);
+      rx_cfg5_fixed_latency_o                  : std_logic_vector(27 downto 0);
+      cfg_or_tx_ethtype_o                      : std_logic;
+      cfg_or_tx_mac_loc_o                      : std_logic;
+      cfg_or_tx_mac_tar_o                      : std_logic;
+      cfg_or_tx_qtag_o                         : std_logic;
+      cfg_or_rx_ethertype_o                    : std_logic;
+      cfg_or_rx_mac_loc_o                      : std_logic;
+      cfg_or_rx_mac_rem_o                      : std_logic;
+      cfg_or_rx_acc_broadcast_o                : std_logic;
+      cfg_or_rx_ftr_remote_o                   : std_logic;
+      cfg_or_rx_fix_lat_o                      : std_logic;
+      dbg_ctrl_mux_o                           : std_logic;
+      dbg_ctrl_start_byte_o                    : std_logic_vector(7 downto 0);
+      end record;
+    
+    constant c_wr_streamers_out_registers_init_value: t_wr_streamers_out_registers := (
+      ver_id_o => (others => '0'),
+      sscr1_rst_stats_o => '0',
+      sscr1_rst_seq_id_o => '0',
+      sscr1_snapshot_stats_o => '0',
+      tx_cfg0_ethertype_o => (others => '0'),
+      tx_cfg1_mac_local_lsb_o => (others => '0'),
+      tx_cfg2_mac_local_msb_o => (others => '0'),
+      tx_cfg3_mac_target_lsb_o => (others => '0'),
+      tx_cfg4_mac_target_msb_o => (others => '0'),
+      tx_cfg5_qtag_ena_o => '0',
+      tx_cfg5_qtag_vid_o => (others => '0'),
+      tx_cfg5_qtag_prio_o => (others => '0'),
+      rx_cfg0_ethertype_o => (others => '0'),
+      rx_cfg0_accept_broadcast_o => '0',
+      rx_cfg0_filter_remote_o => '0',
+      rx_cfg1_mac_local_lsb_o => (others => '0'),
+      rx_cfg2_mac_local_msb_o => (others => '0'),
+      rx_cfg3_mac_remote_lsb_o => (others => '0'),
+      rx_cfg4_mac_remote_msb_o => (others => '0'),
+      rx_cfg5_fixed_latency_o => (others => '0'),
+      cfg_or_tx_ethtype_o => '0',
+      cfg_or_tx_mac_loc_o => '0',
+      cfg_or_tx_mac_tar_o => '0',
+      cfg_or_tx_qtag_o => '0',
+      cfg_or_rx_ethertype_o => '0',
+      cfg_or_rx_mac_loc_o => '0',
+      cfg_or_rx_mac_rem_o => '0',
+      cfg_or_rx_acc_broadcast_o => '0',
+      cfg_or_rx_ftr_remote_o => '0',
+      cfg_or_rx_fix_lat_o => '0',
+      dbg_ctrl_mux_o => '0',
+      dbg_ctrl_start_byte_o => (others => '0')
+      );
+    function "or" (left, right: t_wr_streamers_in_registers) return t_wr_streamers_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body wr_streamers_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if x(i) = '1' then
+tmp(i):= '1';
+else
+tmp(i):= '0';
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_wr_streamers_in_registers) return t_wr_streamers_in_registers is
+variable tmp: t_wr_streamers_in_registers;
+begin
+tmp.sscr1_rx_latency_acc_overflow_i := f_x_to_zero(left.sscr1_rx_latency_acc_overflow_i) or f_x_to_zero(right.sscr1_rx_latency_acc_overflow_i);
+tmp.sscr1_rst_ts_cyc_i := f_x_to_zero(left.sscr1_rst_ts_cyc_i) or f_x_to_zero(right.sscr1_rst_ts_cyc_i);
+tmp.sscr2_rst_ts_tai_lsb_i := f_x_to_zero(left.sscr2_rst_ts_tai_lsb_i) or f_x_to_zero(right.sscr2_rst_ts_tai_lsb_i);
+tmp.sscr3_rst_ts_tai_msb_i := f_x_to_zero(left.sscr3_rst_ts_tai_msb_i) or f_x_to_zero(right.sscr3_rst_ts_tai_msb_i);
+tmp.rx_stat0_rx_latency_max_i := f_x_to_zero(left.rx_stat0_rx_latency_max_i) or f_x_to_zero(right.rx_stat0_rx_latency_max_i);
+tmp.rx_stat1_rx_latency_min_i := f_x_to_zero(left.rx_stat1_rx_latency_min_i) or f_x_to_zero(right.rx_stat1_rx_latency_min_i);
+tmp.tx_stat2_tx_sent_cnt_lsb_i := f_x_to_zero(left.tx_stat2_tx_sent_cnt_lsb_i) or f_x_to_zero(right.tx_stat2_tx_sent_cnt_lsb_i);
+tmp.tx_stat3_tx_sent_cnt_msb_i := f_x_to_zero(left.tx_stat3_tx_sent_cnt_msb_i) or f_x_to_zero(right.tx_stat3_tx_sent_cnt_msb_i);
+tmp.rx_stat4_rx_rcvd_cnt_lsb_i := f_x_to_zero(left.rx_stat4_rx_rcvd_cnt_lsb_i) or f_x_to_zero(right.rx_stat4_rx_rcvd_cnt_lsb_i);
+tmp.rx_stat5_rx_rcvd_cnt_msb_i := f_x_to_zero(left.rx_stat5_rx_rcvd_cnt_msb_i) or f_x_to_zero(right.rx_stat5_rx_rcvd_cnt_msb_i);
+tmp.rx_stat6_rx_loss_cnt_lsb_i := f_x_to_zero(left.rx_stat6_rx_loss_cnt_lsb_i) or f_x_to_zero(right.rx_stat6_rx_loss_cnt_lsb_i);
+tmp.rx_stat7_rx_loss_cnt_msb_i := f_x_to_zero(left.rx_stat7_rx_loss_cnt_msb_i) or f_x_to_zero(right.rx_stat7_rx_loss_cnt_msb_i);
+tmp.rx_stat8_rx_lost_block_cnt_lsb_i := f_x_to_zero(left.rx_stat8_rx_lost_block_cnt_lsb_i) or f_x_to_zero(right.rx_stat8_rx_lost_block_cnt_lsb_i);
+tmp.rx_stat9_rx_lost_block_cnt_msb_i := f_x_to_zero(left.rx_stat9_rx_lost_block_cnt_msb_i) or f_x_to_zero(right.rx_stat9_rx_lost_block_cnt_msb_i);
+tmp.rx_stat10_rx_latency_acc_lsb_i := f_x_to_zero(left.rx_stat10_rx_latency_acc_lsb_i) or f_x_to_zero(right.rx_stat10_rx_latency_acc_lsb_i);
+tmp.rx_stat11_rx_latency_acc_msb_i := f_x_to_zero(left.rx_stat11_rx_latency_acc_msb_i) or f_x_to_zero(right.rx_stat11_rx_latency_acc_msb_i);
+tmp.rx_stat12_rx_latency_acc_cnt_lsb_i := f_x_to_zero(left.rx_stat12_rx_latency_acc_cnt_lsb_i) or f_x_to_zero(right.rx_stat12_rx_latency_acc_cnt_lsb_i);
+tmp.rx_stat13_rx_latency_acc_cnt_msb_i := f_x_to_zero(left.rx_stat13_rx_latency_acc_cnt_msb_i) or f_x_to_zero(right.rx_stat13_rx_latency_acc_cnt_msb_i);
+tmp.dbg_data_i := f_x_to_zero(left.dbg_data_i) or f_x_to_zero(right.dbg_data_i);
+tmp.dummy_dummy_i := f_x_to_zero(left.dummy_dummy_i) or f_x_to_zero(right.dummy_dummy_i);
+return tmp;
+end function;
+end package body;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrtx_streamers_stats.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrtx_streamers_stats.vhd
new file mode 100644
index 000000000..05f22a807
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrtx_streamers_stats.vhd
@@ -0,0 +1,362 @@
+-------------------------------------------------------------------------------
+-- Title      : WR Streamers statistics
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : xrtx_streamers_stats.vhd
+-- Author     : Maciej Lipinski
+-- Company    : CERN
+-- Created    : 2016-06-08
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- Module to collect, reset, snapshot statistics from the streamers. The
+-- statistics are made available through wishbone I/F (outside this entity)
+-- and diags_i/o (generic input/output arrays of 32-bit registers). Wishbone I/F
+-- can be read via bus (PCI, VME,...). Diags can be read via wrpc commands and 
+-- SNMP.
+--
+-- The module provides basic statistics such as:
+-- * number of sent/received streamer frames
+-- * number of lost frames/blocks
+-- * accumulated latency of streamer frames
+-- * count of the accumulated latencies
+-- * max/min latency
+-- * timestamp of the reset pulse
+--
+-- The module allows to snapshot the statistics values as to have a coherent
+-- view.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2016-2017CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+library work;
+use work.wishbone_pkg.all;  -- needed for t_wishbone_slave_in, etc
+use work.streamers_pkg.all; -- needed for streamers
+use work.wr_fabric_pkg.all; -- neede for :t_wrf_source_in, etc
+use work.wrcore_pkg.all;    -- needed for t_generic_word_array
+use work.streamers_priv_pkg.all;
+
+entity xrtx_streamers_stats is
+  generic (
+    -- Indicates whether this module instantiates both streamers (rx and tx) or only one
+    -- of them. An application that only receives or only transmits might want to use
+    -- RX_ONLY or TX_ONLY mode to save resources.
+    g_streamers_op_mode    : t_streamers_op_mode  := TX_AND_RX;
+    -- Width of frame counters
+    g_cnt_width            : integer := 50; -- min:15, max:64, 50 bits should be ok for 50 years
+    g_acc_width            : integer := 64  -- max value 64
+    );
+  port (
+    clk_i                  : in std_logic;
+    rst_n_i                : in std_logic;
+
+    -- input signals from streamers
+    sent_frame_i           : in std_logic;
+    rcvd_frame_i           : in std_logic;
+    lost_block_i           : in std_logic;
+    lost_frame_i           : in std_logic;
+    lost_frames_cnt_i      : in std_logic_vector(14 downto 0);
+    rcvd_latency_i         : in  std_logic_vector(27 downto 0);
+    rcvd_latency_valid_i   : in  std_logic;
+
+    clk_ref_i              : in std_logic;
+    tm_time_valid_i        : in std_logic := '0';
+    tm_tai_i               : in std_logic_vector(39 downto 0) := x"0000000000";
+    tm_cycles_i            : in std_logic_vector(27 downto 0) := x"0000000";
+
+    -- statistic control
+    reset_stats_i          : in std_logic;
+    snapshot_ena_i         : in std_logic := '0';
+    ----------------------- statistics ----------------------------------------
+    -- output statistics: time of last reset of statistics
+    reset_time_tai_o       : out std_logic_vector(39 downto 0) := x"0000000000";
+    reset_time_cycles_o    : out std_logic_vector(27 downto 0) := x"0000000";
+    -- output statistics: tx/rx counters
+    sent_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+    rcvd_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+    lost_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+    lost_block_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+    -- output statistics: latency
+    latency_cnt_o          : out std_logic_vector(g_cnt_width-1 downto 0);
+    latency_acc_overflow_o : out std_logic;
+    latency_acc_o          : out std_logic_vector(g_acc_width-1  downto 0);
+    latency_max_o          : out std_logic_vector(27  downto 0);
+    latency_min_o          : out std_logic_vector(27  downto 0);
+
+    snmp_array_o           : out t_generic_word_array(c_WRS_STATS_ARR_SIZE_OUT-1 downto 0);
+    snmp_array_i           : in  t_generic_word_array(c_WRS_STATS_ARR_SIZE_IN -1 downto 0)
+    );
+
+end xrtx_streamers_stats;
+
+architecture rtl of xrtx_streamers_stats is
+
+  signal reset_time_tai    : std_logic_vector(39 downto 0);
+  signal reset_time_cycles : std_logic_vector(27 downto 0);
+
+  signal sent_frame_cnt    : unsigned(g_cnt_width-1  downto 0);
+  signal rcvd_frame_cnt    : unsigned(g_cnt_width-1  downto 0);
+  signal lost_frame_cnt    : unsigned(g_cnt_width-1  downto 0);
+  signal lost_block_cnt    : unsigned(g_cnt_width-1  downto 0);
+  signal latency_cnt       : unsigned(g_cnt_width-1  downto 0);
+
+  signal latency_max       : std_logic_vector(27  downto 0);
+  signal latency_min       : std_logic_vector(27  downto 0);
+  signal latency_acc       : unsigned(g_acc_width-1+1  downto 0);
+  signal latency_acc_overflow: std_logic;
+
+  signal sent_frame_cnt_out       : std_logic_vector(g_cnt_width-1 downto 0);
+  signal rcvd_frame_cnt_out       : std_logic_vector(g_cnt_width-1 downto 0);
+  signal lost_frame_cnt_out       : std_logic_vector(g_cnt_width-1 downto 0);
+  signal lost_block_cnt_out       : std_logic_vector(g_cnt_width-1 downto 0);
+  signal latency_cnt_out          : std_logic_vector(g_cnt_width-1 downto 0);
+  signal latency_acc_overflow_out : std_logic;
+  signal latency_acc_out          : std_logic_vector(g_acc_width-1  downto 0);
+  signal latency_max_out          : std_logic_vector(27  downto 0);
+  signal latency_min_out          : std_logic_vector(27  downto 0);
+
+  --- statistics resets:
+  signal reset_stats_remote: std_logic;
+  signal reset_stats       : std_logic;
+  signal reset_stats_d1    : std_logic;
+  signal reset_stats_p     : std_logic;
+  signal snapshot_remote_ena  : std_logic;
+  signal snapshot_ena      : std_logic;
+  signal snapshot_ena_d1   : std_logic;
+  
+  -- for code cleanness
+  constant c_cw              : integer := g_cnt_width;
+  constant c_aw              : integer := g_acc_width;
+begin
+
+  -- reset statistics when receiving signal from SNMP or Wishbone
+  reset_stats <= reset_stats_remote or reset_stats_i;
+  -------------------------------------------------------------------------------------------
+  -- produce pulse of reset input signal, this pulse produces timesstamp to be timestamped
+  -------------------------------------------------------------------------------------------
+  -- pulse is on falling and rising edge of the reset signal (reset when signal HIGH)
+  -- in this way, one can 
+  -- 1. read the timestamp of the start of statistics acquisition
+  -- 2. reset HIGH
+  -- 3. read the timestamp of the end of statistics acquisition
+  -- 4. start acqusition
+  -------------------------------------------------------------------------------------------
+  -- when exiting the reset, produce pulse for the timestamper
+  p_stats_reset: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (rst_n_i = '0') then
+         reset_stats_p  <= '0';
+         reset_stats_d1 <= '0';
+      else
+        reset_stats_d1 <= reset_stats;
+        reset_stats_p  <= reset_stats xor reset_stats_d1;
+      end if;
+    end if;
+  end process;
+
+  -------------------------------------------------------------------------------------------
+  -- Timestamp of reset
+  -------------------------------------------------------------------------------------------
+  -- process that timestamps the reset so that we can make statistics over time
+  U_Reset_Timestamper : pulse_stamper
+    port map (
+      clk_ref_i       => clk_ref_i,
+      clk_sys_i       => clk_i,
+      rst_n_i         => rst_n_i,
+      pulse_a_i       => reset_stats_p,
+      tm_time_valid_i => tm_time_valid_i,
+      tm_tai_i        => tm_tai_i,
+      tm_cycles_i     => tm_cycles_i,
+      tag_tai_o       => reset_time_tai,
+      tag_cycles_o    => reset_time_cycles);
+
+  reset_time_tai_o    <= reset_time_tai;
+  reset_time_cycles_o <= reset_time_cycles;
+
+  -------------------------------------------------------------------------------------------
+  -- snapshot 
+  -------------------------------------------------------------------------------------------
+  -- snapshot is used to expose to user coherent value, so that the count for accumulated
+  -- latency is coherent with the accumulated latency and the average can be accurately 
+  -- calculated
+  -------------------------------------------------------------------------------------------
+  snapshot_ena <= snapshot_ena_i or snapshot_remote_ena;
+  -- snapshot
+
+  gen_tx_stats: if(g_streamers_op_mode=TX_ONLY OR g_streamers_op_mode=TX_AND_RX) generate
+    U_TX_STATS: xtx_streamers_stats
+      generic map (
+        g_cnt_width            => g_cnt_width
+        )
+      port map(
+        clk_i                  => clk_i,
+        rst_n_i                => rst_n_i,
+        sent_frame_i           => sent_frame_i,
+        reset_stats_i          => reset_stats,
+        snapshot_ena_i         => snapshot_ena,
+        sent_frame_cnt_o       => sent_frame_cnt_out);
+  end generate gen_tx_stats;
+  gen_not_tx_stats: if(g_streamers_op_mode=RX_ONLY) generate
+    sent_frame_cnt_out <= (others => '0');
+  end generate gen_not_tx_stats;
+
+  gen_rx_stats: if(g_streamers_op_mode=RX_ONLY OR g_streamers_op_mode=TX_AND_RX) generate
+    U_RX_STATS: xrx_streamers_stats
+      generic map(
+        g_cnt_width            => g_cnt_width,
+        g_acc_width            => g_acc_width
+        )
+      port map(
+        clk_i                  => clk_i,
+        rst_n_i                => rst_n_i,
+        rcvd_frame_i           => rcvd_frame_i,
+        lost_block_i           => lost_block_i,
+        lost_frame_i           => lost_frame_i,
+        lost_frames_cnt_i      => lost_frames_cnt_i,
+        rcvd_latency_i         => rcvd_latency_i,
+        rcvd_latency_valid_i   => rcvd_latency_valid_i,
+        tm_time_valid_i        => tm_time_valid_i,
+        snapshot_ena_i         => snapshot_ena,
+        reset_stats_i          => reset_stats,
+        rcvd_frame_cnt_o       => rcvd_frame_cnt_out,
+        lost_frame_cnt_o       => lost_frame_cnt_out,
+        lost_block_cnt_o       => lost_block_cnt_out,
+        latency_cnt_o          => latency_cnt_out,
+        latency_acc_overflow_o => latency_acc_overflow_out,
+        latency_acc_o          => latency_acc_out,
+        latency_max_o          => latency_max_out,
+        latency_min_o          => latency_min_out);
+  end generate gen_rx_stats;
+  gen_not_rx_stats: if(g_streamers_op_mode=TX_ONLY) generate
+    rcvd_frame_cnt_out       <= (others => '0');
+    lost_frame_cnt_out       <= (others => '0');
+    lost_block_cnt_out       <= (others => '0');
+    latency_cnt_out          <= (others => '0');
+    latency_acc_overflow_out <= '0';
+    latency_acc_out          <= (others => '0');
+    latency_max_out          <= (others => '0');
+    latency_min_out          <= (others => '0');
+  end generate gen_not_rx_stats;
+  -------------------------------------------------------------------------------------------
+  -- wishbone local output
+  -------------------------------------------------------------------------------------------
+  sent_frame_cnt_o         <= sent_frame_cnt_out;
+  rcvd_frame_cnt_o         <= rcvd_frame_cnt_out;
+  lost_frame_cnt_o         <= lost_frame_cnt_out;
+  lost_block_cnt_o         <= lost_block_cnt_out;
+  latency_max_o            <= latency_max_out;
+  latency_min_o            <= latency_min_out;
+  latency_acc_o            <= latency_acc_out;
+  latency_cnt_o            <= latency_cnt_out;
+  latency_acc_overflow_o   <= latency_acc_overflow_out;
+
+  -------------------------------------------------------------------------------------------
+  -- SNMP remote output
+  -- Generic communication with WRPC that allows SNMP access via generic array of 32-bits 
+  -- std_logic_vectors. The mapping of the generic vectors to meaningful information needs
+  -- to be made available to the user of SNMP
+  -------------------------------------------------------------------------------------------
+  -- check sanity of values
+  assert (c_cw <= 64) 
+    report "g_cnt_width value not suppported by f_pack_streamers_statistics" severity error;
+  assert (c_aw <= 64) 
+    report "g_acc_width value not suppported by f_pack_streamers_statistics" severity error;
+
+  -- translate generic input vectors to meaningful signals
+  reset_stats_remote                  <= snmp_array_i(0)(0);
+  snapshot_remote_ena                 <= snmp_array_i(0)(1);
+
+  snmp_array_o(0)(             0)     <= reset_stats;                   -- loop back for diagnostics
+  snmp_array_o(0)(             1)     <= latency_acc_overflow_out;
+  snmp_array_o(0) (31   downto 2)     <= (others => '0');
+
+  snmp_array_o(1)(   31 downto 0)     <= x"0" & reset_time_cycles( 27 downto 0);
+  snmp_array_o(2)(   31 downto 0)     <= reset_time_tai(    31 downto 0);
+  snmp_array_o(3)(   31 downto 0)     <= x"000000" & reset_time_tai(    39 downto 32);
+
+  -- translate meaningful signals (statistics values) to generic output vectors
+  snmp_array_o(4 )(31   downto 0)     <= x"0" & latency_max_out(27 downto 0);
+  snmp_array_o(5 )(31   downto 0)     <= x"0" & latency_min_out(27 downto 0); 
+
+  CNT_SINGLE_WORD_gen: if(c_cw < 33) generate
+    snmp_array_o(6 )(c_cw-1    downto       0) <= sent_frame_cnt_out;
+    snmp_array_o(6 )(31        downto    c_cw) <= (others => '0');
+    snmp_array_o(7 )(31        downto       0) <= (others => '0');
+
+    snmp_array_o(8 )(c_cw-1    downto       0) <= rcvd_frame_cnt_out;
+    snmp_array_o(8 )(31        downto    c_cw) <= (others => '0');
+    snmp_array_o(9 )(31        downto       0) <= (others => '0');
+
+    snmp_array_o(10)(c_cw-1    downto       0) <= lost_frame_cnt_out;
+    snmp_array_o(10)(31        downto    c_cw) <= (others => '0');
+    snmp_array_o(11)(31        downto       0) <= (others => '0');
+
+    snmp_array_o(12)(c_cw-1    downto       0) <= lost_block_cnt_out;
+    snmp_array_o(12)(31        downto    c_cw) <= (others => '0');
+    snmp_array_o(13)(31        downto       0) <= (others => '0');
+
+    snmp_array_o(14)(c_cw-1    downto       0) <= latency_cnt_out;
+    snmp_array_o(14)(31        downto    c_cw) <= (others => '0');
+    snmp_array_o(15)(31        downto       0) <= (others => '0');
+  end generate;
+  ACC_SINGLE_WORD_gen: if(c_aw < 33) generate
+    snmp_array_o(16)(c_aw-1    downto       0) <= latency_acc_out;
+    snmp_array_o(16)(31        downto    c_aw) <= (others => '0');
+    snmp_array_o(17)(31        downto       0) <= (others => '0');
+  end generate;
+
+  ---
+  CNT_TWO_WORDs_gen:  if(c_cw > 32)  generate
+    snmp_array_o(6 )(31        downto       0) <= sent_frame_cnt_out(31     downto 0);
+    snmp_array_o(7 )(c_cw-32-1 downto       0) <= sent_frame_cnt_out(c_cw-1 downto 32);
+    snmp_array_o(7 )(31        downto c_cw-32) <= (others => '0');
+
+    snmp_array_o(8 )(31        downto       0) <= rcvd_frame_cnt_out(31     downto 0);
+    snmp_array_o(9 )(c_cw-32-1 downto       0) <= rcvd_frame_cnt_out(c_cw-1 downto 32);
+    snmp_array_o(9 )(31        downto c_cw-32) <= (others => '0');
+
+    snmp_array_o(10)(31        downto       0) <= lost_frame_cnt_out(31     downto 0);
+    snmp_array_o(11)(c_cw-32-1 downto       0) <= lost_frame_cnt_out(c_cw-1 downto 32);
+    snmp_array_o(11 )(31       downto c_cw-32) <= (others => '0');
+
+    snmp_array_o(12)(31        downto       0) <= lost_block_cnt_out(31     downto 0);
+    snmp_array_o(13)(c_cw-32-1 downto       0) <= lost_block_cnt_out(c_cw-1 downto 32);
+    snmp_array_o(13 )(31       downto c_cw-32) <= (others => '0');
+
+    snmp_array_o(14)(31        downto       0) <= latency_cnt_out(31     downto 0);
+    snmp_array_o(15)(c_cw-32-1 downto       0) <= latency_cnt_out(c_cw-1 downto 32);
+    snmp_array_o(15 )(31       downto c_cw-32) <= (others => '0');
+  end generate;
+  ACC_TWO_WORDs_gen:   if(c_aw > 32) generate
+    snmp_array_o(16)(31        downto       0) <= latency_acc_out(31     downto 0);
+    snmp_array_o(17)(c_aw-32-1 downto       0) <= latency_acc_out(c_aw-1 downto 32) ;
+    snmp_array_o(17)(31        downto c_aw-32) <= (others => '0'); 
+  end generate;
+
+end rtl;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrx_streamer.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrx_streamer.vhd
new file mode 100644
index 000000000..e135c0b08
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrx_streamer.vhd
@@ -0,0 +1,677 @@
+-------------------------------------------------------------------------------
+-- Title      : Transmission Streamer
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : xrx_streamer.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-11-02
+-- Platform   : FPGA-generic
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description: A simple core demonstrating how to encapsulate a continuous
+-- stream of data words into Ethernet frames, in a format that is accepted by
+-- the White Rabbit PTP core. This core decodes Ethernet frames encoded by
+-- xtx_streamer. More info in the documentation.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012-2017 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.streamers_priv_pkg.all;
+use work.streamers_pkg.all;
+
+entity xrx_streamer is
+  
+  generic (
+    -- Width of the data words, must be multiple of 16 bits. This value set to this generic
+    -- on the receviving device must be the same as the value of g_tx_data_width set on the
+    -- transmitting node. The g_rx_data_width and g_tx_data_width can be set to different
+    -- values in the same device (i.e. instantiation of xwr_transmission entity). It is the
+    -- responsibility of a network designer to make sure these parameters are properly set 
+    -- in the network.
+    g_data_width        : integer := 32;
+
+    -- Size of RX buffer, in data words.
+    g_buffer_size       : integer := 256;
+
+    -- DO NOT USE unless you know what you are doing
+    -- legacy: the streamers that were initially used in Btrain did not check/insert 
+    -- the escape code. This is justified if only one block of a known number of words is 
+    -- sent/expected.
+    g_escape_code_disable : boolean := FALSE;
+
+    -- DO NOT USE unless you know what you are doing
+    -- legacy: the streamers that were initially used in Btrain accepted only a fixed
+    -- number of words, regardless of the frame content. If this generic is set to number
+    -- other than zero, only a fixed number of words is accepted. 
+    -- In combination with the g_escape_code_disable generic set to TRUE, the behaviour of
+    -- the "Btrain streamers" can be recreated.
+    g_expected_words_number : integer := 0
+    );
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    -- Endpoint/WRC interface 
+    snk_i : in  t_wrf_sink_in;
+    snk_o : out t_wrf_sink_out;
+
+    ---------------------------------------------------------------------------
+    -- WRC Timing interface, used for latency measurement
+    -- Caution: uses clk_ref_i clock domain!
+    ---------------------------------------------------------------------------
+
+    -- White Rabbit reference clock
+    clk_ref_i : in std_logic := '0';
+
+    -- Time valid flag
+    tm_time_valid_i : in std_logic := '0';
+
+    -- TAI seconds
+    tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
+
+    -- Fractional part of the second (in clk_ref_i cycles)
+    tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
+
+    ---------------------------------------------------------------------------
+    -- User interface
+    ---------------------------------------------------------------------------
+
+    -- 1 indicates the 1st word of the data block on rx_data_o.
+    rx_first_p1_o         : out std_logic;
+    -- 1 indicates the last word of the data block on rx_data_o.
+    rx_last_p1_o          : out std_logic;
+    -- Received data.
+    rx_data_o          : out std_logic_vector(g_data_width-1 downto 0);
+    -- 1 indicted that rx_data_o is outputting a valid data word.
+    rx_valid_o         : out std_logic;
+    -- Synchronous data request input: when 1, the streamer may output another
+    -- data word in the subsequent clock cycle.
+    rx_dreq_i          : in  std_logic;
+    -- Lost output: 1 indicates that one or more frames or blocks have been lost
+    -- (left for backward compatibility).
+    rx_lost_p1_o          : out std_logic := '0';
+    -- indicates that one or more blocks within frame are missing
+    rx_lost_blocks_p1_o    :  out std_logic := '0';
+    -- indicates that one or more frames are missing, the number of frames is provied
+    rx_lost_frames_p1_o    :  out std_logic := '0';
+    --number of lost frames, the 0xF...F means that counter overflew
+    rx_lost_frames_cnt_o : out std_logic_vector(14 downto 0);
+    -- Latency measurement output: indicates the transport latency (between the
+    -- TX streamer in remote device and this streamer), in clk_ref_i clock cycles.
+    rx_latency_o       : out std_logic_vector(27 downto 0);
+    -- 1 when the latency on rx_latency_o is valid.
+    rx_latency_valid_o : out std_logic;
+    -- received 	streamer frame (counts all frames, corrupted and not)
+    rx_frame_p1_o         : out std_logic;
+    -- configuration
+    rx_streamer_cfg_i     : in t_rx_streamer_cfg := c_rx_streamer_cfg_default
+    );
+
+end xrx_streamer;
+
+architecture rtl of xrx_streamer is
+
+  type t_rx_state is (IDLE, HEADER, FRAME_SEQ_ID, PAYLOAD, SUBFRAME_HEADER, EOF);
+
+  signal fab, fsm_in : t_pipe;
+
+  signal state : t_rx_state;
+
+  signal ser_count : unsigned(7 downto 0);
+  signal seq_no, seq_new,count  : unsigned(14 downto 0);
+
+  signal crc_match, crc_en, crc_en_masked, crc_restart : std_logic;
+
+  signal detect_escapes, is_escape : std_logic;
+  signal rx_pending                : std_logic;
+
+  signal pack_data, fifo_data : std_logic_vector(g_data_width-1 downto 0);
+
+  signal fifo_drop, fifo_accept, fifo_accept_d0, fifo_dvalid : std_logic;
+  signal fifo_sync, fifo_last, frames_lost, blocks_lost      : std_logic;
+  signal fifo_dout, fifo_din                                 : std_logic_vector(g_data_width + 1 downto 0);
+
+  signal pending_write, fab_dvalid_pre : std_logic;
+
+
+  signal tx_tag_cycles, rx_tag_cycles : std_logic_vector(27 downto 0);
+  signal tx_tag_valid, rx_tag_valid   : std_logic;
+
+  signal got_next_subframe : std_logic;
+  signal is_frame_seq_id : std_logic;
+  signal word_count                                                        : unsigned(11 downto 0);
+  signal sync_seq_no : std_logic;
+
+  -- fixed latency signals
+  type   t_rx_delay_state is (DISABLED, DELAY, ALLOW);
+  signal timestamped        : std_logic;
+  signal delay_cnt          : unsigned(27 downto 0);
+  signal rx_dreq_allow      : std_logic;
+  signal rx_latency         : unsigned(27 downto 0);
+  signal rx_latency_stored  : unsigned(27 downto 0);
+  signal rx_latency_valid   : std_logic;
+  signal delay_state        : t_rx_delay_state;
+  signal rx_dreq            : std_logic;
+  signal is_vlan            : std_logic;
+
+  constant c_fixed_latency_zero : unsigned(27 downto 0) := (others => '0');
+  constant c_timestamper_delay  : unsigned(27 downto 0) := to_unsigned(12, 28); -- cycles
+  
+begin  -- rtl
+
+  U_rx_crc_generator : gc_crc_gen
+    generic map (
+      g_polynomial              => x"1021",
+      g_init_value              => x"ffff",
+      g_residue                 => x"470f",
+      g_data_width              => 16,
+      g_sync_reset              => 1,
+      g_dual_width              => 0,
+      g_registered_match_output => true)
+    port map (
+      clk_i     => clk_sys_i,
+      rst_i     => '0',
+      restart_i => crc_restart,
+      en_i      => crc_en_masked,
+      data_i    => fsm_in.data,
+      half_i    => '0',
+      match_o   => crc_match);
+
+  crc_en_masked <= crc_en and fsm_in.dvalid;
+
+  U_Fabric_Sink : xwb_fabric_sink
+    port map (
+      clk_i     => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      snk_i     => snk_i,
+      snk_o     => snk_o,
+      addr_o    => fab.addr,
+      data_o    => fab.data,
+      dvalid_o  => fab_dvalid_pre,
+      sof_o     => fab.sof,
+      eof_o     => fab.eof,
+      error_o   => fab.error,
+      bytesel_o => fab.bytesel,
+      dreq_i    => fab.dreq);
+
+  fab.dvalid <= '1' when fab_dvalid_pre = '1' and fab.addr = c_WRF_DATA and fab.bytesel = '0' else '0';
+  gen_escape: if (g_escape_code_disable = FALSE) generate
+    U_Escape_Detect : escape_detector
+      generic map (
+        g_data_width  => 16,
+        g_escape_code => x"cafe")
+      port map (
+        clk_i             => clk_sys_i,
+        rst_n_i           => rst_n_i,
+        d_i               => fab.data,
+        d_detect_enable_i => detect_escapes,
+        d_valid_i         => fab.dvalid,
+        d_req_o           => fab.dreq,
+        d_o               => fsm_in.data,
+        d_escape_o        => is_escape,
+        d_valid_o         => fsm_in.dvalid,
+        d_req_i           => fsm_in.dreq);
+  end generate gen_escape;
+  gen_no_escape: if (g_escape_code_disable = TRUE) generate
+    fsm_in.dvalid <= fab.dvalid;
+    fsm_in.data   <= fab.data;
+    fab.dreq      <= fsm_in.dreq;
+    is_escape     <= '0';
+  end generate gen_no_escape;
+  fsm_in.eof <= fab.eof or fab.error;
+  fsm_in.sof <= fab.sof;
+
+
+  U_Output_FIFO : dropping_buffer
+    generic map (
+      g_size       => g_buffer_size,
+      g_data_width => g_data_width + 2)
+    port map (
+      clk_i      => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      d_i        => fifo_din,
+      d_req_o    => fsm_in.dreq,
+      d_drop_i   => fifo_drop,
+      d_accept_i => fifo_accept_d0,
+      d_valid_i  => fifo_dvalid,
+      d_o        => fifo_dout,
+      d_valid_o  => rx_valid_o,
+      d_req_i    => rx_dreq);
+
+  fifo_din(g_data_width+1)          <= fifo_sync;
+  fifo_din(g_data_width)            <= fifo_last or 
+                                        ((not pending_write) and is_escape); -- when word is 16 bits
+  fifo_din(g_data_width-1 downto 0) <= fifo_data;
+
+  rx_data_o  <= fifo_dout(g_data_width-1 downto 0);
+  rx_first_p1_o <= fifo_dout(g_data_width+1);
+  rx_last_p1_o  <= fifo_dout(g_data_width);
+
+  U_RX_Timestamper : pulse_stamper
+    port map (
+      clk_ref_i       => clk_ref_i,
+      clk_sys_i       => clk_sys_i,
+      rst_n_i         => rst_n_i,
+      pulse_a_i       => fsm_in.sof,
+      tm_time_valid_i => tm_time_valid_i,
+      tm_tai_i        => tm_tai_i,
+      tm_cycles_i     => tm_cycles_i,
+      tag_cycles_o    => rx_tag_cycles);
+
+  -------------------------------------------------------------------------------------------
+  -- fixed latency implementation
+  -------------------------------------------------------------------------------------------
+
+  -- mask rx_dreq to prevent reception
+  rx_dreq                           <= rx_dreq_i and rx_dreq_allow;
+  -- produce a pulse when SOF is timestamped, this pulse starts counter in clk_sys clock 
+  -- domain
+  U_sync_with_clk : gc_sync_ffs
+    port map (
+      clk_i          => clk_sys_i,
+      rst_n_i        => rst_n_i,
+      data_i         => fsm_in.sof,
+      synced_o       => timestamped);
+
+  -- introduce fixed latency, if configured to do so
+  p_fixed_latency_fsm : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        delay_state        <= DISABLED;
+        rx_latency_stored  <= (others=>'0');
+        rx_dreq_allow      <= '1';
+        delay_cnt          <= c_timestamper_delay;
+      else
+        case delay_state is
+          when DISABLED => 
+            if unsigned(rx_streamer_cfg_i.fixed_latency) /= c_fixed_latency_zero then
+              delay_state        <= ALLOW;
+            end if;
+            rx_latency_stored  <= (others=>'0');
+            delay_cnt          <= c_timestamper_delay;
+            rx_dreq_allow      <= '1';
+          when ALLOW =>
+            if unsigned(rx_streamer_cfg_i.fixed_latency) = c_fixed_latency_zero then
+              delay_state        <= DISABLED;
+            elsif(rx_latency_valid ='1') then
+              rx_dreq_allow     <= '0';
+              rx_latency_stored <= rx_latency;
+              delay_state       <= DELAY;
+            end if;
+            if(timestamped = '1') then
+              delay_cnt         <= c_timestamper_delay;
+            else
+              delay_cnt <= delay_cnt + 2;
+            end if;
+          when DELAY =>
+            if unsigned(rx_streamer_cfg_i.fixed_latency) <= delay_cnt + rx_latency_stored then
+              rx_latency_stored  <= (others=>'0');
+              rx_dreq_allow      <= '1';
+              delay_state        <= ALLOW;
+            else
+              delay_cnt <= delay_cnt + 2;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  -------------------------------------------------------------------------------------------
+  -- end of fixed latency implementation
+  -- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+  p_fsm : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state                  <= IDLE;
+        count                  <= (others => '0');
+        seq_no                 <= (others => '1');
+        detect_escapes         <= '0';
+        crc_en                 <= '0';
+        fifo_accept            <= '0';
+        fifo_drop              <= '0';
+        fifo_dvalid            <= '0';
+        pending_write          <= '0';
+        got_next_subframe      <= '0';
+        fifo_sync              <= '0';
+        fifo_last              <= '0';
+        tx_tag_valid           <= '0';
+        ser_count              <= (others => '0');
+        word_count             <= (others => '0');
+        sync_seq_no            <= '1';
+        rx_frame_p1_o          <= '0';
+        rx_lost_frames_cnt_o   <= (others => '0');
+        frames_lost            <= '0';
+        rx_latency             <= (others=>'0');
+        rx_latency_valid       <= '0';
+        blocks_lost            <= '0';
+        pack_data              <= (others=>'0');
+        is_vlan                <= '0';
+      else
+        case state is
+          when IDLE =>
+            detect_escapes     <= '0';
+            crc_en             <= '0';
+            count              <= (others => '0');
+            fifo_accept        <= '0';
+            fifo_drop          <= '0';
+            fifo_dvalid        <= '0';
+            pending_write      <= '0';
+            got_next_subframe  <='0';
+            ser_count          <= (others => '0');
+            fifo_sync          <='0';
+            fifo_last          <= '0';
+            word_count         <= (others => '0');
+            tx_tag_valid       <= '0';
+            rx_frame_p1_o      <= '0';
+            rx_lost_frames_cnt_o <= (others => '0');
+            frames_lost          <= '0';
+            blocks_lost          <= '0';
+            rx_latency           <= (others=>'0');
+            rx_latency_valid     <= '0';
+            is_vlan              <= '0';
+
+            if(fsm_in.sof = '1') then
+              state            <= HEADER;
+            end if;
+
+          when HEADER =>
+            if(fsm_in.eof = '1') then
+              state <= IDLE;
+            elsif(fsm_in.dvalid = '1') then
+              case count(7 downto 0) is
+                when x"00" =>
+                  if(fsm_in.data /= rx_streamer_cfg_i.mac_local(47 downto 32) nor (rx_streamer_cfg_i.accept_broadcasts = '1' and fsm_in.data /= x"ffff")) then
+                    state <= IDLE;
+                  end if;
+                  count <= count + 1;
+                when x"01" =>
+                  if(fsm_in.data /= rx_streamer_cfg_i.mac_local(31 downto 16) nor (rx_streamer_cfg_i.accept_broadcasts = '1' and fsm_in.data /= x"ffff")) then
+                    state <= IDLE;
+                  end if;
+                  count <= count + 1;
+                when x"02" =>
+                  if(fsm_in.data /= rx_streamer_cfg_i.mac_local(15 downto 0) nor (rx_streamer_cfg_i.accept_broadcasts = '1' and fsm_in.data /= x"ffff")) then
+                    state <= IDLE;
+                  end if;
+                  count <= count + 1;
+                when x"03" =>
+                  if(fsm_in.data /= rx_streamer_cfg_i.mac_remote(47 downto 32) and rx_streamer_cfg_i.filter_remote ='1') then
+                    state <= IDLE;
+                  end if;
+                  count <= count + 1;
+                when x"04" =>
+                  if(fsm_in.data /= rx_streamer_cfg_i.mac_remote(31 downto 16) and rx_streamer_cfg_i.filter_remote ='1') then
+                    state <= IDLE;
+                  end if;
+                  count <= count + 1;
+                when x"05" =>
+                  if(fsm_in.data /= rx_streamer_cfg_i.mac_remote(15 downto 0) and rx_streamer_cfg_i.filter_remote ='1') then
+                    state <= IDLE;
+                  end if;
+                  count <= count + 1;
+                when x"06" =>
+                  if(fsm_in.data = x"8100") then
+                    is_vlan <='1';
+                  elsif(fsm_in.data /= rx_streamer_cfg_i.ethertype) then
+                    state   <= IDLE;
+                    is_vlan <='0';
+                  end if;
+                  count <= count + 1;
+                when x"07" =>
+                  if(is_vlan = '0') then
+                    tx_tag_valid               <= fsm_in.data(15);
+                    tx_tag_cycles(27 downto 16)<= fsm_in.data(11 downto 0);
+                  end if;
+                  count <= count + 1;
+                when x"08" =>
+                  if(is_vlan = '0') then
+                    tx_tag_cycles(15 downto 0) <= fsm_in.data;
+                    count                      <= count + 1;
+                    crc_en                     <= '1';
+                    detect_escapes             <= '1';
+                    state                      <= FRAME_SEQ_ID;
+                    rx_frame_p1_o              <= '1';
+                  elsif(fsm_in.data /= rx_streamer_cfg_i.ethertype) then
+                    state <= IDLE;
+                  end if;
+                  count <= count + 1;
+                when x"09" =>
+                  tx_tag_valid               <= fsm_in.data(15);
+                  tx_tag_cycles(27 downto 16)<= fsm_in.data(11 downto 0);
+                   count <= count + 1;
+                when x"0A" =>
+                  tx_tag_cycles(15 downto 0) <= fsm_in.data;
+                  count                      <= count + 1;
+                  crc_en                     <= '1';
+                  detect_escapes             <= '1';
+                  state                      <= FRAME_SEQ_ID;
+                  rx_frame_p1_o              <= '1';
+                  count <= count + 1;
+                when others => null;
+              end case;
+            end if;
+
+          when FRAME_SEQ_ID =>
+            rx_frame_p1_o            <= '0';
+            if(fsm_in.eof = '1') then
+              state <= IDLE;
+            elsif(fsm_in.dvalid = '1') then
+              count               <= "000" & x"001"; -- use as subframe seq_no
+              state               <= PAYLOAD;
+              fifo_drop           <= '0';
+              fifo_accept         <= '0';
+              ser_count           <= (others => '0');
+              word_count          <= word_count + 1; -- count words, increment in advance
+              got_next_subframe   <= '1';
+              if(tx_tag_valid = '1') then
+                rx_latency_valid <= '1';
+                if(unsigned(tx_tag_cycles) > unsigned(rx_tag_cycles)) then
+                  rx_latency <= unsigned(rx_tag_cycles) - unsigned(tx_tag_cycles) + to_unsigned(125000000, 28);
+                else
+                  rx_latency <= unsigned(rx_tag_cycles) - unsigned(tx_tag_cycles);
+                end if;
+                tx_tag_valid <= '0';
+              else
+                rx_latency_valid <= '0';
+              end if;
+
+              if(std_logic_vector(seq_no) /= fsm_in.data(14 downto 0)) then
+                seq_no    <= unsigned(fsm_in.data(14 downto 0))+1;
+                if (sync_seq_no = '1') then -- sync to the first received seq_no
+                  sync_seq_no <= '0';
+                  frames_lost   <= '0';
+                  rx_lost_frames_cnt_o <= (others => '0');
+                else
+                  rx_lost_frames_cnt_o <= std_logic_vector(unsigned(fsm_in.data(14 downto 0)) - seq_no);
+                  frames_lost     <= '1';
+                end if;
+              else
+                seq_no    <= unsigned(seq_no + 1);
+                frames_lost <= '0';
+                rx_lost_frames_cnt_o <= (others => '0');
+              end if;
+            end if;
+
+          when SUBFRAME_HEADER =>
+            fifo_drop   <= '0';
+            fifo_accept <= '0';
+            ser_count <= (others => '0');
+
+            if(fsm_in.eof = '1') then
+              state <= IDLE;
+              got_next_subframe <= '0';
+              blocks_lost <= '0';
+            elsif (fsm_in.dvalid = '1' and is_escape = '1') then
+              got_next_subframe <= '1';
+
+              if(std_logic_vector(count) /= fsm_in.data(14 downto 0)) then
+                count     <= unsigned(fsm_in.data(14 downto 0))+1;
+                blocks_lost <= '1';
+              else
+                count    <= count + 1;
+                blocks_lost <= '0';
+              end if;
+              state <= PAYLOAD;
+            end if;
+
+          when PAYLOAD =>
+            frames_lost <= '0';
+            rx_lost_frames_cnt_o <= (others => '0');
+            rx_latency_valid <= '0';
+            fifo_sync <= got_next_subframe;
+
+            if(fsm_in.eof = '1') then
+              state       <= IDLE;
+              fifo_drop   <= '1';
+              fifo_accept <= '0';
+              got_next_subframe <= '0';
+              
+            elsif(fsm_in.dvalid = '1') then
+
+              
+              
+              if(is_escape = '1') then
+                ser_count <= (others => '0');
+                fifo_last <= '1';
+
+                got_next_subframe <= '1';
+
+                if(fsm_in.data(15) = '1') then
+                  
+                  if(std_logic_vector(count) /= fsm_in.data(14 downto 0)) then
+                    count     <= unsigned(fsm_in.data(14 downto 0));
+                    blocks_lost <= '1';
+                  else
+                    count     <= unsigned(count + 1);
+                    blocks_lost <= '0';
+                  end if;
+                  
+                  state <= PAYLOAD;
+
+                  fifo_accept   <= crc_match;      --_latched;
+                  fifo_drop     <= not crc_match;  --_latched;
+                  fifo_dvalid   <= pending_write and not fifo_dvalid;
+                  pending_write <= '0';
+                  
+                elsif fsm_in.data = x"0bad" then
+                  blocks_lost   <= '0';
+                  state       <= EOF;
+                  fifo_accept <= crc_match;      --_latched;
+                  fifo_drop   <= not crc_match;  --_latched;
+                  fifo_dvalid <= pending_write and not fifo_dvalid;
+                else
+                  blocks_lost   <= '0';
+                  state       <= EOF;
+                  fifo_drop   <= '1';
+                  fifo_accept <= '0';
+                end if;
+
+              else --of:  if(is_escape = '1' or word_count = g_expected_words_number) then
+
+                fifo_last   <= '0';
+                fifo_accept <= '0';
+                fifo_drop   <= '0';
+                blocks_lost   <= '0';
+
+                pack_data(to_integer(ser_count) * 16 + 15 downto to_integer(ser_count) * 16) <= fsm_in.data;
+
+                if(ser_count = g_data_width/16 - 1) then
+                  ser_count                                        <= (others => '0');
+
+                  if (ser_count = x"00") then -- ML: the case when g_data_width == 16
+                     fifo_sync <= got_next_subframe;
+                     fifo_data(g_data_width-1 downto 0)            <= pack_data(g_data_width-1 downto 0);
+                     fifo_dvalid <= not is_escape;
+                     pending_write <= '0';
+                  else
+                    ser_count                                        <= (others => '0');
+                    fifo_data(g_data_width-16-1 downto 0)            <= pack_data(g_data_width-16-1 downto 0);
+                    fifo_data(g_data_width-1 downto g_data_width-16) <= fsm_in.data;
+                    fifo_dvalid                                      <= '0';
+                    pending_write                                    <= '1';
+                  end if;
+                  if(word_count = g_expected_words_number) then
+                    state       <= EOF;
+                    fifo_accept <= '1'; 
+                    fifo_drop   <= '0'; 
+                    fifo_dvalid <= '1';
+                  else
+                    word_count <= word_count + 1;
+                  end if;
+                elsif(ser_count = g_data_width/16-2 and pending_write = '1') then
+                  pending_write <= '0';
+                  ser_count     <= ser_count + 1;
+                  fifo_dvalid   <= '1';
+                  fifo_sync <= got_next_subframe;
+                  got_next_subframe <= '0';
+                else
+                  ser_count   <= ser_count + 1;
+                  fifo_dvalid <= '0';
+                end if;
+                
+              end if;
+            else --of:  elsif(fsm_in.dvalid = '1') then
+              fifo_dvalid <= '0';
+            end if;
+
+            if(fifo_dvalid = '1') then
+              fifo_sync <= '0';
+            end if;
+            
+
+          when EOF =>
+            fifo_dvalid <= '0';
+            fifo_drop   <= '0';
+            fifo_accept <= '0';
+            state       <= IDLE;
+            
+        end case;
+      end if;
+    end if;
+  end process;
+
+  p_delay_fifo_accept : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      fifo_accept_d0 <= fifo_accept;
+    end if;
+  end process;
+
+  rx_lost_p1_o        <= frames_lost or blocks_lost;
+  rx_lost_blocks_p1_o <= blocks_lost;
+  rx_lost_frames_p1_o <= frames_lost;
+  rx_latency_o        <= std_logic_vector(rx_latency);
+  rx_latency_valid_o  <= rx_latency_valid;
+  crc_restart <= '1' when (state = FRAME_SEQ_ID or (is_escape = '1' and fsm_in.data(15) = '1')) else not rst_n_i;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrx_streamers_stats.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrx_streamers_stats.vhd
new file mode 100644
index 000000000..d2257ce57
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xrx_streamers_stats.vhd
@@ -0,0 +1,231 @@
+-------------------------------------------------------------------------------
+-- Title      : WR Recpetion Streamers statistics
+-- Project    : White Rabbit Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : xrx_streamers_stats.vhd
+-- Author     : Maciej Lipinski
+-- Company    : CERN
+-- Created    : 2017-04-19
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- This module provies the reception portion of statistics and
+-- allows to snapshot their values. See xrtx_streamers_stats for
+-- more detailed description.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2016 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+---------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+library work;
+use work.wishbone_pkg.all;  -- needed for t_wishbone_slave_in, etc
+use work.streamers_pkg.all; -- needed for streamers
+use work.wr_fabric_pkg.all; -- neede for :t_wrf_source_in, etc
+use work.wrcore_pkg.all;    -- needed for t_generic_word_array
+-- use work.wr_transmission_wbgen2_pkg.all;
+
+entity xrx_streamers_stats is
+  
+  generic (
+    -- Width of frame counters
+    g_cnt_width            : integer := 50; -- min:15, max:64, 50 bits should be ok for 50 years
+    g_acc_width            : integer := 64  -- max value 64
+    );
+  port (
+    clk_i                  : in std_logic;
+    rst_n_i                : in std_logic;
+
+    -- input signals from streamers
+    rcvd_frame_i           : in std_logic;
+    lost_block_i           : in std_logic;
+    lost_frame_i           : in std_logic;
+    lost_frames_cnt_i      : in std_logic_vector(14 downto 0);
+    rcvd_latency_i         : in  std_logic_vector(27 downto 0);
+    rcvd_latency_valid_i   : in  std_logic;
+    tm_time_valid_i        : in  std_logic;
+
+    snapshot_ena_i         : in std_logic := '0';
+    reset_stats_i          : in std_logic;
+    ----------------------- statistics ----------------------------------------
+    -- output statistics: tx/rx counters
+    rcvd_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+    lost_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+    lost_block_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0);
+    -- output statistics: latency
+    latency_cnt_o          : out std_logic_vector(g_cnt_width-1 downto 0);
+    latency_acc_overflow_o : out std_logic;
+    latency_acc_o          : out std_logic_vector(g_acc_width-1  downto 0);
+    latency_max_o          : out std_logic_vector(27  downto 0);
+    latency_min_o          : out std_logic_vector(27  downto 0)
+    );
+
+end xrx_streamers_stats;
+  
+architecture rtl of xrx_streamers_stats is
+
+
+  signal rcvd_frame_cnt    : unsigned(g_cnt_width-1  downto 0);
+  signal lost_frame_cnt    : unsigned(g_cnt_width-1  downto 0);
+  signal lost_block_cnt    : unsigned(g_cnt_width-1  downto 0);
+  signal latency_cnt       : unsigned(g_cnt_width-1  downto 0);
+
+  signal latency_max       : std_logic_vector(27  downto 0);
+  signal latency_min       : std_logic_vector(27  downto 0);
+  signal latency_acc       : unsigned(g_acc_width-1+1  downto 0);
+  signal latency_acc_overflow: std_logic;
+
+  -- snaphsot
+  signal rcvd_frame_cnt_d1    : unsigned(g_cnt_width-1  downto 0);
+  signal lost_frame_cnt_d1    : unsigned(g_cnt_width-1  downto 0);
+  signal lost_block_cnt_d1    : unsigned(g_cnt_width-1  downto 0);
+  signal latency_cnt_d1       : unsigned(g_cnt_width-1  downto 0);
+
+  signal latency_max_d1       : std_logic_vector(27  downto 0);
+  signal latency_min_d1       : std_logic_vector(27  downto 0);
+  signal latency_acc_d1       : unsigned(g_acc_width-1+1  downto 0);
+  signal latency_acc_overflow_d1: std_logic;
+
+  signal snapshot_ena_d1   : std_logic;
+
+begin
+
+  -------------------------------------------------------------------------------------------
+  -- frame/block statistics, i.e. lost, sent, received
+  -------------------------------------------------------------------------------------------
+  -- process that counts: receved/lost frames
+  p_cnts: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (rst_n_i = '0' or reset_stats_i = '1') then
+        rcvd_frame_cnt        <= (others => '0');
+        lost_frame_cnt        <= (others => '0');
+        lost_block_cnt        <= (others => '0');
+      else
+        -- count received frames
+        if(rcvd_frame_i = '1') then
+          rcvd_frame_cnt <= rcvd_frame_cnt + 1;
+        end if;
+        -- count lost frames
+        if(lost_frame_i = '1') then
+          lost_frame_cnt <= lost_frame_cnt + resize(unsigned(lost_frames_cnt_i),lost_frame_cnt'length);
+        end if;
+        -- count lost blocks
+        if(lost_block_i = '1') then
+          lost_block_cnt <= lost_block_cnt + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -------------------------------------------------------------------------------------------
+  -- latency statistics
+  -------------------------------------------------------------------------------------------
+  p_latency_stats: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (rst_n_i = '0' or reset_stats_i = '1') then
+        latency_max            <= (others => '0');
+        latency_min            <= (others => '1');
+        latency_acc            <= (others => '0');
+        latency_cnt            <= (others => '0');
+        latency_acc_overflow   <= '0';
+      else
+        if(rcvd_latency_valid_i = '1' and tm_time_valid_i = '1') then
+          if(latency_max < rcvd_latency_i) then
+            latency_max <= rcvd_latency_i;
+          end if;
+          if(latency_min > rcvd_latency_i) then
+            latency_min <= rcvd_latency_i;
+          end if;
+          if(latency_acc(g_acc_width) ='1') then
+            latency_acc_overflow   <= '1';
+          end if;
+          latency_cnt <= latency_cnt + 1;
+          latency_acc <= latency_acc + resize(unsigned(rcvd_latency_i),latency_acc'length);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -------------------------------------------------------------------------------------------
+  -- snapshot 
+  -------------------------------------------------------------------------------------------
+  -- snapshot is used to expose to user coherent value, so that the count for accumulated
+  -- latency is coherent with the accumulated latency and the average can be accurately 
+  -- calculated
+  -------------------------------------------------------------------------------------------
+
+  -- snapshot
+  p_stats_snapshot: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (rst_n_i = '0') then
+         snapshot_ena_d1         <= '0';
+         rcvd_frame_cnt_d1       <= (others=>'0');
+         lost_frame_cnt_d1       <= (others=>'0');
+         lost_block_cnt_d1       <= (others=>'0');
+         latency_cnt_d1          <= (others=>'0');
+
+         latency_max_d1          <= (others=>'0');
+         latency_min_d1          <= (others=>'0');
+         latency_acc_d1          <= (others=>'0');
+         latency_acc_overflow_d1 <= '0';
+      else
+        if(snapshot_ena_i = '1' and snapshot_ena_d1 = '0') then
+         rcvd_frame_cnt_d1       <= rcvd_frame_cnt;
+         lost_frame_cnt_d1       <= lost_frame_cnt;
+         lost_block_cnt_d1       <= lost_block_cnt;
+         latency_cnt_d1          <= latency_cnt;
+
+         latency_max_d1          <= latency_max;
+         latency_min_d1          <= latency_min;
+         latency_acc_d1          <= latency_acc;
+         latency_acc_overflow_d1 <= latency_acc_overflow;
+        end if;
+        snapshot_ena_d1 <= snapshot_ena_i;
+      end if;
+    end if;
+  end process;
+
+  -------------------------------------------------------------------------------------------
+  -- snapshot or current value
+  -------------------------------------------------------------------------------------------
+  rcvd_frame_cnt_o       <= std_logic_vector(rcvd_frame_cnt_d1) when (snapshot_ena_d1 = '1') else
+                            std_logic_vector(rcvd_frame_cnt);
+  lost_frame_cnt_o       <= std_logic_vector(lost_frame_cnt_d1) when (snapshot_ena_d1 = '1') else
+                            std_logic_vector(lost_frame_cnt);
+  lost_block_cnt_o       <= std_logic_vector(lost_block_cnt_d1) when (snapshot_ena_d1 = '1') else
+                            std_logic_vector(lost_block_cnt);
+  latency_max_o          <= latency_max_d1 when (snapshot_ena_d1 = '1') else
+                            latency_max;
+  latency_min_o          <= latency_min_d1 when (snapshot_ena_d1 = '1') else
+                            latency_min;
+  latency_acc_o          <= std_logic_vector(latency_acc_d1(g_acc_width-1 downto 0)) when (snapshot_ena_d1 = '1') else
+                            std_logic_vector(latency_acc(g_acc_width-1 downto 0));
+  latency_cnt_o          <= std_logic_vector(latency_cnt_d1) when (snapshot_ena_d1 = '1') else
+                            std_logic_vector(latency_cnt);
+  latency_acc_overflow_o <= latency_acc_overflow_d1  when (snapshot_ena_d1 = '1') else
+                            latency_acc_overflow;
+
+end rtl;
\ No newline at end of file
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xtx_streamer.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xtx_streamer.vhd
new file mode 100644
index 000000000..fea78ab7e
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xtx_streamer.vhd
@@ -0,0 +1,597 @@
+-------------------------------------------------------------------------------
+-- Title      : Reception streamer
+-- Project    : WR streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : xtx_streamer.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-11-02
+-- Platform   : FPGA-generic
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description: A simple core demonstrating how to encapsulate a continuous
+-- stream of data words into Ethernet frames, in a format that is accepted by
+-- the White Rabbit PTP core. More info in the documentation.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012-2017 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.streamers_priv_pkg.all;
+use work.streamers_pkg.all;
+
+entity xtx_streamer is
+  generic (
+    -- Width of data words on tx_data_i, must be multiple of 16 bits.
+    g_data_width : integer := 32;
+
+    -- Size of Tx buffer, in data words.
+    g_tx_buffer_size : integer := 256;
+
+    -- Minimum number of data words in the TX buffer that will trigger transmission of an
+    -- Ethernet frame. It cannot be breater than g_tx_buffer_size; it is recommended that
+    -- g_tx_buffer_size = 2 * g_tx_threshold.
+    -- Note that in order for a frame to be transmitted, the buffer must conatain at
+    -- least one complete block.
+    g_tx_threshold : integer := 128;
+
+    -- Maximum number of data words in a single Ethernet frame. It also defines
+    -- the maximum block size (since blocks can't be currently split across
+    -- multiple frames). It cannot be greater than g_tx_buffer_size
+    g_tx_max_words_per_frame : integer := 256;
+
+    -- Transmission timeout (in clk_sys_i cycles), after which the contents
+    -- of TX buffer are sent regardless of the amount of data that is currently
+    -- stored in the buffer, so that data in the buffer does not get stuck.
+    g_tx_timeout : integer := 1024;
+
+    -- DO NOT USE unless you know what you are doing
+    -- legacy stuff: the streamers initially used in Btrain did not check/insert the escape
+    -- code. This is justified if only one block of a known number of words is sent/expected
+    g_escape_code_disable : boolean := FALSE;
+
+    -- simulation mode: it is set to override the startaup-timer, the value with which 
+    -- the timer is overriden is set in the second generic 
+    g_simulation : integer :=0;
+    -- startup counter, used only in simulatin mode (value in 16ns cycles)
+    g_sim_startup_cnt : integer := 6250-- 100us
+    );
+
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    -- Endpoint/WRC interface - packet source
+    src_i : in  t_wrf_source_in;
+    src_o : out t_wrf_source_out;
+
+    ---------------------------------------------------------------------------
+    -- WRC Timing interface, used for latency measurement
+    -- Caution: uses clk_ref_i clock domain!
+    ---------------------------------------------------------------------------
+
+    -- White Rabbit reference clock
+    clk_ref_i : in std_logic := '0';
+
+    -- Time valid flag
+    tm_time_valid_i : in std_logic := '0';
+
+    -- TAI seconds
+    tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
+
+    -- Fractional part of the second (in clk_ref_i cycles)
+    tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
+
+    -- status of the link, in principle the tx can be done only if link is oK
+    link_ok_i                  : in std_logic := '1';
+    ---------------------------------------------------------------------------
+    -- User interface
+    ---------------------------------------------------------------------------
+
+    -- Data word to be sent.
+    tx_data_i : in std_logic_vector(g_data_width-1 downto 0);
+
+    -- 1 indicates that the tx_data_i contains a valid data word.
+    tx_valid_i : in std_logic;
+
+    -- Synchronous data request: if active, the user may send a data word in
+    -- the following clock cycle.
+    tx_dreq_o : out std_logic;
+
+    -- Last signal. Can be used to indicate the last data word in a larger
+    -- block of samples (see documentation for more details).
+    tx_last_p1_i : in std_logic := '1';
+
+    -- Flush input. When asserted, the streamer will immediatly send out all
+    -- the data that is stored in its TX buffer, ignoring g_tx_timeout.
+    tx_flush_p1_i : in std_logic := '0';
+
+    -- Reset sequence number. When asserted, the internal sequence number
+    -- generator used to detect loss of frames is reset to 0. Advanced feature.
+    tx_reset_seq_i : in std_logic := '0';
+    -- successfully sent streamer frame
+    tx_frame_p1_o : out std_logic;
+    -- Configuration
+    tx_streamer_cfg_i : in t_tx_streamer_cfg := c_tx_streamer_cfg_default
+    );
+
+end xtx_streamer;
+
+architecture rtl of xtx_streamer is
+
+  type t_tx_state is (IDLE, SOF, ETH_HEADER, FRAME_SEQ_ID, SUBFRAME_HEADER, PAYLOAD, CRC_WORD, PADDING, EOF);
+
+  constant c_min_packet_size : integer := 32;
+
+  signal tx_threshold_hit : std_logic;
+  signal tx_timeout_hit   : std_logic;
+  signal tx_flush_latched : std_logic;
+
+  signal tx_fifo_last, tx_fifo_we, tx_fifo_full, tx_fifo_empty, tx_fifo_rd : std_logic;
+  signal tx_fifo_q, tx_fifo_d                                              : std_logic_vector(g_data_width downto 0);
+  signal state                                                             : t_tx_state;
+  signal seq_no, count                                                     : unsigned(14 downto 0);
+  signal ser_count                                                         : unsigned(7 downto 0);
+  signal word_count                                                        : unsigned(11 downto 0); --2^12 = 4096*2 bytes (can accommodate jambo frame)
+  signal total_words                                                       : unsigned(10 downto 0);
+
+  signal timeout_counter : unsigned(11 downto 0);
+
+  signal pack_data : std_logic_vector(15 downto 0);
+
+  signal fsm_out, escaper, fab_src     : t_pipe;
+  signal fsm_escape, fsm_escape_enable : std_logic;
+
+  signal crc_en, crc_en_masked, crc_reset : std_logic;
+  signal crc_value                        : std_logic_vector(15 downto 0);
+
+  signal tx_almost_empty, tx_almost_full : std_logic;
+
+  signal buf_frame_count : unsigned(5 downto 0) := (others => '0');
+
+
+  signal tag_cycles                   : std_logic_vector(27 downto 0);
+  signal tag_valid, tag_valid_latched : std_logic;
+
+  signal link_ok_delay_cnt         : unsigned(25 downto 0);
+  constant c_link_ok_rst_delay     : unsigned(25 downto 0) := to_unsigned(62500000, 26);-- 1s
+  constant c_link_ok_rst_delay_sim : unsigned(25 downto 0) := to_unsigned(g_sim_startup_cnt, 26);
+
+begin  -- rtl
+
+  -------------------------------------------------------------------------------------------
+  -- check sanity of input generics
+  -------------------------------------------------------------------------------------------
+  assert g_tx_buffer_size >= g_tx_threshold
+    report "The size of the tx buffer must be greater or equal the tx threashold"
+    severity FAILURE;
+
+  assert g_tx_buffer_size >= g_tx_max_words_per_frame
+    report "The size of tx buffer must be greater or equal the max number of words in frame"
+    severity FAILURE;
+  -------------------------------------------------------------------------------------------
+
+  U_tx_crc_generator : gc_crc_gen
+    generic map (
+      g_polynomial              => x"1021",
+      g_init_value              => x"ffff",
+      g_residue                 => x"0000",
+      g_data_width              => 16,
+      g_sync_reset              => 1,
+      g_dual_width              => 0,
+      g_registered_match_output => false,
+      g_registered_crc_output   => false)
+    port map (
+      clk_i     => clk_sys_i,
+      rst_i     => crc_reset,
+      restart_i => '0',
+      en_i      => crc_en_masked,
+      data_i    => fsm_out.data,
+      half_i    => '0',
+      crc_o     => crc_value);
+
+  crc_en_masked <= crc_en and fsm_out.dvalid;
+
+  U_Fab_Source : xwb_fabric_source
+    port map (
+      clk_i     => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      src_i     => src_i,
+      src_o     => src_o,
+      addr_i    => c_WRF_DATA,
+      data_i    => fab_src.data,
+      dvalid_i  => fab_src.dvalid,
+      sof_i     => fab_src.sof,
+      eof_i     => fab_src.eof,
+      error_i   => '0',
+      bytesel_i => '0',
+      dreq_o    => fab_src.dreq);
+
+  fab_src.sof <= fsm_out.sof;
+  fab_src.eof <= fsm_out.eof;
+
+  
+  gen_escape: if (g_escape_code_disable = FALSE) generate
+    U_Insert_Escape : gc_escape_inserter
+      generic map (
+        g_data_width  => 16,
+        g_escape_code => x"cafe")
+      port map (
+        clk_i             => clk_sys_i,
+        rst_n_i           => rst_n_i,
+        d_i               => fsm_out.data,
+        d_insert_enable_i => fsm_escape_enable,
+        d_escape_i        => fsm_escape,
+        d_valid_i         => fsm_out.dvalid,
+        d_req_o           => fsm_out.dreq,
+
+        d_o       => fab_src.data,
+        d_valid_o => fab_src.dvalid,
+        d_req_i   => fab_src.dreq);
+  end generate gen_escape;
+  gen_no_escape: if (g_escape_code_disable = TRUE) generate
+    fab_src.data   <= fsm_out.data;
+    fab_src.dvalid <= fsm_out.dvalid;
+    fsm_out.dreq   <= fab_src.dreq;
+  end generate gen_no_escape;
+
+  tx_fifo_we <= tx_valid_i and not tx_fifo_full;
+  tx_fifo_d  <= tx_last_p1_i & tx_data_i;
+
+  U_TX_Buffer : generic_sync_fifo
+    generic map (
+      g_data_width             => g_data_width + 1,
+      g_size                   => g_tx_buffer_size,
+      g_with_almost_full       => true,
+      g_with_almost_empty      => true,
+      g_almost_empty_threshold => g_tx_threshold,
+      g_almost_full_threshold  => g_tx_buffer_size - 2,
+      g_show_ahead             => true)
+    port map (
+      rst_n_i        => rst_n_i,
+      clk_i          => clk_sys_i,
+      d_i            => tx_fifo_d,
+      we_i           => tx_fifo_we,
+      q_o            => tx_fifo_q,
+      rd_i           => tx_fifo_rd,
+      empty_o        => tx_fifo_empty,
+      full_o         => tx_fifo_full,
+      almost_empty_o => tx_almost_empty,
+      almost_full_o  => tx_almost_full
+      );
+  tx_fifo_rd       <= '1' when (state = PAYLOAD    and ser_count = g_data_width/16-1 and 
+                          fsm_out.dreq = '1' and tx_fifo_empty = '0')         else
+                      '0';
+  tx_threshold_hit <= '1' when tx_almost_empty = '0' and (buf_frame_count /= 0) else '0';
+  tx_fifo_last     <= tx_fifo_q(g_data_width);
+
+  U_Timestamper : pulse_stamper
+    port map (
+      clk_ref_i       => clk_ref_i,
+      clk_sys_i       => clk_sys_i,
+      rst_n_i         => rst_n_i,
+      pulse_a_i       => fsm_out.sof,
+      tm_time_valid_i => tm_time_valid_i,
+      tm_tai_i        => tm_tai_i,
+      tm_cycles_i     => tm_cycles_i,
+      tag_tai_o       => open,
+      tag_cycles_o    => tag_cycles,
+      tag_valid_o     => tag_valid);
+
+  p_frame_counter : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        buf_frame_count <= (others => '0');
+      else
+        if(tx_fifo_we = '1' and tx_last_p1_i = '1' and (tx_fifo_rd = '0' or tx_fifo_last = '0')) then
+          buf_frame_count <= buf_frame_count+ 1;
+        elsif((tx_fifo_we = '0' or tx_last_p1_i = '0') and (tx_fifo_rd = '1' and tx_fifo_last = '1')) then
+          buf_frame_count <= buf_frame_count - 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_tx_timeout : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        timeout_counter <= (others => '0');
+        tx_timeout_hit  <= '0';
+      else
+        if(tx_fifo_empty = '0' and tx_threshold_hit = '0') then
+          timeout_counter <= timeout_counter + 1;
+        else
+          timeout_counter <= (others => '0');
+        end if;
+
+        if(timeout_counter = g_tx_timeout) then
+          tx_timeout_hit <= '1';
+        else
+          tx_timeout_hit <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_fsm : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state          <= IDLE;
+        fsm_out.sof    <= '0';
+        fsm_out.eof    <= '0';
+        fsm_out.dvalid <= '0';
+        fsm_out.data   <= (others => '0');
+        count          <= (others => '0');
+        seq_no         <= (others => '0');
+        word_count     <= (others => '0');
+        crc_en         <= '0';
+        crc_reset      <= '1';
+        tx_frame_p1_o     <= '0';
+        tag_valid_latched <= '0';
+        tx_flush_latched  <= '0';
+        fsm_escape_enable <= '0';
+        fsm_escape        <= '0';
+        ser_count         <= (others => '0');
+      else
+        if(tx_reset_seq_i = '1') then
+          seq_no <= (others => '0');
+        end if;
+        if(tag_valid = '1') then 
+          tag_valid_latched <= '1'; -- overriden in IDLE
+        end if;
+        tx_flush_latched <= '0';-- overriden in IDLE
+
+        case state is
+          when IDLE =>
+            tag_valid_latched <= '0';
+            tx_flush_latched  <= tx_flush_p1_i or tx_timeout_hit;
+            crc_en         <= '0';
+            crc_reset      <= '0';
+            fsm_out.eof    <= '0';
+            tx_frame_p1_o  <= '0';
+
+            if(fsm_out.dreq = '1' and (tx_flush_latched = '1' or tx_flush_p1_i = '1' or tx_threshold_hit = '1')) then
+              state       <= SOF;
+              fsm_out.sof <= '1';
+            end if;
+
+            fsm_escape_enable <= '0';
+            fsm_escape        <= '0';
+
+          when SOF =>
+            fsm_out.sof <= '0';
+            ser_count   <= (others => '0');
+            state       <= ETH_HEADER;
+            count       <= (others => '0');
+            word_count  <= (others => '0');
+
+          when ETH_HEADER =>
+            if(fsm_out.dreq = '1') then
+              case count(7 downto 0) is
+                when x"00" =>
+                  fsm_out.data <= tx_streamer_cfg_i.mac_target(47 downto 32);
+                  count        <= count + 1;
+                when x"01" =>
+                  fsm_out.data <= tx_streamer_cfg_i.mac_target(31 downto 16);
+                  count        <= count + 1;
+                when x"02" =>
+                  fsm_out.data <= tx_streamer_cfg_i.mac_target(15 downto 0);
+                  count        <= count + 1;
+                when x"03" =>
+                  fsm_out.data <= tx_streamer_cfg_i.mac_local(47 downto 32);
+                  count        <= count + 1;
+                when x"04" =>
+                  fsm_out.data <= tx_streamer_cfg_i.mac_local(31 downto 16);
+                  count        <= count + 1;
+                when x"05" =>
+                  fsm_out.data <= tx_streamer_cfg_i.mac_local(15 downto 0);
+                  count        <= count + 1;
+                when x"06" =>
+                  if(tx_streamer_cfg_i.qtag_ena = '0') then
+                    fsm_out.data <= tx_streamer_cfg_i.ethertype;
+                  else
+                    fsm_out.data <= x"8100";
+                  end if;
+                  count        <= count + 1;
+                when x"07" =>
+                  if(tx_streamer_cfg_i.qtag_ena = '0') then
+                    fsm_out.data <= tag_valid_latched & "000" & tag_cycles(27 downto 16);
+                  else
+                    fsm_out.data <= tx_streamer_cfg_i.qtag_prio & '0' & tx_streamer_cfg_i.qtag_vid;
+                  end if;
+                  count        <= count + 1;
+                when x"08" =>
+                  if(tx_streamer_cfg_i.qtag_ena = '0') then
+                    fsm_out.data <= tag_cycles(15 downto 0);
+                    state        <= FRAME_SEQ_ID;
+                  else
+                    fsm_out.data <= tx_streamer_cfg_i.ethertype;
+                  end if;
+                  count        <= count + 1;
+                when x"09" =>
+                  fsm_out.data <= tag_valid_latched & "000" & tag_cycles(27 downto 16);
+                  count        <= count + 1;
+                when x"0A" =>
+                  fsm_out.data <= tag_cycles(15 downto 0);
+                  state        <= FRAME_SEQ_ID;
+                  count        <= count + 1;
+                when others =>
+                  fsm_out.data <= (others => 'X');
+                  count        <= (others => 'X');
+              end case;
+              fsm_out.dvalid <= '1';
+            else
+              fsm_out.dvalid <= '0';
+            end if;
+          when FRAME_SEQ_ID =>
+            if(fsm_out.dreq = '1') then
+              fsm_out.data      <= '1' & std_logic_vector(seq_no);
+              seq_no            <= seq_no + 1;
+              count             <= "000" & x"001";
+              fsm_out.dvalid    <= '1';
+              fsm_escape        <= '0';
+              fsm_escape_enable <= '1';
+              crc_en            <= '1';
+              crc_reset         <= '0';
+              state             <= PAYLOAD;
+            else
+              fsm_out.dvalid    <= '0';
+            end if;
+          
+          when SUBFRAME_HEADER =>
+            crc_en    <= '1';
+            crc_reset <= '0';
+
+            if(fsm_out.dreq = '1') then
+              fsm_out.dvalid    <= '1';
+              fsm_escape        <= '1';
+              fsm_escape_enable <= '1';
+              fsm_out.data      <= '1' & std_logic_vector(count);
+              count             <= count + 1;
+              state             <= PAYLOAD;
+            else
+              fsm_out.dvalid <= '0';
+              fsm_out.data   <= (others => 'X');
+            end if;
+
+          when PAYLOAD =>
+            fsm_escape <= '0';
+
+            if(fsm_out.dreq = '1') then
+              -- next subframe?
+              if(tx_fifo_empty = '1' or (ser_count = g_data_width/16-1 and tx_fifo_last = '1')) then
+                state <= CRC_WORD;
+              end if;
+
+              if(ser_count = g_data_width/16-1) then
+                word_count   <= word_count + 1;
+                ser_count    <= (others => '0');
+              else
+                ser_count    <= ser_count + 1;
+              end if;
+
+              fsm_out.data   <= tx_fifo_q((to_integer(ser_count) + 1)* 16 -1 downto to_integer(ser_count) * 16);
+              fsm_out.dvalid <= not tx_fifo_empty;
+            else
+              fsm_out.data   <= (others => 'X');
+              fsm_out.dvalid <= '0';
+            end if;
+
+          when CRC_WORD =>
+            crc_en    <= '0';
+            ser_count <= (others => '0');
+
+            if(fsm_out.dreq = '1') then
+              fsm_out.dvalid <= '1';
+              fsm_out.data   <= crc_value;
+
+              crc_reset <= '1';
+
+              if(tx_fifo_empty = '1' or word_count >= g_tx_max_words_per_frame) then
+                state <= PADDING;
+              else
+                state <= SUBFRAME_HEADER;
+              end if;
+            else
+              fsm_out.data   <= (others => 'X');
+              fsm_out.dvalid <= '0';
+            end if;
+
+          when PADDING =>
+            if(fsm_out.dreq = '1') then
+              fsm_escape     <= '1';
+              fsm_out.dvalid <= '1';
+              fsm_out.data   <= x"0bad"; 
+              if(total_words >= c_min_packet_size) then
+                state <= EOF;
+              end if;
+              crc_reset <= '0';
+            else
+              fsm_out.dvalid <= '0';
+              fsm_out.data   <= (others => 'X');
+            end if;
+            
+          when EOF =>
+            fsm_out.dvalid <= '0';
+            if(fsm_out.dreq = '1') then
+              fsm_out.eof <= '1';
+              tx_frame_p1_o  <= '1';
+              state       <= IDLE;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  p_count_words : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        total_words <= (others => '0');
+      else
+        if fsm_out.sof = '1' then
+          total_words <= (others => '0');
+        elsif fsm_out.dvalid = '1' then
+          total_words <= total_words +1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -- after reset, leave some time before accepting requests. This delay 
+  -- is dependent on link_ok signal. This is because after startup (and
+  -- any reset possibly) the PHY first shows link_ok but it is latter 
+  -- restarted by softare... it is a bit of a mess in which we better
+  -- not send anything. Once this startup is done, we only relay on 
+  -- link_ok, i.e. we do not accept requests when link_ok is false.
+  -- During operation (i.e. after start-up/reset, the behaviour of link_ok
+  -- signal is satisfactory
+  p_delay_reset: process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if rst_n_i = '0' then
+          if(g_simulation = 1) then
+            link_ok_delay_cnt     <= c_link_ok_rst_delay_sim;
+          else
+            link_ok_delay_cnt     <= c_link_ok_rst_delay;
+          end if;
+        else
+          -- first initial moments of link_ok_i high are ignored
+          if(link_ok_i = '1' and link_ok_delay_cnt > 0) then
+            link_ok_delay_cnt     <= link_ok_delay_cnt-1;
+          end if;
+        end if;
+      end if;
+    end process;
+
+  tx_dreq_o <= '0' when (link_ok_delay_cnt > 0) else
+               (not tx_almost_full) and link_ok_i;
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xtx_streamers_stats.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xtx_streamers_stats.vhd
new file mode 100644
index 000000000..983e4e640
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xtx_streamers_stats.vhd
@@ -0,0 +1,125 @@
+-------------------------------------------------------------------------------
+-- Title      : WR tx streamers statistics
+-- Project    : WR streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : xrtx_streamers_stats.vhd
+-- Author     : Maciej Lipinski
+-- Company    : CERN
+-- Created    : 2017-04-19
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- This module provies the reception portion of statistics and
+-- allows to snapshot their values. See xrtx_streamers_stats for
+-- more detailed description.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2017 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+library work;
+use work.wishbone_pkg.all;  -- needed for t_wishbone_slave_in, etc
+use work.streamers_pkg.all; -- needed for streamers
+use work.wr_fabric_pkg.all; -- neede for :t_wrf_source_in, etc
+use work.wrcore_pkg.all;    -- needed for t_generic_word_array
+-- use work.wr_transmission_wbgen2_pkg.all;
+
+entity xtx_streamers_stats is
+  
+  generic (
+    -- Width of frame counters
+    g_cnt_width            : integer := 32 -- minimum 15 bits, max 32
+    );
+  port (
+    clk_i                  : in std_logic;
+    rst_n_i                : in std_logic;
+
+    -- input signals from streamers
+    sent_frame_i           : in std_logic;
+
+    -- statistic control
+    reset_stats_i          : in std_logic;
+    snapshot_ena_i         : in std_logic := '0';
+    ----------------------- statistics ----------------------------------------
+    -- output statistics: tx/rx counters
+    sent_frame_cnt_o       : out std_logic_vector(g_cnt_width-1 downto 0)
+  );
+
+end xtx_streamers_stats;
+  
+architecture rtl of xtx_streamers_stats is
+
+  signal sent_frame_cnt    : unsigned(g_cnt_width-1  downto 0);
+  signal sent_frame_cnt_d1 : unsigned(g_cnt_width-1  downto 0);
+  signal snapshot_ena_d1   : std_logic;
+begin
+
+  -------------------------------------------------------------------------------------------
+  -- frame/block statistics, i.e. lost, sent, received
+  -------------------------------------------------------------------------------------------
+  -- process that counts
+  p_cnts: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (rst_n_i = '0' or reset_stats_i = '1') then
+        sent_frame_cnt        <= (others => '0');
+      else
+        -- count sent frames
+        if(sent_frame_i = '1') then
+          sent_frame_cnt <= sent_frame_cnt + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -------------------------------------------------------------------------------------------
+  -- snapshot 
+  -------------------------------------------------------------------------------------------
+  -- snapshot is used to expose to user coherent value, so that the count for accumulated
+  -- latency is coherent with the accumulated latency and the average can be accurately 
+  -- calculated
+  -------------------------------------------------------------------------------------------
+  p_stats_snapshot: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (rst_n_i = '0') then
+         snapshot_ena_d1         <= '0';
+         sent_frame_cnt_d1       <= (others=>'0');
+      else
+        if(snapshot_ena_i = '1' and snapshot_ena_d1 = '0') then
+         sent_frame_cnt_d1       <= sent_frame_cnt;
+        end if;
+        snapshot_ena_d1 <= snapshot_ena_i;
+      end if;
+    end if;
+  end process;
+
+  -------------------------------------------------------------------------------------------
+  -- snapshot or current value
+  -------------------------------------------------------------------------------------------
+  sent_frame_cnt_o       <= std_logic_vector(sent_frame_cnt_d1) when (snapshot_ena_d1 = '1') else
+                            std_logic_vector(sent_frame_cnt);
+
+end rtl;
\ No newline at end of file
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xwr_streamers.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xwr_streamers.vhd
new file mode 100644
index 000000000..774a54a37
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/xwr_streamers.vhd
@@ -0,0 +1,467 @@
+-------------------------------------------------------------------------------
+-- Title      : WR Streamrs
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : xwr_streamers.vhd (renamed from xwr_transmission.vhd)
+-- Author     : Maciej Lipinski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-- Created    : 2016-05-30
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- This module is a top-level entity for WR streamers to be used conveniently
+-- in application. It is inlcluded in the board top entity of wr-cores as one
+-- of transportation means.
+--
+-- It allows to send and receive streames of data over Ethernet network. In
+-- other words, it provides communication over Ethernet network that looks as
+-- FIFO: one one node (e.g. SPEC, the user writes to tx streamer words of 
+-- configureable size. These words are received by the rx streamer in another
+-- node (e.g. SVEC) in the same order. 
+--
+-- This module wraps WR_Streamers-related stuff: i.e.
+-- 1) IP core modules provided in wr-cores: xtx_streamer, xrx_streamer,
+--    xrtx_streamers_stats
+-- 2) wishbone registers that provide access to the statistics and streamer's
+--    control/status registers.
+--
+-- This module interfaces:
+-- 1) WR PTP Core for transmission/reception of raw ethernet frames
+-- 2) Application-specific module for transmission/reception of data
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2016 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+---------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+library work;
+use work.wishbone_pkg.all;  -- needed for t_wishbone_slave_in, etc
+use work.streamers_pkg.all; -- needed for streamers and  c_WR_TRANS_ARR_SIZE_*
+use work.wr_fabric_pkg.all; -- needed for :t_wrf_source_in, etc
+use work.wrcore_pkg.all;    -- needed for t_generic_word_array
+use work.wr_streamers_wbgen2_pkg.all;
+use work.streamers_priv_pkg.all;
+
+entity xwr_streamers is
+  generic (
+    -- Indicates whether this module instantiates both streamers (rx and tx) or only one
+    -- of them. An application that only receives or only transmits might want to use
+    -- RX_ONLY or TX_ONLY mode to save resources.
+    g_streamers_op_mode        : t_streamers_op_mode  := TX_AND_RX;
+    -----------------------------------------------------------------------------------------
+    -- Transmission/reception parameters
+    -----------------------------------------------------------------------------------------
+    g_tx_streamer_params       : t_tx_streamer_params := c_tx_streamer_params_defaut;
+    g_rx_streamer_params       : t_rx_streamer_params := c_rx_streamer_params_defaut;
+    -----------------------------------------------------------------------------------------
+    -- Statistics config
+    -----------------------------------------------------------------------------------------
+    -- width of counters: frame rx/tx/lost, block lost, counter of accumuted latency
+    -- (min:15, max:64, 50 bits should be ok for 50 years)
+    g_stats_cnt_width          : integer := 50;
+    -- width of latency accumulator (max value 64)
+    g_stats_acc_width          : integer := 64;
+    -----------------------------------------------------------------------------------------
+    -- WB I/F configuration
+    -----------------------------------------------------------------------------------------
+    g_slave_mode               : t_wishbone_interface_mode      := CLASSIC;
+    g_slave_granularity        : t_wishbone_address_granularity := BYTE;
+    g_simulation               : integer := 0
+    );
+
+  port (
+    clk_sys_i                  : in std_logic;
+    rst_n_i                    : in std_logic;
+
+    ---------------------------------------------------------------------------
+    -- WR tx/rx interface
+    ---------------------------------------------------------------------------
+    -- Tx
+    src_i                      : in  t_wrf_source_in;
+    src_o                      : out t_wrf_source_out;
+    -- Rx
+    snk_i                      : in  t_wrf_sink_in;
+    snk_o                      : out t_wrf_sink_out;
+
+    ---------------------------------------------------------------------------
+    -- User tx interface
+    ---------------------------------------------------------------------------
+    -- Data word to be sent.
+    tx_data_i                  : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0);
+    -- 1 indicates that the tx_data_i contains a valid data word.
+    tx_valid_i                 : in std_logic;
+    -- Synchronous data request: if active, the user may send a data word in
+    -- the following clock cycle.
+    tx_dreq_o                  : out std_logic;
+    -- Last signal. Can be used to indicate the last data word in a larger
+    -- block of samples (see documentation for more details).
+    tx_last_p1_i               : in std_logic := '1';
+    -- Flush input. When asserted, the streamer will immediatly send out all
+    -- the data that is stored in its TX buffer, ignoring g_tx_timeout.
+    tx_flush_p1_i              : in std_logic := '0';
+
+    ---------------------------------------------------------------------------
+    -- User rx interface
+    ---------------------------------------------------------------------------
+    -- 1 indicates the 1st word of the data block on rx_data_o.
+    rx_first_p1_o              : out std_logic;
+    -- 1 indicates the last word of the data block on rx_data_o.
+    rx_last_p1_o               : out std_logic;
+    -- Received data.
+    rx_data_o                  : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+    -- 1 indicted that rx_data_o is outputting a valid data word.
+    rx_valid_o                 : out std_logic;
+    -- Synchronous data request input: when 1, the streamer may output another
+    -- data word in the subsequent clock cycle.
+    rx_dreq_i                  : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- WRC Timing interface, used for latency measurement
+    ---------------------------------------------------------------------------
+
+    -- White Rabbit reference clock
+    clk_ref_i                  : in std_logic := '0';
+    -- Time valid flag
+    tm_time_valid_i            : in std_logic := '0';
+    -- TAI seconds
+    tm_tai_i                   : in std_logic_vector(39 downto 0) := x"0000000000";
+    -- Fractional part of the second (in clk_ref_i cycles)
+    tm_cycles_i                : in std_logic_vector(27 downto 0) := x"0000000";
+
+    -- status of the link, in principle the tx can be done only if link is oK
+    link_ok_i                  : in std_logic;
+    -- wishbone interface 
+    wb_slave_i                 : in  t_wishbone_slave_in := cc_dummy_slave_in;
+    wb_slave_o                 : out t_wishbone_slave_out;
+
+    snmp_array_o               : out t_generic_word_array(c_WR_STREAMERS_ARR_SIZE_OUT-1 downto 0);
+    snmp_array_i               : in  t_generic_word_array(c_WR_STREAMERS_ARR_SIZE_IN -1 downto 0);
+
+    -----------------------------------------------------------------------------------------
+    -- Transmission and Reception configuration
+    -----------------------------------------------------------------------------------------
+    tx_streamer_cfg_i          : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
+    rx_streamer_cfg_i          : in t_rx_streamer_cfg := c_rx_streamer_cfg_default
+    );
+
+end xwr_streamers;
+
+architecture rtl of xwr_streamers is
+
+  signal to_wb              : t_wr_streamers_in_registers;
+  signal from_wb            : t_wr_streamers_out_registers;
+  signal dbg_word                : std_logic_vector(31 downto 0);
+  signal start_bit               : std_logic_vector(from_wb.dbg_ctrl_start_byte_o'length-1+3 downto 0);
+  signal rx_data                 : std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+  signal wb_regs_slave_in        : t_wishbone_slave_in;
+  signal wb_regs_slave_out       : t_wishbone_slave_out;  
+  signal tx_frame                : std_logic;
+  signal reset_time_tai          : std_logic_vector(39 downto 0);
+  signal latency_acc             : std_logic_vector(g_stats_acc_width-1 downto 0);
+  signal latency_cnt             : std_logic_vector(g_stats_cnt_width-1 downto 0);
+  signal sent_frame_cnt_out      : std_logic_vector(g_stats_cnt_width-1 downto 0);
+  signal rcvd_frame_cnt_out      : std_logic_vector(g_stats_cnt_width-1 downto 0);
+  signal lost_frame_cnt_out      : std_logic_vector(g_stats_cnt_width-1 downto 0);
+  signal lost_block_cnt_out      : std_logic_vector(g_stats_cnt_width-1 downto 0);
+  signal rx_valid                : std_logic;
+
+  signal rx_latency_valid        : std_logic;
+  signal rx_latency              : std_logic_vector(27 downto 0);
+  signal rx_lost_frames          : std_logic;
+  signal rx_lost_frames_cnt      : std_logic_vector(14 downto 0);
+  signal rx_lost_blocks          : std_logic;
+  signal rx_frame                : std_logic;
+
+  signal tx_streamer_cfg         : t_tx_streamer_cfg;
+  signal rx_streamer_cfg         : t_rx_streamer_cfg;
+
+  -- for code cleanness
+  constant c_cw              : integer := g_stats_cnt_width;
+  constant c_aw              : integer := g_stats_acc_width;
+begin
+
+  -------------------------------------------------------------------------------------------
+  -- Instantiate transmission streamer, if configured to do so
+  -------------------------------------------------------------------------------------------
+  gen_tx: if(g_streamers_op_mode=TX_ONLY OR g_streamers_op_mode=TX_AND_RX) generate
+    U_TX: xtx_streamer
+      generic map(
+        g_data_width             => g_tx_streamer_params.data_width,
+        g_tx_buffer_size         => g_tx_streamer_params.buffer_size,
+        g_tx_threshold           => g_tx_streamer_params.threshold,
+        g_tx_max_words_per_frame => g_tx_streamer_params.max_words_per_frame,
+        g_tx_timeout             => g_tx_streamer_params.timeout,
+        g_escape_code_disable    => g_tx_streamer_params.escape_code_disable,
+        g_simulation             => g_simulation)
+      port map(
+        clk_sys_i                => clk_sys_i,
+        rst_n_i                  => rst_n_i,
+        src_i                    => src_i,
+        src_o                    => src_o,
+        clk_ref_i                => clk_ref_i,
+        tm_time_valid_i          => tm_time_valid_i,
+        tm_tai_i                 => tm_tai_i,
+        tm_cycles_i              => tm_cycles_i,
+        link_ok_i                => link_ok_i,
+        tx_data_i                => tx_data_i,
+        tx_valid_i               => tx_valid_i,
+        tx_dreq_o                => tx_dreq_o,
+        tx_last_p1_i             => tx_last_p1_i,
+        tx_flush_p1_i            => tx_flush_p1_i,
+        tx_reset_seq_i           => from_wb.sscr1_rst_seq_id_o,
+        tx_frame_p1_o            => tx_frame,
+        tx_streamer_cfg_i        => tx_streamer_cfg);
+  end generate gen_tx;
+
+  gen_not_tx: if(g_streamers_op_mode=RX_ONLY) generate
+    src_o      <= c_dummy_snk_in;
+    tx_dreq_o  <= '0';
+    tx_frame   <= '0';
+  end generate gen_not_tx;
+
+  -------------------------------------------------------------------------------------------
+  -- -- Instantiate reception streamer, if configured to do so
+  -------------------------------------------------------------------------------------------
+  gen_rx: if(g_streamers_op_mode=RX_ONLY OR g_streamers_op_mode=TX_AND_RX) generate
+    U_RX: xrx_streamer
+      generic map(
+        g_data_width             => g_rx_streamer_params.data_width,
+        g_buffer_size            => g_rx_streamer_params.buffer_size,
+        g_escape_code_disable    => g_rx_streamer_params.escape_code_disable,
+        g_expected_words_number  => g_rx_streamer_params.expected_words_number
+        )
+      port map(
+        clk_sys_i                => clk_sys_i,
+        rst_n_i                  => rst_n_i,
+        snk_i                    => snk_i,
+        snk_o                    => snk_o,
+        clk_ref_i                => clk_ref_i,
+        tm_time_valid_i          => tm_time_valid_i,
+        tm_tai_i                 => tm_tai_i,
+        tm_cycles_i              => tm_cycles_i,
+        rx_first_p1_o            => rx_first_p1_o,
+        rx_last_p1_o             => rx_last_p1_o,
+        rx_data_o                => rx_data,
+        rx_valid_o               => rx_valid,
+        rx_dreq_i                => rx_dreq_i,
+        rx_lost_p1_o             => rx_lost_blocks,
+        rx_lost_frames_p1_o      => rx_lost_frames,
+        rx_lost_frames_cnt_o     => rx_lost_frames_cnt,
+        rx_latency_o             => rx_latency,
+        rx_latency_valid_o       => rx_latency_valid,
+        rx_frame_p1_o            => rx_frame,
+        rx_streamer_cfg_i        => rx_streamer_cfg);
+  end generate gen_rx;
+  gen_not_rx: if(g_streamers_op_mode=TX_ONLY) generate
+    snk_o         <= c_dummy_src_in;
+    rx_first_p1_o <= '0';
+    rx_last_p1_o  <= '0';
+    rx_data       <= (others => '0');
+    rx_valid      <= '0';
+  end generate gen_not_rx;
+
+  -------------------------------------------------------------------------------------------
+  -- Instantiate statistics module - it calculates statistics of rx/tx frames
+  -------------------------------------------------------------------------------------------
+  U_STATS: xrtx_streamers_stats
+    generic map(
+      g_streamers_op_mode      => g_streamers_op_mode,
+      g_cnt_width              => g_stats_cnt_width,
+      g_acc_width              => g_stats_acc_width
+      )
+    port map(
+      clk_i                    => clk_sys_i,
+      rst_n_i                  => rst_n_i,
+      sent_frame_i             => tx_frame,
+      rcvd_frame_i             => rx_frame,
+      lost_frame_i             => rx_lost_frames,
+      lost_block_i             => rx_lost_blocks,
+      lost_frames_cnt_i        => rx_lost_frames_cnt,
+      rcvd_latency_i           => rx_latency,
+      rcvd_latency_valid_i     => rx_latency_valid,
+      clk_ref_i                => clk_ref_i,
+      tm_time_valid_i          => tm_time_valid_i,
+      tm_tai_i                 => tm_tai_i,
+      tm_cycles_i              => tm_cycles_i,
+      reset_stats_i            => from_wb.sscr1_rst_stats_o,
+      snapshot_ena_i           => from_wb.sscr1_snapshot_stats_o,
+      reset_time_tai_o         => reset_time_tai,
+      reset_time_cycles_o      => to_wb.sscr1_rst_ts_cyc_i,
+      sent_frame_cnt_o         => sent_frame_cnt_out,
+      rcvd_frame_cnt_o         => rcvd_frame_cnt_out,
+      lost_frame_cnt_o         => lost_frame_cnt_out,
+      lost_block_cnt_o         => lost_block_cnt_out,
+      latency_cnt_o            => latency_cnt,
+      latency_acc_o            => latency_acc,
+      latency_max_o            => to_wb.rx_stat0_rx_latency_max_i,
+      latency_min_o            => to_wb.rx_stat1_rx_latency_min_i,
+      latency_acc_overflow_o   => to_wb.sscr1_rx_latency_acc_overflow_i,
+      snmp_array_o             => snmp_array_o(c_WRS_STATS_ARR_SIZE_OUT-1 downto 0),
+      snmp_array_i             => snmp_array_i
+      );
+
+  to_wb.sscr2_rst_ts_tai_lsb_i             <= reset_time_tai(31 downto 0);
+  to_wb.sscr3_rst_ts_tai_msb_i             <= reset_time_tai(39 downto 32);
+
+  assert (g_stats_acc_width <= 64 and g_stats_acc_width > 32)
+    report "g_stats_acc_width (c_aw) must be between 33 and 64" severity error;
+  assert (g_stats_cnt_width <= 64 and g_stats_cnt_width > 32)
+    report "g_stats_cnt_width (c_cw) must be between 33 and 64" severity error;
+
+  to_wb.tx_stat2_tx_sent_cnt_lsb_i                             <= sent_frame_cnt_out(31     downto 0);
+  to_wb.tx_stat3_tx_sent_cnt_msb_i        (c_cw-32-1 downto 0) <= sent_frame_cnt_out(c_cw-1 downto 32);
+  to_wb.rx_stat4_rx_rcvd_cnt_lsb_i                             <= rcvd_frame_cnt_out(31     downto 0);
+  to_wb.rx_stat5_rx_rcvd_cnt_msb_i        (c_cw-32-1 downto 0) <= rcvd_frame_cnt_out(c_cw-1 downto 32);
+  to_wb.rx_stat6_rx_loss_cnt_lsb_i                             <= lost_frame_cnt_out(31     downto 0);
+  to_wb.rx_stat7_rx_loss_cnt_msb_i        (c_cw-32-1 downto 0) <= lost_frame_cnt_out(c_cw-1 downto 32);
+  to_wb.rx_stat8_rx_lost_block_cnt_lsb_i                       <= lost_block_cnt_out(31     downto 0);
+  to_wb.rx_stat9_rx_lost_block_cnt_msb_i  (c_cw-32-1 downto 0) <= lost_block_cnt_out(c_cw-1 downto 32);
+  to_wb.rx_stat10_rx_latency_acc_lsb_i                         <= latency_acc       (31     downto 0);
+  to_wb.rx_stat11_rx_latency_acc_msb_i    (c_aw-32-1 downto 0) <= latency_acc       (c_aw-1 downto 32);
+  to_wb.rx_stat12_rx_latency_acc_cnt_lsb_i                     <= latency_cnt       (31     downto 0);
+  to_wb.rx_stat13_rx_latency_acc_cnt_msb_i(c_cw-32-1 downto 0) <= latency_cnt       (c_cw-1 downto 32);
+
+  rx_data_o  <= rx_data;
+  rx_valid_o <= rx_valid;
+
+  -------------------------------------------------------------------------------------------
+  -- Wishbone access to statistics and configuration
+  -------------------------------------------------------------------------------------------
+  U_WB_ADAPTER : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => true,
+      g_slave_mode         => g_slave_mode,
+      g_slave_granularity  => g_slave_granularity)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      slave_i    => wb_slave_i,
+      slave_o    => wb_slave_o,
+      master_i   => wb_regs_slave_out,
+      master_o   => wb_regs_slave_in);
+
+  U_WB:  wr_streamers_wb
+    port map (
+      rst_n_i      => rst_n_i,
+      clk_sys_i    => clk_sys_i,
+      wb_adr_i     => wb_regs_slave_in.adr(5 downto 0),
+      wb_dat_i     => wb_regs_slave_in.dat,
+      wb_dat_o     => wb_regs_slave_out.dat,
+      wb_cyc_i     => wb_regs_slave_in.cyc,
+      wb_sel_i     => wb_regs_slave_in.sel(3 downto 0),
+      wb_stb_i     => wb_regs_slave_in.stb,
+      wb_we_i      => wb_regs_slave_in.we,
+      wb_ack_o     => wb_regs_slave_out.ack,
+      wb_stall_o   => wb_regs_slave_out.stall,
+      regs_i       => to_wb,
+      regs_o       => from_wb
+    );
+
+  -------------------------------------------------------------------------------------------
+  -- Provide generic debugging through WB - user can read 32 bits from each send or received
+  -- word. It is possible to configure through WB which 32-bits of each word should be 
+  -- "snooped". In particular, user can sent:
+  -- * whether he/she wishes to look at received or sent words
+  -- * the byte number at which the snooping shall start, i.e. say users sets byte=2, it means
+  --   that he will be able to read through wishbone bytes 3-6 of each word, provided the
+  --   word is of sufficient width
+  -------------------------------------------------------------------------------------------
+  start_bit <= from_wb.dbg_ctrl_start_byte_o & "000";
+  p_debug_mux: process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        dbg_word <= (others =>'0');
+      else
+        if(from_wb.dbg_ctrl_mux_o = '1') then --rx
+          if(rx_valid = '1') then
+            dbg_word <= f_dbg_word_starting_at_bit(rx_data,start_bit,g_rx_streamer_params.data_width);
+          end if;
+        else -- tx
+          if(tx_valid_i = '1') then
+            dbg_word <= f_dbg_word_starting_at_bit(tx_data_i,start_bit,g_tx_streamer_params.data_width);
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  snmp_array_o(c_WRS_STATS_ARR_SIZE_OUT)   <= dbg_word;
+  snmp_array_o(c_WRS_STATS_ARR_SIZE_OUT+1) <= x"DEADBEEF";
+
+  to_wb.dbg_data_i      <= dbg_word;
+  to_wb.dummy_dummy_i   <= x"DEADBEEF";
+
+  -------------------------------------------------------------------------------------------
+  -- set configuration: the user can access configuration through two channels:
+  -- 1) records (tx_streamer_cfg & rx_streamer_cfg) with input signals
+  -- 2) wishbone write
+  -- By default, the input signals are used. A user can overwrite this default
+  -- configuration using WB access. To override the default configuration two 
+  -- values needs to be written:
+  -- 1) the value of a proper configuration, e.g.: tx_cfg0_ethertype, rx_cfg0_filter_remote
+  -- 2) bit that enables overriding of the configuration, e.g. cfg_or_tx_ethtype and
+  --    cfg_or_rx_ftr_remote_o respectively
+  -- The latter (overriding bit) is the so that user can first configure all values
+  -- that he wishes to and then enable all his desired configuration at the same instant.
+  -- Otherwise, during the transition (e.g. between writing lsb and msb of MAC), the
+  -- behaviour could be unpredictable.
+  -------------------------------------------------------------------------------------------
+  -- tx config
+  tx_streamer_cfg.ethertype         <= from_wb.tx_cfg0_ethertype_o        when (from_wb.cfg_or_tx_ethtype_o='1') else
+                                       tx_streamer_cfg_i.ethertype;
+  tx_streamer_cfg.mac_local         <= from_wb.tx_cfg2_mac_local_msb_o &
+                                       from_wb.tx_cfg1_mac_local_lsb_o    when (from_wb.cfg_or_tx_mac_loc_o='1') else
+                                       tx_streamer_cfg_i.mac_local;
+  tx_streamer_cfg.mac_target        <= from_wb.tx_cfg4_mac_target_msb_o &
+                                       from_wb.tx_cfg3_mac_target_lsb_o   when (from_wb.cfg_or_tx_mac_tar_o='1') else
+                                       tx_streamer_cfg_i.mac_target;
+  tx_streamer_cfg.qtag_ena          <= from_wb.tx_cfg5_qtag_ena_o         when (from_wb.cfg_or_tx_qtag_o='1') else
+                                       tx_streamer_cfg_i.qtag_ena;
+  tx_streamer_cfg.qtag_vid          <= from_wb.tx_cfg5_qtag_vid_o         when (from_wb.cfg_or_tx_qtag_o='1') else
+                                       tx_streamer_cfg_i.qtag_vid;
+  tx_streamer_cfg.qtag_prio         <= from_wb.tx_cfg5_qtag_prio_o        when (from_wb.cfg_or_tx_qtag_o='1') else
+                                       tx_streamer_cfg_i.qtag_prio;
+
+  -- rx config
+  rx_streamer_cfg.ethertype         <= from_wb.rx_cfg0_ethertype_o        when (from_wb.cfg_or_rx_ethertype_o='1') else
+                                       rx_streamer_cfg_i.ethertype;
+  rx_streamer_cfg.mac_local         <= from_wb.rx_cfg2_mac_local_msb_o &
+                                       from_wb.rx_cfg1_mac_local_lsb_o    when (from_wb.cfg_or_rx_mac_loc_o='1') else
+                                       rx_streamer_cfg_i.mac_local;
+  rx_streamer_cfg.mac_remote        <= from_wb.rx_cfg4_mac_remote_msb_o &
+                                       from_wb.rx_cfg3_mac_remote_lsb_o   when (from_wb.cfg_or_rx_mac_rem_o='1') else
+                                       rx_streamer_cfg_i.mac_remote;
+  rx_streamer_cfg.accept_broadcasts <= from_wb.rx_cfg0_accept_broadcast_o when (from_wb.cfg_or_rx_acc_broadcast_o='1') else
+                                       rx_streamer_cfg_i.accept_broadcasts;
+  rx_streamer_cfg.filter_remote     <= from_wb.rx_cfg0_filter_remote_o    when (from_wb.cfg_or_rx_ftr_remote_o='1') else
+                                       rx_streamer_cfg_i.filter_remote;
+  rx_streamer_cfg.fixed_latency     <= from_wb.rx_cfg5_fixed_latency_o    when (from_wb.cfg_or_rx_fix_lat_o='1') else
+                                       rx_streamer_cfg_i.fixed_latency;
+end rtl;
\ No newline at end of file
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_tbi_phy/disparity_gen_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_tbi_phy/disparity_gen_pkg.vhd
new file mode 100644
index 000000000..3c23afa59
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_tbi_phy/disparity_gen_pkg.vhd
@@ -0,0 +1,90 @@
+-- 8b10b disparity generator, based on 8b10b encoder core (c) Mathias Kreider
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package disparity_gen_pkg is
+
+  type t_8b10b_disparity is (RD_PLUS, RD_MINUS);
+  
+  function f_next_8b10b_disparity8 (cur_disp : t_8b10b_disparity;
+                                    ctrl     : std_logic;
+                                    data     : std_logic_vector)
+    return t_8b10b_disparity;
+
+  function f_next_8b10b_disparity16 (
+    cur_disp : t_8b10b_disparity;
+    ctrl     : std_logic_vector;
+    data     : std_logic_vector)
+    return t_8b10b_disparity;
+
+  function to_std_logic(t : t_8b10b_disparity) return std_logic;
+
+  
+
+end disparity_gen_pkg;
+
+package body disparity_gen_pkg is
+
+  function f_next_8b10b_disparity8(cur_disp : t_8b10b_disparity;
+                                   ctrl     : std_logic;
+                                   data     : std_logic_vector) return t_8b10b_disparity is
+
+    constant c_disPar_6b : std_logic_vector(0 to 31) := ("11101000100000011000000110010111");
+
+    constant c_disPar_4b    : std_logic_vector(0 to 7) := ("10001001");
+    variable dp4bit, dp6bit : std_logic;
+    variable new_disp       : t_8b10b_disparity;
+  begin
+-- use 3bit at 7-5 as index for 4bit code and disparity table \n
+
+    dp4bit := c_disPar_4b(to_integer(unsigned(data(7 downto 5))));
+    dp6bit := c_disPar_6b(to_integer(unsigned(data(4 downto 0))));
+
+    new_disp := cur_disp;
+
+    case cur_disp is
+      when RD_MINUS =>
+        if (ctrl xor dp6bit xor dp4bit) /= '0' then
+          new_disp := RD_PLUS;
+        end if;
+
+      when RD_PLUS =>
+        if (ctrl xor dp6bit xor dP4bit) /= '0' then
+          new_disp := RD_MINUS;
+        end if;
+    end case;
+
+    if ( data(1 downto 0) /= "00" and ctrl = '1') then
+      new_disp := cur_disp;
+    end if;
+    
+    return new_disp;
+  end f_next_8b10b_disparity8;
+
+  function f_next_8b10b_disparity16(cur_disp : t_8b10b_disparity;
+                                    ctrl     : std_logic_vector;
+                                    data     : std_logic_vector) return t_8b10b_disparity is
+
+    variable tmp : t_8b10b_disparity;
+    variable msb : std_logic_vector(7 downto 0);
+  begin
+
+    msb := data(15 downto 8);
+    tmp := f_next_8b10b_disparity8(cur_disp, ctrl(1), msb);
+    tmp := f_next_8b10b_disparity8(tmp, ctrl(0), data(7 downto 0));
+    return tmp;
+  end f_next_8b10b_disparity16;
+
+  function to_std_logic(t : t_8b10b_disparity) return std_logic is
+  begin
+    if(t = RD_MINUS) then
+      return '0';
+    else
+      return '1';
+    end if;
+  end to_std_logic;
+
+end package body;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wr_core.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wr_core.vhd
new file mode 100644
index 000000000..c87f5a405
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wr_core.vhd
@@ -0,0 +1,1157 @@
+-------------------------------------------------------------------------------
+-- Title      : WhiteRabbit PTP Core
+-- Project    : WhiteRabbit
+-------------------------------------------------------------------------------
+-- File       : wr_core.vhd
+-- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2011-02-02
+-- Last update: 2017-05-29
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- WR PTP Core is a HDL module implementing a complete gigabit Ethernet
+-- interface (MAC + PCS + PHY) with integrated PTP slave ordinary clock
+-- compatible with White Rabbit protocol. It performs subnanosecond clock
+-- synchronization via WR protocol and also acts as an Ethernet "gateway",
+-- providing access to TX/RX interfaces of the built-in WR MAC.
+--
+-- Starting from version 2.0 all modules are interconnected with pipelined
+-- wishbone interface (using wb crossbars). Separate pipelined wishbone bus is
+-- used for passing packets between Endpoint, Mini-NIC and External
+-- MAC interface.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 - 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Memory map:
+--  0x00000000: I/D Memory
+--  0x00020000: Peripheral interconnect
+--      +0x000: Minic
+--      +0x100: Endpoint
+--      +0x200: Softpll
+--      +0x300: PPS gen
+--      +0x400: Syscon
+--      +0x500: UART
+--      +0x600: OneWire
+--      +0x700: Auxillary space (Etherbone config, etc)
+--      +0x800: WRPC diagnostics registers
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wrcore_pkg.all;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+use work.wishbone_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.sysc_wbgen2_pkg.all;
+use work.softpll_pkg.all;
+
+entity wr_core is
+  generic(
+    --if set to 1, then blocks in PCS use smaller calibration counter to speed
+    --up simulation
+    g_simulation                : integer                        := 0;
+    g_with_external_clock_input : boolean                        := true;
+    --
+    g_board_name                : string                         := "NA  ";
+    g_flash_secsz_kb            : integer                        := 256;        -- default for SVEC (M25P128)
+    g_flash_sdbfs_baddr         : integer                        := 16#600000#; -- default for SVEC (M25P128)
+    g_phys_uart                 : boolean                        := true;
+    g_virtual_uart              : boolean                        := true;
+    g_aux_clks                  : integer                        := 0;
+    g_rx_buffer_size            : integer                        := 1024;
+    g_tx_runt_padding           : boolean                        := true;
+    g_dpram_initf               : string                         := "default";
+    g_dpram_size                : integer                        := 131072/4;  --in 32-bit words
+    g_interface_mode            : t_wishbone_interface_mode      := PIPELINED;
+    g_address_granularity       : t_wishbone_address_granularity := BYTE;
+    g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
+    g_softpll_enable_debugger   : boolean                        := false;
+    g_vuart_fifo_size           : integer                        := 1024;
+    g_pcs_16bit                 : boolean                        := false;
+    g_records_for_phy           : boolean                        := false;
+    g_diag_id                   : integer                        := 0;
+    g_diag_ver                  : integer                        := 0;
+    g_diag_ro_size              : integer                        := 0;
+    g_diag_rw_size              : integer                        := 0);
+  port(
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+
+    -- system reference clock (any frequency <= f(clk_ref_i))
+    clk_sys_i : in std_logic;
+
+    -- DDMTD offset clock (125.x MHz)
+    clk_dmtd_i : in std_logic;
+
+    -- Timing reference (125 MHz)
+    clk_ref_i : in std_logic;
+
+    -- Aux clocks (i.e. the FMC clock), which can be disciplined by the WR Core
+    clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+
+    clk_ext_mul_i : in std_logic := '0';
+    clk_ext_mul_locked_i  : in  std_logic := '1';
+    clk_ext_stopped_i     : in  std_logic := '0';
+    clk_ext_rst_o         : out std_logic;
+
+    -- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
+    clk_ext_i : in std_logic := '0';
+
+    -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
+    pps_ext_i : in std_logic := '0';
+
+    rst_n_i : in std_logic;
+
+    -----------------------------------------
+    --Timing system
+    -----------------------------------------
+    dac_hpll_load_p1_o : out std_logic;
+    dac_hpll_data_o    : out std_logic_vector(15 downto 0);
+
+    dac_dpll_load_p1_o : out std_logic;
+    dac_dpll_data_o    : out std_logic_vector(15 downto 0);
+
+    -- PHY I/f
+    phy_ref_clk_i : in std_logic;
+
+    phy_tx_data_o      : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    phy_tx_k_o         : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+    phy_tx_disparity_i : in  std_logic;
+    phy_tx_enc_err_i   : in  std_logic;
+
+    phy_rx_data_i     : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    phy_rx_rbclk_i    : in std_logic;
+    phy_rx_k_i        : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+    phy_rx_enc_err_i  : in std_logic;
+    phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
+
+    phy_rst_o            : out std_logic;
+    phy_rdy_i            : in  std_logic := '1';
+    phy_loopen_o         : out std_logic;
+    phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+    phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+    phy_sfp_tx_fault_i   : in std_logic := '0';
+    phy_sfp_los_i        : in std_logic := '0';
+    phy_sfp_tx_disable_o : out std_logic;
+
+    -- PHY I/F record-based
+    phy8_o  : out t_phy_8bits_from_wrc;
+    phy8_i  : in  t_phy_8bits_to_wrc  := c_dummy_phy8_to_wrc;
+    phy16_o : out t_phy_16bits_from_wrc;
+    phy16_i : in  t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
+
+    -----------------------------------------
+    --GPIO
+    -----------------------------------------
+    led_act_o  : out std_logic;
+    led_link_o : out std_logic;
+    scl_o      : out std_logic;
+    scl_i      : in  std_logic := '1';
+    sda_o      : out std_logic;
+    sda_i      : in  std_logic := '1';
+    sfp_scl_o  : out std_logic;
+    sfp_scl_i  : in  std_logic := '1';
+    sfp_sda_o  : out std_logic;
+    sfp_sda_i  : in  std_logic := '1';
+    sfp_det_i  : in  std_logic := '1';
+    btn1_i     : in  std_logic := '1';
+    btn2_i     : in  std_logic := '1';
+    spi_sclk_o : out std_logic;
+    spi_ncs_o  : out std_logic;
+    spi_mosi_o : out std_logic;
+    spi_miso_i : in  std_logic := '0';
+
+    -----------------------------------------
+    --UART
+    -----------------------------------------
+    uart_rxd_i : in  std_logic := '1';
+    uart_txd_o : out std_logic;
+
+    -----------------------------------------
+    -- 1-wire
+    -----------------------------------------
+    owr_pwren_o : out std_logic_vector(1 downto 0);
+    owr_en_o    : out std_logic_vector(1 downto 0);
+    owr_i       : in  std_logic_vector(1 downto 0) := (others => '1');
+
+    -----------------------------------------
+    --External WB interface
+    -----------------------------------------
+    wb_adr_i   : in  std_logic_vector(c_wishbone_address_width-1 downto 0)   := (others => '0');
+    wb_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0)      := (others => '0');
+    wb_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_sel_i   : in  std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
+    wb_we_i    : in  std_logic                                               := '0';
+    wb_cyc_i   : in  std_logic                                               := '0';
+    wb_stb_i   : in  std_logic                                               := '0';
+    wb_ack_o   : out std_logic;
+    wb_err_o   : out std_logic;
+    wb_rty_o   : out std_logic;
+    wb_stall_o : out std_logic;
+
+    -----------------------------------------
+    -- Auxillary WB master
+    -----------------------------------------
+    aux_adr_o   : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+    aux_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    aux_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+    aux_sel_o   : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
+    aux_we_o    : out std_logic;
+    aux_cyc_o   : out std_logic;
+    aux_stb_o   : out std_logic;
+    aux_ack_i   : in  std_logic := '1';
+    aux_stall_i : in  std_logic := '0';
+
+    -----------------------------------------
+    -- External Fabric I/F
+    -----------------------------------------
+    ext_snk_adr_i   : in  std_logic_vector(1 downto 0)  := "00";
+    ext_snk_dat_i   : in  std_logic_vector(15 downto 0) := x"0000";
+    ext_snk_sel_i   : in  std_logic_vector(1 downto 0)  := "00";
+    ext_snk_cyc_i   : in  std_logic                     := '0';
+    ext_snk_we_i    : in  std_logic                     := '0';
+    ext_snk_stb_i   : in  std_logic                     := '0';
+    ext_snk_ack_o   : out std_logic;
+    ext_snk_err_o   : out std_logic;
+    ext_snk_stall_o : out std_logic;
+
+    ext_src_adr_o   : out std_logic_vector(1 downto 0);
+    ext_src_dat_o   : out std_logic_vector(15 downto 0);
+    ext_src_sel_o   : out std_logic_vector(1 downto 0);
+    ext_src_cyc_o   : out std_logic;
+    ext_src_stb_o   : out std_logic;
+    ext_src_we_o    : out std_logic;
+    ext_src_ack_i   : in  std_logic := '1';
+    ext_src_err_i   : in  std_logic := '0';
+    ext_src_stall_i : in  std_logic := '0';
+
+    ------------------------------------------
+    -- External TX Timestamp I/F
+    ------------------------------------------
+    txtsu_port_id_o      : out std_logic_vector(4 downto 0);
+    txtsu_frame_id_o     : out std_logic_vector(15 downto 0);
+    txtsu_ts_value_o     : out std_logic_vector(31 downto 0);
+    txtsu_ts_incorrect_o : out std_logic;
+    txtsu_stb_o          : out std_logic;
+    txtsu_ack_i          : in  std_logic := '1';
+
+    -----------------------------------------
+    -- Timestamp helper signals, used for Absolute Calibration
+    -----------------------------------------
+    abscal_txts_o        : out std_logic;
+    abscal_rxts_o        : out std_logic;
+
+    -----------------------------------------
+    -- Pause Frame Control
+    -----------------------------------------
+    fc_tx_pause_req_i   : in  std_logic                     := '0';
+    fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+    fc_tx_pause_ready_o : out std_logic;
+
+    -----------------------------------------
+    -- Timecode/Servo Control
+    -----------------------------------------
+
+    tm_link_up_o         : out std_logic;
+    -- DAC Control
+    tm_dac_value_o       : out std_logic_vector(23 downto 0);
+    tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+    -- Aux clock lock enable
+    tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+    -- Aux clock locked flag
+    tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+    -- Timecode output
+    tm_time_valid_o      : out std_logic;
+    tm_tai_o             : out std_logic_vector(39 downto 0);
+    tm_cycles_o          : out std_logic_vector(27 downto 0);
+    -- 1PPS output
+    pps_csync_o          : out std_logic;
+    pps_p_o              : out std_logic;
+    pps_led_o            : out std_logic;
+
+    rst_aux_n_o : out std_logic;
+
+    link_ok_o : out std_logic;
+
+    -------------------------------------
+    -- DIAG to/from external modules
+    -------------------------------------
+    aux_diag_i : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others=>(others=>'0'));
+    aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0)
+    );
+end wr_core;
+
+architecture struct of wr_core is
+
+  function f_choose_lm32_firmware_file return string is
+  begin
+    if(g_dpram_initf = "default") then
+      if(g_simulation /= 0) then
+        report "[WR Core] Using simulation LM32 firmware." severity note;
+        return "wrc-simulation.ram";
+      else
+        report "[WR Core] Using release LM32 firmware." severity note;
+        return "wrc-release.ram";
+      end if;
+    else
+      report "[WR Core] Using user-provided LM32 firmware." severity note;
+      return g_dpram_initf;
+    end if;
+  end function;
+
+  function f_check_if_lm32_firmware_necessary return boolean is
+  begin
+    if(g_dpram_initf /= "") then
+      return true;
+    else
+      return false;
+    end if;
+  end function;
+
+  -----------------------------------------------------------------------------
+  --Local resets for peripheral
+  -----------------------------------------------------------------------------
+  signal rst_wrc_n : std_logic;
+  signal rst_net_n : std_logic;
+
+  -----------------------------------------------------------------------------
+  --Local resets (resynced)
+  -----------------------------------------------------------------------------
+  signal rst_net_resync_ref_n   : std_logic;
+  signal rst_net_resync_ext_n   : std_logic;
+  signal rst_net_resync_dmtd_n  : std_logic;
+  signal rst_net_resync_rxclk_n : std_logic;
+  signal rst_net_resync_txclk_n : std_logic;
+
+  -----------------------------------------------------------------------------
+  --PPS generator
+  -----------------------------------------------------------------------------
+  signal s_pps_csync : std_logic;
+  signal pps_valid   : std_logic;
+  signal ppsg_link_ok: std_logic;
+
+  signal ppsg_wb_in  : t_wishbone_slave_in;
+  signal ppsg_wb_out : t_wishbone_slave_out;
+
+  -----------------------------------------------------------------------------
+  --Timing system
+  -----------------------------------------------------------------------------
+  signal phy_rx_clk  : std_logic;
+  signal phy_tx_clk  : std_logic;
+  signal spll_wb_in  : t_wishbone_slave_in;
+  signal spll_wb_out : t_wishbone_slave_out;
+
+  -----------------------------------------------------------------------------
+  --Endpoint
+  -----------------------------------------------------------------------------
+  signal ep_txtsu_port_id           : std_logic_vector(4 downto 0);
+  signal ep_txtsu_frame_id          : std_logic_vector(15 downto 0);
+  signal ep_txtsu_ts_value          : std_logic_vector(31 downto 0);
+  signal ep_txtsu_ts_incorrect      : std_logic;
+  signal ep_txtsu_stb, ep_txtsu_ack : std_logic;
+  signal ep_led_link                : std_logic;
+
+  signal phy_rst : std_logic;
+
+  constant c_mnic_memsize_log2 : integer := f_log2_size(g_dpram_size);
+
+  -----------------------------------------------------------------------------
+  --Mini-NIC
+  -----------------------------------------------------------------------------
+  signal mnic_mem_data_o : std_logic_vector(31 downto 0);
+  signal mnic_mem_addr_o : std_logic_vector(c_mnic_memsize_log2-1 downto 0);
+  signal mnic_mem_wr_o   : std_logic;
+  signal mnic_txtsu_ack  : std_logic;
+  signal mnic_txtsu_stb  : std_logic;
+
+  -----------------------------------------------------------------------------
+  --Dual-port RAM
+  -----------------------------------------------------------------------------
+  signal dpram_wbb_i : t_wishbone_slave_in;
+
+  -----------------------------------------------------------------------------
+  --WB Peripherials
+  -----------------------------------------------------------------------------
+  signal periph_slave_i : t_wishbone_slave_in_array(0 to 3);
+  signal periph_slave_o : t_wishbone_slave_out_array(0 to 3);
+  signal sysc_in_regs   : t_sysc_in_registers;
+  signal sysc_out_regs  : t_sysc_out_registers;
+
+  -----------------------------------------------------------------------------
+  --WB Secondary Crossbar
+  -----------------------------------------------------------------------------
+  constant c_secbar_layout : t_sdb_record_array(8 downto 0) :=
+    (0 => f_sdb_embed_device(c_xwr_mini_nic_sdb, x"00000000"),
+     1 => f_sdb_embed_device(c_xwr_endpoint_sdb, x"00000100"),
+     2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00000200"),
+     3 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00000300"),
+     4 => f_sdb_embed_device(c_wrc_periph0_sdb, x"00000400"),  -- Syscon
+     5 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00000500"),  -- UART
+     6 => f_sdb_embed_device(c_wrc_periph2_sdb, x"00000600"),  -- 1-Wire
+     7 => f_sdb_embed_device(g_aux_sdb,         x"00000700"),  -- aux WB bus
+     8 => f_sdb_embed_device(c_wrc_periph4_sdb, x"00000800")   -- WRPC diag registers
+     );
+
+  constant c_secbar_sdb_address : t_wishbone_address := x"00000C00";
+  constant c_secbar_bridge_sdb  : t_sdb_bridge       :=
+    f_xwb_bridge_layout_sdb(true, c_secbar_layout, c_secbar_sdb_address);
+
+  signal secbar_master_i : t_wishbone_master_in_array(8 downto 0);
+  signal secbar_master_o : t_wishbone_master_out_array(8 downto 0);
+
+  -----------------------------------------------------------------------------
+  --WB intercon
+  -----------------------------------------------------------------------------
+  constant c_layout : t_sdb_record_array(1 downto 0) :=
+    (0 => f_sdb_embed_device(f_xwb_dpram(g_dpram_size), x"00000000"),
+     1 => f_sdb_embed_bridge(c_secbar_bridge_sdb, x"00020000"));
+  constant c_sdb_address : t_wishbone_address := x"00030000";
+
+  signal cbar_slave_i  : t_wishbone_slave_in_array (2 downto 0);
+  signal cbar_slave_o  : t_wishbone_slave_out_array(2 downto 0);
+  signal cbar_master_i : t_wishbone_master_in_array(1 downto 0);
+  signal cbar_master_o : t_wishbone_master_out_array(1 downto 0);
+
+  -----------------------------------------------------------------------------
+  --External WB interface
+  -----------------------------------------------------------------------------
+  signal ext_wb_in  : t_wishbone_slave_in;
+  signal ext_wb_out : t_wishbone_slave_out;
+
+  -----------------------------------------------------------------------------
+  -- External Tx TSU interface
+  -----------------------------------------------------------------------------
+
+  --===========================--
+  --         For SPEC          --
+  --===========================--
+
+  signal hpll_auxout  : std_logic_vector(2 downto 0);
+  signal dmpll_auxout : std_logic_vector(2 downto 0);
+
+  signal clk_ref_slv : std_logic_vector(0 downto 0);
+  signal clk_rx_slv  : std_logic_vector(0 downto 0);
+
+  signal s_dummy_addr : std_logic_vector(31 downto 0);
+
+  signal softpll_irq : std_logic;
+
+  signal lm32_irq_slv : std_logic_vector(31 downto 0);
+
+
+  signal ep_wb_in  : t_wishbone_slave_in;
+  signal ep_wb_out : t_wishbone_slave_out;
+
+  signal minic_wb_in  : t_wishbone_slave_in;
+  signal minic_wb_out : t_wishbone_slave_out;
+
+  signal ep_src_out : t_wrf_source_out;
+  signal ep_src_in  : t_wrf_source_in;
+  signal ep_snk_out : t_wrf_sink_out;
+  signal ep_snk_in  : t_wrf_sink_in;
+
+
+  signal mux_src_out : t_wrf_source_out_array(1 downto 0);
+  signal mux_src_in  : t_wrf_source_in_array(1 downto 0);
+  signal mux_snk_out : t_wrf_sink_out_array(1 downto 0);
+  signal mux_snk_in  : t_wrf_sink_in_array(1 downto 0);
+  signal mux_class   : t_wrf_mux_class(1 downto 0);
+
+  signal spll_out_locked : std_logic_vector(g_aux_clks downto 0);
+
+  signal dac_dpll_data    : std_logic_vector(15 downto 0);
+  signal dac_dpll_sel     : std_logic_vector(3 downto 0);
+  signal dac_dpll_load_p1 : std_logic;
+
+  signal clk_fb     : std_logic_vector(g_aux_clks downto 0);
+  signal out_enable : std_logic_vector(g_aux_clks downto 0);
+
+  --component chipscope_ila
+  --  port (
+  --    CONTROL : inout std_logic_vector(35 downto 0);
+  --    CLK     : in    std_logic;
+  --    TRIG0   : in    std_logic_vector(31 downto 0);
+  --    TRIG1   : in    std_logic_vector(31 downto 0);
+  --    TRIG2   : in    std_logic_vector(31 downto 0);
+  --    TRIG3   : in    std_logic_vector(31 downto 0));
+  --end component;
+
+  --component chipscope_icon
+  --  port (
+  --    CONTROL0 : inout std_logic_vector (35 downto 0));
+  --end component;
+
+  --signal CONTROL : std_logic_vector(35 downto 0);
+  --signal CLK     : std_logic;
+  --signal TRIG0   : std_logic_vector(31 downto 0);
+  --signal TRIG1   : std_logic_vector(31 downto 0);
+  --signal TRIG2   : std_logic_vector(31 downto 0);
+  --signal TRIG3   : std_logic_vector(31 downto 0);
+begin
+
+  -----------------------------------------------------------------------------
+  -- PHY TX/RX clock selection based on generics
+  -----------------------------------------------------------------------------
+
+  GEN_16BIT_PHY_IF: if g_pcs_16bit and g_records_for_phy generate
+    phy_rx_clk <= phy16_i.rx_clk;
+    phy_tx_clk <= phy16_i.ref_clk;
+  end generate;
+
+  GEN_8BIT_PHY_IF: if not g_pcs_16bit and g_records_for_phy generate
+    phy_rx_clk <= phy8_i.rx_clk;
+    phy_tx_clk <= phy8_i.ref_clk;
+  end generate;
+
+  GEN_STD_PHY_IF: if not g_records_for_phy generate
+    phy_rx_clk <= phy_rx_rbclk_i;
+    phy_tx_clk <= phy_ref_clk_i;
+  end generate;
+
+  -----------------------------------------------------------------------------
+  -- Reset resync and distribution
+  -----------------------------------------------------------------------------
+
+  rst_aux_n_o <= rst_net_n;
+
+  U_Sync_reset_refclk : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_ref_i,
+      rst_n_i  => '1',
+      data_i   => rst_net_n,
+      synced_o => rst_net_resync_ref_n);
+
+  U_sync_reset_dmtd : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_dmtd_i,
+      rst_n_i  => '1',
+      data_i   => rst_net_n,
+      synced_o => rst_net_resync_dmtd_n);
+
+  U_sync_reset_ext : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_ext_i,
+      rst_n_i  => '1',
+      data_i   => rst_net_n,
+      synced_o => rst_net_resync_ext_n);
+
+  U_sync_reset_rxclk : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_rx_clk,
+      rst_n_i  => '1',
+      data_i   => rst_net_n,
+      synced_o => rst_net_resync_rxclk_n);
+
+  U_sync_reset_txclk : gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => phy_tx_clk,
+      rst_n_i  => '1',
+      data_i   => rst_net_n,
+      synced_o => rst_net_resync_txclk_n);
+
+  -----------------------------------------------------------------------------
+  -- PPS generator
+  -----------------------------------------------------------------------------
+  PPS_GEN : xwr_pps_gen
+    generic map(
+      g_interface_mode       => PIPELINED,
+      g_address_granularity  => BYTE,
+      g_ref_clock_rate       => f_refclk_rate(g_pcs_16bit),
+      g_ext_clock_rate       => 10000000,
+      g_with_ext_clock_input => g_with_external_clock_input)
+    port map(
+      clk_ref_i => clk_ref_i,
+      clk_sys_i => clk_sys_i,
+
+      rst_sys_n_i => rst_net_n,
+      rst_ref_n_i => rst_net_resync_ref_n,
+
+      slave_i => ppsg_wb_in,
+      slave_o => ppsg_wb_out,
+
+      -- used for fast masking of PPS output when link goes down
+      link_ok_i => ppsg_link_ok,
+
+      -- Single-pulse PPS output for synchronizing endpoint to
+      pps_in_i    => pps_ext_i,
+      pps_csync_o => s_pps_csync,
+      pps_out_o   => pps_p_o,
+      pps_led_o   => pps_led_o,
+      pps_valid_o => pps_valid,
+
+      tm_utc_o        => tm_tai_o,
+      tm_cycles_o     => tm_cycles_o,
+      tm_time_valid_o => tm_time_valid_o
+      );
+  ppsg_link_ok <= not phy_rst;
+  pps_csync_o  <= s_pps_csync;
+
+  -----------------------------------------------------------------------------
+  -- Software PLL
+  -----------------------------------------------------------------------------
+  U_SOFTPLL : xwr_softpll_ng
+    generic map(
+      g_with_ext_clock_input => g_with_external_clock_input,
+      g_reverse_dmtds        => false,
+      g_divide_input_by_2    => not g_pcs_16bit,
+      g_with_debug_fifo      => g_softpll_enable_debugger,
+      g_tag_bits             => 22,
+      g_interface_mode       => PIPELINED,
+      g_address_granularity  => BYTE,
+      g_num_ref_inputs       => 1,
+      g_num_outputs          => 1 + g_aux_clks,
+      g_ref_clock_rate       => f_refclk_rate(g_pcs_16bit),
+      g_ext_clock_rate       => 10000000)
+    port map(
+      clk_sys_i    => clk_sys_i,
+      rst_sys_n_i  => rst_net_n,
+      rst_ref_n_i  => rst_net_resync_ref_n,
+      rst_ext_n_i  => rst_net_resync_ext_n,
+      rst_dmtd_n_i => rst_net_resync_dmtd_n,
+
+      -- Reference inputs (i.e. the RX clocks recovered by the PHYs)
+      clk_ref_i(0) => phy_rx_clk,
+      -- Feedback clocks (i.e. the outputs of the main or aux oscillator)
+      clk_fb_i     => clk_fb,
+      -- DMTD Offset clock
+      clk_dmtd_i   => clk_dmtd_i,
+
+      clk_ext_i     => clk_ext_i,
+      clk_ext_mul_i => clk_ext_mul_i,
+      clk_ext_mul_locked_i => clk_ext_mul_locked_i,
+      clk_ext_stopped_i    => clk_ext_stopped_i,
+      clk_ext_rst_o        => clk_ext_rst_o,
+
+      pps_csync_p1_i => s_pps_csync,
+      pps_ext_a_i => pps_ext_i,
+
+      -- DMTD oscillator drive
+      dac_dmtd_data_o => dac_hpll_data_o,
+      dac_dmtd_load_o => dac_hpll_load_p1_o,
+
+      -- Output channel DAC value
+      dac_out_data_o => dac_dpll_data,  --: out std_logic_vector(15 downto 0);
+      -- Output channel select (0 = channel 0, etc. )
+      dac_out_sel_o  => dac_dpll_sel,   --for now use only one output
+      dac_out_load_o => dac_dpll_load_p1,
+
+      out_enable_i => out_enable,
+
+      out_locked_o => spll_out_locked,
+
+      slave_i => spll_wb_in,
+      slave_o => spll_wb_out,
+
+      debug_o => open);
+
+  clk_fb(0)                       <= clk_ref_i;
+  clk_fb(g_aux_clks downto 1)     <= clk_aux_i;
+  out_enable(0)                   <= '1';
+  out_enable(g_aux_clks downto 1) <= tm_clk_aux_lock_en_i;
+
+  dac_dpll_data_o    <= dac_dpll_data;
+  dac_dpll_load_p1_o <= '1' when (dac_dpll_load_p1 = '1' and dac_dpll_sel = x"0") else '0';
+
+  tm_dac_value_o <= x"00" & dac_dpll_data;
+
+  p_decode_dac_writes : process(dac_dpll_load_p1, dac_dpll_sel)
+  begin
+    for i in 0 to g_aux_clks-1 loop
+      if dac_dpll_sel = std_logic_vector(to_unsigned(i+1, 4)) then
+        tm_dac_wr_o(i) <= dac_dpll_load_p1;
+      else
+        tm_dac_wr_o(i) <= '0';
+      end if;
+    end loop;  -- i
+  end process;
+
+  locked_spll : if g_aux_clks > 0 generate
+    tm_clk_aux_locked_o <= spll_out_locked(g_aux_clks downto 1);
+  end generate;
+
+  softpll_irq <= spll_wb_out.int;
+
+  -----------------------------------------------------------------------------
+  -- Endpoint
+  -----------------------------------------------------------------------------
+  U_Endpoint : xwr_endpoint
+    generic map (
+      g_interface_mode      => PIPELINED,
+      g_address_granularity => BYTE,
+      g_simulation          => f_int2bool(g_simulation),
+      g_tx_runt_padding     => g_tx_runt_padding,
+      g_pcs_16bit           => g_pcs_16bit,
+      g_records_for_phy     => g_records_for_phy,
+      g_rx_buffer_size      => g_rx_buffer_size,
+      g_with_rx_buffer      => true,
+      g_with_flow_control   => false,
+      g_with_timestamper    => true,
+      g_with_dpi_classifier => true,
+      g_with_vlans          => false,
+      g_with_rtu            => false,
+      g_with_leds           => true,
+      g_with_packet_injection => false,
+      g_use_new_rxcrc       => true,
+      g_use_new_txcrc       => false)
+    port map (
+      clk_ref_i      => clk_ref_i,
+      clk_sys_i      => clk_sys_i,
+      clk_dmtd_i     => clk_dmtd_i,
+      rst_sys_n_i    => rst_net_n,
+      rst_ref_n_i    => rst_net_resync_ref_n,
+      rst_dmtd_n_i   => rst_net_resync_dmtd_n,
+      rst_txclk_n_i  => rst_net_resync_txclk_n,
+      rst_rxclk_n_i  => rst_net_resync_rxclk_n,
+      pps_csync_p1_i => s_pps_csync,
+      pps_valid_i    => pps_valid,
+
+      phy_rst_o            => phy_rst,
+      phy_rdy_i            => phy_rdy_i,
+      phy_loopen_o         => phy_loopen_o,
+      phy_loopen_vec_o     => phy_loopen_vec_o,
+      phy_tx_prbs_sel_o    => phy_tx_prbs_sel_o,
+      phy_sfp_tx_fault_i   => phy_sfp_tx_fault_i,
+      phy_sfp_los_i        => phy_sfp_los_i,
+      phy_sfp_tx_disable_o => phy_sfp_tx_disable_o,
+      phy_ref_clk_i        => phy_ref_clk_i,
+      phy_tx_data_o        => phy_tx_data_o,
+      phy_tx_k_o           => phy_tx_k_o,
+      phy_tx_disparity_i   => phy_tx_disparity_i,
+      phy_tx_enc_err_i     => phy_tx_enc_err_i,
+      phy_rx_data_i        => phy_rx_data_i,
+      phy_rx_clk_i         => phy_rx_rbclk_i,
+      phy_rx_k_i           => phy_rx_k_i,
+      phy_rx_enc_err_i     => phy_rx_enc_err_i,
+      phy_rx_bitslide_i    => phy_rx_bitslide_i,
+
+      phy8_o  => phy8_o,
+      phy8_i  => phy8_i,
+      phy16_o => phy16_o,
+      phy16_i => phy16_i,
+
+      src_o => ep_src_out,
+      src_i => ep_src_in,
+      snk_o => ep_snk_out,
+      snk_i => ep_snk_in,
+
+      txtsu_port_id_o      => ep_txtsu_port_id,
+      txtsu_frame_id_o     => ep_txtsu_frame_id,
+      txtsu_ts_value_o     => ep_txtsu_ts_value,
+      txtsu_ts_incorrect_o => ep_txtsu_ts_incorrect,
+      txtsu_stb_o          => ep_txtsu_stb,
+      txtsu_ack_i          => ep_txtsu_ack,
+      wb_i                 => ep_wb_in,
+      wb_o                 => ep_wb_out,
+      rmon_events_o        => open,
+      txts_o               => abscal_txts_o,
+      rxts_o               => abscal_rxts_o,
+      fc_tx_pause_req_i    => fc_tx_pause_req_i,
+      fc_tx_pause_delay_i  => fc_tx_pause_delay_i,
+      fc_tx_pause_ready_o  => fc_tx_pause_ready_o,
+      led_link_o           => ep_led_link,
+      led_act_o            => led_act_o);
+
+  led_link_o   <= ep_led_link;
+  link_ok_o    <= ep_led_link;
+
+  tm_link_up_o <= ep_led_link;
+
+  phy_rst_o <= phy_rst;
+
+  -----------------------------------------------------------------------------
+  -- Mini-NIC
+  -----------------------------------------------------------------------------
+  MINI_NIC : xwr_mini_nic
+    generic map (
+      g_interface_mode       => PIPELINED,
+      g_address_granularity  => BYTE,
+      g_tx_fifo_size         => 1024,
+      g_rx_fifo_size         => 2048,
+      g_buffer_little_endian => false)
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_net_n,
+
+      src_o => mux_snk_in(0),
+      src_i => mux_snk_out(0),
+      snk_o => mux_src_in(0),
+      snk_i => mux_src_out(0),
+
+      txtsu_port_id_i     => ep_txtsu_port_id,
+      txtsu_frame_id_i    => ep_txtsu_frame_id,
+      txtsu_tsval_i       => ep_txtsu_ts_value,
+      txtsu_tsincorrect_i => ep_txtsu_ts_incorrect,
+      txtsu_stb_i         => mnic_txtsu_stb,
+      txtsu_ack_o         => mnic_txtsu_ack,
+
+      wb_i => minic_wb_in,
+      wb_o => minic_wb_out
+      );
+
+  lm32_irq_slv(31 downto 1) <= (others => '0');
+  lm32_irq_slv(0)           <= softpll_irq;  -- according to the doc, it's active low.
+
+  -----------------------------------------------------------------------------
+  -- LM32
+  -----------------------------------------------------------------------------
+  LM32_CORE : xwb_lm32
+    generic map(g_profile => "medium_icache")
+    port map(
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_wrc_n,
+      irq_i     => lm32_irq_slv,
+
+      dwb_o => cbar_slave_i(0),
+      dwb_i => cbar_slave_o(0),
+      iwb_o => cbar_slave_i(1),
+      iwb_i => cbar_slave_o(1)
+      );
+
+  -----------------------------------------------------------------------------
+  -- Dual-port RAM
+  -----------------------------------------------------------------------------
+  DPRAM : xwb_dpram
+    generic map(
+      g_size                  => g_dpram_size,
+      g_init_file             => f_choose_lm32_firmware_file,
+      g_must_have_init_file   => f_check_if_lm32_firmware_necessary,
+      g_slave1_interface_mode => PIPELINED,
+      g_slave2_interface_mode => PIPELINED,
+      g_slave1_granularity    => BYTE,
+      g_slave2_granularity    => WORD)
+    port map(
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+
+      slave1_i => cbar_master_o(0),
+      slave1_o => cbar_master_i(0),
+      slave2_i => dpram_wbb_i,
+      slave2_o => open
+      );
+
+  dpram_wbb_i.cyc <= '0';
+  dpram_wbb_i.stb <= '0';
+  dpram_wbb_i.adr <= (c_mnic_memsize_log2-1 downto 0 => '0', others=>'0'); --mnic_mem_addr_o;
+  dpram_wbb_i.sel <= "1111";
+  dpram_wbb_i.we  <= '0'; --mnic_mem_wr_o;
+  dpram_wbb_i.dat <= (others=>'0'); --mnic_mem_data_o;
+
+  -----------------------------------------------------------------------------
+  -- WB Peripherials
+  -----------------------------------------------------------------------------
+  PERIPH : wrc_periph
+    generic map(
+      g_board_name      => g_board_name,
+      g_flash_secsz_kb  => g_flash_secsz_kb,
+      g_flash_sdbfs_baddr => g_flash_sdbfs_baddr,
+      g_phys_uart       => g_phys_uart,
+      g_virtual_uart    => g_virtual_uart,
+      g_mem_words       => g_dpram_size,
+      g_vuart_fifo_size => g_vuart_fifo_size,
+      g_diag_id         => g_diag_id,
+      g_diag_ver        => g_diag_ver,
+      g_diag_ro_size    => g_diag_ro_size,
+      g_diag_rw_size    => g_diag_rw_size)
+    port map(
+      clk_sys_i   => clk_sys_i,
+      rst_n_i     => rst_n_i,
+      rst_net_n_o => rst_net_n,
+      rst_wrc_n_o => rst_wrc_n,
+
+      led_red_o   => open,              --led_red_o,
+      led_green_o => open,              --led_green_o,
+      scl_o       => scl_o,
+      scl_i       => scl_i,
+      sda_o       => sda_o,
+      sda_i       => sda_i,
+      sfp_scl_o   => sfp_scl_o,
+      sfp_scl_i   => sfp_scl_i,
+      sfp_sda_o   => sfp_sda_o,
+      sfp_sda_i   => sfp_sda_i,
+      sfp_det_i   => sfp_det_i,
+      memsize_i   => "0000",
+      btn1_i      => btn1_i,
+      btn2_i      => btn2_i,
+      spi_sclk_o  => spi_sclk_o,
+      spi_ncs_o   => spi_ncs_o,
+      spi_mosi_o  => spi_mosi_o,
+      spi_miso_i  => spi_miso_i,
+
+      slave_i => periph_slave_i,
+      slave_o => periph_slave_o,
+
+      uart_rxd_i => uart_rxd_i,
+      uart_txd_o => uart_txd_o,
+
+      owr_pwren_o => owr_pwren_o,
+      owr_en_o    => owr_en_o,
+      owr_i       => owr_i,
+
+      diag_array_in  => aux_diag_i,
+      diag_array_out => aux_diag_o
+      );
+
+  U_Adapter : wb_slave_adapter
+    generic map(
+      g_master_use_struct  => true,
+      g_master_mode        => PIPELINED,
+      g_master_granularity => BYTE,
+      g_slave_use_struct   => false,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      master_i   => ext_wb_out,
+      master_o   => ext_wb_in,
+      sl_adr_i   => wb_adr_i,
+      sl_dat_i   => wb_dat_i,
+      sl_sel_i   => wb_sel_i,
+      sl_cyc_i   => wb_cyc_i,
+      sl_stb_i   => wb_stb_i,
+      sl_we_i    => wb_we_i,
+      sl_dat_o   => wb_dat_o,
+      sl_ack_o   => wb_ack_o,
+      sl_err_o   => wb_err_o,
+      sl_rty_o   => wb_rty_o,
+      sl_stall_o => wb_stall_o);
+
+  -----------------------------------------------------------------------------
+  -- WB intercon
+  -----------------------------------------------------------------------------
+  WB_CON : xwb_sdb_crossbar
+    generic map(
+      g_num_masters => 3,
+      g_num_slaves  => 2,
+      g_registered  => true,
+      g_wraparound  => true,
+      g_layout      => c_layout,
+      g_sdb_addr    => c_sdb_address
+      )
+    port map(
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      -- Master connections (INTERCON is a slave)
+      slave_i   => cbar_slave_i,
+      slave_o   => cbar_slave_o,
+      -- Slave connections (INTERCON is a master)
+      master_i  => cbar_master_i,
+      master_o  => cbar_master_o
+      );
+
+  cbar_slave_i(2) <= ext_wb_in;
+  ext_wb_out      <= cbar_slave_o(2);
+
+  --chipscope_ila_1 : chipscope_ila
+  --  port map (
+  --    CONTROL => CONTROL,
+  --    CLK     => clk_sys_i,
+  --    TRIG0   => TRIG0,
+  --    TRIG1   => TRIG1,
+  --    TRIG2   => TRIG2,
+  --    TRIG3   => TRIG3);
+
+  --chipscope_icon_1 : chipscope_icon
+  --  port map (
+  --    CONTROL0 => CONTROL);
+
+  --TRIG0(15 downto 0)  <= ep_snk_in.dat;
+  --trig0(17 downto 16) <= ep_snk_in.adr;
+  --trig0(19 downto 18) <= ep_snk_in.sel;
+  --trig0(20) <= ep_snk_in.cyc;
+  --trig0(21) <= ep_snk_in.stb;
+  --trig0(22) <= ep_snk_in.we;
+  --trig0(23) <= ep_snk_out.ack;
+  --trig0(24) <= ep_snk_out.stall;
+  --trig0(26) <= ep_snk_out.err;
+
+  --TRIG1(15 downto 0)  <= mux_snk_in(0).dat;
+  --trig1(17 downto 16) <= mux_snk_in(0).adr;
+  --trig1(19 downto 18) <= mux_snk_in(0).sel;
+  --trig1(20) <= mux_snk_in(0).cyc;
+  --trig1(21) <= mux_snk_in(0).stb;
+  --trig1(22) <= mux_snk_in(0).we;
+  --trig1(23) <= mux_snk_out(0).ack;
+  --trig1(24) <= mux_snk_out(0).stall;
+  --trig1(26) <= mux_snk_out(0).err;
+
+  --TRIG2(15 downto 0)  <= mux_snk_in(1).dat;
+  --trig2(17 downto 16) <= mux_snk_in(1).adr;
+  --trig2(19 downto 18) <= mux_snk_in(1).sel;
+  --trig2(20) <= mux_snk_in(1).cyc;
+  --trig2(21) <= mux_snk_in(1).stb;
+  --trig2(22) <= mux_snk_in(1).we;
+  --trig2(23) <= mux_snk_out(1).ack;
+  --trig2(24) <= mux_snk_out(1).stall;
+  --trig2(26) <= mux_snk_out(1).err;
+  -----------------------------------------------------------------------------
+  -- WB Secondary Crossbar
+  -----------------------------------------------------------------------------
+  WB_SECONDARY_CON : xwb_sdb_crossbar
+    generic map(
+      g_num_masters => 1,
+      g_num_slaves  => 9,
+      g_registered  => true,
+      g_wraparound  => true,
+      g_layout      => c_secbar_layout,
+      g_sdb_addr    => c_secbar_sdb_address
+      )
+    port map(
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      -- Master connections (INTERCON is a slave)
+      slave_i(0) => cbar_master_o(1),
+      slave_o(0) => cbar_master_i(1),
+      -- Slave connections (INTERCON is a master)
+      master_i   => secbar_master_i,
+      master_o   => secbar_master_o
+      );
+
+  secbar_master_i(0) <= minic_wb_out;
+  minic_wb_in        <= secbar_master_o(0);
+  secbar_master_i(1) <= ep_wb_out;
+  ep_wb_in           <= secbar_master_o(1);
+  secbar_master_i(2) <= spll_wb_out;
+  spll_wb_in         <= secbar_master_o(2);
+  secbar_master_i(3) <= ppsg_wb_out;
+  ppsg_wb_in         <= secbar_master_o(3);
+  --peripherials
+  secbar_master_i(4) <= periph_slave_o(0);
+  secbar_master_i(5) <= periph_slave_o(1);
+  secbar_master_i(6) <= periph_slave_o(2);
+  secbar_master_i(8) <= periph_slave_o(3);
+  periph_slave_i(0)  <= secbar_master_o(4);
+  periph_slave_i(1)  <= secbar_master_o(5);
+  periph_slave_i(2)  <= secbar_master_o(6);
+  periph_slave_i(3)  <= secbar_master_o(8);
+
+
+  aux_adr_o <= secbar_master_o(7).adr;
+  aux_dat_o <= secbar_master_o(7).dat;
+  aux_sel_o <= secbar_master_o(7).sel;
+  aux_cyc_o <= secbar_master_o(7).cyc;
+  aux_stb_o <= secbar_master_o(7).stb;
+  aux_we_o  <= secbar_master_o(7).we;
+
+  secbar_master_i(7).dat   <= aux_dat_i;
+  secbar_master_i(7).ack   <= aux_ack_i;
+  secbar_master_i(7).stall <= aux_stall_i;
+  secbar_master_i(7).err   <= '0';
+  secbar_master_i(7).rty   <= '0';
+  secbar_master_i(7).int   <= '0';
+
+  --secbar_master_i(6).err <= '0';
+  --secbar_master_i(5).err <= '0';
+  --secbar_master_i(4).err <= '0';
+  --secbar_master_i(3).err <= '0';
+  --secbar_master_i(2).err <= '0';
+  --secbar_master_i(1).err <= '0';
+  --secbar_master_i(0).err <= '0';
+
+  --secbar_master_i(6).rty <= '0';
+  --secbar_master_i(5).rty <= '0';
+  --secbar_master_i(4).rty <= '0';
+  --secbar_master_i(3).rty <= '0';
+  --secbar_master_i(2).rty <= '0';
+  --secbar_master_i(1).rty <= '0';
+  --secbar_master_i(0).rty <= '0';
+
+
+
+  -----------------------------------------------------------------------------
+  -- WBP MUX
+  -----------------------------------------------------------------------------
+  U_WBP_Mux : xwrf_mux
+    generic map(
+      g_muxed_ports => 2)
+    port map (
+      clk_sys_i   => clk_sys_i,
+      rst_n_i     => rst_net_n,
+      ep_src_o    => ep_snk_in,
+      ep_src_i    => ep_snk_out,
+      ep_snk_o    => ep_src_in,
+      ep_snk_i    => ep_src_out,
+      mux_src_o   => mux_src_out,
+      mux_src_i   => mux_src_in,
+      mux_snk_o   => mux_snk_out,
+      mux_snk_i   => mux_snk_in,
+      mux_class_i => mux_class);
+
+  mux_class(0)  <= x"0f";
+  mux_class(1)  <= x"f0";
+  ext_src_adr_o <= mux_src_out(1).adr;
+  ext_src_dat_o <= mux_src_out(1).dat;
+  ext_src_stb_o <= mux_src_out(1).stb;
+  ext_src_cyc_o <= mux_src_out(1).cyc;
+  ext_src_sel_o <= mux_src_out(1).sel;
+  ext_src_we_o  <= '1';
+
+  mux_src_in(1).ack   <= ext_src_ack_i;
+  mux_src_in(1).stall <= ext_src_stall_i;
+  mux_src_in(1).err   <= ext_src_err_i;
+  mux_src_in(1).rty   <= '0';
+
+  mux_snk_in(1).adr <= ext_snk_adr_i;
+  mux_snk_in(1).dat <= ext_snk_dat_i;
+  mux_snk_in(1).stb <= ext_snk_stb_i;
+  mux_snk_in(1).cyc <= ext_snk_cyc_i;
+  mux_snk_in(1).sel <= ext_snk_sel_i;
+  mux_snk_in(1).we  <= ext_snk_we_i;
+
+  ext_snk_ack_o   <= mux_snk_out(1).ack;
+  ext_snk_err_o   <= mux_snk_out(1).err;
+  ext_snk_stall_o <= mux_snk_out(1).stall;
+
+  -----------------------------------------------------------------------------
+  -- External Tx Timestamping I/F
+  -----------------------------------------------------------------------------
+  txtsu_port_id_o      <= ep_txtsu_port_id;
+  txtsu_frame_id_o     <= ep_txtsu_frame_id;
+  txtsu_ts_value_o     <= ep_txtsu_ts_value;
+  txtsu_ts_incorrect_o <= ep_txtsu_ts_incorrect;
+
+  -- ts goes to external I/F
+  txtsu_stb_o          <= '1' when (ep_txtsu_stb = '1' and (ep_txtsu_frame_id /= x"0000")) else
+                          '0';
+  -- ts goes to minic
+  mnic_txtsu_stb      <=  '1' when (ep_txtsu_stb = '1' and (ep_txtsu_frame_id  = x"0000")) else
+                          '0';
+
+  ep_txtsu_ack <= txtsu_ack_i or mnic_txtsu_ack;
+
+end struct;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_diags_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_diags_pkg.vhd
new file mode 100644
index 000000000..1bedca028
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_diags_pkg.vhd
@@ -0,0 +1,134 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Core Diagnostics
+---------------------------------------------------------------------------------------
+-- File           : wrc_diags_pkg.vhd
+-- Author         : auto-generated by wbgen2 from wrc_diags_wb.wb
+-- Created        : Mon Nov 27 13:37:56 2017
+-- Version        : 0x00000001
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_diags_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package wrc_diags_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_wrc_diags_in_registers is record
+    ctrl_data_valid_i                        : std_logic;
+    wdiag_sstat_wr_mode_i                    : std_logic;
+    wdiag_sstat_servostate_i                 : std_logic_vector(3 downto 0);
+    wdiag_pstat_link_i                       : std_logic;
+    wdiag_pstat_locked_i                     : std_logic;
+    wdiag_ptpstat_ptpstate_i                 : std_logic_vector(7 downto 0);
+    wdiag_astat_aux_i                        : std_logic_vector(7 downto 0);
+    wdiag_txfcnt_i                           : std_logic_vector(31 downto 0);
+    wdiag_rxfcnt_i                           : std_logic_vector(31 downto 0);
+    wdiag_sec_msb_i                          : std_logic_vector(31 downto 0);
+    wdiag_sec_lsb_i                          : std_logic_vector(31 downto 0);
+    wdiag_ns_i                               : std_logic_vector(31 downto 0);
+    wdiag_mu_msb_i                           : std_logic_vector(31 downto 0);
+    wdiag_mu_lsb_i                           : std_logic_vector(31 downto 0);
+    wdiag_dms_msb_i                          : std_logic_vector(31 downto 0);
+    wdiag_dms_lsb_i                          : std_logic_vector(31 downto 0);
+    wdiag_asym_i                             : std_logic_vector(31 downto 0);
+    wdiag_cko_i                              : std_logic_vector(31 downto 0);
+    wdiag_setp_i                             : std_logic_vector(31 downto 0);
+    wdiag_ucnt_i                             : std_logic_vector(31 downto 0);
+    wdiag_temp_i                             : std_logic_vector(31 downto 0);
+    end record;
+  
+  constant c_wrc_diags_in_registers_init_value: t_wrc_diags_in_registers := (
+    ctrl_data_valid_i => '0',
+    wdiag_sstat_wr_mode_i => '0',
+    wdiag_sstat_servostate_i => (others => '0'),
+    wdiag_pstat_link_i => '0',
+    wdiag_pstat_locked_i => '0',
+    wdiag_ptpstat_ptpstate_i => (others => '0'),
+    wdiag_astat_aux_i => (others => '0'),
+    wdiag_txfcnt_i => (others => '0'),
+    wdiag_rxfcnt_i => (others => '0'),
+    wdiag_sec_msb_i => (others => '0'),
+    wdiag_sec_lsb_i => (others => '0'),
+    wdiag_ns_i => (others => '0'),
+    wdiag_mu_msb_i => (others => '0'),
+    wdiag_mu_lsb_i => (others => '0'),
+    wdiag_dms_msb_i => (others => '0'),
+    wdiag_dms_lsb_i => (others => '0'),
+    wdiag_asym_i => (others => '0'),
+    wdiag_cko_i => (others => '0'),
+    wdiag_setp_i => (others => '0'),
+    wdiag_ucnt_i => (others => '0'),
+    wdiag_temp_i => (others => '0')
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_wrc_diags_out_registers is record
+      ver_id_o                                 : std_logic_vector(31 downto 0);
+      ctrl_data_snapshot_o                     : std_logic;
+      end record;
+    
+    constant c_wrc_diags_out_registers_init_value: t_wrc_diags_out_registers := (
+      ver_id_o => (others => '0'),
+      ctrl_data_snapshot_o => '0'
+      );
+    function "or" (left, right: t_wrc_diags_in_registers) return t_wrc_diags_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body wrc_diags_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if x(i) = '1' then
+tmp(i):= '1';
+else
+tmp(i):= '0';
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_wrc_diags_in_registers) return t_wrc_diags_in_registers is
+variable tmp: t_wrc_diags_in_registers;
+begin
+tmp.ctrl_data_valid_i := f_x_to_zero(left.ctrl_data_valid_i) or f_x_to_zero(right.ctrl_data_valid_i);
+tmp.wdiag_sstat_wr_mode_i := f_x_to_zero(left.wdiag_sstat_wr_mode_i) or f_x_to_zero(right.wdiag_sstat_wr_mode_i);
+tmp.wdiag_sstat_servostate_i := f_x_to_zero(left.wdiag_sstat_servostate_i) or f_x_to_zero(right.wdiag_sstat_servostate_i);
+tmp.wdiag_pstat_link_i := f_x_to_zero(left.wdiag_pstat_link_i) or f_x_to_zero(right.wdiag_pstat_link_i);
+tmp.wdiag_pstat_locked_i := f_x_to_zero(left.wdiag_pstat_locked_i) or f_x_to_zero(right.wdiag_pstat_locked_i);
+tmp.wdiag_ptpstat_ptpstate_i := f_x_to_zero(left.wdiag_ptpstat_ptpstate_i) or f_x_to_zero(right.wdiag_ptpstat_ptpstate_i);
+tmp.wdiag_astat_aux_i := f_x_to_zero(left.wdiag_astat_aux_i) or f_x_to_zero(right.wdiag_astat_aux_i);
+tmp.wdiag_txfcnt_i := f_x_to_zero(left.wdiag_txfcnt_i) or f_x_to_zero(right.wdiag_txfcnt_i);
+tmp.wdiag_rxfcnt_i := f_x_to_zero(left.wdiag_rxfcnt_i) or f_x_to_zero(right.wdiag_rxfcnt_i);
+tmp.wdiag_sec_msb_i := f_x_to_zero(left.wdiag_sec_msb_i) or f_x_to_zero(right.wdiag_sec_msb_i);
+tmp.wdiag_sec_lsb_i := f_x_to_zero(left.wdiag_sec_lsb_i) or f_x_to_zero(right.wdiag_sec_lsb_i);
+tmp.wdiag_ns_i := f_x_to_zero(left.wdiag_ns_i) or f_x_to_zero(right.wdiag_ns_i);
+tmp.wdiag_mu_msb_i := f_x_to_zero(left.wdiag_mu_msb_i) or f_x_to_zero(right.wdiag_mu_msb_i);
+tmp.wdiag_mu_lsb_i := f_x_to_zero(left.wdiag_mu_lsb_i) or f_x_to_zero(right.wdiag_mu_lsb_i);
+tmp.wdiag_dms_msb_i := f_x_to_zero(left.wdiag_dms_msb_i) or f_x_to_zero(right.wdiag_dms_msb_i);
+tmp.wdiag_dms_lsb_i := f_x_to_zero(left.wdiag_dms_lsb_i) or f_x_to_zero(right.wdiag_dms_lsb_i);
+tmp.wdiag_asym_i := f_x_to_zero(left.wdiag_asym_i) or f_x_to_zero(right.wdiag_asym_i);
+tmp.wdiag_cko_i := f_x_to_zero(left.wdiag_cko_i) or f_x_to_zero(right.wdiag_cko_i);
+tmp.wdiag_setp_i := f_x_to_zero(left.wdiag_setp_i) or f_x_to_zero(right.wdiag_setp_i);
+tmp.wdiag_ucnt_i := f_x_to_zero(left.wdiag_ucnt_i) or f_x_to_zero(right.wdiag_ucnt_i);
+tmp.wdiag_temp_i := f_x_to_zero(left.wdiag_temp_i) or f_x_to_zero(right.wdiag_temp_i);
+return tmp;
+end function;
+end package body;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_diags_wb.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_diags_wb.vhd
new file mode 100644
index 000000000..99b6e9252
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_diags_wb.vhd
@@ -0,0 +1,376 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Core Diagnostics
+---------------------------------------------------------------------------------------
+-- File           : wrc_diags_wb.vhd
+-- Author         : auto-generated by wbgen2 from wrc_diags_wb.wb
+-- Created        : Mon Nov 27 13:37:56 2017
+-- Version        : 0x00000001
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_diags_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wrc_diags_wbgen2_pkg.all;
+
+
+entity wrc_diags_wb is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(4 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    regs_i                                   : in     t_wrc_diags_in_registers;
+    regs_o                                   : out    t_wrc_diags_out_registers
+  );
+end wrc_diags_wb;
+
+architecture syn of wrc_diags_wb is
+
+signal wrc_diags_ver_id_int                     : std_logic_vector(31 downto 0);
+signal wrc_diags_ctrl_data_snapshot_int         : std_logic      ;
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal rwaddr_reg                               : std_logic_vector(4 downto 0);
+signal ack_in_progress                          : std_logic      ;
+
+begin
+-- Some internal signals assignments
+  wrdata_reg <= wb_dat_i;
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      wrc_diags_ver_id_int <= "00000000000000000000000000000001";
+      wrc_diags_ctrl_data_snapshot_int <= '0';
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          ack_in_progress <= '0';
+        else
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(4 downto 0) is
+          when "00000" => 
+            if (wb_we_i = '1') then
+              wrc_diags_ver_id_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= wrc_diags_ver_id_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00001" => 
+            if (wb_we_i = '1') then
+              wrc_diags_ctrl_data_snapshot_int <= wrdata_reg(8);
+            end if;
+            rddata_reg(0) <= regs_i.ctrl_data_valid_i;
+            rddata_reg(8) <= wrc_diags_ctrl_data_snapshot_int;
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00010" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(0) <= regs_i.wdiag_sstat_wr_mode_i;
+            rddata_reg(11 downto 8) <= regs_i.wdiag_sstat_servostate_i;
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(0) <= regs_i.wdiag_pstat_link_i;
+            rddata_reg(1) <= regs_i.wdiag_pstat_locked_i;
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00100" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(7 downto 0) <= regs_i.wdiag_ptpstat_ptpstate_i;
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(7 downto 0) <= regs_i.wdiag_astat_aux_i;
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00110" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_txfcnt_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00111" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_rxfcnt_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01000" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_sec_msb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01001" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_sec_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01010" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_ns_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_mu_msb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01100" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_mu_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_dms_msb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01110" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_dms_lsb_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01111" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_asym_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10000" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_cko_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10001" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_setp_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10010" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_ucnt_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.wdiag_temp_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- Version identifier
+  regs_o.ver_id_o <= wrc_diags_ver_id_int;
+-- WR DIAG data valid
+-- WR DIAG data snapshot
+  regs_o.ctrl_data_snapshot_o <= wrc_diags_ctrl_data_snapshot_int;
+-- WR valid
+-- Servo State
+-- Link Status
+-- PLL Locked
+-- PTP State
+-- AUX channel
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+-- Data
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_periph.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_periph.vhd
new file mode 100644
index 000000000..ee6035524
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_periph.vhd
@@ -0,0 +1,520 @@
+-------------------------------------------------------------------------------
+-- Title      : WhiteRabbit PTP Core peripherials
+-- Project    : WhiteRabbit
+-------------------------------------------------------------------------------
+-- File       : wrc_periph.vhd
+-- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2011-04-04
+-- Last update: 2017-04-25
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- WRC_PERIPH integrates WRC_SYSCON, UART/VUART, 1-Wire Master, WRPC_DIAGS
+-- 
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 - 2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wrcore_pkg.all;
+use work.wishbone_pkg.all;
+use work.sysc_wbgen2_pkg.all;
+use work.wrc_diags_wbgen2_pkg.all;
+
+entity wrc_periph is
+  generic(
+    g_board_name      : string  := "NA  ";
+    g_flash_secsz_kb    : integer := 256;        -- default for SVEC (M25P128)
+    g_flash_sdbfs_baddr : integer := 16#600000#; -- default for SVEC (M25P128)
+    g_phys_uart       : boolean := true;
+    g_virtual_uart    : boolean := false;
+    g_cntr_period     : integer := 62500;
+    g_mem_words       : integer := 16384;   --in 32-bit words
+    g_vuart_fifo_size : integer := 1024;
+    g_diag_id         : integer := 0;
+    g_diag_ver        : integer := 0;
+    g_diag_ro_size    : integer := 0;
+    g_diag_rw_size    : integer := 0
+    );
+  port(
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    rst_net_n_o : out std_logic;
+    rst_wrc_n_o : out std_logic;
+
+    led_red_o   : out std_logic;
+    led_green_o : out std_logic;
+    scl_o       : out std_logic;
+    scl_i       : in  std_logic;
+    sda_o       : out std_logic;
+    sda_i       : in  std_logic;
+    sfp_scl_o   : out std_logic;
+    sfp_scl_i   : in  std_logic;
+    sfp_sda_o   : out std_logic;
+    sfp_sda_i   : in  std_logic;
+    sfp_det_i   : in  std_logic;
+    memsize_i   : in  std_logic_vector(3 downto 0);
+    btn1_i      : in  std_logic;
+    btn2_i      : in  std_logic;
+    spi_sclk_o  : out std_logic;
+    spi_ncs_o   : out std_logic;
+    spi_mosi_o  : out std_logic;
+    spi_miso_i  : in  std_logic;
+
+    slave_i : in  t_wishbone_slave_in_array(0 to 3);
+    slave_o : out t_wishbone_slave_out_array(0 to 3);
+
+    uart_rxd_i : in  std_logic;
+    uart_txd_o : out std_logic;
+
+    -- 1-Wire
+    owr_pwren_o: out std_logic_vector(1 downto 0);
+    owr_en_o : out std_logic_vector(1 downto 0);
+    owr_i    : in  std_logic_vector(1 downto 0);
+
+    -- optional diagnostics from external HDL modules
+    diag_array_in  : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others=>(others=>'0'));
+    diag_array_out : out t_generic_word_array(g_diag_rw_size-1 downto 0)
+    );
+end wrc_periph;
+
+architecture struct of wrc_periph is
+
+  function f_cnt_memsize(words : integer) return std_logic_vector is
+  begin
+    return std_logic_vector(to_unsigned(words * 4 / 1024 / 16 - 1, 4));
+    -- *4     - to get size in bytes
+    -- /1024  - to get size in kB
+    -- /16 -1 - to get size in format of MEMSIZE@sysc_hwfr register
+  end f_cnt_memsize;
+
+  function f_board_name_conv(name : string) return std_logic_vector is
+    variable ret : std_logic_vector(31 downto 0);
+  begin
+    assert (name'length= 4)
+    report "Board name has to be exactly 4 letters string" severity failure;
+    ret(31 downto 24) := std_logic_vector(to_unsigned(character'pos(name(1)), 8));
+    ret(23 downto 16) := std_logic_vector(to_unsigned(character'pos(name(2)), 8));
+    ret(15 downto  8) := std_logic_vector(to_unsigned(character'pos(name(3)), 8));
+    ret( 7 downto  0) := std_logic_vector(to_unsigned(character'pos(name(4)), 8));
+    return ret;
+  end f_board_name_conv;
+
+  signal sysc_regs_i : t_sysc_in_registers;
+  signal sysc_regs_o : t_sysc_out_registers;
+
+  signal cntr_div      : unsigned(23 downto 0);
+  signal cntr_tics     : unsigned(31 downto 0);
+  signal cntr_overflow : std_logic;
+  
+  signal rst_wrc_n_o_reg : std_logic := '1';
+  signal diag_adr : unsigned(15 downto 0);
+  signal diag_dat : std_logic_vector(31 downto 0);
+  signal diag_out_regs : t_generic_word_array(g_diag_rw_size - 1 downto 0);
+  signal diag_in       : t_generic_word_array(g_diag_ro_size + g_diag_rw_size-1 downto 0);
+  signal wrpc_diag_regs_in     : t_wrc_diags_in_registers;
+  signal wrpc_diag_regs_out    : t_wrc_diags_out_registers;
+
+begin
+
+  rst_wrc_n_o <= rst_n_i and rst_wrc_n_o_reg;
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i = '0') then
+        rst_net_n_o <= '0';
+        rst_wrc_n_o_reg <= '1';
+      else
+
+        if(sysc_regs_o.rstr_trig_wr_o = '1' and sysc_regs_o.rstr_trig_o = x"deadbee") then
+          rst_wrc_n_o_reg <= not sysc_regs_o.rstr_rst_o;
+        end if; 
+            
+        rst_net_n_o <= not sysc_regs_o.gpsr_net_rst_o;
+      end if; 
+    end if; 
+  end process;
+  
+  -------------------------------------
+  -- LEDs
+  -------------------------------------
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(sysc_regs_o.gpsr_led_link_o = '1') then
+        led_red_o <= '1';
+      elsif(sysc_regs_o.gpcr_led_link_o = '1') then
+        led_red_o <= '0';
+      end if;
+
+      if(sysc_regs_o.gpsr_led_stat_o = '1') then
+        led_green_o <= '1';
+      elsif(sysc_regs_o.gpcr_led_stat_o = '1') then
+        led_green_o <= '0';
+      end if;
+    end if;
+  end process;
+
+  -------------------------------------
+  -- buttons
+  -------------------------------------
+  sysc_regs_i.gpsr_btn1_i <= btn1_i;
+  sysc_regs_i.gpsr_btn2_i <= btn2_i;
+
+  -------------------------------------
+  -- MEMSIZE
+  -------------------------------------
+  sysc_regs_i.hwfr_memsize_i(3 downto 0) <= f_cnt_memsize(g_mem_words);
+
+  -------------------------------------
+  -- BOARD NAME and Flash info
+  -------------------------------------
+  sysc_regs_i.hwir_name_i         <= f_board_name_conv(g_board_name);
+  sysc_regs_i.hwfr_storage_sec_i  <= std_logic_vector(to_unsigned(g_flash_secsz_kb, 16));
+  sysc_regs_i.hwfr_storage_type_i <= "00";  -- for now these parameters are only for Flash
+  sysc_regs_i.sdbfs_baddr_i       <= std_logic_vector(to_unsigned(g_flash_sdbfs_baddr, 32));
+
+  -------------------------------------
+  -- TIMER
+  -------------------------------------
+  sysc_regs_i.tvr_i      <= std_logic_vector(cntr_tics);
+  sysc_regs_i.tcr_tdiv_i <= (others => '0');
+
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i = '0') then
+        cntr_div      <= (others => '0');
+        cntr_overflow <= '0';
+      elsif(sysc_regs_o.tcr_enable_o = '1') then
+        if(cntr_div = g_cntr_period-1) then
+          cntr_div      <= (others => '0');
+          cntr_overflow <= '1';
+        else
+          cntr_div      <= cntr_div + 1;
+          cntr_overflow <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  --msec counter
+  process(clk_sys_i)
+  begin
+    if(rising_edge(clk_sys_i)) then
+      if(rst_n_i = '0') then
+        cntr_tics <= (others => '0');
+      elsif(cntr_overflow = '1') then
+        cntr_tics <= cntr_tics + 1;
+      end if;
+    end if;
+  end process;
+
+  -------------------------------------
+  -- I2C - FMC
+  -------------------------------------
+  p_drive_i2c : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        scl_o <= '1';
+        sda_o <= '1';
+      else
+        if(sysc_regs_o.gpsr_fmc_sda_load_o = '1' and sysc_regs_o.gpsr_fmc_sda_o = '1') then
+          sda_o <= '1';
+        elsif(sysc_regs_o.gpcr_fmc_sda_o = '1') then
+          sda_o <= '0';
+        end if;
+
+        if(sysc_regs_o.gpsr_fmc_scl_load_o = '1' and sysc_regs_o.gpsr_fmc_scl_o = '1') then
+          scl_o <= '1';
+        elsif(sysc_regs_o.gpcr_fmc_scl_o = '1') then
+          scl_o <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  sysc_regs_i.gpsr_fmc_sda_i <= sda_i;
+  sysc_regs_i.gpsr_fmc_scl_i <= scl_i;
+
+  -------------------------------------
+  -- I2C - SFP
+  -------------------------------------
+  p_drive_sfpi2c : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        sfp_scl_o <= '1';
+        sfp_sda_o <= '1';
+      else
+        if(sysc_regs_o.gpsr_sfp_sda_load_o = '1' and sysc_regs_o.gpsr_sfp_sda_o = '1') then
+          sfp_sda_o <= '1';
+        elsif(sysc_regs_o.gpcr_sfp_sda_o = '1') then
+          sfp_sda_o <= '0';
+        end if;
+
+        if(sysc_regs_o.gpsr_sfp_scl_load_o = '1' and sysc_regs_o.gpsr_sfp_scl_o = '1') then
+          sfp_scl_o <= '1';
+        elsif(sysc_regs_o.gpcr_sfp_scl_o = '1') then
+          sfp_scl_o <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  sysc_regs_i.gpsr_sfp_sda_i <= sfp_sda_i;
+  sysc_regs_i.gpsr_sfp_scl_i <= sfp_scl_i;
+
+  sysc_regs_i.gpsr_sfp_det_i <= sfp_det_i;
+
+  -------------------------------------
+  -- SPI - Flash
+  -------------------------------------
+  p_drive_spi: process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        spi_sclk_o  <= '0';
+        spi_mosi_o  <= '0';
+        spi_ncs_o   <= '1';
+      else
+        if(sysc_regs_o.gpsr_spi_sclk_load_o = '1' and sysc_regs_o.gpsr_spi_sclk_o = '1') then
+          spi_sclk_o <= '1';
+        elsif(sysc_regs_o.gpcr_spi_sclk_o = '1') then
+          spi_sclk_o <= '0';
+        end if;
+
+        if(sysc_regs_o.gpsr_spi_ncs_load_o = '1' and sysc_regs_o.gpsr_spi_ncs_o = '1') then
+          spi_ncs_o <= '1';
+        elsif(sysc_regs_o.gpcr_spi_cs_o = '1') then
+          spi_ncs_o <= '0';
+        end if;
+
+        if(sysc_regs_o.gpsr_spi_mosi_load_o = '1' and sysc_regs_o.gpsr_spi_mosi_o = '1') then
+          spi_mosi_o <= '1';
+        elsif(sysc_regs_o.gpcr_spi_mosi_o = '1') then
+          spi_mosi_o <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+  sysc_regs_i.gpsr_spi_sclk_i <= '0';
+  sysc_regs_i.gpsr_spi_ncs_i  <= '0';
+  sysc_regs_i.gpsr_spi_mosi_i <= '0';
+  sysc_regs_i.gpsr_spi_miso_i <= spi_miso_i;
+
+
+  -------------------------------------
+  -- DIAG to/from external modules
+  -------------------------------------
+  -- first, provide all the constants
+  sysc_regs_i.diag_info_id_i  <= std_logic_vector(to_unsigned(g_diag_id, 16));
+  sysc_regs_i.diag_info_ver_i <= std_logic_vector(to_unsigned(g_diag_ver, 16));
+  sysc_regs_i.diag_nw_ro_i  <= std_logic_vector(to_unsigned(g_diag_ro_size, 16));
+  sysc_regs_i.diag_nw_rw_i <= std_logic_vector(to_unsigned(g_diag_rw_size, 16));
+
+  diag_array_out <= diag_out_regs;
+  -- r/w registers can be also read
+  diag_in(g_diag_rw_size - 1 downto 0) <= diag_out_regs;
+  -- r/o array after r/w registers for reading
+  diag_in(g_diag_ro_size + g_diag_rw_size-1 downto g_diag_rw_size) <= diag_array_in;
+
+  p_diag_rw: process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        diag_adr <= (others=>'0');
+        diag_dat <= (others=>'0');
+      else
+        if sysc_regs_o.diag_cr_adr_load_o = '1' then
+          diag_adr <= unsigned(sysc_regs_o.diag_cr_adr_o);
+        end if;
+        if sysc_regs_o.diag_dat_load_o = '1' then
+          diag_dat <= sysc_regs_o.diag_dat_o;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  sysc_regs_i.diag_cr_adr_i    <= std_logic_vector(diag_adr);
+  GEN_DIAG_NODAT: if g_diag_rw_size = 0 and g_diag_ro_size = 0 generate
+    sysc_regs_i.diag_dat_i <= (others=>'0');
+  end generate;
+  GEN_DIAG_DAT: if g_diag_rw_size /= 0 or g_diag_ro_size /= 0 generate
+    sysc_regs_i.diag_dat_i <= diag_in(to_integer(diag_adr));
+  end generate;
+
+  -- Write request for each r/w register
+  GEN_DIAG_W: if g_diag_rw_size > 0 generate
+    GEN_LOOP: for I in 0 to g_diag_rw_size-1 generate
+
+      process(clk_sys_i)
+      begin
+        if rising_edge(clk_sys_i) then
+          if rst_n_i = '0' then
+            diag_out_regs(I) <= (others=>'0');
+          elsif sysc_regs_o.diag_cr_adr_load_o = '1' and sysc_regs_o.diag_cr_rw_o = '1' and
+            to_integer(unsigned(sysc_regs_o.diag_cr_adr_o)) = I then
+              diag_out_regs(I) <= diag_dat;
+          end if;
+        end if;
+      end process;
+
+    end generate;
+  end generate;
+
+  GEN_NODIAG_W: if g_diag_rw_size = 0 generate
+    diag_array_out <= (others=>(others=>'0'));
+  end generate;
+
+  ----------------------------------------
+  -- SYSCON
+  ----------------------------------------
+  SYSCON : entity work.wrc_syscon_wb
+    port map (
+      rst_n_i    => rst_n_i,
+      clk_sys_i  => clk_sys_i,
+      wb_adr_i   => slave_i(0).adr(6 downto 2), -- shift address for word addressing
+      wb_dat_i   => slave_i(0).dat,
+      wb_dat_o   => slave_o(0).dat,
+      wb_cyc_i   => slave_i(0).cyc,
+      wb_sel_i   => slave_i(0).sel,
+      wb_stb_i   => slave_i(0).stb,
+      wb_we_i    => slave_i(0).we,
+      wb_ack_o   => slave_o(0).ack,
+      wb_stall_o => slave_o(0).stall,
+      regs_i     => sysc_regs_i,
+      regs_o     => sysc_regs_o);
+
+  slave_o(0).err <= '0';
+  slave_o(0).rty <= '0';
+  slave_o(0).int <= '0';
+
+  --------------------------------------
+  -- UART
+  --------------------------------------
+  UART : xwb_simple_uart
+    generic map(
+      g_with_virtual_uart   => g_virtual_uart,
+      g_with_physical_uart  => g_phys_uart,
+      g_interface_mode      => PIPELINED,
+      g_address_granularity => BYTE,
+      g_vuart_fifo_size     => g_vuart_fifo_size
+      )
+    port map(
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+
+      -- Wishbone
+      slave_i => slave_i(1),
+      slave_o => slave_o(1),
+      desc_o  => open,
+
+      uart_rxd_i => uart_rxd_i,
+      uart_txd_o => uart_txd_o
+      );
+
+  --------------------------------------
+  -- 1-WIRE
+  --------------------------------------
+  ONEWIRE : xwb_onewire_master
+    generic map(
+      g_interface_mode      => PIPELINED,
+      g_address_granularity => BYTE,
+      g_num_ports           => 2,
+      g_ow_btp_normal       => "5.0",
+      g_ow_btp_overdrive    => "1.0"
+      )
+    port map(
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+
+      -- Wishbone
+      slave_i => slave_i(2),
+      slave_o => slave_o(2),
+      desc_o  => open,
+
+      owr_pwren_o => owr_pwren_o,
+      owr_en_o => owr_en_o,
+      owr_i    => owr_i
+      );
+
+  --------------------------------------
+  -- WRPC Diags
+  --------------------------------------
+
+  -- access through WB (PCI/VME/application) to diagnostics of WRPC
+  DIAGS: xwr_diags_wb
+    generic map(
+      g_interface_mode      => PIPELINED,
+      g_address_granularity => BYTE
+    )
+    port map(
+      rst_n_i   => rst_n_i,
+      clk_sys_i => clk_sys_i,
+
+      slave_i   => slave_i(3),
+      slave_o   => slave_o(3),
+
+      regs_i    => wrpc_diag_regs_in,
+      regs_o    => wrpc_diag_regs_out
+    );
+
+   -- the information written to syscon WB registers by LM32 are available to the
+   -- user via diag WB registers
+   -- It might look strange that we use two WB modules for that. Since both LM32
+   -- and user application need to access these registers through the same
+   -- wishbone interface we would needed these registers to be R/W. By creating
+   -- another module (xwr_diags_wb) we make read-only registers to be read by
+   -- the external tool. We want to minimize the possibility of user application
+   -- overwriting these values, thus we want them to be read-only.
+   sysc_regs_i.wdiag_ctrl_data_snapshot_i      <= wrpc_diag_regs_out.ctrl_data_snapshot_o;
+   wrpc_diag_regs_in.ctrl_data_valid_i         <= sysc_regs_o.wdiag_ctrl_data_valid_o;
+   wrpc_diag_regs_in.wdiag_sstat_wr_mode_i     <= sysc_regs_o.wdiag_sstat_wr_mode_o;
+   wrpc_diag_regs_in.wdiag_sstat_servostate_i  <= sysc_regs_o.wdiag_sstat_servostate_o;
+   wrpc_diag_regs_in.wdiag_pstat_link_i        <= sysc_regs_o.wdiag_pstat_link_o;
+   wrpc_diag_regs_in.wdiag_pstat_locked_i      <= sysc_regs_o.wdiag_pstat_locked_o;
+   wrpc_diag_regs_in.wdiag_ptpstat_ptpstate_i  <= sysc_regs_o.wdiag_ptpstat_ptpstate_o;
+   wrpc_diag_regs_in.wdiag_astat_aux_i         <= sysc_regs_o.wdiag_astat_aux_o;
+   wrpc_diag_regs_in.wdiag_txfcnt_i            <= sysc_regs_o.wdiag_txfcnt_o;
+   wrpc_diag_regs_in.wdiag_rxfcnt_i            <= sysc_regs_o.wdiag_rxfcnt_o;
+   wrpc_diag_regs_in.wdiag_sec_msb_i           <= sysc_regs_o.wdiag_sec_msb_o;
+   wrpc_diag_regs_in.wdiag_sec_lsb_i           <= sysc_regs_o.wdiag_sec_lsb_o;
+   wrpc_diag_regs_in.wdiag_ns_i                <= sysc_regs_o.wdiag_ns_o;
+   wrpc_diag_regs_in.wdiag_mu_msb_i            <= sysc_regs_o.wdiag_mu_msb_o;
+   wrpc_diag_regs_in.wdiag_mu_lsb_i            <= sysc_regs_o.wdiag_mu_lsb_o;
+   wrpc_diag_regs_in.wdiag_dms_msb_i           <= sysc_regs_o.wdiag_dms_msb_o;
+   wrpc_diag_regs_in.wdiag_dms_lsb_i           <= sysc_regs_o.wdiag_dms_lsb_o;
+   wrpc_diag_regs_in.wdiag_asym_i              <= sysc_regs_o.wdiag_asym_o;
+   wrpc_diag_regs_in.wdiag_cko_i               <= sysc_regs_o.wdiag_cko_o;
+   wrpc_diag_regs_in.wdiag_setp_i              <= sysc_regs_o.wdiag_setp_o;
+   wrpc_diag_regs_in.wdiag_ucnt_i              <= sysc_regs_o.wdiag_ucnt_o;
+   wrpc_diag_regs_in.wdiag_temp_i              <= sysc_regs_o.wdiag_temp_o;
+
+end struct;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_syscon_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_syscon_pkg.vhd
new file mode 100644
index 000000000..9b33530ce
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_syscon_pkg.vhd
@@ -0,0 +1,253 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Core System Controller
+---------------------------------------------------------------------------------------
+-- File           : wrc_syscon_pkg.vhd
+-- Author         : auto-generated by wbgen2 from wrc_syscon_wb.wb
+-- Created        : Mon Nov 27 13:37:56 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package sysc_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_sysc_in_registers is record
+    gpsr_fmc_scl_i                           : std_logic;
+    gpsr_fmc_sda_i                           : std_logic;
+    gpsr_btn1_i                              : std_logic;
+    gpsr_btn2_i                              : std_logic;
+    gpsr_sfp_det_i                           : std_logic;
+    gpsr_sfp_scl_i                           : std_logic;
+    gpsr_sfp_sda_i                           : std_logic;
+    gpsr_spi_sclk_i                          : std_logic;
+    gpsr_spi_ncs_i                           : std_logic;
+    gpsr_spi_mosi_i                          : std_logic;
+    gpsr_spi_miso_i                          : std_logic;
+    hwfr_memsize_i                           : std_logic_vector(3 downto 0);
+    hwfr_storage_type_i                      : std_logic_vector(1 downto 0);
+    hwfr_storage_sec_i                       : std_logic_vector(15 downto 0);
+    hwir_name_i                              : std_logic_vector(31 downto 0);
+    sdbfs_baddr_i                            : std_logic_vector(31 downto 0);
+    tcr_tdiv_i                               : std_logic_vector(11 downto 0);
+    tvr_i                                    : std_logic_vector(31 downto 0);
+    diag_info_ver_i                          : std_logic_vector(15 downto 0);
+    diag_info_id_i                           : std_logic_vector(15 downto 0);
+    diag_nw_rw_i                             : std_logic_vector(15 downto 0);
+    diag_nw_ro_i                             : std_logic_vector(15 downto 0);
+    diag_cr_adr_i                            : std_logic_vector(15 downto 0);
+    diag_dat_i                               : std_logic_vector(31 downto 0);
+    wdiag_ctrl_data_snapshot_i               : std_logic;
+    end record;
+  
+  constant c_sysc_in_registers_init_value: t_sysc_in_registers := (
+    gpsr_fmc_scl_i => '0',
+    gpsr_fmc_sda_i => '0',
+    gpsr_btn1_i => '0',
+    gpsr_btn2_i => '0',
+    gpsr_sfp_det_i => '0',
+    gpsr_sfp_scl_i => '0',
+    gpsr_sfp_sda_i => '0',
+    gpsr_spi_sclk_i => '0',
+    gpsr_spi_ncs_i => '0',
+    gpsr_spi_mosi_i => '0',
+    gpsr_spi_miso_i => '0',
+    hwfr_memsize_i => (others => '0'),
+    hwfr_storage_type_i => (others => '0'),
+    hwfr_storage_sec_i => (others => '0'),
+    hwir_name_i => (others => '0'),
+    sdbfs_baddr_i => (others => '0'),
+    tcr_tdiv_i => (others => '0'),
+    tvr_i => (others => '0'),
+    diag_info_ver_i => (others => '0'),
+    diag_info_id_i => (others => '0'),
+    diag_nw_rw_i => (others => '0'),
+    diag_nw_ro_i => (others => '0'),
+    diag_cr_adr_i => (others => '0'),
+    diag_dat_i => (others => '0'),
+    wdiag_ctrl_data_snapshot_i => '0'
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_sysc_out_registers is record
+      rstr_trig_o                              : std_logic_vector(27 downto 0);
+      rstr_trig_wr_o                           : std_logic;
+      rstr_rst_o                               : std_logic;
+      gpsr_led_stat_o                          : std_logic;
+      gpsr_led_link_o                          : std_logic;
+      gpsr_fmc_scl_o                           : std_logic;
+      gpsr_fmc_scl_load_o                      : std_logic;
+      gpsr_fmc_sda_o                           : std_logic;
+      gpsr_fmc_sda_load_o                      : std_logic;
+      gpsr_net_rst_o                           : std_logic;
+      gpsr_sfp_scl_o                           : std_logic;
+      gpsr_sfp_scl_load_o                      : std_logic;
+      gpsr_sfp_sda_o                           : std_logic;
+      gpsr_sfp_sda_load_o                      : std_logic;
+      gpsr_spi_sclk_o                          : std_logic;
+      gpsr_spi_sclk_load_o                     : std_logic;
+      gpsr_spi_ncs_o                           : std_logic;
+      gpsr_spi_ncs_load_o                      : std_logic;
+      gpsr_spi_mosi_o                          : std_logic;
+      gpsr_spi_mosi_load_o                     : std_logic;
+      gpcr_led_stat_o                          : std_logic;
+      gpcr_led_link_o                          : std_logic;
+      gpcr_fmc_scl_o                           : std_logic;
+      gpcr_fmc_sda_o                           : std_logic;
+      gpcr_sfp_scl_o                           : std_logic;
+      gpcr_sfp_sda_o                           : std_logic;
+      gpcr_spi_sclk_o                          : std_logic;
+      gpcr_spi_cs_o                            : std_logic;
+      gpcr_spi_mosi_o                          : std_logic;
+      tcr_enable_o                             : std_logic;
+      diag_cr_adr_o                            : std_logic_vector(15 downto 0);
+      diag_cr_adr_load_o                       : std_logic;
+      diag_cr_rw_o                             : std_logic;
+      diag_dat_o                               : std_logic_vector(31 downto 0);
+      diag_dat_load_o                          : std_logic;
+      wdiag_ctrl_data_valid_o                  : std_logic;
+      wdiag_sstat_wr_mode_o                    : std_logic;
+      wdiag_sstat_servostate_o                 : std_logic_vector(3 downto 0);
+      wdiag_pstat_link_o                       : std_logic;
+      wdiag_pstat_locked_o                     : std_logic;
+      wdiag_ptpstat_ptpstate_o                 : std_logic_vector(7 downto 0);
+      wdiag_astat_aux_o                        : std_logic_vector(7 downto 0);
+      wdiag_txfcnt_o                           : std_logic_vector(31 downto 0);
+      wdiag_rxfcnt_o                           : std_logic_vector(31 downto 0);
+      wdiag_sec_msb_o                          : std_logic_vector(31 downto 0);
+      wdiag_sec_lsb_o                          : std_logic_vector(31 downto 0);
+      wdiag_ns_o                               : std_logic_vector(31 downto 0);
+      wdiag_mu_msb_o                           : std_logic_vector(31 downto 0);
+      wdiag_mu_lsb_o                           : std_logic_vector(31 downto 0);
+      wdiag_dms_msb_o                          : std_logic_vector(31 downto 0);
+      wdiag_dms_lsb_o                          : std_logic_vector(31 downto 0);
+      wdiag_asym_o                             : std_logic_vector(31 downto 0);
+      wdiag_cko_o                              : std_logic_vector(31 downto 0);
+      wdiag_setp_o                             : std_logic_vector(31 downto 0);
+      wdiag_ucnt_o                             : std_logic_vector(31 downto 0);
+      wdiag_temp_o                             : std_logic_vector(31 downto 0);
+      end record;
+    
+    constant c_sysc_out_registers_init_value: t_sysc_out_registers := (
+      rstr_trig_o => (others => '0'),
+      rstr_trig_wr_o => '0',
+      rstr_rst_o => '0',
+      gpsr_led_stat_o => '0',
+      gpsr_led_link_o => '0',
+      gpsr_fmc_scl_o => '0',
+      gpsr_fmc_scl_load_o => '0',
+      gpsr_fmc_sda_o => '0',
+      gpsr_fmc_sda_load_o => '0',
+      gpsr_net_rst_o => '0',
+      gpsr_sfp_scl_o => '0',
+      gpsr_sfp_scl_load_o => '0',
+      gpsr_sfp_sda_o => '0',
+      gpsr_sfp_sda_load_o => '0',
+      gpsr_spi_sclk_o => '0',
+      gpsr_spi_sclk_load_o => '0',
+      gpsr_spi_ncs_o => '0',
+      gpsr_spi_ncs_load_o => '0',
+      gpsr_spi_mosi_o => '0',
+      gpsr_spi_mosi_load_o => '0',
+      gpcr_led_stat_o => '0',
+      gpcr_led_link_o => '0',
+      gpcr_fmc_scl_o => '0',
+      gpcr_fmc_sda_o => '0',
+      gpcr_sfp_scl_o => '0',
+      gpcr_sfp_sda_o => '0',
+      gpcr_spi_sclk_o => '0',
+      gpcr_spi_cs_o => '0',
+      gpcr_spi_mosi_o => '0',
+      tcr_enable_o => '0',
+      diag_cr_adr_o => (others => '0'),
+      diag_cr_adr_load_o => '0',
+      diag_cr_rw_o => '0',
+      diag_dat_o => (others => '0'),
+      diag_dat_load_o => '0',
+      wdiag_ctrl_data_valid_o => '0',
+      wdiag_sstat_wr_mode_o => '0',
+      wdiag_sstat_servostate_o => (others => '0'),
+      wdiag_pstat_link_o => '0',
+      wdiag_pstat_locked_o => '0',
+      wdiag_ptpstat_ptpstate_o => (others => '0'),
+      wdiag_astat_aux_o => (others => '0'),
+      wdiag_txfcnt_o => (others => '0'),
+      wdiag_rxfcnt_o => (others => '0'),
+      wdiag_sec_msb_o => (others => '0'),
+      wdiag_sec_lsb_o => (others => '0'),
+      wdiag_ns_o => (others => '0'),
+      wdiag_mu_msb_o => (others => '0'),
+      wdiag_mu_lsb_o => (others => '0'),
+      wdiag_dms_msb_o => (others => '0'),
+      wdiag_dms_lsb_o => (others => '0'),
+      wdiag_asym_o => (others => '0'),
+      wdiag_cko_o => (others => '0'),
+      wdiag_setp_o => (others => '0'),
+      wdiag_ucnt_o => (others => '0'),
+      wdiag_temp_o => (others => '0')
+      );
+    function "or" (left, right: t_sysc_in_registers) return t_sysc_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body sysc_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if x(i) = '1' then
+tmp(i):= '1';
+else
+tmp(i):= '0';
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_sysc_in_registers) return t_sysc_in_registers is
+variable tmp: t_sysc_in_registers;
+begin
+tmp.gpsr_fmc_scl_i := f_x_to_zero(left.gpsr_fmc_scl_i) or f_x_to_zero(right.gpsr_fmc_scl_i);
+tmp.gpsr_fmc_sda_i := f_x_to_zero(left.gpsr_fmc_sda_i) or f_x_to_zero(right.gpsr_fmc_sda_i);
+tmp.gpsr_btn1_i := f_x_to_zero(left.gpsr_btn1_i) or f_x_to_zero(right.gpsr_btn1_i);
+tmp.gpsr_btn2_i := f_x_to_zero(left.gpsr_btn2_i) or f_x_to_zero(right.gpsr_btn2_i);
+tmp.gpsr_sfp_det_i := f_x_to_zero(left.gpsr_sfp_det_i) or f_x_to_zero(right.gpsr_sfp_det_i);
+tmp.gpsr_sfp_scl_i := f_x_to_zero(left.gpsr_sfp_scl_i) or f_x_to_zero(right.gpsr_sfp_scl_i);
+tmp.gpsr_sfp_sda_i := f_x_to_zero(left.gpsr_sfp_sda_i) or f_x_to_zero(right.gpsr_sfp_sda_i);
+tmp.gpsr_spi_sclk_i := f_x_to_zero(left.gpsr_spi_sclk_i) or f_x_to_zero(right.gpsr_spi_sclk_i);
+tmp.gpsr_spi_ncs_i := f_x_to_zero(left.gpsr_spi_ncs_i) or f_x_to_zero(right.gpsr_spi_ncs_i);
+tmp.gpsr_spi_mosi_i := f_x_to_zero(left.gpsr_spi_mosi_i) or f_x_to_zero(right.gpsr_spi_mosi_i);
+tmp.gpsr_spi_miso_i := f_x_to_zero(left.gpsr_spi_miso_i) or f_x_to_zero(right.gpsr_spi_miso_i);
+tmp.hwfr_memsize_i := f_x_to_zero(left.hwfr_memsize_i) or f_x_to_zero(right.hwfr_memsize_i);
+tmp.hwfr_storage_type_i := f_x_to_zero(left.hwfr_storage_type_i) or f_x_to_zero(right.hwfr_storage_type_i);
+tmp.hwfr_storage_sec_i := f_x_to_zero(left.hwfr_storage_sec_i) or f_x_to_zero(right.hwfr_storage_sec_i);
+tmp.hwir_name_i := f_x_to_zero(left.hwir_name_i) or f_x_to_zero(right.hwir_name_i);
+tmp.sdbfs_baddr_i := f_x_to_zero(left.sdbfs_baddr_i) or f_x_to_zero(right.sdbfs_baddr_i);
+tmp.tcr_tdiv_i := f_x_to_zero(left.tcr_tdiv_i) or f_x_to_zero(right.tcr_tdiv_i);
+tmp.tvr_i := f_x_to_zero(left.tvr_i) or f_x_to_zero(right.tvr_i);
+tmp.diag_info_ver_i := f_x_to_zero(left.diag_info_ver_i) or f_x_to_zero(right.diag_info_ver_i);
+tmp.diag_info_id_i := f_x_to_zero(left.diag_info_id_i) or f_x_to_zero(right.diag_info_id_i);
+tmp.diag_nw_rw_i := f_x_to_zero(left.diag_nw_rw_i) or f_x_to_zero(right.diag_nw_rw_i);
+tmp.diag_nw_ro_i := f_x_to_zero(left.diag_nw_ro_i) or f_x_to_zero(right.diag_nw_ro_i);
+tmp.diag_cr_adr_i := f_x_to_zero(left.diag_cr_adr_i) or f_x_to_zero(right.diag_cr_adr_i);
+tmp.diag_dat_i := f_x_to_zero(left.diag_dat_i) or f_x_to_zero(right.diag_dat_i);
+tmp.wdiag_ctrl_data_snapshot_i := f_x_to_zero(left.wdiag_ctrl_data_snapshot_i) or f_x_to_zero(right.wdiag_ctrl_data_snapshot_i);
+return tmp;
+end function;
+end package body;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_syscon_wb.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_syscon_wb.vhd
new file mode 100644
index 000000000..82bfb0e66
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrc_syscon_wb.vhd
@@ -0,0 +1,975 @@
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Core System Controller
+---------------------------------------------------------------------------------------
+-- File           : wrc_syscon_wb.vhd
+-- Author         : auto-generated by wbgen2 from wrc_syscon_wb.wb
+-- Created        : Mon Nov 27 13:37:56 2017
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.sysc_wbgen2_pkg.all;
+
+
+entity wrc_syscon_wb is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(4 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    regs_i                                   : in     t_sysc_in_registers;
+    regs_o                                   : out    t_sysc_out_registers
+  );
+end wrc_syscon_wb;
+
+architecture syn of wrc_syscon_wb is
+
+signal sysc_rstr_rst_int                        : std_logic      ;
+signal sysc_gpsr_led_stat_dly0                  : std_logic      ;
+signal sysc_gpsr_led_stat_int                   : std_logic      ;
+signal sysc_gpsr_led_link_dly0                  : std_logic      ;
+signal sysc_gpsr_led_link_int                   : std_logic      ;
+signal sysc_gpsr_net_rst_dly0                   : std_logic      ;
+signal sysc_gpsr_net_rst_int                    : std_logic      ;
+signal sysc_gpcr_led_stat_dly0                  : std_logic      ;
+signal sysc_gpcr_led_stat_int                   : std_logic      ;
+signal sysc_gpcr_led_link_dly0                  : std_logic      ;
+signal sysc_gpcr_led_link_int                   : std_logic      ;
+signal sysc_gpcr_fmc_scl_dly0                   : std_logic      ;
+signal sysc_gpcr_fmc_scl_int                    : std_logic      ;
+signal sysc_gpcr_fmc_sda_dly0                   : std_logic      ;
+signal sysc_gpcr_fmc_sda_int                    : std_logic      ;
+signal sysc_gpcr_sfp_scl_dly0                   : std_logic      ;
+signal sysc_gpcr_sfp_scl_int                    : std_logic      ;
+signal sysc_gpcr_sfp_sda_dly0                   : std_logic      ;
+signal sysc_gpcr_sfp_sda_int                    : std_logic      ;
+signal sysc_gpcr_spi_sclk_dly0                  : std_logic      ;
+signal sysc_gpcr_spi_sclk_int                   : std_logic      ;
+signal sysc_gpcr_spi_cs_dly0                    : std_logic      ;
+signal sysc_gpcr_spi_cs_int                     : std_logic      ;
+signal sysc_gpcr_spi_mosi_dly0                  : std_logic      ;
+signal sysc_gpcr_spi_mosi_int                   : std_logic      ;
+signal sysc_tcr_enable_int                      : std_logic      ;
+signal sysc_diag_cr_rw_int                      : std_logic      ;
+signal sysc_wdiag_ctrl_data_valid_int           : std_logic      ;
+signal sysc_wdiag_sstat_wr_mode_int             : std_logic      ;
+signal sysc_wdiag_sstat_servostate_int          : std_logic_vector(3 downto 0);
+signal sysc_wdiag_pstat_link_int                : std_logic      ;
+signal sysc_wdiag_pstat_locked_int              : std_logic      ;
+signal sysc_wdiag_ptpstat_ptpstate_int          : std_logic_vector(7 downto 0);
+signal sysc_wdiag_astat_aux_int                 : std_logic_vector(7 downto 0);
+signal sysc_wdiag_txfcnt_int                    : std_logic_vector(31 downto 0);
+signal sysc_wdiag_rxfcnt_int                    : std_logic_vector(31 downto 0);
+signal sysc_wdiag_sec_msb_int                   : std_logic_vector(31 downto 0);
+signal sysc_wdiag_sec_lsb_int                   : std_logic_vector(31 downto 0);
+signal sysc_wdiag_ns_int                        : std_logic_vector(31 downto 0);
+signal sysc_wdiag_mu_msb_int                    : std_logic_vector(31 downto 0);
+signal sysc_wdiag_mu_lsb_int                    : std_logic_vector(31 downto 0);
+signal sysc_wdiag_dms_msb_int                   : std_logic_vector(31 downto 0);
+signal sysc_wdiag_dms_lsb_int                   : std_logic_vector(31 downto 0);
+signal sysc_wdiag_asym_int                      : std_logic_vector(31 downto 0);
+signal sysc_wdiag_cko_int                       : std_logic_vector(31 downto 0);
+signal sysc_wdiag_setp_int                      : std_logic_vector(31 downto 0);
+signal sysc_wdiag_ucnt_int                      : std_logic_vector(31 downto 0);
+signal sysc_wdiag_temp_int                      : std_logic_vector(31 downto 0);
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal rwaddr_reg                               : std_logic_vector(4 downto 0);
+signal ack_in_progress                          : std_logic      ;
+
+begin
+-- Some internal signals assignments
+  wrdata_reg <= wb_dat_i;
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      regs_o.rstr_trig_wr_o <= '0';
+      sysc_rstr_rst_int <= '0';
+      sysc_gpsr_led_stat_int <= '0';
+      sysc_gpsr_led_link_int <= '0';
+      regs_o.gpsr_fmc_scl_load_o <= '0';
+      regs_o.gpsr_fmc_sda_load_o <= '0';
+      sysc_gpsr_net_rst_int <= '0';
+      regs_o.gpsr_sfp_scl_load_o <= '0';
+      regs_o.gpsr_sfp_sda_load_o <= '0';
+      regs_o.gpsr_spi_sclk_load_o <= '0';
+      regs_o.gpsr_spi_ncs_load_o <= '0';
+      regs_o.gpsr_spi_mosi_load_o <= '0';
+      sysc_gpcr_led_stat_int <= '0';
+      sysc_gpcr_led_link_int <= '0';
+      sysc_gpcr_fmc_scl_int <= '0';
+      sysc_gpcr_fmc_sda_int <= '0';
+      sysc_gpcr_sfp_scl_int <= '0';
+      sysc_gpcr_sfp_sda_int <= '0';
+      sysc_gpcr_spi_sclk_int <= '0';
+      sysc_gpcr_spi_cs_int <= '0';
+      sysc_gpcr_spi_mosi_int <= '0';
+      sysc_tcr_enable_int <= '0';
+      regs_o.diag_cr_adr_load_o <= '0';
+      sysc_diag_cr_rw_int <= '0';
+      regs_o.diag_dat_load_o <= '0';
+      sysc_wdiag_ctrl_data_valid_int <= '0';
+      sysc_wdiag_sstat_wr_mode_int <= '0';
+      sysc_wdiag_sstat_servostate_int <= "0000";
+      sysc_wdiag_pstat_link_int <= '0';
+      sysc_wdiag_pstat_locked_int <= '0';
+      sysc_wdiag_ptpstat_ptpstate_int <= "00000000";
+      sysc_wdiag_astat_aux_int <= "00000000";
+      sysc_wdiag_txfcnt_int <= "00000000000000000000000000000000";
+      sysc_wdiag_rxfcnt_int <= "00000000000000000000000000000000";
+      sysc_wdiag_sec_msb_int <= "00000000000000000000000000000000";
+      sysc_wdiag_sec_lsb_int <= "00000000000000000000000000000000";
+      sysc_wdiag_ns_int <= "00000000000000000000000000000000";
+      sysc_wdiag_mu_msb_int <= "00000000000000000000000000000000";
+      sysc_wdiag_mu_lsb_int <= "00000000000000000000000000000000";
+      sysc_wdiag_dms_msb_int <= "00000000000000000000000000000000";
+      sysc_wdiag_dms_lsb_int <= "00000000000000000000000000000000";
+      sysc_wdiag_asym_int <= "00000000000000000000000000000000";
+      sysc_wdiag_cko_int <= "00000000000000000000000000000000";
+      sysc_wdiag_setp_int <= "00000000000000000000000000000000";
+      sysc_wdiag_ucnt_int <= "00000000000000000000000000000000";
+      sysc_wdiag_temp_int <= "00000000000000000000000000000000";
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          regs_o.rstr_trig_wr_o <= '0';
+          sysc_gpsr_led_stat_int <= '0';
+          sysc_gpsr_led_link_int <= '0';
+          regs_o.gpsr_fmc_scl_load_o <= '0';
+          regs_o.gpsr_fmc_sda_load_o <= '0';
+          sysc_gpsr_net_rst_int <= '0';
+          regs_o.gpsr_sfp_scl_load_o <= '0';
+          regs_o.gpsr_sfp_sda_load_o <= '0';
+          regs_o.gpsr_spi_sclk_load_o <= '0';
+          regs_o.gpsr_spi_ncs_load_o <= '0';
+          regs_o.gpsr_spi_mosi_load_o <= '0';
+          sysc_gpcr_led_stat_int <= '0';
+          sysc_gpcr_led_link_int <= '0';
+          sysc_gpcr_fmc_scl_int <= '0';
+          sysc_gpcr_fmc_sda_int <= '0';
+          sysc_gpcr_sfp_scl_int <= '0';
+          sysc_gpcr_sfp_sda_int <= '0';
+          sysc_gpcr_spi_sclk_int <= '0';
+          sysc_gpcr_spi_cs_int <= '0';
+          sysc_gpcr_spi_mosi_int <= '0';
+          regs_o.diag_cr_adr_load_o <= '0';
+          regs_o.diag_dat_load_o <= '0';
+          ack_in_progress <= '0';
+        else
+          regs_o.rstr_trig_wr_o <= '0';
+          regs_o.gpsr_fmc_scl_load_o <= '0';
+          regs_o.gpsr_fmc_sda_load_o <= '0';
+          regs_o.gpsr_sfp_scl_load_o <= '0';
+          regs_o.gpsr_sfp_sda_load_o <= '0';
+          regs_o.gpsr_spi_sclk_load_o <= '0';
+          regs_o.gpsr_spi_ncs_load_o <= '0';
+          regs_o.gpsr_spi_mosi_load_o <= '0';
+          regs_o.diag_cr_adr_load_o <= '0';
+          regs_o.diag_dat_load_o <= '0';
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(4 downto 0) is
+          when "00000" => 
+            if (wb_we_i = '1') then
+              regs_o.rstr_trig_wr_o <= '1';
+              sysc_rstr_rst_int <= wrdata_reg(28);
+            end if;
+            rddata_reg(28) <= sysc_rstr_rst_int;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00001" => 
+            if (wb_we_i = '1') then
+              sysc_gpsr_led_stat_int <= wrdata_reg(0);
+              sysc_gpsr_led_link_int <= wrdata_reg(1);
+              regs_o.gpsr_fmc_scl_load_o <= '1';
+              regs_o.gpsr_fmc_sda_load_o <= '1';
+              sysc_gpsr_net_rst_int <= wrdata_reg(4);
+              regs_o.gpsr_sfp_scl_load_o <= '1';
+              regs_o.gpsr_sfp_sda_load_o <= '1';
+              regs_o.gpsr_spi_sclk_load_o <= '1';
+              regs_o.gpsr_spi_ncs_load_o <= '1';
+              regs_o.gpsr_spi_mosi_load_o <= '1';
+            end if;
+            rddata_reg(0) <= '0';
+            rddata_reg(1) <= '0';
+            rddata_reg(2) <= regs_i.gpsr_fmc_scl_i;
+            rddata_reg(3) <= regs_i.gpsr_fmc_sda_i;
+            rddata_reg(4) <= '0';
+            rddata_reg(5) <= regs_i.gpsr_btn1_i;
+            rddata_reg(6) <= regs_i.gpsr_btn2_i;
+            rddata_reg(7) <= regs_i.gpsr_sfp_det_i;
+            rddata_reg(8) <= regs_i.gpsr_sfp_scl_i;
+            rddata_reg(9) <= regs_i.gpsr_sfp_sda_i;
+            rddata_reg(10) <= regs_i.gpsr_spi_sclk_i;
+            rddata_reg(11) <= regs_i.gpsr_spi_ncs_i;
+            rddata_reg(12) <= regs_i.gpsr_spi_mosi_i;
+            rddata_reg(13) <= regs_i.gpsr_spi_miso_i;
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(2) <= '1';
+            ack_in_progress <= '1';
+          when "00010" => 
+            if (wb_we_i = '1') then
+              sysc_gpcr_led_stat_int <= wrdata_reg(0);
+              sysc_gpcr_led_link_int <= wrdata_reg(1);
+              sysc_gpcr_fmc_scl_int <= wrdata_reg(2);
+              sysc_gpcr_fmc_sda_int <= wrdata_reg(3);
+              sysc_gpcr_sfp_scl_int <= wrdata_reg(8);
+              sysc_gpcr_sfp_sda_int <= wrdata_reg(9);
+              sysc_gpcr_spi_sclk_int <= wrdata_reg(10);
+              sysc_gpcr_spi_cs_int <= wrdata_reg(11);
+              sysc_gpcr_spi_mosi_int <= wrdata_reg(12);
+            end if;
+            rddata_reg(0) <= '0';
+            rddata_reg(1) <= '0';
+            rddata_reg(2) <= '0';
+            rddata_reg(3) <= '0';
+            rddata_reg(8) <= '0';
+            rddata_reg(9) <= '0';
+            rddata_reg(10) <= '0';
+            rddata_reg(11) <= '0';
+            rddata_reg(12) <= '0';
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(2) <= '1';
+            ack_in_progress <= '1';
+          when "00011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(3 downto 0) <= regs_i.hwfr_memsize_i;
+            rddata_reg(9 downto 8) <= regs_i.hwfr_storage_type_i;
+            rddata_reg(31 downto 16) <= regs_i.hwfr_storage_sec_i;
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00100" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.hwir_name_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.sdbfs_baddr_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00110" => 
+            if (wb_we_i = '1') then
+              sysc_tcr_enable_int <= wrdata_reg(31);
+            end if;
+            rddata_reg(11 downto 0) <= regs_i.tcr_tdiv_i;
+            rddata_reg(31) <= sysc_tcr_enable_int;
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "00111" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.tvr_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01000" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(15 downto 0) <= regs_i.diag_info_ver_i;
+            rddata_reg(31 downto 16) <= regs_i.diag_info_id_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01001" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(15 downto 0) <= regs_i.diag_nw_rw_i;
+            rddata_reg(31 downto 16) <= regs_i.diag_nw_ro_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01010" => 
+            if (wb_we_i = '1') then
+              regs_o.diag_cr_adr_load_o <= '1';
+              sysc_diag_cr_rw_int <= wrdata_reg(31);
+            end if;
+            rddata_reg(15 downto 0) <= regs_i.diag_cr_adr_i;
+            rddata_reg(31) <= sysc_diag_cr_rw_int;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01011" => 
+            if (wb_we_i = '1') then
+              regs_o.diag_dat_load_o <= '1';
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.diag_dat_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01100" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_ctrl_data_valid_int <= wrdata_reg(0);
+            end if;
+            rddata_reg(0) <= sysc_wdiag_ctrl_data_valid_int;
+            rddata_reg(8) <= regs_i.wdiag_ctrl_data_snapshot_i;
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01101" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_sstat_wr_mode_int <= wrdata_reg(0);
+              sysc_wdiag_sstat_servostate_int <= wrdata_reg(11 downto 8);
+            end if;
+            rddata_reg(0) <= sysc_wdiag_sstat_wr_mode_int;
+            rddata_reg(11 downto 8) <= sysc_wdiag_sstat_servostate_int;
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01110" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_pstat_link_int <= wrdata_reg(0);
+              sysc_wdiag_pstat_locked_int <= wrdata_reg(1);
+            end if;
+            rddata_reg(0) <= sysc_wdiag_pstat_link_int;
+            rddata_reg(1) <= sysc_wdiag_pstat_locked_int;
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01111" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_ptpstat_ptpstate_int <= wrdata_reg(7 downto 0);
+            end if;
+            rddata_reg(7 downto 0) <= sysc_wdiag_ptpstat_ptpstate_int;
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10000" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_astat_aux_int <= wrdata_reg(7 downto 0);
+            end if;
+            rddata_reg(7 downto 0) <= sysc_wdiag_astat_aux_int;
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10001" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_txfcnt_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_txfcnt_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10010" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_rxfcnt_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_rxfcnt_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10011" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_sec_msb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_sec_msb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10100" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_sec_lsb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_sec_lsb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10101" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_ns_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_ns_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10110" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_mu_msb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_mu_msb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10111" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_mu_lsb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_mu_lsb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "11000" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_dms_msb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_dms_msb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "11001" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_dms_lsb_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_dms_lsb_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "11010" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_asym_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_asym_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "11011" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_cko_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_cko_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "11100" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_setp_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_setp_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "11101" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_ucnt_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_ucnt_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "11110" => 
+            if (wb_we_i = '1') then
+              sysc_wdiag_temp_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= sysc_wdiag_temp_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- Reset trigger
+-- pass-through field: Reset trigger in register: Syscon reset register
+  regs_o.rstr_trig_o <= wrdata_reg(27 downto 0);
+-- Reset line state value
+  regs_o.rstr_rst_o <= sysc_rstr_rst_int;
+-- Status LED
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpsr_led_stat_dly0 <= '0';
+      regs_o.gpsr_led_stat_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpsr_led_stat_dly0 <= sysc_gpsr_led_stat_int;
+      regs_o.gpsr_led_stat_o <= sysc_gpsr_led_stat_int and (not sysc_gpsr_led_stat_dly0);
+    end if;
+  end process;
+  
+  
+-- Link LED
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpsr_led_link_dly0 <= '0';
+      regs_o.gpsr_led_link_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpsr_led_link_dly0 <= sysc_gpsr_led_link_int;
+      regs_o.gpsr_led_link_o <= sysc_gpsr_led_link_int and (not sysc_gpsr_led_link_dly0);
+    end if;
+  end process;
+  
+  
+-- FMC I2C bitbanged SCL
+  regs_o.gpsr_fmc_scl_o <= wrdata_reg(2);
+-- FMC I2C bitbanged SDA
+  regs_o.gpsr_fmc_sda_o <= wrdata_reg(3);
+-- Network AP reset
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpsr_net_rst_dly0 <= '0';
+      regs_o.gpsr_net_rst_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpsr_net_rst_dly0 <= sysc_gpsr_net_rst_int;
+      regs_o.gpsr_net_rst_o <= sysc_gpsr_net_rst_int and (not sysc_gpsr_net_rst_dly0);
+    end if;
+  end process;
+  
+  
+-- SPEC Pushbutton 1 state
+-- SPEC Pushbutton 2 state
+-- SFP detect (MOD_DEF0 signal)
+-- SFP I2C bitbanged SCL
+  regs_o.gpsr_sfp_scl_o <= wrdata_reg(8);
+-- SFP I2C bitbanged SDA
+  regs_o.gpsr_sfp_sda_o <= wrdata_reg(9);
+-- SPI bitbanged SCLK
+  regs_o.gpsr_spi_sclk_o <= wrdata_reg(10);
+-- SPI bitbanged NCS
+  regs_o.gpsr_spi_ncs_o <= wrdata_reg(11);
+-- SPI bitbanged MOSI
+  regs_o.gpsr_spi_mosi_o <= wrdata_reg(12);
+-- SPI bitbanged MISO
+-- Status LED
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpcr_led_stat_dly0 <= '0';
+      regs_o.gpcr_led_stat_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpcr_led_stat_dly0 <= sysc_gpcr_led_stat_int;
+      regs_o.gpcr_led_stat_o <= sysc_gpcr_led_stat_int and (not sysc_gpcr_led_stat_dly0);
+    end if;
+  end process;
+  
+  
+-- Link LED
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpcr_led_link_dly0 <= '0';
+      regs_o.gpcr_led_link_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpcr_led_link_dly0 <= sysc_gpcr_led_link_int;
+      regs_o.gpcr_led_link_o <= sysc_gpcr_led_link_int and (not sysc_gpcr_led_link_dly0);
+    end if;
+  end process;
+  
+  
+-- FMC I2C bitbanged SCL
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpcr_fmc_scl_dly0 <= '0';
+      regs_o.gpcr_fmc_scl_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpcr_fmc_scl_dly0 <= sysc_gpcr_fmc_scl_int;
+      regs_o.gpcr_fmc_scl_o <= sysc_gpcr_fmc_scl_int and (not sysc_gpcr_fmc_scl_dly0);
+    end if;
+  end process;
+  
+  
+-- FMC I2C bitbanged SDA
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpcr_fmc_sda_dly0 <= '0';
+      regs_o.gpcr_fmc_sda_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpcr_fmc_sda_dly0 <= sysc_gpcr_fmc_sda_int;
+      regs_o.gpcr_fmc_sda_o <= sysc_gpcr_fmc_sda_int and (not sysc_gpcr_fmc_sda_dly0);
+    end if;
+  end process;
+  
+  
+-- SFP I2C bitbanged SCL
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpcr_sfp_scl_dly0 <= '0';
+      regs_o.gpcr_sfp_scl_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpcr_sfp_scl_dly0 <= sysc_gpcr_sfp_scl_int;
+      regs_o.gpcr_sfp_scl_o <= sysc_gpcr_sfp_scl_int and (not sysc_gpcr_sfp_scl_dly0);
+    end if;
+  end process;
+  
+  
+-- FMC I2C bitbanged SDA
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpcr_sfp_sda_dly0 <= '0';
+      regs_o.gpcr_sfp_sda_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpcr_sfp_sda_dly0 <= sysc_gpcr_sfp_sda_int;
+      regs_o.gpcr_sfp_sda_o <= sysc_gpcr_sfp_sda_int and (not sysc_gpcr_sfp_sda_dly0);
+    end if;
+  end process;
+  
+  
+-- SPI bitbanged SCLK
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpcr_spi_sclk_dly0 <= '0';
+      regs_o.gpcr_spi_sclk_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpcr_spi_sclk_dly0 <= sysc_gpcr_spi_sclk_int;
+      regs_o.gpcr_spi_sclk_o <= sysc_gpcr_spi_sclk_int and (not sysc_gpcr_spi_sclk_dly0);
+    end if;
+  end process;
+  
+  
+-- SPI bitbanged CS
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpcr_spi_cs_dly0 <= '0';
+      regs_o.gpcr_spi_cs_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpcr_spi_cs_dly0 <= sysc_gpcr_spi_cs_int;
+      regs_o.gpcr_spi_cs_o <= sysc_gpcr_spi_cs_int and (not sysc_gpcr_spi_cs_dly0);
+    end if;
+  end process;
+  
+  
+-- SPI bitbanged MOSI
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      sysc_gpcr_spi_mosi_dly0 <= '0';
+      regs_o.gpcr_spi_mosi_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+      sysc_gpcr_spi_mosi_dly0 <= sysc_gpcr_spi_mosi_int;
+      regs_o.gpcr_spi_mosi_o <= sysc_gpcr_spi_mosi_int and (not sysc_gpcr_spi_mosi_dly0);
+    end if;
+  end process;
+  
+  
+-- Memory size
+-- Storage type
+-- Storage sector size
+-- Board name
+-- Base address
+-- Timer Divider
+-- Timer Enable
+  regs_o.tcr_enable_o <= sysc_tcr_enable_int;
+-- Timer Counter Value
+-- Ver
+-- Id
+-- Read/write words
+-- Read-only words
+-- Address
+  regs_o.diag_cr_adr_o <= wrdata_reg(15 downto 0);
+-- R/W
+  regs_o.diag_cr_rw_o <= sysc_diag_cr_rw_int;
+-- Data
+  regs_o.diag_dat_o <= wrdata_reg(31 downto 0);
+-- WR DIAG data valid
+  regs_o.wdiag_ctrl_data_valid_o <= sysc_wdiag_ctrl_data_valid_int;
+-- WR DIAG data snapshot
+-- WR valid
+  regs_o.wdiag_sstat_wr_mode_o <= sysc_wdiag_sstat_wr_mode_int;
+-- Servo State
+  regs_o.wdiag_sstat_servostate_o <= sysc_wdiag_sstat_servostate_int;
+-- Link Status
+  regs_o.wdiag_pstat_link_o <= sysc_wdiag_pstat_link_int;
+-- PLL Locked
+  regs_o.wdiag_pstat_locked_o <= sysc_wdiag_pstat_locked_int;
+-- PTP State
+  regs_o.wdiag_ptpstat_ptpstate_o <= sysc_wdiag_ptpstat_ptpstate_int;
+-- AUX channel
+  regs_o.wdiag_astat_aux_o <= sysc_wdiag_astat_aux_int;
+-- Data
+  regs_o.wdiag_txfcnt_o <= sysc_wdiag_txfcnt_int;
+-- Data
+  regs_o.wdiag_rxfcnt_o <= sysc_wdiag_rxfcnt_int;
+-- Data
+  regs_o.wdiag_sec_msb_o <= sysc_wdiag_sec_msb_int;
+-- Data
+  regs_o.wdiag_sec_lsb_o <= sysc_wdiag_sec_lsb_int;
+-- Data
+  regs_o.wdiag_ns_o <= sysc_wdiag_ns_int;
+-- Data
+  regs_o.wdiag_mu_msb_o <= sysc_wdiag_mu_msb_int;
+-- Data
+  regs_o.wdiag_mu_lsb_o <= sysc_wdiag_mu_lsb_int;
+-- Data
+  regs_o.wdiag_dms_msb_o <= sysc_wdiag_dms_msb_int;
+-- Data
+  regs_o.wdiag_dms_lsb_o <= sysc_wdiag_dms_lsb_int;
+-- Data
+  regs_o.wdiag_asym_o <= sysc_wdiag_asym_int;
+-- Data
+  regs_o.wdiag_cko_o <= sysc_wdiag_cko_int;
+-- Data
+  regs_o.wdiag_setp_o <= sysc_wdiag_setp_int;
+-- Data
+  regs_o.wdiag_ucnt_o <= sysc_wdiag_ucnt_int;
+-- Data
+  regs_o.wdiag_temp_o <= sysc_wdiag_temp_int;
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrcore_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrcore_pkg.vhd
new file mode 100644
index 000000000..a16166cfe
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/wrcore_pkg.vhd
@@ -0,0 +1,769 @@
+-------------------------------------------------------------------------------
+-- Title      : WhiteRabbit PTP Core
+-- Project    : WhiteRabbit
+-------------------------------------------------------------------------------
+-- File       : wrcore_pkg.vhd
+-- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2011-05-11
+-- Last update: 2017-05-29
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 - 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.genram_pkg.all;
+use work.wishbone_pkg.all;
+use work.sysc_wbgen2_pkg.all;
+use work.wrc_diags_wbgen2_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.softpll_pkg.all;
+
+package wrcore_pkg is
+
+  function f_refclk_rate(pcs_16 : boolean) return integer;
+
+  type t_generic_word_array is array (natural range <>) of std_logic_vector(31 downto 0);
+
+  ----------------------------------------------------------------------------- 
+  --PPS generator
+  -----------------------------------------------------------------------------
+  constant c_xwr_pps_gen_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"de0d8ced",
+        version   => x"00000001",
+        date      => x"20120305",
+        name      => "WR-PPS-Generator   ")));
+
+  component xwr_pps_gen is
+    generic(
+      g_interface_mode       : t_wishbone_interface_mode;
+      g_address_granularity  : t_wishbone_address_granularity;
+      g_ref_clock_rate       : integer;
+      g_ext_clock_rate       : integer;
+      g_with_ext_clock_input : boolean
+      );
+    port (
+      clk_ref_i       : in  std_logic;
+      clk_sys_i       : in  std_logic;
+      rst_ref_n_i     : in  std_logic;
+      rst_sys_n_i     : in  std_logic;
+      slave_i         : in  t_wishbone_slave_in;
+      slave_o         : out t_wishbone_slave_out;
+      link_ok_i       : in  std_logic;
+      pps_in_i        : in  std_logic;
+      pps_csync_o     : out std_logic;
+      pps_out_o       : out std_logic;
+      pps_led_o       : out std_logic;
+      pps_valid_o     : out std_logic;
+      tm_utc_o        : out std_logic_vector(39 downto 0);
+      tm_cycles_o     : out std_logic_vector(27 downto 0);
+      tm_time_valid_o : out std_logic
+      );
+  end component;
+
+  -----------------------------------------------------------------------------
+  --Mini NIC
+  -----------------------------------------------------------------------------
+  constant c_xwr_mini_nic_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"ab28633a",
+        version   => x"00000001",
+        date      => x"20120305",
+        name      => "WR-Mini-NIC        ")));
+
+  component xwr_mini_nic
+    generic (
+      g_interface_mode       : t_wishbone_interface_mode;
+      g_address_granularity  : t_wishbone_address_granularity;
+      g_tx_fifo_size         : integer;
+      g_rx_fifo_size         : integer;
+      g_buffer_little_endian : boolean);
+    port (
+      clk_sys_i           : in  std_logic;
+      rst_n_i             : in  std_logic;
+      src_o               : out t_wrf_source_out;
+      src_i               : in  t_wrf_source_in;
+      snk_o               : out t_wrf_sink_out;
+      snk_i               : in  t_wrf_sink_in;
+      txtsu_port_id_i     : in  std_logic_vector(4 downto 0);
+      txtsu_frame_id_i    : in  std_logic_vector(16 - 1 downto 0);
+      txtsu_tsval_i       : in  std_logic_vector(28 + 4 - 1 downto 0);
+      txtsu_tsincorrect_i : in  std_logic;
+      txtsu_stb_i         : in  std_logic;
+      txtsu_ack_o         : out std_logic;
+      wb_i                : in  t_wishbone_slave_in;
+      wb_o                : out t_wishbone_slave_out);
+  end component;
+
+  -----------------------------------------------------------------------------
+  -- PERIPHERIALS
+  -----------------------------------------------------------------------------
+  component xwr_diags_wb is
+    generic(
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD
+    );
+    port (
+      rst_n_i   : in  std_logic;
+      clk_sys_i : in  std_logic;
+
+      slave_i   : in  t_wishbone_slave_in;
+      slave_o   : out t_wishbone_slave_out;
+
+      regs_i    : in  t_wrc_diags_in_registers;
+      regs_o    : out t_wrc_diags_out_registers
+    );
+  end component;
+
+  constant c_wrc_periph0_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"ff07fc47",
+        version   => x"00000001",
+        date      => x"20120305",
+        name      => "WR-Periph-Syscon   ")));
+
+  constant c_wrc_periph1_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"e2d13d04",
+        version   => x"00000001",
+        date      => x"20120305",
+        name      => "WR-Periph-UART     ")));
+
+  constant c_wrc_periph2_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"779c5443",
+        version   => x"00000001",
+        date      => x"20120305",
+        name      => "WR-Periph-1Wire    ")));
+
+
+  constant c_wrc_periph3_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"779c5445",
+        version   => x"00000001",
+        date      => x"20120615",
+        name      => "WR-Periph-AuxWB    ")));
+
+  constant c_wrc_periph4_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"779c5446",
+        version   => x"00000001",
+        date      => x"20170424",
+        name      => "WR-Periph-WRPC-DIAG")));
+
+  component wrc_periph is
+    generic(
+      g_board_name      : string  := "NA  ";
+      g_flash_secsz_kb    : integer := 64;
+      g_flash_sdbfs_baddr : integer := 16#2e0000#;
+      g_phys_uart       : boolean := true;
+      g_virtual_uart    : boolean := false;
+      g_cntr_period     : integer := 62500;
+      g_mem_words       : integer := 16384;
+      g_vuart_fifo_size : integer := 1024;
+      g_diag_id         : integer := 0;
+      g_diag_ver        : integer := 0;
+      g_diag_ro_size    : integer := 0;
+      g_diag_rw_size    : integer := 0
+      );
+    port(
+      clk_sys_i   : in  std_logic;
+      rst_n_i     : in  std_logic;
+      rst_net_n_o : out std_logic;
+      rst_wrc_n_o : out std_logic;
+      led_red_o   : out std_logic;
+      led_green_o : out std_logic;
+      scl_o       : out std_logic;
+      scl_i       : in  std_logic;
+      sda_o       : out std_logic;
+      sda_i       : in  std_logic;
+      sfp_scl_o   : out std_logic;
+      sfp_scl_i   : in  std_logic;
+      sfp_sda_o   : out std_logic;
+      sfp_sda_i   : in  std_logic;
+      sfp_det_i   : in  std_logic;
+      memsize_i   : in  std_logic_vector(3 downto 0);
+      btn1_i      : in  std_logic;
+      btn2_i      : in  std_logic;
+      spi_sclk_o  : out std_logic;
+      spi_ncs_o   : out std_logic;
+      spi_mosi_o  : out std_logic;
+      spi_miso_i  : in  std_logic;
+      slave_i     : in  t_wishbone_slave_in_array(0 to 3);
+      slave_o     : out t_wishbone_slave_out_array(0 to 3);
+      uart_rxd_i  : in  std_logic;
+      uart_txd_o  : out std_logic;
+      owr_pwren_o : out std_logic_vector(1 downto 0);
+      owr_en_o    : out std_logic_vector(1 downto 0);
+      owr_i       : in  std_logic_vector(1 downto 0);
+      diag_array_in  : in  t_generic_word_array(g_diag_ro_size-1 downto 0);
+      diag_array_out : out t_generic_word_array(g_diag_rw_size-1 downto 0)
+      );
+  end component;
+
+  -----------------------------------------------------------------------------
+  -- Soft-PLL
+  -----------------------------------------------------------------------------
+  constant c_xwr_softpll_ng_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"65158dc0",
+        version   => x"00000002",
+        date      => x"20120305",
+        name      => "WR-Soft-PLL        ")));
+
+  component xwr_softpll_ng
+    generic (
+      g_tag_bits             : integer;
+      g_num_ref_inputs       : integer;
+      g_num_outputs          : integer;
+      g_with_debug_fifo      : boolean;
+      g_with_ext_clock_input : boolean;
+      g_reverse_dmtds        : boolean;
+      g_divide_input_by_2    : boolean;
+      g_ref_clock_rate       : integer;
+      g_ext_clock_rate       : integer;
+      g_interface_mode       : t_wishbone_interface_mode;
+      g_address_granularity  : t_wishbone_address_granularity);
+    port (
+      clk_sys_i       : in  std_logic;
+      rst_sys_n_i     : in  std_logic;
+      rst_ref_n_i     : in  std_logic;
+      rst_ext_n_i     : in  std_logic;
+      rst_dmtd_n_i    : in  std_logic;
+      clk_ref_i       : in  std_logic_vector(g_num_ref_inputs-1 downto 0);
+      clk_fb_i        : in  std_logic_vector(g_num_outputs-1 downto 0);
+      clk_dmtd_i      : in  std_logic;
+      clk_ext_i       : in  std_logic;
+      clk_ext_mul_i   : in  std_logic;
+      clk_ext_mul_locked_i : in std_logic;
+      clk_ext_stopped_i    : in std_logic;
+      clk_ext_rst_o        : out std_logic;
+      pps_csync_p1_i  : in  std_logic;
+      pps_ext_a_i     : in  std_logic;
+      dac_dmtd_data_o : out std_logic_vector(15 downto 0);
+      dac_dmtd_load_o : out std_logic;
+      dac_out_data_o  : out std_logic_vector(15 downto 0);
+      dac_out_sel_o   : out std_logic_vector(3 downto 0);
+      dac_out_load_o  : out std_logic;
+      out_enable_i    : in  std_logic_vector(g_num_outputs-1 downto 0);
+      out_locked_o    : out std_logic_vector(g_num_outputs-1 downto 0);
+      slave_i         : in  t_wishbone_slave_in;
+      slave_o         : out t_wishbone_slave_out;
+      debug_o         : out std_logic_vector(5 downto 0);
+      dbg_fifo_irq_o  : out std_logic);
+  end component;
+  
+  constant cc_unused_master_in : t_wishbone_master_in :=
+    ('1', '0', '0', '0', '0', cc_dummy_data);
+
+  -----------------------------------------------------------------------------
+  -- Public WR component definitions
+  -----------------------------------------------------------------------------
+  component xwr_core is
+    generic(
+      g_simulation                : integer                        := 0;
+      g_board_name                : string                         := "NA  ";
+      g_flash_secsz_kb            : integer                        := 256;        -- default for SVEC (M25P128)
+      g_flash_sdbfs_baddr         : integer                        := 16#600000#; -- default for SVEC (M25P128)
+      g_phys_uart                 : boolean                        := true;
+      g_virtual_uart              : boolean                        := true;
+      g_with_external_clock_input : boolean                        := true;
+      g_aux_clks                  : integer                        := 0;
+      g_ep_rxbuf_size             : integer                        := 1024;
+      g_tx_runt_padding           : boolean                        := true;
+      g_dpram_initf               : string                         := "default";
+      g_dpram_size                : integer                        := 131072/4;  --in 32-bit words
+      g_interface_mode            : t_wishbone_interface_mode      := PIPELINED;
+      g_address_granularity       : t_wishbone_address_granularity := BYTE;
+      g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
+      g_softpll_enable_debugger   : boolean                        := false;
+      g_vuart_fifo_size           : integer                        := 1024;
+      g_pcs_16bit                 : boolean                        := false;
+      g_records_for_phy           : boolean                        := false;
+      g_diag_id                   : integer                        := 0;
+      g_diag_ver                  : integer                        := 0;
+      g_diag_ro_size              : integer                        := 0;
+      g_diag_rw_size              : integer                        := 0);
+    port(
+      clk_sys_i            : in std_logic;
+      clk_dmtd_i           : in std_logic := '0';
+      clk_ref_i            : in std_logic;
+      clk_aux_i            : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+      clk_ext_mul_i        : in std_logic := '0';
+      clk_ext_mul_locked_i : in std_logic := '1';
+      clk_ext_stopped_i    : in std_logic := '0';
+      clk_ext_rst_o        : out std_logic;
+      clk_ext_i            : in std_logic := '0';
+      pps_ext_i            : in std_logic := '0';
+      rst_n_i              : in std_logic;
+
+      dac_hpll_load_p1_o   : out std_logic;
+      dac_hpll_data_o      : out std_logic_vector(15 downto 0);
+      dac_dpll_load_p1_o   : out std_logic;
+      dac_dpll_data_o      : out std_logic_vector(15 downto 0);
+      -----------------------------------------
+      -- PHY I/f
+      -----------------------------------------
+      phy_ref_clk_i        : in  std_logic                    := '0';
+      phy_tx_data_o        : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+      phy_tx_k_o           : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+      phy_tx_disparity_i   : in  std_logic                    := '0';
+      phy_tx_enc_err_i     : in  std_logic                    := '0';
+      phy_rx_data_i        : in  std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy_rx_rbclk_i       : in  std_logic                    := '0';
+      phy_rx_k_i           : in  std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy_rx_enc_err_i     : in  std_logic                    := '0';
+      phy_rx_bitslide_i    : in  std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy_rst_o            : out std_logic;
+      phy_rdy_i            : in  std_logic := '1';
+      phy_loopen_o         : out std_logic;
+      phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+      phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+      phy_sfp_tx_fault_i   : in std_logic := '0';
+      phy_sfp_los_i        : in std_logic := '0';
+      phy_sfp_tx_disable_o : out std_logic;
+      -----------------------------------------
+      -- PHY I/f - record-based
+      -- selection done with g_records_for_phy
+      -----------------------------------------
+      phy8_o  : out t_phy_8bits_from_wrc;
+      phy8_i  : in  t_phy_8bits_to_wrc  := c_dummy_phy8_to_wrc;
+      phy16_o : out t_phy_16bits_from_wrc;
+      phy16_i : in  t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
+
+      led_act_o  : out std_logic;
+      led_link_o : out std_logic;
+      scl_o      : out std_logic;
+      scl_i      : in  std_logic := 'H';
+      sda_o      : out std_logic;
+      sda_i      : in  std_logic := 'H';
+      sfp_scl_o  : out std_logic;
+      sfp_scl_i  : in  std_logic := 'H';
+      sfp_sda_o  : out std_logic;
+      sfp_sda_i  : in  std_logic := 'H';
+      sfp_det_i  : in  std_logic := '1';
+      btn1_i     : in  std_logic := 'H';
+      btn2_i     : in  std_logic := 'H';
+      spi_sclk_o : out std_logic;
+      spi_ncs_o  : out std_logic;
+      spi_mosi_o : out std_logic;
+      spi_miso_i : in  std_logic := '0';
+
+      uart_rxd_i : in  std_logic := 'H';
+      uart_txd_o : out std_logic;
+
+      owr_pwren_o : out std_logic_vector(1 downto 0);
+      owr_en_o    : out std_logic_vector(1 downto 0);
+      owr_i       : in  std_logic_vector(1 downto 0) := "HH";
+
+      slave_i : in  t_wishbone_slave_in := cc_dummy_slave_in;
+      slave_o : out t_wishbone_slave_out;
+
+      aux_master_o : out t_wishbone_master_out;
+      aux_master_i : in  t_wishbone_master_in := cc_unused_master_in;
+
+      wrf_src_o : out t_wrf_source_out;
+      wrf_src_i : in  t_wrf_source_in := c_dummy_src_in;
+      wrf_snk_o : out t_wrf_sink_out;
+      wrf_snk_i : in  t_wrf_sink_in   := c_dummy_snk_in;
+
+      timestamps_o     : out t_txtsu_timestamp;
+      timestamps_ack_i : in  std_logic := '1';
+
+      abscal_txts_o       : out std_logic;
+      abscal_rxts_o       : out std_logic;
+
+      fc_tx_pause_req_i   : in  std_logic                     := '0';
+      fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+      fc_tx_pause_ready_o : out std_logic;
+
+      tm_link_up_o         : out std_logic;
+      tm_dac_value_o       : out std_logic_vector(23 downto 0);
+      tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+      tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+      tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+      tm_time_valid_o      : out std_logic;
+      tm_tai_o             : out std_logic_vector(39 downto 0);
+      tm_cycles_o          : out std_logic_vector(27 downto 0);
+      pps_csync_o          : out std_logic;
+      pps_p_o              : out std_logic;
+      pps_led_o            : out std_logic;
+
+      rst_aux_n_o : out std_logic;
+
+      link_ok_o : out std_logic;
+
+      aux_diag_i : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others=>(others=>'0'));
+      aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0)
+      );
+  end component;
+
+  component wr_core is
+    generic(
+      --if set to 1, then blocks in PCS use smaller calibration counter to speed 
+      --up simulation
+      g_simulation                : integer                        := 0;
+      g_with_external_clock_input : boolean                        := true;
+      --
+      g_board_name                : string                         := "NA  ";
+      g_flash_secsz_kb            : integer                        := 256;        -- default for SVEC (M25P128)
+      g_flash_sdbfs_baddr         : integer                        := 16#600000#; -- default for SVEC (M25P128)
+      g_phys_uart                 : boolean                        := true;
+      g_virtual_uart              : boolean                        := true;
+      g_aux_clks                  : integer                        := 0;
+      g_rx_buffer_size            : integer                        := 1024;
+      g_tx_runt_padding           : boolean                        := true;
+      g_dpram_initf               : string                         := "default";
+      g_dpram_size                : integer                        := 131072/4;  --in 32-bit words
+      g_interface_mode            : t_wishbone_interface_mode      := PIPELINED;
+      g_address_granularity       : t_wishbone_address_granularity := BYTE;
+      g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
+      g_softpll_enable_debugger   : boolean                        := false;
+      g_vuart_fifo_size           : integer                        := 1024;
+      g_pcs_16bit                 : boolean                        := false;
+      g_records_for_phy           : boolean                        := false;
+      g_diag_id                   : integer                        := 0;
+      g_diag_ver                  : integer                        := 0;
+      g_diag_ro_size              : integer                        := 0;
+      g_diag_rw_size              : integer                        := 0);
+    port(
+      ---------------------------------------------------------------------------
+      -- Clocks/resets
+      ---------------------------------------------------------------------------
+
+      -- system reference clock (any frequency <= f(clk_ref_i))
+      clk_sys_i : in std_logic;
+
+      -- DDMTD offset clock (125.x MHz)
+      clk_dmtd_i : in std_logic := '0';
+
+      -- Timing reference (125 MHz)
+      clk_ref_i : in std_logic;
+
+      -- Aux clocks (i.e. the FMC clock), which can be disciplined by the WR Core
+      clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+
+      -- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
+      clk_ext_i : in std_logic := '0';
+
+      clk_ext_mul_i : in std_logic := '0';
+      clk_ext_mul_locked_i : in std_logic := '1';
+      clk_ext_stopped_i    : in std_logic := '0';
+      clk_ext_rst_o        : out std_logic;
+
+      -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
+      pps_ext_i : in std_logic := '0';
+
+      rst_n_i : in std_logic;
+
+      -----------------------------------------
+      --Timing system
+      -----------------------------------------
+      dac_hpll_load_p1_o : out std_logic;
+      dac_hpll_data_o    : out std_logic_vector(15 downto 0);
+
+      dac_dpll_load_p1_o : out std_logic;
+      dac_dpll_data_o    : out std_logic_vector(15 downto 0);
+
+      -----------------------------------------
+      -- PHY I/f
+      -----------------------------------------
+      phy_ref_clk_i : in std_logic;
+
+      phy_tx_data_o      : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+      phy_tx_k_o         : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+      phy_tx_disparity_i : in  std_logic := '0';
+      phy_tx_enc_err_i   : in  std_logic := '0';
+
+      phy_rx_data_i     : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy_rx_rbclk_i    : in std_logic                    := '0';
+      phy_rx_k_i        : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0):= (others=>'0');
+      phy_rx_enc_err_i  : in std_logic                    := '0';
+      phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+
+      phy_rst_o    : out std_logic;
+      phy_rdy_i    : in  std_logic := '1';
+      phy_loopen_o         : out std_logic;
+      phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+      phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+      phy_sfp_tx_fault_i   : in std_logic := '0';
+      phy_sfp_los_i        : in std_logic := '0';
+      phy_sfp_tx_disable_o : out std_logic;
+      -----------------------------------------
+      -- PHY I/f - record-based
+      -- selection done with g_records_for_phy
+      -----------------------------------------
+      phy8_o  : out t_phy_8bits_from_wrc;
+      phy8_i  : in  t_phy_8bits_to_wrc  := c_dummy_phy8_to_wrc;
+      phy16_o : out t_phy_16bits_from_wrc;
+      phy16_i : in  t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
+
+      -----------------------------------------
+      --GPIO
+      -----------------------------------------
+      led_act_o  : out std_logic;
+      led_link_o : out std_logic;
+      scl_o      : out std_logic;
+      scl_i      : in  std_logic := '1';
+      sda_o      : out std_logic;
+      sda_i      : in  std_logic := '1';
+      sfp_scl_o  : out std_logic;
+      sfp_scl_i  : in  std_logic := '1';
+      sfp_sda_o  : out std_logic;
+      sfp_sda_i  : in  std_logic := '1';
+      sfp_det_i  : in  std_logic := '1';
+      btn1_i     : in  std_logic := '1';
+      btn2_i     : in  std_logic := '1';
+      spi_sclk_o : out std_logic;
+      spi_ncs_o  : out std_logic;
+      spi_mosi_o : out std_logic;
+      spi_miso_i : in  std_logic := '0';
+
+      -----------------------------------------
+      --UART
+      -----------------------------------------
+      uart_rxd_i : in  std_logic := '0';
+      uart_txd_o : out std_logic;
+
+      -----------------------------------------
+      -- 1-wire
+      -----------------------------------------
+      owr_pwren_o : out std_logic_vector(1 downto 0);
+      owr_en_o    : out std_logic_vector(1 downto 0);
+      owr_i       : in  std_logic_vector(1 downto 0) := (others => '1');
+
+      -----------------------------------------
+      --External WB interface
+      -----------------------------------------
+      wb_adr_i   : in  std_logic_vector(c_wishbone_address_width-1 downto 0)   := (others => '0');
+      wb_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0)      := (others => '0');
+      wb_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_sel_i   : in  std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
+      wb_we_i    : in  std_logic                                               := '0';
+      wb_cyc_i   : in  std_logic                                               := '0';
+      wb_stb_i   : in  std_logic                                               := '0';
+      wb_ack_o   : out std_logic;
+      wb_err_o   : out std_logic;
+      wb_rty_o   : out std_logic;
+      wb_stall_o : out std_logic;
+
+      -----------------------------------------
+      -- Auxillary WB master
+      -----------------------------------------
+      aux_adr_o   : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+      aux_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      aux_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
+      aux_sel_o   : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
+      aux_we_o    : out std_logic;
+      aux_cyc_o   : out std_logic;
+      aux_stb_o   : out std_logic;
+      aux_ack_i   : in  std_logic                                          := '1';
+      aux_stall_i : in  std_logic                                          := '0';
+
+      -----------------------------------------
+      -- External Fabric I/F
+      -----------------------------------------
+      ext_snk_adr_i   : in  std_logic_vector(1 downto 0)  := "00";
+      ext_snk_dat_i   : in  std_logic_vector(15 downto 0) := x"0000";
+      ext_snk_sel_i   : in  std_logic_vector(1 downto 0)  := "00";
+      ext_snk_cyc_i   : in  std_logic                     := '0';
+      ext_snk_we_i    : in  std_logic                     := '0';
+      ext_snk_stb_i   : in  std_logic                     := '0';
+      ext_snk_ack_o   : out std_logic;
+      ext_snk_err_o   : out std_logic;
+      ext_snk_stall_o : out std_logic;
+
+      ext_src_adr_o   : out std_logic_vector(1 downto 0);
+      ext_src_dat_o   : out std_logic_vector(15 downto 0);
+      ext_src_sel_o   : out std_logic_vector(1 downto 0);
+      ext_src_cyc_o   : out std_logic;
+      ext_src_stb_o   : out std_logic;
+      ext_src_we_o    : out std_logic;
+      ext_src_ack_i   : in  std_logic := '1';
+      ext_src_err_i   : in  std_logic := '0';
+      ext_src_stall_i : in  std_logic := '0';
+
+      ------------------------------------------
+      -- External TX Timestamp I/F
+      ------------------------------------------
+      txtsu_port_id_o      : out std_logic_vector(4 downto 0);
+      txtsu_frame_id_o     : out std_logic_vector(15 downto 0);
+      txtsu_ts_value_o     : out std_logic_vector(31 downto 0);
+      txtsu_ts_incorrect_o : out std_logic;
+      txtsu_stb_o          : out std_logic;
+      txtsu_ack_i          : in  std_logic := '1';
+
+      -----------------------------------------
+      -- Timestamp helper signals, used for Absolute Calibration
+      -----------------------------------------
+      abscal_txts_o        : out std_logic;
+      abscal_rxts_o        : out std_logic;
+
+      -----------------------------------------
+      -- Pause Frame Control
+      -----------------------------------------
+      fc_tx_pause_req_i   : in  std_logic                     := '0';
+      fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+      fc_tx_pause_ready_o : out std_logic;
+
+      -----------------------------------------
+      -- Timecode/Servo Control
+      -----------------------------------------
+
+      tm_link_up_o         : out std_logic;
+
+      tm_dac_value_o       : out std_logic_vector(23 downto 0);
+      tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0) ;
+      tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+      tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0) ;
+
+      -- Timecode output
+      tm_time_valid_o      : out std_logic;
+      tm_tai_o             : out std_logic_vector(39 downto 0);
+      tm_cycles_o          : out std_logic_vector(27 downto 0);
+      -- 1PPS output
+      pps_csync_o          : out std_logic;
+      pps_p_o              : out std_logic;
+      pps_led_o            : out std_logic;
+
+      rst_aux_n_o : out std_logic;
+
+      link_ok_o : out std_logic;
+
+      -------------------------------------
+      -- DIAG to/from external modules
+      -------------------------------------
+      aux_diag_i : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others=>(others=>'0'));
+      aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0)
+      );
+  end component;
+
+  component spec_serial_dac_arb
+    generic(
+      g_invert_sclk    : boolean;
+      g_num_extra_bits : integer);        
+    port (
+      clk_i       : in  std_logic;
+      rst_n_i     : in  std_logic;
+      val1_i      : in  std_logic_vector(15 downto 0);
+      load1_i     : in  std_logic;
+      val2_i      : in  std_logic_vector(15 downto 0);
+      load2_i     : in  std_logic;
+      dac_cs_n_o  : out std_logic_vector(1 downto 0);
+      dac_clr_n_o : out std_logic;
+      dac_sclk_o  : out std_logic;
+      dac_din_o   : out std_logic);
+  end component;
+
+end wrcore_pkg;
+
+package body wrcore_pkg is
+
+  function f_refclk_rate(pcs_16 : boolean)
+    return integer is
+  begin
+    if (pcs_16) then
+      return 62500000;
+    else
+      return 125000000;
+    end if;
+  end function;
+
+end package body wrcore_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/xwr_core.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/xwr_core.vhd
new file mode 100644
index 000000000..25bcc92a1
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/xwr_core.vhd
@@ -0,0 +1,448 @@
+-------------------------------------------------------------------------------
+-- Title      : WhiteRabbit PTP Core
+-- Project    : WhiteRabbit
+-------------------------------------------------------------------------------
+-- File       : xwr_core.vhd
+-- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2011-02-02
+-- Last update: 2017-05-29
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- WR PTP Core is a HDL module implementing a complete gigabit Ethernet 
+-- interface (MAC + PCS + PHY) with integrated PTP slave ordinary clock 
+-- compatible with White Rabbit protocol. It performs subnanosecond clock 
+-- synchronization via WR protocol and also acts as an Ethernet "gateway", 
+-- providing access to TX/RX interfaces of the built-in WR MAC.
+--
+-- Starting from version 2.0 all modules are interconnected with pipelined
+-- wishbone interface (using wb crossbar and bus fanout). Separate pipelined
+-- wishbone bus is used for passing packets between Endpoint, Mini-NIC
+-- and External MAC interface.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 - 2017 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Memory map:
+--  0x00000000: I/D Memory
+--  0x00020000: Peripheral interconnect
+--      +0x000: Minic
+--      +0x100: Endpoint
+--      +0x200: Softpll
+--      +0x300: PPS gen
+--      +0x400: Syscon
+--      +0x500: UART
+--      +0x600: OneWire
+--      +0x700: Auxillary space (Etherbone config, etc)
+--      +0x800: WRPC diagnostics registers
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.wrcore_pkg.all;
+use work.genram_pkg.all;
+use work.wishbone_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.sysc_wbgen2_pkg.all;
+use work.softpll_pkg.all;
+
+
+entity xwr_core is
+  generic(
+    --if set to 1, then blocks in PCS use smaller calibration counter to speed 
+    --up simulation
+    g_simulation                : integer                        := 0;
+    g_with_external_clock_input : boolean                        := true;
+    --
+    g_board_name                : string                         := "NA  ";
+    g_flash_secsz_kb            : integer                        := 256;        -- default for SVEC (M25P128)
+    g_flash_sdbfs_baddr         : integer                        := 16#600000#; -- default for SVEC (M25P128)
+    g_phys_uart                 : boolean                        := true;
+    g_virtual_uart              : boolean                        := true;
+    g_aux_clks                  : integer                        := 0;
+    g_ep_rxbuf_size             : integer                        := 1024;
+    g_tx_runt_padding           : boolean                        := true;
+    g_dpram_initf               : string                         := "";
+    g_dpram_size                : integer                        := 131072/4;  --in 32-bit words
+    g_interface_mode            : t_wishbone_interface_mode      := PIPELINED;
+    g_address_granularity       : t_wishbone_address_granularity := BYTE;
+    g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
+    g_softpll_enable_debugger   : boolean                        := false;
+    g_vuart_fifo_size           : integer                        := 1024;
+    g_pcs_16bit                 : boolean                        := false;
+    g_records_for_phy           : boolean                        := false;
+    g_diag_id                   : integer                        := 0;
+    g_diag_ver                  : integer                        := 0;
+    g_diag_ro_size              : integer                        := 0;
+    g_diag_rw_size              : integer                        := 0);
+  port(
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+
+    -- system reference clock (any frequency <= f(clk_ref_i))
+    clk_sys_i : in std_logic;
+
+    -- DDMTD offset clock (125.x MHz)
+    clk_dmtd_i : in std_logic;
+
+    -- Timing reference (125 MHz)
+    clk_ref_i : in std_logic;
+
+    -- Aux clock (i.e. the FMC clock), which can be disciplined by the WR Core
+    clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+
+    -- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
+    clk_ext_i : in std_logic := '0';
+
+    clk_ext_mul_i : in std_logic := '0';
+    clk_ext_mul_locked_i : in std_logic := '1';
+    clk_ext_stopped_i    : in  std_logic := '0';
+    clk_ext_rst_o        : out std_logic;
+
+    -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
+    pps_ext_i : in std_logic := '0';
+
+    rst_n_i : in std_logic;
+
+    -----------------------------------------
+    --Timing system
+    -----------------------------------------
+    dac_hpll_load_p1_o : out std_logic;
+    dac_hpll_data_o    : out std_logic_vector(15 downto 0);
+
+    dac_dpll_load_p1_o : out std_logic;
+    dac_dpll_data_o    : out std_logic_vector(15 downto 0);
+
+    -----------------------------------------
+    -- PHY I/f
+    -----------------------------------------
+    phy_ref_clk_i : in std_logic;
+
+    phy_tx_data_o        : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    phy_tx_k_o           : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+    phy_tx_disparity_i   : in  std_logic;
+    phy_tx_enc_err_i     : in  std_logic;
+
+    phy_rx_data_i        : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    phy_rx_rbclk_i       : in std_logic;
+    phy_rx_k_i           : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+    phy_rx_enc_err_i     : in std_logic;
+    phy_rx_bitslide_i    : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
+
+    phy_rst_o            : out std_logic;
+    phy_rdy_i            : in  std_logic := '1';
+    phy_loopen_o         : out std_logic;
+    phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+    phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+    phy_sfp_tx_fault_i   : in std_logic := '0';
+    phy_sfp_los_i        : in std_logic := '0';
+    phy_sfp_tx_disable_o : out std_logic;
+    -----------------------------------------
+    -- PHY I/f - record-based
+    -- selection done with g_records_for_phy
+    -----------------------------------------
+    phy8_o               : out t_phy_8bits_from_wrc;
+    phy8_i               : in  t_phy_8bits_to_wrc  := c_dummy_phy8_to_wrc;
+    phy16_o              : out t_phy_16bits_from_wrc;
+    phy16_i              : in  t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
+   
+    -----------------------------------------
+    --GPIO
+    -----------------------------------------
+    led_act_o  : out std_logic;
+    led_link_o : out std_logic;
+    scl_o      : out std_logic;
+    scl_i      : in  std_logic := '1';
+    sda_o      : out std_logic;
+    sda_i      : in  std_logic := '1';
+    sfp_scl_o  : out std_logic;
+    sfp_scl_i  : in  std_logic := '1';
+    sfp_sda_o  : out std_logic;
+    sfp_sda_i  : in  std_logic := '1';
+    sfp_det_i  : in  std_logic;
+    btn1_i     : in  std_logic := '1';
+    btn2_i     : in  std_logic := '1';
+    spi_sclk_o : out std_logic;
+    spi_ncs_o  : out std_logic;
+    spi_mosi_o : out std_logic;
+    spi_miso_i : in  std_logic := '0';
+
+    -----------------------------------------
+    --UART
+    -----------------------------------------
+    uart_rxd_i : in  std_logic := '0';
+    uart_txd_o : out std_logic;
+
+    -----------------------------------------
+    -- 1-wire
+    -----------------------------------------
+    owr_pwren_o : out std_logic_vector(1 downto 0);
+    owr_en_o    : out std_logic_vector(1 downto 0);
+    owr_i       : in  std_logic_vector(1 downto 0) := (others => '1');
+
+    -----------------------------------------
+    --External WB interface
+    -----------------------------------------
+    slave_i : in  t_wishbone_slave_in := cc_dummy_slave_in;
+    slave_o : out t_wishbone_slave_out;
+
+    aux_master_o : out t_wishbone_master_out;
+    aux_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+
+    -----------------------------------------
+    -- External Fabric I/F
+    -----------------------------------------
+    wrf_src_o : out t_wrf_source_out;
+    wrf_src_i : in  t_wrf_source_in := c_dummy_src_in;
+    wrf_snk_o : out t_wrf_sink_out;
+    wrf_snk_i : in  t_wrf_sink_in   := c_dummy_snk_in;
+
+    -----------------------------------------
+    -- External Tx Timestamping I/F
+    -----------------------------------------
+    timestamps_o     : out t_txtsu_timestamp;
+    timestamps_ack_i : in  std_logic := '1';
+
+    -----------------------------------------
+    -- Timestamp helper signals, used for Absolute Calibration
+    -----------------------------------------
+    abscal_txts_o       : out std_logic;
+    abscal_rxts_o       : out std_logic;
+
+    -----------------------------------------
+    -- Pause Frame Control
+    -----------------------------------------
+    fc_tx_pause_req_i   : in  std_logic                     := '0';
+    fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+    fc_tx_pause_ready_o : out std_logic;
+
+    -----------------------------------------
+    -- Timecode/Servo Control
+    -----------------------------------------
+
+    tm_link_up_o         : out std_logic;
+    -- DAC Control
+    tm_dac_value_o       : out std_logic_vector(23 downto 0);
+    tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+    -- Aux clock lock enable
+    tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+    -- Aux clock locked flag
+    tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+    -- Timecode output
+    tm_time_valid_o      : out std_logic;
+    tm_tai_o             : out std_logic_vector(39 downto 0);
+    tm_cycles_o          : out std_logic_vector(27 downto 0);
+    -- 1PPS output
+    pps_csync_o          : out std_logic;
+    pps_p_o              : out std_logic;
+    pps_led_o            : out std_logic;
+
+    rst_aux_n_o : out std_logic;
+
+    aux_diag_i    : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others =>(others=>'0'));
+    aux_diag_o    : out t_generic_word_array(g_diag_rw_size-1 downto 0);
+
+    link_ok_o : out std_logic
+    );
+end xwr_core;
+
+architecture struct of xwr_core is
+begin
+
+  WRPC : wr_core
+    generic map(
+      g_simulation                => g_simulation,
+      g_board_name                => g_board_name,
+      g_flash_secsz_kb            => g_flash_secsz_kb,
+      g_flash_sdbfs_baddr         => g_flash_sdbfs_baddr,
+      g_phys_uart                 => g_phys_uart,
+      g_virtual_uart              => g_virtual_uart,
+      g_rx_buffer_size            => g_ep_rxbuf_size,
+      g_tx_runt_padding           => g_tx_runt_padding,
+      g_with_external_clock_input => g_with_external_clock_input,
+      g_aux_clks                  => g_aux_clks,
+      g_dpram_initf               => g_dpram_initf,
+      g_dpram_size                => g_dpram_size,
+      g_interface_mode            => g_interface_mode,
+      g_address_granularity       => g_address_granularity,
+      g_aux_sdb                   => g_aux_sdb,
+      g_softpll_enable_debugger   => g_softpll_enable_debugger,
+      g_vuart_fifo_size           => g_vuart_fifo_size,
+      g_pcs_16bit                 => g_pcs_16bit,
+      g_records_for_phy           => g_records_for_phy,
+      g_diag_id                   => g_diag_id,
+      g_diag_ver                  => g_diag_ver,
+      g_diag_ro_size              => g_diag_ro_size,
+      g_diag_rw_size              => g_diag_rw_size
+      )
+    port map(
+      clk_sys_i     => clk_sys_i,
+      clk_dmtd_i    => clk_dmtd_i,
+      clk_ref_i     => clk_ref_i,
+      clk_aux_i     => clk_aux_i,
+      clk_ext_i     => clk_ext_i,
+      clk_ext_mul_i => clk_ext_mul_i,
+      clk_ext_mul_locked_i  => clk_ext_mul_locked_i,
+      clk_ext_stopped_i => clk_ext_stopped_i,
+      clk_ext_rst_o     => clk_ext_rst_o,
+      pps_ext_i     => pps_ext_i,
+      rst_n_i       => rst_n_i,
+
+      dac_hpll_load_p1_o   => dac_hpll_load_p1_o,
+      dac_hpll_data_o      => dac_hpll_data_o,
+      dac_dpll_load_p1_o   => dac_dpll_load_p1_o,
+      dac_dpll_data_o      => dac_dpll_data_o,
+
+      phy_ref_clk_i        => phy_ref_clk_i,
+      phy_tx_data_o        => phy_tx_data_o,
+      phy_tx_k_o           => phy_tx_k_o,
+      phy_tx_disparity_i   => phy_tx_disparity_i,
+      phy_tx_enc_err_i     => phy_tx_enc_err_i,
+      phy_rx_data_i        => phy_rx_data_i,
+      phy_rx_rbclk_i       => phy_rx_rbclk_i,
+      phy_rx_k_i           => phy_rx_k_i,
+      phy_rx_enc_err_i     => phy_rx_enc_err_i,
+      phy_rx_bitslide_i    => phy_rx_bitslide_i,
+      phy_rst_o            => phy_rst_o,
+      phy_rdy_i            => phy_rdy_i,
+      phy_loopen_o         => phy_loopen_o,
+      phy_loopen_vec_o     => phy_loopen_vec_o,
+      phy_tx_prbs_sel_o    => phy_tx_prbs_sel_o,
+      phy_sfp_tx_fault_i   => phy_sfp_tx_fault_i,
+      phy_sfp_los_i        => phy_sfp_los_i,
+      phy_sfp_tx_disable_o => phy_sfp_tx_disable_o,
+
+      phy8_o     => phy8_o,
+      phy8_i     => phy8_i,
+      phy16_o    => phy16_o,
+      phy16_i    => phy16_i,
+
+      led_act_o  => led_act_o,
+      led_link_o => led_link_o,
+      scl_o      => scl_o,
+      scl_i      => scl_i,
+      sda_o      => sda_o,
+      sda_i      => sda_i,
+      sfp_scl_o  => sfp_scl_o,
+      sfp_scl_i  => sfp_scl_i,
+      sfp_sda_o  => sfp_sda_o,
+      sfp_sda_i  => sfp_sda_i,
+      sfp_det_i  => sfp_det_i,
+      btn1_i     => btn1_i,
+      btn2_i     => btn2_i,
+      spi_sclk_o => spi_sclk_o,
+      spi_ncs_o  => spi_ncs_o,
+      spi_mosi_o => spi_mosi_o,
+      spi_miso_i => spi_miso_i,
+      uart_rxd_i => uart_rxd_i,
+      uart_txd_o => uart_txd_o,
+
+      owr_pwren_o => owr_pwren_o,
+      owr_en_o    => owr_en_o,
+      owr_i       => owr_i,
+
+      wb_adr_i   => slave_i.adr,
+      wb_dat_i   => slave_i.dat,
+      wb_dat_o   => slave_o.dat,
+      wb_sel_i   => slave_i.sel,
+      wb_we_i    => slave_i.we,
+      wb_cyc_i   => slave_i.cyc,
+      wb_stb_i   => slave_i.stb,
+      wb_ack_o   => slave_o.ack,
+      wb_err_o   => slave_o.err,
+      wb_rty_o   => slave_o.rty,
+      wb_stall_o => slave_o.stall,
+
+      aux_adr_o   => aux_master_o.adr,
+      aux_dat_o   => aux_master_o.dat,
+      aux_sel_o   => aux_master_o.sel,
+      aux_cyc_o   => aux_master_o.cyc,
+      aux_stb_o   => aux_master_o.stb,
+      aux_we_o    => aux_master_o.we,
+      aux_stall_i => aux_master_i.stall,
+      aux_ack_i   => aux_master_i.ack,
+      aux_dat_i   => aux_master_i.dat,
+
+      ext_snk_adr_i   => wrf_snk_i.adr,
+      ext_snk_dat_i   => wrf_snk_i.dat,
+      ext_snk_sel_i   => wrf_snk_i.sel,
+      ext_snk_cyc_i   => wrf_snk_i.cyc,
+      ext_snk_we_i    => wrf_snk_i.we,
+      ext_snk_stb_i   => wrf_snk_i.stb,
+      ext_snk_ack_o   => wrf_snk_o.ack,
+      ext_snk_err_o   => wrf_snk_o.err,
+      ext_snk_stall_o => wrf_snk_o.stall,
+
+      ext_src_adr_o   => wrf_src_o.adr,
+      ext_src_dat_o   => wrf_src_o.dat,
+      ext_src_sel_o   => wrf_src_o.sel,
+      ext_src_cyc_o   => wrf_src_o.cyc,
+      ext_src_stb_o   => wrf_src_o.stb,
+      ext_src_we_o    => wrf_src_o.we,
+      ext_src_ack_i   => wrf_src_i.ack,
+      ext_src_err_i   => wrf_src_i.err,
+      ext_src_stall_i => wrf_src_i.stall,
+
+      txtsu_port_id_o      => timestamps_o.port_id(4 downto 0),
+      txtsu_frame_id_o     => timestamps_o.frame_id,
+      txtsu_ts_value_o     => timestamps_o.tsval,
+      txtsu_ts_incorrect_o => timestamps_o.incorrect,
+      txtsu_stb_o          => timestamps_o.stb,
+      txtsu_ack_i          => timestamps_ack_i,
+
+      abscal_txts_o        => abscal_txts_o,
+      abscal_rxts_o        => abscal_rxts_o,
+      
+      fc_tx_pause_req_i    => fc_tx_pause_req_i,
+      fc_tx_pause_delay_i  => fc_tx_pause_delay_i,
+      fc_tx_pause_ready_o  => fc_tx_pause_ready_o,
+
+      tm_link_up_o         => tm_link_up_o,
+      tm_dac_value_o       => tm_dac_value_o,
+      tm_dac_wr_o          => tm_dac_wr_o,
+      tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
+      tm_clk_aux_locked_o  => tm_clk_aux_locked_o,
+      tm_time_valid_o      => tm_time_valid_o,
+      tm_tai_o             => tm_tai_o,
+      tm_cycles_o          => tm_cycles_o,
+      pps_csync_o          => pps_csync_o,
+      pps_p_o              => pps_p_o,
+      pps_led_o            => pps_led_o,
+
+      rst_aux_n_o => rst_aux_n_o,
+
+      link_ok_o => link_ok_o,
+
+      aux_diag_i => aux_diag_i,
+      aux_diag_o => aux_diag_o
+      );
+
+  timestamps_o.port_id(5) <= '0';
+
+  slave_o.int <= '0';
+
+  wrf_snk_o.rty <= '0';
+
+end struct;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/xwrc_diags_wb.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/xwrc_diags_wb.vhd
new file mode 100644
index 000000000..cce48c8b1
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/xwrc_diags_wb.vhd
@@ -0,0 +1,132 @@
+-------------------------------------------------------------------------------
+-- Title      : WR PTP Core Diagnostics
+-- Project    : WhiteRabbit
+-------------------------------------------------------------------------------
+-- File       : xwrc_diags_wb.vhd
+-- Author     : Maciej Lipinski <maciej.lipinski@cern.ch>
+-- Company    : CERN
+-- Created    : 2017-04-24
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- Wrapper for wrc_diags_wb. Uses types instead of std_logic signals and
+-- can use pipelined or classic wishbone.
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.wishbone_pkg.all;
+use work.wrc_diags_wbgen2_pkg.all;
+
+entity xwr_diags_wb is
+  generic(
+    g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity : t_wishbone_address_granularity := WORD
+  );
+  port (
+    rst_n_i   : in  std_logic;
+    clk_sys_i : in  std_logic;
+
+    slave_i   : in  t_wishbone_slave_in;
+    slave_o   : out t_wishbone_slave_out;
+
+    regs_i    : in  t_wrc_diags_in_registers;
+    regs_o    : out t_wrc_diags_out_registers
+  );
+end xwr_diags_wb;
+
+architecture syn of xwr_diags_wb is
+
+  component wrc_diags_wb is
+    port (
+      rst_n_i                                  : in     std_logic;
+      clk_sys_i                                : in     std_logic;
+      wb_adr_i                                 : in     std_logic_vector(4 downto 0);
+      wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+      wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+      wb_cyc_i                                 : in     std_logic;
+      wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+      wb_stb_i                                 : in     std_logic;
+      wb_we_i                                  : in     std_logic;
+      wb_ack_o                                 : out    std_logic;
+      wb_stall_o                               : out    std_logic;
+      regs_i                                   : in     t_wrc_diags_in_registers;
+      regs_o                                   : out    t_wrc_diags_out_registers
+    );
+  end component;
+
+
+  signal wb_out : t_wishbone_slave_out;
+  signal wb_in  : t_wishbone_slave_in;
+
+begin
+
+  U_Adapter : wb_slave_adapter
+    generic map(
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => false,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      master_i   => wb_out,
+      master_o   => wb_in,
+      sl_adr_i   => slave_i.adr,
+      sl_dat_i   => slave_i.dat,
+      sl_sel_i   => slave_i.sel,
+      sl_cyc_i   => slave_i.cyc,
+      sl_stb_i   => slave_i.stb,
+      sl_we_i    => slave_i.we,
+      sl_dat_o   => slave_o.dat, 
+      sl_ack_o   => slave_o.ack,
+      sl_stall_o => slave_o.stall);
+
+  WRAPPED_DIAGS: wrc_diags_wb
+    port map(
+      rst_n_i    => rst_n_i,
+      clk_sys_i  => clk_sys_i,
+      wb_adr_i   => wb_in.adr(4 downto 0),
+      wb_dat_i   => wb_in.dat,
+      wb_dat_o   => wb_out.dat,
+      wb_cyc_i   => wb_in.cyc,
+      wb_sel_i   => wb_in.sel,
+      wb_stb_i   => wb_in.stb,
+      wb_we_i    => wb_in.we,
+      wb_ack_o   => wb_out.ack,
+      wb_stall_o => wb_out.stall,
+      regs_i     => regs_i,
+      regs_o     => regs_o);
+
+  slave_o.err <= '0';
+  slave_o.rty <= '0';
+  slave_o.int <= '0';
+
+end syn;
+
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd
new file mode 100644
index 000000000..f981871f4
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd
@@ -0,0 +1,491 @@
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.6
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : whiterabbit_gtpe2_channel_wrapper.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module whiterabbit_gtpe2_channel_wrapper (a GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+
+entity whiterabbit_gtpe2_channel_wrapper is
+generic
+(
+    -- Simulation attributes
+    EXAMPLE_SIMULATION             : integer  := 0;      -- Set to 1 for simulation
+    WRAPPER_SIM_GTRESET_SPEEDUP    : string   := "FALSE" -- Set to "true" to speed up sim reset
+);
+port
+(
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --____________________________CHANNEL PORTS________________________________
+    GT0_DRP_BUSY_OUT                        : out  std_logic; 
+    ---------------------------- Channel - DRP Ports  --------------------------
+    GT0_DRPADDR_IN                          : in   std_logic_vector(8 downto 0);
+    GT0_DRPCLK_IN                           : in   std_logic;
+    GT0_DRPDI_IN                            : in   std_logic_vector(15 downto 0);
+    GT0_DRPDO_OUT                           : out  std_logic_vector(15 downto 0);
+    GT0_DRPEN_IN                            : in   std_logic;
+    GT0_DRPRDY_OUT                          : out  std_logic;
+    GT0_DRPWE_IN                            : in   std_logic;
+    ------------------------------- Loopback Ports -----------------------------
+    GT0_LOOPBACK_IN                         : in   std_logic_vector(2 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    GT0_RXUSERRDY_IN                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    GT0_EYESCANDATAERROR_OUT                : out  std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    GT0_RXDATA_OUT                          : out  std_logic_vector(15 downto 0);
+    GT0_RXUSRCLK_IN                         : in   std_logic;
+    GT0_RXUSRCLK2_IN                        : in   std_logic;
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    GT0_RXCHARISCOMMA_OUT                   : out  std_logic_vector(1 downto 0);
+    GT0_RXCHARISK_OUT                       : out  std_logic_vector(1 downto 0);
+    GT0_RXDISPERR_OUT                       : out  std_logic_vector(1 downto 0);
+    GT0_RXNOTINTABLE_OUT                    : out  std_logic_vector(1 downto 0);
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    GT0_GTPRXN_IN                           : in   std_logic;
+    GT0_GTPRXP_IN                           : in   std_logic;
+    -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+    GT0_RXBYTEISALIGNED_OUT                 : out  std_logic;
+    GT0_RXCOMMADET_OUT                      : out  std_logic;
+    GT0_RXSLIDE_IN                          : in   std_logic;
+    --------------------- Receive Ports - RX Equilizer Ports -------------------
+    GT0_RXLPMHFHOLD_IN                      : in   std_logic;
+    GT0_RXLPMLFHOLD_IN                      : in   std_logic;
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    GT0_RXOUTCLK_OUT                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    GT0_GTRXRESET_IN                        : in   std_logic;
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    GT0_RXRESETDONE_OUT                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    GT0_GTTXRESET_IN                        : in   std_logic;
+    GT0_TXUSERRDY_IN                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    GT0_TXDATA_IN                           : in   std_logic_vector(15 downto 0);
+    GT0_TXUSRCLK_IN                         : in   std_logic;
+    GT0_TXUSRCLK2_IN                        : in   std_logic;
+    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
+    GT0_TXCHARISK_IN                        : in   std_logic_vector(1 downto 0);
+    --------------- Transmit Ports - TX Configurable Driver Ports --------------
+    GT0_GTPTXN_OUT                          : out  std_logic;
+    GT0_GTPTXP_OUT                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    GT0_TXOUTCLK_OUT                        : out  std_logic;
+    GT0_TXOUTCLKFABRIC_OUT                  : out  std_logic;
+    GT0_TXOUTCLKPCS_OUT                     : out  std_logic;
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    GT0_TXRESETDONE_OUT                     : out  std_logic;
+    ------------------ Transmit Ports - pattern Generator Ports ----------------
+    GT0_TXPRBSSEL_IN                        : in   std_logic_vector(2 downto 0);
+
+	
+    --____________________________COMMON PORTS________________________________
+    ----------------- Common Block - GTPE2_COMMON Clocking Ports ---------------
+    GT0_GTREFCLK0_IN                        : in   std_logic;
+    -------------------------- Common Block - PLL Ports ------------------------
+    GT0_PLL1LOCK_OUT                        : out  std_logic;
+    GT0_PLL1LOCKDETCLK_IN                   : in   std_logic;
+    GT0_PLL1REFCLKLOST_OUT                  : out  std_logic;
+    GT0_PLL1RESET_IN                        : in   std_logic
+
+
+);
+
+
+end whiterabbit_gtpe2_channel_wrapper;
+    
+architecture RTL of whiterabbit_gtpe2_channel_wrapper is
+
+    attribute CORE_GENERATION_INFO : string;
+    attribute CORE_GENERATION_INFO of RTL : architecture is "whiterabbit_gtpe2_channel_wrapper,gtwizard_v3_6_1,{protocol_file=Start_from_scratch}";
+
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--***************************** Signal Declarations *****************************
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+    signal   gt0_pll0outclk_i       :   std_logic;
+    signal   gt0_pll0outrefclk_i    :   std_logic;
+    signal   gt0_pll1outclk_i       :   std_logic;
+    signal   gt0_pll1outrefclk_i    :   std_logic;
+
+ 
+    signal  gt0_mgtrefclktx_i           :   std_logic_vector(1 downto 0);
+    signal  gt0_mgtrefclkrx_i           :   std_logic_vector(1 downto 0);
+ 
+
+    signal   gt0_pll0clk_i       :   std_logic;
+    signal   gt0_pll0refclk_i    :   std_logic;
+    signal   gt0_pll1clk_i       :   std_logic;
+    signal   gt0_pll1refclk_i    :   std_logic;
+    signal    gt0_rst_i                       : std_logic;
+      
+
+
+
+--*************************** Component Declarations **************************
+component whiterabbit_gtpe2_channel_wrapper_gt
+generic
+(
+    -- Simulation attributes
+    GT_SIM_GTRESET_SPEEDUP    : string := "false";
+    EXAMPLE_SIMULATION        : integer  := 0;  
+    TXSYNC_OVRD_IN            : bit    := '0';
+    TXSYNC_MULTILANE_IN       : bit    := '0'     
+);
+port 
+(   
+    RST_IN                                  : in   std_logic;
+    DRP_BUSY_OUT                            : out  std_logic;
+   
+    ---------------------------- Channel - DRP Ports  --------------------------
+    DRPADDR_IN                              : in   std_logic_vector(8 downto 0);
+    DRPCLK_IN                               : in   std_logic;
+    DRPDI_IN                                : in   std_logic_vector(15 downto 0);
+    DRPDO_OUT                               : out  std_logic_vector(15 downto 0);
+    DRPEN_IN                                : in   std_logic;
+    DRPRDY_OUT                              : out  std_logic;
+    DRPWE_IN                                : in   std_logic;
+    ------------------------ GTPE2_CHANNEL Clocking Ports ----------------------
+    PLL0CLK_IN                              : in   std_logic;
+    PLL0REFCLK_IN                           : in   std_logic;
+    PLL1CLK_IN                              : in   std_logic;
+    PLL1REFCLK_IN                           : in   std_logic;
+    ------------------------------- Loopback Ports -----------------------------
+    LOOPBACK_IN                             : in   std_logic_vector(2 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    RXUSERRDY_IN                            : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    EYESCANDATAERROR_OUT                    : out  std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    RXDATA_OUT                              : out  std_logic_vector(15 downto 0);
+    RXUSRCLK_IN                             : in   std_logic;
+    RXUSRCLK2_IN                            : in   std_logic;
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    RXCHARISCOMMA_OUT                       : out  std_logic_vector(1 downto 0);
+    RXCHARISK_OUT                           : out  std_logic_vector(1 downto 0);
+    RXDISPERR_OUT                           : out  std_logic_vector(1 downto 0);
+    RXNOTINTABLE_OUT                        : out  std_logic_vector(1 downto 0);
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    GTPRXN_IN                               : in   std_logic;
+    GTPRXP_IN                               : in   std_logic;
+    -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+    RXBYTEISALIGNED_OUT                     : out  std_logic;
+    RXCOMMADET_OUT                          : out  std_logic;
+    RXSLIDE_IN                              : in   std_logic;
+    --------------------- Receive Ports - RX Equilizer Ports -------------------
+    RXLPMHFHOLD_IN                          : in   std_logic;
+    RXLPMLFHOLD_IN                          : in   std_logic;
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    RXOUTCLK_OUT                            : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    GTRXRESET_IN                            : in   std_logic;
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    RXRESETDONE_OUT                         : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    GTTXRESET_IN                            : in   std_logic;
+    TXUSERRDY_IN                            : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    TXDATA_IN                               : in   std_logic_vector(15 downto 0);
+    TXUSRCLK_IN                             : in   std_logic;
+    TXUSRCLK2_IN                            : in   std_logic;
+    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
+    TXCHARISK_IN                            : in   std_logic_vector(1 downto 0);
+    --------------- Transmit Ports - TX Configurable Driver Ports --------------
+    GTPTXN_OUT                              : out  std_logic;
+    GTPTXP_OUT                              : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    TXOUTCLK_OUT                            : out  std_logic;
+    TXOUTCLKFABRIC_OUT                      : out  std_logic;
+    TXOUTCLKPCS_OUT                         : out  std_logic;
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    TXRESETDONE_OUT                         : out  std_logic;
+    ------------------ Transmit Ports - pattern Generator Ports ----------------
+    TXPRBSSEL_IN                            : in   std_logic_vector(2 downto 0)
+
+
+);
+end component;
+
+
+    constant PLL0_FBDIV_IN      :   integer := 1;
+    constant PLL1_FBDIV_IN      :   integer := 4;
+    constant PLL0_FBDIV_45_IN   :   integer := 4;
+    constant PLL1_FBDIV_45_IN   :   integer := 5;
+    constant PLL0_REFCLK_DIV_IN :   integer := 1;
+    constant PLL1_REFCLK_DIV_IN :   integer := 1;
+
+--********************************* Main Body of Code**************************
+
+begin                       
+
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+    gt0_pll0clk_i    <= gt0_pll0outclk_i;  
+    gt0_pll0refclk_i <= gt0_pll0outrefclk_i; 
+    gt0_pll1clk_i    <= gt0_pll1outclk_i;  
+    gt0_pll1refclk_i <= gt0_pll1outrefclk_i; 
+      
+    gt0_rst_i        <= GT0_PLL1RESET_IN;
+   
+    
+    --------------------------- GT Instances  -------------------------------   
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    GT_INST : whiterabbit_gtpe2_channel_wrapper_gt
+    generic map
+    (
+        -- Simulation attributes
+        GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
+        EXAMPLE_SIMULATION     => EXAMPLE_SIMULATION,
+        TXSYNC_OVRD_IN         => ('0'),
+        TXSYNC_MULTILANE_IN    => ('0')
+    )
+    port map
+    (
+        RST_IN                          =>      gt0_rst_i,
+        DRP_BUSY_OUT                    =>      GT0_DRP_BUSY_OUT,
+    
+        ---------------------------- Channel - DRP Ports  --------------------------
+        DRPADDR_IN                      =>      GT0_DRPADDR_IN,
+        DRPCLK_IN                       =>      GT0_DRPCLK_IN,
+        DRPDI_IN                        =>      GT0_DRPDI_IN,
+        DRPDO_OUT                       =>      GT0_DRPDO_OUT,
+        DRPEN_IN                        =>      GT0_DRPEN_IN,
+        DRPRDY_OUT                      =>      GT0_DRPRDY_OUT,
+        DRPWE_IN                        =>      GT0_DRPWE_IN,
+        ------------------------ GTPE2_CHANNEL Clocking Ports ----------------------
+        PLL0CLK_IN                      =>      gt0_pll0clk_i,
+        PLL0REFCLK_IN                   =>      gt0_pll0refclk_i,
+        PLL1CLK_IN                      =>      gt0_pll1clk_i,
+        PLL1REFCLK_IN                   =>      gt0_pll1refclk_i,
+        ------------------------------- Loopback Ports -----------------------------
+        LOOPBACK_IN                     =>      GT0_LOOPBACK_IN,
+        --------------------- RX Initialization and Reset Ports --------------------
+        RXUSERRDY_IN                    =>      GT0_RXUSERRDY_IN,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        EYESCANDATAERROR_OUT            =>      GT0_EYESCANDATAERROR_OUT,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        RXDATA_OUT                      =>      GT0_RXDATA_OUT,
+        RXUSRCLK_IN                     =>      GT0_RXUSRCLK_IN,
+        RXUSRCLK2_IN                    =>      GT0_RXUSRCLK2_IN,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        RXCHARISCOMMA_OUT               =>      GT0_RXCHARISCOMMA_OUT,
+        RXCHARISK_OUT                   =>      GT0_RXCHARISK_OUT,
+        RXDISPERR_OUT                   =>      GT0_RXDISPERR_OUT,
+        RXNOTINTABLE_OUT                =>      GT0_RXNOTINTABLE_OUT,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        GTPRXN_IN                       =>      GT0_GTPRXN_IN,
+        GTPRXP_IN                       =>      GT0_GTPRXP_IN,
+        -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+        RXBYTEISALIGNED_OUT             =>      GT0_RXBYTEISALIGNED_OUT,
+        RXCOMMADET_OUT                  =>      GT0_RXCOMMADET_OUT,
+        RXSLIDE_IN                      =>      GT0_RXSLIDE_IN,
+        --------------------- Receive Ports - RX Equilizer Ports -------------------
+        RXLPMHFHOLD_IN                  =>      GT0_RXLPMHFHOLD_IN,
+        RXLPMLFHOLD_IN                  =>      GT0_RXLPMLFHOLD_IN,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        RXOUTCLK_OUT                    =>      GT0_RXOUTCLK_OUT,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        GTRXRESET_IN                    =>      GT0_GTRXRESET_IN,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        RXRESETDONE_OUT                 =>      GT0_RXRESETDONE_OUT,
+        --------------------- TX Initialization and Reset Ports --------------------
+        GTTXRESET_IN                    =>      GT0_GTTXRESET_IN,
+        TXUSERRDY_IN                    =>      GT0_TXUSERRDY_IN,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        TXDATA_IN                       =>      GT0_TXDATA_IN,
+        TXUSRCLK_IN                     =>      GT0_TXUSRCLK_IN,
+        TXUSRCLK2_IN                    =>      GT0_TXUSRCLK2_IN,
+        ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
+        TXCHARISK_IN                    =>      GT0_TXCHARISK_IN,
+        --------------- Transmit Ports - TX Configurable Driver Ports --------------
+        GTPTXN_OUT                      =>      GT0_GTPTXN_OUT,
+        GTPTXP_OUT                      =>      GT0_GTPTXP_OUT,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        TXOUTCLK_OUT                    =>      GT0_TXOUTCLK_OUT,
+        TXOUTCLKFABRIC_OUT              =>      GT0_TXOUTCLKFABRIC_OUT,
+        TXOUTCLKPCS_OUT                 =>      GT0_TXOUTCLKPCS_OUT,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        TXRESETDONE_OUT                 =>      GT0_TXRESETDONE_OUT,
+        ------------------ Transmit Ports - pattern Generator Ports ----------------
+        TXPRBSSEL_IN                    =>      GT0_TXPRBSSEL_IN
+
+    );
+
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --_________________________GTPE2_COMMON____________________________________
+
+    gtpe2_common_0_i : GTPE2_COMMON
+    generic map
+    (
+            -- Simulation attributes
+            SIM_RESET_SPEEDUP    => WRAPPER_SIM_GTRESET_SPEEDUP,
+            SIM_PLL0REFCLK_SEL   => ("001"),
+            SIM_PLL1REFCLK_SEL   => ("001"),
+            SIM_VERSION          => ("1.0"),
+
+            PLL0_FBDIV           => PLL0_FBDIV_IN     ,	
+	    PLL0_FBDIV_45        => PLL0_FBDIV_45_IN  ,	
+	    PLL0_REFCLK_DIV      => PLL0_REFCLK_DIV_IN,	
+	    PLL1_FBDIV           => PLL1_FBDIV_IN     ,	
+	    PLL1_FBDIV_45        => PLL1_FBDIV_45_IN  ,	
+	    PLL1_REFCLK_DIV      => PLL1_REFCLK_DIV_IN,	            
+
+
+       ------------------COMMON BLOCK Attributes---------------
+        BIAS_CFG                                =>     (x"0000000000050001"),
+        COMMON_CFG                              =>     (x"00000000"),
+
+       ----------------------------PLL Attributes----------------------------
+        PLL0_CFG                                =>     (x"01F03DC"),
+        PLL0_DMON_CFG                           =>     ('0'),
+        PLL0_INIT_CFG                           =>     (x"00001E"),
+        PLL0_LOCK_CFG                           =>     (x"1E8"),
+        PLL1_CFG                                =>     (x"01F03DC"),
+        PLL1_DMON_CFG                           =>     ('0'),
+        PLL1_INIT_CFG                           =>     (x"00001E"),
+        PLL1_LOCK_CFG                           =>     (x"1E8"),
+        PLL_CLKOUT_CFG                          =>     (x"00"),
+
+       ----------------------------Reserved Attributes----------------------------
+        RSVD_ATTR0                              =>     (x"0000"),
+        RSVD_ATTR1                              =>     (x"0000")
+
+        
+    )
+    port map
+    (
+	     DMONITOROUT             => open,	
+        ------------- Common Block  - Dynamic Reconfiguration Port (DRP) -----------
+        DRPADDR                         =>      tied_to_ground_vec_i(7 downto 0),
+        DRPCLK                          =>      tied_to_ground_i,
+        DRPDI                           =>      tied_to_ground_vec_i(15 downto 0),
+        DRPDO                           =>      open,
+        DRPEN                           =>      tied_to_ground_i,
+        DRPRDY                          =>      open,
+        DRPWE                           =>      tied_to_ground_i,
+        ----------------- Common Block - GTPE2_COMMON Clocking Ports ---------------
+        GTEASTREFCLK0                   =>      tied_to_ground_i,
+        GTEASTREFCLK1                   =>      tied_to_ground_i,
+        GTGREFCLK1                      =>      tied_to_ground_i,
+        GTREFCLK0                       =>      GT0_GTREFCLK0_IN,
+        GTREFCLK1                       =>      tied_to_ground_i,
+        GTWESTREFCLK0                   =>      tied_to_ground_i,
+        GTWESTREFCLK1                   =>      tied_to_ground_i,
+        PLL0OUTCLK                      =>      gt0_pll0outclk_i,
+        PLL0OUTREFCLK                   =>      gt0_pll0outrefclk_i,
+        PLL1OUTCLK                      =>      gt0_pll1outclk_i,
+        PLL1OUTREFCLK                   =>      gt0_pll1outrefclk_i,
+        -------------------------- Common Block - PLL Ports ------------------------
+        PLL0FBCLKLOST                   =>      open,
+        PLL0LOCK                        =>      open,
+        PLL0LOCKDETCLK                  =>      tied_to_ground_i,
+        PLL0LOCKEN                      =>      tied_to_vcc_i,
+        PLL0PD                          =>      '1',
+        PLL0REFCLKLOST                  =>      open,
+        PLL0REFCLKSEL                   =>      "001",
+        PLL0RESET                       =>      tied_to_ground_i,
+        PLL1FBCLKLOST                   =>      open,
+        PLL1LOCK                        =>      GT0_PLL1LOCK_OUT,
+        PLL1LOCKDETCLK                  =>      GT0_PLL1LOCKDETCLK_IN,
+        PLL1LOCKEN                      =>      tied_to_vcc_i,
+        PLL1PD                          =>      tied_to_ground_i,
+        PLL1REFCLKLOST                  =>      GT0_PLL1REFCLKLOST_OUT,
+        PLL1REFCLKSEL                   =>      "001",
+        PLL1RESET                       =>      GT0_PLL1RESET_IN,
+        ---------------------------- Common Block - Ports --------------------------
+        BGRCALOVRDENB                   =>      tied_to_vcc_i,
+        GTGREFCLK0                      =>      tied_to_ground_i,
+        PLLRSVD1                        =>      "0000000000000000",
+        PLLRSVD2                        =>      "00000",
+        REFCLKOUTMONITOR0               =>      open,
+        REFCLKOUTMONITOR1               =>      open,
+        ------------------------ Common Block - RX AFE Ports -----------------------
+        PMARSVDOUT                      =>      open,
+        --------------------------------- QPLL Ports -------------------------------
+        BGBYPASSB                       =>      tied_to_vcc_i,
+        BGMONITORENB                    =>      tied_to_vcc_i,
+        BGPDB                           =>      tied_to_vcc_i,
+        BGRCALOVRD                      =>      "00000",           -- ug482 table 2-8 says "111111"
+        PMARSVD                         =>      "00000000",
+        RCALENB                         =>      tied_to_vcc_i
+
+    );
+
+     
+end RTL;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd
new file mode 100644
index 000000000..90ca8f391
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd
@@ -0,0 +1,1013 @@
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.6
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : whiterabbit_gtpe2_channel_wrapper_gt.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module whiterabbit_gtpe2_channel_wrapper_GT (a GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***************************** Entity Declaration ****************************
+
+entity whiterabbit_gtpe2_channel_wrapper_gt is
+generic
+(
+    -- Simulation attributes
+    GT_SIM_GTRESET_SPEEDUP    : string := "FALSE"; -- Set to "true" to speed up sim reset
+    EXAMPLE_SIMULATION        : integer  := 0;     -- Set to 1 for simulation
+    TXSYNC_OVRD_IN            : bit    := '0';
+    TXSYNC_MULTILANE_IN       : bit    := '0' 
+);
+port 
+(
+  RST_IN         : in   std_logic;          -- Connect to System Reset
+  DRP_BUSY_OUT   : out  std_logic;          -- Indicates that the DRP bus is not accessible to the User
+    ---------------------------- Channel - DRP Ports  --------------------------
+    drpaddr_in                              : in   std_logic_vector(8 downto 0);
+    drpclk_in                               : in   std_logic;
+    drpdi_in                                : in   std_logic_vector(15 downto 0);
+    drpdo_out                               : out  std_logic_vector(15 downto 0);
+    drpen_in                                : in   std_logic;
+    drprdy_out                              : out  std_logic;
+    drpwe_in                                : in   std_logic;
+    ------------------------ GTPE2_CHANNEL Clocking Ports ----------------------
+    pll0clk_in                              : in   std_logic;
+    pll0refclk_in                           : in   std_logic;
+    pll1clk_in                              : in   std_logic;
+    pll1refclk_in                           : in   std_logic;
+    ------------------------------- Loopback Ports -----------------------------
+    loopback_in                             : in   std_logic_vector(2 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    rxuserrdy_in                            : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    eyescandataerror_out                    : out  std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    rxdata_out                              : out  std_logic_vector(15 downto 0);
+    rxusrclk_in                             : in   std_logic;
+    rxusrclk2_in                            : in   std_logic;
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    rxchariscomma_out                       : out  std_logic_vector(1 downto 0);
+    rxcharisk_out                           : out  std_logic_vector(1 downto 0);
+    rxdisperr_out                           : out  std_logic_vector(1 downto 0);
+    rxnotintable_out                        : out  std_logic_vector(1 downto 0);
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gtprxn_in                               : in   std_logic;
+    gtprxp_in                               : in   std_logic;
+    -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+    rxbyteisaligned_out                     : out  std_logic;
+    rxcommadet_out                          : out  std_logic;
+    rxslide_in                              : in   std_logic;
+    --------------------- Receive Ports - RX Equilizer Ports -------------------
+    rxlpmhfhold_in                          : in   std_logic;
+    rxlpmlfhold_in                          : in   std_logic;
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    rxoutclk_out                            : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gtrxreset_in                            : in   std_logic;
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    rxresetdone_out                         : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gttxreset_in                            : in   std_logic;
+    txuserrdy_in                            : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    txdata_in                               : in   std_logic_vector(15 downto 0);
+    txusrclk_in                             : in   std_logic;
+    txusrclk2_in                            : in   std_logic;
+    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
+    txcharisk_in                            : in   std_logic_vector(1 downto 0);
+    --------------- Transmit Ports - TX Configurable Driver Ports --------------
+    gtptxn_out                              : out  std_logic;
+    gtptxp_out                              : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    txoutclk_out                            : out  std_logic;
+    txoutclkfabric_out                      : out  std_logic;
+    txoutclkpcs_out                         : out  std_logic;
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    txresetdone_out                         : out  std_logic;
+    ------------------ Transmit Ports - pattern Generator Ports ----------------
+    txprbssel_in                            : in   std_logic_vector(2 downto 0)
+
+);
+
+
+end whiterabbit_gtpe2_channel_wrapper_gt;
+
+architecture RTL of whiterabbit_gtpe2_channel_wrapper_gt is
+
+--*************************** Component Declarations **************************
+component whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq  
+  port ( 
+    RST           : IN  std_logic;
+    GTRXRESET_IN  : IN  std_logic;    
+    RXPMARESETDONE: IN  std_logic;
+    GTRXRESET_OUT : OUT std_logic;
+
+    DRPCLK        : IN  std_logic;
+    DRPADDR       : OUT std_logic_vector(8 downto 0);
+    DRPDO	  : IN  std_logic_vector(15 downto 0);
+    DRPDI         : OUT std_logic_vector(15 downto 0);
+    DRPRDY        : IN  std_logic;
+    DRPEN	  : OUT std_logic;
+    DRPWE         : OUT std_logic;
+    DRP_OP_DONE   : OUT std_logic
+);
+end component;
+
+--component whiterabbitgtp_wrapper_rxpmarst_seq 
+--  port ( 
+--    RST                : IN  std_logic;
+--    RXPMARESET_IN      : IN  std_logic;    
+--    RXPMARESETDONE     : IN  std_logic;
+--    RXPMARESET_OUT     : OUT std_logic;
+--
+--    DRPCLK             : IN  std_logic;
+--    DRPADDR            : OUT std_logic_vector(8 downto 0);
+--    DRPDO              : IN  std_logic_vector(15 downto 0);
+--    DRPDI              : OUT std_logic_vector(15 downto 0);
+--    DRPRDY             : IN  std_logic;
+--    DRPEN              : OUT std_logic;
+--    DRPWE              : OUT std_logic;
+--    DRP_BUSY_IN        : IN  std_logic;
+--    DRP_PMA_BUSY_OUT   : OUT std_logic
+--);
+--end component;
+--
+--
+--component whiterabbitgtp_wrapper_rxrate_seq 
+--  port ( 
+--    RST                : IN  std_logic;
+--    RXRATE_IN          : IN  std_logic_vector(2 downto 0);    
+--    RXPMARESETDONE     : IN  std_logic;
+--    RXRATE_OUT         : OUT std_logic_vector(2 downto 0);
+--
+--    DRPCLK             : IN  std_logic;
+--    DRPADDR            : OUT std_logic_vector(8 downto 0);
+--    DRPDO              : IN  std_logic_vector(15 downto 0);
+--    DRPDI              : OUT std_logic_vector(15 downto 0);
+--    DRPRDY             : IN  std_logic;
+--    DRPEN              : OUT std_logic;
+--    DRPWE              : OUT std_logic;
+--    DRP_BUSY_IN        : IN  std_logic;
+--    DRP_RATE_BUSY_OUT  : OUT std_logic
+--);
+--end component;
+
+--**************************** Signal Declarations ****************************
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+
+
+    signal    rxpmaresetdone_t                : std_logic;
+    signal    gtrxreset_out                   : std_logic;
+    signal    rxpmareset_out                  : std_logic;
+    signal    rxrate_out                      : std_logic_vector(2 downto 0);
+    signal    drp_op_done                     : std_logic;
+    signal    drp_pma_busy                    : std_logic;
+    signal    drp_rate_busy                   : std_logic;
+    signal    drp_busy_i1                     : std_logic:= '0';
+    signal    drp_busy_i2                     : std_logic:= '0';
+    signal    drpen_rst_t                     : std_logic;
+    signal    drpaddr_rst_t                   : std_logic_vector(8 downto 0);
+    signal    drpwe_rst_t                     : std_logic;
+    signal    drpdo_rst_t                     : std_logic_vector(15 downto 0);
+    signal    drpdi_rst_t                     : std_logic_vector(15 downto 0);
+    signal    drprdy_rst_t                    : std_logic;
+    signal    drpen_pma_t                     : std_logic;
+    signal    drpaddr_pma_t                   : std_logic_vector(8 downto 0);
+    signal    drpwe_pma_t                     : std_logic;
+    signal    drpdo_pma_t                     : std_logic_vector(15 downto 0);
+    signal    drpdi_pma_t                     : std_logic_vector(15 downto 0);
+    signal    drprdy_pma_t                    : std_logic;
+    signal    drpen_rate_t                    : std_logic;
+    signal    drpaddr_rate_t                  : std_logic_vector(8 downto 0);
+    signal    drpwe_rate_t                    : std_logic;
+    signal    drpdo_rate_t                    : std_logic_vector(15 downto 0);
+    signal    drpdi_rate_t                    : std_logic_vector(15 downto 0);
+    signal    drprdy_rate_t                   : std_logic;
+    signal    drpen_i                         : std_logic;
+    signal    drpaddr_i                       : std_logic_vector(8 downto 0);
+    signal    drpwe_i                         : std_logic;
+    signal    drpdo_i                         : std_logic_vector(15 downto 0);
+    signal    drpdi_i                         : std_logic_vector(15 downto 0);
+    signal    drprdy_i                        : std_logic;
+
+    -- RX Datapath signals
+    signal rxdata_i                         :   std_logic_vector(31 downto 0);      
+    signal rxchariscomma_float_i            :   std_logic_vector(1 downto 0);
+    signal rxcharisk_float_i                :   std_logic_vector(1 downto 0);
+    signal rxdisperr_float_i                :   std_logic_vector(1 downto 0);
+    signal rxnotintable_float_i             :   std_logic_vector(1 downto 0);
+    signal rxrundisp_float_i                :   std_logic_vector(1 downto 0);
+
+
+    -- TX Datapath signals
+    signal txdata_i                         :   std_logic_vector(31 downto 0);
+    signal txkerr_float_i                   :   std_logic_vector(1 downto 0);
+    signal txrundisp_float_i                :   std_logic_vector(1 downto 0);
+    signal rxdatavalid_float_i              :   std_logic;
+        
+--******************************** Main Body of Code***************************
+                       
+begin                      
+
+    ---------------------------  Static signal Assignments ---------------------   
+
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+
+    -------------------  GT Datapath byte mapping  -----------------
+    RXDATA_OUT    <=   rxdata_i(15 downto 0);
+
+    txdata_i    <=   (tied_to_ground_vec_i(15 downto 0) & TXDATA_IN);
+
+
+
+    ----------------------------- GTPE2 Instance  --------------------------   
+
+    gtpe2_i : GTPE2_CHANNEL
+    generic map
+    (
+
+        --_______________________ Simulation-Only Attributes ___________________
+
+        SIM_RECEIVER_DETECT_PASS   =>      ("TRUE"),
+        SIM_RESET_SPEEDUP          =>      (GT_SIM_GTRESET_SPEEDUP),
+        SIM_TX_EIDLE_DRIVE_LEVEL   =>      ("X"),
+        SIM_VERSION                =>      ("2.0"),
+        
+
+       ------------------RX Byte and Word Alignment Attributes---------------
+        ALIGN_COMMA_DOUBLE                      =>     ("FALSE"),
+        ALIGN_COMMA_ENABLE                      =>     ("0001111111"),
+        ALIGN_COMMA_WORD                        =>     (2),
+        ALIGN_MCOMMA_DET                        =>     ("TRUE"),
+        ALIGN_MCOMMA_VALUE                      =>     ("1010000011"),
+        ALIGN_PCOMMA_DET                        =>     ("TRUE"),
+        ALIGN_PCOMMA_VALUE                      =>     ("0101111100"),
+        SHOW_REALIGN_COMMA                      =>     ("FALSE"),
+        RXSLIDE_AUTO_WAIT                       =>     (7),
+        RXSLIDE_MODE                            =>     ("PCS"),
+        RX_SIG_VALID_DLY                        =>     (10),
+
+       ------------------RX 8B/10B Decoder Attributes---------------
+        RX_DISPERR_SEQ_MATCH                    =>     ("TRUE"),
+        DEC_MCOMMA_DETECT                       =>     ("TRUE"),
+        DEC_PCOMMA_DETECT                       =>     ("TRUE"),
+        DEC_VALID_COMMA_ONLY                    =>     ("TRUE"),
+
+       ------------------------RX Clock Correction Attributes----------------------
+        CBCC_DATA_SOURCE_SEL                    =>     ("DECODED"),
+        CLK_COR_SEQ_2_USE                       =>     ("FALSE"),
+        CLK_COR_KEEP_IDLE                       =>     ("FALSE"),
+        CLK_COR_MAX_LAT                         =>     (10),
+        CLK_COR_MIN_LAT                         =>     (8),
+        CLK_COR_PRECEDENCE                      =>     ("TRUE"),
+        CLK_COR_REPEAT_WAIT                     =>     (0),
+        CLK_COR_SEQ_LEN                         =>     (1),
+        CLK_COR_SEQ_1_ENABLE                    =>     ("1111"),
+        CLK_COR_SEQ_1_1                         =>     ("0100000000"),
+        CLK_COR_SEQ_1_2                         =>     ("0000000000"),
+        CLK_COR_SEQ_1_3                         =>     ("0000000000"),
+        CLK_COR_SEQ_1_4                         =>     ("0000000000"),
+        CLK_CORRECT_USE                         =>     ("FALSE"),
+        CLK_COR_SEQ_2_ENABLE                    =>     ("1111"),
+        CLK_COR_SEQ_2_1                         =>     ("0100000000"),
+        CLK_COR_SEQ_2_2                         =>     ("0000000000"),
+        CLK_COR_SEQ_2_3                         =>     ("0000000000"),
+        CLK_COR_SEQ_2_4                         =>     ("0000000000"),
+
+       ------------------------RX Channel Bonding Attributes----------------------
+        CHAN_BOND_KEEP_ALIGN                    =>     ("FALSE"),
+        CHAN_BOND_MAX_SKEW                      =>     (1),
+        CHAN_BOND_SEQ_LEN                       =>     (1),
+        CHAN_BOND_SEQ_1_1                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_2                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_3                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_4                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_ENABLE                  =>     ("1111"),
+        CHAN_BOND_SEQ_2_1                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_2                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_3                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_4                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_ENABLE                  =>     ("1111"),
+        CHAN_BOND_SEQ_2_USE                     =>     ("FALSE"),
+        FTS_DESKEW_SEQ_ENABLE                   =>     ("1111"),
+        FTS_LANE_DESKEW_CFG                     =>     ("1111"),
+        FTS_LANE_DESKEW_EN                      =>     ("FALSE"),
+
+       ---------------------------RX Margin Analysis Attributes----------------------------
+        ES_CONTROL                              =>     ("000000"),
+        ES_ERRDET_EN                            =>     ("FALSE"),
+        ES_EYE_SCAN_EN                          =>     ("FALSE"),
+        ES_HORZ_OFFSET                          =>     (x"010"),
+        ES_PMA_CFG                              =>     ("0000000000"),
+        ES_PRESCALE                             =>     ("00000"),
+        ES_QUALIFIER                            =>     (x"00000000000000000000"),
+        ES_QUAL_MASK                            =>     (x"00000000000000000000"),
+        ES_SDATA_MASK                           =>     (x"00000000000000000000"),
+        ES_VERT_OFFSET                          =>     ("000000000"),
+
+       -------------------------FPGA RX Interface Attributes-------------------------
+        RX_DATA_WIDTH                           =>     (20),
+
+       ---------------------------PMA Attributes----------------------------
+        OUTREFCLK_SEL_INV                       =>     ("11"),
+        PMA_RSV                                 =>     (x"00000333"),
+        PMA_RSV2                                =>     (x"00002040"),
+        PMA_RSV3                                =>     ("00"),
+        PMA_RSV4                                =>     ("0000"),
+        RX_BIAS_CFG                             =>     ("0000111100110011"),
+        DMONITOR_CFG                            =>     (x"000A00"),
+        RX_CM_SEL                               =>     ("01"),
+        RX_CM_TRIM                              =>     ("0000"),
+        RX_DEBUG_CFG                            =>     ("00000000000000"),
+        RX_OS_CFG                               =>     ("0000010000000"),
+        TERM_RCAL_CFG                           =>     ("100001000010000"),
+        TERM_RCAL_OVRD                          =>     ("000"),
+        TST_RSV                                 =>     (x"00000000"),
+        RX_CLK25_DIV                            =>     (5),
+        TX_CLK25_DIV                            =>     (5),
+        UCODEER_CLR                             =>     ('0'),
+
+       ---------------------------PCI Express Attributes----------------------------
+        PCS_PCIE_EN                             =>     ("FALSE"),
+
+       ---------------------------PCS Attributes----------------------------
+        PCS_RSVD_ATTR                           =>     (x"000000000000"),
+
+       -------------RX Buffer Attributes------------
+        RXBUF_ADDR_MODE                         =>     ("FAST"),
+        RXBUF_EIDLE_HI_CNT                      =>     ("1000"),
+        RXBUF_EIDLE_LO_CNT                      =>     ("0000"),
+        RXBUF_EN                                =>     ("TRUE"),
+        RX_BUFFER_CFG                           =>     ("000000"),
+        RXBUF_RESET_ON_CB_CHANGE                =>     ("TRUE"),
+        RXBUF_RESET_ON_COMMAALIGN               =>     ("FALSE"),
+        RXBUF_RESET_ON_EIDLE                    =>     ("FALSE"),
+        RXBUF_RESET_ON_RATE_CHANGE              =>     ("TRUE"),
+        RXBUFRESET_TIME                         =>     ("00001"),
+        RXBUF_THRESH_OVFLW                      =>     (61),
+        RXBUF_THRESH_OVRD                       =>     ("FALSE"),
+        RXBUF_THRESH_UNDFLW                     =>     (4),
+        RXDLY_CFG                               =>     (x"001F"),
+        RXDLY_LCFG                              =>     (x"030"),
+        RXDLY_TAP_CFG                           =>     (x"0000"),
+        RXPH_CFG                                =>     (x"C00002"),
+        RXPHDLY_CFG                             =>     (x"084020"),
+        RXPH_MONITOR_SEL                        =>     ("00000"),
+        RX_XCLK_SEL                             =>     ("RXREC"),
+        RX_DDI_SEL                              =>     ("000000"),
+        RX_DEFER_RESET_BUF_EN                   =>     ("TRUE"),
+
+       -----------------------CDR Attributes-------------------------
+
+       --For Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008
+
+       --For Display Port, HBR2 -   set RXCDR_CFG=72'h038c008bff20200010
+
+       --For SATA Gen1 GTX- set RXCDR_CFG=72'h03_8000_8BFF_4010_0008
+
+       --For SATA Gen2 GTX- set RXCDR_CFG=72'h03_8800_8BFF_4020_0008
+
+       --For SATA Gen3 GTX- set RXCDR_CFG=72'h03_8000_8BFF_1020_0010
+
+       --For SATA Gen3 GTP- set RXCDR_CFG=83'h0_0000_87FE_2060_2444_1010
+
+       --For SATA Gen2 GTP- set RXCDR_CFG=83'h0_0000_47FE_2060_2448_1010
+
+       --For SATA Gen1 GTP- set RXCDR_CFG=83'h0_0000_47FE_1060_2448_1010
+        RXCDR_CFG                               =>     (x"0000107FE106001041010"),
+        RXCDR_FR_RESET_ON_EIDLE                 =>     ('0'),
+        RXCDR_HOLD_DURING_EIDLE                 =>     ('0'),
+        RXCDR_PH_RESET_ON_EIDLE                 =>     ('0'),
+        RXCDR_LOCK_CFG                          =>     ("001001"),
+
+       -------------------RX Initialization and Reset Attributes-------------------
+        RXCDRFREQRESET_TIME                     =>     ("00001"),
+        RXCDRPHRESET_TIME                       =>     ("00001"),
+        RXISCANRESET_TIME                       =>     ("00001"),
+        RXPCSRESET_TIME                         =>     ("00001"),
+        RXPMARESET_TIME                         =>     ("00011"),
+
+       -------------------RX OOB Signaling Attributes-------------------
+        RXOOB_CFG                               =>     ("0000110"),
+
+       -------------------------RX Gearbox Attributes---------------------------
+        RXGEARBOX_EN                            =>     ("FALSE"),
+        GEARBOX_MODE                            =>     ("000"),
+
+       -------------------------PRBS Detection Attribute-----------------------
+        RXPRBS_ERR_LOOPBACK                     =>     ('0'),
+
+       -------------Power-Down Attributes----------
+        PD_TRANS_TIME_FROM_P2                   =>     (x"03c"),
+        PD_TRANS_TIME_NONE_P2                   =>     (x"3c"),
+        PD_TRANS_TIME_TO_P2                     =>     (x"64"),
+
+       -------------RX OOB Signaling Attributes----------
+        SAS_MAX_COM                             =>     (64),
+        SAS_MIN_COM                             =>     (36),
+        SATA_BURST_SEQ_LEN                      =>     ("0101"),
+        SATA_BURST_VAL                          =>     ("100"),
+        SATA_EIDLE_VAL                          =>     ("100"),
+        SATA_MAX_BURST                          =>     (8),
+        SATA_MAX_INIT                           =>     (21),
+        SATA_MAX_WAKE                           =>     (7),
+        SATA_MIN_BURST                          =>     (4),
+        SATA_MIN_INIT                           =>     (12),
+        SATA_MIN_WAKE                           =>     (4),
+
+       -------------RX Fabric Clock Output Control Attributes----------
+        TRANS_TIME_RATE                         =>     (x"0E"),
+
+       --------------TX Buffer Attributes----------------
+        TXBUF_EN                                =>     ("TRUE"),
+        TXBUF_RESET_ON_RATE_CHANGE              =>     ("TRUE"),
+        TXDLY_CFG                               =>     (x"001F"),
+        TXDLY_LCFG                              =>     (x"030"),
+        TXDLY_TAP_CFG                           =>     (x"0000"),
+        TXPH_CFG                                =>     (x"0780"),
+        TXPHDLY_CFG                             =>     (x"084020"),
+        TXPH_MONITOR_SEL                        =>     ("00000"),
+        TX_XCLK_SEL                             =>     ("TXOUT"),
+
+       -------------------------FPGA TX Interface Attributes-------------------------
+        TX_DATA_WIDTH                           =>     (20),
+
+       -------------------------TX Configurable Driver Attributes-------------------------
+        TX_DEEMPH0                              =>     ("000000"),
+        TX_DEEMPH1                              =>     ("000000"),
+        TX_EIDLE_ASSERT_DELAY                   =>     ("110"),
+        TX_EIDLE_DEASSERT_DELAY                 =>     ("100"),
+        TX_LOOPBACK_DRIVE_HIZ                   =>     ("FALSE"),
+        TX_MAINCURSOR_SEL                       =>     ('0'),
+        TX_DRIVE_MODE                           =>     ("DIRECT"),
+        TX_MARGIN_FULL_0                        =>     ("1001110"),
+        TX_MARGIN_FULL_1                        =>     ("1001001"),
+        TX_MARGIN_FULL_2                        =>     ("1000101"),
+        TX_MARGIN_FULL_3                        =>     ("1000010"),
+        TX_MARGIN_FULL_4                        =>     ("1000000"),
+        TX_MARGIN_LOW_0                         =>     ("1000110"),
+        TX_MARGIN_LOW_1                         =>     ("1000100"),
+        TX_MARGIN_LOW_2                         =>     ("1000010"),
+        TX_MARGIN_LOW_3                         =>     ("1000000"),
+        TX_MARGIN_LOW_4                         =>     ("1000000"),
+
+       -------------------------TX Gearbox Attributes--------------------------
+        TXGEARBOX_EN                            =>     ("FALSE"),
+
+       -------------------------TX Initialization and Reset Attributes--------------------------
+        TXPCSRESET_TIME                         =>     ("00001"),
+        TXPMARESET_TIME                         =>     ("00001"),
+
+       -------------------------TX Receiver Detection Attributes--------------------------
+        TX_RXDETECT_CFG                         =>     (x"1832"),
+        TX_RXDETECT_REF                         =>     ("100"),
+
+       ------------------ JTAG Attributes ---------------
+        ACJTAG_DEBUG_MODE                       =>     ('0'),
+        ACJTAG_MODE                             =>     ('0'),
+        ACJTAG_RESET                            =>     ('0'),
+
+       ------------------ CDR Attributes ---------------
+        CFOK_CFG                                =>     (x"49000040E80"),
+        CFOK_CFG2                               =>     ("0100000"),
+        CFOK_CFG3                               =>     ("0100000"),
+        CFOK_CFG4                               =>     ('0'),
+        CFOK_CFG5                               =>     (x"0"),
+        CFOK_CFG6                               =>     ("0000"),
+        RXOSCALRESET_TIME                       =>     ("00011"),
+        RXOSCALRESET_TIMEOUT                    =>     ("00000"),
+
+       ------------------ PMA Attributes ---------------
+        CLK_COMMON_SWING                        =>     ('0'),
+        RX_CLKMUX_EN                            =>     ('1'),
+        TX_CLKMUX_EN                            =>     ('1'),
+        ES_CLK_PHASE_SEL                        =>     ('0'),
+        USE_PCS_CLK_PHASE_SEL                   =>     ('0'),
+        PMA_RSV6                                =>     ('0'),
+        PMA_RSV7                                =>     ('0'),
+
+       ------------------ TX Configuration Driver Attributes ---------------
+        TX_PREDRIVER_MODE                       =>     ('0'),
+        PMA_RSV5                                =>     ('0'),
+        SATA_PLL_CFG                            =>     ("VCO_3000MHZ"),
+
+       ------------------ RX Fabric Clock Output Control Attributes ---------------
+        RXOUT_DIV                               =>     (4),
+
+       ------------------ TX Fabric Clock Output Control Attributes ---------------
+        TXOUT_DIV                               =>     (4),
+
+       ------------------ RX Phase Interpolator Attributes---------------
+        RXPI_CFG0                               =>     ("000"),
+        RXPI_CFG1                               =>     ('1'),
+        RXPI_CFG2                               =>     ('1'),
+
+       --------------RX Equalizer Attributes-------------
+        ADAPT_CFG0                              =>     (x"00000"),
+        RXLPMRESET_TIME                         =>     ("0001111"),
+        RXLPM_BIAS_STARTUP_DISABLE              =>     ('0'),
+        RXLPM_CFG                               =>     ("0110"),
+        RXLPM_CFG1                              =>     ('0'),
+        RXLPM_CM_CFG                            =>     ('0'),
+        RXLPM_GC_CFG                            =>     ("111100010"),
+        RXLPM_GC_CFG2                           =>     ("001"),
+        RXLPM_HF_CFG                            =>     ("00001111110000"),
+        RXLPM_HF_CFG2                           =>     ("01010"),
+        RXLPM_HF_CFG3                           =>     ("0000"),
+        RXLPM_HOLD_DURING_EIDLE                 =>     ('0'),
+        RXLPM_INCM_CFG                          =>     ('0'),
+        RXLPM_IPCM_CFG                          =>     ('1'),
+        RXLPM_LF_CFG                            =>     ("000000001111110000"),
+        RXLPM_LF_CFG2                           =>     ("01010"),
+        RXLPM_OSINT_CFG                         =>     ("100"),
+
+       ------------------ TX Phase Interpolator PPM Controller Attributes---------------
+        TXPI_CFG0                               =>     ("00"),
+        TXPI_CFG1                               =>     ("00"),
+        TXPI_CFG2                               =>     ("00"),
+        TXPI_CFG3                               =>     ('0'),
+        TXPI_CFG4                               =>     ('0'),
+        TXPI_CFG5                               =>     ("000"),
+        TXPI_GREY_SEL                           =>     ('0'),
+        TXPI_INVSTROBE_SEL                      =>     ('0'),
+        TXPI_PPMCLK_SEL                         =>     ("TXUSRCLK2"),
+        TXPI_PPM_CFG                            =>     (x"00"),
+        TXPI_SYNFREQ_PPM                        =>     ("001"),
+
+       ------------------ LOOPBACK Attributes---------------
+        LOOPBACK_CFG                            =>     ('0'),
+        PMA_LOOPBACK_CFG                        =>     ('0'),
+
+       ------------------RX OOB Signalling Attributes---------------
+        RXOOB_CLK_CFG                           =>     ("PMA"),
+
+       ------------------TX OOB Signalling Attributes---------------
+        TXOOB_CFG                               =>     ('0'),
+
+       ------------------RX Buffer Attributes---------------
+        RXSYNC_MULTILANE                        =>     ('0'),
+        RXSYNC_OVRD                             =>     ('0'),
+        RXSYNC_SKIP_DA                          =>     ('0'),
+
+       ------------------TX Buffer Attributes---------------
+        TXSYNC_MULTILANE                        =>     (TXSYNC_MULTILANE_IN),
+        TXSYNC_OVRD                             =>     (TXSYNC_OVRD_IN),
+        TXSYNC_SKIP_DA                          =>     ('0')
+
+
+    )
+    port map
+    (
+                                --------------------------------- CPLL Ports -------------------------------
+        GTRSVD                          =>      "0000000000000000",
+        PCSRSVDIN                       =>      "0000000000000000",
+        TSTIN                           =>      "11111111111111111111",
+        ---------------------------- Channel - DRP Ports  --------------------------
+        DRPADDR                         =>      drpaddr_i,
+        DRPCLK                          =>      DRPCLK_IN,
+        DRPDI                           =>      drpdi_i,
+        DRPDO                           =>      drpdo_i,
+        DRPEN                           =>      drpen_i,
+        DRPRDY                          =>      drprdy_i,
+        DRPWE                           =>      drpwe_i,
+        ------------------------------- Clocking Ports -----------------------------
+        RXSYSCLKSEL                     =>      "11",
+        TXSYSCLKSEL                     =>      "11",
+        ----------------- FPGA TX Interface Datapath Configuration  ----------------
+        TX8B10BEN                       =>      tied_to_vcc_i,
+        ------------------------ GTPE2_CHANNEL Clocking Ports ----------------------
+        PLL0CLK                         =>      PLL0CLK_IN,
+        PLL0REFCLK                      =>      PLL0REFCLK_IN,
+        PLL1CLK                         =>      PLL1CLK_IN,
+        PLL1REFCLK                      =>      PLL1REFCLK_IN,
+        ------------------------------- Loopback Ports -----------------------------
+        LOOPBACK                        =>      LOOPBACK_IN,
+        ----------------------------- PCI Express Ports ----------------------------
+        PHYSTATUS                       =>      open,
+        RXRATE                          =>      tied_to_ground_vec_i(2 downto 0),
+        RXVALID                         =>      open,
+        ----------------------------- PMA Reserved Ports ---------------------------
+        PMARSVDIN3                      =>      '0',
+        PMARSVDIN4                      =>      '0',
+        ------------------------------ Power-Down Ports ----------------------------
+        RXPD                            =>      "00",
+        TXPD                            =>      "00",
+        -------------------------- RX 8B/10B Decoder Ports -------------------------
+        SETERRSTATUS                    =>      tied_to_ground_i,
+        --------------------- RX Initialization and Reset Ports --------------------
+        EYESCANRESET                    =>      tied_to_ground_i,
+        RXUSERRDY                       =>      RXUSERRDY_IN,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        EYESCANDATAERROR                =>      EYESCANDATAERROR_OUT,
+        EYESCANMODE                     =>      tied_to_ground_i,
+        EYESCANTRIGGER                  =>      tied_to_ground_i,
+        ------------------------------- Receive Ports ------------------------------
+        CLKRSVD0                        =>      tied_to_ground_i,
+        CLKRSVD1                        =>      tied_to_ground_i,
+        DMONFIFORESET                   =>      tied_to_ground_i,
+        DMONITORCLK                     =>      tied_to_ground_i,
+        RXPMARESETDONE                  =>      rxpmaresetdone_t,
+        SIGVALIDCLK                     =>      tied_to_ground_i,
+        ------------------------- Receive Ports - CDR Ports ------------------------
+        RXCDRFREQRESET                  =>      tied_to_ground_i,
+        RXCDRHOLD                       =>      tied_to_ground_i,
+        RXCDRLOCK                       =>      open,
+        RXCDROVRDEN                     =>      tied_to_ground_i,
+        RXCDRRESET                      =>      tied_to_ground_i,
+        RXCDRRESETRSV                   =>      tied_to_ground_i,
+        RXOSCALRESET                    =>      tied_to_ground_i,
+        RXOSINTCFG                      =>      "0010",
+        RXOSINTDONE                     =>      open,
+        RXOSINTHOLD                     =>      tied_to_ground_i,
+        RXOSINTOVRDEN                   =>      tied_to_ground_i,
+        RXOSINTPD                       =>      tied_to_ground_i,
+        RXOSINTSTARTED                  =>      open,
+        RXOSINTSTROBE                   =>      tied_to_ground_i,
+        RXOSINTSTROBESTARTED            =>      open,
+        RXOSINTTESTOVRDEN               =>      tied_to_ground_i,
+        ------------------- Receive Ports - Clock Correction Ports -----------------
+        RXCLKCORCNT                     =>      open,
+        ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
+        RX8B10BEN                       =>      tied_to_vcc_i,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        RXDATA                          =>      rxdata_i,
+        RXUSRCLK                        =>      RXUSRCLK_IN,
+        RXUSRCLK2                       =>      RXUSRCLK2_IN,
+        ------------------- Receive Ports - Pattern Checker Ports ------------------
+        RXPRBSERR                       =>      open,
+        RXPRBSSEL                       =>      tied_to_ground_vec_i(2 downto 0),
+        ------------------- Receive Ports - Pattern Checker ports ------------------
+        RXPRBSCNTRESET                  =>      tied_to_ground_i,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        RXCHARISCOMMA(3 downto 2)       =>      rxchariscomma_float_i,
+        RXCHARISCOMMA(1 downto 0)       =>      RXCHARISCOMMA_OUT,
+        RXCHARISK(3 downto 2)           =>      rxcharisk_float_i,
+        RXCHARISK(1 downto 0)           =>      RXCHARISK_OUT,
+        RXDISPERR(3 downto 2)           =>      rxdisperr_float_i,
+        RXDISPERR(1 downto 0)           =>      RXDISPERR_OUT,
+        RXNOTINTABLE(3 downto 2)        =>      rxnotintable_float_i,
+        RXNOTINTABLE(1 downto 0)        =>      RXNOTINTABLE_OUT,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        GTPRXN                          =>      GTPRXN_IN,
+        GTPRXP                          =>      GTPRXP_IN,
+        PMARSVDIN2                      =>      '0',
+        PMARSVDOUT0                     =>      open,
+        PMARSVDOUT1                     =>      open,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        RXBUFRESET                      =>      tied_to_ground_i,
+        RXBUFSTATUS                     =>      open,
+        RXDDIEN                         =>      tied_to_ground_i,
+        RXDLYBYPASS                     =>      tied_to_vcc_i,
+        RXDLYEN                         =>      tied_to_ground_i,
+        RXDLYOVRDEN                     =>      tied_to_ground_i,
+        RXDLYSRESET                     =>      tied_to_ground_i,
+        RXDLYSRESETDONE                 =>      open,
+        RXPHALIGN                       =>      tied_to_ground_i,
+        RXPHALIGNDONE                   =>      open,
+        RXPHALIGNEN                     =>      tied_to_ground_i,
+        RXPHDLYPD                       =>      tied_to_ground_i,
+        RXPHDLYRESET                    =>      tied_to_ground_i,
+        RXPHMONITOR                     =>      open,
+        RXPHOVRDEN                      =>      tied_to_ground_i,
+        RXPHSLIPMONITOR                 =>      open,
+        RXSTATUS                        =>      open,
+        RXSYNCALLIN                     =>      tied_to_ground_i,
+        RXSYNCDONE                      =>      open,
+        RXSYNCIN                        =>      tied_to_ground_i,
+        RXSYNCMODE                      =>      tied_to_ground_i,
+        RXSYNCOUT                       =>      open,
+        -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+        RXBYTEISALIGNED                 =>      RXBYTEISALIGNED_OUT,
+        RXBYTEREALIGN                   =>      open,
+        RXCOMMADET                      =>      RXCOMMADET_OUT,
+        RXCOMMADETEN                    =>      tied_to_vcc_i,
+        RXMCOMMAALIGNEN                 =>      tied_to_ground_i,
+        RXPCOMMAALIGNEN                 =>      tied_to_ground_i,
+        RXSLIDE                         =>      RXSLIDE_IN,
+        ------------------ Receive Ports - RX Channel Bonding Ports ----------------
+        RXCHANBONDSEQ                   =>      open,
+        RXCHBONDEN                      =>      tied_to_ground_i,
+        RXCHBONDI                       =>      "0000",
+        RXCHBONDLEVEL                   =>      tied_to_ground_vec_i(2 downto 0),
+        RXCHBONDMASTER                  =>      tied_to_ground_i,
+        RXCHBONDO                       =>      open,
+        RXCHBONDSLAVE                   =>      tied_to_ground_i,
+        ----------------- Receive Ports - RX Channel Bonding Ports  ----------------
+        RXCHANISALIGNED                 =>      open,
+        RXCHANREALIGN                   =>      open,
+        ------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
+        DMONITOROUT                     =>      open,
+        RXADAPTSELTEST                  =>      tied_to_ground_vec_i(13 downto 0),
+        RXDFEXYDEN                      =>      tied_to_ground_i,
+        RXOSINTEN                       =>      '1',
+        RXOSINTID0                      =>      tied_to_ground_vec_i(3 downto 0),
+        RXOSINTNTRLEN                   =>      tied_to_ground_i,
+        RXOSINTSTROBEDONE               =>      open,
+        ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+        RXLPMLFOVRDEN                   =>      tied_to_ground_i,
+        RXLPMOSINTNTRLEN                =>      tied_to_ground_i,
+        -------------------- Receive Ports - RX Equailizer Ports -------------------
+        RXLPMHFHOLD                     =>      rxlpmhfhold_in,
+        RXLPMHFOVRDEN                   =>      tied_to_ground_i,
+        RXLPMLFHOLD                     =>      rxlpmlfhold_in,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        RXOSHOLD                        =>      tied_to_ground_i,
+        RXOSOVRDEN                      =>      tied_to_ground_i,
+        ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
+        RXRATEDONE                      =>      open,
+        ----------- Receive Ports - RX Fabric Clock Output Control Ports  ----------
+        RXRATEMODE                      =>      '0',
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        RXOUTCLK                        =>      RXOUTCLK_OUT,
+        RXOUTCLKFABRIC                  =>      open,
+        RXOUTCLKPCS                     =>      open,
+        RXOUTCLKSEL                     =>      "010",
+        ---------------------- Receive Ports - RX Gearbox Ports --------------------
+        RXDATAVALID                     =>      open,
+        RXHEADER                        =>      open,
+        RXHEADERVALID                   =>      open,
+        RXSTARTOFSEQ                    =>      open,
+        --------------------- Receive Ports - RX Gearbox Ports  --------------------
+        RXGEARBOXSLIP                   =>      tied_to_ground_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        GTRXRESET                       =>      gtrxreset_out,
+        RXLPMRESET                      =>      tied_to_ground_i,
+        RXOOBRESET                      =>      tied_to_ground_i,
+        RXPCSRESET                      =>      tied_to_ground_i,
+        RXPMARESET                      =>      tied_to_ground_i,
+        ------------------- Receive Ports - RX OOB Signaling ports -----------------
+        RXCOMSASDET                     =>      open,
+        RXCOMWAKEDET                    =>      open,
+        ------------------ Receive Ports - RX OOB Signaling ports  -----------------
+        RXCOMINITDET                    =>      open,
+        ------------------ Receive Ports - RX OOB signalling Ports -----------------
+        RXELECIDLE                      =>      open,
+        RXELECIDLEMODE                  =>      "11",
+        ----------------- Receive Ports - RX Polarity Control Ports ----------------
+        RXPOLARITY                      =>      tied_to_ground_i,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        RXRESETDONE                     =>      RXRESETDONE_OUT,
+        --------------------------- TX Buffer Bypass Ports -------------------------
+        TXPHDLYTSTCLK                   =>      tied_to_ground_i,
+        ------------------------ TX Configurable Driver Ports ----------------------
+        TXPOSTCURSOR                    =>      "00000",
+        TXPOSTCURSORINV                 =>      tied_to_ground_i,
+        TXPRECURSOR                     =>      tied_to_ground_vec_i(4 downto 0),
+        TXPRECURSORINV                  =>      tied_to_ground_i,
+        -------------------- TX Fabric Clock Output Control Ports ------------------
+        TXRATEMODE                      =>      tied_to_ground_i,
+        --------------------- TX Initialization and Reset Ports --------------------
+        CFGRESET                        =>      tied_to_ground_i,
+        GTTXRESET                       =>      GTTXRESET_IN,
+        PCSRSVDOUT                      =>      open,
+        TXUSERRDY                       =>      TXUSERRDY_IN,
+        ----------------- TX Phase Interpolator PPM Controller Ports ---------------
+        TXPIPPMEN                       =>      tied_to_ground_i,
+        TXPIPPMOVRDEN                   =>      tied_to_ground_i,
+        TXPIPPMPD                       =>      tied_to_ground_i,
+        TXPIPPMSEL                      =>      tied_to_vcc_i,
+        TXPIPPMSTEPSIZE                 =>      tied_to_ground_vec_i(4 downto 0),
+        ---------------------- Transceiver Reset Mode Operation --------------------
+        GTRESETSEL                      =>      tied_to_ground_i,
+        RESETOVRD                       =>      tied_to_ground_i,
+        ------------------------------- Transmit Ports -----------------------------
+        TXPMARESETDONE                  =>      open,
+        ----------------- Transmit Ports - Configurable Driver Ports ---------------
+        PMARSVDIN0                      =>      '0',
+        PMARSVDIN1                      =>      '0',
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        TXDATA                          =>      txdata_i,
+        TXUSRCLK                        =>      TXUSRCLK_IN,
+        TXUSRCLK2                       =>      TXUSRCLK2_IN,
+        --------------------- Transmit Ports - PCI Express Ports -------------------
+        TXELECIDLE                      =>      tied_to_ground_i,
+        TXMARGIN                        =>      tied_to_ground_vec_i(2 downto 0),
+        TXRATE                          =>      tied_to_ground_vec_i(2 downto 0),
+        TXSWING                         =>      tied_to_ground_i,
+        ------------------ Transmit Ports - Pattern Generator Ports ----------------
+        TXPRBSFORCEERR                  =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
+        TX8B10BBYPASS                   =>      tied_to_ground_vec_i(3 downto 0),
+        TXCHARDISPMODE                  =>      tied_to_ground_vec_i(3 downto 0),
+        TXCHARDISPVAL                   =>      tied_to_ground_vec_i(3 downto 0),
+        TXCHARISK(3 downto 2)           =>      tied_to_ground_vec_i(1 downto 0),
+        TXCHARISK(1 downto 0)           =>      TXCHARISK_IN,
+        ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+        TXDLYBYPASS                     =>      tied_to_vcc_i,
+        TXDLYEN                         =>      tied_to_ground_i,
+        TXDLYHOLD                       =>      tied_to_ground_i,
+        TXDLYOVRDEN                     =>      tied_to_ground_i,
+        TXDLYSRESET                     =>      tied_to_ground_i,
+        TXDLYSRESETDONE                 =>      open,
+        TXDLYUPDOWN                     =>      tied_to_ground_i,
+        TXPHALIGN                       =>      tied_to_ground_i,
+        TXPHALIGNDONE                   =>      open,
+        TXPHALIGNEN                     =>      tied_to_ground_i,
+        TXPHDLYPD                       =>      tied_to_ground_i,
+        TXPHDLYRESET                    =>      tied_to_ground_i,
+        TXPHINIT                        =>      tied_to_ground_i,
+        TXPHINITDONE                    =>      open,
+        TXPHOVRDEN                      =>      tied_to_ground_i,
+        ---------------------- Transmit Ports - TX Buffer Ports --------------------
+        TXBUFSTATUS                     =>      open,
+        ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
+        TXSYNCALLIN                     =>      tied_to_ground_i,
+        TXSYNCDONE                      =>      open,
+        TXSYNCIN                        =>      tied_to_ground_i,
+        TXSYNCMODE                      =>      tied_to_ground_i,
+        TXSYNCOUT                       =>      open,
+        --------------- Transmit Ports - TX Configurable Driver Ports --------------
+        GTPTXN                          =>      GTPTXN_OUT,
+        GTPTXP                          =>      GTPTXP_OUT,
+        TXBUFDIFFCTRL                   =>      "100",
+        TXDEEMPH                        =>      tied_to_ground_i,
+        TXDIFFCTRL                      =>      "1000",
+        TXDIFFPD                        =>      tied_to_ground_i,
+        TXINHIBIT                       =>      tied_to_ground_i,
+        TXMAINCURSOR                    =>      "0000000",
+        TXPISOPD                        =>      tied_to_ground_i,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        TXOUTCLK                        =>      TXOUTCLK_OUT,
+        TXOUTCLKFABRIC                  =>      TXOUTCLKFABRIC_OUT,
+        TXOUTCLKPCS                     =>      TXOUTCLKPCS_OUT,
+        TXOUTCLKSEL                     =>      "010",
+        TXRATEDONE                      =>      open,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        TXGEARBOXREADY                  =>      open,
+        TXHEADER                        =>      tied_to_ground_vec_i(2 downto 0),
+        TXSEQUENCE                      =>      tied_to_ground_vec_i(6 downto 0),
+        TXSTARTSEQ                      =>      tied_to_ground_i,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        TXPCSRESET                      =>      tied_to_ground_i,
+        TXPMARESET                      =>      tied_to_ground_i,
+        TXRESETDONE                     =>      TXRESETDONE_OUT,
+        ------------------ Transmit Ports - TX OOB signalling Ports ----------------
+        TXCOMFINISH                     =>      open,
+        TXCOMINIT                       =>      tied_to_ground_i,
+        TXCOMSAS                        =>      tied_to_ground_i,
+        TXCOMWAKE                       =>      tied_to_ground_i,
+        TXPDELECIDLEMODE                =>      tied_to_ground_i,
+        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
+        TXPOLARITY                      =>      tied_to_ground_i,
+        --------------- Transmit Ports - TX Receiver Detection Ports  --------------
+        TXDETECTRX                      =>      tied_to_ground_i,
+        ------------------ Transmit Ports - pattern Generator Ports ----------------
+        TXPRBSSEL                       =>      TXPRBSSEL_IN
+
+    );
+
+     ------------------------- Soft Fix for Production Silicon----------------------
+       gtrxreset_seq_i  : whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq 
+       port map
+            (
+        RST                             =>      RST_IN,
+        GTRXRESET_IN                    =>      GTRXRESET_IN,
+        RXPMARESETDONE                  =>      rxpmaresetdone_t,
+        GTRXRESET_OUT                   =>      gtrxreset_out,
+        DRP_OP_DONE                     =>      drp_op_done,
+        DRPCLK                          =>      DRPCLK_IN,
+        DRPEN                           =>      drpen_rst_t,
+        DRPADDR                         =>      drpaddr_rst_t,
+        DRPWE                           =>      drpwe_rst_t,
+        DRPDO                           =>      drpdo_rst_t,
+        DRPDI                           =>      drpdi_rst_t,
+        DRPRDY                          =>      drprdy_rst_t
+            ); 
+
+
+      drpen_i       <= drpen_rst_t     when drp_op_done ='0'   else
+                       drpen_pma_t     when drp_pma_busy = '1' else
+                       drpen_rate_t    when drp_rate_busy ='1' else DRPEN_IN;
+
+
+      drpaddr_i     <= drpaddr_rst_t   when drp_op_done ='0'   else
+                       drpaddr_pma_t   when drp_pma_busy = '1' else
+                       drpaddr_rate_t  when drp_rate_busy ='1' else DRPADDR_IN;
+
+
+      drpwe_i       <= drpwe_rst_t     when drp_op_done ='0'   else
+                       drpwe_pma_t     when drp_pma_busy = '1' else
+                       drpwe_rate_t    when drp_rate_busy ='1' else DRPWE_IN;
+
+
+
+      DRPDO_OUT      <=  drpdo_i when (drp_op_done='1' or drp_pma_busy='0' or drp_rate_busy='0') else x"0000";
+
+      drpdo_rst_t    <=  drpdo_i;
+
+      drpdo_pma_t    <=  drpdo_i;
+
+      drpdo_rate_t   <=  drpdo_i;
+
+
+      drpdi_i        <=  drpdi_rst_t     when drp_op_done ='0'   else
+                         drpdi_pma_t     when drp_pma_busy = '1' else
+                         drpdi_rate_t    when drp_rate_busy ='1' else DRPDI_IN;
+
+
+      DRPRDY_OUT     <=  drprdy_i when (drp_op_done='1' or drp_pma_busy='0' or drp_rate_busy='0') else '0';
+
+      drprdy_rst_t   <=  drprdy_i;
+
+      drprdy_pma_t   <=  drprdy_i;
+
+      drprdy_rate_t  <=  drprdy_i;
+
+
+   drp_pma_busy <= '0';
+   drp_rate_busy <= '0';
+
+  process (DRPCLK_IN)
+  begin
+     if(rising_edge(DRPCLK_IN)) then
+        if(drp_op_done = '0' or drp_rate_busy='1') then
+           drp_busy_i1 <= '1';
+        else
+           drp_busy_i1 <= '0';
+        end if;
+     end if;
+  end process;
+
+  process (DRPCLK_IN)
+  begin
+     if(rising_edge(DRPCLK_IN)) then
+        if(drp_op_done = '0' or drp_pma_busy='1') then
+           drp_busy_i2 <= '1';
+        else
+           drp_busy_i2 <= '0';
+        end if;
+     end if;
+  end process;
+
+    DRP_BUSY_OUT <= drp_busy_i1 or drp_busy_i2;
+
+
+
+
+ end RTL;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd
new file mode 100644
index 000000000..5fc534d53
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd
@@ -0,0 +1,342 @@
+------------------------------------------------------------------------------/
+--   ____  ____ 
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.6
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gencores_pkg.all;
+
+ENTITY whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq IS
+  port ( 
+    RST           : IN  std_logic; --Please add a synchroniser if it is not generated in DRPCLK domain.
+    GTRXRESET_IN  : IN  std_logic; --Please add a synchroniser if it is not generated in DRPCLK domain.    
+    RXPMARESETDONE: IN  std_logic;
+    GTRXRESET_OUT : OUT std_logic;
+
+    DRPCLK        : IN  std_logic;
+    DRPADDR       : OUT std_logic_vector(8 downto 0);
+    DRPDO	  : IN  std_logic_vector(15 downto 0);
+    DRPDI         : OUT std_logic_vector(15 downto 0);
+    DRPRDY        : IN  std_logic;
+    DRPEN	  : OUT std_logic;
+    DRPWE         : OUT std_logic;
+    DRP_OP_DONE   : OUT std_logic
+);
+END whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq;
+
+ARCHITECTURE Behavioral of whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq is
+
+
+--  component whiterabbit_gtpe2_channel_wrapper_sync_block
+--   generic (
+--     INITIALISE : bit_vector(5 downto 0) := "000000"
+--   );
+--   port  (
+--             clk           : in  std_logic;
+--             data_in       : in  std_logic;
+--             data_out      : out std_logic
+--          );
+--   end component;
+
+  constant DLY                : time := 1 ns;
+  type state_type is (idle,
+                      drp_rd,
+                      wait_rd_data,
+                      wr_16,
+                      wait_wr_done1,
+                      wait_pmareset,
+                      wr_20,
+                      wait_wr_done2);
+
+  signal  state               : state_type := idle;
+  signal  next_state          : state_type := idle;
+  signal  gtrxreset_s         : std_logic;
+  signal  gtrxreset_ss        : std_logic;
+  signal  rxpmaresetdone_ss   : std_logic;
+  signal  rxpmaresetdone_sss  : std_logic;
+  signal  rd_data             : std_logic_vector(15 downto 0);
+  signal  next_rd_data        : std_logic_vector(15 downto 0);
+  signal  original_rd_data        : std_logic_vector(15 downto 0);
+  signal  pmarstdone_fall_edge:std_logic;
+  signal  gtrxreset_i         :std_logic;
+  signal  flag                :std_logic := '0';
+  signal  gtrxreset_o         :std_logic;
+  signal  drpen_o             :std_logic;
+  signal  drpwe_o             :std_logic;
+  signal  drpaddr_o           :std_logic_vector(8 downto 0);
+  signal  drpdi_o             :std_logic_vector(15 downto 0);
+  signal  drp_op_done_o       :std_logic;
+  signal  rst_n               :std_logic;
+BEGIN
+
+-- sync0_RXPMARESETDONE : whiterabbit_gtpe2_channel_wrapper_sync_block
+--  port map
+--         (
+--            clk             =>  DRPCLK,
+--            data_in         =>  RXPMARESETDONE,
+--            data_out        =>  rxpmaresetdone_ss
+--         );
+
+  rst_n <= not RST;
+
+  sync0_RXPMARESETDONE : gc_sync_ffs
+  port map
+         (
+            clk_i          =>  DRPCLK,
+            rst_n_i        =>  rst_n,
+            data_i         =>  RXPMARESETDONE,
+            synced_o       =>  rxpmaresetdone_ss,
+            npulse_o       =>  open,
+            ppulse_o       =>  open
+         );
+
+--output assignment	
+  GTRXRESET_OUT <= gtrxreset_o;
+  DRPEN         <= drpen_o;
+  DRPWE         <= drpwe_o;
+  DRPADDR       <= drpaddr_o;
+  DRPDI         <= drpdi_o;
+  DRP_OP_DONE   <= drp_op_done_o;
+
+  PROCESS (DRPCLK,RST)
+  BEGIN
+    IF (RST = '1') THEN
+      state              <= idle              after DLY;
+      gtrxreset_s        <= '0'               after DLY;
+      gtrxreset_ss       <= '0'               after DLY;
+      rxpmaresetdone_sss <= '0'               after DLY;
+      rd_data            <= x"0000"           after DLY;
+      gtrxreset_o        <= '0'               after DLY;
+    ELSIF (DRPCLK'event and DRPCLK='1') THEN
+      state              <= next_state        after DLY;
+      gtrxreset_s        <= GTRXRESET_IN      after DLY;
+      gtrxreset_ss       <= gtrxreset_s       after DLY;
+      rxpmaresetdone_sss <= rxpmaresetdone_ss after DLY;
+      rd_data            <= next_rd_data      after DLY;
+      gtrxreset_o        <= gtrxreset_i       after DLY;
+    END IF;
+  END PROCESS;
+
+  PROCESS (DRPCLK,GTRXRESET_IN)
+  BEGIN
+    IF (GTRXRESET_IN = '1') THEN
+       drp_op_done_o  <= '0'       after DLY;
+
+    ELSIF (DRPCLK'event and DRPCLK='1') THEN
+      IF (state = wait_wr_done2 and DRPRDY = '1') THEN
+         drp_op_done_o  <= '1'       after DLY;
+      ELSE
+         drp_op_done_o  <= drp_op_done_o       after DLY;
+      END IF;
+    END IF;
+  END PROCESS;
+
+  pmarstdone_fall_edge <= (not rxpmaresetdone_ss) and (rxpmaresetdone_sss);
+
+  PROCESS (gtrxreset_ss,DRPRDY,state,pmarstdone_fall_edge)
+  BEGIN
+    CASE state IS
+
+      WHEN idle         =>
+        IF (gtrxreset_ss='1') THEN
+          next_state <= drp_rd;
+        ELSE
+          next_state <= idle;
+	END IF;
+
+      WHEN drp_rd       =>
+	next_state<= wait_rd_data;
+
+      WHEN wait_rd_data =>
+        IF (DRPRDY='1')THEN
+          next_state <= wr_16;
+        ELSE
+          next_state <= wait_rd_data;
+        END IF;
+
+      WHEN wr_16 => 
+	next_state <= wait_wr_done1;
+
+      WHEN wait_wr_done1 => 
+	IF (DRPRDY='1') THEN
+	  next_state <= wait_pmareset;
+        ELSE
+	  next_state <= wait_wr_done1;
+        END IF;
+
+      WHEN wait_pmareset =>
+	IF (pmarstdone_fall_edge='1') THEN
+          next_state <= wr_20;
+        ELSE
+          next_state <= wait_pmareset;
+        END IF;
+
+      WHEN wr_20         =>
+        next_state <= wait_wr_done2;
+
+      WHEN wait_wr_done2 =>
+	IF (DRPRDY='1') THEN
+          next_state <= idle;
+        ELSE
+          next_state <= wait_wr_done2;
+	END IF;
+
+      WHEN others=>
+          next_state <= idle;
+ 
+    END CASE;
+  END PROCESS;
+
+-- drives DRP interface and GTRXRESET_OUT
+  PROCESS(DRPRDY,state,rd_data,DRPDO,gtrxreset_ss,flag,original_rd_data)
+  BEGIN
+-- assert gtrxreset_out until wr to 16-bit is complete
+-- RX_DATA_WIDTH is located at addr x"0011", [13 downto 11]
+-- encoding is this : /16 = x "2", /20 = x"3", /32 = x"4", /40 = x"5"
+    gtrxreset_i  <= '0';
+    drpaddr_o    <= '0'& x"11"; -- 000010001
+    drpen_o      <= '0';
+    drpwe_o      <= '0';
+    drpdi_o      <= x"0000";
+    next_rd_data <= rd_data;
+
+    CASE state IS 
+
+     --do nothing to DRP or reset
+      WHEN idle   => null;
+
+      --assert reset and issue rd
+      WHEN drp_rd => 
+	gtrxreset_i <= '1';
+       	drpen_o     <= '1';
+	drpwe_o     <= '0';
+
+      --assert reset and wait to load rd data
+      WHEN wait_rd_data =>  
+        gtrxreset_i <= '1';
+        IF (DRPRDY='1' and flag = '0') THEN
+          next_rd_data <= DRPDO;
+        ELSIF (DRPRDY='1' and flag = '1') THEN
+          next_rd_data <= original_rd_data;
+          ELSE
+            next_rd_data <= rd_data;
+          END IF;
+
+      --assert reset and write to 16-bit mode
+      WHEN wr_16=>
+	gtrxreset_i<= '1';
+ 	drpen_o    <= '1';
+	drpwe_o    <= '1';
+        -- Addr "00001001" [11] = '0' puts width mode in /16 or /32
+       drpdi_o <= rd_data(15 downto 12) & '0' & rd_data(10 downto 0);
+       
+      --keep asserting reset until write to 16-bit mode is complete
+      WHEN wait_wr_done1=> 
+	gtrxreset_i <= '1';
+
+      --deassert reset and no DRP access until 2nd pmareset
+      WHEN wait_pmareset => null;
+          IF (gtrxreset_ss='1') THEN
+             gtrxreset_i <= '1';
+          ELSE
+             gtrxreset_i <= '0';
+          END IF;
+
+      --write to 20-bit mode
+      WHEN wr_20 =>  
+        drpen_o <='1';
+        drpwe_o <= '1';
+        drpdi_o <= rd_data(15 downto 0); --restore user setting per prev read
+
+      --wait to complete write to 20-bit mode
+      WHEN wait_wr_done2 => 
+
+
+      WHEN others        => null;  
+
+     END CASE;
+  END PROCESS;
+
+  process (DRPCLK)
+  begin
+    if (DRPCLK'event and DRPCLK='1') then
+      if( state = wr_16 or state = wait_pmareset or state = wr_20 or state = wait_wr_done1) then
+        flag <= '1';
+      elsif(state = wait_wr_done2) then
+        flag <= '0';
+      end if; 
+    end if;
+  end process;
+
+  process (DRPCLK)
+  begin
+    if (DRPCLK'event and DRPCLK='1') then
+      if( state = wait_rd_data and DRPRDY ='1' and flag = '0') then
+        original_rd_data <= DRPDO;
+      end if; 
+    end if; 
+  end process;
+
+END Behavioral;
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd
new file mode 100644
index 000000000..a075865d9
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd
@@ -0,0 +1,521 @@
+-------------------------------------------------------------------------------
+-- Title      : Deterministic Xilinx GTP wrapper - artix-7 top module
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : wr_gtp_phy_family7.vhd
+-- Author     : Peter Jansweijer, Rick Lohlefink, Tomasz Wlostowski
+-- Company    : Nikhef, CERN BE-CO-HT
+-- Created    : 2016-05-19
+-- Last update: 2016-05-19
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Dual channel wrapper for Xilinx Artix-7 GTP adapted for
+-- deterministic delays at 1.25 Gbps.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2016-05-19  0.1      PeterJ    Initial release based on "wr_gtx_phy_kintex7.vhd"
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.gencores_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+library work;
+
+use work.disparity_gen_pkg.all;
+
+entity wr_gtp_phy_family7 is
+  generic (
+    -- set to non-zero value to speed up the simulation by reducing some delays
+    g_simulation     : integer := 0
+  );
+  port (
+    -- Dedicated reference 125 MHz clock for the GTP transceiver
+    clk_gtp_i        : in   std_logic;
+
+    -- TX path, synchronous to tx_out_clk_o (62.5 MHz):
+    tx_out_clk_o     : out  std_logic;
+    tx_locked_o      : out  std_logic;
+
+    -- data input (8 bits, not 8b10b-encoded)
+    tx_data_i        : in   std_logic_vector(15 downto 0) := (others => '0');
+
+    -- 1 when tx_data_i contains a control code, 0 when it's a data byte
+    tx_k_i           : in   std_logic_vector(1 downto 0) := (others => '0');
+
+    -- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
+    -- Necessary for the PCS to generate proper frame termination sequences.
+    -- Generated for the 2nd byte (LSB) of tx_data_i.
+    tx_disparity_o   : out  std_logic;
+
+    -- Encoding error indication (1 = error, 0 = no error)
+    tx_enc_err_o     : out  std_logic;
+
+    -- RX path, synchronous to ch0_rx_rbclk_o.
+
+    -- RX recovered clock
+    rx_rbclk_o       : out  std_logic;
+
+    -- 8b10b-decoded data output. The data output must be kept invalid before
+    -- the transceiver is locked on the incoming signal to prevent the EP from
+    -- detecting a false carrier.
+    rx_data_o        : out  std_logic_vector(15 downto 0);
+
+    -- 1 when the byte on rx_data_o is a control code
+    rx_k_o           : out  std_logic_vector(1 downto 0);
+
+    -- encoding error indication
+    rx_enc_err_o     : out  std_logic;
+
+    -- RX bitslide indication, indicating the delay of the RX path of the
+    -- transceiver (in UIs). Must be valid when ch0_rx_data_o is valid.
+    rx_bitslide_o    : out  std_logic_vector(4 downto 0);
+
+    -- reset input, active hi
+    rst_i            : in   std_logic := '0';
+    loopen_i         : in   std_logic_vector(2 downto 0) := (others => '0');
+    tx_prbs_sel_i    : in   std_logic_vector(2 downto 0) := (others => '0');
+
+    pad_rxn_i        : in   std_logic := '0';
+    pad_rxp_i        : in   std_logic := '0';
+
+    pad_txn_o        : out  std_logic;
+    pad_txp_o        : out  std_logic;
+
+    rdy_o            : out  std_logic
+  );
+end entity wr_gtp_phy_family7;
+
+--------------------------------------------------------------------------------
+-- Object        : Architecture work.wr_gtp_phy_family7.structure
+-- Last modified : Mon Nov 23 12:54:18 2015.
+--------------------------------------------------------------------------------
+
+architecture structure of wr_gtp_phy_family7 is
+  constant REQ_DELAY           : integer := 500;                      -- unit = ns
+  constant CLK_PER             : integer := 8;                        -- unit = ns
+  constant INITIAL_WAIT_CYCLES : integer := REQ_DELAY / CLK_PER;      -- Required 500 ns divided by RefClk period
+  constant TOTAL_DELAY         : integer := INITIAL_WAIT_CYCLES + 10; -- Add 10 clock cycles as delay to be sure
+  
+  constant c_rxcdrlock_max     : integer := 3;
+  constant c_reset_cnt_max     : integer := 64;                       -- Reset pulse width 64 * 8 = 512 ns
+  
+  type state_type is (init, count, count_done, wait_reset);
+  signal state : state_type;
+  
+  signal rst_synced         : std_logic;
+  signal rst_int            : std_logic;
+  signal rx_rec_clk         : std_logic;
+  signal rx_rec_clk_bufin   : std_logic;
+  
+  attribute buffer_type     : string;
+  attribute buffer_type of rx_rec_clk_bufin : signal is "bufg";
+  
+  signal tx_out_clk         :    std_logic;
+  signal tx_out_clk_bufin   :    std_logic;
+  
+  --attribute buffer_type of tx_out_clk_bufin : signal is "bufg";
+  
+  signal rx_lost_lock       : std_logic;
+  signal ready_for_reset    : std_logic := '0';
+  signal serdes_ready       : std_logic := '0';
+  signal rx_slide           : std_logic := '0';
+  signal rx_rst_done        : std_logic;
+  signal tx_rst_done        : std_logic;
+  signal rx_comma_det       : std_logic;
+  signal rx_byte_is_aligned : std_logic;
+  signal forced_rx_reset    : std_logic;
+  signal rx_synced          : std_logic;
+  signal rst_done           : std_logic;
+  signal rst_done_n         : std_logic;
+  signal pll_locked_i       : std_logic;
+  signal pll_locked_n_i     : std_logic;
+  signal rx_reset           : std_logic;
+  signal rx_k_int           : std_logic_vector(1 downto 0);
+  signal rx_data_int        : std_logic_vector(15 downto 0);
+  signal rx_disp_err        : std_logic_vector(1 downto 0);
+  signal rx_code_err        : std_logic_vector(1 downto 0);
+  signal cur_disp           : t_8b10b_disparity;
+  signal tx_is_k_swapped    : std_logic_vector(1 downto 0);
+  signal tx_data_swapped    : std_logic_vector(15 downto 0);
+
+  component whiterabbit_gtpe2_channel_wrapper is
+  generic
+  (
+      -- Simulation attributes
+      EXAMPLE_SIMULATION             : integer  := 0;      -- Set to 1 for simulation
+      WRAPPER_SIM_GTRESET_SPEEDUP    : string := "FALSE" -- Set to "true" to speed up sim reset
+  );
+  port
+  (
+      --_________________________________________________________________________
+      --____________________________CHANNEL PORTS________________________________
+      GT0_DRP_BUSY_OUT         : out std_logic; 
+      ---------------------------- Channel - DRP Ports  --------------------------
+      GT0_DRPADDR_IN           : in  std_logic_vector(8 downto 0);
+      GT0_DRPCLK_IN            : in  std_logic;
+      GT0_DRPDI_IN             : in  std_logic_vector(15 downto 0);
+      GT0_DRPDO_OUT            : out std_logic_vector(15 downto 0);
+      GT0_DRPEN_IN             : in  std_logic;
+      GT0_DRPRDY_OUT           : out std_logic;
+      GT0_DRPWE_IN             : in  std_logic;
+      ------------------------------- Loopback Ports -----------------------------
+      GT0_LOOPBACK_IN          : in  std_logic_vector(2 downto 0);
+      --------------------- RX Initialization and Reset Ports --------------------
+      GT0_RXUSERRDY_IN         : in  std_logic;
+      -------------------------- RX Margin Analysis Ports ------------------------
+      GT0_EYESCANDATAERROR_OUT : out std_logic;
+      ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+      GT0_RXDATA_OUT           : out  std_logic_vector(15 downto 0);
+      GT0_RXUSRCLK_IN          : in  std_logic;
+      GT0_RXUSRCLK2_IN         : in  std_logic;
+      ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+      GT0_RXCHARISCOMMA_OUT    : out  std_logic_vector(1 downto 0);
+      GT0_RXCHARISK_OUT        : out  std_logic_vector(1 downto 0);
+      GT0_RXDISPERR_OUT        : out  std_logic_vector(1 downto 0);
+      GT0_RXNOTINTABLE_OUT     : out  std_logic_vector(1 downto 0);
+      ------------------------ Receive Ports - RX AFE Ports ----------------------
+      GT0_GTPRXN_IN            : in  std_logic;
+      GT0_GTPRXP_IN            : in  std_logic;
+      -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+      GT0_RXBYTEISALIGNED_OUT  : out  std_logic;
+      GT0_RXCOMMADET_OUT       : out  std_logic;
+      GT0_RXSLIDE_IN           : in  std_logic;
+      --------------------- Receive Ports - RX Equilizer Ports -------------------
+      GT0_RXLPMHFHOLD_IN       : in  std_logic;
+      GT0_RXLPMLFHOLD_IN       : in  std_logic;
+      --------------- Receive Ports - RX Fabric Output Control Ports -------------
+      GT0_RXOUTCLK_OUT         : out std_logic;
+      ------------- Receive Ports - RX Initialization and Reset Ports ------------
+      GT0_GTRXRESET_IN         : in  std_logic;
+      -------------- Receive Ports -RX Initialization and Reset Ports ------------
+      GT0_RXRESETDONE_OUT      : out  std_logic;
+      --------------------- TX Initialization and Reset Ports --------------------
+      GT0_GTTXRESET_IN         : in  std_logic;
+      GT0_TXUSERRDY_IN         : in  std_logic;
+      ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+      GT0_TXDATA_IN            : in  std_logic_vector(15 downto 0);
+      GT0_TXUSRCLK_IN          : in  std_logic;
+      GT0_TXUSRCLK2_IN         : in  std_logic;
+      ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
+      GT0_TXCHARISK_IN         : in  std_logic_vector(1 downto 0);
+      --------------- Transmit Ports - TX Configurable Driver Ports --------------
+      GT0_GTPTXN_OUT           : out std_logic;
+      GT0_GTPTXP_OUT           : out std_logic;
+      ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+      GT0_TXOUTCLK_OUT         : out std_logic;
+      GT0_TXOUTCLKFABRIC_OUT   : out std_logic;
+      GT0_TXOUTCLKPCS_OUT      : out std_logic;
+      ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+      GT0_TXRESETDONE_OUT      : out std_logic;
+      ------------------ Transmit Ports - pattern Generator Ports ----------------
+      GT0_TXPRBSSEL_IN         : in  std_logic_vector(2 downto 0);
+  
+  
+      --____________________________COMMON PORTS________________________________
+      ----------------- Common Block - GTPE2_COMMON Clocking Ports ---------------
+      GT0_GTREFCLK0_IN         : in  std_logic;
+      -------------------------- Common Block - PLL Ports ------------------------
+      GT0_PLL1LOCK_OUT         : out std_logic;
+      GT0_PLL1LOCKDETCLK_IN    : in  std_logic;
+      GT0_PLL1REFCLKLOST_OUT   : out std_logic;
+      GT0_PLL1RESET_IN         : in  std_logic
+  
+  
+  );
+  end component whiterabbit_gtpe2_channel_wrapper;
+  
+  component gtp_bitslide is
+  generic (
+    g_simulation             :    integer;
+    g_target                 :    string := "artix7"
+  );
+  port (
+    gtp_rst_i                : in  std_logic;
+    gtp_rx_clk_i             : in  std_logic;
+    gtp_rx_comma_det_i       : in  std_logic;
+    gtp_rx_byte_is_aligned_i : in  std_logic;
+    serdes_ready_i           : in  std_logic;
+    gtp_rx_slide_o           : out std_logic;
+    gtp_rx_cdr_rst_o         : out std_logic;
+    bitslide_o               : out std_logic_vector(4 downto 0);
+    synced_o                 : out std_logic
+  );
+  end component;
+
+  component BUFG
+    port (
+      I : in  std_ulogic;
+      O : out  std_ulogic);
+  end component BUFG;
+
+  function f_to_bool(x : integer) return string is
+    begin
+      if(x /= 0) then
+        return "TRUE";
+      else
+        return "FALSE";
+      end if;
+    end f_to_bool;
+
+begin
+
+  U_EdgeDet_rst_i : gc_sync_ffs port map (
+    clk_i    => clk_gtp_i,
+    rst_n_i    => '1',
+    data_i    => rst_i,
+    ppulse_o  => rst_synced);
+  
+  p_reset_pulse : process(clk_gtp_i, rst_synced)
+    variable reset_cnt      : integer range 0 to c_reset_cnt_max;
+  begin
+    if(rst_synced = '1') then
+      reset_cnt := 0;
+      rst_int <= '1';
+    elsif rising_edge(clk_gtp_i) then
+      if reset_cnt /= c_reset_cnt_max then
+        reset_cnt := reset_cnt + 1;
+        rst_int <= '1';
+      else
+        rst_int <= '0';
+      end if;
+    end if;
+  end process;  
+
+  -- ug482 "GTP Transceiver TX/RX Reset in Response to Completion of Configuration"
+  --   1. Wait a minimum of 500 ns after configuration is complete
+  process(clk_gtp_i, rst_int) is
+    variable reset_counter : integer range 0 to TOTAL_DELAY := 0;
+  begin
+    if rst_int = '1' then
+      state <= init;
+    elsif rising_edge(clk_gtp_i) then
+      case state is
+        when init =>
+          reset_counter := 0;
+          state <= count;
+        when count =>
+          if reset_counter = TOTAL_DELAY then
+            reset_counter := 0;
+            state <= count_done;
+          else
+            reset_counter := reset_counter + 1;
+            state <= count;
+          end if;
+        when count_done =>
+          state <= wait_reset;
+        when wait_reset =>
+          state <= wait_reset;
+      end case;
+    end if;
+  end process;
+  
+  ready_for_reset <= '1' when state = count_done else '0';
+  
+  -- 7-Series GTP RXCDRLOCK is reserved (ug482 Table 4.11) and can not be used for detection of proper RX lock.
+  -- Instead use rx_code_err (i.e. RXNOTINTABLE) to check integrity of the received characters.
+  process(rx_rec_clk, rst_int) is
+  begin
+    if rst_int = '1' then
+      rx_lost_lock <= '1';
+    elsif rising_edge(rx_rec_clk) then
+      if rx_synced = '1' then
+        if rx_code_err > "00" then
+          rx_lost_lock <= '1';
+        else
+          rx_lost_lock <= '0';
+        end if;
+      else
+        rx_lost_lock <= '0';
+      end if;
+    end if;
+  end process;
+
+  tx_enc_err_o <= '0';
+  
+  U_BUF_TxOutClk: BUFG
+    port map(
+      I => tx_out_clk_bufin,
+      O => tx_out_clk);
+
+  tx_out_clk_o <= tx_out_clk;
+  tx_locked_o <= pll_locked_i;
+    
+  U_BUF_RxRecClk: BUFG
+    port map(
+      I => rx_rec_clk_bufin,
+      O => rx_rec_clk);
+      
+  rx_rbclk_o <= rx_rec_clk;
+
+  tx_is_k_swapped <= tx_k_i(0) & tx_k_i(1);
+  tx_data_swapped <= tx_data_i(7 downto 0) & tx_data_i(15 downto 8);
+  
+  U_GTP_INST : whiterabbit_gtpe2_channel_wrapper
+  generic map
+  (
+    -- Simulation attributes
+    EXAMPLE_SIMULATION           => g_simulation,
+    WRAPPER_SIM_GTRESET_SPEEDUP  => f_to_bool(g_simulation)
+  )
+  port map
+  (
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --____________________________CHANNEL PORTS________________________________
+    GT0_DRP_BUSY_OUT         =>  open,
+    ---------------------------- Channel - DRP Ports  --------------------------
+    GT0_DRPADDR_IN           =>  (others => '0'),
+    GT0_DRPCLK_IN            =>  clk_gtp_i,
+    GT0_DRPDI_IN             =>  (others => '0'),
+    GT0_DRPDO_OUT            =>  open,
+    GT0_DRPEN_IN             =>  '0',
+    GT0_DRPRDY_OUT           =>  open,
+    GT0_DRPWE_IN             =>  '0',
+    ------------------------------- Loopback Ports -----------------------------
+    GT0_LOOPBACK_IN          =>  loopen_i,
+    --------------------- RX Initialization and Reset Ports --------------------
+    GT0_RXUSERRDY_IN         =>  pll_locked_i,
+    -------------------------- RX Margin Analysis Ports ------------------------
+    GT0_EYESCANDATAERROR_OUT =>  open,
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    GT0_RXDATA_OUT           =>  rx_data_int,
+    GT0_RXUSRCLK_IN          =>  rx_rec_clk,
+    GT0_RXUSRCLK2_IN         =>  rx_rec_clk,
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    GT0_RXCHARISCOMMA_OUT    =>  open,
+    GT0_RXCHARISK_OUT        =>  rx_k_int,
+    GT0_RXDISPERR_OUT        =>  rx_disp_err,
+    GT0_RXNOTINTABLE_OUT     =>  rx_code_err,
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    GT0_GTPRXN_IN            =>  pad_rxn_i,
+    GT0_GTPRXP_IN            =>  pad_rxp_i,
+    -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+    GT0_RXBYTEISALIGNED_OUT  =>  rx_byte_is_aligned,
+    GT0_RXCOMMADET_OUT       =>  rx_comma_det,
+    GT0_RXSLIDE_IN           =>  rx_slide,
+    --------------------- Receive Ports - RX Equilizer Ports -------------------
+    GT0_RXLPMHFHOLD_IN       =>  '0',
+    GT0_RXLPMLFHOLD_IN       =>  '0',
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    GT0_RXOUTCLK_OUT         =>  rx_rec_clk_bufin,
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    GT0_GTRXRESET_IN         =>  rx_reset,
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    GT0_RXRESETDONE_OUT      =>  rx_rst_done,
+    --------------------- TX Initialization and Reset Ports --------------------
+    GT0_GTTXRESET_IN         =>  pll_locked_n_i,
+    GT0_TXUSERRDY_IN         =>  pll_locked_i,
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    GT0_TXDATA_IN            =>  tx_data_swapped,
+    GT0_TXUSRCLK_IN          =>  tx_out_clk,
+    GT0_TXUSRCLK2_IN         =>  tx_out_clk,
+    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
+    GT0_TXCHARISK_IN         =>  tx_is_k_swapped,
+    --------------- Transmit Ports - TX Configurable Driver Ports --------------
+    GT0_GTPTXN_OUT           =>  pad_txn_o,
+    GT0_GTPTXP_OUT           =>  pad_txp_o,
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    GT0_TXOUTCLK_OUT         =>  tx_out_clk_bufin,
+    GT0_TXOUTCLKFABRIC_OUT   =>  open,
+    GT0_TXOUTCLKPCS_OUT      =>  open,
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    GT0_TXRESETDONE_OUT      =>  tx_rst_done,
+        ------------------ Transmit Ports - pattern Generator Ports ----------------
+    GT0_TXPRBSSEL_IN         =>  tx_prbs_sel_i,
+
+    --____________________________COMMON PORTS________________________________
+    ----------------- Common Block - GTPE2_COMMON Clocking Ports ---------------
+    GT0_GTREFCLK0_IN         =>  clk_gtp_i,
+    -------------------------- Common Block - PLL Ports ------------------------
+    GT0_PLL1LOCK_OUT         =>  pll_locked_i,
+    GT0_PLL1LOCKDETCLK_IN    =>  '0',
+    GT0_PLL1REFCLKLOST_OUT   =>  open,
+    GT0_PLL1RESET_IN         =>  ready_for_reset
+  );
+  
+  U_Bitslide : gtp_bitslide
+  generic map (
+    g_simulation             =>  g_simulation,
+    g_target                 =>  ("artix7")
+  )
+  port map (
+    gtp_rst_i                =>  rst_done_n,
+    gtp_rx_clk_i             =>  rx_rec_clk,
+    gtp_rx_comma_det_i       =>  rx_comma_det,
+    gtp_rx_byte_is_aligned_i =>  rx_byte_is_aligned,
+    serdes_ready_i           =>  serdes_ready,
+    gtp_rx_slide_o           =>  rx_slide,
+    gtp_rx_cdr_rst_o         =>  forced_rx_reset,
+    bitslide_o               =>  rx_bitslide_o,
+    synced_o                 =>  rx_synced
+  );
+
+  pll_locked_n_i <= not pll_locked_i;
+  serdes_ready <= not rx_lost_lock and pll_locked_i and tx_rst_done and rx_rst_done;
+  rst_done <= tx_rst_done and rx_rst_done;
+  rst_done_n <= not rst_done;
+  rx_reset <= pll_locked_n_i or forced_rx_reset;
+  rdy_o <= serdes_ready;
+
+  p_gen_rx_outputs : process(rx_rec_clk, rst_done_n)
+  begin
+    if(rst_done_n = '1') then
+      rx_data_o    <= (others => '0');
+      rx_k_o       <= (others => '0');
+      rx_enc_err_o <= '0';
+    elsif rising_edge(rx_rec_clk) then
+      if(serdes_ready = '1' and rx_synced = '1') then
+      rx_data_o    <= rx_data_int(7 downto 0) & rx_data_int(15 downto 8);
+      rx_k_o       <= rx_k_int(0) & rx_k_int(1);
+      rx_enc_err_o <= rx_disp_err(0) or rx_disp_err(1) or rx_code_err(0) or rx_code_err(1);
+      else
+      rx_data_o    <= (others => '1');
+      rx_k_o       <= (others => '1');
+      rx_enc_err_o <= '1';
+      end if;
+    end if;
+  end process;
+
+  p_gen_tx_disparity : process(tx_out_clk, rst_done_n)
+  begin
+    if rising_edge(tx_out_clk) then
+      if rst_done_n = '1' then
+      cur_disp <= RD_MINUS;
+      else
+      cur_disp <= f_next_8b10b_disparity16(cur_disp, tx_k_i, tx_data_i);
+      end if;
+    end if;
+  end process;
+
+  tx_disparity_o <= to_std_logic(cur_disp);
+end architecture structure ; -- of wr_gtp_phy_family7
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd
new file mode 100644
index 000000000..dcf8eb32d
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd
@@ -0,0 +1,803 @@
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 2.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : whiterabbit_gtxe2_channel_wrapper_gt.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module whiterabbit_gtxe2_channel_wrapper_GT (a GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***************************** Entity Declaration ****************************
+
+entity whiterabbit_gtxe2_channel_wrapper_GT is
+generic
+(
+    -- Simulation attributes
+    GT_SIM_GTRESET_SPEEDUP    : string     :=  "FALSE";        -- Set to "true" to speed up sim reset
+    RX_DFE_KL_CFG2_IN         : bit_vector :=   X"3010D90C";
+    PMA_RSV_IN                : bit_vector :=  x"00018480";
+    PCS_RSVD_ATTR_IN          : bit_vector :=   X"000000000000"
+);
+port 
+(
+    --------------------------------- CPLL Ports -------------------------------
+    CPLLFBCLKLOST_OUT                       : out  std_logic;
+    CPLLLOCK_OUT                            : out  std_logic;
+    CPLLLOCKDETCLK_IN                       : in   std_logic;
+    CPLLREFCLKLOST_OUT                      : out  std_logic;
+    CPLLRESET_IN                            : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    GTREFCLK0_IN                            : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    DRPADDR_IN                              : in   std_logic_vector(8 downto 0);
+    DRPCLK_IN                               : in   std_logic;
+    DRPDI_IN                                : in   std_logic_vector(15 downto 0);
+    DRPDO_OUT                               : out  std_logic_vector(15 downto 0);
+    DRPEN_IN                                : in   std_logic;
+    DRPRDY_OUT                              : out  std_logic;
+    DRPWE_IN                                : in   std_logic;
+    ------------------------------- Clocking Ports -----------------------------
+    QPLLCLK_IN                              : in   std_logic;
+    QPLLREFCLK_IN                           : in   std_logic;
+    ------------------------------- Loopback Ports -----------------------------
+    LOOPBACK_IN                             : in   std_logic_vector(2 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    RXUSERRDY_IN                            : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    EYESCANDATAERROR_OUT                    : out  std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+    RXCDRLOCK_OUT                           : out  std_logic;
+    RXCDRRESET_IN                           : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    RXUSRCLK_IN                             : in   std_logic;
+    RXUSRCLK2_IN                            : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    RXDATA_OUT                              : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    RXDISPERR_OUT                           : out  std_logic_vector(1 downto 0);
+    RXNOTINTABLE_OUT                        : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    GTXRXP_IN                               : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    GTXRXN_IN                               : in   std_logic;
+    -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+    RXBYTEISALIGNED_OUT                     : out  std_logic;
+    RXCOMMADET_OUT                          : out  std_logic;
+    --------------------- Receive Ports - RX Equilizer Ports -------------------
+    RXLPMHFHOLD_IN                          : in   std_logic;
+    RXLPMLFHOLD_IN                          : in   std_logic;
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    RXOUTCLK_OUT                            : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    GTRXRESET_IN                            : in   std_logic;
+    RXPMARESET_IN                           : in   std_logic;
+    ---------------------- Receive Ports - RX gearbox ports --------------------
+    RXSLIDE_IN                              : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    RXCHARISK_OUT                           : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    RXRESETDONE_OUT                         : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    GTTXRESET_IN                            : in   std_logic;
+    TXUSERRDY_IN                            : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    TXUSRCLK_IN                             : in   std_logic;
+    TXUSRCLK2_IN                            : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    TXDATA_IN                               : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    GTXTXN_OUT                              : out  std_logic;
+    GTXTXP_OUT                              : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    TXOUTCLK_OUT                            : out  std_logic;
+    TXOUTCLKFABRIC_OUT                      : out  std_logic;
+    TXOUTCLKPCS_OUT                         : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    TXCHARISK_IN                            : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    TXRESETDONE_OUT                         : out  std_logic;
+    ------------------ Transmit Ports - pattern Generator Ports ----------------
+    TXPRBSSEL_IN                            : in   std_logic_vector(2 downto 0)
+
+);
+
+
+end whiterabbit_gtxe2_channel_wrapper_GT;
+
+architecture RTL of whiterabbit_gtxe2_channel_wrapper_GT is
+    
+--**************************** Signal Declarations ****************************
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+
+
+
+    -- RX Datapath signals
+    signal rxdata_i                         :   std_logic_vector(63 downto 0);      
+    signal rxchariscomma_float_i            :   std_logic_vector(5 downto 0);
+    signal rxcharisk_float_i                :   std_logic_vector(5 downto 0);
+    signal rxdisperr_float_i                :   std_logic_vector(5 downto 0);
+    signal rxnotintable_float_i             :   std_logic_vector(5 downto 0);
+    signal rxrundisp_float_i                :   std_logic_vector(5 downto 0);
+    
+
+
+    -- TX Datapath signals
+    signal txdata_i                         :   std_logic_vector(63 downto 0);
+    signal txkerr_float_i                   :   std_logic_vector(5 downto 0);
+    signal txrundisp_float_i                :   std_logic_vector(5 downto 0);
+
+
+--******************************** Main Body of Code***************************
+                       
+begin                      
+
+    ---------------------------  Static signal Assignments ---------------------   
+
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+
+    -------------------  GT Datapath byte mapping  -----------------
+
+    RXDATA_OUT    <=   rxdata_i(15 downto 0);
+
+    txdata_i    <=   (tied_to_ground_vec_i(47 downto 0) & TXDATA_IN);
+
+
+
+    ----------------------------- GTXE2 Instance  --------------------------   
+
+    gtxe2_i :GTXE2_CHANNEL
+    generic map
+    (
+
+        --_______________________ Simulation-Only Attributes ___________________
+
+        SIM_RECEIVER_DETECT_PASS   =>      ("TRUE"),
+        SIM_RESET_SPEEDUP          =>      (GT_SIM_GTRESET_SPEEDUP),
+        SIM_TX_EIDLE_DRIVE_LEVEL   =>      ("X"),
+        SIM_CPLLREFCLK_SEL         =>      ("001"),
+        SIM_VERSION                =>      ("4.0"), 
+        
+
+       ------------------RX Byte and Word Alignment Attributes---------------
+        ALIGN_COMMA_DOUBLE                      =>     ("FALSE"),
+        ALIGN_COMMA_ENABLE                      =>     ("0001111111"),
+        ALIGN_COMMA_WORD                        =>     (2),
+        ALIGN_MCOMMA_DET                        =>     ("TRUE"),
+        ALIGN_MCOMMA_VALUE                      =>     ("1010000011"),
+        ALIGN_PCOMMA_DET                        =>     ("TRUE"),
+        ALIGN_PCOMMA_VALUE                      =>     ("0101111100"),
+        SHOW_REALIGN_COMMA                      =>     ("FALSE"),
+        RXSLIDE_AUTO_WAIT                       =>     (7),
+        RXSLIDE_MODE                            =>     ("PCS"),
+        RX_SIG_VALID_DLY                        =>     (10),
+
+       ------------------RX 8B/10B Decoder Attributes---------------
+        RX_DISPERR_SEQ_MATCH                    =>     ("TRUE"),
+        DEC_MCOMMA_DETECT                       =>     ("TRUE"),
+        DEC_PCOMMA_DETECT                       =>     ("TRUE"),
+        DEC_VALID_COMMA_ONLY                    =>     ("TRUE"),
+
+       ------------------------RX Clock Correction Attributes----------------------
+        CBCC_DATA_SOURCE_SEL                    =>     ("DECODED"),
+        CLK_COR_SEQ_2_USE                       =>     ("FALSE"),
+        CLK_COR_KEEP_IDLE                       =>     ("FALSE"),
+        CLK_COR_MAX_LAT                         =>     (10),
+        CLK_COR_MIN_LAT                         =>     (8),
+        CLK_COR_PRECEDENCE                      =>     ("TRUE"),
+        CLK_COR_REPEAT_WAIT                     =>     (0),
+        CLK_COR_SEQ_LEN                         =>     (1),
+        CLK_COR_SEQ_1_ENABLE                    =>     ("1111"),
+        CLK_COR_SEQ_1_1                         =>     ("0000000000"),
+        CLK_COR_SEQ_1_2                         =>     ("0000000000"),
+        CLK_COR_SEQ_1_3                         =>     ("0000000000"),
+        CLK_COR_SEQ_1_4                         =>     ("0000000000"),
+        CLK_CORRECT_USE                         =>     ("FALSE"),
+        CLK_COR_SEQ_2_ENABLE                    =>     ("1111"),
+        CLK_COR_SEQ_2_1                         =>     ("0000000000"),
+        CLK_COR_SEQ_2_2                         =>     ("0000000000"),
+        CLK_COR_SEQ_2_3                         =>     ("0000000000"),
+        CLK_COR_SEQ_2_4                         =>     ("0000000000"),
+
+       ------------------------RX Channel Bonding Attributes----------------------
+        CHAN_BOND_KEEP_ALIGN                    =>     ("FALSE"),
+        CHAN_BOND_MAX_SKEW                      =>     (1),
+        CHAN_BOND_SEQ_LEN                       =>     (1),
+        CHAN_BOND_SEQ_1_1                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_2                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_3                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_4                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_ENABLE                  =>     ("1111"),
+        CHAN_BOND_SEQ_2_1                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_2                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_3                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_4                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_ENABLE                  =>     ("1111"),
+        CHAN_BOND_SEQ_2_USE                     =>     ("FALSE"),
+        FTS_DESKEW_SEQ_ENABLE                   =>     ("1111"),
+        FTS_LANE_DESKEW_CFG                     =>     ("1111"),
+        FTS_LANE_DESKEW_EN                      =>     ("FALSE"),
+
+       ---------------------------RX Margin Analysis Attributes----------------------------
+        ES_CONTROL                              =>     ("000000"),
+        ES_ERRDET_EN                            =>     ("FALSE"),
+        ES_EYE_SCAN_EN                          =>     ("TRUE"),
+        ES_HORZ_OFFSET                          =>     (x"000"),
+        ES_PMA_CFG                              =>     ("0000000000"),
+        ES_PRESCALE                             =>     ("00000"),
+        ES_QUALIFIER                            =>     (x"00000000000000000000"),
+        ES_QUAL_MASK                            =>     (x"00000000000000000000"),
+        ES_SDATA_MASK                           =>     (x"00000000000000000000"),
+        ES_VERT_OFFSET                          =>     ("000000000"),
+
+       -------------------------FPGA RX Interface Attributes-------------------------
+        RX_DATA_WIDTH                           =>     (20),
+
+       ---------------------------PMA Attributes----------------------------
+        OUTREFCLK_SEL_INV                       =>     ("11"),
+        PMA_RSV                                 =>     (PMA_RSV_IN),
+        PMA_RSV2                                =>     (x"2040"),
+        PMA_RSV3                                =>     ("00"),
+        PMA_RSV4                                =>     (x"00000000"),
+        RX_BIAS_CFG                             =>     ("000000000100"),
+        DMONITOR_CFG                            =>     (x"000A00"),
+        RX_CM_SEL                               =>     ("00"),
+        RX_CM_TRIM                              =>     ("000"),
+        RX_DEBUG_CFG                            =>     ("000000000000"),
+        RX_OS_CFG                               =>     ("0000010000000"),
+        TERM_RCAL_CFG                           =>     ("10000"),
+        TERM_RCAL_OVRD                          =>     ('0'),
+        TST_RSV                                 =>     (x"00000000"),
+        RX_CLK25_DIV                            =>     (5),
+        TX_CLK25_DIV                            =>     (5),
+        UCODEER_CLR                             =>     ('0'),
+
+       ---------------------------PCI Express Attributes----------------------------
+        PCS_PCIE_EN                             =>     ("FALSE"),
+
+       ---------------------------PCS Attributes----------------------------
+        PCS_RSVD_ATTR                           =>     (PCS_RSVD_ATTR_IN),
+
+       -------------RX Buffer Attributes------------
+        RXBUF_ADDR_MODE                         =>     ("FAST"),
+        RXBUF_EIDLE_HI_CNT                      =>     ("1000"),
+        RXBUF_EIDLE_LO_CNT                      =>     ("0000"),
+        RXBUF_EN                                =>     ("TRUE"),
+        RX_BUFFER_CFG                           =>     ("000000"),
+        RXBUF_RESET_ON_CB_CHANGE                =>     ("TRUE"),
+        RXBUF_RESET_ON_COMMAALIGN               =>     ("FALSE"),
+        RXBUF_RESET_ON_EIDLE                    =>     ("FALSE"),
+        RXBUF_RESET_ON_RATE_CHANGE              =>     ("TRUE"),
+        RXBUFRESET_TIME                         =>     ("00001"),
+        RXBUF_THRESH_OVFLW                      =>     (61),
+        RXBUF_THRESH_OVRD                       =>     ("FALSE"),
+        RXBUF_THRESH_UNDFLW                     =>     (4),
+        RXDLY_CFG                               =>     (x"001F"),
+        RXDLY_LCFG                              =>     (x"030"),
+        RXDLY_TAP_CFG                           =>     (x"0000"),
+        RXPH_CFG                                =>     (x"000000"),
+        RXPHDLY_CFG                             =>     (x"084020"),
+        RXPH_MONITOR_SEL                        =>     ("00000"),
+        RX_XCLK_SEL                             =>     ("RXREC"),
+        RX_DDI_SEL                              =>     ("000000"),
+        RX_DEFER_RESET_BUF_EN                   =>     ("TRUE"),
+
+       -----------------------CDR Attributes-------------------------
+
+       --For GTX only: Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200002
+
+       --For GTX only: Display Port, HBR2 -   set RXCDR_CFG=72'h03000023ff10200020
+        RXCDR_CFG                               =>     (x"03000023ff10100020"),
+        RXCDR_FR_RESET_ON_EIDLE                 =>     ('0'),
+        RXCDR_HOLD_DURING_EIDLE                 =>     ('0'),
+        RXCDR_PH_RESET_ON_EIDLE                 =>     ('0'),
+        RXCDR_LOCK_CFG                          =>     ("010101"),
+
+       -------------------RX Initialization and Reset Attributes-------------------
+        RXCDRFREQRESET_TIME                     =>     ("00001"),
+        RXCDRPHRESET_TIME                       =>     ("00001"),
+        RXISCANRESET_TIME                       =>     ("00001"),
+        RXPCSRESET_TIME                         =>     ("00001"),
+        RXPMARESET_TIME                         =>     ("00011"),
+
+       -------------------RX OOB Signaling Attributes-------------------
+        RXOOB_CFG                               =>     ("0000110"),
+
+       -------------------------RX Gearbox Attributes---------------------------
+        RXGEARBOX_EN                            =>     ("FALSE"),
+        GEARBOX_MODE                            =>     ("000"),
+
+       -------------------------PRBS Detection Attribute-----------------------
+        RXPRBS_ERR_LOOPBACK                     =>     ('0'),
+
+       -------------Power-Down Attributes----------
+        PD_TRANS_TIME_FROM_P2                   =>     (x"03c"),
+        PD_TRANS_TIME_NONE_P2                   =>     (x"3c"),
+        PD_TRANS_TIME_TO_P2                     =>     (x"64"),
+
+       -------------RX OOB Signaling Attributes----------
+        SAS_MAX_COM                             =>     (64),
+        SAS_MIN_COM                             =>     (36),
+        SATA_BURST_SEQ_LEN                      =>     ("1111"),
+        SATA_BURST_VAL                          =>     ("100"),
+        SATA_EIDLE_VAL                          =>     ("100"),
+        SATA_MAX_BURST                          =>     (8),
+        SATA_MAX_INIT                           =>     (21),
+        SATA_MAX_WAKE                           =>     (7),
+        SATA_MIN_BURST                          =>     (4),
+        SATA_MIN_INIT                           =>     (12),
+        SATA_MIN_WAKE                           =>     (4),
+
+       -------------RX Fabric Clock Output Control Attributes----------
+        TRANS_TIME_RATE                         =>     (x"0E"),
+
+       --------------TX Buffer Attributes----------------
+        TXBUF_EN                                =>     ("TRUE"),
+        TXBUF_RESET_ON_RATE_CHANGE              =>     ("TRUE"),
+        TXDLY_CFG                               =>     (x"001F"),
+        TXDLY_LCFG                              =>     (x"030"),
+        TXDLY_TAP_CFG                           =>     (x"0000"),
+        TXPH_CFG                                =>     (x"0780"),
+        TXPHDLY_CFG                             =>     (x"084020"),
+        TXPH_MONITOR_SEL                        =>     ("00000"),
+        TX_XCLK_SEL                             =>     ("TXOUT"),
+
+       -------------------------FPGA TX Interface Attributes-------------------------
+        TX_DATA_WIDTH                           =>     (20),
+
+       -------------------------TX Configurable Driver Attributes-------------------------
+        TX_DEEMPH0                              =>     ("00000"),
+        TX_DEEMPH1                              =>     ("00000"),
+        TX_EIDLE_ASSERT_DELAY                   =>     ("110"),
+        TX_EIDLE_DEASSERT_DELAY                 =>     ("100"),
+        TX_LOOPBACK_DRIVE_HIZ                   =>     ("FALSE"),
+        TX_MAINCURSOR_SEL                       =>     ('0'),
+        TX_DRIVE_MODE                           =>     ("DIRECT"),
+        TX_MARGIN_FULL_0                        =>     ("1001110"),
+        TX_MARGIN_FULL_1                        =>     ("1001001"),
+        TX_MARGIN_FULL_2                        =>     ("1000101"),
+        TX_MARGIN_FULL_3                        =>     ("1000010"),
+        TX_MARGIN_FULL_4                        =>     ("1000000"),
+        TX_MARGIN_LOW_0                         =>     ("1000110"),
+        TX_MARGIN_LOW_1                         =>     ("1000100"),
+        TX_MARGIN_LOW_2                         =>     ("1000010"),
+        TX_MARGIN_LOW_3                         =>     ("1000000"),
+        TX_MARGIN_LOW_4                         =>     ("1000000"),
+
+       -------------------------TX Gearbox Attributes--------------------------
+        TXGEARBOX_EN                            =>     ("FALSE"),
+
+       -------------------------TX Initialization and Reset Attributes--------------------------
+        TXPCSRESET_TIME                         =>     ("00001"),
+        TXPMARESET_TIME                         =>     ("00001"),
+
+       -------------------------TX Receiver Detection Attributes--------------------------
+        TX_RXDETECT_CFG                         =>     (x"1832"),
+        TX_RXDETECT_REF                         =>     ("100"),
+
+       ----------------------------CPLL Attributes----------------------------
+        CPLL_CFG                                =>     (x"BC07DC"),
+        CPLL_FBDIV                              =>     (4),
+        CPLL_FBDIV_45                           =>     (5),
+        CPLL_INIT_CFG                           =>     (x"00001E"),
+        CPLL_LOCK_CFG                           =>     (x"01E8"),
+        CPLL_REFCLK_DIV                         =>     (1),
+        RXOUT_DIV                               =>     (4),
+        TXOUT_DIV                               =>     (4),
+        SATA_CPLL_CFG                           =>     ("VCO_3000MHZ"),
+
+       --------------RX Initialization and Reset Attributes-------------
+        RXDFELPMRESET_TIME                      =>     ("0001111"),
+
+       --------------RX Equalizer Attributes-------------
+        RXLPM_HF_CFG                            =>     ("00000011110000"),
+        RXLPM_LF_CFG                            =>     ("00000011110000"),
+        RX_DFE_GAIN_CFG                         =>     (x"020FEA"),
+        RX_DFE_H2_CFG                           =>     ("000000000000"),
+        RX_DFE_H3_CFG                           =>     ("000001000000"),
+        RX_DFE_H4_CFG                           =>     ("00011110000"),
+        RX_DFE_H5_CFG                           =>     ("00011100000"),
+        RX_DFE_KL_CFG                           =>     ("0000011111110"),
+        RX_DFE_LPM_CFG                          =>     (x"0904"),
+        RX_DFE_LPM_HOLD_DURING_EIDLE            =>     ('0'),
+        RX_DFE_UT_CFG                           =>     ("10001111000000000"),
+        RX_DFE_VP_CFG                           =>     ("00011111100000011"),
+
+       -------------------------Power-Down Attributes-------------------------
+        RX_CLKMUX_PD                            =>     ('1'),
+        TX_CLKMUX_PD                            =>     ('1'),
+
+       -------------------------FPGA RX Interface Attribute-------------------------
+        RX_INT_DATAWIDTH                        =>     (0),
+
+       -------------------------FPGA TX Interface Attribute-------------------------
+        TX_INT_DATAWIDTH                        =>     (0),
+
+       ------------------TX Configurable Driver Attributes---------------
+        TX_QPI_STATUS_EN                        =>     ('0'),
+
+       -------------------------RX Equalizer Attributes--------------------------
+        RX_DFE_KL_CFG2                          =>     (RX_DFE_KL_CFG2_IN),
+        RX_DFE_XYD_CFG                          =>     ("0000000000000"),
+
+       -------------------------TX Configurable Driver Attributes--------------------------
+        TX_PREDRIVER_MODE                       =>     ('0')
+
+
+    )
+    port map
+    (
+                      --------------------------------- CPLL Ports -------------------------------
+        CPLLFBCLKLOST                   =>      CPLLFBCLKLOST_OUT,
+        CPLLLOCK                        =>      CPLLLOCK_OUT,
+        CPLLLOCKDETCLK                  =>      CPLLLOCKDETCLK_IN,
+        CPLLLOCKEN                      =>      tied_to_vcc_i,
+        CPLLPD                          =>      tied_to_ground_i,
+        CPLLREFCLKLOST                  =>      CPLLREFCLKLOST_OUT,
+        CPLLREFCLKSEL                   =>      "001",
+        CPLLRESET                       =>      CPLLRESET_IN,
+        GTRSVD                          =>      "0000000000000000",
+        PCSRSVDIN                       =>      "0000000000000000",
+        PCSRSVDIN2                      =>      "00000",
+        PMARSVDIN                       =>      "00000",
+        PMARSVDIN2                      =>      "00000",
+        TSTIN                           =>      "11111111111111111111",
+        TSTOUT                          =>      open,
+        ---------------------------------- Channel ---------------------------------
+        CLKRSVD                         =>      "0000",
+        -------------------------- Channel - Clocking Ports ------------------------
+        GTGREFCLK                       =>      tied_to_ground_i,
+        GTNORTHREFCLK0                  =>      tied_to_ground_i,
+        GTNORTHREFCLK1                  =>      tied_to_ground_i,
+        GTREFCLK0                       =>      GTREFCLK0_IN,
+        GTREFCLK1                       =>      tied_to_ground_i,
+        GTSOUTHREFCLK0                  =>      tied_to_ground_i,
+        GTSOUTHREFCLK1                  =>      tied_to_ground_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        DRPADDR                         =>      DRPADDR_IN,
+        DRPCLK                          =>      DRPCLK_IN,
+        DRPDI                           =>      DRPDI_IN,
+        DRPDO                           =>      DRPDO_OUT,
+        DRPEN                           =>      DRPEN_IN,
+        DRPRDY                          =>      DRPRDY_OUT,
+        DRPWE                           =>      DRPWE_IN,
+        ------------------------------- Clocking Ports -----------------------------
+        GTREFCLKMONITOR                 =>      open,
+        QPLLCLK                         =>      QPLLCLK_IN,
+        QPLLREFCLK                      =>      QPLLREFCLK_IN,
+        RXSYSCLKSEL                     =>      "00",
+        TXSYSCLKSEL                     =>      "00",
+        --------------------------- Digital Monitor Ports --------------------------
+        DMONITOROUT                     =>      open,
+        ----------------- FPGA TX Interface Datapath Configuration  ----------------
+        TX8B10BEN                       =>      tied_to_vcc_i,
+        ------------------------------- Loopback Ports -----------------------------
+        LOOPBACK                        =>      LOOPBACK_IN,
+        ----------------------------- PCI Express Ports ----------------------------
+        PHYSTATUS                       =>      open,
+        RXRATE                          =>      tied_to_ground_vec_i(2 downto 0),
+        RXVALID                         =>      open,
+        ------------------------------ Power-Down Ports ----------------------------
+        RXPD                            =>      "00",
+        TXPD                            =>      "00",
+        -------------------------- RX 8B/10B Decoder Ports -------------------------
+        SETERRSTATUS                    =>      tied_to_ground_i,
+        --------------------- RX Initialization and Reset Ports --------------------
+        EYESCANRESET                    =>      tied_to_ground_i,
+        RXUSERRDY                       =>      RXUSERRDY_IN,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        EYESCANDATAERROR                =>      EYESCANDATAERROR_OUT,
+        EYESCANMODE                     =>      tied_to_ground_i,
+        EYESCANTRIGGER                  =>      tied_to_ground_i,
+        ------------------------- Receive Ports - CDR Ports ------------------------
+        RXCDRFREQRESET                  =>      tied_to_ground_i,
+        RXCDRHOLD                       =>      tied_to_ground_i,
+        RXCDRLOCK                       =>      RXCDRLOCK_OUT,
+        RXCDROVRDEN                     =>      tied_to_ground_i,
+--        RXCDRRESET                      =>      tied_to_ground_i,
+        RXCDRRESET                      =>      RXCDRRESET_IN,
+        RXCDRRESETRSV                   =>      tied_to_ground_i,
+        ------------------- Receive Ports - Clock Correction Ports -----------------
+        RXCLKCORCNT                     =>      open,
+        ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
+        RX8B10BEN                       =>      tied_to_vcc_i,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        RXUSRCLK                        =>      RXUSRCLK_IN,
+        RXUSRCLK2                       =>      RXUSRCLK2_IN,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        RXDATA                          =>      rxdata_i,
+        ------------------- Receive Ports - Pattern Checker Ports ------------------
+        RXPRBSERR                       =>      open,
+        RXPRBSSEL                       =>      tied_to_ground_vec_i(2 downto 0),
+        ------------------- Receive Ports - Pattern Checker ports ------------------
+        RXPRBSCNTRESET                  =>      tied_to_ground_i,
+        -------------------- Receive Ports - RX  Equalizer Ports -------------------
+        RXDFEXYDEN                      =>      tied_to_ground_i,
+        RXDFEXYDHOLD                    =>      tied_to_ground_i,
+        RXDFEXYDOVRDEN                  =>      tied_to_ground_i,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        RXDISPERR(7 downto 2)           =>      rxdisperr_float_i,
+        RXDISPERR(1 downto 0)           =>      RXDISPERR_OUT,
+        RXNOTINTABLE(7 downto 2)        =>      rxnotintable_float_i,
+        RXNOTINTABLE(1 downto 0)        =>      RXNOTINTABLE_OUT,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        GTXRXP                          =>      GTXRXP_IN,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        GTXRXN                          =>      GTXRXN_IN,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        RXBUFRESET                      =>      tied_to_ground_i,
+        RXBUFSTATUS                     =>      open,
+        RXDDIEN                         =>      tied_to_ground_i,
+        RXDLYBYPASS                     =>      tied_to_vcc_i,
+        RXDLYEN                         =>      tied_to_ground_i,
+        RXDLYOVRDEN                     =>      tied_to_ground_i,
+        RXDLYSRESET                     =>      tied_to_ground_i,
+        RXDLYSRESETDONE                 =>      open,
+        RXPHALIGN                       =>      tied_to_ground_i,
+        RXPHALIGNDONE                   =>      open,
+        RXPHALIGNEN                     =>      tied_to_ground_i,
+        RXPHDLYPD                       =>      tied_to_ground_i,
+        RXPHDLYRESET                    =>      tied_to_ground_i,
+        RXPHMONITOR                     =>      open,
+        RXPHOVRDEN                      =>      tied_to_ground_i,
+        RXPHSLIPMONITOR                 =>      open,
+        RXSTATUS                        =>      open,
+        -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+        RXBYTEISALIGNED                 =>      RXBYTEISALIGNED_OUT,
+        RXBYTEREALIGN                   =>      open,
+        RXCOMMADET                      =>      RXCOMMADET_OUT,
+        RXCOMMADETEN                    =>      tied_to_vcc_i,
+        RXMCOMMAALIGNEN                 =>      tied_to_ground_i,
+        RXPCOMMAALIGNEN                 =>      tied_to_ground_i,
+        ------------------ Receive Ports - RX Channel Bonding Ports ----------------
+        RXCHANBONDSEQ                   =>      open,
+        RXCHBONDEN                      =>      tied_to_ground_i,
+        RXCHBONDLEVEL                   =>      tied_to_ground_vec_i(2 downto 0),
+        RXCHBONDMASTER                  =>      tied_to_ground_i,
+        RXCHBONDO                       =>      open,
+        RXCHBONDSLAVE                   =>      tied_to_ground_i,
+        ----------------- Receive Ports - RX Channel Bonding Ports  ----------------
+        RXCHANISALIGNED                 =>      open,
+        RXCHANREALIGN                   =>      open,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        RXDFEAGCHOLD                    =>      tied_to_ground_i,
+        RXDFEAGCOVRDEN                  =>      tied_to_ground_i,
+        RXDFECM1EN                      =>      tied_to_ground_i,
+        RXDFELFHOLD                     =>      tied_to_ground_i,
+        RXDFELFOVRDEN                   =>      tied_to_ground_i,
+        RXDFELPMRESET                   =>      tied_to_ground_i,
+        RXDFETAP2HOLD                   =>      tied_to_ground_i,
+        RXDFETAP2OVRDEN                 =>      tied_to_ground_i,
+        RXDFETAP3HOLD                   =>      tied_to_ground_i,
+        RXDFETAP3OVRDEN                 =>      tied_to_ground_i,
+        RXDFETAP4HOLD                   =>      tied_to_ground_i,
+        RXDFETAP4OVRDEN                 =>      tied_to_ground_i,
+        RXDFETAP5HOLD                   =>      tied_to_ground_i,
+        RXDFETAP5OVRDEN                 =>      tied_to_ground_i,
+        RXDFEUTHOLD                     =>      tied_to_ground_i,
+        RXDFEUTOVRDEN                   =>      tied_to_ground_i,
+        RXDFEVPHOLD                     =>      tied_to_ground_i,
+        RXDFEVPOVRDEN                   =>      tied_to_ground_i,
+        RXDFEVSEN                       =>      tied_to_ground_i,
+        RXLPMLFKLOVRDEN                 =>      tied_to_ground_i,
+        RXMONITOROUT                    =>      open,
+        RXMONITORSEL                    =>      "00",
+        RXOSHOLD                        =>      tied_to_ground_i,
+        RXOSOVRDEN                      =>      tied_to_ground_i,
+        --------------------- Receive Ports - RX Equilizer Ports -------------------
+        RXLPMHFHOLD                     =>      RXLPMHFHOLD_IN,
+        RXLPMHFOVRDEN                   =>      tied_to_ground_i,
+        RXLPMLFHOLD                     =>      RXLPMLFHOLD_IN,
+        ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
+        RXRATEDONE                      =>      open,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        RXOUTCLK                        =>      RXOUTCLK_OUT,
+        RXOUTCLKFABRIC                  =>      open,
+        RXOUTCLKPCS                     =>      open,
+        RXOUTCLKSEL                     =>      "010",
+        ---------------------- Receive Ports - RX Gearbox Ports --------------------
+        RXDATAVALID                     =>      open,
+        RXHEADER                        =>      open,
+        RXHEADERVALID                   =>      open,
+        RXSTARTOFSEQ                    =>      open,
+        --------------------- Receive Ports - RX Gearbox Ports  --------------------
+        RXGEARBOXSLIP                   =>      tied_to_ground_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        GTRXRESET                       =>      GTRXRESET_IN,
+        RXOOBRESET                      =>      tied_to_ground_i,
+        RXPCSRESET                      =>      tied_to_ground_i,
+        RXPMARESET                      =>      RXPMARESET_IN,
+        ------------------ Receive Ports - RX Margin Analysis ports ----------------
+        RXLPMEN                         =>      tied_to_vcc_i,
+        ------------------- Receive Ports - RX OOB Signaling ports -----------------
+        RXCOMSASDET                     =>      open,
+        RXCOMWAKEDET                    =>      open,
+        ------------------ Receive Ports - RX OOB Signaling ports  -----------------
+        RXCOMINITDET                    =>      open,
+        ------------------ Receive Ports - RX OOB signalling Ports -----------------
+        RXELECIDLE                      =>      open,
+        RXELECIDLEMODE                  =>      "11",
+        ----------------- Receive Ports - RX Polarity Control Ports ----------------
+        RXPOLARITY                      =>      tied_to_ground_i,
+        ---------------------- Receive Ports - RX gearbox ports --------------------
+        RXSLIDE                         =>      RXSLIDE_IN,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        RXCHARISCOMMA                   =>      open,
+        RXCHARISK(7 downto 2)           =>      rxcharisk_float_i,
+        RXCHARISK(1 downto 0)           =>      RXCHARISK_OUT,
+        ------------------ Receive Ports - Rx Channel Bonding Ports ----------------
+        RXCHBONDI                       =>      "00000",
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        RXRESETDONE                     =>      RXRESETDONE_OUT,
+        -------------------------------- Rx AFE Ports ------------------------------
+        RXQPIEN                         =>      tied_to_ground_i,
+        RXQPISENN                       =>      open,
+        RXQPISENP                       =>      open,
+        --------------------------- TX Buffer Bypass Ports -------------------------
+        TXPHDLYTSTCLK                   =>      tied_to_ground_i,
+        ------------------------ TX Configurable Driver Ports ----------------------
+        TXPOSTCURSOR                    =>      "00000",
+        TXPOSTCURSORINV                 =>      tied_to_ground_i,
+        TXPRECURSOR                     =>      tied_to_ground_vec_i(4 downto 0),
+        TXPRECURSORINV                  =>      tied_to_ground_i,
+        TXQPIBIASEN                     =>      tied_to_ground_i,
+        TXQPISTRONGPDOWN                =>      tied_to_ground_i,
+        TXQPIWEAKPUP                    =>      tied_to_ground_i,
+        --------------------- TX Initialization and Reset Ports --------------------
+        CFGRESET                        =>      tied_to_ground_i,
+        GTTXRESET                       =>      GTTXRESET_IN,
+        PCSRSVDOUT                      =>      open,
+        TXUSERRDY                       =>      TXUSERRDY_IN,
+        ---------------------- Transceiver Reset Mode Operation --------------------
+        GTRESETSEL                      =>      tied_to_ground_i,
+        RESETOVRD                       =>      tied_to_ground_i,
+        ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+        TXCHARDISPMODE                  =>      tied_to_ground_vec_i(7 downto 0),
+        TXCHARDISPVAL                   =>      tied_to_ground_vec_i(7 downto 0),
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        TXUSRCLK                        =>      TXUSRCLK_IN,
+        TXUSRCLK2                       =>      TXUSRCLK2_IN,
+        --------------------- Transmit Ports - PCI Express Ports -------------------
+        TXELECIDLE                      =>      tied_to_ground_i,
+        TXMARGIN                        =>      tied_to_ground_vec_i(2 downto 0),
+        TXRATE                          =>      tied_to_ground_vec_i(2 downto 0),
+        TXSWING                         =>      tied_to_ground_i,
+        ------------------ Transmit Ports - Pattern Generator Ports ----------------
+        TXPRBSFORCEERR                  =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+        TXDLYBYPASS                     =>      tied_to_vcc_i,
+        TXDLYEN                         =>      tied_to_ground_i,
+        TXDLYHOLD                       =>      tied_to_ground_i,
+        TXDLYOVRDEN                     =>      tied_to_ground_i,
+        TXDLYSRESET                     =>      tied_to_ground_i,
+        TXDLYSRESETDONE                 =>      open,
+        TXDLYUPDOWN                     =>      tied_to_ground_i,
+        TXPHALIGN                       =>      tied_to_ground_i,
+        TXPHALIGNDONE                   =>      open,
+        TXPHALIGNEN                     =>      tied_to_ground_i,
+        TXPHDLYPD                       =>      tied_to_ground_i,
+        TXPHDLYRESET                    =>      tied_to_ground_i,
+        TXPHINIT                        =>      tied_to_ground_i,
+        TXPHINITDONE                    =>      open,
+        TXPHOVRDEN                      =>      tied_to_ground_i,
+        ---------------------- Transmit Ports - TX Buffer Ports --------------------
+        TXBUFSTATUS                     =>      open,
+        --------------- Transmit Ports - TX Configurable Driver Ports --------------
+        TXBUFDIFFCTRL                   =>      "100",
+        TXDEEMPH                        =>      tied_to_ground_i,
+        TXDIFFCTRL                      =>      "1000",
+        TXDIFFPD                        =>      tied_to_ground_i,
+        TXINHIBIT                       =>      tied_to_ground_i,
+        TXMAINCURSOR                    =>      "0000000",
+        TXPISOPD                        =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        TXDATA                          =>      txdata_i,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        GTXTXN                          =>      GTXTXN_OUT,
+        GTXTXP                          =>      GTXTXP_OUT,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        TXOUTCLK                        =>      TXOUTCLK_OUT,
+        TXOUTCLKFABRIC                  =>      TXOUTCLKFABRIC_OUT,
+        TXOUTCLKPCS                     =>      TXOUTCLKPCS_OUT,
+        TXOUTCLKSEL                     =>      "010",
+        TXRATEDONE                      =>      open,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        TXCHARISK(7 downto 2)           =>      tied_to_ground_vec_i(5 downto 0),
+        TXCHARISK(1 downto 0)           =>      TXCHARISK_IN,
+        TXGEARBOXREADY                  =>      open,
+        TXHEADER                        =>      tied_to_ground_vec_i(2 downto 0),
+        TXSEQUENCE                      =>      tied_to_ground_vec_i(6 downto 0),
+        TXSTARTSEQ                      =>      tied_to_ground_i,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        TXPCSRESET                      =>      tied_to_ground_i,
+        TXPMARESET                      =>      tied_to_ground_i,
+        TXRESETDONE                     =>      TXRESETDONE_OUT,
+        ------------------ Transmit Ports - TX OOB signalling Ports ----------------
+        TXCOMFINISH                     =>      open,
+        TXCOMINIT                       =>      tied_to_ground_i,
+        TXCOMSAS                        =>      tied_to_ground_i,
+        TXCOMWAKE                       =>      tied_to_ground_i,
+        TXPDELECIDLEMODE                =>      tied_to_ground_i,
+        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
+        TXPOLARITY                      =>      tied_to_ground_i,
+        --------------- Transmit Ports - TX Receiver Detection Ports  --------------
+        TXDETECTRX                      =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX8b/10b Encoder Ports -----------------
+        TX8B10BBYPASS                   =>      tied_to_ground_vec_i(7 downto 0),
+        ------------------ Transmit Ports - pattern Generator Ports ----------------
+        TXPRBSSEL                       =>      TXPRBSSEL_IN,
+        ----------------------- Tx Configurable Driver  Ports ----------------------
+        TXQPISENN                       =>      open,
+        TXQPISENP                       =>      open
+
+    );
+ 
+ end RTL;
+
+
+ 
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd
new file mode 100644
index 000000000..bc1249fa1
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd
@@ -0,0 +1,505 @@
+-------------------------------------------------------------------------------
+-- Title      : Deterministic Xilinx GTX wrapper - kintex-7 top module
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : wr_gtx_phy_family7.vhd
+-- Author     : Peter Jansweijer, Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2013-04-08
+-- Last update: 2013-04-08
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Dual channel wrapper for Xilinx Kintex-7 GTX adapted for
+-- deterministic delays at 1.25 Gbps.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2013-04-08  0.1      PeterJ    Initial release based on "wr_gtx_phy_virtex6.vhd"
+-- 2013-08-19  0.2      PeterJ    Implemented a small delay before a rx_cdr_lock is propgated
+-- 2014-02_19  0.3      Peterj    Added tx_locked_o to indicate that the cpll reached the lock status
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.gencores_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+library work;
+--use work.gencores_pkg.all;
+use work.disparity_gen_pkg.all;
+
+entity wr_gtx_phy_family7 is
+
+  generic (
+    -- set to non-zero value to speed up the simulation by reducing some delays
+    g_simulation         : integer := 0
+    );
+
+  port (
+    -- Dedicated reference 125 MHz clock for the GTX transceiver
+    clk_gtx_i : in std_logic;
+
+    -- TX path, synchronous to tx_out_clk_o (62.5 MHz):
+    tx_out_clk_o : out std_logic;
+    tx_locked_o  : out std_logic;
+
+    -- data input (8 bits, not 8b10b-encoded)
+    tx_data_i : in std_logic_vector(15 downto 0);
+
+    -- 1 when tx_data_i contains a control code, 0 when it's a data byte
+    tx_k_i : in std_logic_vector(1 downto 0);
+
+    -- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
+    -- Necessary for the PCS to generate proper frame termination sequences.
+    -- Generated for the 2nd byte (LSB) of tx_data_i.
+    tx_disparity_o : out std_logic;
+
+    -- Encoding error indication (1 = error, 0 = no error)
+    tx_enc_err_o : out std_logic;
+
+    -- RX path, synchronous to ch0_rx_rbclk_o.
+
+    -- RX recovered clock
+    rx_rbclk_o : out std_logic;
+
+    -- 8b10b-decoded data output. The data output must be kept invalid before
+    -- the transceiver is locked on the incoming signal to prevent the EP from
+    -- detecting a false carrier.
+    rx_data_o : out std_logic_vector(15 downto 0);
+
+    -- 1 when the byte on rx_data_o is a control code
+    rx_k_o : out std_logic_vector(1 downto 0);
+
+    -- encoding error indication
+    rx_enc_err_o : out std_logic;
+
+    -- RX bitslide indication, indicating the delay of the RX path of the
+    -- transceiver (in UIs). Must be valid when ch0_rx_data_o is valid.
+    rx_bitslide_o : out std_logic_vector(4 downto 0);
+
+    -- reset input, active hi
+    rst_i         : in std_logic;
+    loopen_i      : in std_logic_vector(2 downto 0);
+    tx_prbs_sel_i : in std_logic_vector(2 downto 0);
+    pad_txn_o : out std_logic;
+    pad_txp_o : out std_logic;
+
+    pad_rxn_i : in std_logic := '0';
+    pad_rxp_i : in std_logic := '0';
+
+    rdy_o     : out std_logic);
+end wr_gtx_phy_family7;
+
+architecture rtl of wr_gtx_phy_family7 is
+
+  component WHITERABBIT_GTXE2_CHANNEL_WRAPPER_GT is
+    generic
+    (
+        -- Simulation attributes
+        GT_SIM_GTRESET_SPEEDUP    : string     :=  "TRUE";        -- Set to "TRUE" to speed up sim reset (Need Capital Letters!)
+        RX_DFE_KL_CFG2_IN         : bit_vector :=   X"3010D90C";
+        PMA_RSV_IN                : bit_vector :=   X"00018480";
+        PCS_RSVD_ATTR_IN          : bit_vector :=   X"000000000000"
+    );
+    port 
+    (
+    --------------------------------- CPLL Ports -------------------------------
+    CPLLFBCLKLOST_OUT                       : out  std_logic;
+    CPLLLOCK_OUT                            : out  std_logic;
+    CPLLLOCKDETCLK_IN                       : in   std_logic;
+    CPLLREFCLKLOST_OUT                      : out  std_logic;
+    CPLLRESET_IN                            : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    GTREFCLK0_IN                            : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    DRPADDR_IN                              : in   std_logic_vector(8 downto 0);
+    DRPCLK_IN                               : in   std_logic;
+    DRPDI_IN                                : in   std_logic_vector(15 downto 0);
+    DRPDO_OUT                               : out  std_logic_vector(15 downto 0);
+    DRPEN_IN                                : in   std_logic;
+    DRPRDY_OUT                              : out  std_logic;
+    DRPWE_IN                                : in   std_logic;
+    ------------------------------- Clocking Ports -----------------------------
+    QPLLCLK_IN                              : in   std_logic;
+    QPLLREFCLK_IN                           : in   std_logic;
+    ------------------------------- Loopback Ports -----------------------------
+    LOOPBACK_IN                             : in   std_logic_vector(2 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    RXUSERRDY_IN                            : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    EYESCANDATAERROR_OUT                    : out  std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+    RXCDRLOCK_OUT                           : out  std_logic;
+    RXCDRRESET_IN                           : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    RXUSRCLK_IN                             : in   std_logic;
+    RXUSRCLK2_IN                            : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    RXDATA_OUT                              : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    RXDISPERR_OUT                           : out  std_logic_vector(1 downto 0);
+    RXNOTINTABLE_OUT                        : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    GTXRXP_IN                               : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    GTXRXN_IN                               : in   std_logic;
+    -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+    RXBYTEISALIGNED_OUT                     : out  std_logic;
+    RXCOMMADET_OUT                          : out  std_logic;
+    --------------------- Receive Ports - RX Equilizer Ports -------------------
+    RXLPMHFHOLD_IN                          : in   std_logic;
+    RXLPMLFHOLD_IN                          : in   std_logic;
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    RXOUTCLK_OUT                            : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    GTRXRESET_IN                            : in   std_logic;
+    RXPMARESET_IN                           : in   std_logic;
+    ---------------------- Receive Ports - RX gearbox ports --------------------
+    RXSLIDE_IN                              : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    RXCHARISK_OUT                           : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    RXRESETDONE_OUT                         : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    GTTXRESET_IN                            : in   std_logic;
+    TXUSERRDY_IN                            : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    TXUSRCLK_IN                             : in   std_logic;
+    TXUSRCLK2_IN                            : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    TXDATA_IN                               : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    GTXTXN_OUT                              : out  std_logic;
+    GTXTXP_OUT                              : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    TXOUTCLK_OUT                            : out  std_logic;
+    TXOUTCLKFABRIC_OUT                      : out  std_logic;
+    TXOUTCLKPCS_OUT                         : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    TXCHARISK_IN                            : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    TXRESETDONE_OUT                         : out  std_logic;
+    ------------------ Transmit Ports - pattern Generator Ports ----------------
+    TXPRBSSEL_IN                            : in   std_logic_vector(2 downto 0)
+	);
+  end component WHITERABBIT_GTXE2_CHANNEL_WRAPPER_GT;
+
+  component BUFG
+    port (
+      O : out std_ulogic;
+      I : in  std_ulogic);
+  end component;
+
+  component gtp_bitslide
+    generic (
+      g_simulation : integer;
+      g_target     : string := "virtex6");
+    port (
+      gtp_rst_i                : in  std_logic;
+      gtp_rx_clk_i             : in  std_logic;
+      gtp_rx_comma_det_i       : in  std_logic;
+      gtp_rx_byte_is_aligned_i : in  std_logic;
+      serdes_ready_i           : in  std_logic;
+      gtp_rx_slide_o           : out std_logic;
+      gtp_rx_cdr_rst_o         : out std_logic;
+      bitslide_o               : out std_logic_vector(4 downto 0);
+      synced_o                 : out std_logic);
+  end component;
+
+  constant c_rxcdrlock_max            : integer := 3;
+  constant c_reset_cnt_max            : integer := 64;	-- Reset pulse width 64 * 8 = 512 ns
+  
+  signal rst_synced                   : std_logic;
+  signal rst_int                      : std_logic;
+--  signal trig0, trig1, trig2, trig3   : std_logic_vector(31 downto 0);
+
+  signal rx_rec_clk_bufin             : std_logic;
+  signal rx_rec_clk                   : std_logic;
+  signal tx_out_clk_bufin             : std_logic;
+  signal tx_out_clk                   : std_logic;
+  signal rx_cdr_lock                  : std_logic;
+  signal rx_cdr_lock_filtered         : std_logic;
+
+  signal tx_rst_done, rx_rst_done     : std_logic;
+  signal txpll_lockdet, rxpll_lockdet : std_logic;
+  signal pll_lockdet                  : std_logic;
+  signal cpll_lockdet                 : std_logic;
+  signal gtreset                      : std_logic;
+
+  signal rx_comma_det                 : std_logic;
+  signal rx_byte_is_aligned           : std_logic;
+
+  signal everything_ready             : std_logic;
+  signal rx_slide                     : std_logic;
+  signal rx_cdr_rst                   : std_logic;
+  signal rx_synced                    : std_logic;
+  signal rst_done                     : std_logic;
+  signal rst_done_n                   : std_logic;
+ 
+  signal rx_k_int                     : std_logic_vector(1 downto 0);
+  signal rx_data_int                  : std_logic_vector(15 downto 0);
+
+  signal rx_disp_err, rx_code_err     : std_logic_vector(1 downto 0);
+
+  signal tx_is_k_swapped              : std_logic_vector(1 downto 0);
+  signal tx_data_swapped              : std_logic_vector(15 downto 0);
+
+  signal cur_disp                     : t_8b10b_disparity;
+
+begin  -- rtl
+
+  -- There is a hen and egg problem with the reset in wr_core. Some reset signals are
+  -- synchronized by rx_rbclk_o but this signal is de-asserted by the same reset.
+  -- Therefore the rst_i is made edge sensitive and an internal reset pulse is generated for the PHY.
+  -- After this reset pulse signal rx_rbclk_o starts clocking again and the (still asserted) system
+  -- wide reset signal can by synchronized with this clock.
+
+  -- Note that the rst_i originates from the clk_sys domain. Synchronisation is not needed
+  -- when the clk_sys is phase locked with clk_gtx_i (which is usually the case) but is a safety
+  -- measure. Add a false path for U_EdgeDet_rst_i_reg_sync0 to the timing constraints.
+  U_EdgeDet_rst_i : gc_sync_ffs port map (
+    clk_i    => clk_gtx_i,
+    rst_n_i  => '1',
+    data_i   => rst_i,
+    ppulse_o => rst_synced);
+
+  p_reset_pulse : process(clk_gtx_i, rst_synced)
+    variable reset_cnt      : integer range 0 to c_reset_cnt_max;
+  begin
+    if(rst_synced = '1') then
+      reset_cnt := 0;
+      rst_int <= '1';
+    elsif rising_edge(clk_gtx_i) then
+      if reset_cnt /= c_reset_cnt_max then
+        reset_cnt := reset_cnt + 1;
+		rst_int <= '1';
+      else
+        rst_int <= '0';
+      end if;
+    end if;
+  end process;  
+
+  tx_enc_err_o <= '0';
+
+  U_BUF_TxOutClk : BUFG
+    port map (
+      I => tx_out_clk_bufin,
+      O => tx_out_clk);
+
+   tx_out_clk_o <= tx_out_clk;
+   tx_locked_o  <= cpll_lockdet;
+
+      U_BUF_RxRecClk : BUFG
+    port map (
+      I => rx_rec_clk_bufin,
+      O => rx_rec_clk);
+
+  rx_rbclk_o <= rx_rec_clk;
+    
+  tx_is_k_swapped <= tx_k_i(0) & tx_k_i(1);
+  tx_data_swapped <= tx_data_i(7 downto 0) & tx_data_i(15 downto 8);
+  
+U_GTX_INST : WHITERABBIT_GTXE2_CHANNEL_WRAPPER_GT
+    generic map
+    (
+       -- Simulation attributes
+       GT_SIM_GTRESET_SPEEDUP    =>  "TRUE"        -- Set to "true" to speed up sim reset
+    )
+    port map
+    (
+		--------------------------------- CPLL Ports -------------------------------
+		CPLLFBCLKLOST_OUT          => open,
+		CPLLLOCK_OUT               => cpll_lockdet,
+		CPLLLOCKDETCLK_IN          => '0',
+		CPLLREFCLKLOST_OUT         => open,
+		CPLLRESET_IN               => rst_int,
+		-------------------------- Channel - Clocking Ports ------------------------
+		GTREFCLK0_IN               => clk_gtx_i,
+		---------------------------- Channel - DRP Ports  --------------------------
+		DRPADDR_IN                 => (Others => '0'),
+		DRPCLK_IN                  => '0',
+		DRPDI_IN                   => (Others => '0'),
+		DRPDO_OUT                  => open,
+		DRPEN_IN                   => '0',
+		DRPRDY_OUT                 => open,
+		DRPWE_IN                   => '0',
+		------------------------------- Clocking Ports -----------------------------
+		QPLLCLK_IN                 => '0',
+		QPLLREFCLK_IN              => '0',
+		------------------------------- Loopback Ports -----------------------------
+		LOOPBACK_IN                => loopen_i,
+		--------------------- RX Initialization and Reset Ports --------------------
+--		RXUSERRDY_IN               => rx_cdr_lock,
+		RXUSERRDY_IN               => rx_cdr_lock_filtered,
+		-------------------------- RX Margin Analysis Ports ------------------------
+		EYESCANDATAERROR_OUT       => open,
+		------------------------- Receive Ports - CDR Ports ------------------------
+		RXCDRLOCK_OUT              => rx_cdr_lock,
+		RXCDRRESET_IN              => rx_cdr_rst,   -- this port cannot be generated by the CoreGen GUI, it cannot be turnes "on"                           : in   std_logic;
+		------------------ Receive Ports - FPGA RX Interface Ports -----------------
+		RXUSRCLK_IN                => rx_rec_clk,
+		RXUSRCLK2_IN               => rx_rec_clk,
+		------------------ Receive Ports - FPGA RX interface Ports -----------------
+		RXDATA_OUT                 => rx_data_int,
+		------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+		RXDISPERR_OUT              => rx_disp_err,
+		RXNOTINTABLE_OUT           => rx_code_err,
+		--------------------------- Receive Ports - RX AFE -------------------------
+		GTXRXP_IN                  => pad_rxp_i,
+		------------------------ Receive Ports - RX AFE Ports ----------------------
+		GTXRXN_IN                  => pad_rxn_i,
+		-------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+		RXBYTEISALIGNED_OUT        => rx_byte_is_aligned,
+		RXCOMMADET_OUT             => rx_comma_det,
+		--------------------- Receive Ports - RX Equilizer Ports -------------------
+		RXLPMHFHOLD_IN             => '0',          -- this port is always generated by the CoreGen GUI and cannot be turned "off"
+		RXLPMLFHOLD_IN             => '0',          -- this port is always generated by the CoreGen GUI and cannot be turned "off"
+		--------------- Receive Ports - RX Fabric Output Control Ports -------------
+		RXOUTCLK_OUT               => rx_rec_clk_bufin,
+		------------- Receive Ports - RX Initialization and Reset Ports ------------
+		GTRXRESET_IN               => gtreset,
+		RXPMARESET_IN              => '0',
+		---------------------- Receive Ports - RX gearbox ports --------------------
+		RXSLIDE_IN                 => rx_slide,
+		------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+		RXCHARISK_OUT              => rx_k_int,
+		-------------- Receive Ports -RX Initialization and Reset Ports ------------
+		RXRESETDONE_OUT            => rx_rst_done,
+		--------------------- TX Initialization and Reset Ports --------------------
+		GTTXRESET_IN               => gtreset,
+		TXUSERRDY_IN               => cpll_lockdet,
+		------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+		TXUSRCLK_IN                => tx_out_clk,
+		TXUSRCLK2_IN               => tx_out_clk,
+		------------------ Transmit Ports - TX Data Path interface -----------------
+		TXDATA_IN                  => tx_data_swapped,
+--       TXDATA_IN                  => tx_data_i,
+		---------------- Transmit Ports - TX Driver and OOB signaling --------------
+		GTXTXN_OUT                 => pad_txn_o,
+		GTXTXP_OUT                 => pad_txp_o,
+		----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+		TXOUTCLK_OUT               => tx_out_clk_bufin,
+		TXOUTCLKFABRIC_OUT         => open,
+		TXOUTCLKPCS_OUT            => open,
+		--------------------- Transmit Ports - TX Gearbox Ports --------------------
+		TXCHARISK_IN               => tx_is_k_swapped,
+--       TXCHARISK_IN               => tx_k_i,
+		------------- Transmit Ports - TX Initialization and Reset Ports -----------
+		TXRESETDONE_OUT            => tx_rst_done,
+                ------------------ Transmit Ports - pattern Generator Ports ----------------
+    TXPRBSSEL_IN               => tx_prbs_sel_i
+    );
+
+  U_Bitslide : gtp_bitslide
+    generic map (
+      g_simulation => g_simulation,
+      g_target     => "kintex7")
+    port map (
+      gtp_rst_i                => rst_done_n,
+      gtp_rx_clk_i             => rx_rec_clk,
+      gtp_rx_comma_det_i       => rx_comma_det,
+      gtp_rx_byte_is_aligned_i => rx_byte_is_aligned,
+      serdes_ready_i           => everything_ready,
+      gtp_rx_slide_o           => rx_slide,
+      gtp_rx_cdr_rst_o         => rx_cdr_rst,
+      bitslide_o               => rx_bitslide_o,
+      synced_o                 => rx_synced);
+
+  txpll_lockdet    <= cpll_lockdet;
+--  rxpll_lockdet    <= rx_cdr_lock;
+  rxpll_lockdet    <= rx_cdr_lock_filtered;
+  gtreset          <= not cpll_lockdet;
+  rst_done         <= rx_rst_done and tx_rst_done;
+  rst_done_n       <= not rst_done;
+  pll_lockdet      <= txpll_lockdet and rxpll_lockdet;
+  everything_ready <= rst_done and pll_lockdet;
+  rdy_o            <= everything_ready;
+
+--  trig2(3) <= rx_rst_done;
+--  trig2(4) <= tx_rst_done;
+--  trig2(5) <= txpll_lockdet;
+--  trig2(6) <= rxpll_lockdet;
+--  trig2(7) <= '1';
+
+  -- 2013 August 19: Peterj
+  -- The family 7 GTX seem to have an artifact in rx_cdr_lock. For no reason lock may be lost for a clock cycle
+  -- There is not much information on the web but examples of "Series-7 Integrated Block for PCI Express" (pipe_user.v)
+  -- show that Xilinx itself implements a small delay before an rx_cdr_lock is propagated.
+  p_rx_cdr_lock_filter : process(rx_rec_clk, rst_int)
+    variable rxcdrlock_cnt      : integer range 0 to c_rxcdrlock_max;
+  begin
+    if(rst_int = '1') then  
+      rxcdrlock_cnt := 0;
+      rx_cdr_lock_filtered <= '0';
+    elsif rising_edge(rx_rec_clk) then
+      if rx_cdr_lock = '0' then
+        if rxcdrlock_cnt /= c_rxcdrlock_max then
+           rxcdrlock_cnt := rxcdrlock_cnt + 1;
+        else
+           rx_cdr_lock_filtered <= '0';
+        end if;
+      else
+        rxcdrlock_cnt := 0;
+        rx_cdr_lock_filtered <= '1';
+      end if;
+    end if;
+  end process;
+
+  p_gen_rx_outputs : process(rx_rec_clk, rst_done_n)
+  begin
+    if(rst_done_n = '1') then
+      rx_data_o    <= (others => '0');
+      rx_k_o       <= (others => '0');
+      rx_enc_err_o <= '0';
+    elsif rising_edge(rx_rec_clk) then
+      if(everything_ready = '1' and rx_synced = '1') then
+        rx_data_o    <= rx_data_int(7 downto 0) & rx_data_int(15 downto 8);
+        rx_k_o       <= rx_k_int(0) & rx_k_int(1);
+        rx_enc_err_o <= rx_disp_err(0) or rx_disp_err(1) or rx_code_err(0) or rx_code_err(1);
+      else
+        rx_data_o    <= (others => '1');
+        rx_k_o       <= (others => '1');
+        rx_enc_err_o <= '1';
+      end if;
+    end if;
+  end process;
+
+  p_gen_tx_disparity : process(tx_out_clk, rst_done_n)
+  begin
+    if rising_edge(tx_out_clk) then
+      if rst_done_n = '1' then
+        cur_disp <= RD_MINUS;
+      else
+        cur_disp <= f_next_8b10b_disparity16(cur_disp, tx_k_i, tx_data_i);
+      end if;
+    end if;
+  end process;
+
+  tx_disparity_o <= to_std_logic(cur_disp);
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
new file mode 100644
index 000000000..07ca69aa5
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
@@ -0,0 +1,230 @@
+-------------------------------------------------------------------------------
+-- Title      : Deterministic Xilinx GTP wrapper - bitslide state machine
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : gtp_bitslide.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2013-12-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Module implements a manual bitslide alignment state machine and
+-- provides the obtained bitslide value to the MAC.
+-------------------------------------------------------------------------------
+--
+-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
+-- VHDL port (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2010-11-18  0.4      twlostow  Ported EASE design to VHDL 
+-- 2011-02-07  0.5      twlostow  Verified on Spartan6 GTP
+-- 2011-09-12  0.6      twlostow  Virtex6 port
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity gtp_bitslide is
+  
+  generic (
+-- set to non-zero value to enable some simulation speedups (reduce delays)
+    g_simulation : integer;
+    g_target     : string := "spartan6");
+
+  port (
+    gtp_rst_i : in std_logic;
+
+-- GTP
+    gtp_rx_clk_i : in std_logic;
+
+-- '1' indicates that the GTP has detected a comma in the incoming serial stream
+    gtp_rx_comma_det_i : in std_logic;
+
+
+    gtp_rx_byte_is_aligned_i : in std_logic;
+
+-- GTP ready flag (PLL locked and RX signal present)
+    serdes_ready_i : in std_logic;
+
+-- GTP manual bitslip control line
+    gtp_rx_slide_o : out std_logic;
+
+-- GTP CDR reset, asserted when the link is lost to set the bitslide to a known
+-- value
+    gtp_rx_cdr_rst_o : out std_logic;
+
+-- Current bitslide, in UIs
+    bitslide_o : out std_logic_vector(4 downto 0);
+
+-- '1' when the bitsliding has been completed and the link is up
+    synced_o : out std_logic
+    );
+
+end gtp_bitslide;
+
+
+architecture behavioral of gtp_bitslide is
+
+
+
+  function f_eval_sync_detect_threshold
+    return integer is
+  begin
+    if(g_simulation /= 0) then
+      return 256;
+    else
+      return 4000000;
+    end if;
+  end f_eval_sync_detect_threshold;
+
+  function f_eval_pause_tics return integer is
+  begin
+    if(g_target = "spartan6") then
+      return 31;
+    else
+      return 63;
+    end if;
+  end f_eval_pause_tics;
+
+  function f_max_bts return integer is
+  begin
+    if(g_target = "spartan6") then
+      return 10;
+    else
+      return 20;
+    end if;
+  end f_max_bts;
+
+  constant c_pause_tics            : integer := f_eval_pause_tics;
+  constant c_sync_detect_threshold : integer := f_eval_sync_detect_threshold;
+  constant c_max_bts               : integer := f_max_bts;
+
+
+  type t_bitslide_fsm_state is (S_SYNC_LOST, S_STABILIZE, S_SLIDE, S_PAUSE, S_GOT_SYNC, S_RESET_CDR);
+  signal cur_slide : unsigned(4 downto 0);
+  signal state     : t_bitslide_fsm_state;
+  signal counter   : unsigned(23 downto 0);
+
+  signal commas_missed : unsigned(4 downto 0);
+  
+begin  -- behavioral
+
+  p_do_slide : process(gtp_rx_clk_i, gtp_rst_i)
+  begin
+    if gtp_rst_i = '1' then
+      state            <= S_SYNC_LOST;
+      gtp_rx_slide_o   <= '0';
+      counter          <= (others => '0');
+      synced_o         <= '0';
+      gtp_rx_cdr_rst_o <= '0';
+    elsif rising_edge(gtp_rx_clk_i) then
+      
+      if(serdes_ready_i = '0') then
+        state <= S_SYNC_LOST;
+      end if;
+
+      case state is
+
+-- State: synchronization lost. Waits until a comma pattern is detected
+        when S_SYNC_LOST =>
+          cur_slide        <= (others => '0');
+          counter          <= (others => '0');
+          gtp_rx_slide_o   <= '0';
+          synced_o         <= '0';
+          gtp_rx_cdr_rst_o <= '0';
+          commas_missed    <= (others => '0');
+
+          if(gtp_rx_comma_det_i = '1') then
+            state <= S_STABILIZE;
+          end if;
+
+-- State: stabilize: 
+          
+        when S_STABILIZE =>
+          
+          
+          if(gtp_rx_comma_det_i = '1') then
+            counter       <= counter + 1;
+            commas_missed <= (others => '0');
+          else
+
+            commas_missed <= commas_missed + 1;
+            if(commas_missed(3) = '1') then
+              state <= S_SYNC_LOST;
+            end if;
+          end if;
+
+          if(counter = to_unsigned(c_sync_detect_threshold, counter'length)) then
+            counter <= (others => '0');
+            state   <= S_PAUSE;
+          end if;
+
+          if(serdes_ready_i = '0') then
+            state <= S_SYNC_LOST;
+          end if;
+
+        when S_SLIDE =>
+          if (cur_slide < c_max_bts-1) then
+            cur_slide <= cur_slide + 1;
+          else
+            cur_slide <= (others=>'0');
+          end if;
+          gtp_rx_slide_o <= '1';
+          counter        <= (others => '0');
+
+          state <= S_PAUSE;
+
+          if(serdes_ready_i = '0') then
+            state <= S_SYNC_LOST;
+          end if;
+
+        when S_PAUSE =>
+          counter        <= counter + 1;
+          gtp_rx_slide_o <= '0';
+
+          if(counter = to_unsigned(c_pause_tics, counter'length)) then
+
+            if(gtp_rx_byte_is_aligned_i = '0') then
+              state <= S_SLIDE;
+            else
+              state <= S_GOT_SYNC;
+            end if;
+          end if;
+
+        when S_GOT_SYNC =>
+          gtp_rx_slide_o <= '0';
+          bitslide_o     <= std_logic_vector(cur_slide(4 downto 0));
+          synced_o       <= '1';
+          if(gtp_rx_byte_is_aligned_i = '0' or serdes_ready_i = '0') then
+            gtp_rx_cdr_rst_o <= '1';
+            state            <= S_SYNC_LOST;
+          end if;
+        when others => null;
+      end case;
+    end if;
+  end process;
+  
+  
+
+end behavioral;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd
new file mode 100644
index 000000000..a95ecdd22
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd
@@ -0,0 +1,137 @@
+------------------------------------------------------------------------------
+-- Title      : Deterministic Xilinx GTP wrapper - TX phase alignment
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : gtp_phase_align.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2011-09-12
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: TX phase alignment state machine, as recommended by Xilinx.
+-------------------------------------------------------------------------------
+--
+-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
+-- VHDL port (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2010-11-18  0.4      twlostow  Ported EASE design to VHDL 
+-- 2011-02-07  0.5      twlostow  Verified on Spartan6 GTP
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity gtp_phase_align is
+  generic
+    (g_simulation : integer);
+  
+  port (
+    gtp_rst_i    : in std_logic;
+    gtp_tx_clk_i : in std_logic;
+
+    gtp_tx_en_pma_phase_align_o : out std_logic;
+    gtp_tx_pma_set_phase_o      : out std_logic;
+
+    align_en_i   : in  std_logic;
+    align_done_o : out std_logic
+    );
+
+end gtp_phase_align;
+
+architecture behavioral of gtp_phase_align is
+
+  constant c_wait_en_phase_align  : integer := 32;
+  constant c_wait_set_phase_align : integer := 512;
+  constant c_phase_align_duration : integer := 8192;
+
+
+  type t_align_state is (S_ALIGN_IDLE, S_ALIGN_PAUSE, S_ALIGN_WAIT, S_ALIGN_SET_PHASE, S_ALIGN_DONE);
+
+  signal counter : unsigned(13 downto 0);
+  signal state   : t_align_state;
+
+  
+begin  -- behavioral
+
+  p_align : process(gtp_tx_clk_i, gtp_rst_i)
+  begin
+    if rising_edge(gtp_tx_clk_i) then
+      if gtp_rst_i = '1' then
+        gtp_tx_en_pma_phase_align_o <= '0';
+        gtp_tx_pma_set_phase_o      <= '0';
+        counter                     <= (others => '0');
+        align_done_o                <= '0';
+        state                       <= S_ALIGN_IDLE;
+      else
+        if(align_en_i = '0') then
+          state <= S_ALIGN_IDLE;
+        else
+
+          case (state) is
+            when S_ALIGN_IDLE =>
+              gtp_tx_en_pma_phase_align_o <= '0';
+              gtp_tx_pma_set_phase_o      <= '0';
+              counter                     <= (others => '0');
+              align_done_o                <= '0';
+
+              if(align_en_i = '1') then
+                state <= S_ALIGN_PAUSE;
+              end if;
+
+            when S_ALIGN_PAUSE =>
+              counter <= counter + 1;
+              if(counter = to_unsigned(c_wait_en_phase_align, counter'length)) then
+                state <= S_ALIGN_WAIT;
+              end if;
+
+            when S_ALIGN_WAIT =>
+              gtp_tx_en_pma_phase_align_o <= '1';
+              counter                     <= counter + 1;
+              if(counter = to_unsigned(c_wait_en_phase_align + c_wait_set_phase_align, counter'length)) then
+                state <= S_ALIGN_SET_PHASE;
+              end if;
+
+            when S_ALIGN_SET_PHASE =>
+              counter                <= counter +1;
+              gtp_tx_pma_set_phase_o <= '1';
+
+              if(counter = to_unsigned(c_wait_en_phase_align + c_wait_set_phase_align + c_phase_align_duration, counter'length)) then
+                state <= S_ALIGN_DONE;
+              end if;
+
+            when S_ALIGN_DONE =>
+              gtp_tx_pma_set_phase_o <= '0';
+              counter                <= (others => '0');
+              align_done_o           <= '1';
+            when others => null;
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+
+end behavioral;
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd
new file mode 100644
index 000000000..9a97d3d91
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd
@@ -0,0 +1,712 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
+
+--***************************** Entity Declaration ****************************
+
+entity WHITERABBITGTP_WRAPPER_TILE_SPARTAN6 is
+  generic
+    (
+      TILE_SIM_GTPRESET_SPEEDUP : integer := 0;  -- Set to 1 to speed up sim reset
+      TILE_CLK25_DIVIDER_0      : integer := 4;
+      TILE_CLK25_DIVIDER_1      : integer := 4;
+      TILE_PLL_DIVSEL_FB_0      : integer := 5;
+      TILE_PLL_DIVSEL_FB_1      : integer := 5;
+      TILE_PLL_DIVSEL_REF_0     : integer := 2;
+      TILE_PLL_DIVSEL_REF_1     : integer := 2;
+      TILE_PLL_SOURCE_0         : string  := "PLL0";
+      TILE_PLL_SOURCE_1         : string  := "PLL1"
+      );
+  port
+    (
+      ------------------------ Loopback and Powerdown Ports ----------------------
+      LOOPBACK0_IN         : in  std_logic_vector(2 downto 0);
+      LOOPBACK1_IN         : in  std_logic_vector(2 downto 0);
+      REFCLKOUT0_OUT           : out std_logic;
+      REFCLKOUT1_OUT           : out std_logic;
+      --------------------------------- PLL Ports --------------------------------
+      CLK00_IN             : in  std_logic;
+      CLK01_IN             : in  std_logic;
+      CLK10_IN             : in  std_logic;
+      CLK11_IN             : in  std_logic;
+      GTPRESET0_IN         : in  std_logic;
+      GTPRESET1_IN         : in  std_logic;
+      PLLLKDET0_OUT        : out std_logic;
+      PLLLKDET1_OUT        : out std_logic;
+      RESETDONE0_OUT       : out std_logic;
+      RESETDONE1_OUT       : out std_logic;
+      ----------------------- Receive Ports - 8b10b Decoder ----------------------
+      RXCHARISK0_OUT       : out std_logic;
+      RXCHARISK1_OUT       : out std_logic;
+      RXDISPERR0_OUT       : out std_logic;
+      RXDISPERR1_OUT       : out std_logic;
+      RXNOTINTABLE0_OUT    : out std_logic;
+      RXNOTINTABLE1_OUT    : out std_logic;
+      --------------- Receive Ports - Comma Detection and Alignment --------------
+      RXBYTEISALIGNED0_OUT : out std_logic;
+      RXBYTEISALIGNED1_OUT : out std_logic;
+      RXCOMMADET0_OUT      : out std_logic;
+      RXCOMMADET1_OUT      : out std_logic;
+      RXSLIDE0_IN          : in  std_logic;
+      RXSLIDE1_IN          : in  std_logic;
+      ------------------- Receive Ports - RX Data Path interface -----------------
+      RXDATA0_OUT          : out std_logic_vector(7 downto 0);
+      RXDATA1_OUT          : out std_logic_vector(7 downto 0);
+      RXUSRCLK0_IN         : in  std_logic;
+      RXUSRCLK1_IN         : in  std_logic;
+      RXUSRCLK20_IN        : in  std_logic;
+      RXUSRCLK21_IN        : in  std_logic;
+      ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+      RXCDRRESET0_IN       : in  std_logic;
+      RXCDRRESET1_IN       : in  std_logic;
+      RXN0_IN              : in  std_logic;
+      RXN1_IN              : in  std_logic;
+      RXP0_IN              : in  std_logic;
+      RXP1_IN              : in  std_logic;
+      ---------------------------- TX/RX Datapath Ports --------------------------
+      GTPCLKFBEAST_OUT     : out std_logic_vector(1 downto 0);
+      GTPCLKFBWEST_OUT     : out std_logic_vector(1 downto 0);
+      GTPCLKOUT0_OUT       : out std_logic_vector(1 downto 0);
+      GTPCLKOUT1_OUT       : out std_logic_vector(1 downto 0);
+      ------------------- Transmit Ports - 8b10b Encoder Control -----------------
+      TXCHARISK0_IN        : in  std_logic;
+      TXCHARISK1_IN        : in  std_logic;
+
+      TXCHARDISPMODE0_IN: in std_logic;
+      TXCHARDISPMODE1_IN: in std_logic;
+
+      TXCHARDISPVAL0_IN: in std_logic;
+      TXCHARDISPVAL1_IN: in std_logic;
+
+      TXRUNDISP0_OUT       : out std_logic_vector(3 downto 0);
+      TXRUNDISP1_OUT       : out std_logic_vector(3 downto 0);
+
+      --------------- Transmit Ports - TX Buffer and Phase Alignment -------------
+      TXENPMAPHASEALIGN0_IN : in  std_logic;
+      TXENPMAPHASEALIGN1_IN : in  std_logic;
+      TXPMASETPHASE0_IN     : in  std_logic;
+      TXPMASETPHASE1_IN     : in  std_logic;
+      ------------------ Transmit Ports - TX Data Path interface -----------------
+      TXDATA0_IN            : in  std_logic_vector(7 downto 0);
+      TXDATA1_IN            : in  std_logic_vector(7 downto 0);
+      TXUSRCLK0_IN          : in  std_logic;
+      TXUSRCLK1_IN          : in  std_logic;
+      TXUSRCLK20_IN         : in  std_logic;
+      TXUSRCLK21_IN         : in  std_logic;
+      --------------- Transmit Ports - TX Driver and OOB signalling --------------
+      TXN0_OUT              : out std_logic;
+      TXN1_OUT              : out std_logic;
+      TXP0_OUT              : out std_logic;
+      TXP1_OUT              : out std_logic;
+      --------------- Transmit Ports - PRBS Generator ----------------------------
+      TXENPRBSTST0_IN       : in  std_logic_vector(2 downto 0);
+      TXENPRBSTST1_IN       : in  std_logic_vector(2 downto 0)
+
+      );
+
+
+end WHITERABBITGTP_WRAPPER_TILE_SPARTAN6;
+
+architecture RTL of WHITERABBITGTP_WRAPPER_TILE_SPARTAN6 is
+
+--**************************** Signal Declarations ****************************
+
+  -- ground and tied_to_vcc_i signals
+  signal tied_to_ground_i     : std_logic;
+  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+  signal tied_to_vcc_i        : std_logic;
+  signal tied_to_vcc_vec_i    : std_logic_vector(63 downto 0);
+
+
+
+  -- RX Datapath signals
+  signal rxdata0_i              : std_logic_vector(31 downto 0);
+  signal rxchariscomma0_float_i : std_logic_vector(2 downto 0);
+  signal rxcharisk0_float_i     : std_logic_vector(2 downto 0);
+  signal rxdisperr0_float_i     : std_logic_vector(2 downto 0);
+  signal rxnotintable0_float_i  : std_logic_vector(2 downto 0);
+  signal rxrundisp0_float_i     : std_logic_vector(2 downto 0);
+
+
+  -- TX Datapath signals
+  signal txdata0_i          : std_logic_vector(31 downto 0);
+  signal txkerr0_float_i    : std_logic_vector(2 downto 0);
+  signal txrundisp0_float_i : std_logic_vector(2 downto 0);
+
+
+  -- RX Datapath signals
+  signal rxdata1_i              : std_logic_vector(31 downto 0);
+  signal rxchariscomma1_float_i : std_logic_vector(2 downto 0);
+  signal rxcharisk1_float_i     : std_logic_vector(2 downto 0);
+  signal rxdisperr1_float_i     : std_logic_vector(2 downto 0);
+  signal rxnotintable1_float_i  : std_logic_vector(2 downto 0);
+  signal rxrundisp1_float_i     : std_logic_vector(2 downto 0);
+
+
+  -- TX Datapath signals
+  signal txdata1_i          : std_logic_vector(31 downto 0);
+  signal txkerr1_float_i    : std_logic_vector(2 downto 0);
+  signal txrundisp1_float_i : std_logic_vector(2 downto 0);
+
+--******************************** Main Body of Code***************************
+  
+begin
+
+  ---------------------------  Static signal Assignments ---------------------   
+
+  tied_to_ground_i                  <= '0';
+  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+  tied_to_vcc_i                     <= '1';
+  tied_to_vcc_vec_i(63 downto 0)    <= (others => '1');
+
+  -------------------  GTP Datapath byte mapping  -----------------    
+
+  RXDATA0_OUT <= rxdata0_i(7 downto 0);
+
+  txdata0_i <= (tied_to_ground_vec_i(23 downto 0) & TXDATA0_IN);
+
+  RXDATA1_OUT <= rxdata1_i(7 downto 0);
+
+  txdata1_i <= (tied_to_ground_vec_i(23 downto 0) & TXDATA1_IN);
+
+
+
+  ----------------------------- GTPA1_DUAL Instance  --------------------------   
+
+  gtpa1_dual_i : GTPA1_DUAL
+    generic map
+    (
+
+      --_______________________ Simulation-Only Attributes ___________________
+
+      SIM_RECEIVER_DETECT_PASS => (true),
+      SIM_TX_ELEC_IDLE_LEVEL   => ("X"),
+      SIM_VERSION              => ("2.0"),
+      SIM_REFCLK0_SOURCE       => ("000"),
+      SIM_REFCLK1_SOURCE       => ("000"),
+      SIM_GTPRESET_SPEEDUP     => (TILE_SIM_GTPRESET_SPEEDUP),
+      CLK25_DIVIDER_0          => (TILE_CLK25_DIVIDER_0),
+      CLK25_DIVIDER_1          => (TILE_CLK25_DIVIDER_1),
+      PLL_DIVSEL_FB_0          => (TILE_PLL_DIVSEL_FB_0),
+      PLL_DIVSEL_FB_1          => (TILE_PLL_DIVSEL_FB_1),
+      PLL_DIVSEL_REF_0         => (TILE_PLL_DIVSEL_REF_0),
+      PLL_DIVSEL_REF_1         => (TILE_PLL_DIVSEL_REF_1),
+
+
+      --PLL Attributes
+      CLKINDC_B_0        => (true),
+      CLKRCV_TRST_0      => (true),
+      OOB_CLK_DIVIDER_0  => (4),
+      PLL_COM_CFG_0      => (x"21680a"),
+      PLL_CP_CFG_0       => (x"00"),
+      PLL_RXDIVSEL_OUT_0 => (2),
+      PLL_SATA_0         => (false),
+      PLL_SOURCE_0       => (TILE_PLL_SOURCE_0),
+      PLL_TXDIVSEL_OUT_0 => (2),
+      PLLLKDET_CFG_0     => ("111"),
+
+      --
+      CLKINDC_B_1        => (true),
+      CLKRCV_TRST_1      => (true),
+      OOB_CLK_DIVIDER_1  => (4),
+      PLL_COM_CFG_1      => (x"21680a"),
+      PLL_CP_CFG_1       => (x"00"),
+      PLL_RXDIVSEL_OUT_1 => (2),
+      PLL_SATA_1         => (false),
+      PLL_SOURCE_1       => (TILE_PLL_SOURCE_1),
+      PLL_TXDIVSEL_OUT_1 => (2),
+      PLLLKDET_CFG_1     => ("111"),
+      PMA_COM_CFG_EAST   => (x"000008000"),
+      PMA_COM_CFG_WEST   => (x"000008000"),
+      TST_ATTR_0         => (x"00000000"),
+      TST_ATTR_1         => (x"00000000"),
+
+      --TX Interface Attributes
+      CLK_OUT_GTP_SEL_0 => ("REFCLKPLL0"),
+      TX_TDCC_CFG_0     => ("00"),
+      CLK_OUT_GTP_SEL_1 => ("REFCLKPLL1"),
+      TX_TDCC_CFG_1     => ("00"),
+
+      --TX Buffer and Phase Alignment Attributes
+      PMA_TX_CFG_0    => (x"80082"),
+      TX_BUFFER_USE_0 => (false),
+      TX_XCLK_SEL_0   => ("TXUSR"),
+      TXRX_INVERT_0   => ("111"),
+      PMA_TX_CFG_1    => (x"80082"),
+      TX_BUFFER_USE_1 => (false),
+      TX_XCLK_SEL_1   => ("TXUSR"),
+      TXRX_INVERT_1   => ("111"),
+
+      --TX Driver and OOB signalling Attributes
+      CM_TRIM_0       => ("00"),
+      TX_IDLE_DELAY_0 => ("011"),
+      CM_TRIM_1       => ("00"),
+      TX_IDLE_DELAY_1 => ("011"),
+
+      --TX PIPE/SATA Attributes
+      COM_BURST_VAL_0 => ("1111"),
+      COM_BURST_VAL_1 => ("1111"),
+
+      --RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
+      AC_CAP_DIS_0          => (true),
+      OOBDETECT_THRESHOLD_0 => ("110"),
+      PMA_CDR_SCAN_0        => (x"6404040"),
+      PMA_RX_CFG_0          => (x"05ce048"),
+      PMA_RXSYNC_CFG_0      => (x"00"),
+      RCV_TERM_GND_0        => (false),
+      RCV_TERM_VTTRX_0      => (false),
+      RXEQ_CFG_0            => ("01111011"),
+      TERMINATION_CTRL_0    => ("10100"),
+      TERMINATION_OVRD_0    => (false),
+      TX_DETECT_RX_CFG_0    => (x"1832"),
+      AC_CAP_DIS_1          => (true),
+      OOBDETECT_THRESHOLD_1 => ("110"),
+      PMA_CDR_SCAN_1        => (x"6404040"),
+      PMA_RX_CFG_1          => (x"05ce048"),
+      PMA_RXSYNC_CFG_1      => (x"00"),
+      RCV_TERM_GND_1        => (false),
+      RCV_TERM_VTTRX_1      => (false),
+      RXEQ_CFG_1            => ("01111011"),
+      TERMINATION_CTRL_1    => ("10100"),
+      TERMINATION_OVRD_1    => (false),
+      TX_DETECT_RX_CFG_1    => (x"1832"),
+
+      --PRBS Detection Attributes
+      RXPRBSERR_LOOPBACK_0 => ('0'),
+      RXPRBSERR_LOOPBACK_1 => ('0'),
+
+      --Comma Detection and Alignment Attributes
+      ALIGN_COMMA_WORD_0     => (1),
+      COMMA_10B_ENABLE_0     => ("1111111111"),
+      DEC_MCOMMA_DETECT_0    => (false),
+      DEC_PCOMMA_DETECT_0    => (false),
+      DEC_VALID_COMMA_ONLY_0 => (true),
+      MCOMMA_10B_VALUE_0     => ("1010000011"),
+      MCOMMA_DETECT_0        => (true),
+      PCOMMA_10B_VALUE_0     => ("0101111100"),
+      PCOMMA_DETECT_0        => (true),
+      RX_SLIDE_MODE_0        => ("PCS"),
+      ALIGN_COMMA_WORD_1     => (1),
+      COMMA_10B_ENABLE_1     => ("1111111111"),
+      DEC_MCOMMA_DETECT_1    => (false),
+      DEC_PCOMMA_DETECT_1    => (false),
+      DEC_VALID_COMMA_ONLY_1 => (true),
+      MCOMMA_10B_VALUE_1     => ("1010000011"),
+      MCOMMA_DETECT_1        => (true),
+      PCOMMA_10B_VALUE_1     => ("0101111100"),
+      PCOMMA_DETECT_1        => (true),
+      RX_SLIDE_MODE_1        => ("PCS"),
+
+      --RX Loss-of-sync State Machine Attributes
+      RX_LOS_INVALID_INCR_0 => (8),
+      RX_LOS_THRESHOLD_0    => (128),
+      RX_LOSS_OF_SYNC_FSM_0 => (false),
+      RX_LOS_INVALID_INCR_1 => (8),
+      RX_LOS_THRESHOLD_1    => (128),
+      RX_LOSS_OF_SYNC_FSM_1 => (false),
+
+      --RX Elastic Buffer and Phase alignment Attributes
+      RX_BUFFER_USE_0        => (true),
+      RX_EN_IDLE_RESET_BUF_0 => (true),
+      RX_IDLE_HI_CNT_0       => ("1000"),
+      RX_IDLE_LO_CNT_0       => ("0000"),
+      RX_XCLK_SEL_0          => ("RXREC"),
+      RX_BUFFER_USE_1        => (true),
+      RX_EN_IDLE_RESET_BUF_1 => (true),
+      RX_IDLE_HI_CNT_1       => ("1000"),
+      RX_IDLE_LO_CNT_1       => ("0000"),
+      RX_XCLK_SEL_1          => ("RXREC"),
+
+      --Clock Correction Attributes
+      CLK_COR_ADJ_LEN_0          => (1),
+      CLK_COR_DET_LEN_0          => (1),
+      CLK_COR_INSERT_IDLE_FLAG_0 => (false),
+      CLK_COR_KEEP_IDLE_0        => (false),
+      CLK_COR_MAX_LAT_0          => (18),
+      CLK_COR_MIN_LAT_0          => (16),
+      CLK_COR_PRECEDENCE_0       => (true),
+      CLK_COR_REPEAT_WAIT_0      => (0),
+      CLK_COR_SEQ_1_1_0          => ("0100000000"),
+      CLK_COR_SEQ_1_2_0          => ("0000000000"),
+      CLK_COR_SEQ_1_3_0          => ("0000000000"),
+      CLK_COR_SEQ_1_4_0          => ("0000000000"),
+      CLK_COR_SEQ_1_ENABLE_0     => ("0000"),
+      CLK_COR_SEQ_2_1_0          => ("0100000000"),
+      CLK_COR_SEQ_2_2_0          => ("0000000000"),
+      CLK_COR_SEQ_2_3_0          => ("0000000000"),
+      CLK_COR_SEQ_2_4_0          => ("0000000000"),
+      CLK_COR_SEQ_2_ENABLE_0     => ("0000"),
+      CLK_COR_SEQ_2_USE_0        => (false),
+      CLK_CORRECT_USE_0          => (false),
+      RX_DECODE_SEQ_MATCH_0      => (true),
+      CLK_COR_ADJ_LEN_1          => (1),
+      CLK_COR_DET_LEN_1          => (1),
+      CLK_COR_INSERT_IDLE_FLAG_1 => (false),
+      CLK_COR_KEEP_IDLE_1        => (false),
+      CLK_COR_MAX_LAT_1          => (18),
+      CLK_COR_MIN_LAT_1          => (16),
+      CLK_COR_PRECEDENCE_1       => (true),
+      CLK_COR_REPEAT_WAIT_1      => (0),
+      CLK_COR_SEQ_1_1_1          => ("0100000000"),
+      CLK_COR_SEQ_1_2_1          => ("0000000000"),
+      CLK_COR_SEQ_1_3_1          => ("0000000000"),
+      CLK_COR_SEQ_1_4_1          => ("0000000000"),
+      CLK_COR_SEQ_1_ENABLE_1     => ("0000"),
+      CLK_COR_SEQ_2_1_1          => ("0100000000"),
+      CLK_COR_SEQ_2_2_1          => ("0000000000"),
+      CLK_COR_SEQ_2_3_1          => ("0000000000"),
+      CLK_COR_SEQ_2_4_1          => ("0000000000"),
+      CLK_COR_SEQ_2_ENABLE_1     => ("0000"),
+      CLK_COR_SEQ_2_USE_1        => (false),
+      CLK_CORRECT_USE_1          => (false),
+      RX_DECODE_SEQ_MATCH_1      => (true),
+
+      --Channel Bonding Attributes
+      CHAN_BOND_1_MAX_SKEW_0   => (1),
+      CHAN_BOND_2_MAX_SKEW_0   => (1),
+      CHAN_BOND_KEEP_ALIGN_0   => (false),
+      CHAN_BOND_SEQ_1_1_0      => ("0000000000"),
+      CHAN_BOND_SEQ_1_2_0      => ("0000000000"),
+      CHAN_BOND_SEQ_1_3_0      => ("0000000000"),
+      CHAN_BOND_SEQ_1_4_0      => ("0000000000"),
+      CHAN_BOND_SEQ_1_ENABLE_0 => ("0000"),
+      CHAN_BOND_SEQ_2_1_0      => ("0000000000"),
+      CHAN_BOND_SEQ_2_2_0      => ("0000000000"),
+      CHAN_BOND_SEQ_2_3_0      => ("0000000000"),
+      CHAN_BOND_SEQ_2_4_0      => ("0000000000"),
+      CHAN_BOND_SEQ_2_ENABLE_0 => ("0000"),
+      CHAN_BOND_SEQ_2_USE_0    => (false),
+      CHAN_BOND_SEQ_LEN_0      => (1),
+      RX_EN_MODE_RESET_BUF_0   => (true),
+      CHAN_BOND_1_MAX_SKEW_1   => (1),
+      CHAN_BOND_2_MAX_SKEW_1   => (1),
+      CHAN_BOND_KEEP_ALIGN_1   => (false),
+      CHAN_BOND_SEQ_1_1_1      => ("0000000000"),
+      CHAN_BOND_SEQ_1_2_1      => ("0000000000"),
+      CHAN_BOND_SEQ_1_3_1      => ("0000000000"),
+      CHAN_BOND_SEQ_1_4_1      => ("0000000000"),
+      CHAN_BOND_SEQ_1_ENABLE_1 => ("0000"),
+      CHAN_BOND_SEQ_2_1_1      => ("0000000000"),
+      CHAN_BOND_SEQ_2_2_1      => ("0000000000"),
+      CHAN_BOND_SEQ_2_3_1      => ("0000000000"),
+      CHAN_BOND_SEQ_2_4_1      => ("0000000000"),
+      CHAN_BOND_SEQ_2_ENABLE_1 => ("0000"),
+      CHAN_BOND_SEQ_2_USE_1    => (false),
+      CHAN_BOND_SEQ_LEN_1      => (1),
+      RX_EN_MODE_RESET_BUF_1   => (true),
+
+      --RX PCI Express Attributes
+      CB2_INH_CC_PERIOD_0   => (8),
+      CDR_PH_ADJ_TIME_0     => ("01010"),
+      PCI_EXPRESS_MODE_0    => (false),
+      RX_EN_IDLE_HOLD_CDR_0 => (false),
+      RX_EN_IDLE_RESET_FR_0 => (true),
+      RX_EN_IDLE_RESET_PH_0 => (true),
+      RX_STATUS_FMT_0       => ("PCIE"),
+      TRANS_TIME_FROM_P2_0  => (x"03c"),
+      TRANS_TIME_NON_P2_0   => (x"19"),
+      TRANS_TIME_TO_P2_0    => (x"064"),
+      CB2_INH_CC_PERIOD_1   => (8),
+      CDR_PH_ADJ_TIME_1     => ("01010"),
+      PCI_EXPRESS_MODE_1    => (false),
+      RX_EN_IDLE_HOLD_CDR_1 => (false),
+      RX_EN_IDLE_RESET_FR_1 => (true),
+      RX_EN_IDLE_RESET_PH_1 => (true),
+      RX_STATUS_FMT_1       => ("PCIE"),
+      TRANS_TIME_FROM_P2_1  => (x"03c"),
+      TRANS_TIME_NON_P2_1   => (x"19"),
+      TRANS_TIME_TO_P2_1    => (x"064"),
+
+      --RX SATA Attributes
+      SATA_BURST_VAL_0 => ("100"),
+      SATA_IDLE_VAL_0  => ("100"),
+      SATA_MAX_BURST_0 => (9),
+      SATA_MAX_INIT_0  => (27),
+      SATA_MAX_WAKE_0  => (9),
+      SATA_MIN_BURST_0 => (5),
+      SATA_MIN_INIT_0  => (15),
+      SATA_MIN_WAKE_0  => (5),
+      SATA_BURST_VAL_1 => ("100"),
+      SATA_IDLE_VAL_1  => ("100"),
+      SATA_MAX_BURST_1 => (9),
+      SATA_MAX_INIT_1  => (27),
+      SATA_MAX_WAKE_1  => (9),
+      SATA_MIN_BURST_1 => (5),
+      SATA_MIN_INIT_1  => (15),
+      SATA_MIN_WAKE_1  => (5)
+
+
+      ) 
+    port map
+    (
+      ------------------------ Loopback and Powerdown Ports ----------------------
+      LOOPBACK0                 => LOOPBACK0_IN,
+      LOOPBACK1                 => LOOPBACK1_IN,
+      RXPOWERDOWN0              => tied_to_ground_vec_i(1 downto 0),
+      RXPOWERDOWN1              => tied_to_ground_vec_i(1 downto 0),
+      TXPOWERDOWN0              => tied_to_ground_vec_i(1 downto 0),
+      TXPOWERDOWN1              => tied_to_ground_vec_i(1 downto 0),
+      --------------------------------- PLL Ports --------------------------------
+      CLK00                     => CLK00_IN,
+      CLK01                     => CLK01_IN,
+      CLK10                     => CLK10_IN,
+      CLK11                     => CLK11_IN,
+      CLKINEAST0                => tied_to_ground_i,
+      CLKINEAST1                => tied_to_ground_i,
+      CLKINWEST0                => tied_to_ground_i,
+      CLKINWEST1                => tied_to_ground_i,
+      GCLK00                    => tied_to_ground_i,
+      GCLK01                    => tied_to_ground_i,
+      GCLK10                    => tied_to_ground_i,
+      GCLK11                    => tied_to_ground_i,
+      GTPRESET0                 => GTPRESET0_IN,
+      GTPRESET1                 => GTPRESET1_IN,
+      GTPTEST0                  => "00010000",
+      GTPTEST1                  => "00010000",
+      INTDATAWIDTH0             => tied_to_vcc_i,
+      INTDATAWIDTH1             => tied_to_vcc_i,
+      PLLCLK00                  => tied_to_ground_i,
+      PLLCLK01                  => tied_to_ground_i,
+      PLLCLK10                  => tied_to_ground_i,
+      PLLCLK11                  => tied_to_ground_i,
+      PLLLKDET0                 => PLLLKDET0_OUT,
+      PLLLKDET1                 => PLLLKDET1_OUT,
+      PLLLKDETEN0               => tied_to_vcc_i,
+      PLLLKDETEN1               => tied_to_vcc_i,
+      PLLPOWERDOWN0             => tied_to_ground_i,
+      PLLPOWERDOWN1             => tied_to_ground_i,
+      REFCLKOUT0                => REFCLKOUT0_OUT,
+      REFCLKOUT1                => REFCLKOUT1_OUT,
+      REFCLKPLL0                => open,
+      REFCLKPLL1                => open,
+      REFCLKPWRDNB0             => tied_to_vcc_i,
+      REFCLKPWRDNB1             => tied_to_vcc_i,
+      REFSELDYPLL0              => tied_to_ground_vec_i(2 downto 0),
+      REFSELDYPLL1              => tied_to_ground_vec_i(2 downto 0),
+      RESETDONE0                => RESETDONE0_OUT,
+      RESETDONE1                => RESETDONE1_OUT,
+      TSTCLK0                   => tied_to_ground_i,
+      TSTCLK1                   => tied_to_ground_i,
+      TSTIN0                    => tied_to_ground_vec_i(11 downto 0),
+      TSTIN1                    => tied_to_ground_vec_i(11 downto 0),
+      TSTOUT0                   => open,
+      TSTOUT1                   => open,
+      ----------------------- Receive Ports - 8b10b Decoder ----------------------
+      RXCHARISCOMMA0            => open,
+      RXCHARISCOMMA1            => open,
+      RXCHARISK0(3 downto 1)    => rxcharisk0_float_i,
+      RXCHARISK0(0)             => RXCHARISK0_OUT,
+      RXCHARISK1(3 downto 1)    => rxcharisk1_float_i,
+      RXCHARISK1(0)             => RXCHARISK1_OUT,
+      RXDEC8B10BUSE0            => tied_to_vcc_i,
+      RXDEC8B10BUSE1            => tied_to_vcc_i,
+      RXDISPERR0(3 downto 1)    => rxdisperr0_float_i,
+      RXDISPERR0(0)             => RXDISPERR0_OUT,
+      RXDISPERR1(3 downto 1)    => rxdisperr1_float_i,
+      RXDISPERR1(0)             => RXDISPERR1_OUT,
+      RXNOTINTABLE0(3 downto 1) => rxnotintable0_float_i,
+      RXNOTINTABLE0(0)          => RXNOTINTABLE0_OUT,
+      RXNOTINTABLE1(3 downto 1) => rxnotintable1_float_i,
+      RXNOTINTABLE1(0)          => RXNOTINTABLE1_OUT,
+      RXRUNDISP0                => open,
+      RXRUNDISP1                => open,
+      USRCODEERR0               => tied_to_ground_i,
+      USRCODEERR1               => tied_to_ground_i,
+      ---------------------- Receive Ports - Channel Bonding ---------------------
+      RXCHANBONDSEQ0            => open,
+      RXCHANBONDSEQ1            => open,
+      RXCHANISALIGNED0          => open,
+      RXCHANISALIGNED1          => open,
+      RXCHANREALIGN0            => open,
+      RXCHANREALIGN1            => open,
+      RXCHBONDI                 => tied_to_ground_vec_i(2 downto 0),
+      RXCHBONDMASTER0           => tied_to_ground_i,
+      RXCHBONDMASTER1           => tied_to_ground_i,
+      RXCHBONDO                 => open,
+      RXCHBONDSLAVE0            => tied_to_ground_i,
+      RXCHBONDSLAVE1            => tied_to_ground_i,
+      RXENCHANSYNC0             => tied_to_ground_i,
+      RXENCHANSYNC1             => tied_to_ground_i,
+      ---------------------- Receive Ports - Clock Correction --------------------
+      RXCLKCORCNT0              => open,
+      RXCLKCORCNT1              => open,
+      --------------- Receive Ports - Comma Detection and Alignment --------------
+      RXBYTEISALIGNED0          => RXBYTEISALIGNED0_OUT,
+      RXBYTEISALIGNED1          => RXBYTEISALIGNED1_OUT,
+      RXBYTEREALIGN0            => open,
+      RXBYTEREALIGN1            => open,
+      RXCOMMADET0               => RXCOMMADET0_OUT,
+      RXCOMMADET1               => RXCOMMADET1_OUT,
+      RXCOMMADETUSE0            => tied_to_vcc_i,
+      RXCOMMADETUSE1            => tied_to_vcc_i,
+      RXENMCOMMAALIGN0          => tied_to_ground_i,
+      RXENMCOMMAALIGN1          => tied_to_ground_i,
+      RXENPCOMMAALIGN0          => tied_to_ground_i,
+      RXENPCOMMAALIGN1          => tied_to_ground_i,
+      RXSLIDE0                  => RXSLIDE0_IN,
+      RXSLIDE1                  => RXSLIDE1_IN,
+      ----------------------- Receive Ports - PRBS Detection ---------------------
+      PRBSCNTRESET0             => tied_to_ground_i,
+      PRBSCNTRESET1             => tied_to_ground_i,
+      RXENPRBSTST0              => tied_to_ground_vec_i(2 downto 0),
+      RXENPRBSTST1              => tied_to_ground_vec_i(2 downto 0),
+      RXPRBSERR0                => open,
+      RXPRBSERR1                => open,
+      ------------------- Receive Ports - RX Data Path interface -----------------
+      RXDATA0                   => rxdata0_i,
+      RXDATA1                   => rxdata1_i,
+      RXDATAWIDTH0              => "00",
+      RXDATAWIDTH1              => "00",
+      RXRECCLK0                 => open,
+      RXRECCLK1                 => open,
+      RXRESET0                  => tied_to_ground_i,
+      RXRESET1                  => tied_to_ground_i,
+      RXUSRCLK0                 => RXUSRCLK0_IN,
+      RXUSRCLK1                 => RXUSRCLK1_IN,
+      RXUSRCLK20                => RXUSRCLK20_IN,
+      RXUSRCLK21                => RXUSRCLK21_IN,
+      ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+      GATERXELECIDLE0           => tied_to_ground_i,
+      GATERXELECIDLE1           => tied_to_ground_i,
+      IGNORESIGDET0             => tied_to_ground_i,
+      IGNORESIGDET1             => tied_to_ground_i,
+      RCALINEAST                => tied_to_ground_vec_i(4 downto 0),
+      RCALINWEST                => tied_to_ground_vec_i(4 downto 0),
+      RCALOUTEAST               => open,
+      RCALOUTWEST               => open,
+      RXCDRRESET0               => RXCDRRESET0_IN,
+      RXCDRRESET1               => RXCDRRESET1_IN,
+      RXELECIDLE0               => open,
+      RXELECIDLE1               => open,
+      RXEQMIX0                  => "00",
+      RXEQMIX1                  => "00",
+      RXN0                      => RXN0_IN,
+      RXN1                      => RXN1_IN,
+      RXP0                      => RXP0_IN,
+      RXP1                      => RXP1_IN,
+      ----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
+      RXBUFRESET0               => tied_to_ground_i,
+      RXBUFRESET1               => tied_to_ground_i,
+      RXBUFSTATUS0              => open,
+      RXBUFSTATUS1              => open,
+      RXENPMAPHASEALIGN0        => tied_to_ground_i,
+      RXENPMAPHASEALIGN1        => tied_to_ground_i,
+      RXPMASETPHASE0            => tied_to_ground_i,
+      RXPMASETPHASE1            => tied_to_ground_i,
+      RXSTATUS0                 => open,
+      RXSTATUS1                 => open,
+      --------------- Receive Ports - RX Loss-of-sync State Machine --------------
+      RXLOSSOFSYNC0             => open,
+      RXLOSSOFSYNC1             => open,
+      -------------- Receive Ports - RX Pipe Control for PCI Express -------------
+      PHYSTATUS0                => open,
+      PHYSTATUS1                => open,
+      RXVALID0                  => open,
+      RXVALID1                  => open,
+      -------------------- Receive Ports - RX Polarity Control -------------------
+      RXPOLARITY0               => tied_to_ground_i,
+      RXPOLARITY1               => tied_to_ground_i,
+      ------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
+      DADDR                     => tied_to_ground_vec_i(7 downto 0),
+      DCLK                      => tied_to_ground_i,
+      DEN                       => tied_to_ground_i,
+      DI                        => tied_to_ground_vec_i(15 downto 0),
+      DRDY                      => open,
+      DRPDO                     => open,
+      DWE                       => tied_to_ground_i,
+      ---------------------------- TX/RX Datapath Ports --------------------------
+      GTPCLKFBEAST              => GTPCLKFBEAST_OUT,
+      GTPCLKFBSEL0EAST          => "10",
+      GTPCLKFBSEL0WEST          => "00",
+      GTPCLKFBSEL1EAST          => "11",
+      GTPCLKFBSEL1WEST          => "01",
+      GTPCLKFBWEST              => GTPCLKFBWEST_OUT,
+      GTPCLKOUT0                => GTPCLKOUT0_OUT,
+      GTPCLKOUT1                => GTPCLKOUT1_OUT,
+      ------------------- Transmit Ports - 8b10b Encoder Control -----------------
+      TXBYPASS8B10B0            => tied_to_ground_vec_i(3 downto 0),
+      TXBYPASS8B10B1            => tied_to_ground_vec_i(3 downto 0),
+
+      TXCHARDISPMODE0(0)           => TXCHARDISPMODE0_IN,
+      TXCHARDISPMODE0(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
+
+      TXCHARDISPMODE1(0)           => TXCHARDISPMODE1_IN,
+      TXCHARDISPMODE1(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
+
+      TXCHARDISPVAL0(0)           => TXCHARDISPVAL0_IN,
+      TXCHARDISPVAL0(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
+
+      TXCHARDISPVAL1(0)           => TXCHARDISPVAL1_IN,
+      TXCHARDISPVAL1(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
+      
+      TXCHARISK0(3 downto 1)    => tied_to_ground_vec_i(2 downto 0),
+      TXCHARISK0(0)             => TXCHARISK0_IN,
+      TXCHARISK1(3 downto 1)    => tied_to_ground_vec_i(2 downto 0),
+      TXCHARISK1(0)             => TXCHARISK1_IN,
+      TXENC8B10BUSE0            => tied_to_vcc_i,
+      TXENC8B10BUSE1            => tied_to_vcc_i,
+      TXKERR0                   => open,
+      TXKERR1                   => open,
+      TXRUNDISP0                => TXRUNDISP0_OUT,
+      TXRUNDISP1                => TXRUNDISP1_OUT,
+      --------------- Transmit Ports - TX Buffer and Phase Alignment -------------
+      TXBUFSTATUS0              => open,
+      TXBUFSTATUS1              => open,
+      TXENPMAPHASEALIGN0        => TXENPMAPHASEALIGN0_IN,
+      TXENPMAPHASEALIGN1        => TXENPMAPHASEALIGN1_IN,
+      TXPMASETPHASE0            => TXPMASETPHASE0_IN,
+      TXPMASETPHASE1            => TXPMASETPHASE1_IN,
+      ------------------ Transmit Ports - TX Data Path interface -----------------
+      TXDATA0                   => txdata0_i,
+      TXDATA1                   => txdata1_i,
+      TXDATAWIDTH0              => "00",
+      TXDATAWIDTH1              => "00",
+      TXOUTCLK0                 => open,
+      TXOUTCLK1                 => open,
+      TXRESET0                  => tied_to_ground_i,
+      TXRESET1                  => tied_to_ground_i,
+      TXUSRCLK0                 => TXUSRCLK0_IN,
+      TXUSRCLK1                 => TXUSRCLK1_IN,
+      TXUSRCLK20                => TXUSRCLK20_IN,
+      TXUSRCLK21                => TXUSRCLK21_IN,
+      --------------- Transmit Ports - TX Driver and OOB signalling --------------
+      TXBUFDIFFCTRL0            => "101",
+      TXBUFDIFFCTRL1            => "101",
+      TXDIFFCTRL0               => "0110",
+      TXDIFFCTRL1               => "0110",
+      TXINHIBIT0                => tied_to_ground_i,
+      TXINHIBIT1                => tied_to_ground_i,
+      TXN0                      => TXN0_OUT,
+      TXN1                      => TXN1_OUT,
+      TXP0                      => TXP0_OUT,
+      TXP1                      => TXP1_OUT,
+      TXPREEMPHASIS0            => "000",
+      TXPREEMPHASIS1            => "000",
+      --------------------- Transmit Ports - TX PRBS Generator -------------------
+      TXENPRBSTST0              => TXENPRBSTST0_IN,
+      TXENPRBSTST1              => TXENPRBSTST1_IN,
+      TXPRBSFORCEERR0           => tied_to_ground_i,
+      TXPRBSFORCEERR1           => tied_to_ground_i,
+      -------------------- Transmit Ports - TX Polarity Control ------------------
+      TXPOLARITY0               => tied_to_ground_i,
+      TXPOLARITY1               => tied_to_ground_i,
+      ----------------- Transmit Ports - TX Ports for PCI Express ----------------
+      TXDETECTRX0               => tied_to_ground_i,
+      TXDETECTRX1               => tied_to_ground_i,
+      TXELECIDLE0               => tied_to_ground_i,
+      TXELECIDLE1               => tied_to_ground_i,
+      TXPDOWNASYNCH0            => tied_to_ground_i,
+      TXPDOWNASYNCH1            => tied_to_ground_i,
+      --------------------- Transmit Ports - TX Ports for SATA -------------------
+      TXCOMSTART0               => tied_to_ground_i,
+      TXCOMSTART1               => tied_to_ground_i,
+      TXCOMTYPE0                => tied_to_ground_i,
+      TXCOMTYPE1                => tied_to_ground_i
+
+      );
+
+end RTL;
+
+
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd
new file mode 100644
index 000000000..ca7480834
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd
@@ -0,0 +1,816 @@
+-------------------------------------------------------------------------------
+-- Title      : Deterministic Xilinx GTP wrapper - Spartan-6 top module
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : wr_gtp_phy_spartan6.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2017-05-24
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Dual channel wrapper for Xilinx Spartan-6 GTP adapted for
+-- deterministic delays at 1.25 Gbps.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author    Description
+-- 2010-11-18  0.4      twlostow  Initial release
+-- 2011-02-07  0.5      twlostow  Verified on Spartan6 GTP (single channel only)
+-- 2011-05-15  0.6      twlostow  Added reference clock output
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.disparity_gen_pkg.all;
+
+entity wr_gtp_phy_spartan6 is
+
+  generic (
+    -- set to non-zero value to speed up the simulation by reducing some delays
+    g_simulation      : integer := 1;
+    g_force_disparity : integer := 0;
+    g_enable_ch0      : integer := 1;
+    g_enable_ch1      : integer := 1
+    );
+
+  port (
+    -- Port 0
+
+    -- dedicated GTP clock input
+    gtp_clk_i : in std_logic;
+
+    -- TX path, synchronous to ch0_ref_clk_i
+    ch0_ref_clk_i : in std_logic;
+
+    -- data input (8 bits, not 8b10b-encoded)
+    ch0_tx_data_i : in std_logic_vector(7 downto 0);
+
+    -- 1 when tx_data_i contains a control code, 0 when it's a data byte
+    ch0_tx_k_i : in std_logic;
+
+    -- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
+    -- Necessary for the PCS to generate proper frame termination sequences.
+    ch0_tx_disparity_o : out std_logic;
+
+    -- Encoding error indication (1 = error, 0 = no error)
+    ch0_tx_enc_err_o : out std_logic;
+
+    -- RX path, synchronous to ch0_rx_rbclk_o.
+
+    -- RX recovered clock
+    ch0_rx_rbclk_o : out std_logic;
+
+    -- 8b10b-decoded data output. The data output must be kept invalid before
+    -- the transceiver is locked on the incoming signal to prevent the EP from
+    -- detecting a false carrier.
+    ch0_rx_data_o : out std_logic_vector(7 downto 0);
+
+    -- 1 when the byte on rx_data_o is a control code
+    ch0_rx_k_o : out std_logic;
+
+    -- encoding error indication
+    ch0_rx_enc_err_o : out std_logic;
+
+    -- RX bitslide indication, indicating the delay of the RX path of the
+    -- transceiver (in UIs). Must be valid when ch0_rx_data_o is valid.
+    ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
+
+    -- reset input, active hi
+    ch0_rst_i : in std_logic;
+
+    -- local loopback enable (Tx->Rx), active hi
+    ch0_loopen_i : in std_logic;
+    ch0_loopen_vec_i : in std_logic_vector(2 downto 0) := (others=>'0');
+
+    -- PRBS select (see Xilinx UG386 Table 3-15; "000" = Standard operation, pattern generator off)
+    ch0_tx_prbs_sel_i  : in std_logic_vector(2 downto 0) := (others=>'0');
+
+    -- gtp0 ready: locked & aligned
+    ch0_rdy_o : out std_logic;
+
+-- Port 1
+    ch1_ref_clk_i : in std_logic;
+
+    ch1_tx_data_i      : in  std_logic_vector(7 downto 0) := "00000000";
+    ch1_tx_k_i         : in  std_logic                    := '0';
+    ch1_tx_disparity_o : out std_logic;
+    ch1_tx_enc_err_o   : out std_logic;
+
+    ch1_rx_data_o     : out std_logic_vector(7 downto 0);
+    ch1_rx_rbclk_o    : out std_logic;
+    ch1_rx_k_o        : out std_logic;
+    ch1_rx_enc_err_o  : out std_logic;
+    ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
+
+    ch1_rst_i    : in std_logic := '0';
+    ch1_loopen_i : in std_logic := '0';
+    ch1_loopen_vec_i : in std_logic_vector(2 downto 0) := (others=>'0');
+    ch1_tx_prbs_sel_i: in std_logic_vector(2 downto 0) := (others=>'0');
+    ch1_rdy_o    : out std_logic;
+
+-- Serial I/O
+
+    pad_txn0_o : out std_logic;
+    pad_txp0_o : out std_logic;
+
+    pad_rxn0_i : in std_logic := '0';
+    pad_rxp0_i : in std_logic := '0';
+
+    pad_txn1_o : out std_logic;
+    pad_txp1_o : out std_logic;
+
+    pad_rxn1_i : in std_logic := '0';
+    pad_rxp1_i : in std_logic := '0'
+    );
+
+
+end wr_gtp_phy_spartan6;
+
+architecture rtl of wr_gtp_phy_spartan6 is
+
+  component WHITERABBITGTP_WRAPPER_TILE_SPARTAN6
+    generic (
+      TILE_SIM_GTPRESET_SPEEDUP : integer;
+      TILE_CLK25_DIVIDER_0      : integer;
+      TILE_CLK25_DIVIDER_1      : integer;
+      TILE_PLL_DIVSEL_FB_0      : integer;
+      TILE_PLL_DIVSEL_FB_1      : integer;
+      TILE_PLL_DIVSEL_REF_0     : integer;
+      TILE_PLL_DIVSEL_REF_1     : integer;
+      TILE_PLL_SOURCE_0         : string;
+      TILE_PLL_SOURCE_1         : string);
+    port (
+      LOOPBACK0_IN          : in  std_logic_vector(2 downto 0);
+      LOOPBACK1_IN          : in  std_logic_vector(2 downto 0);
+      REFCLKOUT0_OUT        : out std_logic;
+      REFCLKOUT1_OUT        : out std_logic;
+      CLK00_IN              : in  std_logic;
+      CLK01_IN              : in  std_logic;
+      CLK10_IN              : in  std_logic;
+      CLK11_IN              : in  std_logic;
+      GTPRESET0_IN          : in  std_logic;
+      GTPRESET1_IN          : in  std_logic;
+      PLLLKDET0_OUT         : out std_logic;
+      PLLLKDET1_OUT         : out std_logic;
+      RESETDONE0_OUT        : out std_logic;
+      RESETDONE1_OUT        : out std_logic;
+      RXCHARISK0_OUT        : out std_logic;
+      RXCHARISK1_OUT        : out std_logic;
+      RXDISPERR0_OUT        : out std_logic;
+      RXDISPERR1_OUT        : out std_logic;
+      RXNOTINTABLE0_OUT     : out std_logic;
+      RXNOTINTABLE1_OUT     : out std_logic;
+      RXBYTEISALIGNED0_OUT  : out std_logic;
+      RXBYTEISALIGNED1_OUT  : out std_logic;
+      RXCOMMADET0_OUT       : out std_logic;
+      RXCOMMADET1_OUT       : out std_logic;
+      RXSLIDE0_IN           : in  std_logic;
+      RXSLIDE1_IN           : in  std_logic;
+      RXDATA0_OUT           : out std_logic_vector(7 downto 0);
+      RXDATA1_OUT           : out std_logic_vector(7 downto 0);
+      RXUSRCLK0_IN          : in  std_logic;
+      RXUSRCLK1_IN          : in  std_logic;
+      RXUSRCLK20_IN         : in  std_logic;
+      RXUSRCLK21_IN         : in  std_logic;
+      RXCDRRESET0_IN        : in  std_logic;
+      RXCDRRESET1_IN        : in  std_logic;
+      RXN0_IN               : in  std_logic;
+      RXN1_IN               : in  std_logic;
+      RXP0_IN               : in  std_logic;
+      RXP1_IN               : in  std_logic;
+      GTPCLKFBEAST_OUT      : out std_logic_vector(1 downto 0);
+      GTPCLKFBWEST_OUT      : out std_logic_vector(1 downto 0);
+      GTPCLKOUT0_OUT        : out std_logic_vector(1 downto 0);
+      GTPCLKOUT1_OUT        : out std_logic_vector(1 downto 0);
+      TXCHARISK0_IN         : in  std_logic;
+      TXCHARISK1_IN         : in  std_logic;
+      TXCHARDISPMODE0_IN    : in  std_logic;
+      TXCHARDISPMODE1_IN    : in  std_logic;
+      TXCHARDISPVAL0_IN     : in  std_logic;
+      TXCHARDISPVAL1_IN     : in  std_logic;
+      TXRUNDISP0_OUT        : out std_logic_vector(3 downto 0);
+      TXRUNDISP1_OUT        : out std_logic_vector(3 downto 0);
+      TXENPMAPHASEALIGN0_IN : in  std_logic;
+      TXENPMAPHASEALIGN1_IN : in  std_logic;
+      TXPMASETPHASE0_IN     : in  std_logic;
+      TXPMASETPHASE1_IN     : in  std_logic;
+      TXDATA0_IN            : in  std_logic_vector(7 downto 0);
+      TXDATA1_IN            : in  std_logic_vector(7 downto 0);
+      TXUSRCLK0_IN          : in  std_logic;
+      TXUSRCLK1_IN          : in  std_logic;
+      TXUSRCLK20_IN         : in  std_logic;
+      TXUSRCLK21_IN         : in  std_logic;
+      TXN0_OUT              : out std_logic;
+      TXN1_OUT              : out std_logic;
+      TXP0_OUT              : out std_logic;
+      TXP1_OUT              : out std_logic;
+      TXENPRBSTST0_IN       : in  std_logic_vector(2 downto 0);
+      TXENPRBSTST1_IN       : in  std_logic_vector(2 downto 0));
+  end component;
+
+  component gtp_phase_align
+    generic(
+      g_simulation : integer);
+    port (
+      gtp_rst_i                   : in  std_logic;
+      gtp_tx_clk_i                : in  std_logic;
+      gtp_tx_en_pma_phase_align_o : out std_logic;
+      gtp_tx_pma_set_phase_o      : out std_logic;
+      align_en_i                  : in  std_logic;
+      align_done_o                : out std_logic);
+  end component;
+
+  component gtp_bitslide
+    generic(
+      g_simulation : integer;
+      g_target     : string := "spartan6");
+    port (
+      gtp_rst_i                : in  std_logic;
+      gtp_rx_clk_i             : in  std_logic;
+      gtp_rx_comma_det_i       : in  std_logic;
+      gtp_rx_byte_is_aligned_i : in  std_logic;
+      serdes_ready_i           : in  std_logic;
+      gtp_rx_slide_o           : out std_logic;
+      gtp_rx_cdr_rst_o         : out std_logic;
+      bitslide_o               : out std_logic_vector(4 downto 0);
+      synced_o                 : out std_logic);
+  end component;
+
+  signal ch0_gtp_reset        : std_logic;
+  signal ch0_gtp_loopback     : std_logic_vector(2 downto 0) := "000";
+  signal ch0_gtp_reset_done   : std_logic;
+  signal ch0_gtp_pll_lockdet  : std_logic;
+  signal ch0_tx_pma_set_phase : std_logic                    := '0';
+
+  signal ch0_tx_rundisp_vec : std_logic_vector(3 downto 0);
+
+  signal ch0_tx_en_pma_phase_align : std_logic := '0';
+
+  signal ch0_rx_data_int                : std_logic_vector(7 downto 0);
+  signal ch0_rx_k_int                   : std_logic;
+  signal ch0_rx_disperr, ch0_rx_invcode : std_logic;
+
+  signal ch0_rx_byte_is_aligned : std_logic;
+  signal ch0_rx_comma_det       : std_logic;
+  signal ch0_rx_cdr_rst         : std_logic := '0';
+  signal ch0_rx_rec_clk_pad     : std_logic;
+  signal ch0_rx_rec_clk         : std_logic;
+  signal ch0_rx_data            : std_logic_vector(7 downto 0);
+  signal ch0_rx_k               : std_logic;
+  signal ch0_rx_enc_err         : std_logic;
+  signal ch0_rx_divclk          : std_logic;
+  signal ch0_rx_slide           : std_logic := '0';
+
+  signal ch0_gtp_locked : std_logic;
+  signal ch0_align_done : std_logic;
+  signal ch0_rx_synced  : std_logic;
+
+  signal ch0_gtp_clkout_int                                : std_logic_vector(1 downto 0);
+  signal ch0_rx_enable_output, ch0_rx_enable_output_synced : std_logic;
+
+
+  signal ch1_gtp_reset        : std_logic;
+  signal ch1_gtp_loopback     : std_logic_vector(2 downto 0) := "000";
+  signal ch1_gtp_reset_done   : std_logic;
+  signal ch1_gtp_pll_lockdet  : std_logic;
+  signal ch1_tx_pma_set_phase : std_logic                    := '0';
+
+  signal ch1_tx_rundisp_vec : std_logic_vector(3 downto 0);
+
+  signal ch1_tx_en_pma_phase_align : std_logic := '0';
+
+  signal ch1_rx_data_int                : std_logic_vector(7 downto 0);
+  signal ch1_rx_k_int                   : std_logic;
+  signal ch1_rx_disperr, ch1_rx_invcode : std_logic;
+
+  signal ch1_rx_byte_is_aligned : std_logic;
+  signal ch1_rx_comma_det       : std_logic;
+  signal ch1_rx_cdr_rst         : std_logic := '0';
+  signal ch1_rx_rec_clk_pad     : std_logic;
+  signal ch1_rx_rec_clk         : std_logic;
+  signal ch1_rx_data            : std_logic_vector(7 downto 0);
+  signal ch1_rx_k               : std_logic;
+  signal ch1_rx_enc_err         : std_logic;
+  
+  signal ch1_rx_divclk          : std_logic;
+  signal ch1_rx_slide           : std_logic := '0';
+
+  signal ch1_gtp_locked : std_logic;
+  signal ch1_align_done : std_logic;
+  signal ch1_rx_synced  : std_logic;
+
+  signal ch1_gtp_clkout_int                                : std_logic_vector(1 downto 0);
+  signal ch1_rx_enable_output, ch1_rx_enable_output_synced : std_logic;
+
+  signal ch0_rst_synced    : std_logic;
+  signal ch0_rst_d0        : std_logic;
+  signal ch0_reset_counter : unsigned(9 downto 0);
+
+  signal ch1_rst_synced    : std_logic;
+  signal ch1_rst_d0        : std_logic;
+  signal ch1_reset_counter : unsigned(9 downto 0);
+
+  signal ch0_rx_bitslide_int : std_logic_vector(4 downto 0);
+  signal ch1_rx_bitslide_int : std_logic_vector(4 downto 0);
+
+  signal ch0_ref_clk_in : std_logic_vector(1 downto 0);
+  signal ch1_ref_clk_in : std_logic_vector(1 downto 0);
+
+
+  signal ch0_disparity_set : std_logic;
+  signal ch1_disparity_set : std_logic;
+
+  signal ch0_tx_chardispmode : std_logic;
+  signal ch1_tx_chardispmode : std_logic;
+
+  signal ch0_tx_chardispval : std_logic;
+  signal ch1_tx_chardispval : std_logic;
+
+
+
+  component enc_8b10b
+    port (
+      clk_i     : in  std_logic;
+      rst_n_i   : in  std_logic;
+      ctrl_i    : in  std_logic;
+      in_8b_i   : in  std_logic_vector(7 downto 0);
+      err_o     : out std_logic;
+      dispar_o  : out std_logic;
+      out_10b_o : out std_logic_vector(9 downto 0));
+  end component;
+
+  signal ch0_rst_n : std_logic;
+  signal ch1_rst_n : std_logic;
+
+  signal ch0_cur_disp  : t_8b10b_disparity;
+  signal ch0_disp_pipe : std_logic_vector(1 downto 0);
+  signal ch1_cur_disp  : t_8b10b_disparity;
+  signal ch1_disp_pipe : std_logic_vector(1 downto 0);
+  
+begin  -- rtl
+  -------------------------------------------------------------------------------
+  -- Channel 0 logic
+  -------------------------------------------------------------------------------
+
+  gen_with_channel0 : if(g_enable_ch0 /= 0) generate
+    ch0_rst_n          <= not ch0_gtp_reset;
+    ch0_tx_disparity_o <= ch0_disp_pipe(0);
+
+    ch0_gtp_reset      <= ch0_rst_synced or std_logic(not ch0_reset_counter(ch0_reset_counter'left));
+    ch0_rx_rec_clk_pad <= ch0_gtp_clkout_int(1);
+    ch0_ref_clk_in(0)  <= gtp_clk_i;
+    ch0_ref_clk_in(1)  <= '0';
+    -- Near-end PMA loopback or loopback selected with ch1_loopen_vec_i
+    ch0_gtp_loopback <= "010" when(ch0_loopen_i = '1') else
+                        ch0_loopen_vec_i;
+
+    gen_disp_ch0 : process(ch0_ref_clk_i)
+    begin
+      if rising_edge(ch0_ref_clk_i) then
+        if(ch0_tx_chardispmode = '1' or ch0_rst_n = '0') then
+          if(g_force_disparity = 0) then
+            ch0_cur_disp <= RD_MINUS;
+          else
+            ch0_cur_disp <= RD_PLUS;
+          end if;
+          ch0_disp_pipe <= (others => '0');
+        else
+          ch0_cur_disp     <= f_next_8b10b_disparity8(ch0_cur_disp, ch0_tx_k_i, ch0_tx_data_i);
+          ch0_disp_pipe(0) <= to_std_logic(ch0_cur_disp);
+          ch0_disp_pipe(1) <= ch0_disp_pipe(0);
+        end if;
+      end if;
+    end process;
+
+
+    p_gen_reset_ch0 : process(ch0_ref_clk_i)
+    begin
+      if rising_edge(ch0_ref_clk_i) then
+
+        ch0_rst_d0     <= ch0_rst_i;
+        ch0_rst_synced <= ch0_rst_d0;
+
+        if(ch0_rst_synced = '1') then
+          ch0_reset_counter <= (others => '0');
+        else
+          if(ch0_reset_counter(ch0_reset_counter'left) = '0') then
+            ch0_reset_counter <= ch0_reset_counter + 1;
+          end if;
+        end if;
+      end if;
+    end process;
+
+
+    U_Rbclk_buf_ch0 : BUFIO2
+      port map (
+        DIVCLK       => ch0_rx_divclk,
+        IOCLK        => open,
+        SERDESSTROBE => open,
+        I            => ch0_rx_rec_clk_pad);
+
+    U_Rbclk_bufg_ch0 : BUFG
+      port map (
+        I => ch0_rx_divclk,
+        O => ch0_rx_rec_clk
+        );
+
+    ch0_gtp_locked   <= ch0_gtp_pll_lockdet and ch0_gtp_reset_done;
+    ch0_tx_enc_err_o <= '0';
+
+    U_align_ch0 : gtp_phase_align
+      generic map (
+        g_simulation => g_simulation) 
+      port map (
+        gtp_rst_i                   => ch0_gtp_reset,
+        gtp_tx_clk_i                => ch0_ref_clk_i,
+        gtp_tx_en_pma_phase_align_o => ch0_tx_en_pma_phase_align,
+        gtp_tx_pma_set_phase_o      => ch0_tx_pma_set_phase,
+        align_en_i                  => ch0_gtp_locked,
+        align_done_o                => ch0_align_done);
+
+    U_bitslide_ch0 : gtp_bitslide
+      generic map (
+        g_simulation => g_simulation)
+      port map (
+        gtp_rst_i                => ch0_gtp_reset,
+        gtp_rx_clk_i             => ch0_rx_rec_clk,
+        gtp_rx_comma_det_i       => ch0_rx_comma_det,
+        gtp_rx_byte_is_aligned_i => ch0_rx_byte_is_aligned,
+        serdes_ready_i           => ch0_gtp_locked,
+        gtp_rx_slide_o           => ch0_rx_slide,
+        gtp_rx_cdr_rst_o         => ch0_rx_cdr_rst,
+        bitslide_o               => ch0_rx_bitslide_int,
+        synced_o                 => ch0_rx_synced);
+
+    ch0_rx_bitslide_o    <= ch0_rx_bitslide_int(3 downto 0);
+    ch0_rx_enable_output <= ch0_rx_synced and ch0_align_done;
+
+    U_sync_oen_ch0 : gc_sync_ffs
+      generic map (
+        g_sync_edge => "positive")
+      port map (
+        clk_i    => ch0_rx_rec_clk,
+        rst_n_i  => '1',
+        data_i   => ch0_rx_enable_output,
+        synced_o => ch0_rx_enable_output_synced,
+        npulse_o => open,
+        ppulse_o => open);
+
+    p_force_proper_disparity_ch0 : process(ch0_ref_clk_i, ch0_gtp_reset)
+    begin
+      if (ch0_gtp_reset = '1') then
+        ch0_disparity_set   <= '0';
+        ch0_tx_chardispval  <= '0';
+        ch0_tx_chardispmode <= '0';
+      elsif rising_edge(ch0_ref_clk_i) then
+        if(ch0_disparity_set = '0' and ch0_tx_k_i = '1' and ch0_tx_data_i = x"bc" and ch0_align_done = '1') then
+          ch0_disparity_set <= '1';
+          if(g_force_disparity = 0) then
+            ch0_tx_chardispval <= '0';
+          else
+            ch0_tx_chardispval <= '1';
+          end if;
+          ch0_tx_chardispmode <= '1';
+        else
+          ch0_tx_chardispmode <= '0';
+          ch0_tx_chardispval  <= '0';
+        end if;
+      end if;
+    end process;
+
+    p_gen_output_ch0 : process(ch0_rx_rec_clk, ch0_gtp_reset)
+    begin
+      if(ch0_gtp_reset = '1') then
+        ch0_rx_data      <= (others => '0');
+        ch0_rx_k         <= '0';
+        ch0_rx_enc_err   <= '0';
+        
+      elsif rising_edge(ch0_rx_rec_clk) then
+        if(ch0_rx_enable_output_synced = '0') then
+-- make sure the output data is invalid when the link is down and that it will
+-- trigger the sync loss detection
+          ch0_rx_data      <= (others => '0');
+          ch0_rx_k         <= '1';
+          ch0_rx_enc_err   <= '1';
+        else
+          ch0_rx_data      <= ch0_rx_data_int;
+          ch0_rx_k         <= ch0_rx_k_int;
+          ch0_rx_enc_err   <= ch0_rx_disperr or ch0_rx_invcode;
+        end if;
+      end if;
+    end process;
+
+
+-- drive the recovered clock output
+    ch0_rx_rbclk_o <= ch0_rx_rec_clk;
+    -- drive ch0 ready indicator as well
+    ch0_rdy_o <= ch0_rx_enable_output_synced;
+    -- Note that the above clock assignment takes one delta delay in a simulator.
+    -- In order to keep clock and data signals aligned, re-assign rx_data, rx_k
+    -- and rx_enc_err (also adding one delta delay). This is purely necessary for
+    -- proper simulation only.
+    ch0_rx_data_o    <= ch0_rx_data;
+    ch0_rx_k_o       <= ch0_rx_k;
+    ch0_rx_enc_err_o <= ch0_rx_enc_err;
+  end generate gen_with_channel0;
+
+  -------------------------------------------------------------------------------
+  -- Channel 1 logic
+  -------------------------------------------------------------------------------
+
+  gen_with_channel1 : if(g_enable_ch1 /= 0) generate
+
+    ch1_rst_n          <= not ch1_gtp_reset;
+    ch1_tx_disparity_o <= ch1_disp_pipe(1);
+
+    ch1_gtp_reset      <= ch1_rst_synced or std_logic(not ch1_reset_counter(ch1_reset_counter'left));
+    ch1_rx_rec_clk_pad <= ch1_gtp_clkout_int(1);
+    ch1_ref_clk_in(0)  <= gtp_clk_i;
+    ch1_ref_clk_in(1)  <= '0';
+    -- Near-end PMA loopback or loopback selected with ch1_loopen_vec_i
+    ch1_gtp_loopback <= "010" when(ch1_loopen_i = '1') else
+                        ch1_loopen_vec_i;
+
+    gen_disp_ch1 : process(ch1_ref_clk_i)
+    begin
+      if rising_edge(ch1_ref_clk_i) then
+        if(ch1_tx_chardispmode = '1' or ch1_rst_n = '0') then
+          if(g_force_disparity = 0) then
+            ch1_cur_disp <= RD_MINUS;
+          else
+            ch1_cur_disp <= RD_PLUS;
+          end if;
+          ch1_disp_pipe <= (others => '0');
+        else
+          ch1_cur_disp     <= f_next_8b10b_disparity8(ch1_cur_disp, ch1_tx_k_i, ch1_tx_data_i);
+          ch1_disp_pipe(0) <= to_std_logic(ch1_cur_disp);
+          ch1_disp_pipe(1) <= ch1_disp_pipe(0);
+        end if;
+      end if;
+    end process;
+
+    p_gen_reset_ch1 : process(ch1_ref_clk_i)
+    begin
+      if rising_edge(ch1_ref_clk_i) then
+
+        ch1_rst_d0     <= ch1_rst_i;
+        ch1_rst_synced <= ch1_rst_d0;
+
+        if(ch1_rst_synced = '1') then
+          ch1_reset_counter <= (others => '0');
+        else
+          if(ch1_reset_counter(ch1_reset_counter'left) = '0') then
+            ch1_reset_counter <= ch1_reset_counter + 1;
+          end if;
+        end if;
+      end if;
+    end process;
+
+    U_Rbclk_buf_ch1 : BUFIO2
+      port map (
+        DIVCLK       => ch1_rx_divclk,
+        IOCLK        => open,
+        SERDESSTROBE => open,
+        I            => ch1_rx_rec_clk_pad);
+
+    U_Rbclk_bufg_ch1 : BUFG
+      port map (
+        I => ch1_rx_divclk,
+        O => ch1_rx_rec_clk
+        );
+
+    ch1_gtp_locked   <= ch1_gtp_pll_lockdet and ch1_gtp_reset_done;
+    ch1_tx_enc_err_o <= '0';
+
+    U_align_ch1 : gtp_phase_align
+      generic map (
+        g_simulation => g_simulation) 
+      port map (
+        gtp_rst_i                   => ch1_gtp_reset,
+        gtp_tx_clk_i                => ch1_ref_clk_i,
+        gtp_tx_en_pma_phase_align_o => ch1_tx_en_pma_phase_align,
+        gtp_tx_pma_set_phase_o      => ch1_tx_pma_set_phase,
+        align_en_i                  => ch1_gtp_locked,
+        align_done_o                => ch1_align_done);
+
+    U_bitslide_ch1 : gtp_bitslide
+      generic map (
+        g_simulation => g_simulation)
+      port map (
+        gtp_rst_i                => ch1_gtp_reset,
+        gtp_rx_clk_i             => ch1_rx_rec_clk,
+        gtp_rx_comma_det_i       => ch1_rx_comma_det,
+        gtp_rx_byte_is_aligned_i => ch1_rx_byte_is_aligned,
+        serdes_ready_i           => ch1_gtp_locked,
+        gtp_rx_slide_o           => ch1_rx_slide,
+        gtp_rx_cdr_rst_o         => ch1_rx_cdr_rst,
+        bitslide_o               => ch1_rx_bitslide_int,
+        synced_o                 => ch1_rx_synced);
+
+    ch1_rx_bitslide_o    <= ch1_rx_bitslide_int(3 downto 0);
+    ch1_rx_enable_output <= ch1_rx_synced and ch1_align_done;
+
+    U_sync_oen_ch1 : gc_sync_ffs
+      generic map (
+        g_sync_edge => "positive")
+      port map (
+        clk_i    => ch1_rx_rec_clk,
+        rst_n_i  => '1',
+        data_i   => ch1_rx_enable_output,
+        synced_o => ch1_rx_enable_output_synced,
+        npulse_o => open,
+        ppulse_o => open);
+
+    p_force_proper_disparity_ch1 : process(ch1_ref_clk_i, ch1_gtp_reset)
+    begin
+      if (ch1_gtp_reset = '1') then
+        ch1_disparity_set   <= '0';
+        ch1_tx_chardispval  <= '0';
+        ch1_tx_chardispmode <= '0';
+        
+      elsif rising_edge(ch1_ref_clk_i) then
+        if(ch1_disparity_set = '0' and ch1_tx_k_i = '1' and ch1_tx_data_i = x"bc" and ch1_align_done = '1') then
+          ch1_disparity_set <= '1';
+          if(g_force_disparity = 0) then
+            ch1_tx_chardispval <= '0';
+          else
+            ch1_tx_chardispval <= '1';
+          end if;
+          ch1_tx_chardispmode <= '1';
+        else
+          ch1_tx_chardispmode <= '0';
+          ch1_tx_chardispval  <= '0';
+        end if;
+      end if;
+    end process;
+
+    p_gen_output_ch1 : process(ch1_rx_rec_clk, ch1_rst_i)
+    begin
+      if(ch1_rst_i = '1') then
+        ch1_rx_data    <= (others => '0');
+        ch1_rx_k       <= '0';
+        ch1_rx_enc_err <= '0';
+        
+      elsif rising_edge(ch1_rx_rec_clk) then
+        if(ch1_rx_enable_output_synced = '0') then
+-- make sure the output data is invalid when the link is down and that it will
+-- trigger the sync loss detection
+          ch1_rx_data    <= (others => '0');
+          ch1_rx_k       <= '1';
+          ch1_rx_enc_err <= '1';
+        else
+          ch1_rx_data    <= ch1_rx_data_int;
+          ch1_rx_k       <= ch1_rx_k_int;
+          ch1_rx_enc_err <= ch1_rx_disperr or ch1_rx_invcode;
+        end if;
+      end if;
+    end process;
+
+    ch1_rx_rbclk_o <= ch1_rx_rec_clk;
+    ch1_rdy_o <= ch1_rx_enable_output_synced;
+    -- Note that the above clock assignment takes one delta delay in a simulator.
+    -- In order to keep clock and data signals aligned, re-assign rx_data, rx_k
+    -- and rx_enc_err (also adding one delta delay). This is purely necessary for
+    -- proper simulation only.
+    ch1_rx_data_o    <= ch1_rx_data;
+    ch1_rx_k_o       <= ch1_rx_k;
+    ch1_rx_enc_err_o <= ch1_rx_enc_err;
+  end generate gen_with_channel1;
+
+  U_GTP_TILE_INST : WHITERABBITGTP_WRAPPER_TILE_SPARTAN6
+    generic map
+    (
+      TILE_SIM_GTPRESET_SPEEDUP => g_simulation,  -- Set to 1 to speed up sim reset
+      TILE_CLK25_DIVIDER_0      => 5,
+      TILE_CLK25_DIVIDER_1      => 5,
+      TILE_PLL_DIVSEL_FB_0      => 2,
+      TILE_PLL_DIVSEL_FB_1      => 2,
+      TILE_PLL_DIVSEL_REF_0     => 1,
+      TILE_PLL_DIVSEL_REF_1     => 1,
+
+      -- 
+      TILE_PLL_SOURCE_0 => "PLL0",
+      TILE_PLL_SOURCE_1 => "PLL1"
+      )
+    port map
+    (
+      ------------------------ Loopback and Powerdown Ports ----------------------
+      LOOPBACK0_IN => ch0_gtp_loopback,
+      LOOPBACK1_IN => ch1_gtp_loopback,
+      --------------------------------- PLL Ports --------------------------------
+
+      REFCLKOUT0_OUT => open,
+      REFCLKOUT1_OUT => open,
+      CLK00_IN       => ch0_ref_clk_in(0),
+      CLK01_IN       => ch1_ref_clk_in(0),
+      CLK10_IN       => ch0_ref_clk_in(1),
+      CLK11_IN       => ch1_ref_clk_in(1),
+      GTPRESET0_IN   => ch0_gtp_reset,
+      GTPRESET1_IN   => ch1_gtp_reset,
+      PLLLKDET0_OUT  => ch0_gtp_pll_lockdet,
+      PLLLKDET1_OUT  => ch1_gtp_pll_lockdet,
+      RESETDONE0_OUT => ch0_gtp_reset_done,
+      RESETDONE1_OUT => ch1_gtp_reset_done,
+
+      ----------------------- Receive Ports - 8b10b Decoder ----------------------
+      RXCHARISK0_OUT    => ch0_rx_k_int,
+      RXCHARISK1_OUT    => ch1_rx_k_int,
+      RXDISPERR0_OUT    => ch0_rx_disperr,
+      RXDISPERR1_OUT    => ch1_rx_disperr,
+      RXNOTINTABLE0_OUT => ch0_rx_invcode,
+      RXNOTINTABLE1_OUT => ch1_rx_invcode,
+
+      --------------- Receive Ports - Comma Detection and Alignment --------------
+      RXBYTEISALIGNED0_OUT => ch0_rx_byte_is_aligned,
+      RXBYTEISALIGNED1_OUT => ch1_rx_byte_is_aligned,
+      RXCOMMADET0_OUT      => ch0_rx_comma_det,
+      RXCOMMADET1_OUT      => ch1_rx_comma_det,
+      RXSLIDE0_IN          => ch0_rx_slide,
+      RXSLIDE1_IN          => ch1_rx_slide,
+
+      ------------------- Receive Ports - RX Data Path interface -----------------
+      RXDATA0_OUT   => ch0_rx_data_int,
+      RXDATA1_OUT   => ch1_rx_data_int,
+      RXUSRCLK0_IN  => ch0_rx_rec_clk,
+      RXUSRCLK1_IN  => ch1_rx_rec_clk,
+      RXUSRCLK20_IN => ch0_rx_rec_clk,
+      RXUSRCLK21_IN => ch1_rx_rec_clk,
+
+      ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+      RXCDRRESET0_IN => ch0_rx_cdr_rst,
+      RXCDRRESET1_IN => ch1_rx_cdr_rst,
+      RXN0_IN        => pad_rxn0_i,
+      RXN1_IN        => pad_rxn1_i,
+      RXP0_IN        => pad_rxp0_i,
+      RXP1_IN        => pad_rxp1_i,
+
+      ---------------------------- TX/RX Datapath Ports --------------------------
+      GTPCLKFBEAST_OUT => open,
+      GTPCLKFBWEST_OUT => open,
+      GTPCLKOUT0_OUT   => ch0_gtp_clkout_int,
+      GTPCLKOUT1_OUT   => ch1_gtp_clkout_int,
+      ------------------- Transmit Ports - 8b10b Encoder Control -----------------
+      TXCHARISK0_IN    => ch0_tx_k_i,
+      TXCHARISK1_IN    => ch1_tx_k_i,
+      TXRUNDISP0_OUT   => ch0_tx_rundisp_vec,
+      TXRUNDISP1_OUT   => ch1_tx_rundisp_vec,
+
+      TXCHARDISPMODE0_IN => ch0_tx_chardispmode,
+      TXCHARDISPMODE1_IN => ch1_tx_chardispmode,
+      TXCHARDISPVAL0_IN  => ch0_tx_chardispval,
+      TXCHARDISPVAL1_IN  => ch1_tx_chardispval,
+
+      --------------- Transmit Ports - TX Buffer and Phase Alignment -------------
+      TXENPMAPHASEALIGN0_IN => ch0_tx_en_pma_phase_align,
+      TXENPMAPHASEALIGN1_IN => ch1_tx_en_pma_phase_align,
+      TXPMASETPHASE0_IN     => ch0_tx_pma_set_phase,
+      TXPMASETPHASE1_IN     => ch1_tx_pma_set_phase,
+      ------------------ Transmit Ports - TX Data Path interface -----------------
+      TXDATA0_IN            => ch0_tx_data_i,
+      TXDATA1_IN            => ch1_tx_data_i,
+      TXUSRCLK0_IN          => ch0_ref_clk_i,
+      TXUSRCLK1_IN          => ch1_ref_clk_i,
+      TXUSRCLK20_IN         => ch0_ref_clk_i,
+      TXUSRCLK21_IN         => ch1_ref_clk_i,
+      --------------- Transmit Ports - TX Driver and OOB signalling --------------
+      TXN0_OUT              => pad_txn0_o,
+      TXN1_OUT              => pad_txn1_o,
+      TXP0_OUT              => pad_txp0_o,
+      TXP1_OUT              => pad_txp1_o,
+      --------------- Transmit Ports - TX PRBS Generator -------------------------
+      TXENPRBSTST0_IN       => ch0_tx_prbs_sel_i,
+      TXENPRBSTST1_IN       => ch1_tx_prbs_sel_i
+
+      );
+
+
+end rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_xilinx_pkg.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_xilinx_pkg.vhd
new file mode 100644
index 000000000..5f9f76415
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_xilinx_pkg.vhd
@@ -0,0 +1,192 @@
+-------------------------------------------------------------------------------
+-- Title      : Platform-dependent components needed for WR PTP Core on Xilinx
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : wr_xilinx_pkg.vhd
+-- Author     : Maciej Lipinski, Grzegorz Daniluk, Dimitrios Lampridis
+-- Company    : CERN
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2016-2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.endpoint_pkg.all;
+
+package wr_xilinx_pkg is
+
+  component xwrc_platform_xilinx is
+    generic (
+      g_fpga_family               : string  := "spartan6";
+      g_with_external_clock_input : boolean := FALSE;
+      g_use_default_plls          : boolean := TRUE;
+      g_gtp_enable_ch0            : integer := 0;
+      g_gtp_enable_ch1            : integer := 1;
+      g_simulation                : integer := 0;
+      g_use_ibufgds               : boolean := false);
+    port (
+      areset_n_i            : in  std_logic             := '1';
+      clk_10m_ext_i         : in  std_logic             := '0';
+      clk_125m_gtp_p_i      : in  std_logic;
+      clk_125m_gtp_n_i      : in  std_logic;
+      clk_20m_vcxo_i        : in  std_logic             := '0';
+      clk_125m_pllref_i     : in  std_logic             := '0';
+      clk_125m_dmtd_i       : in  std_logic             := '0';
+      clk_62m5_dmtd_i       : in  std_logic             := '0';
+      clk_dmtd_locked_i     : in  std_logic             := '1';
+      clk_62m5_sys_i        : in  std_logic             := '0';
+      clk_sys_locked_i      : in  std_logic             := '1';
+      clk_125m_ref_i        : in  std_logic             := '0';
+      clk_ref_locked_i      : in  std_logic             := '1';
+      clk_125m_ext_i        : in  std_logic             := '0';
+      clk_ext_locked_i      : in  std_logic             := '1';
+      clk_ext_stopped_i     : in  std_logic             := '0';
+      clk_ext_rst_o         : out std_logic;
+      sfp_txn_o             : out std_logic;
+      sfp_txp_o             : out std_logic;
+      sfp_rxn_i             : in  std_logic;
+      sfp_rxp_i             : in  std_logic;
+      sfp_tx_fault_i        : in  std_logic             := '0';
+      sfp_los_i             : in  std_logic             := '0';
+      sfp_tx_disable_o      : out std_logic;
+      clk_62m5_sys_o        : out std_logic;
+      clk_125m_ref_o        : out std_logic;
+      clk_ref_locked_o      : out std_logic;
+      clk_62m5_dmtd_o       : out std_logic;
+      pll_locked_o          : out std_logic;
+      clk_10m_ext_o         : out std_logic;
+      phy8_o                : out t_phy_8bits_to_wrc;
+      phy8_i                : in  t_phy_8bits_from_wrc  := c_dummy_phy8_from_wrc;
+      phy16_o               : out t_phy_16bits_to_wrc;
+      phy16_i               : in  t_phy_16bits_from_wrc := c_dummy_phy16_from_wrc;
+      ext_ref_mul_o         : out std_logic;
+      ext_ref_mul_locked_o  : out std_logic;
+      ext_ref_mul_stopped_o : out std_logic;
+      ext_ref_rst_i         : in  std_logic             := '0');
+  end component xwrc_platform_xilinx;
+
+  component wr_gtp_phy_spartan6
+    generic (
+      g_enable_ch0 : integer := 1;
+      g_enable_ch1 : integer := 1;
+      g_simulation : integer := 0);
+    port (
+      gtp_clk_i          : in  std_logic;
+      ch0_ref_clk_i      : in  std_logic                    := '0';
+      ch0_tx_data_i      : in  std_logic_vector(7 downto 0) := "00000000";
+      ch0_tx_k_i         : in  std_logic                    := '0';
+      ch0_tx_disparity_o : out std_logic;
+      ch0_tx_enc_err_o   : out std_logic;
+      ch0_rx_rbclk_o     : out std_logic;
+      ch0_rx_data_o      : out std_logic_vector(7 downto 0);
+      ch0_rx_k_o         : out std_logic;
+      ch0_rx_enc_err_o   : out std_logic;
+      ch0_rx_bitslide_o  : out std_logic_vector(3 downto 0);
+      ch0_rst_i          : in  std_logic                    := '0';
+      ch0_loopen_i       : in  std_logic                    := '0';
+      ch0_loopen_vec_i   : in  std_logic_vector(2 downto 0) := (others => '0');
+      ch0_tx_prbs_sel_i  : in  std_logic_vector(2 downto 0) := (others => '0');
+      ch0_rdy_o          : out std_logic;
+      ch1_ref_clk_i      : in  std_logic;
+      ch1_tx_data_i      : in  std_logic_vector(7 downto 0) := "00000000";
+      ch1_tx_k_i         : in  std_logic                    := '0';
+      ch1_tx_disparity_o : out std_logic;
+      ch1_tx_enc_err_o   : out std_logic;
+      ch1_rx_data_o      : out std_logic_vector(7 downto 0);
+      ch1_rx_rbclk_o     : out std_logic;
+      ch1_rx_k_o         : out std_logic;
+      ch1_rx_enc_err_o   : out std_logic;
+      ch1_rx_bitslide_o  : out std_logic_vector(3 downto 0);
+      ch1_rst_i          : in  std_logic                    := '0';
+      ch1_loopen_i       : in  std_logic                    := '0';
+      ch1_loopen_vec_i   : in  std_logic_vector(2 downto 0) := (others => '0');
+      ch1_tx_prbs_sel_i  : in  std_logic_vector(2 downto 0) := (others => '0');
+      ch1_rdy_o          : out std_logic;
+      pad_txn0_o         : out std_logic;
+      pad_txp0_o         : out std_logic;
+      pad_rxn0_i         : in  std_logic                    := '0';
+      pad_rxp0_i         : in  std_logic                    := '0';
+      pad_txn1_o         : out std_logic;
+      pad_txp1_o         : out std_logic;
+      pad_rxn1_i         : in  std_logic                    := '0';
+      pad_rxp1_i         : in  std_logic                    := '0');
+  end component;
+
+  component wr_gtx_phy_family7 is
+    generic (
+      -- set to non-zero value to speed up the simulation by reducing some delays
+      g_simulation : integer := 0);
+    port (
+      clk_gtx_i      : in  std_logic;
+      tx_out_clk_o   : out std_logic;
+      tx_locked_o    : out std_logic;
+      tx_data_i      : in  std_logic_vector(15 downto 0);
+      tx_k_i         : in  std_logic_vector(1 downto 0);
+      tx_disparity_o : out std_logic;
+      tx_enc_err_o   : out std_logic;
+      rx_rbclk_o     : out std_logic;
+      rx_data_o      : out std_logic_vector(15 downto 0);
+      rx_k_o         : out std_logic_vector(1 downto 0);
+      rx_enc_err_o   : out std_logic;
+      rx_bitslide_o  : out std_logic_vector(4 downto 0);
+      rst_i          : in  std_logic;
+      loopen_i       : in  std_logic_vector(2 downto 0);
+      tx_prbs_sel_i  : in  std_logic_vector(2 downto 0);
+      pad_txn_o      : out std_logic;
+      pad_txp_o      : out std_logic;
+      pad_rxn_i      : in  std_logic := '0';
+      pad_rxp_i      : in  std_logic := '0';
+      rdy_o          : out std_logic);
+  end component;
+
+  component wr_gtp_phy_family7 is
+    generic (
+      -- set to non-zero value to speed up the simulation by reducing some delays
+      g_simulation : integer := 0);
+    port (
+      clk_gtp_i      : in  std_logic;
+      tx_out_clk_o   : out std_logic;
+      tx_locked_o    : out std_logic;
+      tx_data_i      : in  std_logic_vector(15 downto 0);
+      tx_k_i         : in  std_logic_vector(1 downto 0);
+      tx_disparity_o : out std_logic;
+      tx_enc_err_o   : out std_logic;
+      rx_rbclk_o     : out std_logic;
+      rx_data_o      : out std_logic_vector(15 downto 0);
+      rx_k_o         : out std_logic_vector(1 downto 0);
+      rx_enc_err_o   : out std_logic;
+      rx_bitslide_o  : out std_logic_vector(4 downto 0);
+      rst_i          : in  std_logic;
+      loopen_i       : in  std_logic_vector(2 downto 0);
+      tx_prbs_sel_i  : in  std_logic_vector(2 downto 0);
+      pad_txn_o      : out std_logic;
+      pad_txp_o      : out std_logic;
+      pad_rxn_i      : in  std_logic := '0';
+      pad_rxp_i      : in  std_logic := '0';
+      rdy_o          : out std_logic);
+  end component;
+
+end wr_xilinx_pkg;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/xwrc_platform_xilinx.vhd b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/xwrc_platform_xilinx.vhd
new file mode 100644
index 000000000..c36d7c3c1
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/xwrc_platform_xilinx.vhd
@@ -0,0 +1,1095 @@
+-------------------------------------------------------------------------------
+-- Title      : Platform-dependent components needed for WR PTP Core on Xilinx
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : wrc_platform_xilinx.vhd
+-- Author     : Maciej Lipinski, Grzegorz Daniluk, Dimitrios Lampridis
+-- Company    : CERN
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description:
+-- This module instantiates platform-specific modules that are needed by the
+-- WR PTP Core (WRPC) to interface hardware on Xilinx FPGA. In particular it
+-- contains:
+-- * PHY
+-- * PLLs
+-- * buffers
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2016-2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.endpoint_pkg.all;
+use work.gencores_pkg.all;
+use work.wr_xilinx_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity xwrc_platform_xilinx is
+  generic
+    (
+      -- Define the family/model of Xilinx FPGA
+      -- (supported: for now only spartan6)
+      g_fpga_family               : string  := "spartan6";
+      -- Select whether to include external ref clock input
+      g_with_external_clock_input : boolean := FALSE;
+      -- Set to FALSE if you want to instantiate your own PLLs
+      g_use_default_plls          : boolean := TRUE;
+      -- Select GTP channel to use (only one can be active)
+      g_gtp_enable_ch0            : integer := 0;
+      g_gtp_enable_ch1            : integer := 1;
+      -- Set to TRUE will speed up some initialization processes
+      g_simulation                : integer := 0;
+      g_use_ibufgds               : boolean := false
+      );
+  port (
+    ---------------------------------------------------------------------------
+    -- Asynchronous reset (active low)
+    ---------------------------------------------------------------------------
+    areset_n_i            : in  std_logic;
+    ---------------------------------------------------------------------------
+    -- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
+    ---------------------------------------------------------------------------
+    clk_10m_ext_i         : in  std_logic             := '0';
+    ---------------------------------------------------------------------------
+    -- 125 MHz GTP/GTX reference
+    -- If g_use_ibufgds=false then connect buffered clock to clk_125m_gtp_p_i
+    ---------------------------------------------------------------------------
+    clk_125m_gtp_p_i      : in  std_logic;
+    clk_125m_gtp_n_i      : in  std_logic;
+    ---------------------------------------------------------------------------
+    -- Clock inputs for default PLLs (g_use_default_plls = TRUE)
+    ---------------------------------------------------------------------------
+    -- 20MHz VCXO clock
+    clk_20m_vcxo_i        : in  std_logic             := '0';
+    -- 125.000 MHz PLL reference
+    clk_125m_pllref_i     : in  std_logic             := '0';
+    -- 124.992 MHz DMTD reference (CLBv3 reference design)
+    clk_125m_dmtd_i       : in  std_logic             := '0';
+    ---------------------------------------------------------------------------
+    -- Clock inputs from custom PLLs (g_use_default_plls = FALSE)
+    ---------------------------------------------------------------------------
+    -- 62.5MHz DMTD offset clock and lock status
+    clk_62m5_dmtd_i       : in  std_logic             := '0';
+    clk_dmtd_locked_i     : in  std_logic             := '1';
+    -- 62.5MHz Main system clock and lock status
+    clk_62m5_sys_i        : in  std_logic             := '0';
+    clk_sys_locked_i      : in  std_logic             := '1';
+    -- 125MHz  Reference clock
+    clk_125m_ref_i        : in  std_logic             := '0';
+    clk_ref_locked_i      : in  std_logic             := '1';
+    -- 125MHz derived from 10MHz external reference and lock status
+    -- (when g_with_external_clock_input = TRUE)
+    clk_125m_ext_i        : in  std_logic             := '0';
+    clk_ext_locked_i      : in  std_logic             := '1';
+    clk_ext_stopped_i     : in  std_logic             := '0';
+    clk_ext_rst_o         : out std_logic;
+    ---------------------------------------------------------------------------
+    -- SFP
+    ---------------------------------------------------------------------------
+    sfp_txn_o             : out std_logic;
+    sfp_txp_o             : out std_logic;
+    sfp_rxn_i             : in  std_logic;
+    sfp_rxp_i             : in  std_logic;
+    sfp_tx_fault_i        : in  std_logic             := '0';
+    sfp_los_i             : in  std_logic             := '0';
+    sfp_tx_disable_o      : out std_logic;
+    ---------------------------------------------------------------------------
+    --Interface to WR PTP Core (WRPC)
+    ---------------------------------------------------------------------------
+    -- PLL outputs
+    clk_62m5_sys_o        : out std_logic;
+    clk_125m_ref_o        : out std_logic;
+    clk_ref_locked_o      : out std_logic;
+    clk_62m5_dmtd_o       : out std_logic;
+    pll_locked_o          : out std_logic;
+    clk_10m_ext_o         : out std_logic;
+    -- PHY
+    phy8_o                : out t_phy_8bits_to_wrc;
+    phy8_i                : in  t_phy_8bits_from_wrc  := c_dummy_phy8_from_wrc;
+    phy16_o               : out t_phy_16bits_to_wrc;
+    phy16_i               : in  t_phy_16bits_from_wrc := c_dummy_phy16_from_wrc;
+    -- External reference
+    ext_ref_mul_o         : out std_logic;
+    ext_ref_mul_locked_o  : out std_logic;
+    ext_ref_mul_stopped_o : out std_logic;
+    ext_ref_rst_i         : in  std_logic             := '0'
+    );
+
+end entity xwrc_platform_xilinx;
+
+architecture rtl of xwrc_platform_xilinx is
+
+  -----------------------------------------------------------------------------
+  -- Signals declaration
+  -----------------------------------------------------------------------------
+
+  signal pll_arst            : std_logic := '0';
+  signal clk_125m_pllref_buf : std_logic;
+
+begin  -- architecture rtl
+
+  -----------------------------------------------------------------------------
+  -- Check for unsupported features and/or misconfiguration
+  -----------------------------------------------------------------------------
+  gen_unknown_fpga : if (g_fpga_family /= "spartan6" and g_fpga_family /= "kintex7" and g_fpga_family /= "artix7") generate
+    assert FALSE
+      report "Xilinx FPGA family [" & g_fpga_family & "] is not supported"
+      severity ERROR;
+  end generate gen_unknown_fpga;
+
+  gen_single_gtp_channel : if (g_gtp_enable_ch0 /= 0 and g_gtp_enable_ch1 /= 0)
+  generate
+    assert FALSE
+      report "Cannot enable both GTP channels simultaneously"
+      severity ERROR;
+  end generate gen_single_gtp_channel;
+
+  -----------------------------------------------------------------------------
+  -- Clock PLLs
+  -----------------------------------------------------------------------------
+
+  -- active high async reset for PLLs
+  pll_arst <= not areset_n_i;
+
+  gen_default_plls : if (g_use_default_plls = TRUE) generate
+
+    -- Default PLL setup consists of two PLLs.
+    -- One takes a 125MHz clock signal as input and produces the
+    -- 62.5MHz WR PTP core main system clock.
+    -- The other PLL takes a 20MHz clock signal as input and produces the
+    -- 62.5MHz DMTD clock.
+    --
+    -- A third PLL is instantiated if also g_with_external_clock_input = TRUE.
+    -- In that case, a 10MHz external reference is multiplied to generate a
+    -- 125MHz reference clock
+    gen_spartan6_default_plls : if (g_fpga_family = "spartan6") generate
+
+      signal clk_sys          : std_logic;
+      signal clk_sys_out      : std_logic;
+      signal clk_sys_fb       : std_logic;
+      signal pll_sys_locked   : std_logic;
+      signal clk_dmtd         : std_logic;
+      signal clk_dmtd_fb      : std_logic;
+      signal pll_dmtd_locked  : std_logic;
+      signal clk_20m_vcxo_buf : std_logic;
+
+    begin  --gen_spartan6_default_plls
+
+      -- System PLL
+      cmp_sys_clk_pll : PLL_BASE
+        generic map (
+          BANDWIDTH          => "OPTIMIZED",
+          CLK_FEEDBACK       => "CLKFBOUT",
+          COMPENSATION       => "INTERNAL",
+          DIVCLK_DIVIDE      => 1,
+          CLKFBOUT_MULT      => 8,
+          CLKFBOUT_PHASE     => 0.000,
+          CLKOUT0_DIVIDE     => 16,
+          CLKOUT0_PHASE      => 0.000,
+          CLKOUT0_DUTY_CYCLE => 0.500,
+          CLKIN_PERIOD       => 8.0,
+          REF_JITTER         => 0.016)
+        port map (
+          CLKFBOUT => clk_sys_fb,
+          CLKOUT0  => clk_sys,
+          LOCKED   => pll_sys_locked,
+          RST      => pll_arst,
+          CLKFBIN  => clk_sys_fb,
+          CLKIN    => clk_125m_pllref_buf);
+
+      -- System PLL input clock buffer
+      cmp_clk_sys_buf_i : BUFG
+        port map (
+          O => clk_125m_pllref_buf,
+          I => clk_125m_pllref_i);
+
+      -- System PLL output clock buffer
+      cmp_clk_sys_buf_o : BUFG
+        port map (
+          O => clk_sys_out,
+          I => clk_sys);
+
+      clk_62m5_sys_o <= clk_sys_out;
+      clk_125m_ref_o <= clk_125m_pllref_buf;
+      pll_locked_o   <= pll_sys_locked and pll_dmtd_locked;
+      clk_ref_locked_o <= '1';
+
+      -- DMTD PLL
+      cmp_dmtd_clk_pll : PLL_BASE
+        generic map (
+          BANDWIDTH          => "OPTIMIZED",
+          CLK_FEEDBACK       => "CLKFBOUT",
+          COMPENSATION       => "INTERNAL",
+          DIVCLK_DIVIDE      => 1,
+          CLKFBOUT_MULT      => 50,
+          CLKFBOUT_PHASE     => 0.000,
+          CLKOUT0_DIVIDE     => 16,
+          CLKOUT0_PHASE      => 0.000,
+          CLKOUT0_DUTY_CYCLE => 0.500,
+          CLKIN_PERIOD       => 50.0,
+          REF_JITTER         => 0.016)
+        port map (
+          CLKFBOUT => clk_dmtd_fb,
+          CLKOUT0  => clk_dmtd,
+          LOCKED   => pll_dmtd_locked,
+          RST      => pll_arst,
+          CLKFBIN  => clk_dmtd_fb,
+          CLKIN    => clk_20m_vcxo_buf);
+
+      -- DMTD PLL input clock buffer
+      cmp_clk_dmtd_buf_i : BUFG
+        port map (
+          O => clk_20m_vcxo_buf,
+          I => clk_20m_vcxo_i);
+
+      -- DMTD PLL output clock buffer
+      cmp_clk_dmtd_buf_o : BUFG
+        port map (
+          O => clk_62m5_dmtd_o,
+          I => clk_dmtd);
+
+
+      gen_spartan6_ext_ref_pll : if (g_with_external_clock_input = TRUE) generate
+
+        signal clk_ext_fbi  : std_logic;
+        signal clk_ext_fbo  : std_logic;
+        signal clk_ext_buf  : std_logic;
+        signal clk_ext      : std_logic;
+        signal clk_ext_stat : std_logic_vector(7 downto 0);
+        signal pll_ext_rst  : std_logic;
+
+      begin  --gen_spartan6_ext_ref_pll
+
+        -- External reference DCM
+        cmp_ext_ref_pll : DCM_SP
+          generic map
+          (CLKDV_DIVIDE       => 2.000,
+           CLKFX_DIVIDE       => 2,
+           CLKFX_MULTIPLY     => 25,
+           CLKIN_DIVIDE_BY_2  => FALSE,
+           CLKIN_PERIOD       => 100.0,
+           CLKOUT_PHASE_SHIFT => "NONE",
+           CLK_FEEDBACK       => "1X",
+           DESKEW_ADJUST      => "SYSTEM_SYNCHRONOUS",
+           PHASE_SHIFT        => 0,
+           STARTUP_WAIT       => FALSE)
+          port map
+          -- Input clock
+          (CLKIN    => clk_ext_buf,
+           CLKFB    => clk_ext_fbi,
+           -- Output clocks
+           CLK0     => clk_ext_fbo,
+           CLKFX    => clk_ext,
+           -- Ports for dynamic phase shift
+           PSCLK    => '0',
+           PSEN     => '0',
+           PSINCDEC => '0',
+           PSDONE   => open,
+           -- Other control and status signals
+           LOCKED   => ext_ref_mul_locked_o,
+           STATUS   => clk_ext_stat,
+           RST      => pll_ext_rst,
+           -- Unused pin, tie low
+           DSSEN    => '0');
+
+        ext_ref_mul_stopped_o <= clk_ext_stat(1);
+
+        -- External reference input buffer
+        cmp_clk_ext_buf_i : BUFG
+          port map
+          (O => clk_ext_buf,
+           I => clk_10m_ext_i);
+
+        clk_10m_ext_o <= clk_ext_buf;
+
+        -- External reference feedback buffer
+        cmp_clk_ext_buf_fb : BUFG
+          port map
+          (O => clk_ext_fbi,
+           I => clk_ext_fbo);
+
+        -- External reference output buffer
+        cmp_clk_ext_buf_o : BUFG
+          port map
+          (O => ext_ref_mul_o,
+           I => clk_ext);
+
+        cmp_extend_ext_reset : gc_extend_pulse
+          generic map (
+            g_width => 1000)
+          port map (
+            clk_i      => clk_sys_out,
+            rst_n_i    => pll_sys_locked,
+            pulse_i    => ext_ref_rst_i,
+            extended_o => pll_ext_rst);
+
+      end generate gen_spartan6_ext_ref_pll;
+
+    end generate gen_spartan6_default_plls;
+
+    ---------------------------------------------------------------------------
+    --   Kintex7 PLLs
+    ---------------------------------------------------------------------------
+    gen_kintex7_default_plls : if (g_fpga_family = "kintex7") generate
+
+      signal clk_sys          : std_logic;
+      signal clk_sys_out      : std_logic;
+      signal clk_sys_fb       : std_logic;
+      signal pll_sys_locked   : std_logic;
+      signal clk_dmtd         : std_logic;
+      signal clk_dmtd_fb      : std_logic;
+      signal pll_dmtd_locked  : std_logic;
+      signal clk_20m_vcxo_buf : std_logic;
+
+    begin
+      -- System PLL (125 MHz -> 62.5 MHz)
+      cmp_sys_clk_pll : MMCME2_ADV
+        generic map (
+          BANDWIDTH            => "OPTIMIZED",
+          CLKOUT4_CASCADE      => false,
+          COMPENSATION         => "ZHOLD",
+          STARTUP_WAIT         => false,
+          DIVCLK_DIVIDE        => 1,
+          CLKFBOUT_MULT_F      => 8.000,     -- 125 MHz x 8.
+          CLKFBOUT_PHASE       => 0.000,
+          CLKFBOUT_USE_FINE_PS => false,
+
+          CLKOUT0_DIVIDE_F    => 16.000,     -- 62.5 MHz sys clock
+          CLKOUT0_PHASE       => 0.000,
+          CLKOUT0_DUTY_CYCLE  => 0.500,
+          CLKOUT0_USE_FINE_PS => false,
+
+          CLKIN1_PERIOD => 8.000,            -- 8 ns means 125 MHz
+          REF_JITTER1   => 0.010)
+        port map (
+          -- Output clocks
+          CLKFBOUT     => clk_sys_fb,
+          CLKOUT0      => clk_sys,
+          -- Input clock control
+          CLKFBIN      => clk_sys_fb,
+          CLKIN1       => clk_125m_pllref_buf,
+          CLKIN2       => '0',
+          -- Tied to always select the primary input clock
+          CLKINSEL     => '1',
+          -- Ports for dynamic reconfiguration
+          DADDR        => (others => '0'),
+          DCLK         => '0',
+          DEN          => '0',
+          DI           => (others => '0'),
+          DO           => open,
+          DRDY         => open,
+          DWE          => '0',
+          -- Ports for dynamic phase shift
+          PSCLK        => '0',
+          PSEN         => '0',
+          PSINCDEC     => '0',
+          PSDONE       => open,
+          -- Other control and status signals
+          LOCKED       => pll_sys_locked,
+          CLKINSTOPPED => open,
+          CLKFBSTOPPED => open,
+          PWRDWN       => '0',
+          RST          => pll_arst);
+
+      -- System PLL output clock buffer
+      cmp_clk_sys_buf_o : BUFG
+      port map (
+        I => clk_sys,
+        O => clk_sys_out);
+
+      clk_62m5_sys_o <= clk_sys_out;
+      pll_locked_o   <= pll_dmtd_locked and pll_sys_locked;
+
+      -- DMTD PLL (20 MHz -> ~62,5 MHz)
+      cmp_dmtd_clk_pll : MMCME2_ADV
+        generic map (
+          BANDWIDTH            => "OPTIMIZED",
+          CLKOUT4_CASCADE      => false,
+          COMPENSATION         => "ZHOLD",
+          STARTUP_WAIT         => false,
+          DIVCLK_DIVIDE        => 1,
+          CLKFBOUT_MULT_F      => 50.000,    -- 20 MHz -> 1 GHz
+          CLKFBOUT_PHASE       => 0.000,
+          CLKFBOUT_USE_FINE_PS => false,
+          CLKOUT0_DIVIDE_F     => 16.000,    -- 1GHz/16 -> 62.5 MHz
+          CLKOUT0_PHASE        => 0.000,
+          CLKOUT0_DUTY_CYCLE   => 0.500,
+          CLKOUT0_USE_FINE_PS  => false,
+          CLKOUT1_DIVIDE       => 16,        -- 1GHz/16 -> 62.5 MHz
+          CLKOUT1_PHASE        => 0.000,
+          CLKOUT1_DUTY_CYCLE   => 0.500,
+          CLKOUT1_USE_FINE_PS  => false,
+          CLKIN1_PERIOD        => 50.000,    -- 50ns for 20 MHz
+          REF_JITTER1          => 0.010)
+        port map (
+          -- Output clocks
+          CLKFBOUT     => clk_dmtd_fb,
+          CLKOUT0      => clk_dmtd,
+          -- Input clock control
+          CLKFBIN      => clk_dmtd_fb,
+          CLKIN1       => clk_20m_vcxo_buf,
+          CLKIN2       => '0',
+          -- Tied to always select the primary input clock
+          CLKINSEL     => '1',
+          -- Ports for dynamic reconfiguration
+          DADDR        => (others => '0'),
+          DCLK         => '0',
+          DEN          => '0',
+          DI           => (others => '0'),
+          DO           => open,
+          DRDY         => open,
+          DWE          => '0',
+          -- Ports for dynamic phase shift
+          PSCLK        => '0',
+          PSEN         => '0',
+          PSINCDEC     => '0',
+          PSDONE       => open,
+          -- Other control and status signals
+          LOCKED       => pll_dmtd_locked,
+          CLKINSTOPPED => open,
+          CLKFBSTOPPED => open,
+          PWRDWN       => '0',
+          RST          => pll_arst);
+
+      -- DMTD PLL input clock buffer
+      cmp_clk_dmtd_buf_i : BUFG
+        port map (
+          O => clk_20m_vcxo_buf,
+          I => clk_20m_vcxo_i);
+
+      -- DMTD PLL output clock buffer
+      cmp_clk_dmtd_buf_o : BUFG
+        port map (
+          O => clk_62m5_dmtd_o,
+          I => clk_dmtd);
+
+      -- External 10MHz reference PLL for Kintex7
+      gen_kintex7_ext_ref_pll : if (g_with_external_clock_input = TRUE) generate
+        
+        signal clk_ext_fbi : std_logic;
+        signal clk_ext_fbo : std_logic;
+        signal clk_ext_buf : std_logic;
+        signal clk_ext_mul : std_logic;
+        signal pll_ext_rst : std_logic;
+
+      begin
+        mmcm_adv_inst : MMCME2_ADV
+          generic map (
+            BANDWIDTH            => "OPTIMIZED",
+            CLKOUT4_CASCADE      => FALSE,
+            COMPENSATION         => "ZHOLD",
+            STARTUP_WAIT         => FALSE,
+            DIVCLK_DIVIDE        => 1,
+            CLKFBOUT_MULT_F      => 62.500,
+            CLKFBOUT_PHASE       => 0.000,
+            CLKFBOUT_USE_FINE_PS => FALSE,
+            CLKOUT0_DIVIDE_F     => 10.000,
+            CLKOUT0_PHASE        => 0.000,
+            CLKOUT0_DUTY_CYCLE   => 0.500,
+            CLKOUT0_USE_FINE_PS  => FALSE,
+            CLKIN1_PERIOD        => 100.000,
+            REF_JITTER1          => 0.005)
+          port map (
+            -- Output clocks
+            CLKFBOUT  => clk_ext_fbo,
+            CLKOUT0   => clk_ext_mul,
+            -- Input clock control
+            CLKFBIN   => clk_ext_fbi,
+            CLKIN1    => clk_ext_buf,
+            CLKIN2    => '0',
+            -- Tied to always select the primary input clock
+            CLKINSEL  => '1',
+            -- Ports for dynamic reconfiguration
+            DADDR     => (others => '0'),
+            DCLK      => '0',
+            DEN       => '0',
+            DI        => (others => '0'),
+            DO        => open,
+            DRDY      => open,
+            DWE       => '0',
+            -- Ports for dynamic phase shift
+            PSCLK     => '0',
+            PSEN      => '0',
+            PSINCDEC  => '0',
+            PSDONE    => open, -- Other control and status signals
+            LOCKED    => ext_ref_mul_locked_o,
+            CLKINSTOPPED => ext_ref_mul_stopped_o,
+            CLKFBSTOPPED => open,
+            PWRDWN   => '0',
+            RST      => pll_ext_rst);
+
+        -- External reference input buffer
+        cmp_clk_ext_buf_i : BUFG
+          port map (
+            O => clk_ext_buf,
+            I => clk_10m_ext_i);
+
+        clk_10m_ext_o <= clk_ext_buf;
+
+        -- External reference feedback buffer
+        cmp_clk_ext_buf_fb : BUFG
+          port map (
+            O => clk_ext_fbi,
+            I => clk_ext_fbo);
+
+        -- External reference output buffer
+        cmp_clk_ext_buf_o : BUFG
+          port map (
+            O => ext_ref_mul_o,
+            I => clk_ext_mul);
+
+        cmp_extend_ext_reset : gc_extend_pulse
+          generic map (
+            g_width => 1000)
+          port map (
+            clk_i      => clk_sys_out,
+            rst_n_i    => pll_sys_locked,
+            pulse_i    => ext_ref_rst_i,
+            extended_o => pll_ext_rst);
+
+      end generate gen_kintex7_ext_ref_pll;
+
+    end generate gen_kintex7_default_plls;
+
+    ---------------------------------------------------------------------------
+    --   Artix7 PLLs
+    ---------------------------------------------------------------------------
+    gen_artix7_default_plls : if (g_fpga_family = "artix7") generate
+
+      signal clk_sys          : std_logic;
+      signal clk_sys_out      : std_logic;
+      signal clk_sys_fb       : std_logic;
+      signal pll_sys_locked   : std_logic;
+      signal clk_dmtd         : std_logic := '0'; -- initialize for simulation
+--      signal clk_dmtd_fb      : std_logic;
+--      signal pll_dmtd_locked  : std_logic;
+--      signal clk_20m_vcxo_buf : std_logic;
+
+    begin
+      -- System PLL (125 MHz -> 62.5 MHz)
+      cmp_sys_clk_pll : MMCME2_ADV
+        generic map (
+          BANDWIDTH            => "OPTIMIZED",
+          CLKOUT4_CASCADE      => false,
+          COMPENSATION         => "ZHOLD",
+          STARTUP_WAIT         => false,
+          DIVCLK_DIVIDE        => 1,
+          CLKFBOUT_MULT_F      => 8.000,     -- 125 MHz x 8.
+          CLKFBOUT_PHASE       => 0.000,
+          CLKFBOUT_USE_FINE_PS => false,
+
+          CLKOUT0_DIVIDE_F    => 16.000,     -- 62.5 MHz sys clock
+          CLKOUT0_PHASE       => 0.000,
+          CLKOUT0_DUTY_CYCLE  => 0.500,
+          CLKOUT0_USE_FINE_PS => false,
+
+          CLKIN1_PERIOD => 8.000,            -- 8 ns means 125 MHz
+          REF_JITTER1   => 0.010)
+        port map (
+          -- Output clocks
+          CLKFBOUT     => clk_sys_fb,
+          CLKOUT0      => clk_sys,
+          -- Input clock control
+          CLKFBIN      => clk_sys_fb,
+          CLKIN1       => clk_125m_pllref_buf,
+          CLKIN2       => '0',
+          -- Tied to always select the primary input clock
+          CLKINSEL     => '1',
+          -- Ports for dynamic reconfiguration
+          DADDR        => (others => '0'),
+          DCLK         => '0',
+          DEN          => '0',
+          DI           => (others => '0'),
+          DO           => open,
+          DRDY         => open,
+          DWE          => '0',
+          -- Ports for dynamic phase shift
+          PSCLK        => '0',
+          PSEN         => '0',
+          PSINCDEC     => '0',
+          PSDONE       => open,
+          -- Other control and status signals
+          LOCKED       => pll_sys_locked,
+          CLKINSTOPPED => open,
+          CLKFBSTOPPED => open,
+          PWRDWN       => '0',
+          RST          => pll_arst);
+
+      -- System PLL output clock buffer
+      cmp_clk_sys_buf_o : BUFG
+      port map (
+        I => clk_sys,
+        O => clk_sys_out);
+
+      clk_62m5_sys_o <= clk_sys_out;
+--      pll_locked_o   <= pll_dmtd_locked and pll_sys_locked;
+      pll_locked_o   <= pll_sys_locked;
+
+--      -- DMTD PLL (20 MHz -> ~62,5 MHz)
+--      cmp_dmtd_clk_pll : MMCME2_ADV
+--        generic map (
+--          BANDWIDTH            => "OPTIMIZED",
+--          CLKOUT4_CASCADE      => false,
+--          COMPENSATION         => "ZHOLD",
+--          STARTUP_WAIT         => false,
+--          DIVCLK_DIVIDE        => 1,
+--          CLKFBOUT_MULT_F      => 50.000,    -- 20 MHz -> 1 GHz
+--          CLKFBOUT_PHASE       => 0.000,
+--          CLKFBOUT_USE_FINE_PS => false,
+--          CLKOUT0_DIVIDE_F     => 16.000,    -- 1GHz/16 -> 62.5 MHz
+--          CLKOUT0_PHASE        => 0.000,
+--          CLKOUT0_DUTY_CYCLE   => 0.500,
+--          CLKOUT0_USE_FINE_PS  => false,
+--          CLKOUT1_DIVIDE       => 16,        -- 1GHz/16 -> 62.5 MHz
+--          CLKOUT1_PHASE        => 0.000,
+--          CLKOUT1_DUTY_CYCLE   => 0.500,
+--          CLKOUT1_USE_FINE_PS  => false,
+--          CLKIN1_PERIOD        => 50.000,    -- 50ns for 20 MHz
+--          REF_JITTER1          => 0.010)
+--        port map (
+--          -- Output clocks
+--          CLKFBOUT     => clk_dmtd_fb,
+--          CLKOUT0      => clk_dmtd,
+--          -- Input clock control
+--          CLKFBIN      => clk_dmtd_fb,
+--          CLKIN1       => clk_20m_vcxo_buf,
+--          CLKIN2       => '0',
+--          -- Tied to always select the primary input clock
+--          CLKINSEL     => '1',
+--          -- Ports for dynamic reconfiguration
+--          DADDR        => (others => '0'),
+--          DCLK         => '0',
+--          DEN          => '0',
+--          DI           => (others => '0'),
+--          DO           => open,
+--          DRDY         => open,
+--          DWE          => '0',
+--          -- Ports for dynamic phase shift
+--          PSCLK        => '0',
+--          PSEN         => '0',
+--          PSINCDEC     => '0',
+--          PSDONE       => open,
+--          -- Other control and status signals
+--          LOCKED       => pll_dmtd_locked,
+--          CLKINSTOPPED => open,
+--          CLKFBSTOPPED => open,
+--          PWRDWN       => '0',
+--          RST          => pll_arst);
+--
+--      -- DMTD PLL input clock buffer
+--      cmp_clk_dmtd_buf_i : BUFG
+--        port map (
+--          O => clk_20m_vcxo_buf,
+--          I => clk_20m_vcxo_i);
+--
+
+      -- DMTD Div2 (124.9920 MHz -> 62,496 MHz)
+      process(clk_125m_dmtd_i)
+      begin
+        if rising_edge(clk_125m_dmtd_i) then
+          clk_dmtd <= not clk_dmtd;
+        end if;
+      end process;
+
+      -- DMTD PLL output clock buffer
+      cmp_clk_dmtd_buf_o : BUFG
+        port map (
+          O => clk_62m5_dmtd_o,
+          I => clk_dmtd);
+
+      -- External 10MHz reference PLL for Artix7
+      gen_artix7_ext_ref_pll : if (g_with_external_clock_input = TRUE) generate
+        
+        signal clk_ext_fbi : std_logic;
+        signal clk_ext_fbo : std_logic;
+        signal clk_ext_buf : std_logic;
+        signal clk_ext_mul : std_logic;
+        signal pll_ext_rst : std_logic;
+
+      begin
+        mmcm_adv_inst : MMCME2_ADV
+          generic map (
+            BANDWIDTH            => "OPTIMIZED",
+            CLKOUT4_CASCADE      => FALSE,
+            COMPENSATION         => "ZHOLD",
+            STARTUP_WAIT         => FALSE,
+            DIVCLK_DIVIDE        => 1,
+            CLKFBOUT_MULT_F      => 62.500,
+            CLKFBOUT_PHASE       => 0.000,
+            CLKFBOUT_USE_FINE_PS => FALSE,
+            CLKOUT0_DIVIDE_F     => 10.000,
+            CLKOUT0_PHASE        => 0.000,
+            CLKOUT0_DUTY_CYCLE   => 0.500,
+            CLKOUT0_USE_FINE_PS  => FALSE,
+            CLKIN1_PERIOD        => 100.000,
+            REF_JITTER1          => 0.005)
+          port map (
+            -- Output clocks
+            CLKFBOUT  => clk_ext_fbo,
+            CLKOUT0   => clk_ext_mul,
+            -- Input clock control
+            CLKFBIN   => clk_ext_fbi,
+            CLKIN1    => clk_ext_buf,
+            CLKIN2    => '0',
+            -- Tied to always select the primary input clock
+            CLKINSEL  => '1',
+            -- Ports for dynamic reconfiguration
+            DADDR     => (others => '0'),
+            DCLK      => '0',
+            DEN       => '0',
+            DI        => (others => '0'),
+            DO        => open,
+            DRDY      => open,
+            DWE       => '0',
+            -- Ports for dynamic phase shift
+            PSCLK     => '0',
+            PSEN      => '0',
+            PSINCDEC  => '0',
+            PSDONE    => open, -- Other control and status signals
+            LOCKED    => ext_ref_mul_locked_o,
+            CLKINSTOPPED => ext_ref_mul_stopped_o,
+            CLKFBSTOPPED => open,
+            PWRDWN   => '0',
+            RST      => pll_ext_rst);
+
+        -- External reference input buffer
+        cmp_clk_ext_buf_i : BUFG
+          port map (
+            O => clk_ext_buf,
+            I => clk_10m_ext_i);
+
+        clk_10m_ext_o <= clk_ext_buf;
+
+        -- External reference feedback buffer
+        cmp_clk_ext_buf_fb : BUFG
+          port map (
+            O => clk_ext_fbi,
+            I => clk_ext_fbo);
+
+        -- External reference output buffer
+        cmp_clk_ext_buf_o : BUFG
+          port map (
+            O => ext_ref_mul_o,
+            I => clk_ext_mul);
+
+        cmp_extend_ext_reset : gc_extend_pulse
+          generic map (
+            g_width => 1000)
+          port map (
+            clk_i      => clk_sys_out,
+            rst_n_i    => pll_sys_locked,
+            pulse_i    => ext_ref_rst_i,
+            extended_o => pll_ext_rst);
+
+      end generate gen_artix7_ext_ref_pll;
+
+    end generate gen_artix7_default_plls;
+    ---------------------------------------------------------------------------
+    
+    gen_no_ext_ref_pll : if (g_with_external_clock_input = FALSE) generate
+      clk_10m_ext_o         <= '0';
+      ext_ref_mul_o         <= '0';
+      ext_ref_mul_locked_o  <= '1';
+      ext_ref_mul_stopped_o <= '1';
+    end generate gen_no_ext_ref_pll;
+
+  end generate gen_default_plls;
+
+  -- If external PLLs are used, just copy clock inputs to outputs
+  gen_custom_plls : if (g_use_default_plls = FALSE) generate
+
+    clk_62m5_sys_o  <= clk_62m5_sys_i;
+    clk_62m5_dmtd_o <= clk_62m5_dmtd_i;
+    clk_125m_ref_o  <= clk_125m_ref_i;
+
+    pll_locked_o     <= clk_sys_locked_i and clk_dmtd_locked_i;
+    clk_ref_locked_o <= clk_ref_locked_i;
+
+    ext_ref_mul_o         <= clk_125m_ext_i;
+    ext_ref_mul_locked_o  <= clk_ext_locked_i;
+    ext_ref_mul_stopped_o <= clk_ext_stopped_i;
+
+  end generate gen_custom_plls;
+
+  -- always pass ext reference reset input to output, even when not used
+  clk_ext_rst_o <= ext_ref_rst_i;
+
+  -----------------------------------------------------------------------------
+  -- Transceiver PHY
+  -----------------------------------------------------------------------------
+
+  gen_phy_spartan6 : if(g_fpga_family = "spartan6") generate
+
+    signal clk_125m_gtp_buf : std_logic;
+
+    signal ch0_phy8_out, ch1_phy8_out : t_phy_8bits_to_wrc;
+
+    signal ch0_sfp_txn, ch0_sfp_txp : std_logic;
+    signal ch1_sfp_txn, ch1_sfp_txp : std_logic;
+    signal ch0_sfp_rxn, ch0_sfp_rxp : std_logic;
+    signal ch1_sfp_rxn, ch1_sfp_rxp : std_logic;
+
+  begin
+
+    cmp_ibufgds_gtp : IBUFGDS
+      generic map (
+        DIFF_TERM    => TRUE,
+        IBUF_LOW_PWR => TRUE,
+        IOSTANDARD   => "DEFAULT")
+      port map (
+        O  => clk_125m_gtp_buf,
+        I  => clk_125m_gtp_p_i,
+        IB => clk_125m_gtp_n_i);
+
+
+    cmp_gtp : wr_gtp_phy_spartan6
+      generic map (
+        g_simulation => g_simulation,
+        g_enable_ch0 => g_gtp_enable_ch0,
+        g_enable_ch1 => g_gtp_enable_ch1)
+      port map (
+        gtp_clk_i          => clk_125m_gtp_buf,
+        ch0_ref_clk_i      => clk_125m_pllref_buf,
+        ch0_tx_data_i      => phy8_i.tx_data,
+        ch0_tx_k_i         => phy8_i.tx_k(0),
+        ch0_tx_disparity_o => ch0_phy8_out.tx_disparity,
+        ch0_tx_enc_err_o   => ch0_phy8_out.tx_enc_err,
+        ch0_rx_data_o      => ch0_phy8_out.rx_data,
+        ch0_rx_rbclk_o     => ch0_phy8_out.rx_clk,
+        ch0_rx_k_o         => ch0_phy8_out.rx_k(0),
+        ch0_rx_enc_err_o   => ch0_phy8_out.rx_enc_err,
+        ch0_rx_bitslide_o  => ch0_phy8_out.rx_bitslide,
+        ch0_rst_i          => phy8_i.rst,
+        ch0_loopen_i       => phy8_i.loopen,
+        ch0_loopen_vec_i   => phy8_i.loopen_vec,
+        ch0_tx_prbs_sel_i  => phy8_i.tx_prbs_sel,
+        ch0_rdy_o          => ch0_phy8_out.rdy,
+        ch1_ref_clk_i      => clk_125m_pllref_buf,
+        ch1_tx_data_i      => phy8_i.tx_data,
+        ch1_tx_k_i         => phy8_i.tx_k(0),
+        ch1_tx_disparity_o => ch1_phy8_out.tx_disparity,
+        ch1_tx_enc_err_o   => ch1_phy8_out.tx_enc_err,
+        ch1_rx_data_o      => ch1_phy8_out.rx_data,
+        ch1_rx_rbclk_o     => ch1_phy8_out.rx_clk,
+        ch1_rx_k_o         => ch1_phy8_out.rx_k(0),
+        ch1_rx_enc_err_o   => ch1_phy8_out.rx_enc_err,
+        ch1_rx_bitslide_o  => ch1_phy8_out.rx_bitslide,
+        ch1_rst_i          => phy8_i.rst,
+        ch1_loopen_i       => phy8_i.loopen,
+        ch1_loopen_vec_i   => phy8_i.loopen_vec,
+        ch1_tx_prbs_sel_i  => phy8_i.tx_prbs_sel,
+        ch1_rdy_o          => ch1_phy8_out.rdy,
+        pad_txn0_o         => ch0_sfp_txn,
+        pad_txp0_o         => ch0_sfp_txp,
+        pad_rxn0_i         => ch0_sfp_rxn,
+        pad_rxp0_i         => ch0_sfp_rxp,
+        pad_txn1_o         => ch1_sfp_txn,
+        pad_txp1_o         => ch1_sfp_txp,
+        pad_rxn1_i         => ch1_sfp_rxn,
+        pad_rxp1_i         => ch1_sfp_rxp
+        );
+
+    gen_gtp_ch0 : if (g_gtp_enable_ch0 = 1) generate
+      ch0_phy8_out.ref_clk      <= clk_125m_pllref_buf;
+      ch0_phy8_out.sfp_tx_fault <= sfp_tx_fault_i;
+      ch0_phy8_out.sfp_los      <= sfp_los_i;
+      phy8_o                    <= ch0_phy8_out;
+      sfp_txp_o                 <= ch0_sfp_txp;
+      sfp_txn_o                 <= ch0_sfp_txn;
+      ch0_sfp_rxp               <= sfp_rxp_i;
+      ch0_sfp_rxn               <= sfp_rxn_i;
+    end generate gen_gtp_ch0;
+
+    gen_gtp_ch1 : if (g_gtp_enable_ch1 = 1) generate
+      ch1_phy8_out.ref_clk      <= clk_125m_pllref_buf;
+      ch1_phy8_out.sfp_tx_fault <= sfp_tx_fault_i;
+      ch1_phy8_out.sfp_los      <= sfp_los_i;
+      phy8_o                    <= ch1_phy8_out;
+      sfp_txp_o                 <= ch1_sfp_txp;
+      sfp_txn_o                 <= ch1_sfp_txn;
+      ch1_sfp_rxp               <= sfp_rxp_i;
+      ch1_sfp_rxn               <= sfp_rxn_i;
+    end generate gen_gtp_ch1;
+
+    sfp_tx_disable_o <= phy8_i.sfp_tx_disable;
+
+    phy16_o <= c_dummy_phy16_to_wrc;
+
+  end generate gen_phy_spartan6;
+
+  ---------------------------------------------------------------------------
+  --   Kintex7 PHY
+  ---------------------------------------------------------------------------
+
+  gen_phy_kintex7 : if (g_fpga_family = "kintex7") generate
+
+    signal clk_ref          : std_logic;
+    signal clk_125m_gtx_buf : std_logic;
+    signal clk_ref_locked   : std_logic;
+
+  begin
+
+    gen_ibufgds: if (g_use_ibufgds=true) generate
+    begin
+      -- Dedicated GTX clock.
+      cmp_gtp_dedicated_clk : IBUFDS_GTE2
+        generic map(
+          CLKCM_CFG    => true,
+          CLKRCV_TRST  => true,
+          CLKSWING_CFG => "11")
+        port map (
+          O     => clk_125m_gtx_buf,
+          ODIV2 => open,
+          CEB   => '0',
+          I     => clk_125m_gtp_p_i,
+          IB    => clk_125m_gtp_n_i);
+    end generate gen_ibufgds;
+
+    gen_no_ibufgds: if (g_use_ibufgds=false) generate
+    begin
+      clk_125m_gtx_buf <= clk_125m_gtp_p_i;
+    end generate gen_no_ibufgds;
+
+
+    -- System PLL input clock buffer
+    cmp_clk_sys_buf_i : BUFG
+      port map (
+        I => clk_125m_gtx_buf,
+        O => clk_125m_pllref_buf);
+
+    cmp_gtx: wr_gtx_phy_family7
+      generic map(
+        g_simulation => g_simulation)
+      port map(
+        clk_gtx_i      => clk_125m_gtx_buf,
+        tx_out_clk_o   => clk_ref,
+        tx_data_i      => phy16_i.tx_data,
+        tx_k_i         => phy16_i.tx_k,
+        tx_disparity_o => phy16_o.tx_disparity,
+        tx_enc_err_o   => phy16_o.tx_enc_err,
+        rx_rbclk_o     => phy16_o.rx_clk,
+        rx_data_o      => phy16_o.rx_data,
+        rx_k_o         => phy16_o.rx_k,
+        rx_enc_err_o   => phy16_o.rx_enc_err,
+        rx_bitslide_o  => phy16_o.rx_bitslide,
+        rst_i          => phy16_i.rst,
+        loopen_i       => phy16_i.loopen_vec,
+        tx_prbs_sel_i  => phy16_i.tx_prbs_sel,
+        rdy_o          => phy16_o.rdy,
+
+        pad_txn_o => sfp_txn_o,
+        pad_txp_o => sfp_txp_o,
+        pad_rxn_i => sfp_rxn_i,
+        pad_rxp_i => sfp_rxp_i,
+
+        tx_locked_o   => clk_ref_locked);
+
+    clk_125m_ref_o       <= clk_ref;
+    clk_ref_locked_o     <= clk_ref_locked;
+    phy16_o.ref_clk      <= clk_ref;
+    phy16_o.sfp_tx_fault <= sfp_tx_fault_i;
+    phy16_o.sfp_los      <= sfp_los_i;
+    sfp_tx_disable_o     <= phy16_i.sfp_tx_disable;
+
+    phy8_o <= c_dummy_phy8_to_wrc;
+
+  end generate gen_phy_kintex7;
+
+  ---------------------------------------------------------------------------
+  --   Artix7 PHY
+  ---------------------------------------------------------------------------
+
+  gen_phy_artix7 : if (g_fpga_family = "artix7") generate
+
+    signal clk_ref          : std_logic;
+    signal clk_125m_gtp_buf : std_logic;
+    signal clk_ref_locked   : std_logic;
+
+  begin
+
+    -- Dedicated GTP clock.
+    cmp_gtp_dedicated_clk : IBUFDS_GTE2
+      generic map(
+        CLKCM_CFG    => true,
+        CLKRCV_TRST  => true,
+        CLKSWING_CFG => "11")
+      port map (
+        O     => clk_125m_gtp_buf,
+        ODIV2 => open,
+        CEB   => '0',
+        I     => clk_125m_gtp_p_i,
+        IB    => clk_125m_gtp_n_i);
+
+    -- System PLL input clock buffer
+    cmp_clk_sys_buf_i : BUFG
+      port map (
+        I => clk_125m_gtp_buf,
+        O => clk_125m_pllref_buf);
+
+    cmp_gtp: wr_gtp_phy_family7
+      generic map(
+        g_simulation => g_simulation)
+      port map(
+        clk_gtp_i      => clk_125m_gtp_buf,
+        tx_out_clk_o   => clk_ref,
+        tx_data_i      => phy16_i.tx_data,
+        tx_k_i         => phy16_i.tx_k,
+        tx_disparity_o => phy16_o.tx_disparity,
+        tx_enc_err_o   => phy16_o.tx_enc_err,
+        rx_rbclk_o     => phy16_o.rx_clk,
+        rx_data_o      => phy16_o.rx_data,
+        rx_k_o         => phy16_o.rx_k,
+        rx_enc_err_o   => phy16_o.rx_enc_err,
+        rx_bitslide_o  => phy16_o.rx_bitslide,
+        rst_i          => phy16_i.rst,
+        loopen_i       => phy16_i.loopen_vec,
+        tx_prbs_sel_i  => phy16_i.tx_prbs_sel,
+        rdy_o          => phy16_o.rdy,
+
+        pad_txn_o => sfp_txn_o,
+        pad_txp_o => sfp_txp_o,
+        pad_rxn_i => sfp_rxn_i,
+        pad_rxp_i => sfp_rxp_i,
+
+        tx_locked_o   => clk_ref_locked);
+
+    clk_125m_ref_o       <= clk_ref;
+    clk_ref_locked_o     <= clk_ref_locked;
+    phy16_o.ref_clk      <= clk_ref;
+    phy16_o.sfp_tx_fault <= sfp_tx_fault_i;
+    phy16_o.sfp_los      <= sfp_los_i;
+    sfp_tx_disable_o     <= phy16_i.sfp_tx_disable;
+
+    phy8_o <= c_dummy_phy8_to_wrc;
+
+  end generate gen_phy_artix7;
+
+  ---------------------------------------------------------------------------
+
+end architecture rtl;
diff --git a/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/source.txt b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/source.txt
new file mode 100644
index 000000000..52c657abc
--- /dev/null
+++ b/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/source.txt
@@ -0,0 +1,2 @@
+This directory is a subset of the following tag:
+https://www.ohwr.org/projects/wr-cores/repository?utf8=%E2%9C%93&rev=wrpc-v4.2&branch=master&tag=wrpc-v4.2
-- 
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