From b63507efb3cf1a8fa20794c452d57028e18da182 Mon Sep 17 00:00:00 2001
From: Ben Hilburn <ben.hilburn@ettus.com>
Date: Tue, 22 Jul 2014 15:49:02 -0700
Subject: fpga: Updating FPGA code for UHD-3.7.2-rc1

---
 fpga/usrp3/lib/timing/Makefile.srcs | 1 +
 1 file changed, 1 insertion(+)

(limited to 'fpga/usrp3/lib/timing/Makefile.srcs')

diff --git a/fpga/usrp3/lib/timing/Makefile.srcs b/fpga/usrp3/lib/timing/Makefile.srcs
index ff4ca17d2..09f0596c5 100644
--- a/fpga/usrp3/lib/timing/Makefile.srcs
+++ b/fpga/usrp3/lib/timing/Makefile.srcs
@@ -8,4 +8,5 @@
 TIMING_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/timing/, \
 time_compare.v \
 timekeeper.v \
+pps.v\
 ))
-- 
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