From ff1546f8137f7f92bb250f685561b0c34cc0e053 Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Fri, 14 Feb 2014 12:05:07 -0800 Subject: Pushing the bulk of UHD-3.7.0 code. --- .../source_flow_control/test_window/default.wcfg | 114 +++++++++++++++++++++ .../sim/source_flow_control/test_window/run_isim | 16 +++ .../source_flow_control/test_window/run_iverilog | 16 +++ 3 files changed, 146 insertions(+) create mode 100644 fpga/usrp3/lib/sim/source_flow_control/test_window/default.wcfg create mode 100755 fpga/usrp3/lib/sim/source_flow_control/test_window/run_isim create mode 100755 fpga/usrp3/lib/sim/source_flow_control/test_window/run_iverilog (limited to 'fpga/usrp3/lib/sim/source_flow_control') diff --git a/fpga/usrp3/lib/sim/source_flow_control/test_window/default.wcfg b/fpga/usrp3/lib/sim/source_flow_control/test_window/default.wcfg new file mode 100644 index 000000000..921a89630 --- /dev/null +++ b/fpga/usrp3/lib/sim/source_flow_control/test_window/default.wcfg @@ -0,0 +1,114 @@ + + + + + + + + + + + + + + + clk + clk + + + reset + reset + + + set_stb + set_stb + + + set_addr[7:0] + set_addr[7:0] + HEXRADIX + + + set_data[31:0] + set_data[31:0] + HEXRADIX + + + in_tdata[63:0] + in_tdata[63:0] + HEXRADIX + + + in_tlast + in_tlast + + + in_tvalid + in_tvalid + + + in_tready + in_tready + + + out_tdata[63:0] + out_tdata[63:0] + HEXRADIX + + + out_tlast + out_tlast + + + out_tvalid + out_tvalid + + + out_tready + out_tready + + + fc_tdata[63:0] + fc_tdata[63:0] + HEXRADIX + + + fc_tvalid + fc_tvalid + + + fc_tready + fc_tready + + + fc_tlast + fc_tlast + + + go_until_seqnum[31:0] + go_until_seqnum[31:0] + HEXRADIX + + + current_seqnum[31:0] + current_seqnum[31:0] + HEXRADIX + + + go + go + + + window_size[31:0] + window_size[31:0] + HEXRADIX + + + window_reset + window_reset + + + always_go + always_go + + diff --git a/fpga/usrp3/lib/sim/source_flow_control/test_window/run_isim b/fpga/usrp3/lib/sim/source_flow_control/test_window/run_isim new file mode 100755 index 000000000..b71b938e6 --- /dev/null +++ b/fpga/usrp3/lib/sim/source_flow_control/test_window/run_isim @@ -0,0 +1,16 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../packet_proc/source_flow_control_tb.v +vlogcomp -work work ../../../packet_proc/source_flow_control.v +vlogcomp -work work ../../../control/setting_reg.v +vlogcomp -work work ../../../control/ram_2port.v +vlogcomp -work work ../../../fifo/axi_fifo.v +vlogcomp -work work ../../../fifo/axi_fifo_short.v + + + +fuse work.source_flow_control_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o source_flow_control_tb.exe + +# run the simulation scrip +./source_flow_control_tb.exe -gui #-tclbatch simcmds.tcl +#./source_flow_control_tb.exe + diff --git a/fpga/usrp3/lib/sim/source_flow_control/test_window/run_iverilog b/fpga/usrp3/lib/sim/source_flow_control/test_window/run_iverilog new file mode 100755 index 000000000..8ae57a610 --- /dev/null +++ b/fpga/usrp3/lib/sim/source_flow_control/test_window/run_iverilog @@ -0,0 +1,16 @@ +iverilog -y . \ +-D SIM_SCRIPT=true \ +../../../vita/new_tx_tb.v \ +-y ../../../vita/ \ +-y ../../../fifo/ \ +-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \ +-y ../../../control/ \ +-y ../../../timing/ \ +-y ../../../dsp/ \ +/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \ +-y ../../../../../usrp2/models/ \ +-Wall \ +-o new_tx_tb.exe + +./new_tx_tb.exe + -- cgit v1.2.3