From fd3e84941de463fa1a7ebab0a69515b4bf2614cd Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Tue, 7 Oct 2014 11:25:20 +0200 Subject: Removed copy of FPGA source files. --- fpga/usrp3/lib/sim/eth_dispatch/default.wcfg | 220 --------------------- fpga/usrp3/lib/sim/eth_dispatch/run_sim | 16 -- .../usrp3/lib/sim/eth_dispatch/simulation_script.v | 78 -------- 3 files changed, 314 deletions(-) delete mode 100644 fpga/usrp3/lib/sim/eth_dispatch/default.wcfg delete mode 100755 fpga/usrp3/lib/sim/eth_dispatch/run_sim delete mode 100644 fpga/usrp3/lib/sim/eth_dispatch/simulation_script.v (limited to 'fpga/usrp3/lib/sim/eth_dispatch') diff --git a/fpga/usrp3/lib/sim/eth_dispatch/default.wcfg b/fpga/usrp3/lib/sim/eth_dispatch/default.wcfg deleted file mode 100644 index f9178c2de..000000000 --- a/fpga/usrp3/lib/sim/eth_dispatch/default.wcfg +++ /dev/null @@ -1,220 +0,0 @@ - - - - - - - - - - - - - - - clk - clk - - - reset - reset - - - set_stb - set_stb - - - set_addr[15:0] - set_addr[15:0] - HEXRADIX - - - set_data[31:0] - set_data[31:0] - HEXRADIX - - - in_tdata[63:0] - in_tdata[63:0] - HEXRADIX - - - in_tuser[3:0] - in_tuser[3:0] - HEXRADIX - - - in_tvalid - in_tvalid - - - in_tready - in_tready - - - in_tlast - in_tlast - - - vita_tdata[63:0] - vita_tdata[63:0] - HEXRADIX - - - vita_tvalid - vita_tvalid - - - vita_tready - vita_tready - - - vita_tlast - vita_tlast - - - zpu_tdata[63:0] - zpu_tdata[63:0] - HEXRADIX - - - zpu_tuser[3:0] - zpu_tuser[3:0] - HEXRADIX - - - zpu_tvalid - zpu_tvalid - - - zpu_tready - zpu_tready - - - zpu_tlast - zpu_tlast - - - xo_tdata[63:0] - xo_tdata[63:0] - HEXRADIX - - - xo_tuser[3:0] - xo_tuser[3:0] - HEXRADIX - - - xo_tvalid - xo_tvalid - - - xo_tready - xo_tready - - - xo_tlast - xo_tlast - - - xo_pre_tdata[63:0] - xo_pre_tdata[63:0] - HEXRADIX - - - xo_pre_tuser[3:0] - xo_pre_tuser[3:0] - HEXRADIX - - - xo_pre_tlast - xo_pre_tlast - - - xo_pre_tvalid - xo_pre_tvalid - - - xo_pre_tready - xo_pre_tready - - - state[2:0] - state[2:0] - HEXRADIX - - - header_ram_addr[3:0] - header_ram_addr[3:0] - HEXRADIX - - - header_done - header_done - - - out_tlast - out_tlast - - - is_eth_dst_addr - is_eth_dst_addr - - - is_eth_broadcast - is_eth_broadcast - - - is_eth_type_ipv4 - is_eth_type_ipv4 - - - is_ipv4_dst_addr - is_ipv4_dst_addr - - - is_ipv4_proto_udp - is_ipv4_proto_udp - - - is_udp_dst_ports[1:0] - is_udp_dst_ports[1:0] - - - my_mac[47:0] - my_mac[47:0] - HEXRADIX - - - my_ip[31:0] - my_ip[31:0] - HEXRADIX - - - my_port0[15:0] - my_port0[15:0] - HEXRADIX - - - my_port1[15:0] - my_port1[15:0] - HEXRADIX - - - rd_addr[9:0] - rd_addr[9:0] - HEXRADIX - - - empty_reg - empty_reg - - - read - read - - - dob[68:0] - dob[68:0] - - diff --git a/fpga/usrp3/lib/sim/eth_dispatch/run_sim b/fpga/usrp3/lib/sim/eth_dispatch/run_sim deleted file mode 100755 index 3fda278f8..000000000 --- a/fpga/usrp3/lib/sim/eth_dispatch/run_sim +++ /dev/null @@ -1,16 +0,0 @@ -vlogcomp -work work ${XILINX}/verilog/src/glbl.v -vlogcomp -work work ../../packet_proc/eth_dispatch_tb.v -vlogcomp -work work ../../packet_proc/eth_dispatch.v -vlogcomp -work work ../../fifo/axi_fifo_short.v -vlogcomp -work work ../../fifo/axi_fifo.v -vlogcomp -work work ../../control/ram_2port.v -vlogcomp -work work ../../control/setting_reg.v -vlogcomp -work work ../../sim/axi_probe_tb.v - - - - -fuse work.eth_dispatch_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o eth_dispatch_tb.exe - -# run the simulation scrip -./eth_dispatch_tb.exe -gui #-tclbatch simcmds.tcl diff --git a/fpga/usrp3/lib/sim/eth_dispatch/simulation_script.v b/fpga/usrp3/lib/sim/eth_dispatch/simulation_script.v deleted file mode 100644 index 7e1df0fba..000000000 --- a/fpga/usrp3/lib/sim/eth_dispatch/simulation_script.v +++ /dev/null @@ -1,78 +0,0 @@ - - -initial $dumpfile("eth_dispatch_tb.vcd"); -initial $dumpvars(0,eth_dispatch_tb); - - reg [15:0] x; - - localparam MAC=48'h010203040506; - localparam IP=(192<<24)|(168<<16)|2; - localparam PORT0=60000; - localparam PORT1=60001; - - - initial - begin - @(posedge clk); - reset <= 1; - repeat (5) @(posedge clk); - @(posedge clk); - reset <= 0; - @(posedge clk); - // Set my MAC address - write_setting_bus(0,MAC&32'hFFFFFFFF); - write_setting_bus(1,MAC>>32); - // Set my IP Address - write_setting_bus(2,IP); - // Set UDP ports for ViTA traffic - write_setting_bus(3,PORT1<<16|PORT0); - @(posedge clk); - enqueue_vita_pkt(MAC,IP,PORT0,10,0,{16'h0,8'hf,8'h5}); - enqueue_vita_pkt(MAC,IP,16'h1234,10,0,{16'h0,8'h5,8'hc}); - enqueue_vita_pkt(48'h223344556677,32'h02030405,16'h1234,10,0,{16'h0,8'hd,8'h7}); - enqueue_arp_req(48'h112233445566,32'h09080706,MAC,IP); - -/* -----\/----- EXCLUDED -----\/----- - // 2x2 Switch so only mask one bit of SID for route dest. - // Each slave must have a unique address, logic doesn't check for this. - // - // Network Addr 0 & 1 go to Slave 0. - write_setting_bus(0,0); // 0.X goes to Port 0 - write_setting_bus(1,0); // 1.X goes to Port 0 - // Local Addr = 2 - write_setting_bus(512,2); - // Host Addr 0 & 2 go to Slave 0... - write_setting_bus(256,0); // 2.0 goes to Port 0 - write_setting_bus(258,0); // 2.2 goes to Port 0 - // ...Host Addr 1 & 3 go to Slave 1... - write_setting_bus(257,1); // 2.1 goes to Port 1 - write_setting_bus(259,1); // 2.3 goes to Port 1 - // - @(posedge clk); - fork - begin - // Master0, addr 0.0 to Slave0 - enqueue_vita_pkt(0,10,0,{16'h0,8'h0,8'h0}); - // Master0, addr 2.0 to Slave0 - enqueue_vita_pkt(0,11,'h12345678,{16'h0,8'h2,8'h0}); - // Master0, addr 2.3 to Slave1 - enqueue_vita_pkt(0,14,'h45678901,{16'h0,8'h2,8'h3}); - // Master0, addr 2.2 to Slave0 - enqueue_vita_pkt(0,11,'h67890123,{16'h0,8'h2,8'h2}); - end - begin - // Master1, addr 1.0 to Slave0 - enqueue_vita_pkt(1,12,'h23456789,{16'h0,8'h1,8'h0}); - // Master1, addr 2.1 to Slave1 - enqueue_vita_pkt(1,13,'h34567890,{16'h0,8'h2,8'h1}); - // Master1, addr 2.3 to Slave1 - enqueue_vita_pkt(1,14,'h56789012,{16'h0,8'h2,8'h3}); - end - join - -----/\----- EXCLUDED -----/\----- */ - - repeat (1000) @(posedge clk); - $finish; - - end // initial begin - -- cgit v1.2.3