From fd3e84941de463fa1a7ebab0a69515b4bf2614cd Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Tue, 7 Oct 2014 11:25:20 +0200 Subject: Removed copy of FPGA source files. --- fpga/usrp3/lib/sim/eth_dispatch/run_sim | 16 ---------------- 1 file changed, 16 deletions(-) delete mode 100755 fpga/usrp3/lib/sim/eth_dispatch/run_sim (limited to 'fpga/usrp3/lib/sim/eth_dispatch/run_sim') diff --git a/fpga/usrp3/lib/sim/eth_dispatch/run_sim b/fpga/usrp3/lib/sim/eth_dispatch/run_sim deleted file mode 100755 index 3fda278f8..000000000 --- a/fpga/usrp3/lib/sim/eth_dispatch/run_sim +++ /dev/null @@ -1,16 +0,0 @@ -vlogcomp -work work ${XILINX}/verilog/src/glbl.v -vlogcomp -work work ../../packet_proc/eth_dispatch_tb.v -vlogcomp -work work ../../packet_proc/eth_dispatch.v -vlogcomp -work work ../../fifo/axi_fifo_short.v -vlogcomp -work work ../../fifo/axi_fifo.v -vlogcomp -work work ../../control/ram_2port.v -vlogcomp -work work ../../control/setting_reg.v -vlogcomp -work work ../../sim/axi_probe_tb.v - - - - -fuse work.eth_dispatch_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o eth_dispatch_tb.exe - -# run the simulation scrip -./eth_dispatch_tb.exe -gui #-tclbatch simcmds.tcl -- cgit v1.2.3