From ff1546f8137f7f92bb250f685561b0c34cc0e053 Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Fri, 14 Feb 2014 12:05:07 -0800 Subject: Pushing the bulk of UHD-3.7.0 code. --- fpga/usrp3/lib/sim/axi_dram_fifo/default.wcfg | 412 ++++++++++++++++++++++++++ fpga/usrp3/lib/sim/axi_dram_fifo/run_isim | 16 + 2 files changed, 428 insertions(+) create mode 100644 fpga/usrp3/lib/sim/axi_dram_fifo/default.wcfg create mode 100755 fpga/usrp3/lib/sim/axi_dram_fifo/run_isim (limited to 'fpga/usrp3/lib/sim/axi_dram_fifo') diff --git a/fpga/usrp3/lib/sim/axi_dram_fifo/default.wcfg b/fpga/usrp3/lib/sim/axi_dram_fifo/default.wcfg new file mode 100644 index 000000000..796071597 --- /dev/null +++ b/fpga/usrp3/lib/sim/axi_dram_fifo/default.wcfg @@ -0,0 +1,412 @@ + + + + + + + + + + + + + + + clk + clk + + + reset + reset + + + clear + clear + + + count_rx[31:0] + count_rx[31:0] + HEXRADIX + + + count_tx[31:0] + count_tx[31:0] + HEXRADIX + + + i_tdata[63:0] + i_tdata[63:0] + HEXRADIX + + + i_tlast + i_tlast + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + input_state[2:0] + input_state[2:0] + HEXRADIX + + + write_ctrl_ready + write_ctrl_ready + + + write_ctrl_valid + write_ctrl_valid + + + occupied_input[5:0] + occupied_input[5:0] + HEXRADIX + + + INPUT TIMEOUT + label + + input_timeout_count[7:0] + input_timeout_count[7:0] + + + input_timeout_reset + input_timeout_reset + + + input_timeout_triggered + input_timeout_triggered + + + + AXI_WADDR + label + + write_addr_state[1:0] + write_addr_state[1:0] + HEXRADIX + true + #ffff00 + + + m_axi_awid[0:0] + m_axi_awid[0:0] + HEXRADIX + + + m_axi_awaddr[31:0] + m_axi_awaddr[31:0] + HEXRADIX + + + m_axi_awlen[7:0] + m_axi_awlen[7:0] + HEXRADIX + + + m_axi_awsize[2:0] + m_axi_awsize[2:0] + HEXRADIX + + + m_axi_awburst[1:0] + m_axi_awburst[1:0] + HEXRADIX + + + m_axi_awvalid + m_axi_awvalid + + + m_axi_awready + m_axi_awready + + + + write_data_count[3:0] + write_data_count[3:0] + HEXRADIX + + + AXI_WDATA + label + + m_axi_wdata[63:0] + m_axi_wdata[63:0] + HEXRADIX + + + m_axi_wstrb[7:0] + m_axi_wstrb[7:0] + HEXRADIX + + + m_axi_wlast + m_axi_wlast + + + m_axi_wvalid + m_axi_wvalid + + + m_axi_wready + m_axi_wready + + + + AXI_WRESP + label + + m_axi_bid[0:0] + m_axi_bid[0:0] + HEXRADIX + + + m_axi_bresp[1:0] + m_axi_bresp[1:0] + HEXRADIX + + + m_axi_bvalid + m_axi_bvalid + + + m_axi_bready + m_axi_bready + true + #00ff00 + /axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bready + + + + space[10:0] + space[10:0] + HEXRADIX + + + occupied[10:0] + occupied[10:0] + HEXRADIX + true + #00ffff + + + AXI_RADDR + label + + read_addr_state[1:0] + read_addr_state[1:0] + HEXRADIX + true + #ffff00 + + + m_axi_arid[0:0] + m_axi_arid[0:0] + HEXRADIX + + + m_axi_araddr[31:0] + m_axi_araddr[31:0] + HEXRADIX + + + m_axi_arlen[7:0] + m_axi_arlen[7:0] + HEXRADIX + + + m_axi_arsize[2:0] + m_axi_arsize[2:0] + HEXRADIX + + + m_axi_arburst[1:0] + m_axi_arburst[1:0] + HEXRADIX + + + m_axi_arvalid + m_axi_arvalid + + + m_axi_arready + m_axi_arready + + + + AXI_RDATA + label + + read_data_state[1:0] + read_data_state[1:0] + HEXRADIX + true + #ffff00 + + + m_axi_rid[0:0] + m_axi_rid[0:0] + HEXRADIX + + + m_axi_rdata[63:0] + m_axi_rdata[63:0] + HEXRADIX + + + m_axi_rresp[1:0] + m_axi_rresp[1:0] + HEXRADIX + + + m_axi_rlast + m_axi_rlast + + + m_axi_rvalid + m_axi_rvalid + + + m_axi_rready + m_axi_rready + + + + read_ctrl_valid + read_ctrl_valid + true + #ffff00 + + + read_ctrl_ready + read_ctrl_ready + + + read_data_count[3:0] + read_data_count[3:0] + HEXRADIX + + + output_state[2:0] + output_state[2:0] + HEXRADIX + + + space_output[5:0] + space_output[5:0] + HEXRADIX + + + DRAM FIFO OUT + label + + o_tdata_output[63:0] + o_tdata_output[63:0] + HEXRADIX + + + o_tvalid_output + o_tvalid_output + + + o_tready_output + o_tready_output + + + + update_write + update_write + true + #ff00ff + + + write_count[3:0] + write_count[3:0] + HEXRADIX + + + update_read + update_read + true + #ff00ff + + + read_count[3:0] + read_count[3:0] + HEXRADIX + + + Output TImeout + label + + output_timeout_count[7:0] + output_timeout_count[7:0] + + + output_timeout_reset + output_timeout_reset + + + output_timeout_triggered + output_timeout_triggered + + + + Extract TLAST + label + + o_tdata_i0[63:0] + o_tdata_i0[63:0] + HEXRADIX + + + o_tvalid_i0 + o_tvalid_i0 + + + o_tready_i0 + o_tready_i0 + + + o_tdata_i1[63:0] + o_tdata_i1[63:0] + HEXRADIX + + + o_tvalid_i1 + o_tvalid_i1 + + + o_tready_i1 + o_tready_i1 + + + o_tlast_i1 + o_tlast_i1 + + + + o_tdata[63:0] + o_tdata[63:0] + HEXRADIX + + + o_tlast + o_tlast + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + diff --git a/fpga/usrp3/lib/sim/axi_dram_fifo/run_isim b/fpga/usrp3/lib/sim/axi_dram_fifo/run_isim new file mode 100755 index 000000000..5d32efcdd --- /dev/null +++ b/fpga/usrp3/lib/sim/axi_dram_fifo/run_isim @@ -0,0 +1,16 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +#vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../packet_proc/source_flow_control_tb.v +vlogcomp -work work --sourcelibext .v \ + --sourcelibdir ../../axi \ + --sourcelibdir ../../fifo \ + --sourcelibdir ../../../top/b250/coregen \ + ../../axi/axi_dram_fifo_tb.v + + + +fuse work.axi_dram_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_dram_fifo_tb.exe + +# run the simulation scrip +./axi_dram_fifo_tb.exe -gui #-tclbatch simcmds.tcl +#./source_flow_control_tb.exe + -- cgit v1.2.3