From 6936a9ac664cbc312fd17a5ebab9b40069615f7a Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Mon, 7 Feb 2022 14:18:06 -0600 Subject: fpga: rfnoc: Change AWIDTH default for axi_ram_fifo Change AWIDTH to be the same as MEM_ADDR_W by default. Current USRPs assume the AXI address width is the same as MEM_ADDR_W. --- .../rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'fpga/usrp3/lib/rfnoc') diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo.v index 68dbbd4ec..2a169366d 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo.v +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo.v @@ -66,7 +66,7 @@ module rfnoc_block_axi_ram_fifo #( parameter MTU = 10, parameter MEM_DATA_W = CHDR_W, parameter MEM_ADDR_W = 32, - parameter AWIDTH = 32, + parameter AWIDTH = MEM_ADDR_W, parameter [NUM_PORTS*MEM_ADDR_W-1:0] FIFO_ADDR_BASE = {NUM_PORTS{ {MEM_ADDR_W{1'b0}} }}, parameter [NUM_PORTS*MEM_ADDR_W-1:0] FIFO_ADDR_MASK = {NUM_PORTS{ {(MEM_ADDR_W-$clog2(NUM_PORTS)){1'b1}} }}, parameter [ NUM_PORTS*32-1:0] BURST_TIMEOUT = {NUM_PORTS{ 32'd256 }}, -- cgit v1.2.3