From eed4988cc266a63370a4332351d02fadedde3a3b Mon Sep 17 00:00:00 2001 From: Andrew Moch Date: Thu, 25 Jun 2020 21:49:00 +0100 Subject: fpga: lib: Add width agnostic version of Ethernet Interface The rnfoc/xport section is refactored in System Verilog to allow the following improvements (1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run at a different clock rate than the main ethernet pipe (2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run at a different clock rate than the main ethernet pipe (3) ENET_W - Sets the size of the eth_tx and eth_rx pipes. eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously against the original xport_sv implementation, and against the new implementation with widths of 64/128/512. A chdr_management node info request queries the port info of the node0 in the eth_interface. eth_ifc_synth_test.sv can be compiled with the make xsim target to test out the size of various configurations. --- fpga/usrp3/lib/rfnoc/xport_sv/eth_regs.vh | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 fpga/usrp3/lib/rfnoc/xport_sv/eth_regs.vh (limited to 'fpga/usrp3/lib/rfnoc/xport_sv/eth_regs.vh') diff --git a/fpga/usrp3/lib/rfnoc/xport_sv/eth_regs.vh b/fpga/usrp3/lib/rfnoc/xport_sv/eth_regs.vh new file mode 100644 index 000000000..354a19414 --- /dev/null +++ b/fpga/usrp3/lib/rfnoc/xport_sv/eth_regs.vh @@ -0,0 +1,29 @@ +// +// Copyright 2020 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: eth_constants (Header File) +// +// Description: +// Holds register offsets for the Ethernet Interface +// NOTE: These depend on the following parameters +// Parameters: +// REG_AWIDTH - How wide the register window is in bits +// BASE - Base address added to the offsets here +// REGISTER OFFSETS +// Allocate one full page for MAC +localparam [REG_AWIDTH-1:0] REG_MAC_LSB = BASE + 'h0000; +localparam [REG_AWIDTH-1:0] REG_MAC_MSB = BASE + 'h0004; + +// Source IP address +localparam [REG_AWIDTH-1:0] REG_IP = BASE + 'h1000; +// Source UDP Port +localparam [REG_AWIDTH-1:0] REG_UDP = BASE + 'h1004; + +// Registers for Internal/Bridge Network Mode in CPU +localparam [REG_AWIDTH-1:0] REG_BRIDGE_MAC_LSB = BASE + 'h1010; +localparam [REG_AWIDTH-1:0] REG_BRIDGE_MAC_MSB = BASE + 'h1014; +localparam [REG_AWIDTH-1:0] REG_BRIDGE_IP = BASE + 'h1018; +localparam [REG_AWIDTH-1:0] REG_BRIDGE_UDP = BASE + 'h101c; +localparam [REG_AWIDTH-1:0] REG_BRIDGE_ENABLE = BASE + 'h1020; -- cgit v1.2.3