From bafa9d95453387814ef25e6b6256ba8db2df612f Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Thu, 23 Jan 2020 16:10:22 -0800 Subject: Merge FPGA repository back into UHD repository MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams Co-authored-by: Andrej Rode Co-authored-by: Ashish Chaudhari Co-authored-by: Ben Hilburn Co-authored-by: Ciro Nishiguchi Co-authored-by: Daniel Jepson Co-authored-by: Derek Kozel Co-authored-by: EJ Kreinar Co-authored-by: Humberto Jimenez Co-authored-by: Ian Buckley Co-authored-by: Jörg Hofrichter Co-authored-by: Jon Kiser Co-authored-by: Josh Blum Co-authored-by: Jonathon Pendlum Co-authored-by: Martin Braun Co-authored-by: Matt Ettus Co-authored-by: Michael West Co-authored-by: Moritz Fischer Co-authored-by: Nick Foster Co-authored-by: Nicolas Cuervo Co-authored-by: Paul Butler Co-authored-by: Paul David Co-authored-by: Ryan Marlow Co-authored-by: Sugandha Gupta Co-authored-by: Sylvain Munaut Co-authored-by: Trung Tran Co-authored-by: Vidush Vishwanath Co-authored-by: Wade Fife --- fpga/usrp3/lib/rfnoc/fosphor/axi_logpwr.v | 102 +++++ fpga/usrp3/lib/rfnoc/fosphor/delay.v | 140 ++++++ fpga/usrp3/lib/rfnoc/fosphor/f15_avg.v | 117 +++++ fpga/usrp3/lib/rfnoc/fosphor/f15_binmap.v | 139 ++++++ fpga/usrp3/lib/rfnoc/fosphor/f15_core.v | 609 ++++++++++++++++++++++++++ fpga/usrp3/lib/rfnoc/fosphor/f15_eoseq.v | 78 ++++ fpga/usrp3/lib/rfnoc/fosphor/f15_histo_mem.v | 287 ++++++++++++ fpga/usrp3/lib/rfnoc/fosphor/f15_line_mem.v | 67 +++ fpga/usrp3/lib/rfnoc/fosphor/f15_logpwr.v | 504 +++++++++++++++++++++ fpga/usrp3/lib/rfnoc/fosphor/f15_maxhold.v | 71 +++ fpga/usrp3/lib/rfnoc/fosphor/f15_packetizer.v | 136 ++++++ fpga/usrp3/lib/rfnoc/fosphor/f15_rise_decay.v | 160 +++++++ fpga/usrp3/lib/rfnoc/fosphor/f15_wf_agg.v | 189 ++++++++ fpga/usrp3/lib/rfnoc/fosphor/fifo_srl.v | 169 +++++++ fpga/usrp3/lib/rfnoc/fosphor/rng.v | 87 ++++ 15 files changed, 2855 insertions(+) create mode 100644 fpga/usrp3/lib/rfnoc/fosphor/axi_logpwr.v create mode 100644 fpga/usrp3/lib/rfnoc/fosphor/delay.v create mode 100644 fpga/usrp3/lib/rfnoc/fosphor/f15_avg.v create mode 100644 fpga/usrp3/lib/rfnoc/fosphor/f15_binmap.v create mode 100644 fpga/usrp3/lib/rfnoc/fosphor/f15_core.v create mode 100644 fpga/usrp3/lib/rfnoc/fosphor/f15_eoseq.v create mode 100644 fpga/usrp3/lib/rfnoc/fosphor/f15_histo_mem.v create mode 100644 fpga/usrp3/lib/rfnoc/fosphor/f15_line_mem.v create mode 100644 fpga/usrp3/lib/rfnoc/fosphor/f15_logpwr.v create mode 100644 fpga/usrp3/lib/rfnoc/fosphor/f15_maxhold.v create mode 100644 fpga/usrp3/lib/rfnoc/fosphor/f15_packetizer.v create mode 100644 fpga/usrp3/lib/rfnoc/fosphor/f15_rise_decay.v create mode 100644 fpga/usrp3/lib/rfnoc/fosphor/f15_wf_agg.v create mode 100644 fpga/usrp3/lib/rfnoc/fosphor/fifo_srl.v create mode 100644 fpga/usrp3/lib/rfnoc/fosphor/rng.v (limited to 'fpga/usrp3/lib/rfnoc/fosphor') diff --git a/fpga/usrp3/lib/rfnoc/fosphor/axi_logpwr.v b/fpga/usrp3/lib/rfnoc/fosphor/axi_logpwr.v new file mode 100644 index 000000000..037c33563 --- /dev/null +++ b/fpga/usrp3/lib/rfnoc/fosphor/axi_logpwr.v @@ -0,0 +1,102 @@ +/* + * axi_logpwr.v + * + * Copyright (C) 2014 Ettus Corporation LLC + * Copyright 2018 Ettus Research, a National Instruments Company + * + * SPDX-License-Identifier: LGPL-3.0-or-later + * + * vim: ts=4 sw=4 + */ + +`ifdef SIM +`default_nettype none +`endif + +module axi_logpwr #( + parameter [1:0] RANDOM_MODE = 2'b11 +)( + input clk, input reset, + input [31:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, + output [15:0] o_tdata, output o_tlast, output o_tvalid, input o_tready +); + + // Signals + reg ready; + reg valid_1; + wire valid_12; + wire last_12; + + wire [31:0] rng; + + wire [15:0] in_real_0; + wire [15:0] in_imag_0; + wire [15:0] out_logpwr_12; + + wire [16:0] fifo_di; + wire [16:0] fifo_do; + wire fifo_wren; + wire fifo_afull; + wire fifo_rden; + wire fifo_empty; + + // Input control + assign in_real_0 = i_tdata[31:16]; + assign in_imag_0 = i_tdata[15:0]; + + always @(posedge clk) + begin + ready <= ~fifo_afull | o_tready; + valid_1 <= i_tvalid & ready; + end + + assign i_tready = ready; + + // Delays + delay_bit #(11) dl_valid (valid_1, valid_12, clk); + delay_bit #(12) dl_last (i_tlast, last_12, clk); + + // RNG Instance + rng rng_I ( + .out(rng), + .clk(clk), + .rst(reset) + ); + + // logpwr Instance + f15_logpwr logpwr_I ( + .in_real_0(in_real_0), + .in_imag_0(in_imag_0), + .out_12(out_logpwr_12), + .rng(rng), + .random_mode(RANDOM_MODE), + .clk(clk), + .rst(reset) + ); + + // Output FIFO + assign fifo_di = { last_12, out_logpwr_12 }; + assign fifo_wren = { valid_12 }; + + fifo_srl #( + .WIDTH(17), + .LOG2_DEPTH(6), + .AFULL_LEVEL(49) + ) fifo_I ( + .di(fifo_di), + .wren(fifo_wren), + .afull(fifo_afull), + .do(fifo_do), + .rden(fifo_rden), + .empty(fifo_empty), + .clk(clk), + .rst(reset) + ); + + assign o_tdata = fifo_do[15:0]; + assign o_tlast = fifo_do[16]; + assign o_tvalid = ~fifo_empty; + + assign fifo_rden = ~fifo_empty & o_tready; + +endmodule // axi_logpwr diff --git a/fpga/usrp3/lib/rfnoc/fosphor/delay.v b/fpga/usrp3/lib/rfnoc/fosphor/delay.v new file mode 100644 index 000000000..44c043642 --- /dev/null +++ b/fpga/usrp3/lib/rfnoc/fosphor/delay.v @@ -0,0 +1,140 @@ +/* + * delay.v + * + * Generates a delay line/bus using a combination of SRL and Register + * + * Copyright (C) 2014 Ettus Corporation LLC + * Copyright 2018 Ettus Research, a National Instruments Company + * + * SPDX-License-Identifier: LGPL-3.0-or-later + * + * vim: ts=4 sw=4 + */ + +`ifdef SIM +`default_nettype none +`endif + +// --------------------------------------------------------------------------- +// Single line delay +// --------------------------------------------------------------------------- + +module delay_bit #( + parameter integer DELAY = 1 +)( + input wire d, + output wire q, + input wire clk +); + + // Signals + wire [4:0] addr = DELAY - 2; + wire ff_in; + + // Generate SRL if needed (or bypass if not) + generate + if (DELAY > 17) begin + SRLC32E srl_I ( + .Q(ff_in), + .A(addr), + .CE(1'b1), + .CLK(clk), + .D(d) + ); + end else if (DELAY > 1) begin + SRL16E srl_I ( + .Q(ff_in), + .A0(addr[0]), + .A1(addr[1]), + .A2(addr[2]), + .A3(addr[3]), + .CE(1'b1), + .CLK(clk), + .D(d) + ); + end else begin + assign ff_in = d; + end + endgenerate + + // Generate flip-flop if needed (or bypass if not) + generate + if (DELAY > 0) begin + FDRE ff_I ( + .Q(q), + .C(clk), + .CE(1'b1), + .D(ff_in), + .R(1'b0) + ); + end else begin + assign q = ff_in; + end + endgenerate + +endmodule // delay_bit + + +// --------------------------------------------------------------------------- +// Bus delay +// --------------------------------------------------------------------------- + +module delay_bus #( + parameter integer DELAY = 1, + parameter integer WIDTH = 1 +)( + input wire [WIDTH-1:0] d, + output wire [WIDTH-1:0] q, + input wire clk +); + genvar i; + + // Variables / Signals + wire [4:0] addr = DELAY - 2; + wire [WIDTH-1:0] ff_in; + + // Generate SRL if needed (or bypass if not) + generate + if (DELAY > 17) begin + for (i=0; i 1) begin + for (i=0; i 0) begin + for (i=0; i take r_2 + // - If overflow = 1 -> sature to all 1's + // If max-hold + // - If overflow = 0 -> take y_2 + // - If overflow = 1 -> take x_2 + if (init_2) + y_3 <= x_2; + else if (cfg_mode) + y_3 <= over_2 ? { (Y_WIDTH){1'b1} } : r_2[R_WIDTH-2:R_WIDTH-Y_WIDTH-1]; + else + y_3 <= over_2 ? x_2 : y_2; + end + + assign yout_3 = y_3; + assign zout_3 = y_3[Y_WIDTH-1:Y_WIDTH-8]; + + + // Control + // ------- + + // 1-in-N decimation counter + always @(posedge clk) + begin + if (rst) + decim_cnt <= 0; + else if (cfg_decim_changed) + // Force Reload + decim_cnt <= { 1'b0, cfg_decim }; + else if (valid_0 & last_0) + if (decim_cnt[DECIM_WIDTH]) + // Reload + decim_cnt <= { 1'b0, cfg_decim }; + else + // Just decrement + decim_cnt <= decim_cnt - 1; + end + + // Decimation flush & init states + always @(posedge clk) + begin + if (rst) begin + // Initial state + flush_0 <= 1'b0; + init_0 <= 1'b1; + init_force_0 <= 1'b0; + end else begin + if (valid_0 & last_0) begin + // Flushing + flush_0 <= decim_cnt[DECIM_WIDTH]; + + // Init after flush or if forced + init_0 <= flush_0 | init_force_0; + end + + // Init forcing after a decim change + if (cfg_decim_changed) + init_force_0 <= 1'b1; + else if (valid_0 & last_0) + init_force_0 <= 1'b0; + end + end + + delay_bit #(2) dl_init(init_0, init_2, clk); + + // Z-output valid + always @(posedge clk) + zvalid_1 <= valid_0 & flush_0; + + delay_bit #(2) dl_zvalid(zvalid_1, zvalid_3, clk); + +endmodule // f15_wf_agg diff --git a/fpga/usrp3/lib/rfnoc/fosphor/fifo_srl.v b/fpga/usrp3/lib/rfnoc/fosphor/fifo_srl.v new file mode 100644 index 000000000..700da18d3 --- /dev/null +++ b/fpga/usrp3/lib/rfnoc/fosphor/fifo_srl.v @@ -0,0 +1,169 @@ +/* + * fifo_srl.v + * + * Very small/light-weight FIFO using SRL. + * Only for synchronous design. Has a fixed depth of 15 or 31 entries and + * always work in the so-called first-word-fall-thru mode. + * + * Copyright (C) 2014 Ettus Corporation LLC + * Copyright 2018 Ettus Research, a National Instruments Company + * + * SPDX-License-Identifier: LGPL-3.0-or-later + * + * vim: ts=4 sw=4 + */ + +`ifdef SIM +`default_nettype none +`endif + +module fifo_srl #( + parameter integer WIDTH = 4, + parameter integer LOG2_DEPTH = 5, // 4 or 5 + parameter integer AFULL_LEVEL = -1 // -1 -> No AFULL + +)( + input wire [WIDTH-1:0] di, + input wire wren, + output wire full, + output wire afull, + + output reg [WIDTH-1:0] do, + input wire rden, + output reg empty, + + input wire clk, + input wire rst +); + + genvar i; + + // Signals + wire [WIDTH-1:0] srl_q; + reg [LOG2_DEPTH-1:0] srl_addr; + wire srl_addr_ce; + + wire srl_write; + wire srl_read; + + wire srl_full; + wire srl_afull; + reg srl_empty; + wire srl_aempty; + + // Instanciate the SRLs + generate + if (LOG2_DEPTH == 6) begin + wire [WIDTH-1:0] srl0_q31, srl0_q, srl1_q; + + for (i=0; i= AFULL_LEVEL) && ~&(srl_addr); + end else begin + assign srl_afull = 1'b0; + end + endgenerate + + assign srl_aempty = &(~srl_addr); + + always @(posedge clk) + begin + if (rst) + srl_empty <= 1'b1; + else if (srl_addr_ce) + srl_empty <= srl_aempty & srl_read; + end + + // Output register (to capture whatever comes out from SRL) + always @(posedge clk) + begin + if (srl_read) + do <= srl_q; + end + + // Control and flag generation + // Write/Full is easy + assign srl_write = wren; + assign full = srl_full; + assign afull = srl_afull; + + // Read/Empty is tricky + always @(posedge clk) + begin + if (rst) + empty <= 1'b1; + else if (rden | srl_read) + empty <= srl_empty; + end + + assign srl_read = (rden | empty) & ~srl_empty; + +endmodule // fifo_srl diff --git a/fpga/usrp3/lib/rfnoc/fosphor/rng.v b/fpga/usrp3/lib/rfnoc/fosphor/rng.v new file mode 100644 index 000000000..6d6715fd0 --- /dev/null +++ b/fpga/usrp3/lib/rfnoc/fosphor/rng.v @@ -0,0 +1,87 @@ +/* + * rng.v + * + * Very simple 32-bits PRNG using a few underlying LFSR. + * + * Copyright (C) 2014 Ettus Corporation LLC + * Copyright 2018 Ettus Research, a National Instruments Company + * + * SPDX-License-Identifier: LGPL-3.0-or-later + * + * vim: ts=4 sw=4 + */ + +`ifdef SIM +`default_nettype none +`endif + +// --------------------------------------------------------------------------- +// Main RNG +// --------------------------------------------------------------------------- + +module rng( + output reg [31:0] out, + input wire clk, + input wire rst +); + + // Signals + wire [4:0] out5, out5rev; + wire [7:0] out8; + wire [11:0] out12; + wire [15:0] out16; + + // Instanciate 4 LFSRs of different lengths + lfsr #(.WIDTH( 5), .POLY( 5'b01001)) lfsr5 (.out(out5), .clk(clk), .rst(rst)); + lfsr #(.WIDTH( 8), .POLY( 8'h71 )) lfsr8 (.out(out8), .clk(clk), .rst(rst)); + lfsr #(.WIDTH(12), .POLY(12'hc11 )) lfsr12 (.out(out12), .clk(clk), .rst(rst)); + lfsr #(.WIDTH(16), .POLY(16'h6701 )) lfsr16 (.out(out16), .clk(clk), .rst(rst)); + + // Reverse the 5 bit LFSR output + genvar i; + generate + for (i=0; i<5; i=i+1) + assign out5rev[i] = out5[4-i]; + endgenerate + + // Combine the outputs 'somehow' + always @(posedge clk) + out <= { + out16[15:11] ^ out5rev, // 5 bits + out16[10:2], // 9 bits + out16[1:0] ^ out12[11:10], // 2 bits + out12[9:2], // 8 bits + out12[1:0] ^ out8[7:6], // 2 bits + out8[5:0] // 6 bits + }; + +endmodule // rng + + +// --------------------------------------------------------------------------- +// LFSR sub module +// --------------------------------------------------------------------------- + +module lfsr #( + parameter integer WIDTH = 8, + parameter POLY = 8'h71 +)( + output reg [WIDTH-1:0] out, + input wire clk, + input wire rst +); + + // Signals + wire fb; + + // Linear Feedback + assign fb = ^(out & POLY); + + // Register + always @(posedge clk) + if (rst) + out <= { {(WIDTH-1){1'b0}}, 1'b1 }; + else + out <= { fb, out[WIDTH-1:1] }; + +endmodule // lfsr -- cgit v1.2.3