From ff1546f8137f7f92bb250f685561b0c34cc0e053 Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Fri, 14 Feb 2014 12:05:07 -0800 Subject: Pushing the bulk of UHD-3.7.0 code. --- fpga/usrp3/lib/fifo/Makefile.srcs | 1 + fpga/usrp3/lib/fifo/axi_fifo.v | 14 +-- fpga/usrp3/lib/fifo/axi_fifo_2clk.v | 14 +-- fpga/usrp3/lib/fifo/axi_fifo_short.v | 14 +-- fpga/usrp3/lib/fifo/axi_filter_mux4.v | 154 +++++++++++++++++++++++++++++++++ fpga/usrp3/lib/fifo/axi_packet_gate.v | 14 +-- fpga/usrp3/lib/fifo/monitor_axi_fifo.v | 14 +-- fpga/usrp3/lib/fifo/shortfifo.v | 14 +-- 8 files changed, 161 insertions(+), 78 deletions(-) create mode 100644 fpga/usrp3/lib/fifo/axi_filter_mux4.v (limited to 'fpga/usrp3/lib/fifo') diff --git a/fpga/usrp3/lib/fifo/Makefile.srcs b/fpga/usrp3/lib/fifo/Makefile.srcs index ffe2484f8..389766605 100644 --- a/fpga/usrp3/lib/fifo/Makefile.srcs +++ b/fpga/usrp3/lib/fifo/Makefile.srcs @@ -17,4 +17,5 @@ axi_fifo64_to_fifo32.v \ axi_fifo32_to_fifo64.v \ axi_fifo_2clk.v \ axi_loopback.v \ +axi_filter_mux4.v \ )) diff --git a/fpga/usrp3/lib/fifo/axi_fifo.v b/fpga/usrp3/lib/fifo/axi_fifo.v index efc8f02f1..2f42fc181 100644 --- a/fpga/usrp3/lib/fifo/axi_fifo.v +++ b/fpga/usrp3/lib/fifo/axi_fifo.v @@ -1,19 +1,7 @@ // // Copyright 2012-2013 Ettus Research LLC // -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// + // Block RAM AXI fifo diff --git a/fpga/usrp3/lib/fifo/axi_fifo_2clk.v b/fpga/usrp3/lib/fifo/axi_fifo_2clk.v index 889bc0f9a..f9f7beb88 100644 --- a/fpga/usrp3/lib/fifo/axi_fifo_2clk.v +++ b/fpga/usrp3/lib/fifo/axi_fifo_2clk.v @@ -1,19 +1,7 @@ // // Copyright 2013 Ettus Research LLC // -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// + // Special case SIZE <= 5 uses a short fifo diff --git a/fpga/usrp3/lib/fifo/axi_fifo_short.v b/fpga/usrp3/lib/fifo/axi_fifo_short.v index db34af082..e13993199 100644 --- a/fpga/usrp3/lib/fifo/axi_fifo_short.v +++ b/fpga/usrp3/lib/fifo/axi_fifo_short.v @@ -1,19 +1,7 @@ // // Copyright 2012 Ettus Research LLC // -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// + // // 32 word FIFO with AXI4-STREAM interface. diff --git a/fpga/usrp3/lib/fifo/axi_filter_mux4.v b/fpga/usrp3/lib/fifo/axi_filter_mux4.v new file mode 100644 index 000000000..cdc314e5f --- /dev/null +++ b/fpga/usrp3/lib/fifo/axi_filter_mux4.v @@ -0,0 +1,154 @@ +// Copyright 2014 Ettus Research LLC +// axi_filter_mux -- takes 4 64-bit AXI stream of CHDR data, merges them to 1 output channel +// Round-robin if PRIO=0, priority if PRIO=1 (lower number ports get priority) +// Bubble cycles are inserted after each packet in PRIO mode, or on wraparound in Round Robin mode. +// Filter forces specific destination SID to pass per port, else dump data to /dev/null + +module axi_filter_mux4 + #(parameter PRIO=0, + parameter WIDTH=64, + parameter BUFFER=0, + parameter FILTER0 =0, + parameter FILTER1 =0, + parameter FILTER2 =0, + parameter FILTER3 =0 + ) + (input clk, input reset, input clear, + input [WIDTH-1:0] i0_tdata, input i0_tlast, input i0_tvalid, output i0_tready, + input [WIDTH-1:0] i1_tdata, input i1_tlast, input i1_tvalid, output i1_tready, + input [WIDTH-1:0] i2_tdata, input i2_tlast, input i2_tvalid, output i2_tready, + input [WIDTH-1:0] i3_tdata, input i3_tlast, input i3_tvalid, output i3_tready, + output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready); + + wire [WIDTH-1:0] o_tdata_int; + wire o_tlast_int, o_tvalid_int, o_tready_int; + + reg [3:0] mx_state; + reg filter_packet; + + localparam MX_IDLE = 4'b0000; + localparam MX_0 = 4'b0001; + localparam MX_1 = 4'b0010; + localparam MX_2 = 4'b0100; + localparam MX_3 = 4'b1000; + + + assign good0 = i0_tdata[15:0]==FILTER0; + assign good1 = i1_tdata[15:0]==FILTER1; + assign good2 = i2_tdata[15:0]==FILTER2; + assign good3 = i3_tdata[15:0]==FILTER3; + + always @(posedge clk) + if(reset | clear) + mx_state <= MX_IDLE; + else + case (mx_state) + MX_IDLE : + if(i0_tvalid) begin + mx_state <= MX_0; + filter_packet <= !good0; + end + else if(i1_tvalid) begin + mx_state <= MX_1; + filter_packet <= !good1; + end + else if(i2_tvalid) begin + mx_state <= MX_2; + filter_packet <= !good2; + end + else if(i3_tvalid) begin + mx_state <= MX_3; + filter_packet <= !good3; + end + + MX_0 : + if(o_tready_int & o_tvalid_int & o_tlast_int) + if(PRIO) + mx_state <= MX_IDLE; + else if(i1_tvalid) begin + mx_state <= MX_1; + filter_packet <= !good1; + end + else if(i2_tvalid) begin + mx_state <= MX_2; + filter_packet <= !good2; + end + else if(i3_tvalid) begin + mx_state <= MX_3; + filter_packet <= !good3; + end + else begin + mx_state <= MX_IDLE; + filter_packet <= 0; + end + + MX_1 : + if(o_tready_int & o_tvalid_int & o_tlast_int) + if(PRIO) + mx_state <= MX_IDLE; + else if(i2_tvalid) begin + mx_state <= MX_2; + filter_packet <= !good2; + end + else if(i3_tvalid) begin + mx_state <= MX_3; + filter_packet <= !good3; + end + else begin + mx_state <= MX_IDLE; + filter_packet <= 0; + end + MX_2 : + if(o_tready_int & o_tvalid_int & o_tlast_int) + if(PRIO) + mx_state <= MX_IDLE; + else if(i3_tvalid) begin + mx_state <= MX_3; + filter_packet <= !good3; + end + else begin + mx_state <= MX_IDLE; + filter_packet <= 0; + end + MX_3 : + if(o_tready_int & o_tvalid_int & o_tlast_int) + begin + mx_state <= MX_IDLE; + filter_packet <= 0; + end + + default : + mx_state <= MX_IDLE; + endcase // case (mx_state) + + assign {i3_tready, i2_tready, i1_tready, i0_tready} = mx_state & {4{o_tready_int}}; + + assign o_tvalid_int = |(mx_state & ({i3_tvalid, i2_tvalid, i1_tvalid, i0_tvalid})); + + assign {o_tlast_int, o_tdata_int} = mx_state[3] ? {i3_tlast, i3_tdata} : + mx_state[2] ? {i2_tlast, i2_tdata} : + mx_state[1] ? {i1_tlast, i1_tdata} : + {i0_tlast, i0_tdata}; + + generate + if(BUFFER == 0) + begin + assign o_tdata = o_tdata_int; + assign o_tlast = o_tlast_int; + assign o_tvalid = o_tvalid_int & !filter_packet; + assign o_tready_int = o_tready | filter_packet; + end + else + begin + wire o_tready_int_fifo; + assign o_tready_int = o_tready_int_fifo | filter_packet; + + axi_fifo_short #(.WIDTH(WIDTH+1)) axi_fifo_short + (.clk(clk), .reset(reset), .clear(clear), + .i_tdata({o_tlast_int,o_tdata_int}), .i_tvalid(o_tvalid_int & !filter_packet), .i_tready(o_tready_int_fifo), + .o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready), + .space(), .occupied()); + end + endgenerate + +endmodule // axi__mux4 diff --git a/fpga/usrp3/lib/fifo/axi_packet_gate.v b/fpga/usrp3/lib/fifo/axi_packet_gate.v index e1f999250..6d10a8cf4 100644 --- a/fpga/usrp3/lib/fifo/axi_packet_gate.v +++ b/fpga/usrp3/lib/fifo/axi_packet_gate.v @@ -1,19 +1,7 @@ // // Copyright 2012 Ettus Research LLC // -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// + // Hold packets in fifo until they are complete. This prevents slowly-built packets // from clogging up the downstream. This block will hold up to 255 packets. diff --git a/fpga/usrp3/lib/fifo/monitor_axi_fifo.v b/fpga/usrp3/lib/fifo/monitor_axi_fifo.v index 504296e92..f5d73455f 100644 --- a/fpga/usrp3/lib/fifo/monitor_axi_fifo.v +++ b/fpga/usrp3/lib/fifo/monitor_axi_fifo.v @@ -1,19 +1,7 @@ // // Copyright 2012 Ettus Research LLC // -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// + // // This module is instantiated in parallel with a FIFO with AXI4-STREAM interfaces. diff --git a/fpga/usrp3/lib/fifo/shortfifo.v b/fpga/usrp3/lib/fifo/shortfifo.v index c7c916375..fbf92e2ed 100644 --- a/fpga/usrp3/lib/fifo/shortfifo.v +++ b/fpga/usrp3/lib/fifo/shortfifo.v @@ -1,19 +1,7 @@ // // Copyright 2011 Ettus Research LLC // -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// + module shortfifo -- cgit v1.2.3