From 0df4b801a34697f2058b4a7b95e08d2a0576c9db Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Thu, 10 Oct 2013 10:17:27 -0700 Subject: Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus. --- fpga/usrp3/lib/fifo/Makefile.srcs | 20 +++ fpga/usrp3/lib/fifo/axi_demux4.v | 77 +++++++++++ fpga/usrp3/lib/fifo/axi_demux8.v | 60 ++++++++ fpga/usrp3/lib/fifo/axi_fifo.v | 169 +++++++++++++++++++++++ fpga/usrp3/lib/fifo/axi_fifo32_to_fifo64.v | 38 ++++++ fpga/usrp3/lib/fifo/axi_fifo64_to_fifo32.v | 31 +++++ fpga/usrp3/lib/fifo/axi_fifo_2clk.v | 88 ++++++++++++ fpga/usrp3/lib/fifo/axi_fifo_32_64_tb.v | 114 ++++++++++++++++ fpga/usrp3/lib/fifo/axi_fifo_short.v | 110 +++++++++++++++ fpga/usrp3/lib/fifo/axi_fifo_tb.v | 211 +++++++++++++++++++++++++++++ fpga/usrp3/lib/fifo/axi_loopback.v | 71 ++++++++++ fpga/usrp3/lib/fifo/axi_mux4.v | 112 +++++++++++++++ fpga/usrp3/lib/fifo/axi_mux8.v | 56 ++++++++ fpga/usrp3/lib/fifo/axi_packet_gate.v | 78 +++++++++++ fpga/usrp3/lib/fifo/axi_packet_gate_tb.v | 106 +++++++++++++++ fpga/usrp3/lib/fifo/monitor_axi_fifo.v | 123 +++++++++++++++++ fpga/usrp3/lib/fifo/shortfifo.v | 92 +++++++++++++ 17 files changed, 1556 insertions(+) create mode 100644 fpga/usrp3/lib/fifo/Makefile.srcs create mode 100644 fpga/usrp3/lib/fifo/axi_demux4.v create mode 100644 fpga/usrp3/lib/fifo/axi_demux8.v create mode 100644 fpga/usrp3/lib/fifo/axi_fifo.v create mode 100644 fpga/usrp3/lib/fifo/axi_fifo32_to_fifo64.v create mode 100644 fpga/usrp3/lib/fifo/axi_fifo64_to_fifo32.v create mode 100644 fpga/usrp3/lib/fifo/axi_fifo_2clk.v create mode 100644 fpga/usrp3/lib/fifo/axi_fifo_32_64_tb.v create mode 100644 fpga/usrp3/lib/fifo/axi_fifo_short.v create mode 100644 fpga/usrp3/lib/fifo/axi_fifo_tb.v create mode 100644 fpga/usrp3/lib/fifo/axi_loopback.v create mode 100644 fpga/usrp3/lib/fifo/axi_mux4.v create mode 100644 fpga/usrp3/lib/fifo/axi_mux8.v create mode 100644 fpga/usrp3/lib/fifo/axi_packet_gate.v create mode 100644 fpga/usrp3/lib/fifo/axi_packet_gate_tb.v create mode 100644 fpga/usrp3/lib/fifo/monitor_axi_fifo.v create mode 100644 fpga/usrp3/lib/fifo/shortfifo.v (limited to 'fpga/usrp3/lib/fifo') diff --git a/fpga/usrp3/lib/fifo/Makefile.srcs b/fpga/usrp3/lib/fifo/Makefile.srcs new file mode 100644 index 000000000..ffe2484f8 --- /dev/null +++ b/fpga/usrp3/lib/fifo/Makefile.srcs @@ -0,0 +1,20 @@ +# +# Copyright 2012-2013 Ettus Research LLC +# + +################################################## +# FIFO Sources +################################################## +FIFO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/fifo/, \ +axi_mux4.v \ +axi_mux8.v \ +axi_demux4.v \ +axi_demux8.v \ +axi_fifo_short.v \ +axi_packet_gate.v \ +axi_fifo.v \ +axi_fifo64_to_fifo32.v \ +axi_fifo32_to_fifo64.v \ +axi_fifo_2clk.v \ +axi_loopback.v \ +)) diff --git a/fpga/usrp3/lib/fifo/axi_demux4.v b/fpga/usrp3/lib/fifo/axi_demux4.v new file mode 100644 index 000000000..c613b064d --- /dev/null +++ b/fpga/usrp3/lib/fifo/axi_demux4.v @@ -0,0 +1,77 @@ + +// Copyright 2012 Ettus Research LLC +// axi_demux -- takes one AXI stream, sends to one of 4 output channels +// Choice of output channel is by external logic based on first line of packet ("header" port) +// If compressed vita data, this line contains vita header and streamid. + +module axi_demux4 + #(parameter ACTIVE_CHAN = 4'b1111, // ACTIVE_CHAN is a map of connected outputs + parameter WIDTH = 64, + parameter BUFFER=0) + (input clk, input reset, input clear, + output [WIDTH-1:0] header, input [1:0] dest, + input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, + output [WIDTH-1:0] o0_tdata, output o0_tlast, output o0_tvalid, input o0_tready, + output [WIDTH-1:0] o1_tdata, output o1_tlast, output o1_tvalid, input o1_tready, + output [WIDTH-1:0] o2_tdata, output o2_tlast, output o2_tvalid, input o2_tready, + output [WIDTH-1:0] o3_tdata, output o3_tlast, output o3_tvalid, input o3_tready); + + wire [WIDTH-1:0] i_tdata_int; + wire i_tlast_int, i_tvalid_int, i_tready_int; + + generate + if(BUFFER == 0) + begin + assign i_tdata_int = i_tdata; + assign i_tlast_int = i_tlast; + assign i_tvalid_int = i_tvalid; + assign i_tready = i_tready_int; + end + else + axi_fifo_short #(.WIDTH(WIDTH+1)) axi_fifo_short + (.clk(clk), .reset(reset), .clear(clear), + .i_tdata({i_tlast,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready), + .o_tdata({i_tlast_int,i_tdata_int}), .o_tvalid(i_tvalid_int), .o_tready(i_tready_int), + .space(), .occupied()); + endgenerate + + reg [3:0] dm_state; + localparam DM_IDLE = 4'b0000; + localparam DM_0 = 4'b0001; + localparam DM_1 = 4'b0010; + localparam DM_2 = 4'b0100; + localparam DM_3 = 4'b1000; + + assign header = i_tdata_int; + + always @(posedge clk) + if(reset | clear) + dm_state <= DM_IDLE; + else + case (dm_state) + DM_IDLE : + if(i_tvalid_int) + case(dest) + 2'b00 : dm_state <= DM_0; + 2'b01 : dm_state <= DM_1; + 2'b10 : dm_state <= DM_2; + 2'b11 : dm_state <= DM_3; + endcase // case (i_tdata[1:0]) + + DM_0, DM_1, DM_2, DM_3 : + if(i_tvalid_int & i_tready_int & i_tlast_int) + dm_state <= DM_IDLE; + + default : + dm_state <= DM_IDLE; + endcase // case (dm_state) + + assign {o3_tvalid, o2_tvalid, o1_tvalid, o0_tvalid} = dm_state & {4{i_tvalid_int}}; + assign i_tready_int = |(dm_state & ({o3_tready, o2_tready, o1_tready, o0_tready} | ~ACTIVE_CHAN)); + + assign {o0_tlast, o0_tdata} = {i_tlast_int, i_tdata_int}; + assign {o1_tlast, o1_tdata} = {i_tlast_int, i_tdata_int}; + assign {o2_tlast, o2_tdata} = {i_tlast_int, i_tdata_int}; + assign {o3_tlast, o3_tdata} = {i_tlast_int, i_tdata_int}; + +endmodule // axi_demux4 diff --git a/fpga/usrp3/lib/fifo/axi_demux8.v b/fpga/usrp3/lib/fifo/axi_demux8.v new file mode 100644 index 000000000..9aa51674d --- /dev/null +++ b/fpga/usrp3/lib/fifo/axi_demux8.v @@ -0,0 +1,60 @@ + +// Copyright 2012 Ettus Research LLC +// axi_demux -- takes one AXI stream, sends to one of 8 output channels +// Choice of output channel is by external logic based on first line of packet ("header" port) +// If compressed vita data, this line contains vita header and streamid. + +module axi_demux8 #( + parameter ACTIVE_CHAN = 8'b11111111, // ACTIVE_CHAN is a map of connected outputs + parameter WIDTH = 64, + parameter BUFFER=0 +) ( + input clk, input reset, input clear, + output [WIDTH-1:0] header, input [2:0] dest, + input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, + output [WIDTH-1:0] o0_tdata, output o0_tlast, output o0_tvalid, input o0_tready, + output [WIDTH-1:0] o1_tdata, output o1_tlast, output o1_tvalid, input o1_tready, + output [WIDTH-1:0] o2_tdata, output o2_tlast, output o2_tvalid, input o2_tready, + output [WIDTH-1:0] o3_tdata, output o3_tlast, output o3_tvalid, input o3_tready, + output [WIDTH-1:0] o4_tdata, output o4_tlast, output o4_tvalid, input o4_tready, + output [WIDTH-1:0] o5_tdata, output o5_tlast, output o5_tvalid, input o5_tready, + output [WIDTH-1:0] o6_tdata, output o6_tlast, output o6_tvalid, input o6_tready, + output [WIDTH-1:0] o7_tdata, output o7_tlast, output o7_tvalid, input o7_tready +); + + wire [WIDTH-1:0] i_tdata_int0, i_tdata_int1; + wire i_tlast_int0, i_tlast_int1; + wire i_tvalid_int0, i_tvalid_int1; + wire i_tready_int0, i_tready_int1; + + axi_demux4 #(.ACTIVE_CHAN({2'b00, (|(ACTIVE_CHAN[7:4])), (|(ACTIVE_CHAN[3:0]))}), .WIDTH(WIDTH), .BUFFER(BUFFER)) demux2 ( + .clk(clk), .reset(reset), .clear(clear), + .header(header), .dest({1'b0, dest[2]}), + .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready), + .o0_tdata(i_tdata_int0), .o0_tlast(i_tlast_int0), .o0_tvalid(i_tvalid_int0), .o0_tready(i_tready_int0), + .o1_tdata(i_tdata_int1), .o1_tlast(i_tlast_int1), .o1_tvalid(i_tvalid_int1), .o1_tready(i_tready_int1), + .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b0), + .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b0) + ); + + axi_demux4 #(.ACTIVE_CHAN(ACTIVE_CHAN[3:0]), .WIDTH(WIDTH), .BUFFER(0)) demux4_int0 ( + .clk(clk), .reset(reset), .clear(clear), + .header(), .dest(dest[1:0]), + .i_tdata(i_tdata_int0), .i_tlast(i_tlast_int0), .i_tvalid(i_tvalid_int0), .i_tready(i_tready_int0), + .o0_tdata(o0_tdata), .o0_tlast(o0_tlast), .o0_tvalid(o0_tvalid), .o0_tready(o0_tready), + .o1_tdata(o1_tdata), .o1_tlast(o1_tlast), .o1_tvalid(o1_tvalid), .o1_tready(o1_tready), + .o2_tdata(o2_tdata), .o2_tlast(o2_tlast), .o2_tvalid(o2_tvalid), .o2_tready(o2_tready), + .o3_tdata(o3_tdata), .o3_tlast(o3_tlast), .o3_tvalid(o3_tvalid), .o3_tready(o3_tready) + ); + + axi_demux4 #(.ACTIVE_CHAN(ACTIVE_CHAN[7:4]), .WIDTH(WIDTH), .BUFFER(0)) demux4_int1 ( + .clk(clk), .reset(reset), .clear(clear), + .header(), .dest(dest[1:0]), + .i_tdata(i_tdata_int1), .i_tlast(i_tlast_int1), .i_tvalid(i_tvalid_int1), .i_tready(i_tready_int1), + .o0_tdata(o4_tdata), .o0_tlast(o4_tlast), .o0_tvalid(o4_tvalid), .o0_tready(o4_tready), + .o1_tdata(o5_tdata), .o1_tlast(o5_tlast), .o1_tvalid(o5_tvalid), .o1_tready(o5_tready), + .o2_tdata(o6_tdata), .o2_tlast(o6_tlast), .o2_tvalid(o6_tvalid), .o2_tready(o6_tready), + .o3_tdata(o7_tdata), .o3_tlast(o7_tlast), .o3_tvalid(o7_tvalid), .o3_tready(o7_tready) + ); + +endmodule // axi_demux4 diff --git a/fpga/usrp3/lib/fifo/axi_fifo.v b/fpga/usrp3/lib/fifo/axi_fifo.v new file mode 100644 index 000000000..2f42fc181 --- /dev/null +++ b/fpga/usrp3/lib/fifo/axi_fifo.v @@ -0,0 +1,169 @@ +// +// Copyright 2012-2013 Ettus Research LLC +// + + + +// Block RAM AXI fifo + +// Special case SIZE <= 5 uses a short fifo + +module axi_fifo + #(parameter WIDTH=32, SIZE=9) + (input clk, input reset, input clear, + input [WIDTH-1:0] i_tdata, + input i_tvalid, + output i_tready, + output [WIDTH-1:0] o_tdata, + output o_tvalid, + input o_tready, + + output reg [15:0] space, + output reg [15:0] occupied); + + generate + if(SIZE<=5) begin + wire [5:0] space_short, occupied_short; + axi_fifo_short #(.WIDTH(WIDTH)) fifo_short + ( + .clk(clk), .reset(reset), .clear(clear), + .i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready), + .o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready), + .space(space_short), .occupied(occupied_short) + ); + always @* space <= {10'b0, space_short}; + always @* occupied <= {10'b0, occupied_short}; + end + else begin + + wire write = i_tvalid & i_tready; + wire read = o_tvalid & o_tready; + wire full, empty; + + assign i_tready = ~full; + assign o_tvalid = ~empty; + + // Read side states + localparam EMPTY = 0; + localparam PRE_READ = 1; + localparam READING = 2; + + reg [SIZE-1:0] wr_addr, rd_addr; + reg [1:0] read_state; + + reg empty_reg, full_reg; + always @(posedge clk) + if(reset) + wr_addr <= 0; + else if(clear) + wr_addr <= 0; + else if(write) + wr_addr <= wr_addr + 1; + + ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE)) + ram (.clka(clk), + .ena(1'b1), + .wea(write), + .addra(wr_addr), + .dia(i_tdata), + .doa(), + + .clkb(clk), + .enb((read_state==PRE_READ)|read), + .web(1'b0), + .addrb(rd_addr), + .dib({WIDTH{1'b1}}), + .dob(o_tdata)); + + always @(posedge clk) + if(reset) + begin + read_state <= EMPTY; + rd_addr <= 0; + empty_reg <= 1; + end + else + if(clear) + begin + read_state <= EMPTY; + rd_addr <= 0; + empty_reg <= 1; + end + else + case(read_state) + EMPTY : + if(write) + begin + //rd_addr <= wr_addr; + read_state <= PRE_READ; + end + PRE_READ : + begin + read_state <= READING; + empty_reg <= 0; + rd_addr <= rd_addr + 1; + end + + READING : + if(read) + if(rd_addr == wr_addr) + begin + empty_reg <= 1; + if(write) + read_state <= PRE_READ; + else + read_state <= EMPTY; + end + else + rd_addr <= rd_addr + 1; + endcase // case(read_state) + + wire [SIZE-1:0] dont_write_past_me = rd_addr - 2; + wire becoming_full = wr_addr == dont_write_past_me; + + always @(posedge clk) + if(reset) + full_reg <= 0; + else if(clear) + full_reg <= 0; + else if(read & ~write) + full_reg <= 0; + //else if(write & ~read & (wr_addr == (rd_addr-3))) + else if(write & ~read & becoming_full) + full_reg <= 1; + + //assign empty = (read_state != READING); + assign empty = empty_reg; + + // assign full = ((rd_addr - 1) == wr_addr); + assign full = full_reg; + + ////////////////////////////////////////////// + // space and occupied are for diagnostics only + // not guaranteed exact + + localparam NUMLINES = (1<9) + axi_fifo #(.WIDTH(WIDTH), .SIZE(SIZE)) fifo_1clk + (.clk(o_aclk), .reset(reset), .clear(1'b0), + .i_tdata(tdata_int), .i_tvalid(tvalid_int), .i_tready(tready_int), + .o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready), + .space(), .occupied()); + else + begin + assign o_tdata = tdata_int; + assign o_tvalid = tvalid_int; + assign tready_int = o_tready; + end + endgenerate + +endmodule // axi_fifo_2clk diff --git a/fpga/usrp3/lib/fifo/axi_fifo_32_64_tb.v b/fpga/usrp3/lib/fifo/axi_fifo_32_64_tb.v new file mode 100644 index 000000000..9b104f1d9 --- /dev/null +++ b/fpga/usrp3/lib/fifo/axi_fifo_32_64_tb.v @@ -0,0 +1,114 @@ +`timescale 1ns/1ps + +module axi_fifo_32_64_tb(); + + reg clk = 0; + reg reset = 1; + + always #10 clk = ~clk; + + initial $dumpfile("axi_fifo_32_64_tb.vcd"); + initial $dumpvars(0,axi_fifo_32_64_tb); + + task send_packet; + input [63:0] data_start; + input [2:0] user; + input [31:0] len; + + begin + @(posedge clk); + {i_tuser, i_tlast, i_tdata} <= { 3'd0, 1'b0, data_start }; + repeat(len-1) + begin + i_tvalid <= 1; + @(posedge clk); + i_tdata <= i_tdata + 64'h0000_0002_0000_0002; + end + i_tuser <= user; + i_tlast <= 1; + @(posedge clk); + i_tvalid <= 1'b0; + @(posedge clk); + end + endtask // send_packet + + initial + begin + #1000 reset = 0; + #200000; + $finish; + end + + reg [63:0] i_tdata; + reg [2:0] i_tuser; + reg i_tlast; + reg i_tvalid; + wire i_tready; + + wire [63:0] i_tdata_int; + wire [2:0] i_tuser_int; + wire i_tlast_int, i_tvalid_int, i_tready_int; + + wire [63:0] o_tdata; + wire [31:0] o_tdata_int, o_tdata_int2; + wire [2:0] o_tuser; + wire [1:0] o_tuser_int, o_tuser_int2; + wire o_tlast, o_tlast_int, o_tvalid, o_tvalid_int, o_tready, o_tready_int; + wire o_tlast_int2, o_tvalid_int2, o_tready_int2; + + localparam RPT_COUNT = 16; + + initial + begin + i_tvalid <= 0; + + while(reset) + @(posedge clk); + @(posedge clk); + + send_packet(64'hA0000000_A0000001, 3'd7, 4); + @(posedge clk); + end // initial begin + + axi_fifo #(.WIDTH(68), .SIZE(10)) fifo + (.clk(clk), .reset(reset), .clear(1'b0), + .i_tdata({i_tlast,i_tuser,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready), + .o_tdata({i_tlast_int,i_tuser_int,i_tdata_int}), .o_tvalid(i_tvalid_int), .o_tready(i_tready_int)); + + axi_fifo64_to_fifo32 dut + (.clk(clk), .reset(reset), .clear(1'b0), + .i_tdata(i_tdata_int), .i_tuser(i_tuser_int), .i_tlast(i_tlast_int), .i_tvalid(i_tvalid_int), .i_tready(i_tready_int), + .o_tdata(o_tdata_int), .o_tuser(o_tuser_int), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int)); + + /* + axi_fifo #(.WIDTH(35), .SIZE(10)) fifo_middle + (.clk(clk), .reset(reset), .clear(1'b0), + .i_tdata({o_tlast_int,o_tuser_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int), + .o_tdata({o_tlast_int2,o_tuser_int2,o_tdata_int2}), .o_tvalid(o_tvalid_int2), .o_tready(o_tready_int2)); +*/ + assign o_tdata_int2 = o_tdata_int; + assign o_tlast_int2 = o_tlast_int; + assign o_tuser_int2 = o_tuser_int; + assign o_tvalid_int2 = o_tvalid_int; + assign o_tready_int = o_tready_int2; + + axi_fifo32_to_fifo64 dut2 + (.clk(clk), .reset(reset), .clear(1'b0), + .i_tdata(o_tdata_int2), .i_tuser(o_tuser_int2), .i_tlast(o_tlast_int2), .i_tvalid(o_tvalid_int2), .i_tready(o_tready_int2), + .o_tdata(o_tdata), .o_tuser(o_tuser), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)); + + assign o_tready = 1'b1; + + always @(posedge clk) + if(i_tvalid & i_tready) + $display("IN: TUSER %x\tTLAST %x\tTDATA %x", i_tuser, i_tlast, i_tdata); + + always @(posedge clk) + if(o_tvalid_int & o_tready_int) + $display("\t\t\t\t\t\tMIDDLE: TUSER %x\tTLAST %x\tTDATA %x", o_tuser_int, o_tlast_int, o_tdata_int); + + always @(posedge clk) + if(o_tvalid & o_tready) + $display("\t\t\t\t\t\t\t\t\t\t\tOUT: TUSER %x\tTLAST %x\tTDATA %x", o_tuser, o_tlast, o_tdata); + +endmodule // axi_fifo_32_64_tb diff --git a/fpga/usrp3/lib/fifo/axi_fifo_short.v b/fpga/usrp3/lib/fifo/axi_fifo_short.v new file mode 100644 index 000000000..e13993199 --- /dev/null +++ b/fpga/usrp3/lib/fifo/axi_fifo_short.v @@ -0,0 +1,110 @@ +// +// Copyright 2012 Ettus Research LLC +// + + +// +// 32 word FIFO with AXI4-STREAM interface. +// +// NOTE: This module uses the SRLC32E primitive explicitly and as such +// can only be used with Xilinx technology of the VIRTEX-6/SPARTAN-6/SIERIES-7 or newer. +// + +module axi_fifo_short + #(parameter WIDTH=32) + ( + input clk, + input reset, + input clear, + input [WIDTH-1:0] i_tdata, + input i_tvalid, + output i_tready, + output [WIDTH-1:0] o_tdata, + output o_tvalid, + input o_tready, + + output reg [5:0] space, + output reg [5:0] occupied + ); + + reg full, empty; + wire write = i_tvalid & i_tready; + wire read = o_tready & o_tvalid; + + assign i_tready = ~full; + assign o_tvalid = ~empty; + + reg [4:0] a; + genvar i; + + generate + for (i=0;i