From 0df4b801a34697f2058b4a7b95e08d2a0576c9db Mon Sep 17 00:00:00 2001
From: Ben Hilburn <ben.hilburn@ettus.com>
Date: Thu, 10 Oct 2013 10:17:27 -0700
Subject: Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt
 Ettus.

---
 fpga/usrp3/lib/dsp/srl.v | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 fpga/usrp3/lib/dsp/srl.v

(limited to 'fpga/usrp3/lib/dsp/srl.v')

diff --git a/fpga/usrp3/lib/dsp/srl.v b/fpga/usrp3/lib/dsp/srl.v
new file mode 100644
index 000000000..bbd8ac1c9
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/srl.v
@@ -0,0 +1,27 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+
+module srl
+  #(parameter WIDTH=18)
+    (input clk,
+     input rst,
+     input write,
+     input [WIDTH-1:0] in,
+     input [3:0] addr,
+     output [WIDTH-1:0] out);
+   
+   genvar 		i;
+   generate
+      for (i=0;i<WIDTH;i=i+1)
+	begin : gen_srl
+	   SRL16E
+	     srl16e(.Q(out[i]),
+		    .A0(addr[0]),.A1(addr[1]),.A2(addr[2]),.A3(addr[3]),
+		    .CE(write|rst),.CLK(clk),.D(in[i]));
+	end
+   endgenerate
+
+endmodule // srl
-- 
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