From 4b4365a517938b365af57674a3ab1462432c2c3a Mon Sep 17 00:00:00 2001
From: Ben Hilburn <ben.hilburn@ettus.com>
Date: Tue, 3 Dec 2013 10:35:35 -0800
Subject: b2xx: Updating FPGA source with recent bugfixes.
---
fpga/usrp3/lib/control/Makefile.srcs | 1 +
fpga/usrp3/lib/control/arb_qualify_master.v | 14 ++-
fpga/usrp3/lib/control/axi_crossbar.v | 14 ++-
fpga/usrp3/lib/control/axi_crossbar_tb.v | 14 ++-
fpga/usrp3/lib/control/axi_fifo_header.v | 14 ++-
fpga/usrp3/lib/control/axi_forwarding_cam.v | 14 ++-
fpga/usrp3/lib/control/axi_slave_mux.v | 14 ++-
fpga/usrp3/lib/control/binary_encoder.v | 42 +++++++++
fpga/usrp3/lib/control/cvita_uart.v | 14 ++-
fpga/usrp3/lib/control/gpio_atr.v | 14 ++-
fpga/usrp3/lib/control/por_gen.v | 14 ++-
fpga/usrp3/lib/control/ram_2port.v | 14 ++-
fpga/usrp3/lib/control/reset_sync.v | 14 ++-
fpga/usrp3/lib/control/serial_to_settings.v | 111 +++++++++++++++++++++++
fpga/usrp3/lib/control/serial_to_settings_tb.v | 54 +++++++++++
fpga/usrp3/lib/control/setting_reg.v | 14 ++-
fpga/usrp3/lib/control/settings_bus_crossclock.v | 14 ++-
fpga/usrp3/lib/control/simple_i2c_core.v | 14 ++-
fpga/usrp3/lib/control/simple_spi_core.v | 14 ++-
19 files changed, 403 insertions(+), 15 deletions(-)
create mode 100644 fpga/usrp3/lib/control/binary_encoder.v
create mode 100644 fpga/usrp3/lib/control/serial_to_settings.v
create mode 100644 fpga/usrp3/lib/control/serial_to_settings_tb.v
(limited to 'fpga/usrp3/lib/control')
diff --git a/fpga/usrp3/lib/control/Makefile.srcs b/fpga/usrp3/lib/control/Makefile.srcs
index e0ad8a942..9e44579ad 100644
--- a/fpga/usrp3/lib/control/Makefile.srcs
+++ b/fpga/usrp3/lib/control/Makefile.srcs
@@ -23,4 +23,5 @@ axi_forwarding_cam.v \
axi_test_vfifo.v \
dram_2port.v \
cvita_uart.v \
+serial_to_settings.v \
))
diff --git a/fpga/usrp3/lib/control/arb_qualify_master.v b/fpga/usrp3/lib/control/arb_qualify_master.v
index df17fac57..e9c67b7ac 100644
--- a/fpga/usrp3/lib/control/arb_qualify_master.v
+++ b/fpga/usrp3/lib/control/arb_qualify_master.v
@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
-
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
//
// This module forms the qualification engine for a single master as
diff --git a/fpga/usrp3/lib/control/axi_crossbar.v b/fpga/usrp3/lib/control/axi_crossbar.v
index a408f69f0..c64931b6e 100644
--- a/fpga/usrp3/lib/control/axi_crossbar.v
+++ b/fpga/usrp3/lib/control/axi_crossbar.v
@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
-
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
`define LOG2(N) (\
N < 2 ? 0 : \
diff --git a/fpga/usrp3/lib/control/axi_crossbar_tb.v b/fpga/usrp3/lib/control/axi_crossbar_tb.v
index 1994cb352..b14f859d4 100644
--- a/fpga/usrp3/lib/control/axi_crossbar_tb.v
+++ b/fpga/usrp3/lib/control/axi_crossbar_tb.v
@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
-
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
`timescale 1 ps / 1 ps
module axi_crossbar_tb;
diff --git a/fpga/usrp3/lib/control/axi_fifo_header.v b/fpga/usrp3/lib/control/axi_fifo_header.v
index ceac8e324..1a0d13cd0 100644
--- a/fpga/usrp3/lib/control/axi_fifo_header.v
+++ b/fpga/usrp3/lib/control/axi_fifo_header.v
@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
-
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
//
// This module is connected to the output port of an AXI4-STREAM FIFO that is used to move packetized data.
diff --git a/fpga/usrp3/lib/control/axi_forwarding_cam.v b/fpga/usrp3/lib/control/axi_forwarding_cam.v
index 2f28b5640..cb6e82684 100644
--- a/fpga/usrp3/lib/control/axi_forwarding_cam.v
+++ b/fpga/usrp3/lib/control/axi_forwarding_cam.v
@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
-
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
//
// This module implements a highly customized TCAM that enbales forwarding
diff --git a/fpga/usrp3/lib/control/axi_slave_mux.v b/fpga/usrp3/lib/control/axi_slave_mux.v
index 1a307aba5..3f2424584 100644
--- a/fpga/usrp3/lib/control/axi_slave_mux.v
+++ b/fpga/usrp3/lib/control/axi_slave_mux.v
@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
-
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
diff --git a/fpga/usrp3/lib/control/binary_encoder.v b/fpga/usrp3/lib/control/binary_encoder.v
new file mode 100644
index 000000000..e13a8174b
--- /dev/null
+++ b/fpga/usrp3/lib/control/binary_encoder.v
@@ -0,0 +1,42 @@
+
+`define LOG2(N) (\
+ N < 2 ? 0 : \
+ N < 4 ? 1 : \
+ N < 8 ? 2 : \
+ N < 16 ? 3 : \
+ N < 32 ? 4 : \
+ N < 64 ? 5 : \
+ N < 128 ? 6 : \
+ N < 256 ? 7 : \
+ N < 512 ? 8 : \
+ N < 1024 ? 9 : \
+ 10)
+
+ module binary_encoder
+ #(
+ parameter SIZE = 16
+ )
+ (
+ input [SIZE-1:0] in,
+ output [`LOG2(SIZE)-1:0] out
+ );
+
+ genvar m,n;
+
+ generate
+ // Loop enough times to represent the total number of input bits as an encoded value
+ for (m = 0; m <= `log2(SIZE-1); m = m + 1) begin: expand_or_tree
+ wire [SIZE-1:0] encoding;
+ // Build enable mask by iterating through every input bit.
+ for (n = 0; n < SIZE ; n = n + 1) begin: encode_this_bit
+ assign encoding[n] = n[m];
+ end
+ // OR tree for this output bit with appropraite bits enabled.
+ assign out[m] = |(encoding & in);
+ end
+ endgenerate
+endmodule // binary_encoder
+
+
+
+
\ No newline at end of file
diff --git a/fpga/usrp3/lib/control/cvita_uart.v b/fpga/usrp3/lib/control/cvita_uart.v
index cbb272fc2..e0d4697ce 100644
--- a/fpga/usrp3/lib/control/cvita_uart.v
+++ b/fpga/usrp3/lib/control/cvita_uart.v
@@ -2,7 +2,19 @@
//
// Copyright 2013 Ettus Research LLC
//
-
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
//create a compressed vita based uart data interface
diff --git a/fpga/usrp3/lib/control/gpio_atr.v b/fpga/usrp3/lib/control/gpio_atr.v
index 9c707e52a..16449a711 100644
--- a/fpga/usrp3/lib/control/gpio_atr.v
+++ b/fpga/usrp3/lib/control/gpio_atr.v
@@ -2,7 +2,19 @@
//
// Copyright 2011 Ettus Research LLC
//
-
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
module gpio_atr
diff --git a/fpga/usrp3/lib/control/por_gen.v b/fpga/usrp3/lib/control/por_gen.v
index 0e4fcd88a..89dc93d82 100644
--- a/fpga/usrp3/lib/control/por_gen.v
+++ b/fpga/usrp3/lib/control/por_gen.v
@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
-
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
module por_gen
diff --git a/fpga/usrp3/lib/control/ram_2port.v b/fpga/usrp3/lib/control/ram_2port.v
index 434af0ff3..ab93157a4 100644
--- a/fpga/usrp3/lib/control/ram_2port.v
+++ b/fpga/usrp3/lib/control/ram_2port.v
@@ -1,7 +1,19 @@
//
// Copyright 2011 Ettus Research LLC
//
-
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
diff --git a/fpga/usrp3/lib/control/reset_sync.v b/fpga/usrp3/lib/control/reset_sync.v
index da284e62e..3a58c0a5f 100644
--- a/fpga/usrp3/lib/control/reset_sync.v
+++ b/fpga/usrp3/lib/control/reset_sync.v
@@ -1,7 +1,19 @@
//
// Copyright 2011 Ettus Research LLC
//
-
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
diff --git a/fpga/usrp3/lib/control/serial_to_settings.v b/fpga/usrp3/lib/control/serial_to_settings.v
new file mode 100644
index 000000000..53e112a62
--- /dev/null
+++ b/fpga/usrp3/lib/control/serial_to_settings.v
@@ -0,0 +1,111 @@
+
+
+module serial_to_settings
+ (
+ input clk,
+ input reset,
+ // Serial signals (async)
+ input scl,
+ input sda,
+ // Settngs bus out
+ output reg set_stb,
+ output reg [7:0] set_addr,
+ output reg [31:0] set_data
+ );
+
+ reg [2:0] state;
+
+ localparam SEARCH = 3'h0;
+ localparam ADDRESS = 3'h1;
+ localparam DATA = 3'h2;
+ localparam STOP1 = 3'h3;
+ localparam STOP2 = 3'h4;
+
+ reg scl_pre_reg, scl_reg, scl_reg2;
+ reg sda_pre_reg, sda_reg, sda_reg2;
+ reg [4:0] counter;
+
+
+ always @(posedge clk) begin
+ scl_reg2 <= scl_reg;
+ scl_reg <= scl_pre_reg;
+ scl_pre_reg <= scl;
+ sda_reg2 <= sda_reg;
+ sda_reg <= sda_pre_reg;
+ sda_pre_reg <= sda;
+ end
+
+
+ always @(posedge clk)
+ if (reset) begin
+ state <= SEARCH;
+ counter <= 0;
+ set_addr <= 0;
+ set_data <= 0;
+ set_stb <= 0;
+ end else begin
+ case(state)
+ //
+ // Search for I2C like start indication: SDA goes low whilst clock is high.
+ //
+ SEARCH: begin
+ set_stb <= 0;
+ // Look for START.
+ if (scl_reg && scl_reg2 && !sda_reg && sda_reg2) begin
+ state <= ADDRESS;
+ counter <= 0;
+ end
+ end
+ //
+ // Count 8 Address bits.
+ // Master changes SDA on falling edge of SCL, we sample on the rising edge.
+ //
+ ADDRESS: begin
+ if (scl_reg && !scl_reg2) begin
+ set_addr[7:0] <= {set_addr[6:0],sda_reg};
+ if (counter == 7) begin
+ state <= DATA;
+ counter <= 0;
+ end else
+ counter <= counter + 1;
+ end
+ end
+ //
+ // Count 32 data bits.
+ // Master changes SDA on falling edge of SCL, we sample on the rising edge.
+ //
+ DATA: begin
+ if (scl_reg && !scl_reg2) begin
+ set_data[31:0] <= {set_data[30:0],sda_reg};
+ if (counter == 31) begin
+ state <= STOP1;
+ counter <= 0;
+ end else
+ counter <= counter + 1;
+ end
+ end
+ //
+ // Looks for rising SCL edge before STOP bit.
+ //
+ STOP1: begin
+ if (scl_reg && !scl_reg2) begin
+ state <= STOP2;
+ end
+ end
+ //
+ // Looks for STOP bit
+ //
+ STOP2: begin
+ if (scl_reg && scl_reg2 && sda_reg && !sda_reg2) begin
+ state <= SEARCH;
+ counter <= 0;
+ set_stb <= 1;
+ end
+ end
+
+ endcase // case(state)
+ end // else: !if(reset)
+
+
+
+endmodule // serial_to_settings
diff --git a/fpga/usrp3/lib/control/serial_to_settings_tb.v b/fpga/usrp3/lib/control/serial_to_settings_tb.v
new file mode 100644
index 000000000..8111c115e
--- /dev/null
+++ b/fpga/usrp3/lib/control/serial_to_settings_tb.v
@@ -0,0 +1,54 @@
+
+
+module serial_to_settings_tb();
+
+
+
+ reg clk;
+ reg reset;
+
+ wire scl;
+ wire sda;
+ wire set_stb;
+ wire [7:0] set_addr;
+ wire [31:0] set_data;
+
+ //
+ // These registers optionaly used
+ // to drive nets through procedural assignments in test bench.
+ // These drivers default to tri-stated.
+ //
+ reg scl_r;
+ reg sda_r;
+
+ assign scl = scl_r;
+ assign sda = sda_r;
+
+ initial
+ begin
+ scl_r <= 1'bz;
+ sda_r <= 1'bz;
+ end
+
+
+
+ serial_to_settings serial_to_settings_i
+ (
+ .clk(clk),
+ .reset(reset),
+ // Serial signals (async)
+ .scl(scl),
+ .sda(sda),
+ // Settngs bus out
+ .set_stb(set_stb),
+ .set_addr(set_addr),
+ .set_data(set_data)
+ );
+
+
+ //
+ // Bring in a simulation script here
+ //
+ `include "simulation_script.v"
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/control/setting_reg.v b/fpga/usrp3/lib/control/setting_reg.v
index 1664f54e2..e9c1c73ac 100644
--- a/fpga/usrp3/lib/control/setting_reg.v
+++ b/fpga/usrp3/lib/control/setting_reg.v
@@ -1,7 +1,19 @@
//
// Copyright 2011-2012 Ettus Research LLC
//
-
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
//----------------------------------------------------------------------
//-- A settings register is a peripheral for the settings register bus.
diff --git a/fpga/usrp3/lib/control/settings_bus_crossclock.v b/fpga/usrp3/lib/control/settings_bus_crossclock.v
index 2a6e7e7ef..de74f67ee 100644
--- a/fpga/usrp3/lib/control/settings_bus_crossclock.v
+++ b/fpga/usrp3/lib/control/settings_bus_crossclock.v
@@ -1,7 +1,19 @@
//
// Copyright 2011-2012 Ettus Research LLC
//
-
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
diff --git a/fpga/usrp3/lib/control/simple_i2c_core.v b/fpga/usrp3/lib/control/simple_i2c_core.v
index 47f1ac82a..9c61de8fb 100644
--- a/fpga/usrp3/lib/control/simple_i2c_core.v
+++ b/fpga/usrp3/lib/control/simple_i2c_core.v
@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
-
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
// Simple I2C core
diff --git a/fpga/usrp3/lib/control/simple_spi_core.v b/fpga/usrp3/lib/control/simple_spi_core.v
index a18e00709..b94515e40 100644
--- a/fpga/usrp3/lib/control/simple_spi_core.v
+++ b/fpga/usrp3/lib/control/simple_spi_core.v
@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
-
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
// Simple SPI core, the simplest, yet complete spi core I can think of
--
cgit v1.2.3