From 1e94f85b8bafc3f9acab7ef35d2675fa7e61f6f4 Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Fri, 19 Jun 2020 15:40:12 -0500 Subject: fpga: rfnoc: Add Signal Generator RFNoC block --- fpga/usrp3/lib/control/axi_setting_reg.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'fpga/usrp3/lib/control') diff --git a/fpga/usrp3/lib/control/axi_setting_reg.v b/fpga/usrp3/lib/control/axi_setting_reg.v index 9d419ec32..c231540aa 100644 --- a/fpga/usrp3/lib/control/axi_setting_reg.v +++ b/fpga/usrp3/lib/control/axi_setting_reg.v @@ -40,7 +40,7 @@ module axi_setting_reg #( reg init; reg [WIDTH-1:0] o_tdata_int; - reg o_tlast_int, o_tvalid_int; + reg o_tlast_int, o_tvalid_int = VALID_AT_RESET; wire o_tready_int; always @(posedge clk) begin -- cgit v1.2.3