From 0df4b801a34697f2058b4a7b95e08d2a0576c9db Mon Sep 17 00:00:00 2001
From: Ben Hilburn <ben.hilburn@ettus.com>
Date: Thu, 10 Oct 2013 10:17:27 -0700
Subject: Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt
 Ettus.

---
 fpga/usrp3/lib/control/ram_2port.v | 49 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 fpga/usrp3/lib/control/ram_2port.v

(limited to 'fpga/usrp3/lib/control/ram_2port.v')

diff --git a/fpga/usrp3/lib/control/ram_2port.v b/fpga/usrp3/lib/control/ram_2port.v
new file mode 100644
index 000000000..434af0ff3
--- /dev/null
+++ b/fpga/usrp3/lib/control/ram_2port.v
@@ -0,0 +1,49 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+
+
+module ram_2port
+  #(parameter DWIDTH=32,
+    parameter AWIDTH=9)
+    (input clka,
+     input ena,
+     input wea,
+     input [AWIDTH-1:0] addra,
+     input [DWIDTH-1:0] dia,
+     output reg [DWIDTH-1:0] doa,
+     
+     input clkb,
+     input enb,
+     input web,
+     input [AWIDTH-1:0] addrb,
+     input [DWIDTH-1:0] dib,
+     output reg [DWIDTH-1:0] dob);
+   
+   reg [DWIDTH-1:0] ram [(1<<AWIDTH)-1:0];
+   /*
+   integer 	    i;
+   initial
+     for(i=0;i<(1<<AWIDTH);i=i+1)
+       ram[i] <= {DWIDTH{1'b0}};
+       */
+   
+   always @(posedge clka) begin
+      if (ena)
+        begin
+           if (wea)
+             ram[addra] <= dia;
+           doa <= ram[addra];
+        end
+   end
+   always @(posedge clkb) begin
+      if (enb)
+        begin
+           if (web)
+             ram[addrb] <= dib;
+           dob <= ram[addrb];
+        end
+   end
+endmodule // ram_2port
-- 
cgit v1.2.3