From ff1546f8137f7f92bb250f685561b0c34cc0e053 Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Fri, 14 Feb 2014 12:05:07 -0800 Subject: Pushing the bulk of UHD-3.7.0 code. --- fpga/usrp3/lib/axi/axi_chdr_header_trigger.v | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 fpga/usrp3/lib/axi/axi_chdr_header_trigger.v (limited to 'fpga/usrp3/lib/axi/axi_chdr_header_trigger.v') diff --git a/fpga/usrp3/lib/axi/axi_chdr_header_trigger.v b/fpga/usrp3/lib/axi/axi_chdr_header_trigger.v new file mode 100644 index 000000000..e8dee3675 --- /dev/null +++ b/fpga/usrp3/lib/axi/axi_chdr_header_trigger.v @@ -0,0 +1,40 @@ + +// Copyright 2014 Ettus Research LLC + + +module axi_chdr_header_trigger + #( + parameter WIDTH=64, + parameter SID=0 + ) + (input clk, input reset, input clear, + input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, input i_tready, + output trigger + ); + + + reg state; + localparam IDLE = 0; + localparam RUN = 1; + + + always @(posedge clk) + if(reset | clear) + state <= IDLE; + else + case (state) + IDLE : + if(i_tvalid && i_tready) + state <= RUN; + + RUN : + if(i_tready && i_tvalid && i_tlast) + state <= IDLE; + + default : + state <= IDLE; + endcase // case (state) + + assign trigger = i_tvalid && i_tready && (state == IDLE) && (i_tdata[15:0] != SID); + +endmodule // axi_chdr_header_trigger -- cgit v1.2.3