From fd3e84941de463fa1a7ebab0a69515b4bf2614cd Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Tue, 7 Oct 2014 11:25:20 +0200 Subject: Removed copy of FPGA source files. --- fpga/usrp2/boot_cpld/.gitignore | 38 - fpga/usrp2/boot_cpld/_impact.cmd | 34 - fpga/usrp2/boot_cpld/boot_cpld.ipf | Bin 2967 -> 0 bytes fpga/usrp2/boot_cpld/boot_cpld.ise | Bin 227573 -> 0 bytes fpga/usrp2/boot_cpld/boot_cpld.lfp | 5 - fpga/usrp2/boot_cpld/boot_cpld.ucf | 34 - fpga/usrp2/boot_cpld/boot_cpld.v | 95 - fpga/usrp2/control_lib/.gitignore | 5 - fpga/usrp2/control_lib/CRC16_D16.v | 89 - fpga/usrp2/control_lib/Makefile.srcs | 61 - fpga/usrp2/control_lib/atr_controller.v | 77 - fpga/usrp2/control_lib/atr_controller16.v | 79 - fpga/usrp2/control_lib/bin2gray.v | 27 - fpga/usrp2/control_lib/bootram.v | 312 - fpga/usrp2/control_lib/bootrom.mem | 26 - fpga/usrp2/control_lib/clock_bootstrap_rom.v | 51 - fpga/usrp2/control_lib/clock_control.v | 132 - fpga/usrp2/control_lib/clock_control_tb.v | 52 - fpga/usrp2/control_lib/cmdfile | 18 - fpga/usrp2/control_lib/dbsm.v | 164 - fpga/usrp2/control_lib/dcache.v | 182 - fpga/usrp2/control_lib/decoder_3_8.v | 38 - fpga/usrp2/control_lib/double_buffer.v | 139 - fpga/usrp2/control_lib/double_buffer_tb.v | 312 - fpga/usrp2/control_lib/dpram32.v | 99 - fpga/usrp2/control_lib/fifo_to_wb.v | 183 - fpga/usrp2/control_lib/fifo_to_wb_tb.v | 136 - fpga/usrp2/control_lib/gpio_atr.v | 71 - fpga/usrp2/control_lib/gray2bin.v | 30 - fpga/usrp2/control_lib/gray_send.v | 46 - fpga/usrp2/control_lib/icache.v | 152 - fpga/usrp2/control_lib/longfifo.v | 167 - fpga/usrp2/control_lib/medfifo.v | 66 - fpga/usrp2/control_lib/mux4.v | 33 - fpga/usrp2/control_lib/mux8.v | 38 - fpga/usrp2/control_lib/mux_32_4.v | 30 - fpga/usrp2/control_lib/nsgpio.v | 93 - fpga/usrp2/control_lib/nsgpio16LE.v | 123 - fpga/usrp2/control_lib/oneshot_2clk.v | 52 - fpga/usrp2/control_lib/pic.v | 183 - fpga/usrp2/control_lib/priority_enc.v | 61 - fpga/usrp2/control_lib/quad_uart.v | 88 - fpga/usrp2/control_lib/ram_2port.v | 59 - fpga/usrp2/control_lib/ram_2port_mixed_width.v | 137 - fpga/usrp2/control_lib/ram_harv_cache.v | 92 - fpga/usrp2/control_lib/ram_harvard.v | 84 - fpga/usrp2/control_lib/ram_harvard2.v | 94 - fpga/usrp2/control_lib/ram_loader.v | 278 - fpga/usrp2/control_lib/ram_wb_harvard.v | 103 - fpga/usrp2/control_lib/reset_sync.v | 33 - fpga/usrp2/control_lib/s3a_icap_wb.v | 76 - fpga/usrp2/control_lib/sd_spi.v | 87 - fpga/usrp2/control_lib/sd_spi_tb.v | 57 - fpga/usrp2/control_lib/sd_spi_wb.v | 93 - fpga/usrp2/control_lib/setting_reg.v | 42 - fpga/usrp2/control_lib/settings_bus.v | 58 - fpga/usrp2/control_lib/settings_bus_16LE.v | 71 - fpga/usrp2/control_lib/settings_bus_crossclock.v | 38 - fpga/usrp2/control_lib/settings_fifo_ctrl.v | 395 - fpga/usrp2/control_lib/shortfifo.v | 104 - fpga/usrp2/control_lib/simple_i2c_core.v | 116 - fpga/usrp2/control_lib/simple_spi_core.v | 214 - fpga/usrp2/control_lib/simple_uart.v | 79 - fpga/usrp2/control_lib/simple_uart_rx.v | 81 - fpga/usrp2/control_lib/simple_uart_tx.v | 77 - fpga/usrp2/control_lib/spi.v | 101 - fpga/usrp2/control_lib/srl.v | 38 - fpga/usrp2/control_lib/ss_rcvr.v | 98 - fpga/usrp2/control_lib/system_control.v | 64 - fpga/usrp2/control_lib/system_control_tb.v | 74 - fpga/usrp2/control_lib/traffic_cop.v | 42 - fpga/usrp2/control_lib/user_settings.v | 63 - fpga/usrp2/control_lib/v5icap_wb.v | 71 - fpga/usrp2/control_lib/wb_1master.v | 464 - fpga/usrp2/control_lib/wb_bridge_16_32.v | 53 - fpga/usrp2/control_lib/wb_bus_writer.v | 74 - fpga/usrp2/control_lib/wb_output_pins32.v | 66 - fpga/usrp2/control_lib/wb_ram_block.v | 53 - fpga/usrp2/control_lib/wb_ram_dist.v | 50 - fpga/usrp2/control_lib/wb_readback_mux.v | 77 - fpga/usrp2/control_lib/wb_readback_mux_16LE.v | 90 - fpga/usrp2/control_lib/wb_regfile_2clock.v | 124 - fpga/usrp2/control_lib/wb_semaphore.v | 59 - fpga/usrp2/control_lib/wb_sim.v | 96 - fpga/usrp2/coregen/.gitignore | 3 - fpga/usrp2/coregen/Makefile.srcs | 27 - fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs | 18 - fpga/usrp2/coregen/coregen.cgp | 22 - fpga/usrp2/coregen/coregen_s6.cgc | 2352 - fpga/usrp2/coregen/coregen_s6.cgp | 22 - .../usrp2/coregen/fifo_generator_release_notes.txt | 160 - fpga/usrp2/coregen/fifo_generator_ug175.pdf | Bin 2895895 -> 0 bytes fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.asy | 49 - fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.gise | 31 - fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.ngc | 3 - fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.v | 173 - fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.veo | 53 - fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xco | 84 - fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xise | 392 - fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_flist.txt | 13 - fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_readme.txt | 51 - fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_xmdf.tcl | 72 - fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.asy | 49 - fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.gise | 31 - fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.ngc | 3 - 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45cf9a86b..000000000 --- a/fpga/usrp2/boot_cpld/.gitignore +++ /dev/null @@ -1,38 +0,0 @@ -/*_xdb -/*.restore -/*.xrpt -/*.zip -/xst -/_ngo -/_xmsgs -/*.log -/*.stx -/*.tspec -/*.xml -/*.gyd -/*.ngr -/*.tim -/*.err -/*.lso -/*.bld -/*.cmd_log -/*.ise_ISE_Backup -/*.ipf_ISE_Backup -/*.mfd -/*.vm6 -/*.syr -/*.xst -/*.csv -/*.html -/*.jed -/*.pad -/*.ng* -/*.pnx -/*.rpt -/*.prj -/*_html -/*.cel -/_pace.ucf -/*.lock -/*.tfi -/templates diff --git a/fpga/usrp2/boot_cpld/_impact.cmd b/fpga/usrp2/boot_cpld/_impact.cmd deleted file mode 100755 index 4af86cb02..000000000 --- a/fpga/usrp2/boot_cpld/_impact.cmd +++ /dev/null @@ -1,34 +0,0 @@ -loadProjectFile -file "C:\cygwin\home\matt\usrp2\fpga\boot_cpld/boot_cpld.ipf" -setMode -ss -setMode -sm -setMode -hw140 -setMode -spi -setMode -acecf -setMode -acempm -setMode -pff -setMode -bs -setMode -bs -setMode -bs -setMode -bs -setCable -port auto -Identify -identifyMPM -assignFile -p 1 -file "C:/cygwin/home/matt/usrp2/fpga/boot_cpld/boot_cpld.jed" -Program -p 1 -e -v -defaultVersion 0 -Program -p 1 -e -v -defaultVersion 0 -Program -p 1 -e -v -defaultVersion 0 -Program -p 1 -e -v -defaultVersion 0 -Program -p 1 -e -v -defaultVersion 0 -Program -p 1 -e -v -defaultVersion 0 -Identify -identifyMPM -Identify -identifyMPM -Identify -identifyMPM -Identify -identifyMPM -Identify -identifyMPM -setMode -bs -deleteDevice -position 1 diff --git a/fpga/usrp2/boot_cpld/boot_cpld.ipf b/fpga/usrp2/boot_cpld/boot_cpld.ipf deleted file mode 100755 index 8acb6821e..000000000 Binary files a/fpga/usrp2/boot_cpld/boot_cpld.ipf and /dev/null differ diff --git a/fpga/usrp2/boot_cpld/boot_cpld.ise b/fpga/usrp2/boot_cpld/boot_cpld.ise deleted file mode 100755 index 7252d3768..000000000 Binary files a/fpga/usrp2/boot_cpld/boot_cpld.ise and /dev/null differ diff --git a/fpga/usrp2/boot_cpld/boot_cpld.lfp b/fpga/usrp2/boot_cpld/boot_cpld.lfp deleted file mode 100755 index 0f0c8f2e2..000000000 --- a/fpga/usrp2/boot_cpld/boot_cpld.lfp +++ /dev/null @@ -1,5 +0,0 @@ -# begin LFP file C:\cygwin\home\matt\u2f\boot_cpld\boot_cpld.lfp -designfile boot_cpld.v -parttype xc9572xl-vq44-10 -bus_delimiter 0; -set_busdelim_onsave 1; diff --git a/fpga/usrp2/boot_cpld/boot_cpld.ucf b/fpga/usrp2/boot_cpld/boot_cpld.ucf deleted file mode 100755 index 789bb1d96..000000000 --- a/fpga/usrp2/boot_cpld/boot_cpld.ucf +++ /dev/null @@ -1,34 +0,0 @@ -NET "CLK_25MHZ" LOC = "P5" ; -NET "CLK_25MHZ_EN" LOC = "P6" ; -NET "LED<0>" LOC = "P12" ; -NET "LED<1>" LOC = "P8" ; -NET "LED<2>" LOC = "P7" ; -NET "DEBUG<0>" LOC = "P1" ; -NET "DEBUG<1>" LOC = "P2" ; -NET "DEBUG<2>" LOC = "P3" ; -NET "DEBUG<3>" LOC = "P29" ; -NET "DEBUG<4>" LOC = "P30" ; -NET "DEBUG<5>" LOC = "P31" ; -NET "DEBUG<6>" LOC = "P32" ; -NET "DEBUG<7>" LOC = "P33" ; -NET "DEBUG<8>" LOC = "P34" ; -NET "POR" LOC = "P42" ; -NET "SD_nCS" LOC = "P20" ; -NET "SD_Din" LOC = "P21" ; -NET "SD_CLK" LOC = "P22" ; -NET "SD_Dout" LOC = "P23" ; -NET "SD_DAT1" LOC = "P27" ; -NET "SD_DAT2" LOC = "P28" ; -NET "SD_prot" LOC = "P19" ; -NET "SD_det" LOC = "P36" ; -NET "CFG_INIT_B" LOC = "P38" ; -NET "CFG_Din" LOC = "P37" ; -NET "CFG_CCLK" LOC = "P41" ; -NET "CFG_DONE" LOC = "P40" ; -NET "CFG_PROG_B" LOC = "P39" ; -NET "CPLD_CLK" LOC = "P13" ; -NET "START" LOC = "P14" ; -NET "MODE" LOC = "P18" ; -NET "DONE" LOC = "P16" ; -NET "detached" LOC = "P43" ; -NET "CPLD_misc" LOC = "P44" ; diff --git a/fpga/usrp2/boot_cpld/boot_cpld.v b/fpga/usrp2/boot_cpld/boot_cpld.v deleted file mode 100755 index 2ffc6daed..000000000 --- a/fpga/usrp2/boot_cpld/boot_cpld.v +++ /dev/null @@ -1,95 +0,0 @@ -`timescale 1ns / 1ps -// //////////////////////////////////////////////////////////////////////////////// -// Boot CPLD design, only for u2_rev2 -// //////////////////////////////////////////////////////////////////////////////// - -module boot_cpld - (input CLK_25MHZ, - output CLK_25MHZ_EN, - output [2:0] LED, - output [8:0] DEBUG, - input POR, - - // To SD Card - output SD_nCS, - output SD_Din, - output SD_CLK, - input SD_Dout, - input SD_DAT1, // Unused - input SD_DAT2, // Unused - input SD_prot, // Write Protect - input SD_det, // Card Detect - - // To FPGA Config Interface - input CFG_INIT_B, - output CFG_Din, // Also used in Data interface - output CFG_CCLK, - input CFG_DONE, - output CFG_PROG_B, - - // To FPGA data interface - output CPLD_CLK, - input START, - input MODE, - input DONE, - output detached, - input CPLD_misc // Unused for now - ); - - assign CLK_25MHZ_EN = 1'b1; - - assign LED[0] = ~CFG_DONE; - assign LED[1] = CFG_INIT_B; - assign LED[2] = ~CFG_PROG_B; - - wire en_outs; - wire [3:0] set_sel = 4'd0; - - assign CPLD_CLK = CFG_CCLK; - assign DEBUG[8:0] = { CLK_25MHZ, SD_nCS, SD_CLK, SD_Din, SD_Dout, - START, MODE, DONE, CPLD_misc}; - - // Handle cutover to FPGA control of SD - wire fpga_takeover = ~CPLD_misc; - wire SD_CLK_int, SD_nCS_int, SD_Din_int, CFG_Din_int; - - assign SD_CLK = fpga_takeover ? START : SD_CLK_int; - assign SD_nCS = fpga_takeover ? MODE : SD_nCS_int; - assign SD_Din = fpga_takeover ? DONE : SD_Din_int; - assign CFG_Din = fpga_takeover ? SD_Dout : CFG_Din_int; - - spi_boot #(.width_set_sel_g(4), // How many sets (16) - .width_bit_cnt_g(6), // Block length (12 is faster, 6 is minimum) - .width_img_cnt_g(2), // How many images per set - .num_bits_per_img_g(20), // Image size, 20 = 1MB - .sd_init_g(1), // SD-specific initialization - .mmc_compat_clk_div_g(0),// No MMC support - .width_mmc_clk_div_g(0), // No MMC support - .reset_level_g(0)) // Active low reset - - spi_boot(.clk_i(CLK_25MHZ), - .reset_i(POR), - - // To SD Card - .spi_clk_o(SD_CLK_int), - .spi_cs_n_o(SD_nCS_int), - .spi_data_in_i(SD_Dout), - .spi_data_out_o(SD_Din_int), - .spi_en_outs_o(en_outs), - - // Data Port - .start_i(START), - .mode_i(MODE), // 0->conf mode, 1->data mode - .detached_o(detached), - .dat_done_i(DONE), - .set_sel_i(set_sel), - - // To FPGA - .config_n_o(CFG_PROG_B), - .cfg_init_n_i(CFG_INIT_B), - .cfg_done_i(CFG_DONE), - .cfg_clk_o(CFG_CCLK), - .cfg_dat_o(CFG_Din_int) - ); - -endmodule // boot_cpld diff --git a/fpga/usrp2/control_lib/.gitignore b/fpga/usrp2/control_lib/.gitignore deleted file mode 100644 index 025385cff..000000000 --- a/fpga/usrp2/control_lib/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -/a.out -/*.vcd -/*.lxt -/*.sav -/*.log diff --git a/fpga/usrp2/control_lib/CRC16_D16.v b/fpga/usrp2/control_lib/CRC16_D16.v deleted file mode 100644 index 7e2816af1..000000000 --- a/fpga/usrp2/control_lib/CRC16_D16.v +++ /dev/null @@ -1,89 +0,0 @@ -/////////////////////////////////////////////////////////////////////// -// File: CRC16_D16.v -// Date: Sun Jun 17 06:42:55 2007 -// -// Copyright (C) 1999-2003 Easics NV. -// This source file may be used and distributed without restriction -// provided that this copyright statement is not removed from the file -// and that any derivative work contains the original copyright notice -// and the associated disclaimer. -// -// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS -// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED -// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. -// -// Purpose: Verilog module containing a synthesizable CRC function -// * polynomial: (0 5 12 16) -// * data width: 16 -// -// Info: tools@easics.be -// http://www.easics.com -/////////////////////////////////////////////////////////////////////// - - -module CRC16_D16 - (input [15:0] Data, - input [15:0] CRC, - output [15:0] NewCRC); - - assign NewCRC = nextCRC16_D16(Data,CRC); - - // polynomial: (0 5 12 16) - // data width: 16 - // convention: the first serial data bit is D[15] - function [15:0] nextCRC16_D16; - - input [15:0] Data; - input [15:0] CRC; - - reg [15:0] D; - reg [15:0] C; - reg [15:0] NewCRC; - - begin - - D = Data; - C = CRC; - - NewCRC[0] = D[12] ^ D[11] ^ D[8] ^ D[4] ^ D[0] ^ C[0] ^ C[4] ^ - C[8] ^ C[11] ^ C[12]; - NewCRC[1] = D[13] ^ D[12] ^ D[9] ^ D[5] ^ D[1] ^ C[1] ^ C[5] ^ - C[9] ^ C[12] ^ C[13]; - NewCRC[2] = D[14] ^ D[13] ^ D[10] ^ D[6] ^ D[2] ^ C[2] ^ C[6] ^ - C[10] ^ C[13] ^ C[14]; - NewCRC[3] = D[15] ^ D[14] ^ D[11] ^ D[7] ^ D[3] ^ C[3] ^ C[7] ^ - C[11] ^ C[14] ^ C[15]; - NewCRC[4] = D[15] ^ D[12] ^ D[8] ^ D[4] ^ C[4] ^ C[8] ^ C[12] ^ - C[15]; - NewCRC[5] = D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[8] ^ D[5] ^ D[4] ^ - D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ - C[13]; - NewCRC[6] = D[14] ^ D[13] ^ D[12] ^ D[10] ^ D[9] ^ D[6] ^ D[5] ^ - D[1] ^ C[1] ^ C[5] ^ C[6] ^ C[9] ^ C[10] ^ C[12] ^ - C[13] ^ C[14]; - NewCRC[7] = D[15] ^ D[14] ^ D[13] ^ D[11] ^ D[10] ^ D[7] ^ D[6] ^ - D[2] ^ C[2] ^ C[6] ^ C[7] ^ C[10] ^ C[11] ^ C[13] ^ - C[14] ^ C[15]; - NewCRC[8] = D[15] ^ D[14] ^ D[12] ^ D[11] ^ D[8] ^ D[7] ^ D[3] ^ - C[3] ^ C[7] ^ C[8] ^ C[11] ^ C[12] ^ C[14] ^ C[15]; - NewCRC[9] = D[15] ^ D[13] ^ D[12] ^ D[9] ^ D[8] ^ D[4] ^ C[4] ^ - C[8] ^ C[9] ^ C[12] ^ C[13] ^ C[15]; - NewCRC[10] = D[14] ^ D[13] ^ D[10] ^ D[9] ^ D[5] ^ C[5] ^ C[9] ^ - C[10] ^ C[13] ^ C[14]; - NewCRC[11] = D[15] ^ D[14] ^ D[11] ^ D[10] ^ D[6] ^ C[6] ^ C[10] ^ - C[11] ^ C[14] ^ C[15]; - NewCRC[12] = D[15] ^ D[8] ^ D[7] ^ D[4] ^ D[0] ^ C[0] ^ C[4] ^ C[7] ^ - C[8] ^ C[15]; - NewCRC[13] = D[9] ^ D[8] ^ D[5] ^ D[1] ^ C[1] ^ C[5] ^ C[8] ^ C[9]; - NewCRC[14] = D[10] ^ D[9] ^ D[6] ^ D[2] ^ C[2] ^ C[6] ^ C[9] ^ C[10]; - NewCRC[15] = D[11] ^ D[10] ^ D[7] ^ D[3] ^ C[3] ^ C[7] ^ C[10] ^ - C[11]; - - nextCRC16_D16 = NewCRC; - - end - - endfunction - -endmodule - diff --git a/fpga/usrp2/control_lib/Makefile.srcs b/fpga/usrp2/control_lib/Makefile.srcs deleted file mode 100644 index 42862a50f..000000000 --- a/fpga/usrp2/control_lib/Makefile.srcs +++ /dev/null @@ -1,61 +0,0 @@ -# -# Copyright 2010-2012 Ettus Research LLC -# - -################################################## -# Control Lib Sources -################################################## -CONTROL_LIB_SRCS = $(abspath $(addprefix $(BASE_DIR)/../control_lib/, \ -CRC16_D16.v \ -atr_controller.v \ -bin2gray.v \ -dcache.v \ -decoder_3_8.v \ -dbsm.v \ -dpram32.v \ -double_buffer.v \ -gray2bin.v \ -gray_send.v \ -icache.v \ -mux4.v \ -mux8.v \ -nsgpio.v \ -ram_2port.v \ -ram_harv_cache.v \ -ram_harvard.v \ -ram_harvard2.v \ -ram_loader.v \ -setting_reg.v \ -settings_bus.v \ -settings_bus_crossclock.v \ -srl.v \ -system_control.v \ -wb_1master.v \ -wb_readback_mux.v \ -wb_readback_mux_16LE.v \ -quad_uart.v \ -simple_uart.v \ -simple_uart_tx.v \ -simple_uart_rx.v \ -oneshot_2clk.v \ -sd_spi.v \ -sd_spi_wb.v \ -wb_bridge_16_32.v \ -reset_sync.v \ -priority_enc.v \ -pic.v \ -longfifo.v \ -shortfifo.v \ -medfifo.v \ -s3a_icap_wb.v \ -bootram.v \ -nsgpio16LE.v \ -settings_bus_16LE.v \ -atr_controller16.v \ -fifo_to_wb.v \ -gpio_atr.v \ -user_settings.v \ -settings_fifo_ctrl.v \ -simple_spi_core.v \ -simple_i2c_core.v \ -)) diff --git a/fpga/usrp2/control_lib/atr_controller.v b/fpga/usrp2/control_lib/atr_controller.v deleted file mode 100644 index ee8b260c5..000000000 --- a/fpga/usrp2/control_lib/atr_controller.v +++ /dev/null @@ -1,77 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Automatic transmit/receive switching of control pins to daughterboards -// Store everything in registers for now, but could use a RAM for more -// complex state machines in the future - -module atr_controller - (input clk_i, input rst_i, - input [5:0] adr_i, input [3:0] sel_i, input [31:0] dat_i, output reg [31:0] dat_o, - input we_i, input stb_i, input cyc_i, output reg ack_o, - input run_rx, input run_tx, - output [31:0] ctrl_lines); - - reg [3:0] state; - reg [31:0] atr_ram [0:15]; // DP distributed RAM - - // WB Interface - always @(posedge clk_i) - if(we_i & stb_i & cyc_i) - begin - if(sel_i[3]) - atr_ram[adr_i[5:2]][31:24] <= dat_i[31:24]; - if(sel_i[2]) - atr_ram[adr_i[5:2]][23:16] <= dat_i[23:16]; - if(sel_i[1]) - atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8]; - if(sel_i[0]) - atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0]; - end // if (we_i & stb_i & cyc_i) - - // Removing readback allows ram to be synthesized as LUTs instead of regs - //always @(posedge clk_i) - // dat_o <= atr_ram[adr_i[5:2]]; - always - dat_o <= 32'd0; - - always @(posedge clk_i) - ack_o <= stb_i & cyc_i & ~ack_o; - - // Control side of DP RAM - assign ctrl_lines = atr_ram[state]; - - // Put a more complex state machine with time delays and multiple states here - // if daughterboard requires more complex sequencing - localparam ATR_IDLE = 4'd0; - localparam ATR_TX = 4'd1; - localparam ATR_RX = 4'd2; - localparam ATR_FULL_DUPLEX = 4'd3; - - always @(posedge clk_i) - if(rst_i) - state <= ATR_IDLE; - else - case ({run_rx,run_tx}) - 2'b00 : state <= ATR_IDLE; - 2'b01 : state <= ATR_TX; - 2'b10 : state <= ATR_RX; - 2'b11 : state <= ATR_FULL_DUPLEX; - endcase // case({run_rx,run_tx}) - -endmodule // atr_controller diff --git a/fpga/usrp2/control_lib/atr_controller16.v b/fpga/usrp2/control_lib/atr_controller16.v deleted file mode 100644 index 578da4a5c..000000000 --- a/fpga/usrp2/control_lib/atr_controller16.v +++ /dev/null @@ -1,79 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Automatic transmit/receive switching of control pins to daughterboards -// Store everything in registers for now, but could use a RAM for more -// complex state machines in the future - -module atr_controller16 - (input clk_i, input rst_i, - input [5:0] adr_i, input [1:0] sel_i, input [15:0] dat_i, output [15:0] dat_o, - input we_i, input stb_i, input cyc_i, output reg ack_o, - input run_rx, input run_tx, - output [31:0] ctrl_lines); - - reg [3:0] state; - reg [31:0] atr_ram [0:15]; // DP distributed RAM - - wire [3:0] sel_int = { (sel_i[1] & adr_i[1]), (sel_i[0] & adr_i[1]), - (sel_i[1] & ~adr_i[1]), (sel_i[0] & ~adr_i[1]) }; - - // WB Interface - always @(posedge clk_i) - if(we_i & stb_i & cyc_i) - begin - if(sel_int[3]) - atr_ram[adr_i[5:2]][31:24] <= dat_i[15:8]; - if(sel_int[2]) - atr_ram[adr_i[5:2]][23:16] <= dat_i[7:0]; - if(sel_int[1]) - atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8]; - if(sel_int[0]) - atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0]; - end // if (we_i & stb_i & cyc_i) - - // Removing readback allows ram to be synthesized as LUTs instead of regs - //always @(posedge clk_i) - // dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0]; - assign dat_o = 16'd0; - - always @(posedge clk_i) - ack_o <= stb_i & cyc_i & ~ack_o; - - // Control side of DP RAM - assign ctrl_lines = atr_ram[state]; - - // Put a more complex state machine with time delays and multiple states here - // if daughterboard requires more complex sequencing - localparam ATR_IDLE = 4'd0; - localparam ATR_TX = 4'd1; - localparam ATR_RX = 4'd2; - localparam ATR_FULL_DUPLEX = 4'd3; - - always @(posedge clk_i) - if(rst_i) - state <= ATR_IDLE; - else - case ({run_rx,run_tx}) - 2'b00 : state <= ATR_IDLE; - 2'b01 : state <= ATR_TX; - 2'b10 : state <= ATR_RX; - 2'b11 : state <= ATR_FULL_DUPLEX; - endcase // case({run_rx,run_tx}) - -endmodule // atr_controller16 diff --git a/fpga/usrp2/control_lib/bin2gray.v b/fpga/usrp2/control_lib/bin2gray.v deleted file mode 100644 index 8336a5afc..000000000 --- a/fpga/usrp2/control_lib/bin2gray.v +++ /dev/null @@ -1,27 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module bin2gray - #(parameter WIDTH=8) - (input [WIDTH-1:0] bin, - output [WIDTH-1:0] gray); - - assign gray = (bin >> 1) ^ bin; - -endmodule // bin2gray diff --git a/fpga/usrp2/control_lib/bootram.v b/fpga/usrp2/control_lib/bootram.v deleted file mode 100644 index 7821fbc4c..000000000 --- a/fpga/usrp2/control_lib/bootram.v +++ /dev/null @@ -1,312 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Boot RAM for S3A, 8KB, dual port - -// RAMB16BWE_S36_S36: 512 x 32 + 4 Parity bits byte-wide write Dual-Port RAM -// Spartan-3A Xilinx HDL Libraries Guide, version 10.1.1 - -module bootram - (input clk, input reset, - input [13:0] if_adr, - output [31:0] if_data, - - input [13:0] dwb_adr_i, - input [31:0] dwb_dat_i, - output [31:0] dwb_dat_o, - input dwb_we_i, - output reg dwb_ack_o, - input dwb_stb_i, - input [3:0] dwb_sel_i); - - wire [31:0] DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7; - wire [31:0] DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7; - wire ENB0, ENB1, ENB2, ENB3, ENB4, ENB5, ENB6, ENB7; - wire [3:0] WEB; - - reg [2:0] delayed_if_bank; - always @(posedge clk) - delayed_if_bank <= if_adr[13:11]; - - assign if_data = delayed_if_bank[2] ? - (delayed_if_bank[1] ? (delayed_if_bank[0] ? DOA7 : DOA6) : (delayed_if_bank[0] ? DOA5 : DOA4)) - : (delayed_if_bank[1] ? (delayed_if_bank[0] ? DOA3 : DOA2) : (delayed_if_bank[0] ? DOA1 : DOA0)); - - - assign dwb_dat_o = dwb_adr_i[13] ? - (dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB7 : DOB6) : (dwb_adr_i[11] ? DOB5 : DOB4)) - : (dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB3 : DOB2) : (dwb_adr_i[11] ? DOB1 : DOB0)); - - always @(posedge clk) - if(reset) - dwb_ack_o <= 0; - else - dwb_ack_o <= dwb_stb_i & ~dwb_ack_o; - - assign ENB0 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b000); - assign ENB1 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b001); - assign ENB2 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b010); - assign ENB3 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b011); - assign ENB4 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b100); - assign ENB5 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b101); - assign ENB6 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b110); - assign ENB7 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b111); - - assign WEB = {4{dwb_we_i}} & dwb_sel_i; - - RAMB16BWE_S36_S36 - #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup - .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup - .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" - .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion - .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion - .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE - .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE - RAM0 - (.DOA(DOA0), // Port A 32-bit Data Output - .DOPA(), // Port A 4-bit Parity Output - .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input - .CLKA(clk), // Port A 1-bit Clock - .DIA(32'hffffffff), // Port A 32-bit Data Input - .DIPA(4'hf), // Port A 4-bit parity Input - .ENA(1'b1), // Port A 1-bit RAM Enable Input - .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input - .WEA(1'b0), // Port A 4-bit Write Enable Input - - .DOB(DOB0), // Port B 32-bit Data Output - .DOPB(), // Port B 4-bit Parity Output - .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input - .CLKB(clk), // Port B 1-bit Clock - .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'hf), // Port-B 4-bit parity Input - .ENB(ENB0), // Port B 1-bit RAM Enable Input - .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input - .WEB(WEB) // Port B 4-bit Write Enable Input - ); // End of RAMB16BWE_S36_S36_inst instantiation - - RAMB16BWE_S36_S36 - #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup - .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup - .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" - .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion - .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion - .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE - .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE - RAM1 - (.DOA(DOA1), // Port A 32-bit Data Output - .DOPA(), // Port A 4-bit Parity Output - .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input - .CLKA(clk), // Port A 1-bit Clock - .DIA(32'hffffffff), // Port A 32-bit Data Input - .DIPA(4'hf), // Port A 4-bit parity Input - .ENA(1'b1), // Port A 1-bit RAM Enable Input - .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input - .WEA(1'b0), // Port A 4-bit Write Enable Input - - .DOB(DOB1), // Port B 32-bit Data Output - .DOPB(), // Port B 4-bit Parity Output - .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input - .CLKB(clk), // Port B 1-bit Clock - .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'hf), // Port-B 4-bit parity Input - .ENB(ENB1), // Port B 1-bit RAM Enable Input - .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input - .WEB(WEB) // Port B 4-bit Write Enable Input - ); // End of RAMB16BWE_S36_S36_inst instantiation - - RAMB16BWE_S36_S36 - #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup - .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup - .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" - .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion - .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion - .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE - .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE - RAM2 - (.DOA(DOA2), // Port A 32-bit Data Output - .DOPA(), // Port A 4-bit Parity Output - .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input - .CLKA(clk), // Port A 1-bit Clock - .DIA(32'hffffffff), // Port A 32-bit Data Input - .DIPA(4'hf), // Port A 4-bit parity Input - .ENA(1'b1), // Port A 1-bit RAM Enable Input - .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input - .WEA(1'b0), // Port A 4-bit Write Enable Input - - .DOB(DOB2), // Port B 32-bit Data Output - .DOPB(), // Port B 4-bit Parity Output - .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input - .CLKB(clk), // Port B 1-bit Clock - .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'hf), // Port-B 4-bit parity Input - .ENB(ENB2), // Port B 1-bit RAM Enable Input - .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input - .WEB(WEB) // Port B 4-bit Write Enable Input - ); // End of RAMB16BWE_S36_S36_inst instantiation - - RAMB16BWE_S36_S36 - #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup - .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup - .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" - .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion - .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion - .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE - .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE - RAM3 - (.DOA(DOA3), // Port A 32-bit Data Output - .DOPA(), // Port A 4-bit Parity Output - .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input - .CLKA(clk), // Port A 1-bit Clock - .DIA(32'hffffffff), // Port A 32-bit Data Input - .DIPA(4'hf), // Port A 4-bit parity Input - .ENA(1'b1), // Port A 1-bit RAM Enable Input - .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input - .WEA(1'b0), // Port A 4-bit Write Enable Input - - .DOB(DOB3), // Port B 32-bit Data Output - .DOPB(), // Port B 4-bit Parity Output - .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input - .CLKB(clk), // Port B 1-bit Clock - .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'hf), // Port-B 4-bit parity Input - .ENB(ENB3), // Port B 1-bit RAM Enable Input - .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input - .WEB(WEB) // Port B 4-bit Write Enable Input - ); // End of RAMB16BWE_S36_S36_inst instantiation - - RAMB16BWE_S36_S36 - #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup - .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup - .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" - .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion - .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion - .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE - .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE - RAM4 - (.DOA(DOA4), // Port A 32-bit Data Output - .DOPA(), // Port A 4-bit Parity Output - .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input - .CLKA(clk), // Port A 1-bit Clock - .DIA(32'hffffffff), // Port A 32-bit Data Input - .DIPA(4'hf), // Port A 4-bit parity Input - .ENA(1'b1), // Port A 1-bit RAM Enable Input - .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input - .WEA(1'b0), // Port A 4-bit Write Enable Input - - .DOB(DOB4), // Port B 32-bit Data Output - .DOPB(), // Port B 4-bit Parity Output - .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input - .CLKB(clk), // Port B 1-bit Clock - .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'hf), // Port-B 4-bit parity Input - .ENB(ENB4), // Port B 1-bit RAM Enable Input - .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input - .WEB(WEB) // Port B 4-bit Write Enable Input - ); // End of RAMB16BWE_S36_S36_inst instantiation - - RAMB16BWE_S36_S36 - #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup - .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup - .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" - .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion - .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion - .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE - .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE - RAM5 - (.DOA(DOA5), // Port A 32-bit Data Output - .DOPA(), // Port A 4-bit Parity Output - .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input - .CLKA(clk), // Port A 1-bit Clock - .DIA(32'hffffffff), // Port A 32-bit Data Input - .DIPA(4'hf), // Port A 4-bit parity Input - .ENA(1'b1), // Port A 1-bit RAM Enable Input - .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input - .WEA(1'b0), // Port A 4-bit Write Enable Input - - .DOB(DOB5), // Port B 32-bit Data Output - .DOPB(), // Port B 4-bit Parity Output - .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input - .CLKB(clk), // Port B 1-bit Clock - .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'hf), // Port-B 4-bit parity Input - .ENB(ENB5), // Port B 1-bit RAM Enable Input - .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input - .WEB(WEB) // Port B 4-bit Write Enable Input - ); // End of RAMB16BWE_S36_S36_inst instantiation - - RAMB16BWE_S36_S36 - #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup - .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup - .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" - .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion - .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion - .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE - .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE - RAM6 - (.DOA(DOA6), // Port A 32-bit Data Output - .DOPA(), // Port A 4-bit Parity Output - .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input - .CLKA(clk), // Port A 1-bit Clock - .DIA(32'hffffffff), // Port A 32-bit Data Input - .DIPA(4'hf), // Port A 4-bit parity Input - .ENA(1'b1), // Port A 1-bit RAM Enable Input - .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input - .WEA(1'b0), // Port A 4-bit Write Enable Input - - .DOB(DOB6), // Port B 32-bit Data Output - .DOPB(), // Port B 4-bit Parity Output - .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input - .CLKB(clk), // Port B 1-bit Clock - .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'hf), // Port-B 4-bit parity Input - .ENB(ENB6), // Port B 1-bit RAM Enable Input - .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input - .WEB(WEB) // Port B 4-bit Write Enable Input - ); // End of RAMB16BWE_S36_S36_inst instantiation - - RAMB16BWE_S36_S36 - #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup - .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup - .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" - .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion - .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion - .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE - .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE - RAM7 - (.DOA(DOA7), // Port A 32-bit Data Output - .DOPA(), // Port A 4-bit Parity Output - .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input - .CLKA(clk), // Port A 1-bit Clock - .DIA(32'hffffffff), // Port A 32-bit Data Input - .DIPA(4'hf), // Port A 4-bit parity Input - .ENA(1'b1), // Port A 1-bit RAM Enable Input - .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input - .WEA(1'b0), // Port A 4-bit Write Enable Input - - .DOB(DOB7), // Port B 32-bit Data Output - .DOPB(), // Port B 4-bit Parity Output - .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input - .CLKB(clk), // Port B 1-bit Clock - .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'hf), // Port-B 4-bit parity Input - .ENB(ENB7), // Port B 1-bit RAM Enable Input - .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input - .WEB(WEB) // Port B 4-bit Write Enable Input - ); // End of RAMB16BWE_S36_S36_inst instantiation - -endmodule // bootram diff --git a/fpga/usrp2/control_lib/bootrom.mem b/fpga/usrp2/control_lib/bootrom.mem deleted file mode 100644 index d688b4342..000000000 --- a/fpga/usrp2/control_lib/bootrom.mem +++ /dev/null @@ -1,26 +0,0 @@ -00000C000F03 -101400000000 - // SPI: Set Divider to div by 2 -// Both clk sel choose ext ref (0), both are enabled (1), turn off SERDES, ADCs, turn on leds -1018_0000_0001 // SPI: Choose AD9510 -1010_0000_3418 // SPI: Auto-slave select, interrupt when done, TX_NEG, 24-bit word -1000_0000_0010 // SPI: AD9510 A:0 D:10 Set up AD9510 SPI -1010_0000_3518 // SPI: SEND IT Auto-slave select, interrupt when done, TX_NEG, 24-bit word -ffff_ffff_ffff // terminate -#// First 16 bits are address, last 32 are data -#// First 4 bits of address select which slave -// 6'd01 : addr_data = {13'h45,8'h00}; // CLK2 drives distribution, everything on -// 6'd02 : addr_data = {13'h3D,8'h80}; // Turn on output 1, normal levels -// 6'd03 : addr_data = {13'h4B,8'h80}; // Bypass divider 1 (div by 1) -// 6'd04 : addr_data = {13'h08,8'h47}; // POS PFD, Dig LK Det, Charge Pump normal -// 6'd05 : addr_data = {13'h09,8'h70}; // Max Charge Pump current -// 6'd06 : addr_data = {13'h0A,8'h04}; // Normal operation, Prescalar Div by 2, PLL On -// 6'd07 : addr_data = {13'h0B,8'h00}; // RDIV MSB (6 bits) -// 6'd08 : addr_data = {13'h0C,8'h01}; // RDIV LSB (8 bits), Div by 1 -// 6'd09 : addr_data = {13'h0D,8'h00}; // Everything normal, Dig Lock Det -// 6'd10 : addr_data = {13'h07,8'h00}; // Disable LOR detect - LOR causes failure... -// 6'd11 : addr_data = {13'h04,8'h00}; // A Counter = Don't Care -// 6'd12 : addr_data = {13'h05,8'h00}; // B Counter MSB = 0 -// 6'd13 : addr_data = {13'h06,8'h05}; // B Counter LSB = 5 - // default : addr_data = {13'h5A,8'h01}; // Register Update -// @ 55 // Jump to new address 8'h55 diff --git a/fpga/usrp2/control_lib/clock_bootstrap_rom.v b/fpga/usrp2/control_lib/clock_bootstrap_rom.v deleted file mode 100644 index 542f49380..000000000 --- a/fpga/usrp2/control_lib/clock_bootstrap_rom.v +++ /dev/null @@ -1,51 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module clock_bootstrap_rom(input [15:0] addr, output [47:0] data); - - reg [47:0] rom [0:15]; - - //initial - // $readmemh("bootrom.mem", rom); - - assign data = rom[addr]; - - initial - begin - // First 16 bits are address, last 32 are data - // First 4 bits of address select which slave - rom[0] = 48'h0000_0C00_0F03; // Both clk sel choose ext ref (0), both are enabled (1), turn off SERDES, ADCs, turn on leds - rom[1] = 48'h1014_0000_0000; // SPI: Set Divider to div by 2 - rom[2] = 48'h1018_0000_0001; // SPI: Choose AD9510 - rom[3] = 48'h1010_0000_3418; // SPI: Auto-slave select, interrupt when done, TX_NEG, 24-bit word - rom[4] = 48'h1000_0000_0010; // SPI: AD9510 A:0 D:10 Set up AD9510 SPI - rom[5] = 48'h1010_0000_3518; // SPI: SEND IT Auto-slave select, interrupt when done, TX_NEG, 24-bit word - rom[6] = 48'hffff_ffff_ffff; // terminate - rom[7] = 48'hffff_ffff_ffff; // terminate - rom[8] = 48'hffff_ffff_ffff; // terminate - rom[9] = 48'hffff_ffff_ffff; // terminate - rom[10] = 48'hffff_ffff_ffff; // terminate - rom[11] = 48'hffff_ffff_ffff; // terminate - rom[12] = 48'hffff_ffff_ffff; // terminate - rom[13] = 48'hffff_ffff_ffff; // terminate - rom[14] = 48'hffff_ffff_ffff; // terminate - rom[15] = 48'hffff_ffff_ffff; // terminate - end // initial begin - -endmodule // clock_bootstrap_rom diff --git a/fpga/usrp2/control_lib/clock_control.v b/fpga/usrp2/control_lib/clock_control.v deleted file mode 100644 index 000eaf1fb..000000000 --- a/fpga/usrp2/control_lib/clock_control.v +++ /dev/null @@ -1,132 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -// AD9510 Register Map (from datasheet Rev. A) - -/* INSTRUCTION word format (16 bits) - * 15 Read = 1, Write = 0 - * 14:13 W1/W0, Number of bytes 00 - 1, 01 - 2, 10 - 3, 11 - stream - * 12:0 Address - */ - -/* ADDR Contents Value (hex) - * 00 Serial Config Port 10 (def) -- MSB first, SDI/SDO separate - * 04 A Counter - * 05-06 B Counter - * 07-0A PLL Control - * 0B-0C R Divider - * 0D PLL Control - * 34-3A Fine Delay - * 3C-3F LVPECL Outs - * 40-43 LVDS/CMOS Outs - * 45 Clock select, power down - * 48-57 Dividers - * 58 Func and Sync - * 5A Update regs - */ - - -module clock_control - (input reset, - input aux_clk, // 25MHz, for before fpga clock is active - input clk_fpga, // real 100 MHz FPGA clock - output [1:0] clk_en, // controls source of reference clock - output [1:0] clk_sel, // controls source of reference clock - input clk_func, // FIXME needs to be some kind of out SYNC or reset to 9510 - input clk_status, // Monitor PLL or SYNC status - - output sen, // Enable for the AD9510 - output sclk, // FIXME these need to be shared - input sdi, - output sdo - ); - - wire read = 1'b0; // Always write for now - wire [1:0] w = 2'b00; // Always send 1 byte at a time - - assign clk_sel = 2'b00; // Both outputs from External Ref (SMA) - assign clk_en = 2'b11; // Both outputs enabled - - reg [20:0] addr_data; - - reg [5:0] entry; - reg start; - reg [7:0] counter; - reg [23:0] command; - - always @* - case(entry) - 6'd00 : addr_data = {13'h00,8'h10}; // Serial setup - 6'd01 : addr_data = {13'h45,8'h00}; // CLK2 drives distribution, everything on - 6'd02 : addr_data = {13'h3D,8'h80}; // Turn on output 1, normal levels - 6'd03 : addr_data = {13'h4B,8'h80}; // Bypass divider 1 (div by 1) - 6'd04 : addr_data = {13'h08,8'h47}; // POS PFD, Dig LK Det, Charge Pump normal - 6'd05 : addr_data = {13'h09,8'h70}; // Max Charge Pump current - 6'd06 : addr_data = {13'h0A,8'h04}; // Normal operation, Prescalar Div by 2, PLL On - 6'd07 : addr_data = {13'h0B,8'h00}; // RDIV MSB (6 bits) - 6'd08 : addr_data = {13'h0C,8'h01}; // RDIV LSB (8 bits), Div by 1 - 6'd09 : addr_data = {13'h0D,8'h00}; // Everything normal, Dig Lock Det - 6'd10 : addr_data = {13'h07,8'h00}; // Disable LOR detect - LOR causes failure... - 6'd11 : addr_data = {13'h04,8'h00}; // A Counter = Don't Care - 6'd12 : addr_data = {13'h05,8'h00}; // B Counter MSB = 0 - 6'd13 : addr_data = {13'h06,8'h05}; // B Counter LSB = 5 - default : addr_data = {13'h5A,8'h01}; // Register Update - endcase // case(entry) - - wire [5:0] lastentry = 6'd15; - wire done = (counter == 8'd49); - - always @(posedge aux_clk) - if(reset) - begin - entry <= #1 6'd0; - start <= #1 1'b1; - end - else if(start) - start <= #1 1'b0; - else if(done && (entry. -// - - - -module clock_control_tb(); - - clock_control clock_control - (.reset(reset), - .aux_clk(aux_clk), - .clk_fpga(clk_fpga), - .clk_en(clk_en), - .clk_sel(clk_sel), - .clk_func(clk_func), - .clk_status(clk_status), - - .sen(sen), - .sclk(sclk), - .sdi(sdi), - .sdo(sdo) - ); - - reg reset, aux_clk; - - wire [1:0] clk_sel, clk_en; - - initial reset = 1'b1; - initial #1000 reset = 1'b0; - - initial aux_clk = 1'b0; - always #10 aux_clk = ~aux_clk; - - initial $dumpfile("clock_control_tb.vcd"); - initial $dumpvars(0,clock_control_tb); - - initial #10000 $finish; - -endmodule // clock_control_tb diff --git a/fpga/usrp2/control_lib/cmdfile b/fpga/usrp2/control_lib/cmdfile deleted file mode 100644 index cb3756cfc..000000000 --- a/fpga/usrp2/control_lib/cmdfile +++ /dev/null @@ -1,18 +0,0 @@ -# My stuff --y . --y ../u2_basic --y ../control_lib --y ../sdr_lib - -# Models --y ../models - -# Open Cores --y ../opencores/spi/rtl/verilog -+incdir+../opencores/spi/rtl/verilog --y ../opencores/wb_conbus/rtl/verilog -+incdir+../opencores/wb_conbus/rtl/verilog --y ../opencores/i2c/rtl/verilog -+incdir+../opencores/i2c/rtl/verilog --y ../opencores/aemb/rtl/verilog --y ../opencores/simple_gpio/rtl diff --git a/fpga/usrp2/control_lib/dbsm.v b/fpga/usrp2/control_lib/dbsm.v deleted file mode 100644 index fea51096f..000000000 --- a/fpga/usrp2/control_lib/dbsm.v +++ /dev/null @@ -1,164 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module dbsm - (input clk, - input reset, - input clear, - - output write_ok, - output write_ptr, - input write_done, - - output read_ok, - output read_ptr, - input read_done, - - output access_ok, - output access_ptr, - input access_done, - input access_skip_read - ); - - localparam PORT_WAIT_0 = 0; - localparam PORT_USE_0 = 1; - localparam PORT_WAIT_1 = 2; - localparam PORT_USE_1 = 3; - - reg [1:0] write_port_state, access_port_state, read_port_state; - - localparam BUFF_WRITABLE = 0; - localparam BUFF_ACCESSIBLE = 1; - localparam BUFF_READABLE = 2; - localparam BUFF_ERROR = 3; - - wire [1:0] buff_state[0:1]; - - always @(posedge clk) - if(reset | clear) - write_port_state <= PORT_WAIT_0; - else - case(write_port_state) - PORT_WAIT_0 : - if(buff_state[0]==BUFF_WRITABLE) - write_port_state <= PORT_USE_0; - PORT_USE_0 : - if(write_done) - write_port_state <= PORT_WAIT_1; - PORT_WAIT_1 : - if(buff_state[1]==BUFF_WRITABLE) - write_port_state <= PORT_USE_1; - PORT_USE_1 : - if(write_done) - write_port_state <= PORT_WAIT_0; - endcase // case (write_port_state) - - assign write_ok = (write_port_state == PORT_USE_0) | (write_port_state == PORT_USE_1); - assign write_ptr = (write_port_state == PORT_USE_1); - - always @(posedge clk) - if(reset | clear) - access_port_state <= PORT_WAIT_0; - else - case(access_port_state) - PORT_WAIT_0 : - if(buff_state[0]==BUFF_ACCESSIBLE) - access_port_state <= PORT_USE_0; - PORT_USE_0 : - if(access_done) - access_port_state <= PORT_WAIT_1; - PORT_WAIT_1 : - if(buff_state[1]==BUFF_ACCESSIBLE) - access_port_state <= PORT_USE_1; - PORT_USE_1 : - if(access_done) - access_port_state <= PORT_WAIT_0; - endcase // case (access_port_state) - - assign access_ok = (access_port_state == PORT_USE_0) | (access_port_state == PORT_USE_1); - assign access_ptr = (access_port_state == PORT_USE_1); - - always @(posedge clk) - if(reset | clear) - read_port_state <= PORT_WAIT_0; - else - case(read_port_state) - PORT_WAIT_0 : - if(buff_state[0]==BUFF_READABLE) - read_port_state <= PORT_USE_0; - PORT_USE_0 : - if(read_done) - read_port_state <= PORT_WAIT_1; - PORT_WAIT_1 : - if(buff_state[1]==BUFF_READABLE) - read_port_state <= PORT_USE_1; - PORT_USE_1 : - if(read_done) - read_port_state <= PORT_WAIT_0; - endcase // case (read_port_state) - - assign read_ok = (read_port_state == PORT_USE_0) | (read_port_state == PORT_USE_1); - assign read_ptr = (read_port_state == PORT_USE_1); - - buff_sm #(.PORT_USE_FLAG(PORT_USE_0)) buff0_sm - (.clk(clk), .reset(reset), .clear(clear), - .write_done(write_done), .access_done(access_done), .access_skip_read(access_skip_read), .read_done(read_done), - .write_port_state(write_port_state), .access_port_state(access_port_state), .read_port_state(read_port_state), - .buff_state(buff_state[0])); - - buff_sm #(.PORT_USE_FLAG(PORT_USE_1)) buff1_sm - (.clk(clk), .reset(reset), .clear(clear), - .write_done(write_done), .access_done(access_done), .access_skip_read(access_skip_read), .read_done(read_done), - .write_port_state(write_port_state), .access_port_state(access_port_state), .read_port_state(read_port_state), - .buff_state(buff_state[1])); - -endmodule // dbsm - -module buff_sm - #(parameter PORT_USE_FLAG=0) - (input clk, input reset, input clear, - input write_done, input access_done, input access_skip_read, input read_done, - input [1:0] write_port_state, input [1:0] access_port_state, input [1:0] read_port_state, - output reg [1:0] buff_state); - - localparam BUFF_WRITABLE = 0; - localparam BUFF_ACCESSIBLE = 1; - localparam BUFF_READABLE = 2; - localparam BUFF_ERROR = 3; - - always @(posedge clk) - if(reset | clear) - buff_state <= BUFF_WRITABLE; - else - case(buff_state) - BUFF_WRITABLE : - if(write_done & (write_port_state == PORT_USE_FLAG)) - buff_state <= BUFF_ACCESSIBLE; - BUFF_ACCESSIBLE : - if(access_done & (access_port_state == PORT_USE_FLAG)) - if(access_skip_read) - buff_state <= BUFF_WRITABLE; - else - buff_state <= BUFF_READABLE; - BUFF_READABLE : - if(read_done & (read_port_state == PORT_USE_FLAG)) - buff_state <= BUFF_WRITABLE; - BUFF_ERROR : - ; - endcase - -endmodule // buff_sm diff --git a/fpga/usrp2/control_lib/dcache.v b/fpga/usrp2/control_lib/dcache.v deleted file mode 100644 index 384c5a149..000000000 --- a/fpga/usrp2/control_lib/dcache.v +++ /dev/null @@ -1,182 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module dcache - #(parameter AWIDTH=14, - parameter CWIDTH=6) - (input wb_clk_i, - input wb_rst_i, - - input [AWIDTH-1:0] dwb_adr_i, - input dwb_stb_i, - input dwb_we_i, - input [3:0] dwb_sel_i, - input [31:0] dwb_dat_i, - output [31:0] dwb_dat_o, - output dwb_ack_o, - - input [31:0] dram_dat_i, - output [31:0] dram_dat_o, - output [AWIDTH-1:0] dram_adr_o, - output dram_we_o, - output dram_en_o, - output [3:0] dram_sel_o ); - - localparam TAGWIDTH = AWIDTH-CWIDTH-2; - reg stb_d1, ack_d1, miss_d1; - reg [AWIDTH-1:0] held_addr; - reg [31:0] ddata [0:(1<. -// - - -module decoder_3_8 - (input [2:0] sel, - output reg [7:0] res); - - always @(sel or res) - begin - case (sel) - 3'b000 : res = 8'b00000001; - 3'b001 : res = 8'b00000010; - 3'b010 : res = 8'b00000100; - 3'b011 : res = 8'b00001000; - 3'b100 : res = 8'b00010000; - 3'b101 : res = 8'b00100000; - 3'b110 : res = 8'b01000000; - default : res = 8'b10000000; - endcase // case(sel) - end // always @ (sel or res) - -endmodule // decoder_3_8 - diff --git a/fpga/usrp2/control_lib/double_buffer.v b/fpga/usrp2/control_lib/double_buffer.v deleted file mode 100644 index 8865bddee..000000000 --- a/fpga/usrp2/control_lib/double_buffer.v +++ /dev/null @@ -1,139 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module double_buffer - #(parameter BUF_SIZE = 9) - (input clk, input reset, input clear, - - // Random access interface to RAM - input access_we, - input access_stb, - output access_ok, - input access_done, - input access_skip_read, - input [BUF_SIZE-1:0] access_adr, - output [BUF_SIZE-1:0] access_len, - input [35:0] access_dat_i, - output [35:0] access_dat_o, - - // Write FIFO Interface - input [35:0] data_i, - input src_rdy_i, - output dst_rdy_o, - - // Read FIFO Interface - output [35:0] data_o, - output src_rdy_o, - input dst_rdy_i - ); - - wire [35:0] data_o_0, data_o_1; - - wire read, read_ok, read_ptr, read_done; - wire write, write_ok, write_ptr, write_done; - - wire [BUF_SIZE-1:0] rw0_adr, rw1_adr; - reg [BUF_SIZE-1:0] read_adr, write_adr; - reg [BUF_SIZE-1:0] len0, len1; - - assign data_o = read_ptr ? data_o_1 : data_o_0; - assign rw0_adr = (write_ok & ~write_ptr) ? write_adr : read_adr; - assign rw1_adr = (write_ok & write_ptr) ? write_adr : read_adr; - - wire [35:0] access_dat_o_0, access_dat_o_1; - wire access_ptr; - assign access_dat_o = access_ptr? access_dat_o_1 : access_dat_o_0; - - dbsm dbsm - (.clk(clk), .reset(reset), .clear(clear), - .write_ok(write_ok), .write_ptr(write_ptr), .write_done(write_done), - .access_ok(access_ok), .access_ptr(access_ptr), .access_done(access_done), .access_skip_read(access_skip_read), - .read_ok(read_ok), .read_ptr(read_ptr), .read_done(read_done)); - - // Port A for random access, Port B for FIFO read and write - ram_2port #(.DWIDTH(36),.AWIDTH(BUF_SIZE)) buffer0 - (.clka(clk),.ena(access_stb & access_ok & (access_ptr == 0)),.wea(access_we), - .addra(access_adr),.dia(access_dat_i),.doa(access_dat_o_0), - .clkb(clk),.enb((read & read_ok & ~read_ptr)|(write & write_ok & ~write_ptr) ),.web(write&write_ok&~write_ptr), - .addrb(rw0_adr),.dib(data_i),.dob(data_o_0)); - - ram_2port #(.DWIDTH(36),.AWIDTH(BUF_SIZE)) buffer1 - (.clka(clk),.ena(access_stb & access_ok & (access_ptr == 1)),.wea(access_we), - .addra(access_adr),.dia(access_dat_i),.doa(access_dat_o_1), - .clkb(clk),.enb((read & read_ok & read_ptr)|(write & write_ok & write_ptr) ),.web(write&write_ok&write_ptr), - .addrb(rw1_adr),.dib(data_i),.dob(data_o_1)); - - // Write into buffers - assign dst_rdy_o = write_ok; - assign write = src_rdy_i & write_ok; - assign write_done = write & data_i[33]; // done - always @(posedge clk) - if(reset | clear) - write_adr <= 0; - else - if(write_done) - begin - write_adr <= 0; - if(write_ptr) - len1 <= write_adr + 1; - else - len0 <= write_adr + 1; - end - else if(write) - write_adr <= write_adr + 1; - - assign access_len = access_ptr ? len1 : len0; - - reg [1:0] read_state; - localparam IDLE = 0; - localparam PRE_READ = 1; - localparam READING = 2; - - always @(posedge clk) - if(reset | clear) - begin - read_state <= IDLE; - read_adr <= 0; - end - else - case(read_state) - IDLE : - begin - read_adr <= 0; - if(read_ok) - read_state <= PRE_READ; - end - PRE_READ : - begin - read_state <= READING; - read_adr <= 1; - end - - READING : - if(dst_rdy_i) - begin - read_adr <= read_adr + 1; - if(data_o[33]) - read_state <= IDLE; - end - endcase // case (read_state) - - assign read = ~((read_state==READING)& ~dst_rdy_i); - assign read_done = data_o[33] & dst_rdy_i & src_rdy_o; - assign src_rdy_o = (read_state == READING); - -endmodule // double_buffer diff --git a/fpga/usrp2/control_lib/double_buffer_tb.v b/fpga/usrp2/control_lib/double_buffer_tb.v deleted file mode 100644 index 804e8804d..000000000 --- a/fpga/usrp2/control_lib/double_buffer_tb.v +++ /dev/null @@ -1,312 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module double_buffer_tb(); - - reg clk = 0; - reg rst = 1; - reg clear = 0; - initial #1000 rst = 0; - always #50 clk = ~clk; - - wire src_rdy_o; - reg src_rdy_i = 0; - wire dst_rdy_o; - - wire dst_rdy_i = 0; - wire [35:0] data_o; - reg [35:0] data_i; - - wire access_we, access_stb, access_done, access_ok, access_skip_read; - - wire [8:0] access_adr, access_len; - wire [35:0] dsp_to_buf, buf_to_dsp; - reg set_stb = 0; - - double_buffer db - (.clk(clk),.reset(rst),.clear(0), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(dsp_to_buf), .access_dat_o(buf_to_dsp), - - .data_i(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), - .data_o(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); - - dspengine_8to16 #(.HEADER_OFFSET(1)) dspengine_8to16 - (.clk(clk),.reset(rst),.clear(0), - .set_stb(set_stb), .set_addr(0), .set_data(1), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf)); - - always @(posedge clk) - if(src_rdy_o & dst_rdy_i) - begin - $display("SOF %d, EOF %d, OCC %x, DAT %x",data_o[32],data_o[33],data_o[35:34],data_o[31:0]); - if(data_o[33]) - $display(); - end - initial $dumpfile("double_buffer_tb.vcd"); - initial $dumpvars(0,double_buffer_tb); - - initial - begin - @(negedge rst); - @(posedge clk); - @(posedge clk); - @(posedge clk); -/* - // Passthrough - $display("Passthrough"); - src_rdy_i <= 1; - data_i <= { 2'b00,1'b0,1'b1,32'h01234567}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'hFFFFFFFF}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h04050607}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h08090a0b}; - @(posedge clk); - data_i <= { 2'b00,1'b1,1'b0,32'h0c0d0e0f}; - @(posedge clk); - src_rdy_i <= 0; - @(posedge clk); - - repeat (5) - @(posedge clk); -*/ - $display("Enabled"); - set_stb <= 1; - @(posedge clk); - set_stb <= 0; -/* - @(posedge clk); - $display("Non-IF Data Passthrough"); - src_rdy_i <= 1; - data_i <= { 2'b00,1'b0,1'b1,32'h89acdef0}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'hC0000000}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h14151617}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h18191a1b}; - @(posedge clk); - data_i <= { 2'b00,1'b1,1'b0,32'h1c1d1e1f}; - @(posedge clk); - src_rdy_i <= 0; - @(posedge clk); - - while(~dst_rdy_o) - @(posedge clk); - - $display("No StreamID, No Trailer, Even"); - src_rdy_i <= 1; - data_i <= { 2'b00,1'b0,1'b1,32'hAAAAAAAA}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h0000FFFF}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h01000200}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h03000400}; - src_rdy_i <= 0; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - src_rdy_i <= 1; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h05000600}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h07000800}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h09000a00}; - @(posedge clk); - data_i <= { 2'b00,1'b1,1'b0,32'h0b000c00}; - @(posedge clk); - src_rdy_i <= 0; - @(posedge clk); - - while(~dst_rdy_o) - @(posedge clk); - - $display("No StreamID, No Trailer, Odd"); - src_rdy_i <= 1; - data_i <= { 2'b00,1'b0,1'b1,32'hBBBBBBBB}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h0000FFFF}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h11001200}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h13001400}; - src_rdy_i <= 0; - @(posedge clk); - src_rdy_i <= 1; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h15001600}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h17001800}; - @(posedge clk); - data_i <= { 2'b00,1'b1,1'b0,32'h19001a00}; - @(posedge clk); - src_rdy_i <= 0; - @(posedge clk); - - while(~dst_rdy_o) - @(posedge clk); -*/ - /* - $display("No StreamID, Trailer, Even"); - src_rdy_i <= 1; - data_i <= { 2'b00,1'b0,1'b1,32'hCCCCCCCC}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h0400FFFF}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h21222324}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h25262728}; - src_rdy_i <= 0; - @(posedge clk); - src_rdy_i <= 1; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h292a2b2c}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h2d2e2f30}; - @(posedge clk); - data_i <= { 2'b00,1'b1,1'b0,32'hDEADBEEF}; - @(posedge clk); - src_rdy_i <= 0; - @(posedge clk); -*/ - while(~dst_rdy_o) - @(posedge clk); -/* - $display("No StreamID, Trailer, Odd"); - src_rdy_i <= 1; - data_i <= { 2'b00,1'b0,1'b1,32'hDDDDDDDD}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h0400FFFF}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h21222324}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h25262728}; - src_rdy_i <= 0; - @(posedge clk); - src_rdy_i <= 1; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h292a2b2c}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h2d2e2f30}; - @(posedge clk); - data_i <= { 2'b00,1'b1,1'b0,32'hDEBDBF0D}; - @(posedge clk); - src_rdy_i <= 0; - @(posedge clk); -*/ - while(~dst_rdy_o) - @(posedge clk); - -/* - $display("No StreamID, Trailer, Odd"); - src_rdy_i <= 1; - data_i <= { 2'b00,1'b0,1'b1,32'h0400FFFF}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h31003200}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h33003400}; - src_rdy_i <= 0; - @(posedge clk); - src_rdy_i <= 1; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h35003600}; - @(posedge clk); - data_i <= { 2'b00,1'b1,1'b0,32'h39003a00}; - @(posedge clk); - src_rdy_i <= 0; - @(posedge clk); - - while(~dst_rdy_o) - @(posedge clk); - - $display("StreamID, No Trailer, Even"); - src_rdy_i <= 1; - data_i <= { 2'b00,1'b0,1'b1,32'h1000FFFF}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h11001200}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h13001400}; - src_rdy_i <= 0; - @(posedge clk); - src_rdy_i <= 1; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h15001600}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h17001800}; - @(posedge clk); - data_i <= { 2'b00,1'b1,1'b0,32'h19001a00}; - @(posedge clk); - src_rdy_i <= 0; - @(posedge clk); - - while(~dst_rdy_o) - @(posedge clk); -*/ - $display("StreamID, Trailer, Odd"); - src_rdy_i <= 1; - data_i <= { 2'b00,1'b0,1'b1,32'hABCDEF98}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h1c034567}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'ha0a1a2a3}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'ha4a5a6a7}; -// src_rdy_i <= 0; -// @(posedge clk); -// src_rdy_i <= 1; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'ha8a9aaab}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'hacadaeaf}; - @(posedge clk); - data_i <= { 2'b00,1'b1,1'b0,32'hdeadbeef}; - @(posedge clk); - src_rdy_i <= 0; - @(posedge clk); - src_rdy_i <= 1; - data_i <= { 2'b00,1'b0,1'b1,32'hABCDEF98}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'h1c034567}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'ha0a1a2a3}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'ha4a5a6a7}; -// src_rdy_i <= 0; -// @(posedge clk); -// src_rdy_i <= 1; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'ha8a9aaab}; - @(posedge clk); - data_i <= { 2'b00,1'b0,1'b0,32'hacadaeaf}; - @(posedge clk); - data_i <= { 2'b00,1'b1,1'b0,32'hdeadbeef}; - @(posedge clk); - src_rdy_i <= 0; - @(posedge clk); - - end - - initial #28000 $finish; -endmodule // double_buffer_tb diff --git a/fpga/usrp2/control_lib/dpram32.v b/fpga/usrp2/control_lib/dpram32.v deleted file mode 100644 index 386435e70..000000000 --- a/fpga/usrp2/control_lib/dpram32.v +++ /dev/null @@ -1,99 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Dual ported RAM -// Addresses are byte-oriented, so botton 2 address bits are ignored. -// AWIDTH of 13 allows you to address 8K bytes. -// For Spartan 3, if the total RAM size is not a multiple of 8K then BRAM space is wasted -// RAM_SIZE parameter allows odd-sized RAMs, like 24K - -module dpram32 #(parameter AWIDTH=15, - parameter RAM_SIZE=16384) - (input clk, - - input [AWIDTH-1:0] adr1_i, - input [31:0] dat1_i, - output reg [31:0] dat1_o, - input we1_i, - input en1_i, - input [3:0] sel1_i, - - input [AWIDTH-1:0] adr2_i, - input [31:0] dat2_i, - output reg [31:0] dat2_o, - input we2_i, - input en2_i, - input [3:0] sel2_i ); - - reg [7:0] ram0 [0:(RAM_SIZE/4)-1]; - reg [7:0] ram1 [0:(RAM_SIZE/4)-1]; - reg [7:0] ram2 [0:(RAM_SIZE/4)-1]; - reg [7:0] ram3 [0:(RAM_SIZE/4)-1]; - - // This is how we used to size the RAM --> - // reg [7:0] ram3 [0:(1<<(AWIDTH-2))-1]; - - // Port 1 - always @(posedge clk) - if(en1_i) dat1_o[31:24] <= ram3[adr1_i[AWIDTH-1:2]]; - always @(posedge clk) - if(en1_i) dat1_o[23:16] <= ram2[adr1_i[AWIDTH-1:2]]; - always @(posedge clk) - if(en1_i) dat1_o[15:8] <= ram1[adr1_i[AWIDTH-1:2]]; - always @(posedge clk) - if(en1_i) dat1_o[7:0] <= ram0[adr1_i[AWIDTH-1:2]]; - - always @(posedge clk) - if(we1_i & en1_i & sel1_i[3]) - ram3[adr1_i[AWIDTH-1:2]] <= dat1_i[31:24]; - always @(posedge clk) - if(we1_i & en1_i & sel1_i[2]) - ram2[adr1_i[AWIDTH-1:2]] <= dat1_i[23:16]; - always @(posedge clk) - if(we1_i & en1_i & sel1_i[1]) - ram1[adr1_i[AWIDTH-1:2]] <= dat1_i[15:8]; - always @(posedge clk) - if(we1_i & en1_i & sel1_i[0]) - ram0[adr1_i[AWIDTH-1:2]] <= dat1_i[7:0]; - - // Port 2 - always @(posedge clk) - if(en2_i) dat2_o[31:24] <= ram3[adr2_i[AWIDTH-1:2]]; - always @(posedge clk) - if(en2_i) dat2_o[23:16] <= ram2[adr2_i[AWIDTH-1:2]]; - always @(posedge clk) - if(en2_i) dat2_o[15:8] <= ram1[adr2_i[AWIDTH-1:2]]; - always @(posedge clk) - if(en2_i) dat2_o[7:0] <= ram0[adr2_i[AWIDTH-1:2]]; - - always @(posedge clk) - if(we2_i & en2_i & sel2_i[3]) - ram3[adr2_i[AWIDTH-1:2]] <= dat2_i[31:24]; - always @(posedge clk) - if(we2_i & en2_i & sel2_i[2]) - ram2[adr2_i[AWIDTH-1:2]] <= dat2_i[23:16]; - always @(posedge clk) - if(we2_i & en2_i & sel2_i[1]) - ram1[adr2_i[AWIDTH-1:2]] <= dat2_i[15:8]; - always @(posedge clk) - if(we2_i & en2_i & sel2_i[0]) - ram0[adr2_i[AWIDTH-1:2]] <= dat2_i[7:0]; - -endmodule // dpram32 - - diff --git a/fpga/usrp2/control_lib/fifo_to_wb.v b/fpga/usrp2/control_lib/fifo_to_wb.v deleted file mode 100644 index 9b6b5e804..000000000 --- a/fpga/usrp2/control_lib/fifo_to_wb.v +++ /dev/null @@ -1,183 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module fifo_to_wb - #(parameter PKT_LEN = 16) - (input clk, input reset, input clear, - input [18:0] data_i, input src_rdy_i, output dst_rdy_o, - output [18:0] data_o, output src_rdy_o, input dst_rdy_i, - output reg [15:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, - output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, - input [7:0] triggers, - output [31:0] debug0, output [31:0] debug1); - - wire [18:0] ctrl_data; - reg [18:0] resp_data; - wire ctrl_src_rdy, ctrl_dst_rdy, resp_src_rdy, resp_dst_rdy; - - fifo_short #(.WIDTH(19)) ctrl_sfifo - (.clk(clk), .reset(reset), .clear(clear), - .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), - .dataout(ctrl_data), .src_rdy_o(ctrl_src_rdy), .dst_rdy_i(ctrl_dst_rdy)); - - fifo_short #(.WIDTH(19)) resp_sfifo - (.clk(clk), .reset(reset), .clear(clear), - .datain(resp_data), .src_rdy_i(resp_src_rdy), .dst_rdy_o(resp_dst_rdy), - .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); - - // Need a programmable state machine here. The program is the fifo contents. - // All words are 16 bits wide - // Word 0 Command { Read, Write, Triggers[5:0], Seqno [7:0] } - // Word 1 Length - // Word 2 Address LSW - // Word 3 Address MSW (should all be 0) - - localparam RESP_IDLE = 0; - localparam RESP_LEN = 1; - localparam RESP_ADDR_LSW = 2; - localparam RESP_ADDR_MSW = 3; - localparam RESP_WRITE = 4; - localparam RESP_DUMP = 5; - localparam RESP_WAIT_READ = 6; - localparam RESP_RCMD = 7; - localparam RESP_RLEN = 8; - localparam RESP_RADDR_LSW = 9; - localparam RESP_RADDR_MSW = 10; - localparam RESP_READ = 11; - - reg [3:0] resp_state; - reg rd, wr; - reg [15:0] base_addr; - reg [15:0] length; - reg [15:0] count; - reg [7:0] seqnum; - reg [5:0] which_trig; - - always @(posedge clk) - if(reset | clear) - resp_state <= RESP_IDLE; - else - case(resp_state) - RESP_IDLE : - if(ctrl_src_rdy) - begin - { rd, wr, which_trig[5:0], seqnum[7:0] } <= ctrl_data[15:0]; - if(ctrl_data[16]) // WAIT for start of packet, clean out otherwise - resp_state <= RESP_LEN; - end - RESP_LEN : - if(ctrl_src_rdy) - begin - length <= ctrl_data[15:0]; - count <= ctrl_data[15:0]; - resp_state <= RESP_ADDR_LSW; - end - RESP_ADDR_LSW : - if(ctrl_src_rdy) - begin - base_addr <= ctrl_data[15:0]; - wb_adr_o <= ctrl_data[15:0]; - resp_state <= RESP_ADDR_MSW; - end - RESP_ADDR_MSW : - if(ctrl_src_rdy) - if(wr) - resp_state <= RESP_WRITE; - else - resp_state <= RESP_DUMP; - RESP_WRITE : - if(ctrl_src_rdy & wb_ack_i) - if(count==1) - if(ctrl_data[17]) //eof - resp_state <= RESP_IDLE; - else // clean out padding - resp_state <= RESP_DUMP; - else - begin - wb_adr_o <= wb_adr_o + 2; - count <= count - 1; - end - RESP_DUMP : - if(ctrl_src_rdy & ctrl_data[17]) - if(rd) - resp_state <= RESP_WAIT_READ; - else - resp_state <= RESP_IDLE; - RESP_WAIT_READ : - begin - wb_adr_o <= base_addr; - count <= length; - if( &(triggers | ~which_trig) ) - resp_state <= RESP_RCMD; - end - RESP_RCMD : - if(resp_dst_rdy) - resp_state <= RESP_RLEN; - RESP_RLEN : - if(resp_dst_rdy) - resp_state <= RESP_RADDR_LSW; - RESP_RADDR_LSW : - if(resp_dst_rdy) - resp_state <= RESP_RADDR_MSW; - RESP_RADDR_MSW : - if(resp_dst_rdy) - resp_state <= RESP_READ; - RESP_READ : - if(resp_dst_rdy & wb_ack_i) - if(count==1) - resp_state <= RESP_IDLE; - else - begin - wb_adr_o <= wb_adr_o + 2; - count <= count - 1; - end - endcase // case (resp_state) - - always @* - case(resp_state) - RESP_RCMD : resp_data <= { 3'b001, 8'hAA, seqnum }; - RESP_RLEN : resp_data <= { 3'b000, length }; - RESP_RADDR_LSW : resp_data <= { 3'b000, base_addr }; - RESP_RADDR_MSW : resp_data <= { 3'b000, 16'd0 }; - default : resp_data <= { 1'b0, (count==1), 1'b0, wb_dat_miso }; - endcase // case (resp_state) - - assign ctrl_dst_rdy = (resp_state == RESP_IDLE) | - (resp_state == RESP_LEN) | - (resp_state == RESP_ADDR_LSW) | - (resp_state == RESP_ADDR_MSW) | - ((resp_state == RESP_WRITE) & wb_ack_i) | - (resp_state == RESP_DUMP); - - assign resp_src_rdy = (resp_state == RESP_RCMD) | - (resp_state == RESP_RLEN) | - (resp_state == RESP_RADDR_LSW) | - (resp_state == RESP_RADDR_MSW) | - ((resp_state == RESP_READ) & wb_ack_i); - - assign wb_dat_mosi = ctrl_data[15:0]; - assign wb_we_o = (resp_state == RESP_WRITE); - assign wb_cyc_o = wb_stb_o; - assign wb_sel_o = 2'b11; - assign wb_stb_o = (ctrl_src_rdy & (resp_state == RESP_WRITE)) | (resp_dst_rdy & (resp_state == RESP_READ)); - - - assign debug0 = { 14'd0, ctrl_data[17:0] }; - assign debug1 = { ctrl_src_rdy, ctrl_dst_rdy, resp_src_rdy, resp_dst_rdy, 2'b00, ctrl_data[17:16] }; - -endmodule // fifo_to_wb diff --git a/fpga/usrp2/control_lib/fifo_to_wb_tb.v b/fpga/usrp2/control_lib/fifo_to_wb_tb.v deleted file mode 100644 index 37459e2c2..000000000 --- a/fpga/usrp2/control_lib/fifo_to_wb_tb.v +++ /dev/null @@ -1,136 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module fifo_to_wb_tb(); - - reg clk = 0; - reg rst = 1; - reg clear = 0; - initial #1000 rst = 0; - always #50 clk = ~clk; - - reg trigger = 0; - initial #10000 trigger = 1; - - wire wb_cyc, wb_stb, wb_we, wb_ack; - wire [15:0] wb_adr; - wire [15:0] wb_dat_miso, wb_dat_mosi; - - reg cmd_src_rdy; - wire cmd_dst_rdy, resp_src_rdy, resp_dst_rdy; - reg [17:0] cmd; - wire [17:0] resp; - - wire [17:0] resp_int; - wire resp_src_rdy_int, resp_dst_rdy_int; - - fifo_to_wb fifo_to_wb - (.clk(clk), .reset(rst), .clear(clear), - .data_i(cmd), .src_rdy_i(cmd_src_rdy), .dst_rdy_o(cmd_dst_rdy), - .data_o(resp_int), .src_rdy_o(resp_src_rdy_int), .dst_rdy_i(resp_dst_rdy_int), - - .wb_adr_o(wb_adr), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), - .wb_sel_o(), .wb_cyc_o(wb_cyc), .wb_stb_o(wb_stb), - .wb_we_o(wb_we), .wb_ack_i(wb_ack), - .triggers()); - - assign wb_dat_miso = {wb_adr[7:0],8'hBF}; - - fifo19_pad #(.LENGTH(16)) fifo19_pad - (.clk(clk), .reset(rst), .clear(clear), - .data_i(resp_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int), - .data_o(resp), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy)); - - - // Set up monitors - always @(posedge clk) - if(wb_cyc & wb_stb & wb_ack) - if(wb_we) - $display("WB-WRITE ADDR:%h DATA:%h",wb_adr, wb_dat_mosi); - else - $display("WB-READ ADDR:%h DATA:%h",wb_adr, wb_dat_miso); - - always @(posedge clk) - if(cmd_src_rdy & cmd_dst_rdy) - $display("CMD-WRITE SOF:%b EOF:%b DATA:%h",cmd[16],cmd[17],cmd[15:0]); - - always @(posedge clk) - if(resp_src_rdy & resp_dst_rdy) - $display("RESP-READ SOF:%b EOF:%b DATA:%h",resp[16],resp[17],resp[15:0]); - - assign wb_ack = wb_stb; - assign resp_dst_rdy = 1; - - task InsertRW; - input [15:0] data_start; - input [5:0] triggers; - input [7:0] seqno; - input [15:0] len; - input [15:0] addr; - reg [15:0] data_val; - - begin - data_val <= data_start; - @(posedge clk); - cmd <= {2'b01,2'b11,triggers,seqno}; - cmd_src_rdy <= 1; - @(posedge clk); - cmd <= {2'b00,len}; - @(posedge clk); - cmd <= {2'b00,addr}; - @(posedge clk); - cmd <= {2'b00,16'd0}; - @(posedge clk); - repeat (len) - begin - cmd <= {2'b00,data_val}; - data_val <= data_val + 1; - @(posedge clk); - end - repeat (12-len-1) - begin - cmd <= {2'b00,16'hBEEF}; - @(posedge clk); - end - cmd <= {2'b10, 16'hDEAD}; - @(posedge clk); - cmd_src_rdy <= 0; - end - endtask // InsertRead - - initial $dumpfile("fifo_to_wb_tb.vcd"); - initial $dumpvars(0,fifo_to_wb_tb); - - initial - begin - @(negedge rst); - //#10000; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - InsertRW(16'hF00D, 6'd0, 8'hB5, 16'd7, 16'h1234); - #20000; - InsertRW(16'h9876, 6'd0, 8'h43, 16'd8, 16'hBEEF); - #20000; - InsertRW(16'h1000, 6'd0, 8'h96, 16'd4, 16'hF00D); - #20000; - InsertRW(16'h3000, 6'd0, 8'h12, 16'd10,16'hDEAD); - #20000 $finish; - end - -endmodule // fifo_to_wb_tb diff --git a/fpga/usrp2/control_lib/gpio_atr.v b/fpga/usrp2/control_lib/gpio_atr.v deleted file mode 100644 index 82d72b815..000000000 --- a/fpga/usrp2/control_lib/gpio_atr.v +++ /dev/null @@ -1,71 +0,0 @@ - -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module gpio_atr - #(parameter BASE = 0, - parameter WIDTH = 32) - (input clk, input reset, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - input rx, input tx, - inout [WIDTH-1:0] gpio, - output reg [31:0] gpio_readback - ); - - wire [WIDTH-1:0] ddr, in_idle, in_tx, in_rx, in_fdx; - reg [WIDTH-1:0] rgpio, igpio; - - setting_reg #(.my_addr(BASE+0), .width(WIDTH)) reg_idle - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data), - .out(in_idle),.changed()); - - setting_reg #(.my_addr(BASE+1), .width(WIDTH)) reg_rx - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data), - .out(in_rx),.changed()); - - setting_reg #(.my_addr(BASE+2), .width(WIDTH)) reg_tx - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data), - .out(in_tx),.changed()); - - setting_reg #(.my_addr(BASE+3), .width(WIDTH)) reg_fdx - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data), - .out(in_fdx),.changed()); - - setting_reg #(.my_addr(BASE+4), .width(WIDTH)) reg_ddr - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data), - .out(ddr),.changed()); - - always @(posedge clk) - case({tx,rx}) - 2'b00: rgpio <= in_idle; - 2'b01: rgpio <= in_rx; - 2'b10: rgpio <= in_tx; - 2'b11: rgpio <= in_fdx; - endcase // case ({tx,rx}) - - integer n; - always @* - for(n=0;n. -// - - - -module gray2bin - #(parameter WIDTH=8) - (input [WIDTH-1:0] gray, - output reg [WIDTH-1:0] bin); - - integer i; - always @(gray) - for(i = 0;i>i); - -endmodule // gray2bin diff --git a/fpga/usrp2/control_lib/gray_send.v b/fpga/usrp2/control_lib/gray_send.v deleted file mode 100644 index 62402f8d3..000000000 --- a/fpga/usrp2/control_lib/gray_send.v +++ /dev/null @@ -1,46 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - - -module gray_send - #(parameter WIDTH = 8) - (input clk_in, input [WIDTH-1:0] addr_in, - input clk_out, output reg [WIDTH-1:0] addr_out); - - reg [WIDTH-1:0] gray_clkin, gray_clkout, gray_clkout_d1; - wire [WIDTH-1:0] gray, bin; - - bin2gray #(.WIDTH(WIDTH)) b2g (.bin(addr_in), .gray(gray) ); - - always @(posedge clk_in) - gray_clkin <= gray; - - always @(posedge clk_out) - gray_clkout <= gray_clkin; - - always @(posedge clk_out) - gray_clkout_d1 <= gray_clkout; - - gray2bin #(.WIDTH(WIDTH)) g2b (.gray(gray_clkout_d1), .bin(bin) ); - - // FIXME we may not need the next register, but it may help timing - always @(posedge clk_out) - addr_out <= bin; - -endmodule // gray_send diff --git a/fpga/usrp2/control_lib/icache.v b/fpga/usrp2/control_lib/icache.v deleted file mode 100644 index 810b5fa64..000000000 --- a/fpga/usrp2/control_lib/icache.v +++ /dev/null @@ -1,152 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module icache - #(parameter AWIDTH=14, - parameter CWIDTH=6) - - (input wb_clk_i, - input wb_rst_i, - input [AWIDTH-1:0] iwb_adr_i, - input iwb_stb_i, - output [31:0] iwb_dat_o, - output iwb_ack_o, - input [31:0] iram_dat_i, - output [AWIDTH-1:0] iram_adr_o, - output iram_en_o, - input flush); - - localparam TAGWIDTH = AWIDTH-CWIDTH-2; - reg stb_d1, ack_d1, miss_d1; - reg [AWIDTH-1:0] held_addr; - reg [31:0] idata [0:(1<. -// - - -// FIFO intended to be interchangeable with shortfifo, but -// based on block ram instead of SRL16's -// only one clock domain - -// Port A is write port, Port B is read port - -module longfifo - #(parameter WIDTH=32, SIZE=9) - (input clk, input rst, - input [WIDTH-1:0] datain, - output [WIDTH-1:0] dataout, - input read, - input write, - input clear, - output full, - output empty, - output reg [15:0] space, - output reg [15:0] occupied); - - // Read side states - localparam EMPTY = 0; - localparam PRE_READ = 1; - localparam READING = 2; - - reg [SIZE-1:0] wr_addr, rd_addr; - reg [1:0] read_state; - - reg empty_reg, full_reg; - always @(posedge clk) - if(rst) - wr_addr <= 0; - else if(clear) - wr_addr <= 0; - else if(write) - wr_addr <= wr_addr + 1; - - ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE)) - ram (.clka(clk), - .ena(1'b1), - .wea(write), - .addra(wr_addr), - .dia(datain), - .doa(), - - .clkb(clk), - .enb((read_state==PRE_READ)|read), - .web(0), - .addrb(rd_addr), - .dib(0), - .dob(dataout)); - - always @(posedge clk) - if(rst) - begin - read_state <= EMPTY; - rd_addr <= 0; - empty_reg <= 1; - end - else - if(clear) - begin - read_state <= EMPTY; - rd_addr <= 0; - empty_reg <= 1; - end - else - case(read_state) - EMPTY : - if(write) - begin - //rd_addr <= wr_addr; - read_state <= PRE_READ; - end - PRE_READ : - begin - read_state <= READING; - empty_reg <= 0; - rd_addr <= rd_addr + 1; - end - - READING : - if(read) - if(rd_addr == wr_addr) - begin - empty_reg <= 1; - if(write) - read_state <= PRE_READ; - else - read_state <= EMPTY; - end - else - rd_addr <= rd_addr + 1; - endcase // case(read_state) - - wire [SIZE-1:0] dont_write_past_me = rd_addr - 3; - wire becoming_full = wr_addr == dont_write_past_me; - - always @(posedge clk) - if(rst) - full_reg <= 0; - else if(clear) - full_reg <= 0; - else if(read & ~write) - full_reg <= 0; - //else if(write & ~read & (wr_addr == (rd_addr-3))) - else if(write & ~read & becoming_full) - full_reg <= 1; - - //assign empty = (read_state != READING); - assign empty = empty_reg; - - // assign full = ((rd_addr - 1) == wr_addr); - assign full = full_reg; - - ////////////////////////////////////////////// - // space and occupied are for diagnostics only - // not guaranteed exact - - localparam NUMLINES = (1<. -// - - -module medfifo - #(parameter WIDTH=32, - parameter DEPTH=1) - (input clk, input rst, - input [WIDTH-1:0] datain, - output [WIDTH-1:0] dataout, - input read, - input write, - input clear, - output full, - output empty, - output [7:0] space, - output [7:0] occupied); - - localparam NUM_FIFOS = (1<. -// - - - -module mux4 - #(parameter WIDTH=32, parameter DISABLED=0) - (input en, - input [1:0] sel, - input [WIDTH-1:0] i0, - input [WIDTH-1:0] i1, - input [WIDTH-1:0] i2, - input [WIDTH-1:0] i3, - output [WIDTH-1:0] o); - - assign o = en ? (sel[1] ? (sel[0] ? i3 : i2) : (sel[0] ? i1 : i0)) : - DISABLED; - -endmodule // mux4 diff --git a/fpga/usrp2/control_lib/mux8.v b/fpga/usrp2/control_lib/mux8.v deleted file mode 100644 index bdb015dc3..000000000 --- a/fpga/usrp2/control_lib/mux8.v +++ /dev/null @@ -1,38 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module mux8 - #(parameter WIDTH=32, parameter DISABLED=0) - (input en, - input [2:0] sel, - input [WIDTH-1:0] i0, - input [WIDTH-1:0] i1, - input [WIDTH-1:0] i2, - input [WIDTH-1:0] i3, - input [WIDTH-1:0] i4, - input [WIDTH-1:0] i5, - input [WIDTH-1:0] i6, - input [WIDTH-1:0] i7, - output [WIDTH-1:0] o); - - assign o = en ? (sel[2] ? (sel[1] ? (sel[0] ? i7 : i6) : (sel[0] ? i5 : i4)) : - (sel[1] ? (sel[0] ? i3 : i2) : (sel[0] ? i1 : i0))) : - DISABLED; - -endmodule // mux8 diff --git a/fpga/usrp2/control_lib/mux_32_4.v b/fpga/usrp2/control_lib/mux_32_4.v deleted file mode 100644 index 4a1244933..000000000 --- a/fpga/usrp2/control_lib/mux_32_4.v +++ /dev/null @@ -1,30 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module mux_32_4 - (input [1:0] sel, - input [31:0] in0, - input [31:0] in1, - input [31:0] in2, - input [31:0] in3, - output [31:0] out); - - assign out = sel[1] ? (sel[0] ? in3 : in2) : (sel[0] ? in1 : in0); - -endmodule // mux_32_4 diff --git a/fpga/usrp2/control_lib/nsgpio.v b/fpga/usrp2/control_lib/nsgpio.v deleted file mode 100644 index 6c6873fee..000000000 --- a/fpga/usrp2/control_lib/nsgpio.v +++ /dev/null @@ -1,93 +0,0 @@ -// Modified from code originally by Richard Herveille, his copyright is below - -///////////////////////////////////////////////////////////////////// -//// //// -//// OpenCores Simple General Purpose IO core //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - - -module nsgpio - (input clk_i, input rst_i, - input cyc_i, input stb_i, input [4:0] adr_i, input we_i, input [31:0] dat_i, - output reg [31:0] dat_o, output reg ack_o, - input tx, input rx, inout [31:0] gpio - ); - - integer n; - reg [31:0] ddr; - reg [31:0] idle_out, rx_out, tx_out, fdx_out; - reg [31:0] rgpio, igpio; - - wire wb_acc = cyc_i & stb_i; // WISHBONE access - wire wb_wr = wb_acc & we_i; // WISHBONE write access - - always @(posedge clk_i or posedge rst_i) - if (rst_i) - ddr <= 0; - else if (wb_wr) - case( adr_i[4:2] ) - 3'b000 : - idle_out <= dat_i; - 3'b001 : - rx_out <= dat_i; - 3'b010 : - tx_out <= dat_i; - 3'b011 : - fdx_out <= dat_i; - 3'b100 : - ddr <= dat_i; - endcase // case ( adr_i[4:2] ) - - always @(posedge clk_i) - dat_o <= gpio; - - always @(posedge clk_i or posedge rst_i) - if (rst_i) - ack_o <= 1'b0; - else - ack_o <= wb_acc & !ack_o; - - always @(posedge clk_i) - case({tx,rx}) - 2'b00 : rgpio <= idle_out; - 2'b01 : rgpio <= rx_out; - 2'b10 : rgpio <= tx_out; - 2'b11 : rgpio <= fdx_out; - endcase // case ({tx,rx}) - - always @* - for(n=0;n<32;n=n+1) - igpio[n] <= ddr[n] ? rgpio[n] : 1'bz; - - assign gpio = igpio; - -endmodule diff --git a/fpga/usrp2/control_lib/nsgpio16LE.v b/fpga/usrp2/control_lib/nsgpio16LE.v deleted file mode 100644 index 8aef0c7ae..000000000 --- a/fpga/usrp2/control_lib/nsgpio16LE.v +++ /dev/null @@ -1,123 +0,0 @@ -// Modified from code originally by Richard Herveille, his copyright is below - -///////////////////////////////////////////////////////////////////// -//// //// -//// OpenCores Simple General Purpose IO core //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - - -module nsgpio16LE - (input clk_i, input rst_i, - input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [15:0] dat_i, - output reg [15:0] dat_o, output reg ack_o, - input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1, - inout [31:0] gpio - ); - - reg [31:0] ctrl, line, ddr, dbg, lgpio; - - wire wb_acc = cyc_i & stb_i; // WISHBONE access - wire wb_wr = wb_acc & we_i; // WISHBONE write access - - always @(posedge clk_i or posedge rst_i) - if (rst_i) - begin - ctrl <= 32'h0; - line <= 32'h0; - ddr <= 32'h0; - dbg <= 32'h0; - end - else if (wb_wr) - case( adr_i[3:1] ) - 3'b000 : - line[15:0] <= dat_i; - 3'b001 : - line[31:16] <= dat_i; - 3'b010 : - ddr[15:0] <= dat_i; - 3'b011 : - ddr[31:16] <= dat_i; - 3'b100 : - ctrl[15:0] <= dat_i; - 3'b101 : - ctrl[31:16] <= dat_i; - 3'b110 : - dbg[15:0] <= dat_i; - 3'b111 : - dbg[31:16] <= dat_i; - endcase // case ( adr_i[3:1] ) - - always @(posedge clk_i) - case (adr_i[3:1]) - 3'b000 : - dat_o <= lgpio[15:0]; - 3'b001 : - dat_o <= lgpio[31:16]; - 3'b010 : - dat_o <= ddr[15:0]; - 3'b011 : - dat_o <= ddr[31:16]; - 3'b100 : - dat_o <= ctrl[15:0]; - 3'b101 : - dat_o <= ctrl[31:16]; - 3'b110 : - dat_o <= dbg[15:0]; - 3'b111 : - dat_o <= dbg[31:16]; - endcase // case (adr_i[3:1]) - - - always @(posedge clk_i or posedge rst_i) - if (rst_i) - ack_o <= 1'b0; - else - ack_o <= wb_acc & !ack_o; - - // latch GPIO input pins - always @(posedge clk_i) - lgpio <= gpio; - - // assign GPIO outputs - integer n; - reg [31:0] igpio; // temporary internal signal - - always @(ctrl or line or debug_1 or debug_0 or atr or ddr or dbg) - for(n=0;n<32;n=n+1) - igpio[n] <= ddr[n] ? (dbg[n] ? (ctrl[n] ? debug_1[n] : debug_0[n]) : - (ctrl[n] ? atr[n] : line[n]) ) - : 1'bz; - - assign gpio = igpio; - -endmodule - diff --git a/fpga/usrp2/control_lib/oneshot_2clk.v b/fpga/usrp2/control_lib/oneshot_2clk.v deleted file mode 100644 index 7ed5bc8f6..000000000 --- a/fpga/usrp2/control_lib/oneshot_2clk.v +++ /dev/null @@ -1,52 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Retime a single bit from one clock domain to another -// Guarantees that no matter what the relative clock rates, if the in signal is high for at least -// one clock cycle in the clk_in domain, then the out signal will be high for at least one -// clock cycle in the clk_out domain. If the in signal goes high again before the process is done -// the behavior is undefined. No other guarantees. Designed for passing reset into a new -// clock domain. - -module oneshot_2clk - (input clk_in, - input in, - input clk_out, - output reg out); - - reg del_in = 0; - reg sendit = 0, gotit = 0; - reg sendit_d = 0, gotit_d = 0; - - always @(posedge clk_in) del_in <= in; - - always @(posedge clk_in) - if(in & ~del_in) // we have a positive edge - sendit <= 1; - else if(gotit) - sendit <= 0; - - always @(posedge clk_out) sendit_d <= sendit; - always @(posedge clk_out) out <= sendit_d; - - always @(posedge clk_in) gotit_d <= out; - always @(posedge clk_in) gotit <= gotit_d; - -endmodule // oneshot_2clk - - diff --git a/fpga/usrp2/control_lib/pic.v b/fpga/usrp2/control_lib/pic.v deleted file mode 100644 index 9b9944d4a..000000000 --- a/fpga/usrp2/control_lib/pic.v +++ /dev/null @@ -1,183 +0,0 @@ - -// Heavily modified by M. Ettus, 2009, little original code remains -// Modified by M. Ettus, 2008 for 32 bit width - -///////////////////////////////////////////////////////////////////// -//// //// -//// OpenCores Simple Programmable Interrupt Controller //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// -// -// This is a simple Programmable Interrupt Controller. -// The number of interrupts is depending on the databus size. -// There's one interrupt input per databit (i.e. 16 interrupts for a 16 -// bit databus). -// All attached devices share the same CPU priority level. -// -// -// -// Registers: -// -// 0x00: EdgeEnable Register -// bits 7:0 R/W Edge Enable '1' = edge triggered interrupt source -// '0' = level triggered interrupt source -// 0x01: PolarityRegister -// bits 7:0 R/W Polarity '1' = high level / rising edge -// '0' = low level / falling edge -// 0x02: MaskRegister -// bits 7:0 R/W Mask '1' = interrupt masked (disabled) -// '0' = interrupt not masked (enabled) -// 0x03: PendingRegister -// bits 7:0 R/W Pending '1' = interrupt pending -// '0' = no interrupt pending -// -// A CPU interrupt is generated when an interrupt is pending and its -// MASK bit is cleared. -// -// -// -// HOWTO: -// -// Clearing pending interrupts: -// Writing a '1' to a bit in the interrupt pending register clears the -// interrupt. Make sure to clear the interrupt at the source before -// writing to the interrupt pending register. Otherwise the interrupt -// will be set again. -// -// Priority based interrupts: -// Upon reception of an interrupt, check the interrupt register and -// determine the highest priority interrupt. Mask all interrupts from the -// current level to the lowest level. This negates the interrupt line, and -// makes sure only interrupts with a higher level are triggered. After -// completion of the interrupt service routine, clear the interrupt source, -// the interrupt bit in the pending register, and restore the MASK register -// to it's previous state. -// -// Addapt the core for fewer interrupt sources: -// If less than 8 interrupt sources are required, than the 'is' parameter -// can be set to the amount of required interrupts. Interrupts are mapped -// starting at the LSBs. So only the 'is' LSBs per register are valid. All -// other bits (i.e. the 8-'is' MSBs) are set to zero '0'. -// Codesize is approximately linear to the amount of interrupts. I.e. using -// 4 instead of 8 interrupt sources reduces the size by approx. half. -// - - -module pic - (input clk_i, input rst_i, input cyc_i, input stb_i, - input [2:0] adr_i, - input we_i, - input [31:0] dat_i, - output reg [31:0] dat_o, - output reg ack_o, - output reg int_o, - input [31:0] irq - ); - - reg [31:0] pol, edgen, pending, mask; // register bank - reg [31:0] lirq, dirq; // latched irqs, delayed latched irqs - - // latch interrupt inputs - always @(posedge clk_i) - lirq <= irq; - - // generate delayed latched irqs - always @(posedge clk_i) - dirq <= lirq; - - // generate actual triggers - function trigger; - input edgen, pol, lirq, dirq; - reg edge_irq, level_irq; - begin - edge_irq = pol ? (lirq & ~dirq) : (dirq & ~lirq); - level_irq = pol ? lirq : ~lirq; - trigger = edgen ? edge_irq : level_irq; - end - endfunction - - reg [31:0] irq_event; - integer n; - always @(posedge clk_i) - for(n = 0; n < 32; n = n+1) - irq_event[n] <= trigger(edgen[n], pol[n], lirq[n], dirq[n]); - - // generate wishbone register bank writes - wire wb_acc = cyc_i & stb_i; // WISHBONE access - wire wb_wr = wb_acc & we_i; // WISHBONE write access - - always @(posedge clk_i) - if (rst_i) - begin - pol <= 0; // clear polarity register - edgen <= 0; // clear edge enable register - mask <= 0; // mask all interrupts - end - else if(wb_wr) // wishbone write cycle?? - case (adr_i) // synopsys full_case parallel_case - 3'd0 : edgen <= dat_i; // EDGE-ENABLE register - 3'd1 : pol <= dat_i; // POLARITY register - 3'd2 : mask <= dat_i; // MASK register - 3'd3 : ; // PENDING register is a special case (see below) - 3'd4 : ; // Priority encoded live (pending & ~mask) - endcase - - // pending register is a special case - always @(posedge clk_i) - if (rst_i) - pending <= 0; // clear all pending interrupts - else if ( wb_wr & (adr_i == 3'd3) ) - pending <= (pending & ~dat_i) | irq_event; - else - pending <= pending | irq_event; - - wire [31:0] live_enc; - priority_enc priority_enc ( .in(pending & ~mask), .out(live_enc) ); - - always @(posedge clk_i) - case (adr_i) // synopsys full_case parallel_case - 3'd0 : dat_o <= edgen; - 3'd1 : dat_o <= pol; - 3'd2 : dat_o <= mask; - 3'd3 : dat_o <= pending; - 3'd4 : dat_o <= live_enc; - endcase - - always @(posedge clk_i) - ack_o <= wb_acc & !ack_o; - - always @(posedge clk_i) - if(rst_i) - int_o <= 0; - else - int_o <= |(pending & ~mask); - -endmodule diff --git a/fpga/usrp2/control_lib/priority_enc.v b/fpga/usrp2/control_lib/priority_enc.v deleted file mode 100644 index d30870be9..000000000 --- a/fpga/usrp2/control_lib/priority_enc.v +++ /dev/null @@ -1,61 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module priority_enc - (input [31:0] in, - output reg [31:0] out); - - always @* - casex(in) - 32'b1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 31; - 32'b01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 30; - 32'b001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 29; - 32'b0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 28; - 32'b0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 27; - 32'b0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 26; - 32'b0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 25; - 32'b0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 24; - 32'b0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 23; - 32'b0000_0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 22; - 32'b0000_0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 21; - 32'b0000_0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 20; - 32'b0000_0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx : out <= 19; - 32'b0000_0000_0000_01xx_xxxx_xxxx_xxxx_xxxx : out <= 18; - 32'b0000_0000_0000_001x_xxxx_xxxx_xxxx_xxxx : out <= 17; - 32'b0000_0000_0000_0001_xxxx_xxxx_xxxx_xxxx : out <= 16; - 32'b0000_0000_0000_0000_1xxx_xxxx_xxxx_xxxx : out <= 15; - 32'b0000_0000_0000_0000_01xx_xxxx_xxxx_xxxx : out <= 14; - 32'b0000_0000_0000_0000_001x_xxxx_xxxx_xxxx : out <= 13; - 32'b0000_0000_0000_0000_0001_xxxx_xxxx_xxxx : out <= 12; - 32'b0000_0000_0000_0000_0000_1xxx_xxxx_xxxx : out <= 11; - 32'b0000_0000_0000_0000_0000_01xx_xxxx_xxxx : out <= 10; - 32'b0000_0000_0000_0000_0000_001x_xxxx_xxxx : out <= 9; - 32'b0000_0000_0000_0000_0000_0001_xxxx_xxxx : out <= 8; - 32'b0000_0000_0000_0000_0000_0000_1xxx_xxxx : out <= 7; - 32'b0000_0000_0000_0000_0000_0000_01xx_xxxx : out <= 6; - 32'b0000_0000_0000_0000_0000_0000_001x_xxxx : out <= 5; - 32'b0000_0000_0000_0000_0000_0000_0001_xxxx : out <= 4; - 32'b0000_0000_0000_0000_0000_0000_0000_1xxx : out <= 3; - 32'b0000_0000_0000_0000_0000_0000_0000_01xx : out <= 2; - 32'b0000_0000_0000_0000_0000_0000_0000_001x : out <= 1; - 32'b0000_0000_0000_0000_0000_0000_0000_0001 : out <= 0; - 32'b0000_0000_0000_0000_0000_0000_0000_0000 : out <= 32'hFFFF_FFFF; - default : out <= 32'hFFFF_FFFF; - endcase // casex (in) - -endmodule // priority_enc diff --git a/fpga/usrp2/control_lib/quad_uart.v b/fpga/usrp2/control_lib/quad_uart.v deleted file mode 100644 index 39998150d..000000000 --- a/fpga/usrp2/control_lib/quad_uart.v +++ /dev/null @@ -1,88 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module quad_uart - #(parameter TXDEPTH = 1, - parameter RXDEPTH = 1) - (input clk_i, input rst_i, - input we_i, input stb_i, input cyc_i, output reg ack_o, - input [4:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o, - output [3:0] rx_int_o, output [3:0] tx_int_o, - output [3:0] tx_o, input [3:0] rx_i, output [3:0] baud_o - ); - - // Register Map - localparam SUART_CLKDIV = 0; - localparam SUART_TXLEVEL = 1; - localparam SUART_RXLEVEL = 2; - localparam SUART_TXCHAR = 3; - localparam SUART_RXCHAR = 4; - - wire wb_acc = cyc_i & stb_i; // WISHBONE access - wire wb_wr = wb_acc & we_i; // WISHBONE write access - - reg [15:0] clkdiv[0:3]; - wire [7:0] rx_char[0:3]; - wire [3:0] tx_fifo_full, rx_fifo_empty; - wire [7:0] tx_fifo_level[0:3], rx_fifo_level[0:3]; - - always @(posedge clk_i) - if (rst_i) - ack_o <= 1'b0; - else - ack_o <= wb_acc & ~ack_o; - - integer i; - always @(posedge clk_i) - if (rst_i) - for(i=0;i<4;i=i+1) - clkdiv[i] <= 0; - else if (wb_wr) - case(adr_i[2:0]) - SUART_CLKDIV : clkdiv[adr_i[4:3]] <= dat_i[15:0]; - endcase // case(adr_i) - - always @(posedge clk_i) - case (adr_i[2:0]) - SUART_TXLEVEL : dat_o <= tx_fifo_level[adr_i[4:3]]; - SUART_RXLEVEL : dat_o <= rx_fifo_level[adr_i[4:3]]; - SUART_RXCHAR : dat_o <= rx_char[adr_i[4:3]]; - endcase // case(adr_i) - - genvar j; - generate - for(j=0;j<4;j=j+1) - begin : gen_uarts - simple_uart_tx #(.DEPTH(TXDEPTH)) simple_uart_tx - (.clk(clk_i),.rst(rst_i), - .fifo_in(dat_i[7:0]),.fifo_write(ack_o && wb_wr && (adr_i[2:0] == SUART_TXCHAR) && (adr_i[4:3]==j)), - .fifo_level(tx_fifo_level[j]),.fifo_full(tx_fifo_full[j]), - .clkdiv(clkdiv[j]),.baudclk(baud_o[j]),.tx(tx_o[j])); - - simple_uart_rx #(.DEPTH(RXDEPTH)) simple_uart_rx - (.clk(clk_i),.rst(rst_i), - .fifo_out(rx_char[j]),.fifo_read(ack_o && ~wb_wr && (adr_i[2:0] == SUART_RXCHAR) && (adr_i[4:3]==j)), - .fifo_level(rx_fifo_level[j]),.fifo_empty(rx_fifo_empty[j]), - .clkdiv(clkdiv[j]),.rx(rx_i[j])); - end // block: gen_uarts - endgenerate - - assign tx_int_o = ~tx_fifo_full; // Interrupt for those that have space - assign rx_int_o = ~rx_fifo_empty; // Interrupt for those that have data - -endmodule // quad_uart diff --git a/fpga/usrp2/control_lib/ram_2port.v b/fpga/usrp2/control_lib/ram_2port.v deleted file mode 100644 index 86d7e4703..000000000 --- a/fpga/usrp2/control_lib/ram_2port.v +++ /dev/null @@ -1,59 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module ram_2port - #(parameter DWIDTH=32, - parameter AWIDTH=9) - (input clka, - input ena, - input wea, - input [AWIDTH-1:0] addra, - input [DWIDTH-1:0] dia, - output reg [DWIDTH-1:0] doa, - - input clkb, - input enb, - input web, - input [AWIDTH-1:0] addrb, - input [DWIDTH-1:0] dib, - output reg [DWIDTH-1:0] dob); - - reg [DWIDTH-1:0] ram [(1<. -// - - -module ram_2port_mixed_width - (input clk16, - input en16, - input we16, - input [10:0] addr16, - input [15:0] di16, - output [15:0] do16, - input clk32, - input en32, - input we32, - input [9:0] addr32, - input [31:0] di32, - output [31:0] do32); - - wire en32a = en32 & ~addr32[9]; - wire en32b = en32 & addr32[9]; - wire en16a = en16 & ~addr16[10]; - wire en16b = en16 & addr16[10]; - - wire [31:0] do32a, do32b; - wire [15:0] do16a, do16b; - - assign do32 = addr32[9] ? do32b : do32a; - assign do16 = addr16[10] ? do16b : do16a; - - RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000), - .INIT_B(18'h00000), - .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" - .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion - .SRVAL_B(18'h00000), // Port B output value upon SSR assertion - .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE - .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE - ) - RAMB16BWE_S36_S18_0 (.DOA(do32a), // Port A 32-bit Data Output - .DOB(do16a), // Port B 16-bit Data Output - .DOPA(), // Port A 4-bit Parity Output - .DOPB(), // Port B 2-bit Parity Output - .ADDRA(addr32[8:0]), // Port A 9-bit Address Input - .ADDRB(addr16[9:0]), // Port B 10-bit Address Input - .CLKA(clk32), // Port A 1-bit Clock - .CLKB(clk16), // Port B 1-bit Clock - .DIA(di32), // Port A 32-bit Data Input - .DIB(di16), // Port B 16-bit Data Input - .DIPA(0), // Port A 4-bit parity Input - .DIPB(0), // Port-B 2-bit parity Input - .ENA(en32a), // Port A 1-bit RAM Enable Input - .ENB(en16a), // Port B 1-bit RAM Enable Input - .SSRA(0), // Port A 1-bit Synchronous Set/Reset Input - .SSRB(0), // Port B 1-bit Synchronous Set/Reset Input - .WEA({4{we32}}), // Port A 4-bit Write Enable Input - .WEB({2{we16}}) // Port B 2-bit Write Enable Input - ); - - RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000), - .INIT_B(18'h00000), - .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" - .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion - .SRVAL_B(18'h00000), // Port B output value upon SSR assertion - .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE - .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE - ) - RAMB16BWE_S36_S18_1 (.DOA(do32b), // Port A 32-bit Data Output - .DOB(do16b), // Port B 16-bit Data Output - .DOPA(), // Port A 4-bit Parity Output - .DOPB(), // Port B 2-bit Parity Output - .ADDRA(addr32[8:0]), // Port A 9-bit Address Input - .ADDRB(addr16[9:0]), // Port B 10-bit Address Input - .CLKA(clk32), // Port A 1-bit Clock - .CLKB(clk16), // Port B 1-bit Clock - .DIA(di32), // Port A 32-bit Data Input - .DIB(di16), // Port B 16-bit Data Input - .DIPA(0), // Port A 4-bit parity Input - .DIPB(0), // Port-B 2-bit parity Input - .ENA(en32b), // Port A 1-bit RAM Enable Input - .ENB(en16b), // Port B 1-bit RAM Enable Input - .SSRA(0), // Port A 1-bit Synchronous Set/Reset Input - .SSRB(0), // Port B 1-bit Synchronous Set/Reset Input - .WEA({4{we32}}), // Port A 4-bit Write Enable Input - .WEB({2{we16}}) // Port B 2-bit Write Enable Input - ); - -endmodule // ram_2port_mixed_width - - - - -// ISE 10.1.03 chokes on the following - -/* - - reg [31:0] ram [(1<. -// - - - -// Dual ported, Harvard architecture, cached ram - -module ram_harv_cache - #(parameter AWIDTH=15,parameter RAM_SIZE=16384,parameter ICWIDTH=6,parameter DCWIDTH=6) - (input wb_clk_i, input wb_rst_i, - - input [AWIDTH-1:0] ram_loader_adr_i, - input [31:0] ram_loader_dat_i, - input ram_loader_stb_i, - input [3:0] ram_loader_sel_i, - input ram_loader_we_i, - output ram_loader_ack_o, - input ram_loader_done_i, - - input [AWIDTH-1:0] iwb_adr_i, - input iwb_stb_i, - output [31:0] iwb_dat_o, - output iwb_ack_o, - - input [AWIDTH-1:0] dwb_adr_i, - input [31:0] dwb_dat_i, - output [31:0] dwb_dat_o, - input dwb_we_i, - output dwb_ack_o, - input dwb_stb_i, - input [3:0] dwb_sel_i, - - input flush_icache ); - - wire [31:0] iram_dat, dram_dat_i, dram_dat_o; - wire [AWIDTH-1:0] iram_adr, dram_adr; - wire iram_en, dram_en, dram_we; - wire [3:0] dram_sel; - - dpram32 #(.AWIDTH(AWIDTH),.RAM_SIZE(RAM_SIZE)) sys_ram - (.clk(wb_clk_i), - - .adr1_i(ram_loader_done_i ? iram_adr : ram_loader_adr_i), - .dat1_i(ram_loader_dat_i), - .dat1_o(iram_dat), - .we1_i(ram_loader_done_i ? 1'b0 : ram_loader_we_i), - .en1_i(ram_loader_done_i ? iram_en : ram_loader_stb_i), - .sel1_i(ram_loader_done_i ? 4'hF : ram_loader_sel_i), - - .adr2_i(dram_adr),.dat2_i(dram_dat_i),.dat2_o(dram_dat_o), - .we2_i(dram_we),.en2_i(dram_en),.sel2_i(dram_sel) ); - - // Data bus side - dcache #(.AWIDTH(AWIDTH),.CWIDTH(DCWIDTH)) - dcache(.wb_clk_i(wb_clk_i),.wb_rst_i(wb_rst_i), - .dwb_adr_i(dwb_adr_i),.dwb_stb_i(dwb_stb_i), - .dwb_we_i(dwb_we_i),.dwb_sel_i(dwb_sel_i), - .dwb_dat_i(dwb_dat_i),.dwb_dat_o(dwb_dat_o), - .dwb_ack_o(dwb_ack_o), - .dram_dat_i(dram_dat_o),.dram_dat_o(dram_dat_i),.dram_adr_o(dram_adr), - .dram_we_o(dram_we),.dram_en_o(dram_en), .dram_sel_o(dram_sel) ); - - // Instruction bus side - icache #(.AWIDTH(AWIDTH),.CWIDTH(ICWIDTH)) - icache(.wb_clk_i(wb_clk_i),.wb_rst_i(wb_rst_i), - .iwb_adr_i(iwb_adr_i),.iwb_stb_i(iwb_stb_i), - .iwb_dat_o(iwb_dat_o),.iwb_ack_o(iwb_ack_o), - .iram_dat_i(iram_dat),.iram_adr_o(iram_adr),.iram_en_o(iram_en), - .flush(flush_icache)); - - // RAM loader - assign ram_loader_ack_o = ram_loader_stb_i; - - // Performance Monitoring - wire i_wait = iwb_stb_i & ~iwb_ack_o; - wire d_wait = dwb_stb_i & ~dwb_ack_o; - -endmodule // ram_harv_cache diff --git a/fpga/usrp2/control_lib/ram_harvard.v b/fpga/usrp2/control_lib/ram_harvard.v deleted file mode 100644 index 00ffb1984..000000000 --- a/fpga/usrp2/control_lib/ram_harvard.v +++ /dev/null @@ -1,84 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -// Dual ported, Harvard architecture, cached ram - -module ram_harvard - #(parameter AWIDTH=15, - parameter RAM_SIZE=16384, - parameter ICWIDTH=6, - parameter DCWIDTH=6) - - (input wb_clk_i, - input wb_rst_i, - // Firmware download port. - input [AWIDTH-1:0] ram_loader_adr_i, - input [31:0] ram_loader_dat_i, - input [3:0] ram_loader_sel_i, - input ram_loader_stb_i, - input ram_loader_we_i, - input ram_loader_done_i, - // Instruction fetch port. - input [AWIDTH-1:0] if_adr, - output [31:0] if_data, - // Data access port. - input [AWIDTH-1:0] dwb_adr_i, - input [31:0] dwb_dat_i, - output [31:0] dwb_dat_o, - input dwb_we_i, - output dwb_ack_o, - input dwb_stb_i, - input [3:0] dwb_sel_i ); - - reg ack_d1; - reg stb_d1; - - dpram32 #(.AWIDTH(AWIDTH),.RAM_SIZE(RAM_SIZE)) - sys_ram - (.clk(wb_clk_i), - .adr1_i(ram_loader_done_i ? if_adr : ram_loader_adr_i), - .dat1_i(ram_loader_dat_i), - .dat1_o(if_data), - .we1_i(ram_loader_done_i ? 1'b0 : ram_loader_we_i), - .en1_i(ram_loader_done_i ? 1'b1 : ram_loader_stb_i), - //.sel1_i(ram_loader_done_i ? 4'hF : ram_loader_sel_i), - .sel1_i(ram_loader_sel_i), // Sel is only for writes anyway - .adr2_i(dwb_adr_i), - .dat2_i(dwb_dat_i), - .dat2_o(dwb_dat_o), - .we2_i(dwb_we_i), - .en2_i(dwb_stb_i), - .sel2_i(dwb_sel_i) - ); - - assign dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1)); - - always @(posedge wb_clk_i) - if(wb_rst_i) - ack_d1 <= 1'b0; - else - ack_d1 <= dwb_ack_o; - - always @(posedge wb_clk_i) - if(wb_rst_i) - stb_d1 <= 0; - else - stb_d1 <= dwb_stb_i; - -endmodule // ram_harvard diff --git a/fpga/usrp2/control_lib/ram_harvard2.v b/fpga/usrp2/control_lib/ram_harvard2.v deleted file mode 100644 index d8fe472f5..000000000 --- a/fpga/usrp2/control_lib/ram_harvard2.v +++ /dev/null @@ -1,94 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -// Dual ported, Harvard architecture - -module ram_harvard2 - #(parameter AWIDTH=15, - parameter RAM_SIZE=32768) - (input wb_clk_i, - input wb_rst_i, - // Instruction fetch port. - input [AWIDTH-1:0] if_adr, - output reg [31:0] if_data, - // Data access port. - input [AWIDTH-1:0] dwb_adr_i, - input [31:0] dwb_dat_i, - output reg [31:0] dwb_dat_o, - input dwb_we_i, - output dwb_ack_o, - input dwb_stb_i, - input [3:0] dwb_sel_i); - - reg ack_d1; - reg stb_d1; - - assign dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1)); - - always @(posedge wb_clk_i) - if(wb_rst_i) - ack_d1 <= 1'b0; - else - ack_d1 <= dwb_ack_o; - - always @(posedge wb_clk_i) - if(wb_rst_i) - stb_d1 <= 0; - else - stb_d1 <= dwb_stb_i; - - reg [7:0] ram0 [0:(RAM_SIZE/4)-1]; - reg [7:0] ram1 [0:(RAM_SIZE/4)-1]; - reg [7:0] ram2 [0:(RAM_SIZE/4)-1]; - reg [7:0] ram3 [0:(RAM_SIZE/4)-1]; - - // Port 1, Read only - always @(posedge wb_clk_i) - if_data[31:24] <= ram3[if_adr[AWIDTH-1:2]]; - always @(posedge wb_clk_i) - if_data[23:16] <= ram2[if_adr[AWIDTH-1:2]]; - always @(posedge wb_clk_i) - if_data[15:8] <= ram1[if_adr[AWIDTH-1:2]]; - always @(posedge wb_clk_i) - if_data[7:0] <= ram0[if_adr[AWIDTH-1:2]]; - - // Port 2, R/W - always @(posedge wb_clk_i) - if(dwb_stb_i) dwb_dat_o[31:24] <= ram3[dwb_adr_i[AWIDTH-1:2]]; - always @(posedge wb_clk_i) - if(dwb_stb_i) dwb_dat_o[23:16] <= ram2[dwb_adr_i[AWIDTH-1:2]]; - always @(posedge wb_clk_i) - if(dwb_stb_i) dwb_dat_o[15:8] <= ram1[dwb_adr_i[AWIDTH-1:2]]; - always @(posedge wb_clk_i) - if(dwb_stb_i) dwb_dat_o[7:0] <= ram0[dwb_adr_i[AWIDTH-1:2]]; - - always @(posedge wb_clk_i) - if(dwb_we_i & dwb_stb_i & dwb_sel_i[3]) - ram3[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[31:24]; - always @(posedge wb_clk_i) - if(dwb_we_i & dwb_stb_i & dwb_sel_i[2]) - ram2[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[23:16]; - always @(posedge wb_clk_i) - if(dwb_we_i & dwb_stb_i & dwb_sel_i[1]) - ram1[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[15:8]; - always @(posedge wb_clk_i) - if(dwb_we_i & dwb_stb_i & dwb_sel_i[0]) - ram0[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[7:0]; - -endmodule // ram_harvard diff --git a/fpga/usrp2/control_lib/ram_loader.v b/fpga/usrp2/control_lib/ram_loader.v deleted file mode 100644 index 85ccf91b4..000000000 --- a/fpga/usrp2/control_lib/ram_loader.v +++ /dev/null @@ -1,278 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module ram_loader - #(parameter AWIDTH=16, RAM_SIZE=16384) - ( - // Wishbone I/F and clock domain - input wb_clk, - input dsp_clk, - input ram_loader_rst, - output wire [31:0] wb_dat, - output wire [AWIDTH-1:0] wb_adr, - output wb_stb, - output reg [3:0] wb_sel, - output wb_we, - output reg ram_loader_done, - // CPLD signals and clock domain - input cpld_clk, - input cpld_din, - output reg cpld_start, - output reg cpld_mode, - output reg cpld_done, - input cpld_detached - ); - - localparam S0 = 0; - localparam S1 = 1; - localparam S2 = 2; - localparam S3 = 3; - localparam S4 = 4; - localparam S5 = 5; - localparam S6 = 6; - localparam RESET = 7; - - localparam WB_IDLE = 0; - localparam WB_WRITE = 1; - - - reg [AWIDTH+2:0] count; // 3 LSB's count bits in, the MSB's generate the Wishbone address - reg [6:0] shift_reg; - reg [7:0] data_reg; - reg sampled_clk; - reg sampled_clk_meta; - reg sampled_din; - reg inc_count; - reg load_data_reg; - reg shift; - reg wb_state, wb_next_state; - reg [2:0] state, next_state; - - // - // CPLD clock doesn't free run and is approximately 12.5MHz. - // Use 50MHz Wishbone clock to sample it as a signal and avoid having - // an extra clock domain for no reason. - // - - always @(posedge dsp_clk or posedge ram_loader_rst) - if (ram_loader_rst) - begin - sampled_clk_meta <= 1'b0; - sampled_clk <= 1'b0; - sampled_din <= 1'b0; - count <= 'h7FFF8; // Initialize so that address will be 0 when first byte fully received. - data_reg <= 0; - shift_reg <= 0; - end - else - begin - sampled_clk_meta <= cpld_clk; - sampled_clk <= sampled_clk_meta; - sampled_din <= cpld_din; - if (inc_count) - count <= count + 1'b1; - if (load_data_reg) - data_reg <= {shift_reg,sampled_din}; - if (shift) - shift_reg <= {shift_reg[5:0],sampled_din}; - end // else: !if(ram_loader_rst) - - - always @(posedge dsp_clk or posedge ram_loader_rst) - if (ram_loader_rst) - state <= RESET; - else - state <= next_state; - - - always @* - begin - // Defaults - next_state = state; - cpld_start = 1'b0; - shift = 1'b0; - inc_count = 0; - load_data_reg = 1'b0; - ram_loader_done = 1'b0; - cpld_mode = 1'b0; - cpld_done = 1'b1; - - - - case (state) //synthesis parallel_case full_case - // After reset wait until CPLD indicates its detached. - RESET: begin - if (cpld_detached) - next_state = S0; - else - next_state = RESET; - end - - // Assert cpld_start to signal the CPLD its to start sending serial clock and data. - // Assume cpld_clk is low as we transition into search for first rising edge - S0: begin - cpld_start = 1'b1; - cpld_done = 1'b0; - if (~cpld_detached) - next_state = S2; - else - next_state = S0; - end - - // - S1: begin - cpld_start = 1'b1; - cpld_done = 1'b0; - if (sampled_clk) - begin - // Found rising edge on cpld_clk. - if (count[2:0] == 3'b111) - // Its the last bit of a byte, send it out to the Wishbone bus. - begin - load_data_reg = 1'b1; - inc_count = 1'b1; - end - else - // Shift databit into LSB of shift register and increment count - begin - shift = 1'b1; - inc_count = 1'b1; - end // else: !if(count[2:0] == 3'b111) - next_state = S2; - end // if (sampled_clk) - else - next_state = S1; - end // case: S1 - - // - S2: begin - cpld_start = 1'b1; - cpld_done = 1'b0; - if (~sampled_clk) - // Found negative edge of clock - if (count[AWIDTH+2:3] == RAM_SIZE-1) // NOTE need to change this constant - // All firmware now downloaded - next_state = S3; - else - next_state = S1; - else - next_state = S2; - end // case: S2 - - // Now that terminal count is reached and all firmware is downloaded signal CPLD that download is done - // and that mode is now SPI mode. - S3: begin - if (sampled_clk) - begin - cpld_mode = 1'b1; - cpld_done = 1'b1; - next_state = S4; - end - else - next_state = S3; - end - - // Search for negedge of cpld_clk whilst keeping done sequence asserted. - // Keep done assserted - S4: begin - cpld_mode = 1'b1; - cpld_done = 1'b1; - if (~sampled_clk) - next_state = S5; - else - next_state = S4; - end - - // Search for posedge of cpld_clk whilst keeping done sequence asserted. - S5: begin - cpld_mode = 1'b1; - cpld_done = 1'b1; - if (sampled_clk) - next_state = S6; - else - next_state = S5; - end - - // Stay in this state until reset/power down - S6: begin - ram_loader_done = 1'b1; - cpld_done = 1'b1; - cpld_mode = 1'b1; - next_state = S6; - end - - endcase // case(state) - end - - always @(posedge dsp_clk or posedge ram_loader_rst) - if (ram_loader_rst) - wb_state <= WB_IDLE; - else - wb_state <= wb_next_state; - - reg do_write; - wire empty, full; - - always @* - begin - wb_next_state = wb_state; - do_write = 1'b0; - - case (wb_state) //synthesis full_case parallel_case - // - WB_IDLE: begin - if (load_data_reg) - // Data reg will load ready to write wishbone @ next clock edge - wb_next_state = WB_WRITE; - else - wb_next_state = WB_IDLE; - end - - // Drive address and data onto wishbone. - WB_WRITE: begin - do_write = 1'b1; - if (~full) - wb_next_state = WB_IDLE; - else - wb_next_state = WB_WRITE; - end - - endcase // case(wb_state) - end // always @ * - - wire [1:0] count_out; - wire [7:0] data_out; - - fifo_xlnx_16x40_2clk crossclk - (.rst(ram_loader_rst), - .wr_clk(dsp_clk), .din({count[4:3],count[AWIDTH+2:3],data_reg}), .wr_en(do_write), .full(full), - .rd_clk(wb_clk), .dout({count_out,wb_adr,data_out}), .rd_en(~empty), .empty(empty)); - - assign wb_dat = {4{data_out}}; - - always @* - case(count_out[1:0]) //synthesis parallel_case full_case - 2'b00 : wb_sel = 4'b1000; - 2'b01 : wb_sel = 4'b0100; - 2'b10 : wb_sel = 4'b0010; - 2'b11 : wb_sel = 4'b0001; - endcase - - assign wb_we = ~empty; - assign wb_stb = ~empty; - -endmodule // ram_loader diff --git a/fpga/usrp2/control_lib/ram_wb_harvard.v b/fpga/usrp2/control_lib/ram_wb_harvard.v deleted file mode 100644 index 8d5a45247..000000000 --- a/fpga/usrp2/control_lib/ram_wb_harvard.v +++ /dev/null @@ -1,103 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Dual ported RAM for Harvard architecture processors -// Does no forwarding -// Addresses are byte-oriented, so botton 2 address bits are ignored. FIXME -// AWIDTH of 13 gives 8K bytes. For Spartan 3, if the total RAM size is not a -// multiple of 8K then BRAM space is wasted - -module ram_wb_harvard #(parameter AWIDTH=13) - (input wb_clk_i, - input wb_rst_i, - - input [AWIDTH-1:0] iwb_adr_i, - input [31:0] iwb_dat_i, - output reg [31:0] iwb_dat_o, - input iwb_we_i, - output reg iwb_ack_o, - input iwb_stb_i, - input [3:0] iwb_sel_i, - - input [AWIDTH-1:0] dwb_adr_i, - input [31:0] dwb_dat_i, - output reg [31:0] dwb_dat_o, - input dwb_we_i, - output reg dwb_ack_o, - input dwb_stb_i, - input [3:0] dwb_sel_i); - - reg [7:0] ram0 [0:(1<<(AWIDTH-2))-1]; - reg [7:0] ram1 [0:(1<<(AWIDTH-2))-1]; - reg [7:0] ram2 [0:(1<<(AWIDTH-2))-1]; - reg [7:0] ram3 [0:(1<<(AWIDTH-2))-1]; - - // Instruction Read Port - always @(posedge wb_clk_i) - iwb_ack_o <= iwb_stb_i & ~iwb_ack_o; - - always @(posedge wb_clk_i) - iwb_dat_o[31:24] <= ram3[iwb_adr_i[AWIDTH-1:2]]; - always @(posedge wb_clk_i) - iwb_dat_o[23:16] <= ram2[iwb_adr_i[AWIDTH-1:2]]; - always @(posedge wb_clk_i) - iwb_dat_o[15:8] <= ram1[iwb_adr_i[AWIDTH-1:2]]; - always @(posedge wb_clk_i) - iwb_dat_o[7:0] <= ram0[iwb_adr_i[AWIDTH-1:2]]; - - always @(posedge wb_clk_i) - if(iwb_we_i & iwb_stb_i & iwb_sel_i[3]) - ram3[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[31:24]; - always @(posedge wb_clk_i) - if(iwb_we_i & iwb_stb_i & iwb_sel_i[2]) - ram2[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[23:16]; - always @(posedge wb_clk_i) - if(iwb_we_i & iwb_stb_i & iwb_sel_i[1]) - ram1[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[15:8]; - always @(posedge wb_clk_i) - if(iwb_we_i & iwb_stb_i & iwb_sel_i[0]) - ram0[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[7:0]; - - // Data Port - always @(posedge wb_clk_i) - dwb_ack_o <= dwb_stb_i & ~dwb_ack_o; - - always @(posedge wb_clk_i) - dwb_dat_o[31:24] <= ram3[dwb_adr_i[AWIDTH-1:2]]; - always @(posedge wb_clk_i) - dwb_dat_o[23:16] <= ram2[dwb_adr_i[AWIDTH-1:2]]; - always @(posedge wb_clk_i) - dwb_dat_o[15:8] <= ram1[dwb_adr_i[AWIDTH-1:2]]; - always @(posedge wb_clk_i) - dwb_dat_o[7:0] <= ram0[dwb_adr_i[AWIDTH-1:2]]; - - always @(posedge wb_clk_i) - if(dwb_we_i & dwb_stb_i & dwb_sel_i[3]) - ram3[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[31:24]; - always @(posedge wb_clk_i) - if(dwb_we_i & dwb_stb_i & dwb_sel_i[2]) - ram2[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[23:16]; - always @(posedge wb_clk_i) - if(dwb_we_i & dwb_stb_i & dwb_sel_i[1]) - ram1[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[15:8]; - always @(posedge wb_clk_i) - if(dwb_we_i & dwb_stb_i & dwb_sel_i[0]) - ram0[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[7:0]; - -endmodule // ram_wb_harvard - diff --git a/fpga/usrp2/control_lib/reset_sync.v b/fpga/usrp2/control_lib/reset_sync.v deleted file mode 100644 index 304aba106..000000000 --- a/fpga/usrp2/control_lib/reset_sync.v +++ /dev/null @@ -1,33 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module reset_sync - (input clk, - input reset_in, - output reg reset_out); - - reg reset_int; - - always @(posedge clk or posedge reset_in) - if(reset_in) - {reset_out,reset_int} <= 2'b11; - else - {reset_out,reset_int} <= {reset_int,1'b0}; - -endmodule // reset_sync diff --git a/fpga/usrp2/control_lib/s3a_icap_wb.v b/fpga/usrp2/control_lib/s3a_icap_wb.v deleted file mode 100644 index e49b56cff..000000000 --- a/fpga/usrp2/control_lib/s3a_icap_wb.v +++ /dev/null @@ -1,76 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module s3a_icap_wb - (input clk, input reset, - input cyc_i, input stb_i, input we_i, output ack_o, - input [31:0] dat_i, output [31:0] dat_o);//, output [31:0] debug_out); - - assign dat_o[31:8] = 24'd0; - - wire BUSY, CE, WRITE, ICAPCLK; - - //changed this to gray-ish code to prevent glitching - reg [2:0] icap_state; - localparam ICAP_IDLE = 0; - localparam ICAP_WR0 = 1; - localparam ICAP_WR1 = 5; - localparam ICAP_RD0 = 2; - localparam ICAP_RD1 = 3; - - always @(posedge clk) - if(reset) - icap_state <= ICAP_IDLE; - else - case(icap_state) - ICAP_IDLE : - begin - if(stb_i & cyc_i) - if(we_i) - icap_state <= ICAP_WR0; - else - icap_state <= ICAP_RD0; - end - ICAP_WR0 : - icap_state <= ICAP_WR1; - ICAP_WR1 : - icap_state <= ICAP_IDLE; - ICAP_RD0 : - icap_state <= ICAP_RD1; - ICAP_RD1 : - icap_state <= ICAP_IDLE; - endcase // case (icap_state) - - assign WRITE = (icap_state == ICAP_WR0) | (icap_state == ICAP_WR1); - assign CE = (icap_state == ICAP_WR0) | (icap_state == ICAP_RD0); - assign ICAPCLK = CE & (~clk); - - assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1); - //assign debug_out = {17'd0, BUSY, dat_i[7:0], ~CE, ICAPCLK, ~WRITE, icap_state}; - - ICAP_SPARTAN3A ICAP_SPARTAN3A_inst - (.BUSY(BUSY), // Busy output - .O(dat_o[7:0]), // 32-bit data output - .CE(~CE), // Clock enable input - .CLK(ICAPCLK), // Clock input - .I(dat_i[7:0]), // 32-bit data input - .WRITE(~WRITE) // Write input - ); - -endmodule // s3a_icap_wb diff --git a/fpga/usrp2/control_lib/sd_spi.v b/fpga/usrp2/control_lib/sd_spi.v deleted file mode 100644 index fa998d19a..000000000 --- a/fpga/usrp2/control_lib/sd_spi.v +++ /dev/null @@ -1,87 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module sd_spi - (input clk, - input rst, - - // SD Card interface - output reg sd_clk, - output sd_mosi, - input sd_miso, - - // Controls - input [7:0] clk_div, - input [7:0] send_dat, - output [7:0] rcv_dat, - input go, - output ready); - - reg [7:0] clk_ctr; - reg [3:0] bit_ctr; - - wire bit_ready = (clk_ctr == 8'd0); - wire bit_busy = (clk_ctr != 8'd0); - wire bit_done = (clk_ctr == clk_div); - - wire send_clk_hi = (clk_ctr == (clk_div>>1)); - wire latch_dat = (clk_ctr == (clk_div - 8'd2)); - wire send_clk_lo = (clk_ctr == (clk_div - 8'd1)); - - wire send_bit = (bit_ready && (bit_ctr != 0)); - assign ready = (bit_ctr == 0); - - always @(posedge clk) - if(rst) - clk_ctr <= 0; - else if(bit_done) - clk_ctr <= 0; - else if(bit_busy) - clk_ctr <= clk_ctr + 1; - else if(send_bit) - clk_ctr <= 1; - - always @(posedge clk) - if(rst) - sd_clk <= 0; - else if(send_clk_hi) - sd_clk <= 1; - else if(send_clk_lo) - sd_clk <= 0; - - always @(posedge clk) - if(rst) - bit_ctr <= 0; - else if(bit_done) - if(bit_ctr == 4'd8) - bit_ctr <= 0; - else - bit_ctr <= bit_ctr + 1; - else if(bit_ready & go) - bit_ctr <= 1; - - reg [7:0] shift_reg; - always @(posedge clk) - if(go) - shift_reg <= send_dat; - else if(latch_dat) - shift_reg <= {shift_reg[6:0],sd_miso}; - - assign sd_mosi = shift_reg[7]; - assign rcv_dat = shift_reg; - -endmodule // sd_spi diff --git a/fpga/usrp2/control_lib/sd_spi_tb.v b/fpga/usrp2/control_lib/sd_spi_tb.v deleted file mode 100644 index 2b5ae083f..000000000 --- a/fpga/usrp2/control_lib/sd_spi_tb.v +++ /dev/null @@ -1,57 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module sd_spi_tb; - - reg clk = 0; - always #5 clk = ~clk; - reg rst = 1; - initial #32 rst = 0; - - wire sd_clk, sd_mosi, sd_miso; - wire [7:0] clk_div = 12; - wire [7:0] send_dat = 23; - wire [7:0] rcv_dat; - - wire ready; - reg go = 0; - initial - begin - repeat (100) - @(posedge clk); - go <= 1; - @(posedge clk); - go <= 0; - end - - sd_spi dut(.clk(clk),.rst(rst), - .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso), - .clk_div(clk_div),.send_dat(send_dat),.rcv_dat(rcv_dat), - .go(go),.ready(ready) ); - - initial - begin - $dumpfile("sd_spi_tb.vcd"); - $dumpvars(0,sd_spi_tb); - end - - initial - #10000 $finish(); - -endmodule // sd_spi_tb diff --git a/fpga/usrp2/control_lib/sd_spi_wb.v b/fpga/usrp2/control_lib/sd_spi_wb.v deleted file mode 100644 index b09debd70..000000000 --- a/fpga/usrp2/control_lib/sd_spi_wb.v +++ /dev/null @@ -1,93 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Wishbone module for spi communications with an SD Card -// The programming interface is simple -- -// Write the desired clock divider to address 1 (should be 1 or higher) -// Status is in address 0. A 1 indicates the last transaction is done and it is safe to -// send another -// Writing a byte to address 2 sends that byte over SPI. When it is done, -// status (addr 0) goes high again, and the received byte can be read from address 3. - -module sd_spi_wb - (input clk, - input rst, - - // SD Card interface - output sd_clk, - output sd_csn, - output sd_mosi, - input sd_miso, - - input wb_cyc_i, - input wb_stb_i, - input wb_we_i, - input [1:0] wb_adr_i, - input [7:0] wb_dat_i, - output reg [7:0] wb_dat_o, - output reg wb_ack_o); - - localparam ADDR_STATUS = 0; - localparam ADDR_CLKDIV = 1; - localparam ADDR_WRITE = 2; - localparam ADDR_READ = 3; - - wire [7:0] status, rcv_dat; - reg [7:0] clkdiv; - wire ready; - reg ack_d1; - - reg cs_reg; - assign sd_csn = ~cs_reg; // FIXME - - always @(posedge clk) - if(rst) ack_d1 <= 0; - else ack_d1 <= wb_ack_o; - - always @(posedge clk) - if(rst) wb_ack_o <= 0; - else wb_ack_o <= wb_cyc_i & wb_stb_i & ~ack_d1; - - always @(posedge clk) - case(wb_adr_i) - ADDR_STATUS : wb_dat_o <= {7'd0,ready}; - ADDR_CLKDIV : wb_dat_o <= clkdiv; - ADDR_READ : wb_dat_o <= rcv_dat; - default : wb_dat_o <= 0; - endcase // case(wb_adr_i) - - always @(posedge clk) - if(rst) - begin - clkdiv <= 200; - cs_reg <= 0; - end - else if(wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o) - case(wb_adr_i) - ADDR_STATUS : cs_reg <= wb_dat_i; - ADDR_CLKDIV : clkdiv <= wb_dat_i; - endcase // case(wb_adr_i) - - wire go = wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o & (wb_adr_i == ADDR_WRITE); - - sd_spi sd_spi(.clk(clk),.rst(rst), - .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso), - .clk_div(clkdiv),.send_dat(wb_dat_i),.rcv_dat(rcv_dat), - .go(go),.ready(ready) ); - -endmodule // sd_spi_wb diff --git a/fpga/usrp2/control_lib/setting_reg.v b/fpga/usrp2/control_lib/setting_reg.v deleted file mode 100644 index e4c84d910..000000000 --- a/fpga/usrp2/control_lib/setting_reg.v +++ /dev/null @@ -1,42 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module setting_reg - #(parameter my_addr = 0, - parameter width = 32, - parameter at_reset=32'd0) - (input clk, input rst, input strobe, input wire [7:0] addr, - input wire [31:0] in, output reg [width-1:0] out, output reg changed); - - always @(posedge clk) - if(rst) - begin - out <= at_reset; - changed <= 1'b0; - end - else - if(strobe & (my_addr==addr)) - begin - out <= in; - changed <= 1'b1; - end - else - changed <= 1'b0; - -endmodule // setting_reg diff --git a/fpga/usrp2/control_lib/settings_bus.v b/fpga/usrp2/control_lib/settings_bus.v deleted file mode 100644 index e2ea7e44b..000000000 --- a/fpga/usrp2/control_lib/settings_bus.v +++ /dev/null @@ -1,58 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Grab settings off the wishbone bus, send them out to our simpler bus on the fast clock - -module settings_bus - #(parameter AWIDTH=16, parameter DWIDTH=32) - (input wb_clk, - input wb_rst, - input [AWIDTH-1:0] wb_adr_i, - input [DWIDTH-1:0] wb_dat_i, - input wb_stb_i, - input wb_we_i, - output reg wb_ack_o, - output reg strobe, - output reg [7:0] addr, - output reg [31:0] data); - - reg stb_int, stb_int_d1; - - always @(posedge wb_clk) - if(wb_rst) - begin - strobe <= 1'b0; - addr <= 8'd0; - data <= 32'd0; - end - else if(wb_we_i & wb_stb_i & ~wb_ack_o) - begin - strobe <= 1'b1; - addr <= wb_adr_i[9:2]; - data <= wb_dat_i; - end - else - strobe <= 1'b0; - - always @(posedge wb_clk) - if(wb_rst) - wb_ack_o <= 0; - else - wb_ack_o <= wb_stb_i & ~wb_ack_o; - -endmodule // settings_bus diff --git a/fpga/usrp2/control_lib/settings_bus_16LE.v b/fpga/usrp2/control_lib/settings_bus_16LE.v deleted file mode 100644 index 7c42a0870..000000000 --- a/fpga/usrp2/control_lib/settings_bus_16LE.v +++ /dev/null @@ -1,71 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Grab settings off the wishbone bus, send them out to settings bus -// 16 bits little endian, but all registers need to be written 32 bits at a time. -// This means that you write the low 16 bits first and then the high 16 bits. -// The setting regs are strobed when the high 16 bits are written - -module settings_bus_16LE - #(parameter AWIDTH=16, RWIDTH=8) - (input wb_clk, - input wb_rst, - input [AWIDTH-1:0] wb_adr_i, - input [15:0] wb_dat_i, - input wb_stb_i, - input wb_we_i, - output reg wb_ack_o, - output strobe, - output reg [7:0] addr, - output reg [31:0] data); - - reg stb_int; - - always @(posedge wb_clk) - if(wb_rst) - begin - stb_int <= 1'b0; - addr <= 8'd0; - data <= 32'd0; - end - else if(wb_we_i & wb_stb_i) - begin - addr <= wb_adr_i[RWIDTH+1:2]; // Zero pad high bits - if(wb_adr_i[1]) - begin - stb_int <= 1'b1; // We now have both halves - data[31:16] <= wb_dat_i; - end - else - begin - stb_int <= 1'b0; // Don't strobe, we need other half - data[15:0] <= wb_dat_i; - end - end - else - stb_int <= 1'b0; - - always @(posedge wb_clk) - if(wb_rst) - wb_ack_o <= 0; - else - wb_ack_o <= wb_stb_i & ~wb_ack_o; - - assign strobe = stb_int & wb_ack_o; - -endmodule // settings_bus_16LE diff --git a/fpga/usrp2/control_lib/settings_bus_crossclock.v b/fpga/usrp2/control_lib/settings_bus_crossclock.v deleted file mode 100644 index a61ee8fad..000000000 --- a/fpga/usrp2/control_lib/settings_bus_crossclock.v +++ /dev/null @@ -1,38 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -// This module takes the settings bus on one clock domain and crosses it over to another domain -// Typically it will be used with the input settings bus on the wishbone clock, and either -// the system or dsp clock on the output side - -module settings_bus_crossclock - #(parameter FLOW_CTRL=0) - (input clk_i, input rst_i, input set_stb_i, input [7:0] set_addr_i, input [31:0] set_data_i, - input clk_o, input rst_o, output set_stb_o, output [7:0] set_addr_o, output [31:0] set_data_o, input blocked); - - wire full, empty; - - fifo_xlnx_16x40_2clk settings_fifo - (.rst(rst_i), - .wr_clk(clk_i), .din({set_addr_i,set_data_i}), .wr_en(set_stb_i & ~full), .full(full), - .rd_clk(clk_o), .dout({set_addr_o,set_data_o}), .rd_en(set_stb_o), .empty(empty)); - - assign set_stb_o = ~empty & (~blocked | ~FLOW_CTRL); - -endmodule // settings_bus_crossclock diff --git a/fpga/usrp2/control_lib/settings_fifo_ctrl.v b/fpga/usrp2/control_lib/settings_fifo_ctrl.v deleted file mode 100644 index 37f11776e..000000000 --- a/fpga/usrp2/control_lib/settings_fifo_ctrl.v +++ /dev/null @@ -1,395 +0,0 @@ -// -// Copyright 2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// A settings and readback bus controlled via fifo36 interface - -module settings_fifo_ctrl - #( - parameter XPORT_HDR = 1, //extra transport hdr line - parameter PROT_DEST = 0, //protocol framer destination - parameter PROT_HDR = 1, //needs a protocol header? - parameter ACK_SID = 0 //stream ID for packet ACK - ) - ( - //clock and synchronous reset for all interfaces - input clock, input reset, input clear, - - //current system time - input [63:0] vita_time, - - //ready signal for multiple peripherals - input perfs_ready, - - //input fifo36 interface control - input [35:0] in_data, input in_valid, output in_ready, - - //output fifo36 interface status - output [35:0] out_data, output out_valid, input out_ready, - - //32-bit settings bus outputs - output strobe, output [7:0] addr, output [31:0] data, - - //16X 32-bit inputs for readback - input [31:0] word00, - input [31:0] word01, - input [31:0] word02, - input [31:0] word03, - input [31:0] word04, - input [31:0] word05, - input [31:0] word06, - input [31:0] word07, - input [31:0] word08, - input [31:0] word09, - input [31:0] word10, - input [31:0] word11, - input [31:0] word12, - input [31:0] word13, - input [31:0] word14, - input [31:0] word15, - - //debug output - output [31:0] debug - ); - - wire reading = in_valid && in_ready; - wire writing = out_valid && out_ready; - - //------------------------------------------------------------------ - //-- The command fifo: - //-- Stores an individual register access command per line. - //------------------------------------------------------------------ - wire [63:0] in_command_ticks, out_command_ticks; - wire [31:0] in_command_hdr, out_command_hdr; - wire [31:0] in_command_data, out_command_data; - wire in_command_has_time, out_command_has_time; - wire command_fifo_full, command_fifo_empty; - wire command_fifo_read, command_fifo_write; - - shortfifo #(.WIDTH(129)) command_fifo ( - .clk(clock), .rst(reset), .clear(clear), - .datain({in_command_ticks, in_command_hdr, in_command_data, in_command_has_time}), - .dataout({out_command_ticks, out_command_hdr, out_command_data, out_command_has_time}), - .write(command_fifo_write), .full(command_fifo_full), //input interface - .empty(command_fifo_empty), .read(command_fifo_read) //output interface - ); - - //------------------------------------------------------------------ - //-- The result fifo: - //-- Stores an individual result of a command per line. - //------------------------------------------------------------------ - wire [31:0] in_result_hdr, out_result_hdr; - wire [31:0] in_result_data, out_result_data; - wire result_fifo_full, result_fifo_empty; - wire result_fifo_read, result_fifo_write; - - shortfifo #(.WIDTH(64)) result_fifo ( - .clk(clock), .rst(reset), .clear(clear), - .datain({in_result_hdr, in_result_data}), - .dataout({out_result_hdr, out_result_data}), - .write(result_fifo_write), .full(result_fifo_full), //input interface - .empty(result_fifo_empty), .read(result_fifo_read) //output interface - ); - - //------------------------------------------------------------------ - //-- Input state machine: - //-- Read input packet and fill a command fifo entry. - //------------------------------------------------------------------ - localparam READ_LINE0 = 0; - localparam VITA_HDR = 1; - localparam VITA_SID = 2; - localparam VITA_CID0 = 3; - localparam VITA_CID1 = 4; - localparam VITA_TSI = 5; - localparam VITA_TSF0 = 6; - localparam VITA_TSF1 = 7; - localparam READ_HDR = 8; - localparam READ_DATA = 9; - localparam WAIT_EOF = 10; - localparam STORE_CMD = 11; - - localparam START_STATE = (XPORT_HDR)? READ_LINE0 : VITA_HDR; - - reg [4:0] in_state; - - //holdover from current read inputs - reg [31:0] in_data_reg, in_hdr_reg; - reg [63:0] in_ticks_reg; - wire has_sid = in_data[28]; - wire has_cid = in_data[27]; - wire has_tsi = in_data[23:22] != 0; - wire has_tsf = in_data[21:20] != 0; - reg has_sid_reg, has_cid_reg, has_tsi_reg, has_tsf_reg; - - assign in_ready = (in_state < STORE_CMD); - assign command_fifo_write = (in_state == STORE_CMD); - assign in_command_ticks = in_ticks_reg; - assign in_command_data = in_data_reg; - assign in_command_hdr = in_hdr_reg; - assign in_command_has_time = has_tsf_reg; - - always @(posedge clock) begin - if (reset) begin - in_state <= START_STATE; - end - else begin - case (in_state) - - READ_LINE0: begin - if (reading) in_state <= VITA_HDR; - end - - VITA_HDR: begin - if (reading) begin - if (has_sid) in_state <= VITA_SID; - else if (has_cid) in_state <= VITA_CID0; - else if (has_tsi) in_state <= VITA_TSI; - else if (has_tsf) in_state <= VITA_TSF0; - else in_state <= READ_HDR; - end - has_sid_reg <= has_sid; - has_cid_reg <= has_cid; - has_tsi_reg <= has_tsi; - has_tsf_reg <= has_tsf; - end - - VITA_SID: begin - if (reading) begin - if (has_cid_reg) in_state <= VITA_CID0; - else if (has_tsi_reg) in_state <= VITA_TSI; - else if (has_tsf_reg) in_state <= VITA_TSF0; - else in_state <= READ_HDR; - end - end - - VITA_CID0: begin - if (reading) in_state <= VITA_CID1; - end - - VITA_CID1: begin - if (reading) begin - if (has_tsi_reg) in_state <= VITA_TSI; - else if (has_tsf_reg) in_state <= VITA_TSF0; - else in_state <= READ_HDR; - end - end - - VITA_TSI: begin - if (reading) begin - if (has_tsf_reg) in_state <= VITA_TSF0; - else in_state <= READ_HDR; - end - end - - VITA_TSF0: begin - if (reading) in_state <= VITA_TSF1; - in_ticks_reg[63:32] <= in_data; - end - - VITA_TSF1: begin - if (reading) in_state <= READ_HDR; - in_ticks_reg[31:0] <= in_data; - end - - READ_HDR: begin - if (reading) in_state <= READ_DATA; - in_hdr_reg <= in_data[31:0]; - end - - READ_DATA: begin - if (reading) in_state <= (in_data[33])? STORE_CMD : WAIT_EOF; - in_data_reg <= in_data[31:0]; - end - - WAIT_EOF: begin - if (reading && in_data[33]) in_state <= STORE_CMD; - end - - STORE_CMD: begin - if (~command_fifo_full) in_state <= START_STATE; - end - - endcase //in_state - end - end - - //------------------------------------------------------------------ - //-- Command state machine: - //-- Read a command fifo entry, act on it, produce result. - //------------------------------------------------------------------ - localparam LOAD_CMD = 0; - localparam EVENT_CMD = 1; - - reg cmd_state; - reg [31:0] rb_data; - - reg [63:0] command_ticks_reg; - reg [31:0] command_hdr_reg; - reg [31:0] command_data_reg; - - reg [63:0] vita_time_reg; - always @(posedge clock) - vita_time_reg <= vita_time; - - wire late; - `ifndef FIFO_CTRL_NO_TIME - time_compare time_compare( - .time_now(vita_time_reg), .trigger_time(command_ticks_reg), .late(late)); - `else - assign late = 1; - `endif - - //action occurs in the event state and when there is fifo space (should always be true) - //the third condition is that all peripherals in the perfs signal are ready/active high - //the fourth condition is that is an event time has been set, action is delayed until that time - wire time_ready = (out_command_has_time)? late : 1; - wire action = (cmd_state == EVENT_CMD) && ~result_fifo_full && perfs_ready && time_ready; - - assign command_fifo_read = action; - assign result_fifo_write = action; - assign in_result_hdr = command_hdr_reg; - assign in_result_data = rb_data; - - always @(posedge clock) begin - if (reset) begin - cmd_state <= LOAD_CMD; - end - else begin - case (cmd_state) - - LOAD_CMD: begin - if (~command_fifo_empty) cmd_state <= EVENT_CMD; - command_ticks_reg <= out_command_ticks; - command_hdr_reg <= out_command_hdr; - command_data_reg <= out_command_data; - end - - EVENT_CMD: begin // poking and peeking happens here! - if (action || clear) cmd_state <= LOAD_CMD; - end - - endcase //cmd_state - end - end - - //------------------------------------------------------------------ - //-- assign to settings bus interface - //------------------------------------------------------------------ - reg strobe_reg; - assign strobe = strobe_reg; - assign data = command_data_reg; - assign addr = command_hdr_reg[7:0]; - wire poke = command_hdr_reg[8]; - - always @(posedge clock) begin - if (reset || clear) strobe_reg <= 0; - else strobe_reg <= action && poke; - end - - //------------------------------------------------------------------ - //-- readback mux - //------------------------------------------------------------------ - always @(posedge clock) begin - case (out_command_hdr[3:0]) - 0 : rb_data <= word00; - 1 : rb_data <= word01; - 2 : rb_data <= word02; - 3 : rb_data <= word03; - 4 : rb_data <= word04; - 5 : rb_data <= word05; - 6 : rb_data <= word06; - 7 : rb_data <= word07; - 8 : rb_data <= word08; - 9 : rb_data <= word09; - 10: rb_data <= word10; - 11: rb_data <= word11; - 12: rb_data <= word12; - 13: rb_data <= word13; - 14: rb_data <= word14; - 15: rb_data <= word15; - endcase // case(addr_reg[3:0]) - end - - //------------------------------------------------------------------ - //-- Output state machine: - //-- Read a command fifo entry, act on it, produce ack packet. - //------------------------------------------------------------------ - localparam WRITE_PROT_HDR = 0; - localparam WRITE_VRT_HDR = 1; - localparam WRITE_VRT_SID = 2; - localparam WRITE_RB_HDR = 3; - localparam WRITE_RB_DATA = 4; - - //the state for the start of packet condition - localparam WRITE_PKT_HDR = (PROT_HDR)? WRITE_PROT_HDR : WRITE_VRT_HDR; - - reg [2:0] out_state; - - assign out_valid = ~result_fifo_empty; - assign result_fifo_read = out_data[33] && writing; - - always @(posedge clock) begin - if (reset) begin - out_state <= WRITE_PKT_HDR; - end - else if (writing && out_data[33]) begin - out_state <= WRITE_PKT_HDR; - end - else if (writing) begin - out_state <= out_state + 1; - end - end - - //------------------------------------------------------------------ - //-- assign to output fifo interface - //------------------------------------------------------------------ - wire [31:0] prot_hdr; - assign prot_hdr[15:0] = 16; //bytes in proceeding vita packet - assign prot_hdr[16] = 1; //yes frame - assign prot_hdr[18:17] = PROT_DEST; - assign prot_hdr[31:19] = 0; //nothing - - reg [31:0] out_data_int; - always @* begin - case (out_state) - WRITE_PROT_HDR: out_data_int <= prot_hdr; - WRITE_VRT_HDR: out_data_int <= {12'b010100000000, out_result_hdr[19:16], 2'b0, prot_hdr[15:2]}; - WRITE_VRT_SID: out_data_int <= ACK_SID; - WRITE_RB_HDR: out_data_int <= out_result_hdr; - WRITE_RB_DATA: out_data_int <= out_result_data; - default: out_data_int <= 0; - endcase //state - end - - assign out_data[35:34] = 2'b0; - assign out_data[33] = (out_state == WRITE_RB_DATA); - assign out_data[32] = (out_state == WRITE_PKT_HDR); - assign out_data[31:0] = out_data_int; - - //------------------------------------------------------------------ - //-- debug outputs - //------------------------------------------------------------------ - assign debug = { - in_state, out_state, //8 - in_valid, in_ready, in_data[33:32], //4 - out_valid, out_ready, out_data[33:32], //4 - command_fifo_empty, command_fifo_full, //2 - command_fifo_read, command_fifo_write, //2 - addr, //8 - strobe_reg, strobe, poke, out_command_has_time //4 - }; - -endmodule //settings_fifo_ctrl diff --git a/fpga/usrp2/control_lib/shortfifo.v b/fpga/usrp2/control_lib/shortfifo.v deleted file mode 100644 index c7c916375..000000000 --- a/fpga/usrp2/control_lib/shortfifo.v +++ /dev/null @@ -1,104 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module shortfifo - #(parameter WIDTH=32) - (input clk, input rst, - input [WIDTH-1:0] datain, - output [WIDTH-1:0] dataout, - input read, - input write, - input clear, - output reg full, - output reg empty, - output reg [4:0] space, - output reg [4:0] occupied); - - reg [3:0] a; - genvar i; - - generate - for (i=0;i. -// - -// Simple I2C core - -// Settings reg map: -// -// BASE+0 control register -// byte0 - control bits, data byte, or command bits, prescaler -// byte1 - what to do? (documented in cpp file) -// write prescaler lo -// write prescaler hi -// write control -// write data -// write command -// read data -// read status -// - -// Readback: -// -// byte0 has readback value based on the last read command -// - -module simple_i2c_core - #( - //settings register base address - parameter BASE = 0, - - //i2c line level at reset - parameter ARST_LVL = 1 - ) - ( - //clock and synchronous reset - input clock, input reset, - - //32-bit settings bus inputs - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - //32-bit data readback - output reg [31:0] readback, - - //read is high when i2c core can begin another transaction - output reg ready, - - // I2C signals - // i2c clock line - input scl_pad_i, // SCL-line input - output scl_pad_o, // SCL-line output (always 1'b0) - output scl_padoen_o, // SCL-line output enable (active low) - - // i2c data line - input sda_pad_i, // SDA-line input - output sda_pad_o, // SDA-line output (always 1'b0) - output sda_padoen_o, // SDA-line output enable (active low) - - //optional debug output - output [31:0] debug - ); - - //declare command settings register - wire [7:0] sr_what, sr_data; - wire sr_changed; - setting_reg #(.my_addr(BASE+0),.width(16)) i2c_cmd_sr( - .clk(clock),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data), - .out({sr_what, sr_data}),.changed(sr_changed)); - - //declare wb interface signals - wire [2:0] wb_addr; - wire [7:0] wb_data_mosi; - wire [7:0] wb_data_miso; - wire wb_we, wb_stb, wb_cyc; - wire wb_ack; - - //create wishbone-based i2c core - i2c_master_top #(.ARST_LVL(ARST_LVL)) i2c - (.wb_clk_i(clock),.wb_rst_i(reset),.arst_i(1'b0), - .wb_adr_i(wb_addr),.wb_dat_i(wb_data_mosi),.wb_dat_o(wb_data_miso), - .wb_we_i(wb_we),.wb_stb_i(wb_stb),.wb_cyc_i(wb_cyc), - .wb_ack_o(wb_ack),.wb_inta_o(), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_padoen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_padoen_o) ); - - //not ready between setting register and wishbone ack - always @(posedge clock) begin - if (reset || wb_ack) ready <= 1; - else if (sr_changed) ready <= 0; - end - - //register wishbone data on every ack - always @(posedge clock) begin - if (wb_ack) readback <= {24'b0, wb_data_miso}; - end - - //assign wishbone signals - assign wb_addr = sr_what[2:0]; - assign wb_stb = sr_changed; - assign wb_we = wb_stb && sr_what[3]; - assign wb_cyc = wb_stb; - assign wb_data_mosi = sr_data; - -endmodule //simple_i2c_core diff --git a/fpga/usrp2/control_lib/simple_spi_core.v b/fpga/usrp2/control_lib/simple_spi_core.v deleted file mode 100644 index 3c0ed60b9..000000000 --- a/fpga/usrp2/control_lib/simple_spi_core.v +++ /dev/null @@ -1,214 +0,0 @@ -// -// Copyright 2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// Simple SPI core, the simplest, yet complete spi core I can think of - -// Settings register controlled. -// 2 settings regs, control and data -// 1 32-bit readback and status signal - -// Settings reg map: -// -// BASE+0 divider setting -// bits [15:0] spi clock divider -// -// BASE+1 configuration input -// bits [23:0] slave select, bit0 = slave0 enabled -// bits [29:24] num bits (1 through 32) -// bit [30] data input edge = in data bit latched on rising edge of clock -// bit [31] data output edge = out data bit latched on rising edge of clock -// -// BASE+2 input data -// Writing this register begins a spi transaction. -// Bits are latched out from bit 0. -// Therefore, load this register in reverse. -// -// Readback -// Bits are latched into bit 0. -// Therefore, data will be in-order. - -module simple_spi_core - #( - //settings register base address - parameter BASE = 0, - - //width of serial enables (up to 24 is possible) - parameter WIDTH = 8, - - //idle state of the spi clock - parameter CLK_IDLE = 0, - - //idle state of the serial enables - parameter SEN_IDLE = 24'hffffff - ) - ( - //clock and synchronous reset - input clock, input reset, - - //32-bit settings bus inputs - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - //32-bit data readback - output [31:0] readback, - - //read is high when spi core can begin another transaction - output ready, - - //spi interface, slave selects, clock, data in, data out - output [WIDTH-1:0] sen, - output sclk, - output mosi, - input miso, - - //optional debug output - output [31:0] debug - ); - - wire [15:0] sclk_divider; - setting_reg #(.my_addr(BASE+0),.width(16)) divider_sr( - .clk(clock),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data), - .out(sclk_divider),.changed()); - - wire [23:0] slave_select; - wire [5:0] num_bits; - wire datain_edge, dataout_edge; - setting_reg #(.my_addr(BASE+1),.width(32)) config_sr( - .clk(clock),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data), - .out({dataout_edge, datain_edge, num_bits, slave_select}),.changed()); - - wire [31:0] mosi_data; - wire trigger_spi; - setting_reg #(.my_addr(BASE+2),.width(32)) data_sr( - .clk(clock),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data), - .out(mosi_data),.changed(trigger_spi)); - - localparam WAIT_TRIG = 0; - localparam PRE_IDLE = 1; - localparam CLK_REG = 2; - localparam CLK_INV = 3; - localparam POST_IDLE = 4; - localparam IDLE_SEN = 5; - - reg [2:0] state; - - reg ready_reg; - assign ready = ready_reg && ~trigger_spi; - - //serial clock either idles or is in one of two clock states - reg sclk_reg; - assign sclk = sclk_reg; - - //serial enables either idle or enabled based on state - wire sen_is_idle = (state == WAIT_TRIG) || (state == IDLE_SEN); - wire [23:0] sen24 = (sen_is_idle)? SEN_IDLE : (SEN_IDLE ^ slave_select); - reg [WIDTH-1:0] sen_reg; - always @(posedge clock) sen_reg <= sen24[WIDTH-1:0]; - assign sen = sen_reg; - - //data output shift register - reg [31:0] dataout_reg; - wire [31:0] dataout_next = {dataout_reg[30:0], 1'b0}; - assign mosi = dataout_reg[31]; - - //data input shift register - reg [31:0] datain_reg; - wire [31:0] datain_next = {datain_reg[30:0], miso}; - assign readback = datain_reg; - - //counter for spi clock - reg [15:0] sclk_counter; - wire sclk_counter_done = (sclk_counter == sclk_divider); - wire [15:0] sclk_counter_next = (sclk_counter_done)? 0 : sclk_counter + 1; - - //counter for latching bits miso/mosi - reg [6:0] bit_counter; - wire [6:0] bit_counter_next = bit_counter + 1; - wire bit_counter_done = (bit_counter_next == num_bits); - - always @(posedge clock) begin - if (reset) begin - state <= WAIT_TRIG; - sclk_reg <= CLK_IDLE; - ready_reg <= 0; - end - else begin - case (state) - - WAIT_TRIG: begin - if (trigger_spi) state <= PRE_IDLE; - ready_reg <= ~trigger_spi; - dataout_reg <= mosi_data; - sclk_counter <= 0; - bit_counter <= 0; - sclk_reg <= CLK_IDLE; - end - - PRE_IDLE: begin - if (sclk_counter_done) state <= CLK_REG; - sclk_counter <= sclk_counter_next; - sclk_reg <= CLK_IDLE; - end - - CLK_REG: begin - if (sclk_counter_done) begin - state <= CLK_INV; - if (datain_edge != CLK_IDLE) datain_reg <= datain_next; - if (dataout_edge != CLK_IDLE && bit_counter != 0) dataout_reg <= dataout_next; - sclk_reg <= ~CLK_IDLE; //transition to rising when CLK_IDLE == 0 - end - sclk_counter <= sclk_counter_next; - end - - CLK_INV: begin - if (sclk_counter_done) begin - state <= (bit_counter_done)? POST_IDLE : CLK_REG; - bit_counter <= bit_counter_next; - if (datain_edge == CLK_IDLE) datain_reg <= datain_next; - if (dataout_edge == CLK_IDLE && ~bit_counter_done) dataout_reg <= dataout_next; - sclk_reg <= CLK_IDLE; //transition to falling when CLK_IDLE == 0 - end - sclk_counter <= sclk_counter_next; - end - - POST_IDLE: begin - if (sclk_counter_done) state <= IDLE_SEN; - sclk_counter <= sclk_counter_next; - sclk_reg <= CLK_IDLE; - end - - IDLE_SEN: begin - if (sclk_counter_done) state <= WAIT_TRIG; - sclk_counter <= sclk_counter_next; - sclk_reg <= CLK_IDLE; - end - - default: state <= WAIT_TRIG; - - endcase //state - end - end - - assign debug = { - trigger_spi, state, //4 - sclk, mosi, miso, ready, //4 - sen[7:0], //8 - 1'b0, bit_counter[6:0], //8 - sclk_counter_done, bit_counter_done, //2 - sclk_counter[5:0] //6 - }; - -endmodule //simple_spi_core diff --git a/fpga/usrp2/control_lib/simple_uart.v b/fpga/usrp2/control_lib/simple_uart.v deleted file mode 100644 index f44a719f4..000000000 --- a/fpga/usrp2/control_lib/simple_uart.v +++ /dev/null @@ -1,79 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module simple_uart - #(parameter TXDEPTH = 1, - parameter RXDEPTH = 1, - parameter CLKDIV_DEFAULT = 16'd0) - (input clk_i, input rst_i, - input we_i, input stb_i, input cyc_i, output reg ack_o, - input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o, - output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o); - - // Register Map - localparam SUART_CLKDIV = 0; - localparam SUART_TXLEVEL = 1; - localparam SUART_RXLEVEL = 2; - localparam SUART_TXCHAR = 3; - localparam SUART_RXCHAR = 4; - - wire wb_acc = cyc_i & stb_i; // WISHBONE access - wire wb_wr = wb_acc & we_i; // WISHBONE write access - - reg [15:0] clkdiv; - wire [7:0] rx_char; - wire tx_fifo_full, rx_fifo_empty; - wire [7:0] tx_fifo_level, rx_fifo_level; - - always @(posedge clk_i) - if (rst_i) - ack_o <= 1'b0; - else - ack_o <= wb_acc & ~ack_o; - - always @(posedge clk_i) - if (rst_i) - clkdiv <= CLKDIV_DEFAULT; - else if (wb_wr) - case(adr_i) - SUART_CLKDIV : clkdiv <= dat_i[15:0]; - endcase // case(adr_i) - - always @(posedge clk_i) - case (adr_i) - SUART_TXLEVEL : dat_o <= tx_fifo_level; - SUART_RXLEVEL : dat_o <= rx_fifo_level; - SUART_RXCHAR : dat_o <= rx_char; - endcase // case(adr_i) - - simple_uart_tx #(.DEPTH(TXDEPTH)) simple_uart_tx - (.clk(clk_i),.rst(rst_i), - .fifo_in(dat_i[7:0]),.fifo_write(ack_o && wb_wr && (adr_i == SUART_TXCHAR)), - .fifo_level(tx_fifo_level),.fifo_full(tx_fifo_full), - .clkdiv(clkdiv),.baudclk(baud_o),.tx(tx_o)); - - simple_uart_rx #(.DEPTH(RXDEPTH)) simple_uart_rx - (.clk(clk_i),.rst(rst_i), - .fifo_out(rx_char),.fifo_read(ack_o && ~wb_wr && (adr_i == SUART_RXCHAR)), - .fifo_level(rx_fifo_level),.fifo_empty(rx_fifo_empty), - .clkdiv(clkdiv),.rx(rx_i)); - - assign tx_int_o = ~tx_fifo_full; - assign rx_int_o = ~rx_fifo_empty; - -endmodule // simple_uart diff --git a/fpga/usrp2/control_lib/simple_uart_rx.v b/fpga/usrp2/control_lib/simple_uart_rx.v deleted file mode 100644 index 5f7646e03..000000000 --- a/fpga/usrp2/control_lib/simple_uart_rx.v +++ /dev/null @@ -1,81 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module simple_uart_rx - #(parameter DEPTH=0) - (input clk, input rst, - output [7:0] fifo_out, input fifo_read, output [7:0] fifo_level, output fifo_empty, - input [15:0] clkdiv, input rx); - - reg rx_d1, rx_d2; - always @(posedge clk) - if(rst) - {rx_d2,rx_d1} <= 0; - else - {rx_d2,rx_d1} <= {rx_d1,rx}; - - reg [15:0] baud_ctr; - reg [3:0] bit_ctr; - reg [7:0] sr; - - wire neg_trans = rx_d2 & ~rx_d1; - wire shift_now = baud_ctr == (clkdiv>>1); - wire stop_now = (bit_ctr == 10) && shift_now; - wire go_now = (bit_ctr == 0) && neg_trans; - - always @(posedge clk) - if(rst) - sr <= 0; - else if(shift_now) - sr <= {rx_d2,sr[7:1]}; - - always @(posedge clk) - if(rst) - baud_ctr <= 0; - else - if(go_now) - baud_ctr <= 1; - else if(stop_now) - baud_ctr <= 0; - else if(baud_ctr >= clkdiv) - baud_ctr <= 1; - else if(baud_ctr != 0) - baud_ctr <= baud_ctr + 1; - - always @(posedge clk) - if(rst) - bit_ctr <= 0; - else - if(go_now) - bit_ctr <= 1; - else if(stop_now) - bit_ctr <= 0; - else if(baud_ctr == clkdiv) - bit_ctr <= bit_ctr + 1; - - wire full; - wire write = ~full & rx_d2 & stop_now; - - medfifo #(.WIDTH(8),.DEPTH(DEPTH)) fifo - (.clk(clk),.rst(rst), - .datain(sr),.write(write),.full(full), - .dataout(fifo_out),.read(fifo_read),.empty(fifo_empty), - .clear(0),.space(),.occupied(fifo_level) ); - -endmodule // simple_uart_rx diff --git a/fpga/usrp2/control_lib/simple_uart_tx.v b/fpga/usrp2/control_lib/simple_uart_tx.v deleted file mode 100644 index f38460bd4..000000000 --- a/fpga/usrp2/control_lib/simple_uart_tx.v +++ /dev/null @@ -1,77 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module simple_uart_tx - #(parameter DEPTH=0) - (input clk, input rst, - input [7:0] fifo_in, input fifo_write, output [7:0] fifo_level, output fifo_full, - input [15:0] clkdiv, output baudclk, output reg tx); - - reg [15:0] baud_ctr; - reg [3:0] bit_ctr; - - wire read, empty; - wire [7:0] char_to_send; - - medfifo #(.WIDTH(8),.DEPTH(DEPTH)) fifo - (.clk(clk),.rst(rst), - .datain(fifo_in),.write(fifo_write),.full(fifo_full), - .dataout(char_to_send),.read(read),.empty(empty), - .clear(0),.space(fifo_level),.occupied() ); - - always @(posedge clk) - if(rst) - baud_ctr <= 0; - else if (baud_ctr >= clkdiv) - baud_ctr <= 0; - else - baud_ctr <= baud_ctr + 1; - - always @(posedge clk) - if(rst) - bit_ctr <= 0; - else if(baud_ctr == clkdiv) - if(bit_ctr == 9) - bit_ctr <= 0; - else if(bit_ctr != 0) - bit_ctr <= bit_ctr + 1; - else if(~empty) - bit_ctr <= 1; - - always @(posedge clk) - if(rst) - tx <= 1; - else - case(bit_ctr) - 0 : tx <= 1; - 1 : tx <= 0; - 2 : tx <= char_to_send[0]; - 3 : tx <= char_to_send[1]; - 4 : tx <= char_to_send[2]; - 5 : tx <= char_to_send[3]; - 6 : tx <= char_to_send[4]; - 7 : tx <= char_to_send[5]; - 8 : tx <= char_to_send[6]; - 9 : tx <= char_to_send[7]; - default : tx <= 1; - endcase // case(bit_ctr) - - assign read = (bit_ctr == 9) && (baud_ctr == clkdiv); - assign baudclk = (baud_ctr == 1); // Only for debug purposes - -endmodule // simple_uart_tx diff --git a/fpga/usrp2/control_lib/spi.v b/fpga/usrp2/control_lib/spi.v deleted file mode 100644 index 1abebee1c..000000000 --- a/fpga/usrp2/control_lib/spi.v +++ /dev/null @@ -1,101 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -// AD9510 Register Map (from datasheet Rev. A) - -/* INSTRUCTION word format (16 bits) - * 15 Read = 1, Write = 0 - * 14:13 W1/W0, Number of bytes 00 - 1, 01 - 2, 10 - 3, 11 - stream - * 12:0 Address - */ - -/* ADDR Contents Value (hex) - * 00 Serial Config Port 10 (def) -- MSB first, SDI/SDO separate - * 04 A Counter - * 05-06 B Counter - * 07-0A PLL Control - * 0B-0C R Divider - * 0D PLL Control - * 34-3A Fine Delay - * 3C-3F LVPECL Outs - * 40-43 LVDS/CMOS Outs - * 45 Clock select, power down - * 48-57 Dividers - * 58 Func and Sync - * 5A Update regs - */ - - -module spi - (input reset, - input clk, - - // SPI signals - output sen, - output sclk, - input sdi, - output sdo, - - // Interfaces - input read_1, - input write_1, - input [15:0] command_1, - input [15:0] wdata_1, - output [15:0] rdata_1, - output reg done_1, - input msb_first_1, - input [5:0] command_width_1, - input [5:0] data_width_1, - input [7:0] clkdiv_1 - - ); - - reg [15:0] command, wdata, rdata; - reg done; - - always @(posedge clk) - if(reset) - done_1 <= #1 1'b0; - - always @(posedge clk) - if(reset) - begin - counter <= #1 7'd0; - command <= #1 20'd0; - end - else if(start) - begin - counter <= #1 7'd1; - command <= #1 {read,w,addr_data}; - end - else if( |counter && ~done ) - begin - counter <= #1 counter + 7'd1; - if(~counter[0]) - command <= {command[22:0],1'b0}; - end - - wire done = (counter == 8'd49); - - assign sen = (done | counter == 8'd0); // CSB is high when we're not doing anything - assign sclk = ~counter[0]; - assign sdo = command[23]; - - -endmodule // clock_control diff --git a/fpga/usrp2/control_lib/srl.v b/fpga/usrp2/control_lib/srl.v deleted file mode 100644 index bdef30058..000000000 --- a/fpga/usrp2/control_lib/srl.v +++ /dev/null @@ -1,38 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module srl - #(parameter WIDTH=18) - (input clk, - input write, - input [WIDTH-1:0] in, - input [3:0] addr, - output [WIDTH-1:0] out); - - genvar i; - generate - for (i=0;i. -// - - - -// Source-synchronous receiver -// Assumes both clocks are at the same rate -// Relative clock phase is -// unknown -// variable -// bounded -// The output will come several cycles later than the input - -// This should synthesize efficiently in Xilinx distributed ram cells, -// which is why we use a buffer depth of 16 - -// FIXME Async reset on rxclk side? - -module ss_rcvr - #(parameter WIDTH=16) - (input rxclk, - input sysclk, - input rst, - - input [WIDTH-1:0] data_in, - output [WIDTH-1:0] data_out, - output reg clock_present); - - wire [3:0] rd_addr, wr_addr; - - // Distributed RAM - reg [WIDTH-1:0] buffer [0:15]; - always @(posedge rxclk) - buffer[wr_addr] <= data_in; - - assign data_out = buffer[rd_addr]; - - // Write address generation - reg [3:0] wr_counter; - always @(posedge rxclk or posedge rst) - if (rst) - wr_counter <= 0; - else - wr_counter <= wr_counter + 1; - - assign wr_addr = {wr_counter[3], ^wr_counter[3:2], ^wr_counter[2:1], ^wr_counter[1:0]}; - - // Read Address generation - wire [3:0] wr_ctr_sys, diff, abs_diff; - reg [3:0] wr_addr_sys_d1, wr_addr_sys_d2; - reg [3:0] rd_counter; - - assign rd_addr = {rd_counter[3], ^rd_counter[3:2], ^rd_counter[2:1], ^rd_counter[1:0]}; - - always @(posedge sysclk) - wr_addr_sys_d1 <= wr_addr; - - always @(posedge sysclk) - wr_addr_sys_d2 <= wr_addr_sys_d1; - - assign wr_ctr_sys = {wr_addr_sys_d2[3],^wr_addr_sys_d2[3:2],^wr_addr_sys_d2[3:1],^wr_addr_sys_d2[3:0]}; - - assign diff = wr_ctr_sys - rd_counter; - assign abs_diff = diff[3] ? (~diff+1) : diff; - - always @(posedge sysclk) - if(rst) - begin - clock_present <= 0; - rd_counter <= 0; - end - else - if(~clock_present) - if(abs_diff > 5) - clock_present <= 1; - else - ; - else - if(abs_diff<3) - clock_present <= 0; - else - rd_counter <= rd_counter + 1; - -endmodule // ss_rcvr diff --git a/fpga/usrp2/control_lib/system_control.v b/fpga/usrp2/control_lib/system_control.v deleted file mode 100644 index 7e7b71f3c..000000000 --- a/fpga/usrp2/control_lib/system_control.v +++ /dev/null @@ -1,64 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// System bootup order: -// 0 - Internal POR to reset this block. Maybe control it from CPLD in the future? -// 1 - Everything in reset -// 2 - Take RAM Loader out of reset -// 3 - When RAM Loader done, take processor and wishbone out of reset - -module system_control - (input wb_clk_i, - output reg ram_loader_rst_o, - output reg wb_rst_o, - input ram_loader_done_i - ); - - reg POR = 1'b1; - reg [3:0] POR_ctr; - - initial POR_ctr = 4'd0; - always @(posedge wb_clk_i) - if(POR_ctr == 4'd15) - POR <= 1'b0; - else - POR_ctr <= POR_ctr + 4'd1; - - always @(posedge POR or posedge wb_clk_i) - if(POR) - ram_loader_rst_o <= 1'b1; - else - ram_loader_rst_o <= #1 1'b0; - - // Main system reset - reg delayed_rst; - - always @(posedge POR or posedge wb_clk_i) - if(POR) - begin - wb_rst_o <= 1'b1; - delayed_rst <= 1'b1; - end - else if(ram_loader_done_i) - begin - delayed_rst <= 1'b0; - wb_rst_o <= delayed_rst; - end - -endmodule // system_control - - diff --git a/fpga/usrp2/control_lib/system_control_tb.v b/fpga/usrp2/control_lib/system_control_tb.v deleted file mode 100644 index 8fecfd1f0..000000000 --- a/fpga/usrp2/control_lib/system_control_tb.v +++ /dev/null @@ -1,74 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module system_control_tb(); - - reg aux_clk, clk_fpga; - wire wb_clk, dsp_clk; - wire wb_rst, dsp_rst, rl_rst, proc_rst; - - reg rl_done, clock_ready; - - initial aux_clk = 1'b0; - always #25 aux_clk = ~aux_clk; - - initial clk_fpga = 1'b0; - - initial clock_ready = 1'b0; - initial - begin - @(negedge proc_rst); - #1003 clock_ready <= 1'b1; - end - - always #7 clk_fpga = ~clk_fpga; - - initial begin - $dumpfile("system_control_tb.vcd"); - $dumpvars(0,system_control_tb); - end - - initial #10000 $finish; - - initial - begin - @(negedge rl_rst); - rl_done <= 1'b0; - #1325 rl_done <= 1'b1; - end - - initial - begin - @(negedge proc_rst); - clock_ready <= 1'b0; - #327 clock_ready <= 1'b1; - end - - system_control - system_control(.aux_clk_i(aux_clk),.clk_fpga_i(clk_fpga), - .dsp_clk_o(dsp_clk),.wb_clk_o(wb_clk), - .ram_loader_rst_o(rl_rst), - .processor_rst_o(proc_rst), - .wb_rst_o(wb_rst), - .dsp_rst_o(dsp_rst), - .ram_loader_done_i(rl_done), - .clock_ready_i(clock_ready), - .debug_o()); - -endmodule // system_control_tb diff --git a/fpga/usrp2/control_lib/traffic_cop.v b/fpga/usrp2/control_lib/traffic_cop.v deleted file mode 100644 index 874e4c2d9..000000000 --- a/fpga/usrp2/control_lib/traffic_cop.v +++ /dev/null @@ -1,42 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module traffic_cop(); - - -endmodule // traffic_cop - - - -/* - - Traffic Cop to control buffer pool - - Inputs - - Commands - - Basic Operations - - Outputs - - - - - - */ diff --git a/fpga/usrp2/control_lib/user_settings.v b/fpga/usrp2/control_lib/user_settings.v deleted file mode 100644 index d87f1de21..000000000 --- a/fpga/usrp2/control_lib/user_settings.v +++ /dev/null @@ -1,63 +0,0 @@ -// -// Copyright 2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// User settings bus -// -// Provides 8-bit address, 32-bit data write only bus for user settings, consumes to addresses in -// normal settings bus. -// -// Write user address to BASE -// Write user data to BASE+1 -// -// The user_set_stb will strobe after data write, must write new address even if same as previous one. - -module user_settings - #(parameter BASE=0) - (input clk, - input rst, - - input set_stb, - input [7:0] set_addr, - input [31:0] set_data, - - output set_stb_user, - output [7:0] set_addr_user, - output [31:0] set_data_user - ); - - wire addr_changed, data_changed; - reg stb_int; - - setting_reg #(.my_addr(BASE+0),.width(8)) sr_0 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(set_addr_user),.changed(addr_changed) ); - - setting_reg #(.my_addr(BASE+1)) sr_1 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(set_data_user),.changed(data_changed) ); - - always @(posedge clk) - if (rst|set_stb_user) - stb_int <= 0; - else - if (addr_changed) - stb_int <= 1; - - assign set_stb_user = stb_int & data_changed; - -endmodule // user_settings - diff --git a/fpga/usrp2/control_lib/v5icap_wb.v b/fpga/usrp2/control_lib/v5icap_wb.v deleted file mode 100644 index 92a6769e5..000000000 --- a/fpga/usrp2/control_lib/v5icap_wb.v +++ /dev/null @@ -1,71 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module v5icap_wb - (input clk, input reset, - input cyc_i, input stb_i, input we_i, output ack_o, - input [31:0] dat_i, output [31:0] dat_o); - - wire BUSY, CE, WRITE; - - reg [2:0] icap_state; - localparam ICAP_IDLE = 0; - localparam ICAP_WR0 = 1; - localparam ICAP_WR1 = 2; - localparam ICAP_RD0 = 3; - localparam ICAP_RD1 = 4; - - always @(posedge clk) - if(reset) - icap_state <= ICAP_IDLE; - else - case(icap_state) - ICAP_IDLE : - begin - if(stb_i & cyc_i) - if(we_i) - icap_state <= ICAP_WR0; - else - icap_state <= ICAP_RD0; - end - ICAP_WR0 : - icap_state <= ICAP_WR1; - ICAP_WR1 : - icap_state <= ICAP_IDLE; - ICAP_RD0 : - icap_state <= ICAP_RD1; - ICAP_RD1 : - icap_state <= ICAP_IDLE; - endcase // case (icap_state) - - assign WRITE = (icap_state == ICAP_WR0) | (icap_state == ICAP_WR1); - assign CE = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD0); - - assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1); - - ICAP_VIRTEX5 #(.ICAP_WIDTH("X32")) ICAP_VIRTEX5_inst - (.BUSY(BUSY), // Busy output - .O(dat_o), // 32-bit data output - .CE(~CE), // Clock enable input - .CLK(clk), // Clock input - .I(dat_i), // 32-bit data input - .WRITE(~WRITE) // Write input - ); - -endmodule // v5icap_wb diff --git a/fpga/usrp2/control_lib/wb_1master.v b/fpga/usrp2/control_lib/wb_1master.v deleted file mode 100644 index fb313efae..000000000 --- a/fpga/usrp2/control_lib/wb_1master.v +++ /dev/null @@ -1,464 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE Connection Bus Top Level //// -//// //// -//// //// -//// Original Author: Johny Chi //// -//// chisuhua@yahoo.com.cn //// -//// Modified By Matt Ettus, matt@ettus.com //// -//// //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000, 2007 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// Up to 8 slaves share a Wishbone Bus connection to 1 master - - module wb_1master - #(parameter decode_w = 8, // address decode width - parameter s0_addr = 8'h0, // slave 0 address - parameter s0_mask = 8'h0, // slave 0 don't cares - parameter s1_addr = 8'h0, // slave 1 address - parameter s1_mask = 8'h0, // slave 1 don't cares - parameter s2_addr = 8'h0, // slave 2 address - parameter s2_mask = 8'h0, // slave 2 don't cares - parameter s3_addr = 8'h0, // slave 3 address - parameter s3_mask = 8'h0, // slave 3 don't cares - parameter s4_addr = 8'h0, // slave 4 address - parameter s4_mask = 8'h0, // slave 4 don't cares - parameter s5_addr = 8'h0, // slave 5 address - parameter s5_mask = 8'h0, // slave 5 don't cares - parameter s6_addr = 8'h0, // slave 6 address - parameter s6_mask = 8'h0, // slave 6 don't cares - parameter s7_addr = 8'h0, // slave 7 address - parameter s7_mask = 8'h0, // slave 7 don't cares - parameter s8_addr = 8'h0, // slave 8 address - parameter s8_mask = 8'h0, // slave 8 don't cares - parameter s9_addr = 8'h0, // slave 9 address - parameter s9_mask = 8'h0, // slave 9 don't cares - parameter sa_addr = 8'h0, // slave a address - parameter sa_mask = 8'h0, // slave a don't cares - parameter sb_addr = 8'h0, // slave b address - parameter sb_mask = 8'h0, // slave b don't cares - parameter sc_addr = 8'h0, // slave c address - parameter sc_mask = 8'h0, // slave c don't cares - parameter sd_addr = 8'h0, // slave d address - parameter sd_mask = 8'h0, // slave d don't cares - parameter se_addr = 8'h0, // slave e address - parameter se_mask = 8'h0, // slave e don't cares - parameter sf_addr = 8'h0, // slave f address - parameter sf_mask = 8'h0, // slave f don't cares - - parameter dw = 32, // Data bus Width - parameter aw = 32, // Address bus Width - parameter sw = 4) // Number of Select Lines - - (input clk_i, - input rst_i, - - // Master Interface - input [dw-1:0] m0_dat_i, - output [dw-1:0] m0_dat_o, - input [aw-1:0] m0_adr_i, - input [sw-1:0] m0_sel_i, - input m0_we_i, - input m0_cyc_i, - input m0_stb_i, - output m0_ack_o, - output m0_err_o, - output m0_rty_o, - - // Slave Interfaces - input [dw-1:0] s0_dat_i, - output [dw-1:0] s0_dat_o, - output [aw-1:0] s0_adr_o, - output [sw-1:0] s0_sel_o, - output s0_we_o, - output s0_cyc_o, - output s0_stb_o, - input s0_ack_i, - input s0_err_i, - input s0_rty_i, - - input [dw-1:0] s1_dat_i, - output [dw-1:0] s1_dat_o, - output [aw-1:0] s1_adr_o, - output [sw-1:0] s1_sel_o, - output s1_we_o, - output s1_cyc_o, - output s1_stb_o, - input s1_ack_i, - input s1_err_i, - input s1_rty_i, - - input [dw-1:0] s2_dat_i, - output [dw-1:0] s2_dat_o, - output [aw-1:0] s2_adr_o, - output [sw-1:0] s2_sel_o, - output s2_we_o, - output s2_cyc_o, - output s2_stb_o, - input s2_ack_i, - input s2_err_i, - input s2_rty_i, - - input [dw-1:0] s3_dat_i, - output [dw-1:0] s3_dat_o, - output [aw-1:0] s3_adr_o, - output [sw-1:0] s3_sel_o, - output s3_we_o, - output s3_cyc_o, - output s3_stb_o, - input s3_ack_i, - input s3_err_i, - input s3_rty_i, - - input [dw-1:0] s4_dat_i, - output [dw-1:0] s4_dat_o, - output [aw-1:0] s4_adr_o, - output [sw-1:0] s4_sel_o, - output s4_we_o, - output s4_cyc_o, - output s4_stb_o, - input s4_ack_i, - input s4_err_i, - input s4_rty_i, - - input [dw-1:0] s5_dat_i, - output [dw-1:0] s5_dat_o, - output [aw-1:0] s5_adr_o, - output [sw-1:0] s5_sel_o, - output s5_we_o, - output s5_cyc_o, - output s5_stb_o, - input s5_ack_i, - input s5_err_i, - input s5_rty_i, - - input [dw-1:0] s6_dat_i, - output [dw-1:0] s6_dat_o, - output [aw-1:0] s6_adr_o, - output [sw-1:0] s6_sel_o, - output s6_we_o, - output s6_cyc_o, - output s6_stb_o, - input s6_ack_i, - input s6_err_i, - input s6_rty_i, - - input [dw-1:0] s7_dat_i, - output [dw-1:0] s7_dat_o, - output [aw-1:0] s7_adr_o, - output [sw-1:0] s7_sel_o, - output s7_we_o, - output s7_cyc_o, - output s7_stb_o, - input s7_ack_i, - input s7_err_i, - input s7_rty_i, - - input [dw-1:0] s8_dat_i, - output [dw-1:0] s8_dat_o, - output [aw-1:0] s8_adr_o, - output [sw-1:0] s8_sel_o, - output s8_we_o, - output s8_cyc_o, - output s8_stb_o, - input s8_ack_i, - input s8_err_i, - input s8_rty_i, - - input [dw-1:0] s9_dat_i, - output [dw-1:0] s9_dat_o, - output [aw-1:0] s9_adr_o, - output [sw-1:0] s9_sel_o, - output s9_we_o, - output s9_cyc_o, - output s9_stb_o, - input s9_ack_i, - input s9_err_i, - input s9_rty_i, - - input [dw-1:0] sa_dat_i, - output [dw-1:0] sa_dat_o, - output [aw-1:0] sa_adr_o, - output [sw-1:0] sa_sel_o, - output sa_we_o, - output sa_cyc_o, - output sa_stb_o, - input sa_ack_i, - input sa_err_i, - input sa_rty_i, - - input [dw-1:0] sb_dat_i, - output [dw-1:0] sb_dat_o, - output [aw-1:0] sb_adr_o, - output [sw-1:0] sb_sel_o, - output sb_we_o, - output sb_cyc_o, - output sb_stb_o, - input sb_ack_i, - input sb_err_i, - input sb_rty_i, - - input [dw-1:0] sc_dat_i, - output [dw-1:0] sc_dat_o, - output [aw-1:0] sc_adr_o, - output [sw-1:0] sc_sel_o, - output sc_we_o, - output sc_cyc_o, - output sc_stb_o, - input sc_ack_i, - input sc_err_i, - input sc_rty_i, - - input [dw-1:0] sd_dat_i, - output [dw-1:0] sd_dat_o, - output [aw-1:0] sd_adr_o, - output [sw-1:0] sd_sel_o, - output sd_we_o, - output sd_cyc_o, - output sd_stb_o, - input sd_ack_i, - input sd_err_i, - input sd_rty_i, - - input [dw-1:0] se_dat_i, - output [dw-1:0] se_dat_o, - output [aw-1:0] se_adr_o, - output [sw-1:0] se_sel_o, - output se_we_o, - output se_cyc_o, - output se_stb_o, - input se_ack_i, - input se_err_i, - input se_rty_i, - - input [dw-1:0] sf_dat_i, - output [dw-1:0] sf_dat_o, - output [aw-1:0] sf_adr_o, - output [sw-1:0] sf_sel_o, - output sf_we_o, - output sf_cyc_o, - output sf_stb_o, - input sf_ack_i, - input sf_err_i, - input sf_rty_i - ); - - // //////////////////////////////////////////////////////////////// - // - // Local wires - // - - wire [15:0] ssel_dec; - reg [dw-1:0] i_dat_s; // internal share bus , slave data to master - - // Master output Interface - assign m0_dat_o = i_dat_s; - - always @* - case(ssel_dec) - 1 : i_dat_s <= s0_dat_i; - 2 : i_dat_s <= s1_dat_i; - 4 : i_dat_s <= s2_dat_i; - 8 : i_dat_s <= s3_dat_i; - 16 : i_dat_s <= s4_dat_i; - 32 : i_dat_s <= s5_dat_i; - 64 : i_dat_s <= s6_dat_i; - 128 : i_dat_s <= s7_dat_i; - 256 : i_dat_s <= s8_dat_i; - 512 : i_dat_s <= s9_dat_i; - 1024 : i_dat_s <= sa_dat_i; - 2048 : i_dat_s <= sb_dat_i; - 4096 : i_dat_s <= sc_dat_i; - 8192 : i_dat_s <= sd_dat_i; - 16384 : i_dat_s <= se_dat_i; - 32768 : i_dat_s <= sf_dat_i; - default : i_dat_s <= s0_dat_i; - endcase // case(ssel_dec) - - assign {m0_ack_o, m0_err_o, m0_rty_o} - = {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i | - s8_ack_i | s9_ack_i | sa_ack_i | sb_ack_i | sc_ack_i | sd_ack_i | se_ack_i | sf_ack_i , - s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i | - s8_err_i | s9_err_i | sa_err_i | sb_err_i | sc_err_i | sd_err_i | se_err_i | sf_err_i , - s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i | - s8_rty_i | s9_rty_i | sa_rty_i | sb_rty_i | sc_rty_i | sd_rty_i | se_rty_i | sf_rty_i }; - - // Slave output interfaces - assign s0_adr_o = m0_adr_i; - assign s0_sel_o = m0_sel_i; - assign s0_dat_o = m0_dat_i; - assign s0_we_o = m0_we_i; - assign s0_cyc_o = m0_cyc_i; - assign s0_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[0]; - - assign s1_adr_o = m0_adr_i; - assign s1_sel_o = m0_sel_i; - assign s1_dat_o = m0_dat_i; - assign s1_we_o = m0_we_i; - assign s1_cyc_o = m0_cyc_i; - assign s1_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[1]; - - assign s2_adr_o = m0_adr_i; - assign s2_sel_o = m0_sel_i; - assign s2_dat_o = m0_dat_i; - assign s2_we_o = m0_we_i; - assign s2_cyc_o = m0_cyc_i; - assign s2_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[2]; - - assign s3_adr_o = m0_adr_i; - assign s3_sel_o = m0_sel_i; - assign s3_dat_o = m0_dat_i; - assign s3_we_o = m0_we_i; - assign s3_cyc_o = m0_cyc_i; - assign s3_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[3]; - - assign s4_adr_o = m0_adr_i; - assign s4_sel_o = m0_sel_i; - assign s4_dat_o = m0_dat_i; - assign s4_we_o = m0_we_i; - assign s4_cyc_o = m0_cyc_i; - assign s4_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[4]; - - assign s5_adr_o = m0_adr_i; - assign s5_sel_o = m0_sel_i; - assign s5_dat_o = m0_dat_i; - assign s5_we_o = m0_we_i; - assign s5_cyc_o = m0_cyc_i; - assign s5_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[5]; - - assign s6_adr_o = m0_adr_i; - assign s6_sel_o = m0_sel_i; - assign s6_dat_o = m0_dat_i; - assign s6_we_o = m0_we_i; - assign s6_cyc_o = m0_cyc_i; - assign s6_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[6]; - - assign s7_adr_o = m0_adr_i; - assign s7_sel_o = m0_sel_i; - assign s7_dat_o = m0_dat_i; - assign s7_we_o = m0_we_i; - assign s7_cyc_o = m0_cyc_i; - assign s7_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[7]; - - assign s8_adr_o = m0_adr_i; - assign s8_sel_o = m0_sel_i; - assign s8_dat_o = m0_dat_i; - assign s8_we_o = m0_we_i; - assign s8_cyc_o = m0_cyc_i; - assign s8_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[8]; - - assign s9_adr_o = m0_adr_i; - assign s9_sel_o = m0_sel_i; - assign s9_dat_o = m0_dat_i; - assign s9_we_o = m0_we_i; - assign s9_cyc_o = m0_cyc_i; - assign s9_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[9]; - - assign sa_adr_o = m0_adr_i; - assign sa_sel_o = m0_sel_i; - assign sa_dat_o = m0_dat_i; - assign sa_we_o = m0_we_i; - assign sa_cyc_o = m0_cyc_i; - assign sa_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[10]; - - assign sb_adr_o = m0_adr_i; - assign sb_sel_o = m0_sel_i; - assign sb_dat_o = m0_dat_i; - assign sb_we_o = m0_we_i; - assign sb_cyc_o = m0_cyc_i; - assign sb_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[11]; - - assign sc_adr_o = m0_adr_i; - assign sc_sel_o = m0_sel_i; - assign sc_dat_o = m0_dat_i; - assign sc_we_o = m0_we_i; - assign sc_cyc_o = m0_cyc_i; - assign sc_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[12]; - - assign sd_adr_o = m0_adr_i; - assign sd_sel_o = m0_sel_i; - assign sd_dat_o = m0_dat_i; - assign sd_we_o = m0_we_i; - assign sd_cyc_o = m0_cyc_i; - assign sd_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[13]; - - assign se_adr_o = m0_adr_i; - assign se_sel_o = m0_sel_i; - assign se_dat_o = m0_dat_i; - assign se_we_o = m0_we_i; - assign se_cyc_o = m0_cyc_i; - assign se_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[14]; - - assign sf_adr_o = m0_adr_i; - assign sf_sel_o = m0_sel_i; - assign sf_dat_o = m0_dat_i; - assign sf_we_o = m0_we_i; - assign sf_cyc_o = m0_cyc_i; - assign sf_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[15]; - - // Address decode logic - // WARNING -- must make sure these are mutually exclusive! - - - assign ssel_dec[0] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s0_addr) & s0_mask); - assign ssel_dec[1] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s1_addr) & s1_mask); - assign ssel_dec[2] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s2_addr) & s2_mask); - assign ssel_dec[3] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s3_addr) & s3_mask); - assign ssel_dec[4] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s4_addr) & s4_mask); - assign ssel_dec[5] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s5_addr) & s5_mask); - assign ssel_dec[6] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s6_addr) & s6_mask); - assign ssel_dec[7] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s7_addr) & s7_mask); - assign ssel_dec[8] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s8_addr) & s8_mask); - assign ssel_dec[9] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s9_addr) & s9_mask); - assign ssel_dec[10] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sa_addr) & sa_mask); - assign ssel_dec[11] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sb_addr) & sb_mask); - assign ssel_dec[12] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sc_addr) & sc_mask); - assign ssel_dec[13] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sd_addr) & sd_mask); - assign ssel_dec[14] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ se_addr) & se_mask); - assign ssel_dec[15] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sf_addr) & sf_mask); - -/* - assign ssel_dec[0] = (m0_adr_i[aw -1 : aw - decode_w ] == s0_addr); - assign ssel_dec[1] = (m0_adr_i[aw -1 : aw - decode_w ] == s1_addr); - assign ssel_dec[2] = (m0_adr_i[aw -1 : aw - decode_w ] == s2_addr); - assign ssel_dec[3] = (m0_adr_i[aw -1 : aw - decode_w ] == s3_addr); - assign ssel_dec[4] = (m0_adr_i[aw -1 : aw - decode_w ] == s4_addr); - assign ssel_dec[5] = (m0_adr_i[aw -1 : aw - decode_w ] == s5_addr); - assign ssel_dec[6] = (m0_adr_i[aw -1 : aw - decode_w ] == s6_addr); - assign ssel_dec[7] = (m0_adr_i[aw -1 : aw - decode_w ] == s7_addr); - assign ssel_dec[8] = (m0_adr_i[aw -1 : aw - decode_w ] == s8_addr); - assign ssel_dec[9] = (m0_adr_i[aw -1 : aw - decode_w ] == s9_addr); - assign ssel_dec[10] = (m0_adr_i[aw -1 : aw - decode_w ] == sa_addr); - assign ssel_dec[11] = (m0_adr_i[aw -1 : aw - decode_w ] == sb_addr); - assign ssel_dec[12] = (m0_adr_i[aw -1 : aw - decode_w ] == sc_addr); - assign ssel_dec[13] = (m0_adr_i[aw -1 : aw - decode_w ] == sd_addr); - assign ssel_dec[14] = (m0_adr_i[aw -1 : aw - decode_w ] == se_addr); - assign ssel_dec[15] = (m0_adr_i[aw -1 : aw - decode_w ] == sf_addr); - */ -endmodule // wb_1master diff --git a/fpga/usrp2/control_lib/wb_bridge_16_32.v b/fpga/usrp2/control_lib/wb_bridge_16_32.v deleted file mode 100644 index 7c62c9cbd..000000000 --- a/fpga/usrp2/control_lib/wb_bridge_16_32.v +++ /dev/null @@ -1,53 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module wb_bridge_16_32 - #(parameter AWIDTH=16) - (input wb_clk, input wb_rst, - input A_cyc_i, input A_stb_i, input A_we_i, input [3:0] A_sel_i, - input [AWIDTH-1:0] A_adr_i, input [31:0] A_dat_i, output [31:0] A_dat_o, output A_ack_o, - output B_cyc_o, output B_stb_o, output B_we_o, output [1:0] B_sel_o, - output [AWIDTH-1:0] B_adr_o, output [15:0] B_dat_o, input [15:0] B_dat_i, input B_ack_i - ); - - reg [15:0] holding; - reg phase; - - assign B_adr_o = {A_adr_i[AWIDTH-1:2],phase,1'b0}; - assign B_cyc_o = A_cyc_i; - assign B_stb_o = A_stb_i; - assign B_we_o = A_we_i; - - assign B_dat_o = ~phase ? A_dat_i[15:0] : A_dat_i[31:16]; - assign B_sel_o = ~phase ? A_sel_i[1:0] : A_sel_i[3:2]; - - assign A_dat_o = {B_dat_i,holding}; - assign A_ack_o = phase & B_ack_i; - - always @(posedge wb_clk) - if(wb_rst) - phase <= 0; - else if(B_ack_i) - phase <= ~phase; - - always @(posedge wb_clk) - if(~phase & B_ack_i) - holding <= B_dat_i; - -endmodule // wb_bridge_16_32 diff --git a/fpga/usrp2/control_lib/wb_bus_writer.v b/fpga/usrp2/control_lib/wb_bus_writer.v deleted file mode 100644 index 08e641d37..000000000 --- a/fpga/usrp2/control_lib/wb_bus_writer.v +++ /dev/null @@ -1,74 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// wb_bus_writer -// -// WB Bus Master device to send a sequence of single-word transactions -// based on a list in a RAM or ROM (FASM interface) -// ROM data format is {WB_ADDR[15:0],WB_DATA[31:0]} -// continues until it gets an all-1s entry - -module wb_bus_writer (input start, - output done, - output reg [15:0] rom_addr, - input [47:0] rom_data, - // WB Master Interface, don't need wb_dat_i - input wb_clk_i, - input wb_rst_i, - output [31:0] wb_dat_o, - input wb_ack_i, - output [15:0] wb_adr_o, - output wb_cyc_o, - output [3:0] wb_sel_o, - output wb_stb_o, - output wb_we_o - ); - -`define IDLE 0 -`define READ 1 - - reg [3:0] state; - - assign done = (state != `IDLE) && (&rom_data); // Done when we see all 1s - - always @(posedge wb_clk_i) - if(wb_rst_i) - begin - rom_addr <= #1 0; - state <= #1 0; - end - else if(start) - begin - rom_addr <= #1 0; - state <= #1 `READ; - end - else if((state == `READ) && wb_ack_i) - if(done) - state <= #1 `IDLE; - else - rom_addr <= #1 rom_addr + 1; - - assign wb_dat_o = rom_data[31:0]; - assign wb_adr_o = rom_data[47:32]; - assign wb_sel_o = 4'b1111; // All writes are the full 32 bits - - assign wb_cyc_o = !done & (state != `IDLE); - assign wb_stb_o = !done & (state != `IDLE); - assign wb_we_o = !done & (state != `IDLE); - -endmodule // wb_bus_writer diff --git a/fpga/usrp2/control_lib/wb_output_pins32.v b/fpga/usrp2/control_lib/wb_output_pins32.v deleted file mode 100644 index 43e239797..000000000 --- a/fpga/usrp2/control_lib/wb_output_pins32.v +++ /dev/null @@ -1,66 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -// Simple 32-bit Wishbone compatible slave output port -// with 8-bit granularity, modeled after the one in the spec -// Allows for readback -// Assumes a 32-bit wishbone bus -// Lowest order bits get sel[0] -// - -module wb_output_pins32 - (wb_rst_i, wb_clk_i, wb_dat_i, wb_dat_o, - wb_we_i, wb_sel_i, wb_stb_i, wb_ack_o, wb_cyc_i, - port_output); - - input wb_rst_i; - input wb_clk_i; - input wire [31:0] wb_dat_i; - output wire [31:0] wb_dat_o; - input wb_we_i; - input wire [3:0] wb_sel_i; - input wb_stb_i; - output wb_ack_o; - input wb_cyc_i; - - output wire [31:0] port_output; - - reg [31:0] internal_reg; - - always @(posedge wb_clk_i) - if(wb_rst_i) - internal_reg <= #1 32'b0; - else - begin - if(wb_stb_i & wb_we_i & wb_sel_i[0]) - internal_reg[7:0] <= #1 wb_dat_i[7:0]; - if(wb_stb_i & wb_we_i & wb_sel_i[1]) - internal_reg[15:8] <= #1 wb_dat_i[15:8]; - if(wb_stb_i & wb_we_i & wb_sel_i[2]) - internal_reg[23:16] <= #1 wb_dat_i[23:16]; - if(wb_stb_i & wb_we_i & wb_sel_i[3]) - internal_reg[31:24] <= #1 wb_dat_i[31:24]; - end // else: !if(wb_rst_i) - - assign wb_dat_o = internal_reg; - assign port_output = internal_reg; - assign wb_ack_o = wb_stb_i; - -endmodule // wb_output_pins32 - diff --git a/fpga/usrp2/control_lib/wb_ram_block.v b/fpga/usrp2/control_lib/wb_ram_block.v deleted file mode 100644 index da6c610d3..000000000 --- a/fpga/usrp2/control_lib/wb_ram_block.v +++ /dev/null @@ -1,53 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -// Since this is a block ram, there are no byte-selects and there is a 1-cycle read latency -// These have to be a multiple of 512 lines (2K) long - -module wb_ram_block - #(parameter AWIDTH=9) - (input clk_i, - input stb_i, - input we_i, - input [AWIDTH-1:0] adr_i, - input [31:0] dat_i, - output reg [31:0] dat_o, - output ack_o); - - reg [31:0] distram [0:1<<(AWIDTH-1)]; - - always @(posedge clk_i) - begin - if(stb_i & we_i) - distram[adr_i] <= dat_i; - dat_o <= distram[adr_i]; - end - - reg stb_d1, ack_d1; - always @(posedge clk_i) - stb_d1 <= stb_i; - - always @(posedge clk_i) - ack_d1 <= ack_o; - - assign ack_o = stb_i & (we_i | (stb_d1 & ~ack_d1)); -endmodule // wb_ram_block - - - diff --git a/fpga/usrp2/control_lib/wb_ram_dist.v b/fpga/usrp2/control_lib/wb_ram_dist.v deleted file mode 100644 index 491a6ae11..000000000 --- a/fpga/usrp2/control_lib/wb_ram_dist.v +++ /dev/null @@ -1,50 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module wb_ram_dist - #(parameter AWIDTH=8) - (input clk_i, - input stb_i, - input we_i, - input [AWIDTH-1:0] adr_i, - input [31:0] dat_i, - input [3:0] sel_i, - output [31:0] dat_o, - output ack_o); - - reg [31:0] distram [0:1<<(AWIDTH-1)]; - - always @(posedge clk_i) - begin - if(stb_i & we_i & sel_i[3]) - distram[adr_i][31:24] <= dat_i[31:24]; - if(stb_i & we_i & sel_i[2]) - distram[adr_i][24:16] <= dat_i[24:16]; - if(stb_i & we_i & sel_i[1]) - distram[adr_i][15:8] <= dat_i[15:8]; - if(stb_i & we_i & sel_i[0]) - distram[adr_i][7:0] <= dat_i[7:0]; - end // always @ (posedge clk_i) - - assign dat_o = distram[adr_i]; - assign ack_o = stb_i; - -endmodule // wb_ram_dist - - diff --git a/fpga/usrp2/control_lib/wb_readback_mux.v b/fpga/usrp2/control_lib/wb_readback_mux.v deleted file mode 100644 index a5bf224b8..000000000 --- a/fpga/usrp2/control_lib/wb_readback_mux.v +++ /dev/null @@ -1,77 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -// Note -- clocks must be synchronous (derived from the same source) -// Assumes alt_clk is running at a multiple of wb_clk - -module wb_readback_mux - (input wb_clk_i, - input wb_rst_i, - input wb_stb_i, - input [15:0] wb_adr_i, - output reg [31:0] wb_dat_o, - output reg wb_ack_o, - - input [31:0] word00, - input [31:0] word01, - input [31:0] word02, - input [31:0] word03, - input [31:0] word04, - input [31:0] word05, - input [31:0] word06, - input [31:0] word07, - input [31:0] word08, - input [31:0] word09, - input [31:0] word10, - input [31:0] word11, - input [31:0] word12, - input [31:0] word13, - input [31:0] word14, - input [31:0] word15 - ); - - always @(posedge wb_clk_i) - if(wb_rst_i) - wb_ack_o <= 0; - else - wb_ack_o <= wb_stb_i & ~wb_ack_o; - - always @(posedge wb_clk_i) - case(wb_adr_i[5:2]) - 0 : wb_dat_o <= word00; - 1 : wb_dat_o <= word01; - 2 : wb_dat_o <= word02; - 3 : wb_dat_o <= word03; - 4 : wb_dat_o <= word04; - 5 : wb_dat_o <= word05; - 6 : wb_dat_o <= word06; - 7 : wb_dat_o <= word07; - 8 : wb_dat_o <= word08; - 9 : wb_dat_o <= word09; - 10: wb_dat_o <= word10; - 11: wb_dat_o <= word11; - 12: wb_dat_o <= word12; - 13: wb_dat_o <= word13; - 14: wb_dat_o <= word14; - 15: wb_dat_o <= word15; - endcase // case(addr_reg[3:0]) - -endmodule // wb_readback_mux - - diff --git a/fpga/usrp2/control_lib/wb_readback_mux_16LE.v b/fpga/usrp2/control_lib/wb_readback_mux_16LE.v deleted file mode 100644 index aceec601b..000000000 --- a/fpga/usrp2/control_lib/wb_readback_mux_16LE.v +++ /dev/null @@ -1,90 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -// Note -- clocks must be synchronous (derived from the same source) -// Assumes alt_clk is running at a multiple of wb_clk - -// Note -- assumes that the lower-16 bits will be requested first, -// and that the upper-16 bit request will come immediately after. - -module wb_readback_mux_16LE - (input wb_clk_i, - input wb_rst_i, - input wb_stb_i, - input [15:0] wb_adr_i, - output [15:0] wb_dat_o, - output reg wb_ack_o, - - input [31:0] word00, - input [31:0] word01, - input [31:0] word02, - input [31:0] word03, - input [31:0] word04, - input [31:0] word05, - input [31:0] word06, - input [31:0] word07, - input [31:0] word08, - input [31:0] word09, - input [31:0] word10, - input [31:0] word11, - input [31:0] word12, - input [31:0] word13, - input [31:0] word14, - input [31:0] word15 - ); - - wire ack_next = wb_stb_i & ~wb_ack_o; - - always @(posedge wb_clk_i) - if(wb_rst_i) - wb_ack_o <= 0; - else - wb_ack_o <= ack_next; - - reg [31:0] data; - assign wb_dat_o = data[15:0]; - - always @(posedge wb_clk_i) - if (wb_adr_i[1] & ack_next) begin //upper half - data[15:0] <= data[31:16]; - end - else if (~wb_adr_i[1] & ack_next) begin //lower half - case(wb_adr_i[5:2]) - 0 : data <= word00; - 1 : data <= word01; - 2 : data <= word02; - 3 : data <= word03; - 4 : data <= word04; - 5 : data <= word05; - 6 : data <= word06; - 7 : data <= word07; - 8 : data <= word08; - 9 : data <= word09; - 10: data <= word10; - 11: data <= word11; - 12: data <= word12; - 13: data <= word13; - 14: data <= word14; - 15: data <= word15; - endcase // case(wb_adr_i[5:2]) - end - -endmodule // wb_readback_mux - - diff --git a/fpga/usrp2/control_lib/wb_regfile_2clock.v b/fpga/usrp2/control_lib/wb_regfile_2clock.v deleted file mode 100644 index ce93ab3f4..000000000 --- a/fpga/usrp2/control_lib/wb_regfile_2clock.v +++ /dev/null @@ -1,124 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module wb_regfile_2clock - (input wb_clk_i, - input wb_rst_i, - input wb_stb_i, - input wb_we_i, - input [15:0] wb_adr_i, - input [3:0] wb_sel_i, - input [31:0] wb_dat_i, - output [31:0] wb_dat_o, - output wb_ack_o, - input alt_clk, - input alt_rst, - - output reg [31:0] reg00, - output reg [31:0] reg01, - output reg [31:0] reg02, - output reg [31:0] reg03, - output reg [31:0] reg04, - output reg [31:0] reg05, - output reg [31:0] reg06, - output reg [31:0] reg07 - ); - - reg [15:0] addr_reg; - reg [3:0] sel_reg; - reg [31:0] dat_reg; - reg wr_ret1, wr_ret2, we_reg, stb_reg; - - always @(posedge wb_clk_i) - if(wb_rst_i) - begin - addr_reg <= 0; - sel_reg <= 0; - dat_reg <= 0; - end - else if(wb_stb_i & wb_we_i) - begin - addr_reg <= wb_adr_i; - sel_reg <= wb_sel_i; - dat_reg <= wb_dat_i; - end - - always @(posedge wb_clk_i) - if(wb_rst_i) - {we_reg,stb_reg} <= 2'b0; - else - {we_reg,stb_reg} <= {wb_we_i,wb_stb_i}; - - assign wb_ack_o = stb_reg; - - always @(posedge alt_clk) - if(alt_rst) - {wr_ret2, wr_ret1} <= 2'b0; - else - {wr_ret2, wr_ret1} <= {wr_ret1, we_reg & stb_reg}; - - always @(posedge alt_clk) - if(alt_rst) - begin - reg00 <= 0; - reg01 <= 0; - reg02 <= 0; - reg03 <= 0; - reg04 <= 0; - reg05 <= 0; - reg06 <= 0; - reg07 <= 0; - end // if (alt_rst) - else if(wr_ret2) - case(addr_reg[4:2]) - 3'd0: reg00 <= { {sel_reg[3] ? dat_reg[31:24] : reg00[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg00[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg00[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg00[7:0]}}; - 3'd1: reg01 <= { {sel_reg[3] ? dat_reg[31:24] : reg01[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg01[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg01[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg01[7:0]}}; - 3'd2: reg02 <= { {sel_reg[3] ? dat_reg[31:24] : reg02[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg02[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg02[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg02[7:0]}}; - 3'd3: reg03 <= { {sel_reg[3] ? dat_reg[31:24] : reg03[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg03[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg03[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg03[7:0]}}; - 3'd4: reg04 <= { {sel_reg[3] ? dat_reg[31:24] : reg04[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg04[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg04[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg04[7:0]}}; - 3'd5: reg05 <= { {sel_reg[3] ? dat_reg[31:24] : reg05[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg05[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg05[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg05[7:0]}}; - 3'd6: reg06 <= { {sel_reg[3] ? dat_reg[31:24] : reg06[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg06[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg06[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg06[7:0]}}; - 3'd7: reg07 <= { {sel_reg[3] ? dat_reg[31:24] : reg07[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg07[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg07[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg07[7:0]}}; - endcase // case(addr_reg[2:0]) - -endmodule // wb_regfile_2clock - diff --git a/fpga/usrp2/control_lib/wb_semaphore.v b/fpga/usrp2/control_lib/wb_semaphore.v deleted file mode 100644 index e90950509..000000000 --- a/fpga/usrp2/control_lib/wb_semaphore.v +++ /dev/null @@ -1,59 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// up to 8 semaphores - -// After a read operation, the semaphore is always locked -// If it was already locked before the read (meaning someone else holds the lock) -// then a 1 is returned -// If it was not already locked (meaning the reader now holds the lock) -// then a 0 is returned - -// A write operation clears the lock - -module wb_semaphore - #(parameter count=8, DBUS_WIDTH=32) - (input wb_clk_i, - input wb_rst_i, - input [DBUS_WIDTH-1:0] wb_dat_i, - input [2:0] wb_adr_i, - input wb_cyc_i, - input wb_stb_i, - input wb_we_i, - output wb_ack_o, - output [DBUS_WIDTH-1:0] wb_dat_o); - - reg [count-1:0] locked; - - always @(posedge clock) - if(wb_rst_i) - locked <= {count{1'b0}}; - else if(wb_stb_i) - if(wb_we_i) - locked[adr_i] <= 1'b0; - else - locked[adr_i] <= 1'b1; - - assign wb_dat_o[DBUS_WIDTH-1:1] = {(DBUS_WIDTH-1){1'b0}}; - assign wb_dat_o[0] = locked[adr_i]; - assign wb_ack_o = wb_stb_i; - - -endmodule // wb_semaphore - - diff --git a/fpga/usrp2/control_lib/wb_sim.v b/fpga/usrp2/control_lib/wb_sim.v deleted file mode 100644 index 9f2fbea54..000000000 --- a/fpga/usrp2/control_lib/wb_sim.v +++ /dev/null @@ -1,96 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module wb_sim(); - - wire wb_clk, wb_rst; - wire start; - - reg POR, aux_clk, clk_fpga; - - initial POR = 1'b1; - initial #103 POR = 1'b0; - - initial aux_clk = 1'b0; - always #25 aux_clk = ~aux_clk; - - initial clk_fpga = 1'bx; - initial #3007 clk_fpga = 1'b0; - always #7 clk_fpga = ~clk_fpga; - - initial begin - $dumpfile("wb_sim.vcd"); - $dumpvars(0,wb_sim); - end - - initial #10000 $finish; - - wire [15:0] rom_addr; - wire [47:0] rom_data; - wire [31:0] wb_dat; - wire [15:0] wb_adr; - wire wb_cyc,wb_stb,wb_we,wb_ack; - wire [3:0] wb_sel; - - wire [31:0] port_output; - - - system_control system_control(.dsp_clk(dsp_clk), - .reset_out(reset_out), - .wb_clk_o(wb_clk), - .wb_rst_o(wb_rst), - .wb_rst_o_alt(wb_rst_o_alt), - .start (start), - .aux_clk(aux_clk), - .clk_fpga(clk_fpga), - .POR (POR), - .done (done)); - - clock_bootstrap_rom cbrom(.addr(rom_addr),.data(rom_data)); - - wb_bus_writer bus_writer(.rom_addr (rom_addr[15:0]), - .wb_dat_o (wb_dat[31:0]), - .wb_adr_o (wb_adr[15:0]), - .wb_cyc_o (wb_cyc), - .wb_sel_o (wb_sel[3:0]), - .wb_stb_o (wb_stb), - .wb_we_o (wb_we), - .start (start), - .done (done), - .rom_data (rom_data[47:0]), - .wb_clk_i (wb_clk), - .wb_rst_i (wb_rst), - .wb_ack_i (wb_ack)); - - wb_output_pins32 output_pins(.wb_dat_o(), - .wb_ack_o(wb_ack), - .port_output(port_output[31:0]), - .wb_rst_i(wb_rst), - .wb_clk_i(wb_clk), - .wb_dat_i(wb_dat[31:0]), - .wb_we_i(wb_we), - .wb_sel_i(wb_sel[3:0]), - .wb_stb_i(wb_stb), - .wb_cyc_i(wb_cyc)); - - - - -endmodule // wb_sim - diff --git a/fpga/usrp2/coregen/.gitignore b/fpga/usrp2/coregen/.gitignore deleted file mode 100644 index 956cab52b..000000000 --- a/fpga/usrp2/coregen/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -/xlnx_auto* -/*log -/tmp diff --git a/fpga/usrp2/coregen/Makefile.srcs b/fpga/usrp2/coregen/Makefile.srcs deleted file mode 100644 index a3a5d826d..000000000 --- a/fpga/usrp2/coregen/Makefile.srcs +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright 2010 Ettus Research LLC -# - -################################################## -# Coregen Sources -################################################## -COREGEN_SRCS = $(abspath $(addprefix $(BASE_DIR)/../coregen/, \ -fifo_xlnx_2Kx36_2clk.v \ -fifo_xlnx_2Kx36_2clk.xco \ -fifo_xlnx_512x36_2clk.v \ -fifo_xlnx_512x36_2clk.xco \ -fifo_xlnx_64x36_2clk.v \ -fifo_xlnx_64x36_2clk.xco \ -fifo_xlnx_16x19_2clk.v \ -fifo_xlnx_16x19_2clk.xco \ -fifo_xlnx_16x40_2clk.v \ -fifo_xlnx_16x40_2clk.xco \ -fifo_xlnx_32x36_2clk.v \ -fifo_xlnx_32x36_2clk.xco \ -fifo_xlnx_512x36_2clk_36to18.v \ -fifo_xlnx_512x36_2clk_36to18.xco \ -fifo_xlnx_512x36_2clk_18to36.v \ -fifo_xlnx_512x36_2clk_18to36.xco \ -fifo_xlnx_512x36_2clk_prog_full.v \ -fifo_xlnx_512x36_2clk_prog_full.xco \ -)) diff --git a/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs b/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs deleted file mode 100644 index e7bbdb9d5..000000000 --- a/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs +++ /dev/null @@ -1,18 +0,0 @@ - - - - - - - - - - -Parsing Verilog file "/home/jblum/src/ettus/fpga_b200/usrp2/coregen/pll_100_40_75.v" into library work - - -Parsing Verilog file "/home/jblum/src/ettus/fpga_b200/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.v" into library work - - - - diff --git a/fpga/usrp2/coregen/coregen.cgp b/fpga/usrp2/coregen/coregen.cgp deleted file mode 100644 index dd85a7f50..000000000 --- a/fpga/usrp2/coregen/coregen.cgp +++ /dev/null @@ -1,22 +0,0 @@ -# Date: Fri Oct 15 07:50:19 2010 - -SET addpads = false -SET asysymbol = false -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc3s2000 -SET devicefamily = spartan3 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = fg456 -SET removerpms = false -SET simulationfiles = Structural -SET speedgrade = -5 -SET verilogsim = true -SET vhdlsim = false -SET workingdirectory = /tmp/ - -# CRC: 983b9b45 diff --git a/fpga/usrp2/coregen/coregen_s6.cgc b/fpga/usrp2/coregen/coregen_s6.cgc deleted file mode 100644 index 90b359eab..000000000 --- a/fpga/usrp2/coregen/coregen_s6.cgc +++ /dev/null @@ -1,2352 +0,0 @@ - - - xilinx.com - project - coregen_s6 - 1.0 - - - fifo_s6_1Kx36_2clk - - - fifo_s6_1Kx36_2clk - false - true - 1022 - 5 - 36 - 1024 - false - No_Programmable_Empty_Threshold - false - false - Independent_Clocks_Block_RAM - false - true - 1 - Active_High - 11 - false - 10 - 1024 - 0 - true - true - Active_High - Active_High - false - true - false - No_Programmable_Full_Threshold - false - 11 - Asynchronous_Reset - First_Word_Fall_Through - 1023 - true - false - false - 1 - Active_High - false - 4 - 36 - 1 - false - - - - - coregen_s6 - ./ - ./tmp/ - ./tmp/_cg/ - - - xc6slx75 - spartan6 - csg484 - -3 - - - BusFormatAngleBracketNotRipped - Verilog - true - Other - false - false - false - Ngc - false - - - Behavioral - Verilog - false - - - 2012-04-24+06:33 - - - - - - fifo_s6_2Kx36_2clk - - - fifo_s6_2Kx36_2clk - false - true - 2046 - 5 - 36 - 2048 - false - No_Programmable_Empty_Threshold - false - false - Independent_Clocks_Block_RAM - false - true - 1 - Active_High - 12 - false - 11 - 2048 - 0 - true - true - Active_High - Active_High - false - true - false - No_Programmable_Full_Threshold - false - 12 - Asynchronous_Reset - First_Word_Fall_Through - 2047 - true - false - false - 1 - Active_High - false - 4 - 36 - 1 - false - - - - - coregen_s6 - ./ - ./tmp/ - ./tmp/_cg/ - - - xc6slx75 - spartan6 - csg484 - -3 - - - BusFormatAngleBracketNotRipped - Verilog - true - Other - false - false - false - Ngc - false - - - Behavioral - Verilog - false - - - 2012-04-24+06:33 - - - - - - fifo_s6_512x36_2clk - - - fifo_s6_512x36_2clk - false - true - 510 - 5 - 36 - 512 - false - No_Programmable_Empty_Threshold - false - false - Independent_Clocks_Block_RAM - false - true - 1 - Active_High - 10 - false - 9 - 512 - 0 - true - true - Active_High - Active_High - false - true - false - No_Programmable_Full_Threshold - false - 10 - Asynchronous_Reset - First_Word_Fall_Through - 511 - true - false - false - 1 - Active_High - false - 4 - 36 - 1 - false - - - - - coregen_s6 - ./ - ./tmp/ - ./tmp/_cg/ - - - xc6slx75 - spartan6 - csg484 - -3 - - - BusFormatAngleBracketNotRipped - Verilog - true - Other - false - false - false - Ngc - false - - - Behavioral - Verilog - false - - - 2012-04-24+06:33 - - - - - - fifo_xlnx_16x19_2clk - - - fifo_xlnx_16x19_2clk - false - true - 14 - 5 - 19 - 16 - false - No_Programmable_Empty_Threshold - false - false - Independent_Clocks_Distributed_RAM - false - true - 1 - Active_High - 5 - 5 - 16 - 0 - true - Active_High - Active_High - false - true - false - No_Programmable_Full_Threshold - 5 - Asynchronous_Reset - First_Word_Fall_Through - 15 - true - false - false - 1 - Active_High - false - 4 - 19 - 1 - false - - - - - coregen_s6 - ./ - ./tmp/ - ./tmp/_cg/ - - - xc3s2000 - spartan3 - fg456 - -5 - - - BusFormatAngleBracketNotRipped - Verilog - false - Other - false - false - false - Ngc - false - - - Behavioral - Verilog - false - - - 2012-04-24+06:33 - - - - - - fifo_xlnx_16x40_2clk - - - fifo_xlnx_16x40_2clk - false - false - 14 - 5 - 40 - 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ignore - tcl - Mon Jun 25 01:22:04 GMT 2012 - 0x80B0E436 - generationID_4013899584 - - - ./pll_100_40_75/simulation/functional/simulate_isim.bat - ignore - unknown - Mon Jun 25 01:22:04 GMT 2012 - 0x3B0D2786 - generationID_4013899584 - - - ./pll_100_40_75/simulation/functional/simulate_isim.sh - ignore - unknown - Mon Jun 25 01:22:04 GMT 2012 - 0x3479DE2E - generationID_4013899584 - - - ./pll_100_40_75/simulation/functional/simulate_mti.bat - ignore - unknown - Mon Jun 25 01:22:04 GMT 2012 - 0x23E49D4C - generationID_4013899584 - - - ./pll_100_40_75/simulation/functional/simulate_mti.do - ignore - unknown - Mon Jun 25 01:22:04 GMT 2012 - 0x196566F3 - generationID_4013899584 - - - ./pll_100_40_75/simulation/functional/simulate_mti.sh - ignore - unknown - Mon Jun 25 01:22:04 GMT 2012 - 0xA92E962D - generationID_4013899584 - - - ./pll_100_40_75/simulation/functional/simulate_ncsim.sh - ignore - unknown - Mon Jun 25 01:22:04 GMT 2012 - 0x414DA0D8 - generationID_4013899584 - - - ./pll_100_40_75/simulation/functional/simulate_vcs.sh - ignore - unknown - Mon Jun 25 01:22:04 GMT 2012 - 0x040C0268 - generationID_4013899584 - - - ./pll_100_40_75/simulation/functional/ucli_commands.key - ignore - unknown - Mon Jun 25 01:22:04 GMT 2012 - 0x957E258B - generationID_4013899584 - - - ./pll_100_40_75/simulation/functional/vcs_session.tcl - ignore - tcl - Mon Jun 25 01:22:04 GMT 2012 - 0x859D76CE - generationID_4013899584 - - - ./pll_100_40_75/simulation/functional/wave.do - ignore - unknown - Mon Jun 25 01:22:04 GMT 2012 - 0xF6D99A50 - generationID_4013899584 - - - ./pll_100_40_75/simulation/functional/wave.sv - ignore - unknown - Mon Jun 25 01:22:04 GMT 2012 - 0x5BAF49BA - generationID_4013899584 - - - ./pll_100_40_75/simulation/pll_100_40_75_tb.v - ignore - verilog - Mon Jun 25 01:22:04 GMT 2012 - 0x338F9EC4 - generationID_4013899584 - - - ./pll_100_40_75/simulation/timing/pll_100_40_75_tb.v - ignore - verilog - Mon Jun 25 01:22:04 GMT 2012 - 0xF8A7FBD8 - generationID_4013899584 - - - ./pll_100_40_75/simulation/timing/sdf_cmd_file - ignore - unknown - Mon Jun 25 01:22:04 GMT 2012 - 0xE37E41C3 - generationID_4013899584 - - - ./pll_100_40_75/simulation/timing/simcmds.tcl - ignore - tcl - Mon Jun 25 01:22:04 GMT 2012 - 0x59F13085 - generationID_4013899584 - - - ./pll_100_40_75/simulation/timing/simulate_isim.sh - ignore - unknown - Mon Jun 25 01:22:04 GMT 2012 - 0x513F3CD7 - generationID_4013899584 - - - ./pll_100_40_75/simulation/timing/simulate_mti.bat - ignore - unknown - Mon Jun 25 01:22:04 GMT 2012 - 0x6032836B - generationID_4013899584 - - - ./pll_100_40_75/simulation/timing/simulate_mti.do - ignore - unknown - Mon Jun 25 01:22:04 GMT 2012 - 0x8556A6D6 - generationID_4013899584 - - - ./pll_100_40_75/simulation/timing/simulate_mti.sh - ignore - unknown - Mon Jun 25 01:22:04 GMT 2012 - 0xF19800C9 - generationID_4013899584 - - - ./pll_100_40_75/simulation/timing/simulate_ncsim.sh - ignore - unknown - Mon Jun 25 01:22:04 GMT 2012 - 0xEFFEEFB9 - generationID_4013899584 - - - ./pll_100_40_75/simulation/timing/simulate_vcs.sh - ignore - unknown - Mon Jun 25 01:22:04 GMT 2012 - 0xE87CCB6C - generationID_4013899584 - - - ./pll_100_40_75/simulation/timing/ucli_commands.key - ignore - unknown - Mon Jun 25 01:22:04 GMT 2012 - 0x9DC0E037 - generationID_4013899584 - - - ./pll_100_40_75/simulation/timing/vcs_session.tcl - ignore - tcl - Mon Jun 25 01:22:04 GMT 2012 - 0x28340249 - generationID_4013899584 - - - ./pll_100_40_75/simulation/timing/wave.do - ignore - unknown - Mon Jun 25 01:22:04 GMT 2012 - 0x251C4591 - generationID_4013899584 - - - ./pll_100_40_75.ucf - ignore - ucf - Mon Jun 25 01:22:04 GMT 2012 - 0x4904DEF4 - generationID_4013899584 - - - ./pll_100_40_75.v - verilog - Mon Jun 25 01:22:03 GMT 2012 - 0xF7DE77A9 - generationID_4013899584 - - - ./pll_100_40_75.veo - veo - Mon Jun 25 01:22:04 GMT 2012 - 0xC3431095 - generationID_4013899584 - - - ./pll_100_40_75.xdc - ignore - xdc - Mon Jun 25 01:22:04 GMT 2012 - 0x590C1CA7 - generationID_4013899584 - - - ./pll_100_40_75_xmdf.tcl - tcl - Mon Jun 25 01:22:04 GMT 2012 - 0x970F3026 - generationID_4013899584 - - - - all_documents_generator - - ./pll_100_40_75/doc/clk_wiz_gsg521.pdf - ignore - pdf - Mon Jun 25 01:22:08 GMT 2012 - 0x7660EFEE - generationID_4013899584 - - - ./pll_100_40_75/doc/clk_wiz_v3_5_readme.txt - ignore - txt - Mon Jun 25 01:22:08 GMT 2012 - 0x1BF90E4F - generationID_4013899584 - - - ./pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html - ignore - unknown - Mon Jun 25 01:22:08 GMT 2012 - 0xD0135075 - generationID_4013899584 - - - - readme_documents_generator - - ./pll_100_40_75/doc/clk_wiz_v3_5_readme.txt - ignore - txt - Mon Jun 25 01:22:09 GMT 2012 - 0x1BF90E4F - generationID_4013899584 - - - - asy_generator - - ./pll_100_40_75.asy - asy - Mon Jun 25 01:22:17 GMT 2012 - 0x61F47740 - generationID_4013899584 - - - - ise_generator - - ./_xmsgs/pn_parser.xmsgs - ignore - unknown - Mon Jun 25 01:22:24 GMT 2012 - 0xEDD97934 - generationID_4013899584 - - - ./pll_100_40_75.gise - ignore - gise - Mon Jun 25 01:22:25 GMT 2012 - 0x3AB6E652 - generationID_4013899584 - - - ./pll_100_40_75.xise - ignore - xise - Mon Jun 25 01:22:25 GMT 2012 - 0xAD3860B6 - generationID_4013899584 - - - - deliver_readme_generator - - - flist_generator - - ./pll_100_40_75_flist.txt - ignore - txtFlist - txt - Mon Jun 25 01:22:25 GMT 2012 - 0x4D0B8946 - generationID_4013899584 - - - - view_readme_generator - - - - - - - - - coregen_s6 - ./ - ./tmp/ - ./tmp/_cg/ - - - xc6slx75 - spartan6 - csg484 - -3 - - - BusFormatAngleBracketNotRipped - Verilog - true - Other - false - false - false - Ngc - false - - - Behavioral - Verilog - false - - - - - diff --git a/fpga/usrp2/coregen/coregen_s6.cgp b/fpga/usrp2/coregen/coregen_s6.cgp deleted file mode 100644 index 1abd1b021..000000000 --- a/fpga/usrp2/coregen/coregen_s6.cgp +++ /dev/null @@ -1,22 +0,0 @@ -# Date: Fri May 4 20:42:23 2012 - -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc6slx75 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = csg484 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -3 -SET verilogsim = true -SET vhdlsim = false -SET workingdirectory = ./tmp/ - -# CRC: f7d4ca66 diff --git a/fpga/usrp2/coregen/fifo_generator_release_notes.txt b/fpga/usrp2/coregen/fifo_generator_release_notes.txt deleted file mode 100644 index 554ec87f4..000000000 --- a/fpga/usrp2/coregen/fifo_generator_release_notes.txt +++ /dev/null @@ -1,160 +0,0 @@ -COPYRIGHT (c) 2006, 2007 XILINX, INC. -ALL RIGHTS RESERVED - -Core name : FIFO Generator -Version : v4.1 -Release Date : August 8, 2007 -File : fifo_generator_release_notes.txt - -Revision History -Date By Version Change Description -======================================================================== -09/2006 Xilinx, Inc. 3.2 Initial creation. -02/2007 Xilinx, Inc. 3.3 Revised for v3.3. -02/2007 Xilinx, Inc. 3.3 Revised for v3.3 rev 1. -08/2007 Xilinx, Inc. 3.4 Revised for v4.1. -======================================================================== - -INTRODUCTION -RELEASE NOTES - 1. General Core Design - 1.1 Enhancements - 1.2 Resolved Issues - 1.3 Outstanding Issues - 2. General Simulation - 2.1 Enhancements - 2.2 Resolved Issues - 2.3 Outstanding Issues - 3. Documentation - 3.1 Enhancements - 3.2 Resolved Issues - 3.3 Outstanding Issues -OTHER GENERAL INFORMATION -TECHNICAL SUPPORT - -======================================================================== - -INTRODUCTION -============ -Thank you using the FIFO Generator core from Xilinx! -In order to obtain the latest core updates and documentation, -please visit the Intellectual Property page located at: -http://www.xilinx.com/ipcenter/index.htm -This document contains the release notes for FIFO Generator v4.1 -which includes enhancements, resolved issues and outstanding known -issues. For release notes and known issues for CORE Generator 9.2i IP -Update 1 and FIFO Generator v4.1 please see Answer Record 25222. - -RELEASE NOTES -============= -This section lists any enhancements, resolved issues and outstanding -known issues. - - -1. General Core Design - 1.1 Enhancements - 1.1.1 Error Correction Checking (ECC) feature support for - Virtex-5 block RAM FIFO configurations - - 1.1.2 Full range data count widths now supported for non-symmetric - aspect ratio configurations - - 1.1.3 Option to define asynchronous reset value for full condition - flags (FULL, ALMOST_FULL, PROG_FULL). Applies to block RAM, - distributed RAM and shift RAM-based FIFO configurations only - - 1.1.4 Support added for use embedded output registers in block RAM - FIFO configurations (Virtex-4 and Virtex-5 only) - - 1.2 Resolved Issues - 1.2.1 Coregen GUI - For built-in FIFOs, GUI reports incorrect - number of built-in FIFO primitives used. - Change request: 4433738 - - 1.2.2 Programmable full flag is always asserted even when FIFO is - empty due to incorrect threshold setting. - Change request: 435835 - - 1.2.3 "ERROR:LIT:250 - Pins WEA0, WEA1, WEA2, WEA3 of RAMB16 symbol - .. , these pins should be connected to the same signal" occur - during MAP when targeting Virtex-4 and Virtex-5. - Change request: 338260 - - 1.2.4 Write Data Count and Read Data Count overestimate the number - of words written or read when core is configured with this - combination of options: First-Word-Fall-Through(FWFT), - accurate data count using extra logic, non-symmetric port - aspect ratio. - Change request: 436886 - - 1.2.5 SBITERR and DBITERR outputs are not driven in behavior - models. - Change request: 433637 - - 1.2.6 Maximum programmable empty threshold negate value is - incorrect. - Change request: 433921 - - 1.2.7 Programmable full flag behavior is incorrect when the - core is configured with this combination of options: - FWFT, non-symmetric port aspect ratio, single or - multiple programmable full threshold input port. - Change request: 435874 - - 1.2.8 Programmable empty flag stuck high when the core is - configured with this combination of options: block or - distributed RAM FIFO, single or multiple programmable - empty threshold input port. - Change request: 443569 - - 1.3 Outstanding Issues - 1.3.1 "WARNING:Ngdbuild:452 - logical net - 'u1/BU2/prog_*_thresh_assert<*>' has no driver" occur during - NgdBuild although programmable empty or full is not selected. - Warnings can be safely ignored. - Change request: 431975 - -2. General Simulation - 2.1 Enhancements - None at this time. - - 2.2 Resolved Issues - None at this time. - - 2.3 Outstanding Issues - 2.3.1 Ncelab warnings during Verilog structural and timing simulations - in ncsim for Virtex5 Block RAM FIFOs. - The simulations will be successful, but there will be warnings - similar to the following in the log file: "memory index out of - declared bounds" in simprims_ver_virtex5_source.v or - unisims_ver_virtex5_source.v. Cadence does not want to fix this - issue. These warning messages can safely be ignored. - Change request: 423374, 423375 - -3. Documentation - 3.1 Enhancements - 3.1.1 Added clarification on FIFO flag latency. - - 3.1.1 Added clarification on actual FIFO depth. - - 3.2 Resolved Issues - None at this time. - - 3.3 Outstanding Issues - None at this time. - - -TECHNICAL SUPPORT -================= -The fastest method for obtaining specific technical support for the -FIFO Generator core is through the http://support.xilinx.com/ -website. Questions are routed to a team of engineers with specific -expertise in using the FIFO Generator core. Xilinx will provide -technical support for use of this product as described in the FIFO -Generator Datasheet. Xilinx cannot guarantee timing, functionality, -or support of this product for designs that do not follow these -guidelines. - - - - diff --git a/fpga/usrp2/coregen/fifo_generator_ug175.pdf b/fpga/usrp2/coregen/fifo_generator_ug175.pdf deleted file mode 100644 index 5fba6029c..000000000 Binary files a/fpga/usrp2/coregen/fifo_generator_ug175.pdf and /dev/null differ diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.asy b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.asy deleted file mode 100644 index 9664f3a57..000000000 --- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.asy +++ /dev/null @@ -1,49 +0,0 @@ -Version 4 -SymbolType BLOCK -TEXT 32 32 LEFT 4 fifo_s6_1Kx36_2clk -RECTANGLE Normal 32 32 544 768 -LINE Wide 0 80 32 80 -PIN 0 80 LEFT 36 -PINATTR PinName din[35:0] -PINATTR Polarity IN -LINE Normal 0 144 32 144 -PIN 0 144 LEFT 36 -PINATTR PinName wr_en -PINATTR Polarity IN -LINE Normal 0 176 32 176 -PIN 0 176 LEFT 36 -PINATTR PinName wr_clk -PINATTR Polarity IN -LINE Normal 0 240 32 240 -PIN 0 240 LEFT 36 -PINATTR PinName rd_en -PINATTR Polarity IN -LINE Normal 0 272 32 272 -PIN 0 272 LEFT 36 -PINATTR PinName rd_clk -PINATTR Polarity IN -LINE Normal 144 800 144 768 -PIN 144 800 BOTTOM 36 -PINATTR PinName rst -PINATTR Polarity IN -LINE Wide 576 80 544 80 -PIN 576 80 RIGHT 36 -PINATTR PinName dout[35:0] -PINATTR Polarity OUT -LINE Normal 576 208 544 208 -PIN 576 208 RIGHT 36 -PINATTR PinName full -PINATTR Polarity OUT -LINE Wide 576 368 544 368 -PIN 576 368 RIGHT 36 -PINATTR PinName wr_data_count[10:0] -PINATTR Polarity OUT -LINE Normal 576 432 544 432 -PIN 576 432 RIGHT 36 -PINATTR PinName empty -PINATTR Polarity OUT -LINE Wide 576 592 544 592 -PIN 576 592 RIGHT 36 -PINATTR PinName rd_data_count[10:0] -PINATTR Polarity OUT - diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.gise b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.gise deleted file mode 100644 index 90240bfb2..000000000 --- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.gise +++ /dev/null @@ -1,31 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - - - - diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.ngc b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.ngc deleted file mode 100644 index f7e21b27e..000000000 --- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.v b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.v deleted file mode 100644 index 593d3f82c..000000000 --- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.v +++ /dev/null @@ -1,173 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2009 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file fifo_s6_1Kx36_2clk.v when simulating -// the core, fifo_s6_1Kx36_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module fifo_s6_1Kx36_2clk( - rst, - wr_clk, - rd_clk, - din, - wr_en, - rd_en, - dout, - full, - empty, - rd_data_count, - wr_data_count); - - -input rst; -input wr_clk; -input rd_clk; -input [35 : 0] din; -input wr_en; -input rd_en; -output [35 : 0] dout; -output full; -output empty; -output [10 : 0] rd_data_count; -output [10 : 0] wr_data_count; - -// synthesis translate_off - - FIFO_GENERATOR_V6_1 #( - .C_COMMON_CLOCK(0), - .C_COUNT_TYPE(0), - .C_DATA_COUNT_WIDTH(10), - .C_DEFAULT_VALUE("BlankString"), - .C_DIN_WIDTH(36), - .C_DOUT_RST_VAL("0"), - .C_DOUT_WIDTH(36), - .C_ENABLE_RLOCS(0), - .C_ENABLE_RST_SYNC(1), - .C_ERROR_INJECTION_TYPE(0), - .C_FAMILY("spartan6"), - .C_FULL_FLAGS_RST_VAL(1), - .C_HAS_ALMOST_EMPTY(0), - .C_HAS_ALMOST_FULL(0), - .C_HAS_BACKUP(0), - .C_HAS_DATA_COUNT(0), - .C_HAS_INT_CLK(0), - .C_HAS_MEMINIT_FILE(0), - .C_HAS_OVERFLOW(0), - .C_HAS_RD_DATA_COUNT(1), - .C_HAS_RD_RST(0), - .C_HAS_RST(1), - .C_HAS_SRST(0), - .C_HAS_UNDERFLOW(0), - .C_HAS_VALID(0), - .C_HAS_WR_ACK(0), - .C_HAS_WR_DATA_COUNT(1), - .C_HAS_WR_RST(0), - .C_IMPLEMENTATION_TYPE(2), - .C_INIT_WR_PNTR_VAL(0), - .C_MEMORY_TYPE(1), - .C_MIF_FILE_NAME("BlankString"), - .C_MSGON_VAL(1), - .C_OPTIMIZATION_MODE(0), - .C_OVERFLOW_LOW(0), - .C_PRELOAD_LATENCY(0), - .C_PRELOAD_REGS(1), - .C_PRIM_FIFO_TYPE("1kx36"), - .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), - .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), - .C_PROG_EMPTY_TYPE(0), - .C_PROG_FULL_THRESH_ASSERT_VAL(1023), - .C_PROG_FULL_THRESH_NEGATE_VAL(1022), - .C_PROG_FULL_TYPE(0), - .C_RD_DATA_COUNT_WIDTH(11), - .C_RD_DEPTH(1024), - .C_RD_FREQ(1), - .C_RD_PNTR_WIDTH(10), - .C_UNDERFLOW_LOW(0), - .C_USE_DOUT_RST(1), - .C_USE_ECC(0), - .C_USE_EMBEDDED_REG(0), - .C_USE_FIFO16_FLAGS(0), - .C_USE_FWFT_DATA_COUNT(1), - .C_VALID_LOW(0), - .C_WR_ACK_LOW(0), - .C_WR_DATA_COUNT_WIDTH(11), - .C_WR_DEPTH(1024), - .C_WR_FREQ(1), - .C_WR_PNTR_WIDTH(10), - .C_WR_RESPONSE_LATENCY(1)) - inst ( - .RST(rst), - .WR_CLK(wr_clk), - .RD_CLK(rd_clk), - .DIN(din), - .WR_EN(wr_en), - .RD_EN(rd_en), - .DOUT(dout), - .FULL(full), - .EMPTY(empty), - .RD_DATA_COUNT(rd_data_count), - .WR_DATA_COUNT(wr_data_count), - .BACKUP(), - .BACKUP_MARKER(), - .CLK(), - .SRST(), - .WR_RST(), - .RD_RST(), - .PROG_EMPTY_THRESH(), - .PROG_EMPTY_THRESH_ASSERT(), - .PROG_EMPTY_THRESH_NEGATE(), - .PROG_FULL_THRESH(), - .PROG_FULL_THRESH_ASSERT(), - .PROG_FULL_THRESH_NEGATE(), - .INT_CLK(), - .INJECTDBITERR(), - .INJECTSBITERR(), - .ALMOST_FULL(), - .WR_ACK(), - .OVERFLOW(), - .ALMOST_EMPTY(), - .VALID(), - .UNDERFLOW(), - .DATA_COUNT(), - .PROG_FULL(), - .PROG_EMPTY(), - .SBITERR(), - .DBITERR()); - - -// synthesis translate_on - -endmodule - diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.veo b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.veo deleted file mode 100644 index e348767a3..000000000 --- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.veo +++ /dev/null @@ -1,53 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2009 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fifo_s6_1Kx36_2clk YourInstanceName ( - .rst(rst), - .wr_clk(wr_clk), - .rd_clk(rd_clk), - .din(din), // Bus [35 : 0] - .wr_en(wr_en), - .rd_en(rd_en), - .dout(dout), // Bus [35 : 0] - .full(full), - .empty(empty), - .rd_data_count(rd_data_count), // Bus [10 : 0] - .wr_data_count(wr_data_count)); // Bus [10 : 0] - -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file fifo_s6_1Kx36_2clk.v when simulating -// the core, fifo_s6_1Kx36_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xco b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xco deleted file mode 100644 index 14ad27c2a..000000000 --- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xco +++ /dev/null @@ -1,84 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 12.1 -# Date: Fri May 4 20:49:07 2012 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc6slx75 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = csg484 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -3 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 6.1 -# END Select -# BEGIN Parameters -CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET component_name=fifo_s6_1Kx36_2clk -CSET data_count=false -CSET data_count_width=10 -CSET disable_timing_violations=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=4 -CSET empty_threshold_negate_value=5 -CSET enable_ecc=false -CSET enable_int_clk=false -CSET enable_reset_synchronization=true -CSET fifo_implementation=Independent_Clocks_Block_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=1023 -CSET full_threshold_negate_value=1022 -CSET inject_dbit_error=false -CSET inject_sbit_error=false -CSET input_data_width=36 -CSET input_depth=1024 -CSET output_data_width=36 -CSET output_depth=1024 -CSET overflow_flag=false -CSET overflow_sense=Active_High -CSET performance_options=First_Word_Fall_Through -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET read_clock_frequency=1 -CSET read_data_count=true -CSET read_data_count_width=11 -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET underflow_flag=false -CSET underflow_sense=Active_High -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=true -CSET valid_flag=false -CSET valid_sense=Active_High -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=true -CSET write_data_count_width=11 -# END Parameters -GENERATE -# CRC: 5f5a2e48 diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xise b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xise deleted file mode 100644 index b6109869c..000000000 --- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xise +++ /dev/null @@ -1,392 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_flist.txt deleted file mode 100644 index 4f5b34b9b..000000000 --- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_flist.txt +++ /dev/null @@ -1,13 +0,0 @@ -# Output products list for -_xmsgs/pn_parser.xmsgs -fifo_generator_ug175.pdf -fifo_s6_1Kx36_2clk.asy -fifo_s6_1Kx36_2clk.gise -fifo_s6_1Kx36_2clk.ngc -fifo_s6_1Kx36_2clk.v -fifo_s6_1Kx36_2clk.veo -fifo_s6_1Kx36_2clk.xco -fifo_s6_1Kx36_2clk.xise -fifo_s6_1Kx36_2clk_flist.txt -fifo_s6_1Kx36_2clk_readme.txt -fifo_s6_1Kx36_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_readme.txt deleted file mode 100644 index b101bd8cf..000000000 --- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_readme.txt +++ /dev/null @@ -1,51 +0,0 @@ -The following files were generated for 'fifo_s6_1Kx36_2clk' in directory -/home/matt/fpgapriv/usrp2/coregen/ - -fifo_generator_ug175.pdf: - Please see the core data sheet. - -fifo_s6_1Kx36_2clk.asy: - Graphical symbol information file. Used by the ISE tools and some - third party tools to create a symbol representing the core. - -fifo_s6_1Kx36_2clk.gise: - ISE Project Navigator support file. This is a generated file and should - not be edited directly. - -fifo_s6_1Kx36_2clk.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -fifo_s6_1Kx36_2clk.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -fifo_s6_1Kx36_2clk.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -fifo_s6_1Kx36_2clk.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -fifo_s6_1Kx36_2clk.xise: - ISE Project Navigator support file. This is a generated file and should - not be edited directly. - -fifo_s6_1Kx36_2clk_readme.txt: - Text file indicating the files generated and how they are used. - -fifo_s6_1Kx36_2clk_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - -fifo_s6_1Kx36_2clk_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. - diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_xmdf.tcl deleted file mode 100644 index f9a9ac233..000000000 --- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_xmdf.tcl +++ /dev/null @@ -1,72 +0,0 @@ -# The package naming convention is _xmdf -package provide fifo_s6_1Kx36_2clk_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::fifo_s6_1Kx36_2clk_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::fifo_s6_1Kx36_2clk_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_s6_1Kx36_2clk -} -# ::fifo_s6_1Kx36_2clk_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::fifo_s6_1Kx36_2clk_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.asy -utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_s6_1Kx36_2clk -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.asy b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.asy deleted file mode 100644 index 0b429a886..000000000 --- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.asy +++ /dev/null @@ -1,49 +0,0 @@ -Version 4 -SymbolType BLOCK -TEXT 32 32 LEFT 4 fifo_s6_2Kx36_2clk -RECTANGLE Normal 32 32 544 768 -LINE Wide 0 80 32 80 -PIN 0 80 LEFT 36 -PINATTR PinName din[35:0] -PINATTR Polarity IN -LINE Normal 0 144 32 144 -PIN 0 144 LEFT 36 -PINATTR PinName wr_en -PINATTR Polarity IN -LINE Normal 0 176 32 176 -PIN 0 176 LEFT 36 -PINATTR PinName wr_clk -PINATTR Polarity IN -LINE Normal 0 240 32 240 -PIN 0 240 LEFT 36 -PINATTR PinName rd_en -PINATTR Polarity IN -LINE Normal 0 272 32 272 -PIN 0 272 LEFT 36 -PINATTR PinName rd_clk -PINATTR Polarity IN -LINE Normal 144 800 144 768 -PIN 144 800 BOTTOM 36 -PINATTR PinName rst -PINATTR Polarity IN -LINE Wide 576 80 544 80 -PIN 576 80 RIGHT 36 -PINATTR PinName dout[35:0] -PINATTR Polarity OUT -LINE Normal 576 208 544 208 -PIN 576 208 RIGHT 36 -PINATTR PinName full -PINATTR Polarity OUT -LINE Wide 576 368 544 368 -PIN 576 368 RIGHT 36 -PINATTR PinName wr_data_count[11:0] -PINATTR Polarity OUT -LINE Normal 576 432 544 432 -PIN 576 432 RIGHT 36 -PINATTR PinName empty -PINATTR Polarity OUT -LINE Wide 576 592 544 592 -PIN 576 592 RIGHT 36 -PINATTR PinName rd_data_count[11:0] -PINATTR Polarity OUT - diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.gise b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.gise deleted file mode 100644 index d90a25595..000000000 --- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.gise +++ /dev/null @@ -1,31 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - - - - diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.ngc b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.ngc deleted file mode 100644 index 994b767ea..000000000 --- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.v b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.v deleted file mode 100644 index 9f2cc7d4e..000000000 --- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.v +++ /dev/null @@ -1,173 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2009 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file fifo_s6_2Kx36_2clk.v when simulating -// the core, fifo_s6_2Kx36_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module fifo_s6_2Kx36_2clk( - rst, - wr_clk, - rd_clk, - din, - wr_en, - rd_en, - dout, - full, - empty, - rd_data_count, - wr_data_count); - - -input rst; -input wr_clk; -input rd_clk; -input [35 : 0] din; -input wr_en; -input rd_en; -output [35 : 0] dout; -output full; -output empty; -output [11 : 0] rd_data_count; -output [11 : 0] wr_data_count; - -// synthesis translate_off - - FIFO_GENERATOR_V6_1 #( - .C_COMMON_CLOCK(0), - .C_COUNT_TYPE(0), - .C_DATA_COUNT_WIDTH(11), - .C_DEFAULT_VALUE("BlankString"), - .C_DIN_WIDTH(36), - .C_DOUT_RST_VAL("0"), - .C_DOUT_WIDTH(36), - .C_ENABLE_RLOCS(0), - .C_ENABLE_RST_SYNC(1), - .C_ERROR_INJECTION_TYPE(0), - .C_FAMILY("spartan6"), - .C_FULL_FLAGS_RST_VAL(1), - .C_HAS_ALMOST_EMPTY(0), - .C_HAS_ALMOST_FULL(0), - .C_HAS_BACKUP(0), - .C_HAS_DATA_COUNT(0), - .C_HAS_INT_CLK(0), - .C_HAS_MEMINIT_FILE(0), - .C_HAS_OVERFLOW(0), - .C_HAS_RD_DATA_COUNT(1), - .C_HAS_RD_RST(0), - .C_HAS_RST(1), - .C_HAS_SRST(0), - .C_HAS_UNDERFLOW(0), - .C_HAS_VALID(0), - .C_HAS_WR_ACK(0), - .C_HAS_WR_DATA_COUNT(1), - .C_HAS_WR_RST(0), - .C_IMPLEMENTATION_TYPE(2), - .C_INIT_WR_PNTR_VAL(0), - .C_MEMORY_TYPE(1), - .C_MIF_FILE_NAME("BlankString"), - .C_MSGON_VAL(1), - .C_OPTIMIZATION_MODE(0), - .C_OVERFLOW_LOW(0), - .C_PRELOAD_LATENCY(0), - .C_PRELOAD_REGS(1), - .C_PRIM_FIFO_TYPE("2kx18"), - .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), - .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), - .C_PROG_EMPTY_TYPE(0), - .C_PROG_FULL_THRESH_ASSERT_VAL(2047), - .C_PROG_FULL_THRESH_NEGATE_VAL(2046), - .C_PROG_FULL_TYPE(0), - .C_RD_DATA_COUNT_WIDTH(12), - .C_RD_DEPTH(2048), - .C_RD_FREQ(1), - .C_RD_PNTR_WIDTH(11), - .C_UNDERFLOW_LOW(0), - .C_USE_DOUT_RST(1), - .C_USE_ECC(0), - .C_USE_EMBEDDED_REG(0), - .C_USE_FIFO16_FLAGS(0), - .C_USE_FWFT_DATA_COUNT(1), - .C_VALID_LOW(0), - .C_WR_ACK_LOW(0), - .C_WR_DATA_COUNT_WIDTH(12), - .C_WR_DEPTH(2048), - .C_WR_FREQ(1), - .C_WR_PNTR_WIDTH(11), - .C_WR_RESPONSE_LATENCY(1)) - inst ( - .RST(rst), - .WR_CLK(wr_clk), - .RD_CLK(rd_clk), - .DIN(din), - .WR_EN(wr_en), - .RD_EN(rd_en), - .DOUT(dout), - .FULL(full), - .EMPTY(empty), - .RD_DATA_COUNT(rd_data_count), - .WR_DATA_COUNT(wr_data_count), - .BACKUP(), - .BACKUP_MARKER(), - .CLK(), - .SRST(), - .WR_RST(), - .RD_RST(), - .PROG_EMPTY_THRESH(), - .PROG_EMPTY_THRESH_ASSERT(), - .PROG_EMPTY_THRESH_NEGATE(), - .PROG_FULL_THRESH(), - .PROG_FULL_THRESH_ASSERT(), - .PROG_FULL_THRESH_NEGATE(), - .INT_CLK(), - .INJECTDBITERR(), - .INJECTSBITERR(), - .ALMOST_FULL(), - .WR_ACK(), - .OVERFLOW(), - .ALMOST_EMPTY(), - .VALID(), - .UNDERFLOW(), - .DATA_COUNT(), - .PROG_FULL(), - .PROG_EMPTY(), - .SBITERR(), - .DBITERR()); - - -// synthesis translate_on - -endmodule - diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.veo b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.veo deleted file mode 100644 index 7657f41bc..000000000 --- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.veo +++ /dev/null @@ -1,53 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2009 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fifo_s6_2Kx36_2clk YourInstanceName ( - .rst(rst), - .wr_clk(wr_clk), - .rd_clk(rd_clk), - .din(din), // Bus [35 : 0] - .wr_en(wr_en), - .rd_en(rd_en), - .dout(dout), // Bus [35 : 0] - .full(full), - .empty(empty), - .rd_data_count(rd_data_count), // Bus [11 : 0] - .wr_data_count(wr_data_count)); // Bus [11 : 0] - -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file fifo_s6_2Kx36_2clk.v when simulating -// the core, fifo_s6_2Kx36_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xco b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xco deleted file mode 100644 index 659795e5f..000000000 --- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xco +++ /dev/null @@ -1,84 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 12.1 -# Date: Fri May 4 20:55:54 2012 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc6slx75 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = csg484 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -3 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 6.1 -# END Select -# BEGIN Parameters -CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET component_name=fifo_s6_2Kx36_2clk -CSET data_count=false -CSET data_count_width=11 -CSET disable_timing_violations=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=4 -CSET empty_threshold_negate_value=5 -CSET enable_ecc=false -CSET enable_int_clk=false -CSET enable_reset_synchronization=true -CSET fifo_implementation=Independent_Clocks_Block_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=2047 -CSET full_threshold_negate_value=2046 -CSET inject_dbit_error=false -CSET inject_sbit_error=false -CSET input_data_width=36 -CSET input_depth=2048 -CSET output_data_width=36 -CSET output_depth=2048 -CSET overflow_flag=false -CSET overflow_sense=Active_High -CSET performance_options=First_Word_Fall_Through -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET read_clock_frequency=1 -CSET read_data_count=true -CSET read_data_count_width=12 -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET underflow_flag=false -CSET underflow_sense=Active_High -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=true -CSET valid_flag=false -CSET valid_sense=Active_High -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=true -CSET write_data_count_width=12 -# END Parameters -GENERATE -# CRC: e7a1c106 diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xise b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xise deleted file mode 100644 index c09cc4b35..000000000 --- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xise +++ /dev/null @@ -1,392 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_flist.txt deleted file mode 100644 index 3466e5f91..000000000 --- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_flist.txt +++ /dev/null @@ -1,13 +0,0 @@ -# Output products list for -_xmsgs/pn_parser.xmsgs -fifo_generator_ug175.pdf -fifo_s6_2Kx36_2clk.asy -fifo_s6_2Kx36_2clk.gise -fifo_s6_2Kx36_2clk.ngc -fifo_s6_2Kx36_2clk.v -fifo_s6_2Kx36_2clk.veo -fifo_s6_2Kx36_2clk.xco -fifo_s6_2Kx36_2clk.xise -fifo_s6_2Kx36_2clk_flist.txt -fifo_s6_2Kx36_2clk_readme.txt -fifo_s6_2Kx36_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_readme.txt deleted file mode 100644 index 3a017fbb0..000000000 --- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_readme.txt +++ /dev/null @@ -1,51 +0,0 @@ -The following files were generated for 'fifo_s6_2Kx36_2clk' in directory -/home/matt/fpgapriv/usrp2/coregen/ - -fifo_generator_ug175.pdf: - Please see the core data sheet. - -fifo_s6_2Kx36_2clk.asy: - Graphical symbol information file. Used by the ISE tools and some - third party tools to create a symbol representing the core. - -fifo_s6_2Kx36_2clk.gise: - ISE Project Navigator support file. This is a generated file and should - not be edited directly. - -fifo_s6_2Kx36_2clk.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -fifo_s6_2Kx36_2clk.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -fifo_s6_2Kx36_2clk.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -fifo_s6_2Kx36_2clk.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -fifo_s6_2Kx36_2clk.xise: - ISE Project Navigator support file. This is a generated file and should - not be edited directly. - -fifo_s6_2Kx36_2clk_readme.txt: - Text file indicating the files generated and how they are used. - -fifo_s6_2Kx36_2clk_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - -fifo_s6_2Kx36_2clk_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. - diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_xmdf.tcl deleted file mode 100644 index 63b4f2099..000000000 --- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_xmdf.tcl +++ /dev/null @@ -1,72 +0,0 @@ -# The package naming convention is _xmdf -package provide fifo_s6_2Kx36_2clk_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::fifo_s6_2Kx36_2clk_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::fifo_s6_2Kx36_2clk_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_s6_2Kx36_2clk -} -# ::fifo_s6_2Kx36_2clk_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::fifo_s6_2Kx36_2clk_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.asy -utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_s6_2Kx36_2clk -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.asy b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.asy deleted file mode 100644 index 5adf4bfb4..000000000 --- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.asy +++ /dev/null @@ -1,49 +0,0 @@ -Version 4 -SymbolType BLOCK -TEXT 32 32 LEFT 4 fifo_s6_512x36_2clk -RECTANGLE Normal 32 32 544 768 -LINE Wide 0 80 32 80 -PIN 0 80 LEFT 36 -PINATTR PinName din[35:0] -PINATTR Polarity IN -LINE Normal 0 144 32 144 -PIN 0 144 LEFT 36 -PINATTR PinName wr_en -PINATTR Polarity IN -LINE Normal 0 176 32 176 -PIN 0 176 LEFT 36 -PINATTR PinName wr_clk -PINATTR Polarity IN -LINE Normal 0 240 32 240 -PIN 0 240 LEFT 36 -PINATTR PinName rd_en -PINATTR Polarity IN -LINE Normal 0 272 32 272 -PIN 0 272 LEFT 36 -PINATTR PinName rd_clk -PINATTR Polarity IN -LINE Normal 144 800 144 768 -PIN 144 800 BOTTOM 36 -PINATTR PinName rst -PINATTR Polarity IN -LINE Wide 576 80 544 80 -PIN 576 80 RIGHT 36 -PINATTR PinName dout[35:0] -PINATTR Polarity OUT -LINE Normal 576 208 544 208 -PIN 576 208 RIGHT 36 -PINATTR PinName full -PINATTR Polarity OUT -LINE Wide 576 368 544 368 -PIN 576 368 RIGHT 36 -PINATTR PinName wr_data_count[9:0] -PINATTR Polarity OUT -LINE Normal 576 432 544 432 -PIN 576 432 RIGHT 36 -PINATTR PinName empty -PINATTR Polarity OUT -LINE Wide 576 592 544 592 -PIN 576 592 RIGHT 36 -PINATTR PinName rd_data_count[9:0] -PINATTR Polarity OUT - diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.gise b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.gise deleted file mode 100644 index 2edb1c020..000000000 --- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.gise +++ /dev/null @@ -1,31 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - - - - diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.ngc b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.ngc deleted file mode 100644 index 523080a69..000000000 --- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.v b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.v deleted file mode 100644 index 4b7a31173..000000000 --- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.v +++ /dev/null @@ -1,173 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2009 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file fifo_s6_512x36_2clk.v when simulating -// the core, fifo_s6_512x36_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module fifo_s6_512x36_2clk( - rst, - wr_clk, - rd_clk, - din, - wr_en, - rd_en, - dout, - full, - empty, - rd_data_count, - wr_data_count); - - -input rst; -input wr_clk; -input rd_clk; -input [35 : 0] din; -input wr_en; -input rd_en; -output [35 : 0] dout; -output full; -output empty; -output [9 : 0] rd_data_count; -output [9 : 0] wr_data_count; - -// synthesis translate_off - - FIFO_GENERATOR_V6_1 #( - .C_COMMON_CLOCK(0), - .C_COUNT_TYPE(0), - .C_DATA_COUNT_WIDTH(9), - .C_DEFAULT_VALUE("BlankString"), - .C_DIN_WIDTH(36), - .C_DOUT_RST_VAL("0"), - .C_DOUT_WIDTH(36), - .C_ENABLE_RLOCS(0), - .C_ENABLE_RST_SYNC(1), - .C_ERROR_INJECTION_TYPE(0), - .C_FAMILY("spartan6"), - .C_FULL_FLAGS_RST_VAL(1), - .C_HAS_ALMOST_EMPTY(0), - .C_HAS_ALMOST_FULL(0), - .C_HAS_BACKUP(0), - .C_HAS_DATA_COUNT(0), - .C_HAS_INT_CLK(0), - .C_HAS_MEMINIT_FILE(0), - .C_HAS_OVERFLOW(0), - .C_HAS_RD_DATA_COUNT(1), - .C_HAS_RD_RST(0), - .C_HAS_RST(1), - .C_HAS_SRST(0), - .C_HAS_UNDERFLOW(0), - .C_HAS_VALID(0), - .C_HAS_WR_ACK(0), - .C_HAS_WR_DATA_COUNT(1), - .C_HAS_WR_RST(0), - .C_IMPLEMENTATION_TYPE(2), - .C_INIT_WR_PNTR_VAL(0), - .C_MEMORY_TYPE(1), - .C_MIF_FILE_NAME("BlankString"), - .C_MSGON_VAL(1), - .C_OPTIMIZATION_MODE(0), - .C_OVERFLOW_LOW(0), - .C_PRELOAD_LATENCY(0), - .C_PRELOAD_REGS(1), - .C_PRIM_FIFO_TYPE("512x36"), - .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), - .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), - .C_PROG_EMPTY_TYPE(0), - .C_PROG_FULL_THRESH_ASSERT_VAL(511), - .C_PROG_FULL_THRESH_NEGATE_VAL(510), - .C_PROG_FULL_TYPE(0), - .C_RD_DATA_COUNT_WIDTH(10), - .C_RD_DEPTH(512), - .C_RD_FREQ(1), - .C_RD_PNTR_WIDTH(9), - .C_UNDERFLOW_LOW(0), - .C_USE_DOUT_RST(1), - .C_USE_ECC(0), - .C_USE_EMBEDDED_REG(0), - .C_USE_FIFO16_FLAGS(0), - .C_USE_FWFT_DATA_COUNT(1), - .C_VALID_LOW(0), - .C_WR_ACK_LOW(0), - .C_WR_DATA_COUNT_WIDTH(10), - .C_WR_DEPTH(512), - .C_WR_FREQ(1), - .C_WR_PNTR_WIDTH(9), - .C_WR_RESPONSE_LATENCY(1)) - inst ( - .RST(rst), - .WR_CLK(wr_clk), - .RD_CLK(rd_clk), - .DIN(din), - .WR_EN(wr_en), - .RD_EN(rd_en), - .DOUT(dout), - .FULL(full), - .EMPTY(empty), - .RD_DATA_COUNT(rd_data_count), - .WR_DATA_COUNT(wr_data_count), - .BACKUP(), - .BACKUP_MARKER(), - .CLK(), - .SRST(), - .WR_RST(), - .RD_RST(), - .PROG_EMPTY_THRESH(), - .PROG_EMPTY_THRESH_ASSERT(), - .PROG_EMPTY_THRESH_NEGATE(), - .PROG_FULL_THRESH(), - .PROG_FULL_THRESH_ASSERT(), - .PROG_FULL_THRESH_NEGATE(), - .INT_CLK(), - .INJECTDBITERR(), - .INJECTSBITERR(), - .ALMOST_FULL(), - .WR_ACK(), - .OVERFLOW(), - .ALMOST_EMPTY(), - .VALID(), - .UNDERFLOW(), - .DATA_COUNT(), - .PROG_FULL(), - .PROG_EMPTY(), - .SBITERR(), - .DBITERR()); - - -// synthesis translate_on - -endmodule - diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.veo b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.veo deleted file mode 100644 index 766965d02..000000000 --- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.veo +++ /dev/null @@ -1,53 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2009 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fifo_s6_512x36_2clk YourInstanceName ( - .rst(rst), - .wr_clk(wr_clk), - .rd_clk(rd_clk), - .din(din), // Bus [35 : 0] - .wr_en(wr_en), - .rd_en(rd_en), - .dout(dout), // Bus [35 : 0] - .full(full), - .empty(empty), - .rd_data_count(rd_data_count), // Bus [9 : 0] - .wr_data_count(wr_data_count)); // Bus [9 : 0] - -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file fifo_s6_512x36_2clk.v when simulating -// the core, fifo_s6_512x36_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xco b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xco deleted file mode 100644 index 4f40b8702..000000000 --- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xco +++ /dev/null @@ -1,84 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 12.1 -# Date: Fri May 4 20:46:48 2012 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc6slx75 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = csg484 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -3 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 6.1 -# END Select -# BEGIN Parameters -CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET component_name=fifo_s6_512x36_2clk -CSET data_count=false -CSET data_count_width=9 -CSET disable_timing_violations=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=4 -CSET empty_threshold_negate_value=5 -CSET enable_ecc=false -CSET enable_int_clk=false -CSET enable_reset_synchronization=true -CSET fifo_implementation=Independent_Clocks_Block_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=511 -CSET full_threshold_negate_value=510 -CSET inject_dbit_error=false -CSET inject_sbit_error=false -CSET input_data_width=36 -CSET input_depth=512 -CSET output_data_width=36 -CSET output_depth=512 -CSET overflow_flag=false -CSET overflow_sense=Active_High -CSET performance_options=First_Word_Fall_Through -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET read_clock_frequency=1 -CSET read_data_count=true -CSET read_data_count_width=10 -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET underflow_flag=false -CSET underflow_sense=Active_High -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=true -CSET valid_flag=false -CSET valid_sense=Active_High -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=true -CSET write_data_count_width=10 -# END Parameters -GENERATE -# CRC: a4cd75c3 diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xise b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xise deleted file mode 100644 index 9f43a161e..000000000 --- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xise +++ /dev/null @@ -1,392 +0,0 @@ - - - -

- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_s6_512x36_2clk_flist.txt deleted file mode 100644 index e72108931..000000000 --- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk_flist.txt +++ /dev/null @@ -1,13 +0,0 @@ -# Output products list for -_xmsgs/pn_parser.xmsgs -fifo_generator_ug175.pdf -fifo_s6_512x36_2clk.asy -fifo_s6_512x36_2clk.gise -fifo_s6_512x36_2clk.ngc -fifo_s6_512x36_2clk.v -fifo_s6_512x36_2clk.veo -fifo_s6_512x36_2clk.xco -fifo_s6_512x36_2clk.xise -fifo_s6_512x36_2clk_flist.txt -fifo_s6_512x36_2clk_readme.txt -fifo_s6_512x36_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_s6_512x36_2clk_readme.txt deleted file mode 100644 index 21f058c0b..000000000 --- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk_readme.txt +++ /dev/null @@ -1,51 +0,0 @@ -The following files were generated for 'fifo_s6_512x36_2clk' in directory -/home/matt/fpgapriv/usrp2/coregen/ - -fifo_generator_ug175.pdf: - Please see the core data sheet. - -fifo_s6_512x36_2clk.asy: - Graphical symbol information file. Used by the ISE tools and some - third party tools to create a symbol representing the core. - -fifo_s6_512x36_2clk.gise: - ISE Project Navigator support file. This is a generated file and should - not be edited directly. - -fifo_s6_512x36_2clk.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -fifo_s6_512x36_2clk.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -fifo_s6_512x36_2clk.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -fifo_s6_512x36_2clk.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -fifo_s6_512x36_2clk.xise: - ISE Project Navigator support file. This is a generated file and should - not be edited directly. - -fifo_s6_512x36_2clk_readme.txt: - Text file indicating the files generated and how they are used. - -fifo_s6_512x36_2clk_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - -fifo_s6_512x36_2clk_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. - diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_s6_512x36_2clk_xmdf.tcl deleted file mode 100644 index 150807984..000000000 --- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk_xmdf.tcl +++ /dev/null @@ -1,72 +0,0 @@ -# The package naming convention is _xmdf -package provide fifo_s6_512x36_2clk_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::fifo_s6_512x36_2clk_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::fifo_s6_512x36_2clk_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_s6_512x36_2clk -} -# ::fifo_s6_512x36_2clk_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::fifo_s6_512x36_2clk_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.asy -utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_s6_512x36_2clk -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.ngc deleted file mode 100644 index b12d34d7c..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.4e -$3f24g<,[o}e~g`n;"2*413&;$>"9 > %10?*nhel%fmyz cnpfc`h(|dz$Sni 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v deleted file mode 100644 index 1d633384b..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v +++ /dev/null @@ -1,169 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file fifo_xlnx_16x19_2clk.v when simulating -// the core, fifo_xlnx_16x19_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module fifo_xlnx_16x19_2clk( - din, - rd_clk, - rd_en, - rst, - wr_clk, - wr_en, - dout, - empty, - full, - rd_data_count, - wr_data_count); - - -input [18 : 0] din; -input rd_clk; -input rd_en; -input rst; -input wr_clk; -input wr_en; -output [18 : 0] dout; -output empty; -output full; -output [4 : 0] rd_data_count; -output [4 : 0] wr_data_count; - -// synthesis translate_off - - FIFO_GENERATOR_V4_3 #( - .C_COMMON_CLOCK(0), - .C_COUNT_TYPE(0), - .C_DATA_COUNT_WIDTH(5), - .C_DEFAULT_VALUE("BlankString"), - .C_DIN_WIDTH(19), - .C_DOUT_RST_VAL("0"), - .C_DOUT_WIDTH(19), - .C_ENABLE_RLOCS(0), - .C_FAMILY("spartan3"), - .C_FULL_FLAGS_RST_VAL(1), - .C_HAS_ALMOST_EMPTY(0), - .C_HAS_ALMOST_FULL(0), - .C_HAS_BACKUP(0), - .C_HAS_DATA_COUNT(0), - .C_HAS_INT_CLK(0), - .C_HAS_MEMINIT_FILE(0), - .C_HAS_OVERFLOW(0), - .C_HAS_RD_DATA_COUNT(1), - .C_HAS_RD_RST(0), - .C_HAS_RST(1), - .C_HAS_SRST(0), - .C_HAS_UNDERFLOW(0), - .C_HAS_VALID(0), - .C_HAS_WR_ACK(0), - .C_HAS_WR_DATA_COUNT(1), - .C_HAS_WR_RST(0), - .C_IMPLEMENTATION_TYPE(2), - .C_INIT_WR_PNTR_VAL(0), - .C_MEMORY_TYPE(2), - .C_MIF_FILE_NAME("BlankString"), - .C_MSGON_VAL(1), - .C_OPTIMIZATION_MODE(0), - .C_OVERFLOW_LOW(0), - .C_PRELOAD_LATENCY(0), - .C_PRELOAD_REGS(1), - .C_PRIM_FIFO_TYPE("512x36"), - .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), - .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), - .C_PROG_EMPTY_TYPE(0), - .C_PROG_FULL_THRESH_ASSERT_VAL(15), - .C_PROG_FULL_THRESH_NEGATE_VAL(14), - .C_PROG_FULL_TYPE(0), - .C_RD_DATA_COUNT_WIDTH(5), - .C_RD_DEPTH(16), - .C_RD_FREQ(1), - .C_RD_PNTR_WIDTH(4), - .C_UNDERFLOW_LOW(0), - .C_USE_DOUT_RST(1), - .C_USE_ECC(0), - .C_USE_EMBEDDED_REG(0), - .C_USE_FIFO16_FLAGS(0), - .C_USE_FWFT_DATA_COUNT(1), - .C_VALID_LOW(0), - .C_WR_ACK_LOW(0), - .C_WR_DATA_COUNT_WIDTH(5), - .C_WR_DEPTH(16), - .C_WR_FREQ(1), - .C_WR_PNTR_WIDTH(4), - .C_WR_RESPONSE_LATENCY(1)) - inst ( - .DIN(din), - .RD_CLK(rd_clk), - .RD_EN(rd_en), - .RST(rst), - .WR_CLK(wr_clk), - .WR_EN(wr_en), - .DOUT(dout), - .EMPTY(empty), - .FULL(full), - .RD_DATA_COUNT(rd_data_count), - .WR_DATA_COUNT(wr_data_count), - .CLK(), - .INT_CLK(), - .BACKUP(), - .BACKUP_MARKER(), - .PROG_EMPTY_THRESH(), - .PROG_EMPTY_THRESH_ASSERT(), - .PROG_EMPTY_THRESH_NEGATE(), - .PROG_FULL_THRESH(), - .PROG_FULL_THRESH_ASSERT(), - .PROG_FULL_THRESH_NEGATE(), - .RD_RST(), - .SRST(), - .WR_RST(), - .ALMOST_EMPTY(), - .ALMOST_FULL(), - .DATA_COUNT(), - .OVERFLOW(), - .PROG_EMPTY(), - .PROG_FULL(), - .VALID(), - .UNDERFLOW(), - .WR_ACK(), - .SBITERR(), - .DBITERR()); - - -// synthesis translate_on - -endmodule - diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.veo deleted file mode 100644 index 2e9af1efa..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.veo +++ /dev/null @@ -1,53 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fifo_xlnx_16x19_2clk YourInstanceName ( - .din(din), // Bus [18 : 0] - .rd_clk(rd_clk), - .rd_en(rd_en), - .rst(rst), - .wr_clk(wr_clk), - .wr_en(wr_en), - .dout(dout), // Bus [18 : 0] - .empty(empty), - .full(full), - .rd_data_count(rd_data_count), // Bus [4 : 0] - .wr_data_count(wr_data_count)); // Bus [4 : 0] - -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file fifo_xlnx_16x19_2clk.v when simulating -// the core, fifo_xlnx_16x19_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco deleted file mode 100644 index d0f638026..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco +++ /dev/null @@ -1,82 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version K.39 -# Date: Fri Sep 11 04:33:27 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = Verilog -SET device = xc3s2000 -SET devicefamily = spartan3 -SET flowvendor = Other -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = fg456 -SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -5 -SET verilogsim = True -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 4.3 -# END Select -# BEGIN Parameters -CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET component_name=fifo_xlnx_16x19_2clk -CSET data_count=false -CSET data_count_width=5 -CSET disable_timing_violations=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=4 -CSET empty_threshold_negate_value=5 -CSET enable_ecc=false -CSET enable_int_clk=false -CSET fifo_implementation=Independent_Clocks_Distributed_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=15 -CSET full_threshold_negate_value=14 -CSET input_data_width=19 -CSET input_depth=16 -CSET output_data_width=19 -CSET output_depth=16 -CSET overflow_flag=false -CSET overflow_sense=Active_High -CSET performance_options=First_Word_Fall_Through -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET read_clock_frequency=1 -CSET read_data_count=true -CSET read_data_count_width=5 -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET underflow_flag=false -CSET underflow_sense=Active_High -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=true -CSET valid_flag=false -CSET valid_sense=Active_High -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=true -CSET write_data_count_width=5 -# END Parameters -GENERATE -# CRC: 60b85dda - diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso deleted file mode 100644 index f1a6f7899..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso +++ /dev/null @@ -1,3 +0,0 @@ -blkmemdp_v6_2 -blk_mem_gen_v2_6 -fifo_generator_v4_3 diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt deleted file mode 100644 index ef33fff67..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +++ /dev/null @@ -1,103 +0,0 @@ - - - - - - -
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- - - diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_flist.txt deleted file mode 100644 index 5e1a6ed35..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_flist.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Output products list for -fifo_xlnx_16x19_2clk.ngc -fifo_xlnx_16x19_2clk.v -fifo_xlnx_16x19_2clk.veo -fifo_xlnx_16x19_2clk.xco -fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -fifo_xlnx_16x19_2clk_flist.txt -fifo_xlnx_16x19_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_readme.txt deleted file mode 100644 index 1b5976555..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_readme.txt +++ /dev/null @@ -1,39 +0,0 @@ -The following files were generated for 'fifo_xlnx_16x19_2clk' in directory -/home/matt/gnuradio.git/usrp2/fpga/coregen/: - -fifo_xlnx_16x19_2clk.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -fifo_xlnx_16x19_2clk.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -fifo_xlnx_16x19_2clk.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -fifo_xlnx_16x19_2clk.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: - Please see the core data sheet. - -fifo_xlnx_16x19_2clk_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - -fifo_xlnx_16x19_2clk_readme.txt: - Text file indicating the files generated and how they are used. - -fifo_xlnx_16x19_2clk_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. - diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl deleted file mode 100644 index 8d633e9c2..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl +++ /dev/null @@ -1,68 +0,0 @@ -# The package naming convention is _xmdf -package provide fifo_xlnx_16x19_2clk_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::fifo_xlnx_16x19_2clk_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::fifo_xlnx_16x19_2clk_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_16x19_2clk -} -# ::fifo_xlnx_16x19_2clk_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::fifo_xlnx_16x19_2clk_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_16x19_2clk -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.ngc deleted file mode 100644 index f42663419..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.4e -$2604g<,[o}e~g`n;"2*413&;$>"9 > %10?*nhel%fmyz cnpfc`h(|dz$Sni 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v deleted file mode 100644 index 8a08330d5..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v +++ /dev/null @@ -1,165 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file fifo_xlnx_16x40_2clk.v when simulating -// the core, fifo_xlnx_16x40_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module fifo_xlnx_16x40_2clk( - din, - rd_clk, - rd_en, - rst, - wr_clk, - wr_en, - dout, - empty, - full); - - -input [39 : 0] din; -input rd_clk; -input rd_en; -input rst; -input wr_clk; -input wr_en; -output [39 : 0] dout; -output empty; -output full; - -// synthesis translate_off - - FIFO_GENERATOR_V4_3 #( - .C_COMMON_CLOCK(0), - .C_COUNT_TYPE(0), - .C_DATA_COUNT_WIDTH(4), - .C_DEFAULT_VALUE("BlankString"), - .C_DIN_WIDTH(40), - .C_DOUT_RST_VAL("0"), - .C_DOUT_WIDTH(40), - .C_ENABLE_RLOCS(0), - .C_FAMILY("spartan3"), - .C_FULL_FLAGS_RST_VAL(1), - .C_HAS_ALMOST_EMPTY(0), - .C_HAS_ALMOST_FULL(0), - .C_HAS_BACKUP(0), - .C_HAS_DATA_COUNT(0), - .C_HAS_INT_CLK(0), - .C_HAS_MEMINIT_FILE(0), - .C_HAS_OVERFLOW(0), - .C_HAS_RD_DATA_COUNT(0), - .C_HAS_RD_RST(0), - .C_HAS_RST(1), - .C_HAS_SRST(0), - .C_HAS_UNDERFLOW(0), - .C_HAS_VALID(0), - .C_HAS_WR_ACK(0), - .C_HAS_WR_DATA_COUNT(0), - .C_HAS_WR_RST(0), - .C_IMPLEMENTATION_TYPE(2), - .C_INIT_WR_PNTR_VAL(0), - .C_MEMORY_TYPE(2), - .C_MIF_FILE_NAME("BlankString"), - .C_MSGON_VAL(1), - .C_OPTIMIZATION_MODE(0), - .C_OVERFLOW_LOW(0), - .C_PRELOAD_LATENCY(0), - .C_PRELOAD_REGS(1), - .C_PRIM_FIFO_TYPE("512x72"), - .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), - .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), - .C_PROG_EMPTY_TYPE(0), - .C_PROG_FULL_THRESH_ASSERT_VAL(15), - .C_PROG_FULL_THRESH_NEGATE_VAL(14), - .C_PROG_FULL_TYPE(0), - .C_RD_DATA_COUNT_WIDTH(4), - .C_RD_DEPTH(16), - .C_RD_FREQ(1), - .C_RD_PNTR_WIDTH(4), - .C_UNDERFLOW_LOW(0), - .C_USE_DOUT_RST(1), - .C_USE_ECC(0), - .C_USE_EMBEDDED_REG(0), - .C_USE_FIFO16_FLAGS(0), - .C_USE_FWFT_DATA_COUNT(0), - .C_VALID_LOW(0), - .C_WR_ACK_LOW(0), - .C_WR_DATA_COUNT_WIDTH(4), - .C_WR_DEPTH(16), - .C_WR_FREQ(1), - .C_WR_PNTR_WIDTH(4), - .C_WR_RESPONSE_LATENCY(1)) - inst ( - .DIN(din), - .RD_CLK(rd_clk), - .RD_EN(rd_en), - .RST(rst), - .WR_CLK(wr_clk), - .WR_EN(wr_en), - .DOUT(dout), - .EMPTY(empty), - .FULL(full), - .CLK(), - .INT_CLK(), - .BACKUP(), - .BACKUP_MARKER(), - .PROG_EMPTY_THRESH(), - .PROG_EMPTY_THRESH_ASSERT(), - .PROG_EMPTY_THRESH_NEGATE(), - .PROG_FULL_THRESH(), - .PROG_FULL_THRESH_ASSERT(), - .PROG_FULL_THRESH_NEGATE(), - .RD_RST(), - .SRST(), - .WR_RST(), - .ALMOST_EMPTY(), - .ALMOST_FULL(), - .DATA_COUNT(), - .OVERFLOW(), - .PROG_EMPTY(), - .PROG_FULL(), - .VALID(), - .RD_DATA_COUNT(), - .UNDERFLOW(), - .WR_ACK(), - .WR_DATA_COUNT(), - .SBITERR(), - .DBITERR()); - - -// synthesis translate_on - -endmodule - diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.veo deleted file mode 100644 index 684078e58..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.veo +++ /dev/null @@ -1,51 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fifo_xlnx_16x40_2clk YourInstanceName ( - .din(din), // Bus [39 : 0] - .rd_clk(rd_clk), - .rd_en(rd_en), - .rst(rst), - .wr_clk(wr_clk), - .wr_en(wr_en), - .dout(dout), // Bus [39 : 0] - .empty(empty), - .full(full)); - -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file fifo_xlnx_16x40_2clk.v when simulating -// the core, fifo_xlnx_16x40_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco deleted file mode 100644 index d0da5a6e8..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco +++ /dev/null @@ -1,82 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version K.39 -# Date: Tue May 11 20:27:53 2010 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = Verilog -SET device = xc3s2000 -SET devicefamily = spartan3 -SET flowvendor = Other -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = fg456 -SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -5 -SET verilogsim = True -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 4.3 -# END Select -# BEGIN Parameters -CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET component_name=fifo_xlnx_16x40_2clk -CSET data_count=false -CSET data_count_width=4 -CSET disable_timing_violations=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=4 -CSET empty_threshold_negate_value=5 -CSET enable_ecc=false -CSET enable_int_clk=false -CSET fifo_implementation=Independent_Clocks_Distributed_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=15 -CSET full_threshold_negate_value=14 -CSET input_data_width=40 -CSET input_depth=16 -CSET output_data_width=40 -CSET output_depth=16 -CSET overflow_flag=false -CSET overflow_sense=Active_High -CSET performance_options=First_Word_Fall_Through -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET read_clock_frequency=1 -CSET read_data_count=false -CSET read_data_count_width=4 -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET underflow_flag=false -CSET underflow_sense=Active_High -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=false -CSET valid_flag=false -CSET valid_sense=Active_High -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=false -CSET write_data_count_width=4 -# END Parameters -GENERATE -# CRC: 6bcb05e1 - diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt deleted file mode 100644 index 544bda31d..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +++ /dev/null @@ -1,98 +0,0 @@ - - - - - - -
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- - - -
- - - diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_flist.txt deleted file mode 100644 index c38f4e991..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_flist.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Output products list for -fifo_xlnx_16x40_2clk.ngc -fifo_xlnx_16x40_2clk.v -fifo_xlnx_16x40_2clk.veo -fifo_xlnx_16x40_2clk.xco -fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -fifo_xlnx_16x40_2clk_flist.txt -fifo_xlnx_16x40_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_readme.txt deleted file mode 100644 index bbcd4af79..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_readme.txt +++ /dev/null @@ -1,39 +0,0 @@ -The following files were generated for 'fifo_xlnx_16x40_2clk' in directory -/home/matt/sourcerepo/fpga/usrp2/coregen/: - -fifo_xlnx_16x40_2clk.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -fifo_xlnx_16x40_2clk.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -fifo_xlnx_16x40_2clk.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -fifo_xlnx_16x40_2clk.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: - Please see the core data sheet. - -fifo_xlnx_16x40_2clk_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - -fifo_xlnx_16x40_2clk_readme.txt: - Text file indicating the files generated and how they are used. - -fifo_xlnx_16x40_2clk_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. - diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_xmdf.tcl deleted file mode 100644 index 2b4824831..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_xmdf.tcl +++ /dev/null @@ -1,68 +0,0 @@ -# The package naming convention is _xmdf -package provide fifo_xlnx_16x40_2clk_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::fifo_xlnx_16x40_2clk_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::fifo_xlnx_16x40_2clk_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_16x40_2clk -} -# ::fifo_xlnx_16x40_2clk_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::fifo_xlnx_16x40_2clk_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_16x40_2clk -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.asy b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.asy deleted file mode 100644 index a87aa2f84..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.asy +++ /dev/null @@ -1,49 +0,0 @@ -Version 4 -SymbolType BLOCK -TEXT 32 32 LEFT 4 fifo_xlnx_2Kx36_2clk -RECTANGLE Normal 32 32 544 672 -LINE Wide 0 80 32 80 -PIN 0 80 LEFT 36 -PINATTR PinName din[35:0] -PINATTR Polarity IN -LINE Normal 0 144 32 144 -PIN 0 144 LEFT 36 -PINATTR PinName wr_en -PINATTR Polarity IN -LINE Normal 0 176 32 176 -PIN 0 176 LEFT 36 -PINATTR PinName wr_clk -PINATTR Polarity IN -LINE Normal 0 240 32 240 -PIN 0 240 LEFT 36 -PINATTR PinName rd_en -PINATTR Polarity IN -LINE Normal 0 272 32 272 -PIN 0 272 LEFT 36 -PINATTR PinName rd_clk -PINATTR Polarity IN -LINE Normal 144 704 144 672 -PIN 144 704 BOTTOM 36 -PINATTR PinName rst -PINATTR Polarity IN -LINE Wide 576 80 544 80 -PIN 576 80 RIGHT 36 -PINATTR PinName dout[35:0] -PINATTR Polarity OUT -LINE Normal 576 208 544 208 -PIN 576 208 RIGHT 36 -PINATTR PinName full -PINATTR Polarity OUT -LINE Wide 576 368 544 368 -PIN 576 368 RIGHT 36 -PINATTR PinName wr_data_count[11:0] -PINATTR Polarity OUT -LINE Normal 576 432 544 432 -PIN 576 432 RIGHT 36 -PINATTR PinName empty -PINATTR Polarity OUT -LINE Wide 576 592 544 592 -PIN 576 592 RIGHT 36 -PINATTR PinName rd_data_count[11:0] -PINATTR Polarity OUT - diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.ngc deleted file mode 100644 index 684eb74f4..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.4e -$7134g<,[o}e~g`n;"2*413&;$>"9 > %10?*nhel%fmyz cnpfc`h(|dz$Sni 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.sym b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.sym deleted file mode 100644 index 5d56b5c98..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.sym +++ /dev/null @@ -1,74 +0,0 @@ -VERSION 5 -BEGIN SYMBOL fifo_xlnx_2Kx36_2clk -SYMBOLTYPE BLOCK -TIMESTAMP 2009 9 3 17 25 13 -SYMPIN 0 80 Input din[35:0] -SYMPIN 0 144 Input wr_en -SYMPIN 0 176 Input wr_clk -SYMPIN 0 240 Input rd_en -SYMPIN 0 272 Input rd_clk -SYMPIN 144 704 Input rst -SYMPIN 576 80 Output dout[35:0] -SYMPIN 576 208 Output full -SYMPIN 576 368 Output wr_data_count[11:0] -SYMPIN 576 432 Output empty -SYMPIN 576 592 Output rd_data_count[11:0] -BEGIN DISPLAY 32 32 TEXT fifo_xlnx_2Kx36_2clk - FONT 40 "Arial" -END DISPLAY -RECTANGLE N 32 32 544 672 -BEGIN LINE W 0 80 32 80 -END LINE -BEGIN DISPLAY 36 80 PIN din[35:0] ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 144 32 144 -BEGIN DISPLAY 36 144 PIN wr_en ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 176 32 176 -BEGIN DISPLAY 36 176 PIN wr_clk ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 240 32 240 -BEGIN DISPLAY 36 240 PIN rd_en ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 272 32 272 -BEGIN DISPLAY 36 272 PIN rd_clk ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 144 704 144 672 -BEGIN DISPLAY 144 668 PIN rst ATTR PinName - ALIGNMENT BCENTER - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 576 80 544 80 -END LINE -BEGIN DISPLAY 540 80 PIN dout[35:0] ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -LINE N 576 208 544 208 -BEGIN DISPLAY 540 208 PIN full ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 576 368 544 368 -END LINE -BEGIN DISPLAY 540 368 PIN wr_data_count[11:0] ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -LINE N 576 432 544 432 -BEGIN DISPLAY 540 432 PIN empty ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 576 592 544 592 -END LINE -BEGIN DISPLAY 540 592 PIN rd_data_count[11:0] ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -END SYMBOL diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v deleted file mode 100644 index 0762b3ae9..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v +++ /dev/null @@ -1,173 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file fifo_xlnx_2Kx36_2clk.v when simulating -// the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module fifo_xlnx_2Kx36_2clk( - din, - rd_clk, - rd_en, - rst, - wr_clk, - wr_en, - dout, - empty, - full, - rd_data_count, - wr_data_count); - - -input [35 : 0] din; -input rd_clk; -input rd_en; -input rst; -input wr_clk; -input wr_en; -output [35 : 0] dout; -output empty; -output full; -output [11 : 0] rd_data_count; -output [11 : 0] wr_data_count; - -// synthesis translate_off - - FIFO_GENERATOR_V4_3 #( - .C_COMMON_CLOCK(0), - .C_COUNT_TYPE(0), - .C_DATA_COUNT_WIDTH(12), - .C_DEFAULT_VALUE("BlankString"), - .C_DIN_WIDTH(36), - .C_DOUT_RST_VAL("0"), - .C_DOUT_WIDTH(36), - .C_ENABLE_RLOCS(0), - .C_FAMILY("spartan3"), - .C_FULL_FLAGS_RST_VAL(1), - .C_HAS_ALMOST_EMPTY(0), - .C_HAS_ALMOST_FULL(0), - .C_HAS_BACKUP(0), - .C_HAS_DATA_COUNT(0), - .C_HAS_INT_CLK(0), - .C_HAS_MEMINIT_FILE(0), - .C_HAS_OVERFLOW(0), - .C_HAS_RD_DATA_COUNT(1), - .C_HAS_RD_RST(0), - .C_HAS_RST(1), - .C_HAS_SRST(0), - .C_HAS_UNDERFLOW(0), - .C_HAS_VALID(0), - .C_HAS_WR_ACK(0), - .C_HAS_WR_DATA_COUNT(1), - .C_HAS_WR_RST(0), - .C_IMPLEMENTATION_TYPE(2), - .C_INIT_WR_PNTR_VAL(0), - .C_MEMORY_TYPE(1), - .C_MIF_FILE_NAME("BlankString"), - .C_MSGON_VAL(1), - .C_OPTIMIZATION_MODE(0), - .C_OVERFLOW_LOW(0), - .C_PRELOAD_LATENCY(0), - .C_PRELOAD_REGS(1), - .C_PRIM_FIFO_TYPE("2kx18"), - .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), - .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), - .C_PROG_EMPTY_TYPE(0), - .C_PROG_FULL_THRESH_ASSERT_VAL(2047), - .C_PROG_FULL_THRESH_NEGATE_VAL(2046), - .C_PROG_FULL_TYPE(0), - .C_RD_DATA_COUNT_WIDTH(12), - .C_RD_DEPTH(2048), - .C_RD_FREQ(1), - .C_RD_PNTR_WIDTH(11), - .C_UNDERFLOW_LOW(0), - .C_USE_DOUT_RST(1), - .C_USE_ECC(0), - .C_USE_EMBEDDED_REG(0), - .C_USE_FIFO16_FLAGS(0), - .C_USE_FWFT_DATA_COUNT(1), - .C_VALID_LOW(0), - .C_WR_ACK_LOW(0), - .C_WR_DATA_COUNT_WIDTH(12), - .C_WR_DEPTH(2048), - .C_WR_FREQ(1), - .C_WR_PNTR_WIDTH(11), - .C_WR_RESPONSE_LATENCY(1)) - inst ( - .DIN(din), - .RD_CLK(rd_clk), - .RD_EN(rd_en), - .RST(rst), - .WR_CLK(wr_clk), - .WR_EN(wr_en), - .DOUT(dout), - .EMPTY(empty), - .FULL(full), - .RD_DATA_COUNT(rd_data_count), - .WR_DATA_COUNT(wr_data_count), - .CLK(), - .INT_CLK(), - .BACKUP(), - .BACKUP_MARKER(), - .PROG_EMPTY_THRESH(), - .PROG_EMPTY_THRESH_ASSERT(), - .PROG_EMPTY_THRESH_NEGATE(), - .PROG_FULL_THRESH(), - .PROG_FULL_THRESH_ASSERT(), - .PROG_FULL_THRESH_NEGATE(), - .RD_RST(), - .SRST(), - .WR_RST(), - .ALMOST_EMPTY(), - .ALMOST_FULL(), - .DATA_COUNT(), - .OVERFLOW(), - .PROG_EMPTY(), - .PROG_FULL(), - .VALID(), - .UNDERFLOW(), - .WR_ACK(), - .SBITERR(), - .DBITERR()); - - -// synthesis translate_on - -// XST black box declaration -// box_type "black_box" -// synthesis attribute box_type of fifo_xlnx_2Kx36_2clk is "black_box" - -endmodule - diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.veo deleted file mode 100644 index af9191555..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.veo +++ /dev/null @@ -1,53 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fifo_xlnx_2Kx36_2clk YourInstanceName ( - .din(din), // Bus [35 : 0] - .rd_clk(rd_clk), - .rd_en(rd_en), - .rst(rst), - .wr_clk(wr_clk), - .wr_en(wr_en), - .dout(dout), // Bus [35 : 0] - .empty(empty), - .full(full), - .rd_data_count(rd_data_count), // Bus [11 : 0] - .wr_data_count(wr_data_count)); // Bus [11 : 0] - -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file fifo_xlnx_2Kx36_2clk.v when simulating -// the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd deleted file mode 100644 index 53033dc97..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd +++ /dev/null @@ -1,156 +0,0 @@ --------------------------------------------------------------------------------- --- This file is owned and controlled by Xilinx and must be used -- --- solely for design, simulation, implementation and creation of -- --- design files limited to Xilinx devices or technologies. Use -- --- with non-Xilinx devices or technologies is expressly prohibited -- --- and immediately terminates your license. -- --- -- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- --- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- --- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- --- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- --- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- --- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- --- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- --- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- --- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- --- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- --- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- --- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- --- FOR A PARTICULAR PURPOSE. -- --- -- --- Xilinx products are not intended for use in life support -- --- appliances, devices, or systems. Use in such applications are -- --- expressly prohibited. -- --- -- --- (c) Copyright 1995-2007 Xilinx, Inc. -- --- All rights reserved. -- --------------------------------------------------------------------------------- --- You must compile the wrapper file fifo_xlnx_2Kx36_2clk.vhd when simulating --- the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to --- reference the XilinxCoreLib VHDL simulation library. For detailed --- instructions, please refer to the "CORE Generator Help". - --- The synthesis directives "translate_off/translate_on" specified --- below are supported by Xilinx, Mentor Graphics and Synplicity --- synthesis tools. Ensure they are correct for your synthesis tool(s). - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; --- synthesis translate_off -Library XilinxCoreLib; --- synthesis translate_on -ENTITY fifo_xlnx_2Kx36_2clk IS - port ( - din: IN std_logic_VECTOR(35 downto 0); - rd_clk: IN std_logic; - rd_en: IN std_logic; - rst: IN std_logic; - wr_clk: IN std_logic; - wr_en: IN std_logic; - dout: OUT std_logic_VECTOR(35 downto 0); - empty: OUT std_logic; - full: OUT std_logic; - rd_data_count: OUT std_logic_VECTOR(11 downto 0); - wr_data_count: OUT std_logic_VECTOR(11 downto 0)); -END fifo_xlnx_2Kx36_2clk; - -ARCHITECTURE fifo_xlnx_2Kx36_2clk_a OF fifo_xlnx_2Kx36_2clk IS --- synthesis translate_off -component wrapped_fifo_xlnx_2Kx36_2clk - port ( - din: IN std_logic_VECTOR(35 downto 0); - rd_clk: IN std_logic; - rd_en: IN std_logic; - rst: IN std_logic; - wr_clk: IN std_logic; - wr_en: IN std_logic; - dout: OUT std_logic_VECTOR(35 downto 0); - empty: OUT std_logic; - full: OUT std_logic; - rd_data_count: OUT std_logic_VECTOR(11 downto 0); - wr_data_count: OUT std_logic_VECTOR(11 downto 0)); -end component; - --- Configuration specification - for all : wrapped_fifo_xlnx_2Kx36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral) - generic map( - c_has_int_clk => 0, - c_rd_freq => 1, - c_wr_response_latency => 1, - c_has_srst => 0, - c_has_rd_data_count => 1, - c_din_width => 36, - c_has_wr_data_count => 1, - c_full_flags_rst_val => 1, - c_implementation_type => 2, - c_family => "spartan3", - c_use_embedded_reg => 0, - c_has_wr_rst => 0, - c_wr_freq => 1, - c_use_dout_rst => 1, - c_underflow_low => 0, - c_has_meminit_file => 0, - c_has_overflow => 0, - c_preload_latency => 0, - c_dout_width => 36, - c_msgon_val => 1, - c_rd_depth => 2048, - c_default_value => "BlankString", - c_mif_file_name => "BlankString", - c_has_underflow => 0, - c_has_rd_rst => 0, - c_has_almost_full => 0, - c_has_rst => 1, - c_data_count_width => 12, - c_has_wr_ack => 0, - c_use_ecc => 0, - c_wr_ack_low => 0, - c_common_clock => 0, - c_rd_pntr_width => 11, - c_use_fwft_data_count => 1, - c_has_almost_empty => 0, - c_rd_data_count_width => 12, - c_enable_rlocs => 0, - c_wr_pntr_width => 11, - c_overflow_low => 0, - c_prog_empty_type => 0, - c_optimization_mode => 0, - c_wr_data_count_width => 12, - c_preload_regs => 1, - c_dout_rst_val => "0", - c_has_data_count => 0, - c_prog_full_thresh_negate_val => 2046, - c_wr_depth => 2048, - c_prog_empty_thresh_negate_val => 5, - c_prog_empty_thresh_assert_val => 4, - c_has_valid => 0, - c_init_wr_pntr_val => 0, - c_prog_full_thresh_assert_val => 2047, - c_use_fifo16_flags => 0, - c_has_backup => 0, - c_valid_low => 0, - c_prim_fifo_type => "2kx18", - c_count_type => 0, - c_prog_full_type => 0, - c_memory_type => 1); --- synthesis translate_on -BEGIN --- synthesis translate_off -U0 : wrapped_fifo_xlnx_2Kx36_2clk - port map ( - din => din, - rd_clk => rd_clk, - rd_en => rd_en, - rst => rst, - wr_clk => wr_clk, - wr_en => wr_en, - dout => dout, - empty => empty, - full => full, - rd_data_count => rd_data_count, - wr_data_count => wr_data_count); --- synthesis translate_on - -END fifo_xlnx_2Kx36_2clk_a; - diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vho b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vho deleted file mode 100644 index 5165b0bc4..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vho +++ /dev/null @@ -1,76 +0,0 @@ --------------------------------------------------------------------------------- --- This file is owned and controlled by Xilinx and must be used -- --- solely for design, simulation, implementation and creation of -- --- design files limited to Xilinx devices or technologies. Use -- --- with non-Xilinx devices or technologies is expressly prohibited -- --- and immediately terminates your license. -- --- -- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- --- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- --- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- --- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- --- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- --- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- --- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- --- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- --- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- --- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- --- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- --- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- --- FOR A PARTICULAR PURPOSE. -- --- -- --- Xilinx products are not intended for use in life support -- --- appliances, devices, or systems. Use in such applications are -- --- expressly prohibited. -- --- -- --- (c) Copyright 1995-2007 Xilinx, Inc. -- --- All rights reserved. -- --------------------------------------------------------------------------------- --- The following code must appear in the VHDL architecture header: - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -component fifo_xlnx_2Kx36_2clk - port ( - din: IN std_logic_VECTOR(35 downto 0); - rd_clk: IN std_logic; - rd_en: IN std_logic; - rst: IN std_logic; - wr_clk: IN std_logic; - wr_en: IN std_logic; - dout: OUT std_logic_VECTOR(35 downto 0); - empty: OUT std_logic; - full: OUT std_logic; - rd_data_count: OUT std_logic_VECTOR(11 downto 0); - wr_data_count: OUT std_logic_VECTOR(11 downto 0)); -end component; - --- Synplicity black box declaration -attribute syn_black_box : boolean; -attribute syn_black_box of fifo_xlnx_2Kx36_2clk: component is true; - --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : fifo_xlnx_2Kx36_2clk - port map ( - din => din, - rd_clk => rd_clk, - rd_en => rd_en, - rst => rst, - wr_clk => wr_clk, - wr_en => wr_en, - dout => dout, - empty => empty, - full => full, - rd_data_count => rd_data_count, - wr_data_count => wr_data_count); --- INST_TAG_END ------ End INSTANTIATION Template ------------ - --- You must compile the wrapper file fifo_xlnx_2Kx36_2clk.vhd when simulating --- the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to --- reference the XilinxCoreLib VHDL simulation library. For detailed --- instructions, please refer to the "CORE Generator Help". - diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco deleted file mode 100644 index e25ad38da..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco +++ /dev/null @@ -1,82 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version K.39 -# Date: Thu Sep 3 17:25:43 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = True -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = VHDL -SET device = xc3s2000 -SET devicefamily = spartan3 -SET flowvendor = Foundation_iSE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = fg456 -SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -5 -SET verilogsim = True -SET vhdlsim = True -# END Project Options -# BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 4.3 -# END Select -# BEGIN Parameters -CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET component_name=fifo_xlnx_2Kx36_2clk -CSET data_count=false -CSET data_count_width=12 -CSET disable_timing_violations=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=4 -CSET empty_threshold_negate_value=5 -CSET enable_ecc=false -CSET enable_int_clk=false -CSET fifo_implementation=Independent_Clocks_Block_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=2047 -CSET full_threshold_negate_value=2046 -CSET input_data_width=36 -CSET input_depth=2048 -CSET output_data_width=36 -CSET output_depth=2048 -CSET overflow_flag=false -CSET overflow_sense=Active_High -CSET performance_options=First_Word_Fall_Through -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET read_clock_frequency=1 -CSET read_data_count=true -CSET read_data_count_width=12 -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET underflow_flag=false -CSET underflow_sense=Active_High -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=true -CSET valid_flag=false -CSET valid_sense=Active_High -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=true -CSET write_data_count_width=12 -# END Parameters -GENERATE -# CRC: 2ae9f6ef - diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso deleted file mode 100644 index f1a6f7899..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso +++ /dev/null @@ -1,3 +0,0 @@ -blkmemdp_v6_2 -blk_mem_gen_v2_6 -fifo_generator_v4_3 diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt deleted file mode 100644 index 5108be2c5..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +++ /dev/null @@ -1,106 +0,0 @@ - - - - - - -
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- - - diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_flist.txt deleted file mode 100644 index 670d84713..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_flist.txt +++ /dev/null @@ -1,12 +0,0 @@ -# Output products list for -fifo_xlnx_2Kx36_2clk.asy -fifo_xlnx_2Kx36_2clk.ngc -fifo_xlnx_2Kx36_2clk.sym -fifo_xlnx_2Kx36_2clk.v -fifo_xlnx_2Kx36_2clk.veo -fifo_xlnx_2Kx36_2clk.vhd -fifo_xlnx_2Kx36_2clk.vho -fifo_xlnx_2Kx36_2clk.xco -fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -fifo_xlnx_2Kx36_2clk_flist.txt -fifo_xlnx_2Kx36_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_readme.txt deleted file mode 100644 index 1879503a9..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_readme.txt +++ /dev/null @@ -1,55 +0,0 @@ -The following files were generated for 'fifo_xlnx_2Kx36_2clk' in directory -/home/matt/gnuradio.git/usrp2/fpga/coregen/: - -fifo_xlnx_2Kx36_2clk.asy: - Graphical symbol information file. Used by the ISE tools and some - third party tools to create a symbol representing the core. - -fifo_xlnx_2Kx36_2clk.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -fifo_xlnx_2Kx36_2clk.sym: - Please see the core data sheet. - -fifo_xlnx_2Kx36_2clk.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -fifo_xlnx_2Kx36_2clk.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -fifo_xlnx_2Kx36_2clk.vhd: - VHDL wrapper file provided to support functional simulation. This - file contains simulation model customization data that is passed to - a parameterized simulation model for the core. - -fifo_xlnx_2Kx36_2clk.vho: - VHO template file containing code that can be used as a model for - instantiating a CORE Generator module in a VHDL design. - -fifo_xlnx_2Kx36_2clk.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: - Please see the core data sheet. - -fifo_xlnx_2Kx36_2clk_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - -fifo_xlnx_2Kx36_2clk_readme.txt: - Text file indicating the files generated and how they are used. - -fifo_xlnx_2Kx36_2clk_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. - diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl deleted file mode 100644 index cac25efd2..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl +++ /dev/null @@ -1,84 +0,0 @@ -# The package naming convention is _xmdf -package provide fifo_xlnx_2Kx36_2clk_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::fifo_xlnx_2Kx36_2clk_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_2Kx36_2clk -} -# ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.asy -utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.sym -utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.vho -utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_2Kx36_2clk -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise deleted file mode 100644 index 70ee54054..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise +++ /dev/null @@ -1,30 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - - - diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf deleted file mode 100644 index e69de29bb..000000000 diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc deleted file mode 100644 index d1ed419a7..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.6e -$56140<,[o}e~g`n;"2*726&;$9,)<>;.vnt*Ydo&lbjbQwloz\77~4>V8h`f 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6202>80q~:>5;296~X39<16>o4;149'711=?<1vqcm50;0xL62?3tdh8<4?:3yK71>7>52zJ00==zfj>86=4={I17<>{ik=>1<73:1>vF<499~jf202909wE=;8:mg1>=838pD>:7;|l`0<<72;qC?964}oa7e?6=:rB8855rnb6a>5<5sA9?46sac5a94?4|@:>37p`l4e83>7}O;=20qcm;e;296~N4<11vbn:i:181M5302weo8>50;0xL62?3tdh9<4?:3yK71>>7>52zJ00==zfj?86=4={I17<>{ik<>1<73:1>vF<499~jf302909wE=;8:mg0>=838pD>:7;|l`1<<72;qC?964}oa6e?6=:rB8855rnb7a>5<5sA9?46sac4a94?4|@:>37p`l5e83>7}O;=20qcm:e;296~N4<11vbn;i:181M5302weo;>50;0xL62?3tdh:<4?:3yK71>7>52zJ00==zfj<86=4={I17<>{ik?>1<7<0;6?uG35:8yke1>3:1>vF<499~jf002909wE=;8:mg3>=838pD>:7;|l`2<<72;qC?964}oa5e?6=:rB8855rnb4a>5<5sA9?46sac7a94?4|@:>37p`l6e83>7}O;=20qcm9e;296~N4<11vbn8i:181M5302weo:>50;0xL62?3tdh;<4?:3yK71>7>52zJ00==zfj=86=4={I17<>{ik>>1<73:1>vF<499~jf102909wE=;8:mg2>=838pD>:7;|l`3<<72;qC?964}oa4e?6=:rB8855rnb5a>5<5sA9?46sac6a94?4|@:>37p`l7e83>7}O;=20qcm8e;296~N4<11vbn9i:181M5302weo5>50;0xL62?3tdh4<4?:3yK71>7>52zJ00==zfj286=4={I17<>{ik1>1<73:1>vF<499~jf>02909wE=;8:mg=>=838pD>:7;|l`<<<72;qC?964}oa;e?6=:rB8855rnb:a>5<5sA9?46sac9a94?4|@:>37p`l8e83>7}O;=20qcm7e;296~N4<11vbll9:182M5302wen=950;3xL62?3tdi<54?:0yK71>51zJ00==zfk:j6=4>{I17<>{ij9h1<7?tH26;?xhe8j0;6:7;|la55<728qC?964}o`25?6=9rB8855rnc31>5<6sA9?46sab0194?7|@:>37p`m1583>4}O;=20qcl>5;295~N4<11vbo?9:182M5302wen<950;3xL62?3tdi=54?:0yK71>51zJ00==zfk;j6=4>{I17<>{ij8h1<7?tH26;?xhe9j0;6:7;|la65<728qC?964}o`15?6=9rB8855rnc01>5<6sA9?46sab3194?7|@:>37p`m2583>4}O;=20qcl=5;295~N4<11vbo<9:182M5302wen?950;3xL62?3tdi>54?:0yK71>51zJ00==zfk8j6=4>{I17<>{ij;h1<7?tH26;?xhe:j0;6:7;|la75<728qC?964}o`05?6=9rB8855rnc11>5<6sA9?46sab2194?7|@:>37p`m3583>4}O;=20qcl<5;295~N4<11vbo=9:182M5302wen>950;3xL62?3tdi?54?:0yK71>51zJ00==zfk9j6=4>{I17<>{ij:h1<7?tH26;?xhe;j0;6:7;|la05<728qC?964}o`75?6=9rB8855rnc61>5<6sA9?46sab5194?7|@:>37p`m4583>4}O;=20qcl;5;295~N4<11vbo:9:182M5302wen9950;3xL62?3tdi854?:0yK71>51zJ00==zfk>j6=4>{I17<>{ij=h1<7?tH26;?xhe:7;|la15<728qC?964}o`65?6=9rB8855rnc71>5<6sA9?46sab4194?7|@:>37p`m5583>4}O;=20qcl:5;295~N4<11vbo;9:182M5302wen8950;3xL62?3tdi954?:0yK71>57>51zJ00==zfk?j6=4>{I17<>{ij:7;|la25<728qC?964}o`55?6=9rB8855rnc41>5<6sA9?46sab7194?7|@:>37p`m6583>4}O;=20qcl95;295~N4<11vbo89:182M5302wen;950;3xL62?3tdi:54?:0yK71>51zJ00==zfk{I17<>{ij?h1<7?tH26;?xhe>j0;6:7;|la35<728qC?964}o`45?6=9rB8855rnc51>5<6sA9?46sab6194?7|@:>37p`m7583>4}O;=20qcl85;295~N4<11vbo99:182M5302wen:950;3xL62?3tdi;54?:0yK71>51zJ00==zfk=j6=4>{I17<>{ij>h1<7?tH26;?xhe?j0;6:7;|la<5<728qC?964}o`;5?6=9rB8855rnc:1>5<6sA9?46sab9194?7|@:>37p`m8583>4}O;=20qcl75;295~N4<11vbo69:182M5302wen5950;3xL62?3tdi454?:0yK71>51zJ00==zfk2j6=4>{I17<>{ij1h1<7?tH26;?xhe0j0;6b290:wE=;8:mf=`=83;pD>:7;|la=5<728qC?964}o`:5?6=9rB8855rnc;1>5<6sA9?46sab8194?7|@:>37p`m9583>4}O;=20qcl65;295~N4<11vbo79:182M5302wen4950;3xL62?3tdi554?:0yK71>51zJ00==zfk3j6=4>{I17<>{ij0h1<7?tH26;?xhe1j0;6l3:1=vF<499~jg?b290:wE=;8:mf<`=83;pD>:7;|lae5<728qC?964}o`b5?6=9rB8855rncc1>5<6sA9?46sab`194?7|@:>37p`ma583>4}O;=20qcln5;295~N4<11vboo9:182M5302wenl950;3xL62?3tdim54?:0yK71>51zJ00==zfkkj6=4>{I17<>{ijhh1<7?tH26;?xheij0;6:7;|laf5<728qC?964}o`a5?6=9rB8855rnc`1>5<6sA9?46sabc194?7|@:>37p`mb583>4}O;=20qclm5;295~N4<11vbol9:182M5302weno950;3xL62?3tdin54?:0yK71>51zJ00==zfkhj6=4>{I17<>{ijkh1<7?tH26;?xhejj0;6:7;|lag5<728qC?964}o``5?6=9rB8855rnca1>5<6sA9?46sabb194?7|@:>37p`mc583>4}O;=20qcll5;295~N4<11vbom9:182M5302wenn950;3xL62?3tdio54?:0yK71>51zJ00==zfkij6=4>{I17<>{ijjh1<7?tH26;?xhekj0;6:7;|la`5<728qC?964}o`g5?6=9rB8855rncf1>5<6sA9?46sabe194?7|@:>37p`md583>4}O;=20qclk5;295~N4<11vboj9:182M5302weni950;3xL62?3tdih54?:0yK71>51zJ00==zfknj6=4>{I17<>{ijmh1<7?tH26;?xhelj0;6:7;|laa5<728qC?964}o`f5?6=9rB8855rncg1>5<6sA9?46sabd194?7|@:>37p`me583>4}O;=20qclj5;295~N4<11vbok9:182M5302wenh950;3xL62?3tdii54?:0yK71>51zJ00==zfkoj6=4>{I17<>{ijlh1<7?tH26;?xhemj0;6:7;|lab5<728qC?964}o`e5?6=9rB8855rncd1>5<6sA9?46sabg194?7|@:>37p`mf583>4}O;=20qcli5;295~N4<11vboh9:182M5302wenk950;3xL62?3tdij54?:0yK71>51zJ00==zfklj6=4>{I17<>{ijoh1<7?tH26;?xhenj0;6:7;|l`45<728qC?964}oa35?6=9rB8855rnb21>5<6sA9?46sac1194?7|@:>37p`l0583>4}O;=20qcm?5;295~N4<11vbn>9:182M5302weo=950;3xL62?3tdh<54?:0yK71>51zJ00==zfj:j6=4>{I17<>{ik9h1<7?tH26;?xhd8j0;6:7;|l`55<728qC?964}oa25?6=9rB8855rnb31>5<6sA9?46sac0194?7|@:>37p`l1583>4}O;=20qcm>5;295~N4<11vbn?9:182M5302weo<950;3xL62?3tdh=54?:0yK71>51zJ00==zfj;j6=4>{I17<>{ik8h1<7?tH26;?xhd9j0;6:7;|l`65<728qC?964}oa15?6=9rB8855rnb01>5<6sA9?46sac3194?7|@:>37p`l2583>4}O;=20qcm=5;295~N4<11vbn<9:182M5302weo?950;3xL62?3tdh>54?:0yK71>51zJ00==zfj8j6=4>{I17<>{ik;h1<7?tH26;?xhd:j0;6:7;|l`75<728qC?964}oa05?6=9rB8855rnb11>5<6sA9?46sac2194?7|@:>37p`l3583>4}O;=20qcm<5;295~N4<11vbn=9:182M5302weo>950;3xL62?3tdh?54?:0yK71>51zJ00==zfj9j6=4>{I17<>{ik:h1<7?tH26;?xhd;j0;6111 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), - .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), - .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), - .LO(\BU2/U0/grf.rf/gl0.rd/rpntr/N11 ) - ); - LUT3_L #( - .INIT ( 8'h7F )) - \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3>111 ( - .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), - .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), - .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), - .LO(\BU2/U0/grf.rf/gl0.wr/wpntr/N11 ) - ); - LUT2_L #( - .INIT ( 4'h6 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_SW0 ( - .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]), - .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]), - .LO(\BU2/N16 ) - ); - LUT2_L #( - .INIT ( 4'h6 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_SW0 ( - .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]), - .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]), - .LO(\BU2/N14 ) - ); - INV \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<0>11_INV_0 ( - .I(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), - .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ) - ); - INV \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<0>11_INV_0 ( - .I(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), - .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_1 ( - .I0(wr_en), - .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), - .O(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ) - ); - LUT4 #( - .INIT ( 16'h2333 )) - \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_1 ( - .I0(rd_en), - .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ), - .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), - .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), - .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ) - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<3>12 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]), - .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), - .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), - .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), - .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ) - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3>12 ( - .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]), - .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), - .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), - .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), - .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ) - ); - LUT3 #( - .INIT ( 8'h08 )) - \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1 ( - .I0(wr_en), - .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]), - .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ) - ); - LUT3 #( - .INIT ( 8'h10 )) - \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl ( - .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), - .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]), - .I2(wr_en), - .O(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<5> ( - .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]), - .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [5]) - ); - LUT4 #( - .INIT ( 16'h9000 )) - \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i78 ( - .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]), - .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]), - .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 ), - .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 ), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ) - ); - LUT4 #( - .INIT ( 16'h9000 )) - \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158 ( - .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]), - .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), - .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 ), - .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 ), - .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<4> ( - .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), - .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<3> ( - .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), - .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [3]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<2> ( - .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), - .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [2]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<1> ( - .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]), - .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [1]) - ); - LUT4 #( - .INIT ( 16'h5450 )) - \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000105 ( - .I0(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ), - .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 ), - .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 ), - .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063 ( - .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]), - .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), - .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]), - .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 ) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027 ( - .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]), - .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]), - .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]), - .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 ) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26 ( - .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]), - .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]), - .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]), - .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 ) - ); - LUT4 #( - .INIT ( 16'h5450 )) - \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000107 ( - .I0(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ), - .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 ), - .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ), - .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 ), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 ) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067 ( - .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]), - .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), - .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]), - .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 ) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026 ( - .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]), - .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]), - .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]), - .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1 ( - .I0(wr_en), - .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), - .O(\BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 ) - ); - LUT4 #( - .INIT ( 16'hECA0 )) - \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000183 ( - .I0(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 ), - .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 ), - .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 ), - .I3(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 ), - .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]), - .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]), - .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]), - .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]), - .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 ) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062 ( - .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]), - .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]), - .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 ) - ); - LUT4 #( - .INIT ( 16'h8241 )) - \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026 ( - .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]), - .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]), - .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 ) - ); - LUT4 #( - .INIT ( 16'h2333 )) - \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21 ( - .I0(rd_en), - .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ), - .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), - .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), - .O(\BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 ) - ); - LUT3 #( - .INIT ( 8'hA6 )) - \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<4>11 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]), - .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]), - .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/N11 ), - .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ) - ); - LUT3 #( - .INIT ( 8'hA6 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<4>11 ( - .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]), - .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]), - .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/N11 ), - .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX11 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N5 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N7 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [0]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1011 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N45 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N47 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [10]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1111 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N9 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N11 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [1]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX11111 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N49 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N51 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [11]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1211 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N53 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N55 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [12]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1311 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N57 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N59 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [13]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1411 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N61 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N63 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [14]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1511 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N65 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N67 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [15]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1611 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N69 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N71 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [16]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1711 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N73 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N75 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [17]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1811 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N77 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N79 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [18]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1911 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N81 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N83 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [19]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2011 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N85 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N87 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [20]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2111 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N13 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N15 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [2]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX21111 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N89 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N91 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [21]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2211 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N93 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N95 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [22]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2311 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N97 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N99 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [23]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2411 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N101 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N103 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [24]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2511 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N105 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N107 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [25]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2611 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N109 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N111 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [26]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2711 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N113 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N115 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [27]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2811 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N117 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N119 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [28]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2911 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N121 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N123 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [29]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3011 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N125 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N127 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [30]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3111 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N17 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N19 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [3]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX31111 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N129 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N131 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [31]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3211 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N133 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N135 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [32]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3311 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N137 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N139 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [33]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3411 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N141 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N143 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [34]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3511 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N145 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N147 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [35]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX411 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N21 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N23 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [4]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX511 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N25 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N27 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [5]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX611 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N29 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N31 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [6]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX711 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N33 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N35 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [7]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX811 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N37 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N39 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [8]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX911 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/mem/gdm.dm/N41 ), - .I2(\BU2/U0/grf.rf/mem/gdm.dm/N43 ), - .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [9]) - ); - LUT4 #( - .INIT ( 16'h6996 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003 ( - .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]), - .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0]), - .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), - .I3(\BU2/N16 ), - .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 ) - ); - LUT4 #( - .INIT ( 16'h6996 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003 ( - .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]), - .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0]), - .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), - .I3(\BU2/N14 ), - .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 ) - ); - LUT3 #( - .INIT ( 8'hA2 )) - \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_REGOUT_EN11 ( - .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), - .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), - .I2(rd_en), - .O(\BU2/U0/grf.rf/mem/dout_i_not0001 ) - ); - LUT2 #( - .INIT ( 4'hD )) - \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_not00011 ( - .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), - .I1(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ) - ); - LUT4 #( - .INIT ( 16'h8E8A )) - \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux00001 ( - .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 ), - .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), - .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), - .I3(rd_en), - .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ) - ); - LUT4 #( - .INIT ( 16'h6996 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00021 ( - .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]), - .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]), - .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), - .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]), - .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ) - ); - LUT4 #( - .INIT ( 16'h6996 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00021 ( - .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]), - .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]), - .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), - .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]), - .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ) - ); - LUT4 #( - .INIT ( 16'h40FF )) - \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001<0>1 ( - .I0(rd_en), - .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), - .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), - .I3(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ), - .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [0]) - ); - LUT3 #( - .INIT ( 8'h6A )) - \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<2>11 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), - .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), - .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), - .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ) - ); - LUT3 #( - .INIT ( 8'h6A )) - \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<2>11 ( - .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), - .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), - .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), - .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ) - ); - LUT3 #( - .INIT ( 8'h96 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00011 ( - .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), - .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]), - .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]), - .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ) - ); - LUT3 #( - .INIT ( 8'h96 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00011 ( - .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), - .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]), - .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]), - .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ) - ); - LUT3 #( - .INIT ( 8'hF2 )) - \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001<1>1 ( - .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), - .I1(rd_en), - .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), - .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [1]) - ); - LUT3 #( - .INIT ( 8'h08 )) - \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux00031 ( - .I0(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [4]), - .I1(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [5]), - .I2(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0000_Result1 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0001_Result1 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0002_Result1 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0003_Result1 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0000_Result1 ( - .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]), - .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0001_Result1 ( - .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0002_Result1 ( - .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0003_Result1 ( - .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<1>11 ( - .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), - .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), - .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<1>11 ( - .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), - .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), - .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00001 ( - .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]), - .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), - .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00001 ( - .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]), - .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), - .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \BU2/U0/grf.rf/rstblk/rd_rst_comb1 ( - .I0(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 ), - .I1(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ), - .O(\BU2/U0/grf.rf/rstblk/rd_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \BU2/U0/grf.rf/rstblk/wr_rst_comb1 ( - .I0(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 ), - .I1(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ), - .O(\BU2/U0/grf.rf/rstblk/wr_rst_comb ) - ); - FDPE #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ), - .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 ), - .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), - .Q(almost_full) - ); - FDP #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i ( - .C(wr_clk), - .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ), - .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), - .Q(full) - ); - FDP #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i ( - .C(wr_clk), - .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ), - .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), - .Q(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_0 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [0]), - .Q(dout_3[0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_1 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [1]), - .Q(dout_3[1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_2 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [2]), - .Q(dout_3[2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_3 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [3]), - .Q(dout_3[3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_4 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [4]), - .Q(dout_3[4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_5 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [5]), - .Q(dout_3[5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_6 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [6]), - .Q(dout_3[6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_7 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [7]), - .Q(dout_3[7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_8 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [8]), - .Q(dout_3[8]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_9 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [9]), - .Q(dout_3[9]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_10 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [10]), - .Q(dout_3[10]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_11 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [11]), - .Q(dout_3[11]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_12 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [12]), - .Q(dout_3[12]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_13 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [13]), - .Q(dout_3[13]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_14 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [14]), - .Q(dout_3[14]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_15 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [15]), - .Q(dout_3[15]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_16 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [16]), - .Q(dout_3[16]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_17 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [17]), - .Q(dout_3[17]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_18 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [18]), - .Q(dout_3[18]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_19 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [19]), - .Q(dout_3[19]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_20 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [20]), - .Q(dout_3[20]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_21 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [21]), - .Q(dout_3[21]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_22 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [22]), - .Q(dout_3[22]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_23 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [23]), - .Q(dout_3[23]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_24 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [24]), - .Q(dout_3[24]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_25 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [25]), - .Q(dout_3[25]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_26 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [26]), - .Q(dout_3[26]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_27 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [27]), - .Q(dout_3[27]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_28 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [28]), - .Q(dout_3[28]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_29 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [29]), - .Q(dout_3[29]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_30 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [30]), - .Q(dout_3[30]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_31 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [31]), - .Q(dout_3[31]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_32 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [32]), - .Q(dout_3[32]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_33 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [33]), - .Q(dout_3[33]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_34 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [34]), - .Q(dout_3[34]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/dout_i_35 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [35]), - .Q(dout_3[35]) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[35]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N147 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[35]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N145 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[34]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N143 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[34]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N141 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[33]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N137 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[32]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N135 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[33]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N139 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[32]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N133 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[31]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N131 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[31]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N129 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[30]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N127 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[29]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N123 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[29]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N121 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[30]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N125 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[28]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N119 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[28]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N117 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[27]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N115 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[27]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N113 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[26]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N109 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[25]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N107 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[26]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N111 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[24]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N103 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[24]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N101 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[25]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N105 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[23]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N97 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[22]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N95 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[23]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N99 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[22]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N93 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[21]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N91 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[21]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N89 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[20]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N87 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[19]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N83 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[19]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N81 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[20]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N85 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[18]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N79 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[18]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N77 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[17]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N75 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[17]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N73 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[16]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N69 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[15]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N67 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[16]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N71 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[15]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N65 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[14]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N63 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[14]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N61 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[13]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N59 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[12]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N55 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[12]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N53 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[13]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N57 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[11]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N51 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[11]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N49 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[10]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N47 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[10]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N45 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[9]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N41 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[8]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N39 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[9]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N43 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[8]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N37 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[7]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N35 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[7]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N33 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[6]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N31 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[5]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N27 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[5]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N25 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[6]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N29 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[4]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N23 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[4]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N21 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[3]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N19 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[3]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N17 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[2]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N13 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[1]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N11 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[2]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N15 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[1]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N9 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[0]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N7 ) - ); - RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1 ( - .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), - .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), - .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), - .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), - .D(din_2[0]), - .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), - .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), - .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), - .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), - .WCLK(wr_clk), - .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), - .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_SPO_UNCONNECTED ), - .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N5 ) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_35 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [35]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [35]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_34 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [34]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [34]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_33 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [33]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [33]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_32 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [32]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [32]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_31 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [31]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [31]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_30 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [30]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [30]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_29 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [29]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [29]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_28 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [28]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [28]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_27 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [27]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [27]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_26 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [26]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [26]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_25 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [25]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [25]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_24 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [24]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [24]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_23 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [23]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [23]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_22 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [22]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [22]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_21 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [21]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [21]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_20 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [20]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [20]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_19 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [19]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [19]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_18 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [18]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [18]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_17 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [17]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [17]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_16 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [16]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [16]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_15 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [15]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [15]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_14 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [14]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [14]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_13 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [13]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [13]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_12 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [12]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [12]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_11 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [11]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [11]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_10 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [10]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [10]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_9 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [9]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [9]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_8 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [8]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [8]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_7 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [7]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_6 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [6]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_5 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [5]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_4 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [4]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_3 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [3]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_2 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [2]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_1 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [1]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/mem/gdm.dm/dout_i_0 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), - .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [0]), - .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_0 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_1 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_2 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_3 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_4 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_4 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_3 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_1 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]) - ); - FDPE #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_0 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]), - .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_2 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_4 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_3 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]) - ); - FDPE #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_1 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), - .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_0 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_2 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_2 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]) - ); - FDPE #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_0 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ), - .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]) - ); - FDPE #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_1 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ), - .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_3 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.wr/wpntr/count_4 ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ), - .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]) - ); - FDPE #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ), - .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 ), - .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), - .Q(prog_full) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_4 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [4]), - .Q(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [4]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_5 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), - .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [5]), - .Q(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [5]) - ); - MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<0> ( - .CI(\BU2/N1 ), - .DI(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), - .S(\BU2/rd_data_count [0]), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [0]) - ); - MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<1> ( - .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [0]), - .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]), - .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [1]), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [1]) - ); - MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<2> ( - .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [1]), - .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), - .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [2]), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [2]) - ); - MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<3> ( - .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [2]), - .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), - .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [3]), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]) - ); - MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<4> ( - .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]), - .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), - .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [4]) - ); - XORCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_xor<4> ( - .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]), - .LI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [4]) - ); - XORCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_xor<5> ( - .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [4]), - .LI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [5]), - .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [5]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_0 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), - .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [1]), - .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_1 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), - .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [0]), - .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]) - ); - FDP #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i ( - .C(rd_clk), - .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ), - .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), - .Q(empty) - ); - FDP #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb ( - .C(rd_clk), - .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ), - .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), - .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 ) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_0 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), - .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), - .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_1 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), - .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), - .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_2 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), - .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), - .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_3 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), - .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]), - .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_4 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), - .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]), - .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.rd/rpntr/count_2 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), - .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ), - .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]) - ); - FDPE #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/gl0.rd/rpntr/count_0 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ), - .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), - .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.rd/rpntr/count_1 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), - .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ), - .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.rd/rpntr/count_3 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), - .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ), - .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gl0.rd/rpntr/count_4 ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), - .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ), - .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_0 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_1 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_2 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_3 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_4 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_0 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_1 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_2 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_3 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_4 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_0 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0]), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_1 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1]), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_2 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2]), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_3 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3]), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_4 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4]), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_0 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0]), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_1 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1]), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_2 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2]), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_3 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3]), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_4 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4]), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_0 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0]), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_1 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1]), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_2 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2]), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_3 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3]), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_4 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4]), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_0 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0]), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_1 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1]), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_2 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2]), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_3 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3]), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_4 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4]), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_0 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 ), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_1 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_2 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_3 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_4 ( - .C(rd_clk), - .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), - .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), - .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_0 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 ), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_1 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_2 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_3 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_4 ( - .C(wr_clk), - .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), - .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), - .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]) - ); - FDP #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/rstblk/wr_rst_reg_0 ( - .C(wr_clk), - .D(\BU2/rd_data_count [0]), - .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ), - .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]) - ); - FDP #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/rstblk/wr_rst_reg_1 ( - .C(wr_clk), - .D(\BU2/rd_data_count [0]), - .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ), - .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]) - ); - FDP #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/rstblk/rd_rst_reg_0 ( - .C(rd_clk), - .D(\BU2/rd_data_count [0]), - .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ), - .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]) - ); - FDP #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/rstblk/rd_rst_reg_1 ( - .C(rd_clk), - .D(\BU2/rd_data_count [0]), - .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ), - .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]) - ); - FDP #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/rstblk/rd_rst_reg_2 ( - .C(rd_clk), - .D(\BU2/rd_data_count [0]), - .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ), - .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]) - ); - FDP #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/rstblk/rst_d1 ( - .C(wr_clk), - .D(\BU2/rd_data_count [0]), - .PRE(rst), - .Q(\BU2/U0/grf.rf/rstblk/rst_d1_93 ) - ); - FDPE \BU2/U0/grf.rf/rstblk/rd_rst_asreg ( - .C(rd_clk), - .CE(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ), - .D(\BU2/rd_data_count [0]), - .PRE(rst), - .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ) - ); - FD #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1 ( - .C(wr_clk), - .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ), - .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ) - ); - FDPE \BU2/U0/grf.rf/rstblk/wr_rst_asreg ( - .C(wr_clk), - .CE(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ), - .D(\BU2/rd_data_count [0]), - .PRE(rst), - .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ) - ); - FD #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1 ( - .C(rd_clk), - .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ), - .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ) - ); - FDP #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/rstblk/rst_d2 ( - .C(wr_clk), - .D(\BU2/U0/grf.rf/rstblk/rst_d1_93 ), - .PRE(rst), - .Q(\BU2/U0/grf.rf/rstblk/rst_d2_88 ) - ); - FD #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2 ( - .C(wr_clk), - .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ), - .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 ) - ); - FD #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2 ( - .C(rd_clk), - .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ), - .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 ) - ); - FDP #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/rstblk/rst_d3 ( - .C(wr_clk), - .D(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), - .PRE(rst), - .Q(\BU2/U0/grf.rf/rstblk/rst_d3_86 ) - ); - FDC #( - .INIT ( 1'b0 )) - \BU2/U0/grf.rf/rstblk/RST_FULL_GEN ( - .C(wr_clk), - .CLR(rst), - .D(\BU2/U0/grf.rf/rstblk/rst_d3_86 ), - .Q(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ) - ); - FDP #( - .INIT ( 1'b1 )) - \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i ( - .C(rd_clk), - .D(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ), - .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), - .Q(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ) - ); - VCC \BU2/XST_VCC ( - .P(\BU2/N1 ) - ); - GND \BU2/XST_GND ( - .G(\BU2/rd_data_count [0]) - ); - -// synthesis translate_on - -endmodule - -// synthesis translate_off - -`ifndef GLBL -`define GLBL - -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (weak1, weak0) GSR = GSR_int; - assign (weak1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule - -`endif - -// synthesis translate_on diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo deleted file mode 100644 index eb98a2b70..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo +++ /dev/null @@ -1,47 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2009 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fifo_xlnx_32x36_2clk YourInstanceName ( - .rst(rst), - .wr_clk(wr_clk), - .rd_clk(rd_clk), - .din(din), // Bus [35 : 0] - .wr_en(wr_en), - .rd_en(rd_en), - .dout(dout), // Bus [35 : 0] - .full(full), - .almost_full(almost_full), - .empty(empty), - .prog_full(prog_full)); - -// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco deleted file mode 100644 index 1cf4c8ba5..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco +++ /dev/null @@ -1,84 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 12.2 -# Date: Fri Oct 15 07:50:15 2010 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = false -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc3s2000 -SET devicefamily = spartan3 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = fg456 -SET removerpms = false -SET simulationfiles = Structural -SET speedgrade = -5 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 6.1 -# END Select -# BEGIN Parameters -CSET almost_empty_flag=false -CSET almost_full_flag=true -CSET component_name=fifo_xlnx_32x36_2clk -CSET data_count=false -CSET data_count_width=5 -CSET disable_timing_violations=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=4 -CSET empty_threshold_negate_value=5 -CSET enable_ecc=false -CSET enable_int_clk=false -CSET enable_reset_synchronization=true -CSET fifo_implementation=Independent_Clocks_Distributed_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=24 -CSET full_threshold_negate_value=23 -CSET inject_dbit_error=false -CSET inject_sbit_error=false -CSET input_data_width=36 -CSET input_depth=32 -CSET output_data_width=36 -CSET output_depth=32 -CSET overflow_flag=false -CSET overflow_sense=Active_High -CSET performance_options=First_Word_Fall_Through -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant -CSET read_clock_frequency=1 -CSET read_data_count=false -CSET read_data_count_width=5 -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET underflow_flag=false -CSET underflow_sense=Active_High -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=false -CSET valid_flag=false -CSET valid_sense=Active_High -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=false -CSET write_data_count_width=5 -# END Parameters -GENERATE -# CRC: 8e84ee7f diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise deleted file mode 100644 index b9eb7bd1a..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise +++ /dev/null @@ -1,72 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt deleted file mode 100644 index b8c69a9f7..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt +++ /dev/null @@ -1,12 +0,0 @@ -# Output products list for -_xmsgs/pn_parser.xmsgs -fifo_generator_ug175.pdf -fifo_xlnx_32x36_2clk.gise -fifo_xlnx_32x36_2clk.ngc -fifo_xlnx_32x36_2clk.v -fifo_xlnx_32x36_2clk.veo -fifo_xlnx_32x36_2clk.xco -fifo_xlnx_32x36_2clk.xise -fifo_xlnx_32x36_2clk_flist.txt -fifo_xlnx_32x36_2clk_readme.txt -fifo_xlnx_32x36_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt deleted file mode 100644 index 8ab5679fd..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt +++ /dev/null @@ -1,46 +0,0 @@ -The following files were generated for 'fifo_xlnx_32x36_2clk' in directory -/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ - -fifo_generator_ug175.pdf: - Please see the core data sheet. - -fifo_xlnx_32x36_2clk.gise: - ISE Project Navigator support file. This is a generated file and should - not be edited directly. - -fifo_xlnx_32x36_2clk.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -fifo_xlnx_32x36_2clk.v: - Unisim Verilog file containing the information required to simulate - the module. - -fifo_xlnx_32x36_2clk.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -fifo_xlnx_32x36_2clk.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -fifo_xlnx_32x36_2clk.xise: - ISE Project Navigator support file. This is a generated file and should - not be edited directly. - -fifo_xlnx_32x36_2clk_readme.txt: - Text file indicating the files generated and how they are used. - -fifo_xlnx_32x36_2clk_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - -fifo_xlnx_32x36_2clk_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. - diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl deleted file mode 100644 index ec9426357..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl +++ /dev/null @@ -1,68 +0,0 @@ -# The package naming convention is _xmdf -package provide fifo_xlnx_32x36_2clk_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::fifo_xlnx_32x36_2clk_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::fifo_xlnx_32x36_2clk_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_32x36_2clk -} -# ::fifo_xlnx_32x36_2clk_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::fifo_xlnx_32x36_2clk_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_32x36_2clk -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.asy b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.asy deleted file mode 100644 index ecc80b648..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.asy +++ /dev/null @@ -1,49 +0,0 @@ -Version 4 -SymbolType BLOCK -TEXT 32 32 LEFT 4 fifo_xlnx_512x36_2clk -RECTANGLE Normal 32 32 544 672 -LINE Wide 0 80 32 80 -PIN 0 80 LEFT 36 -PINATTR PinName din[35:0] -PINATTR Polarity IN -LINE Normal 0 144 32 144 -PIN 0 144 LEFT 36 -PINATTR PinName wr_en -PINATTR Polarity IN -LINE Normal 0 176 32 176 -PIN 0 176 LEFT 36 -PINATTR PinName wr_clk -PINATTR Polarity IN -LINE Normal 0 240 32 240 -PIN 0 240 LEFT 36 -PINATTR PinName rd_en -PINATTR Polarity IN -LINE Normal 0 272 32 272 -PIN 0 272 LEFT 36 -PINATTR PinName rd_clk -PINATTR Polarity IN -LINE Normal 144 704 144 672 -PIN 144 704 BOTTOM 36 -PINATTR PinName rst -PINATTR Polarity IN -LINE Wide 576 80 544 80 -PIN 576 80 RIGHT 36 -PINATTR PinName dout[35:0] -PINATTR Polarity OUT -LINE Normal 576 208 544 208 -PIN 576 208 RIGHT 36 -PINATTR PinName full -PINATTR Polarity OUT -LINE Wide 576 368 544 368 -PIN 576 368 RIGHT 36 -PINATTR PinName wr_data_count[8:0] -PINATTR Polarity OUT -LINE Normal 576 432 544 432 -PIN 576 432 RIGHT 36 -PINATTR PinName empty -PINATTR Polarity OUT -LINE Wide 576 592 544 592 -PIN 576 592 RIGHT 36 -PINATTR PinName rd_data_count[8:0] -PINATTR Polarity OUT - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.ngc deleted file mode 100644 index 55486485a..000000000 --- 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.sym b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.sym deleted file mode 100644 index 13e8af33d..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.sym +++ /dev/null @@ -1,74 +0,0 @@ -VERSION 5 -BEGIN SYMBOL fifo_xlnx_512x36_2clk -SYMBOLTYPE BLOCK -TIMESTAMP 2008 7 28 22 45 53 -SYMPIN 0 80 Input din[35:0] -SYMPIN 0 144 Input wr_en -SYMPIN 0 176 Input wr_clk -SYMPIN 0 240 Input rd_en -SYMPIN 0 272 Input rd_clk -SYMPIN 144 704 Input rst -SYMPIN 576 80 Output dout[35:0] -SYMPIN 576 208 Output full -SYMPIN 576 368 Output wr_data_count[8:0] -SYMPIN 576 432 Output empty -SYMPIN 576 592 Output rd_data_count[8:0] -BEGIN DISPLAY 32 32 TEXT fifo_xlnx_512x36_2clk - FONT 40 "Arial" -END DISPLAY -RECTANGLE N 32 32 544 672 -BEGIN LINE W 0 80 32 80 -END LINE -BEGIN DISPLAY 36 80 PIN din[35:0] ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 144 32 144 -BEGIN DISPLAY 36 144 PIN wr_en ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 176 32 176 -BEGIN DISPLAY 36 176 PIN wr_clk ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 240 32 240 -BEGIN DISPLAY 36 240 PIN rd_en ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 272 32 272 -BEGIN DISPLAY 36 272 PIN rd_clk ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 144 704 144 672 -BEGIN DISPLAY 144 668 PIN rst ATTR PinName - ALIGNMENT BCENTER - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 576 80 544 80 -END LINE -BEGIN DISPLAY 540 80 PIN dout[35:0] ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -LINE N 576 208 544 208 -BEGIN DISPLAY 540 208 PIN full ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 576 368 544 368 -END LINE -BEGIN DISPLAY 540 368 PIN wr_data_count[8:0] ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -LINE N 576 432 544 432 -BEGIN DISPLAY 540 432 PIN empty ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 576 592 544 592 -END LINE -BEGIN DISPLAY 540 592 PIN rd_data_count[8:0] ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -END SYMBOL diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v deleted file mode 100644 index 905069743..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v +++ /dev/null @@ -1,169 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file fifo_xlnx_512x36_2clk.v when simulating -// the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module fifo_xlnx_512x36_2clk( - din, - rd_clk, - rd_en, - rst, - wr_clk, - wr_en, - dout, - empty, - full, - rd_data_count, - wr_data_count); - - -input [35 : 0] din; -input rd_clk; -input rd_en; -input rst; -input wr_clk; -input wr_en; -output [35 : 0] dout; -output empty; -output full; -output [9 : 0] rd_data_count; -output [9 : 0] wr_data_count; - -// synthesis translate_off - - FIFO_GENERATOR_V4_3 #( - .C_COMMON_CLOCK(0), - .C_COUNT_TYPE(0), - .C_DATA_COUNT_WIDTH(10), - .C_DEFAULT_VALUE("BlankString"), - .C_DIN_WIDTH(36), - .C_DOUT_RST_VAL("0"), - .C_DOUT_WIDTH(36), - .C_ENABLE_RLOCS(0), - .C_FAMILY("spartan3"), - .C_FULL_FLAGS_RST_VAL(1), - .C_HAS_ALMOST_EMPTY(0), - .C_HAS_ALMOST_FULL(0), - .C_HAS_BACKUP(0), - .C_HAS_DATA_COUNT(0), - .C_HAS_INT_CLK(0), - .C_HAS_MEMINIT_FILE(0), - .C_HAS_OVERFLOW(0), - .C_HAS_RD_DATA_COUNT(1), - .C_HAS_RD_RST(0), - .C_HAS_RST(1), - .C_HAS_SRST(0), - .C_HAS_UNDERFLOW(0), - .C_HAS_VALID(0), - .C_HAS_WR_ACK(0), - .C_HAS_WR_DATA_COUNT(1), - .C_HAS_WR_RST(0), - .C_IMPLEMENTATION_TYPE(2), - .C_INIT_WR_PNTR_VAL(0), - .C_MEMORY_TYPE(1), - .C_MIF_FILE_NAME("BlankString"), - .C_MSGON_VAL(1), - .C_OPTIMIZATION_MODE(0), - .C_OVERFLOW_LOW(0), - .C_PRELOAD_LATENCY(0), - .C_PRELOAD_REGS(1), - .C_PRIM_FIFO_TYPE("512x36"), - .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), - .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), - .C_PROG_EMPTY_TYPE(0), - .C_PROG_FULL_THRESH_ASSERT_VAL(511), - .C_PROG_FULL_THRESH_NEGATE_VAL(510), - .C_PROG_FULL_TYPE(0), - .C_RD_DATA_COUNT_WIDTH(10), - .C_RD_DEPTH(512), - .C_RD_FREQ(1), - .C_RD_PNTR_WIDTH(9), - .C_UNDERFLOW_LOW(0), - .C_USE_DOUT_RST(1), - .C_USE_ECC(0), - .C_USE_EMBEDDED_REG(0), - .C_USE_FIFO16_FLAGS(0), - .C_USE_FWFT_DATA_COUNT(1), - .C_VALID_LOW(0), - .C_WR_ACK_LOW(0), - .C_WR_DATA_COUNT_WIDTH(10), - .C_WR_DEPTH(512), - .C_WR_FREQ(1), - .C_WR_PNTR_WIDTH(9), - .C_WR_RESPONSE_LATENCY(1)) - inst ( - .DIN(din), - .RD_CLK(rd_clk), - .RD_EN(rd_en), - .RST(rst), - .WR_CLK(wr_clk), - .WR_EN(wr_en), - .DOUT(dout), - .EMPTY(empty), - .FULL(full), - .RD_DATA_COUNT(rd_data_count), - .WR_DATA_COUNT(wr_data_count), - .CLK(), - .INT_CLK(), - .BACKUP(), - .BACKUP_MARKER(), - .PROG_EMPTY_THRESH(), - .PROG_EMPTY_THRESH_ASSERT(), - .PROG_EMPTY_THRESH_NEGATE(), - .PROG_FULL_THRESH(), - .PROG_FULL_THRESH_ASSERT(), - .PROG_FULL_THRESH_NEGATE(), - .RD_RST(), - .SRST(), - .WR_RST(), - .ALMOST_EMPTY(), - .ALMOST_FULL(), - .DATA_COUNT(), - .OVERFLOW(), - .PROG_EMPTY(), - .PROG_FULL(), - .VALID(), - .UNDERFLOW(), - .WR_ACK(), - .SBITERR(), - .DBITERR()); - - -// synthesis translate_on - -endmodule - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.veo deleted file mode 100644 index 6699ee73b..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.veo +++ /dev/null @@ -1,53 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fifo_xlnx_512x36_2clk YourInstanceName ( - .din(din), // Bus [35 : 0] - .rd_clk(rd_clk), - .rd_en(rd_en), - .rst(rst), - .wr_clk(wr_clk), - .wr_en(wr_en), - .dout(dout), // Bus [35 : 0] - .empty(empty), - .full(full), - .rd_data_count(rd_data_count), // Bus [9 : 0] - .wr_data_count(wr_data_count)); // Bus [9 : 0] - -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file fifo_xlnx_512x36_2clk.v when simulating -// the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd deleted file mode 100644 index d9c2dd307..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd +++ /dev/null @@ -1,156 +0,0 @@ --------------------------------------------------------------------------------- --- This file is owned and controlled by Xilinx and must be used -- --- solely for design, simulation, implementation and creation of -- --- design files limited to Xilinx devices or technologies. Use -- --- with non-Xilinx devices or technologies is expressly prohibited -- --- and immediately terminates your license. -- --- -- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- --- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- --- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- --- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- --- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- --- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- --- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- --- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- --- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- --- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- --- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- --- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- --- FOR A PARTICULAR PURPOSE. -- --- -- --- Xilinx products are not intended for use in life support -- --- appliances, devices, or systems. Use in such applications are -- --- expressly prohibited. -- --- -- --- (c) Copyright 1995-2007 Xilinx, Inc. -- --- All rights reserved. -- --------------------------------------------------------------------------------- --- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating --- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to --- reference the XilinxCoreLib VHDL simulation library. For detailed --- instructions, please refer to the "CORE Generator Help". - --- The synthesis directives "translate_off/translate_on" specified --- below are supported by Xilinx, Mentor Graphics and Synplicity --- synthesis tools. Ensure they are correct for your synthesis tool(s). - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; --- synthesis translate_off -Library XilinxCoreLib; --- synthesis translate_on -ENTITY fifo_xlnx_512x36_2clk IS - port ( - din: IN std_logic_VECTOR(35 downto 0); - rd_clk: IN std_logic; - rd_en: IN std_logic; - rst: IN std_logic; - wr_clk: IN std_logic; - wr_en: IN std_logic; - dout: OUT std_logic_VECTOR(35 downto 0); - empty: OUT std_logic; - full: OUT std_logic; - rd_data_count: OUT std_logic_VECTOR(8 downto 0); - wr_data_count: OUT std_logic_VECTOR(8 downto 0)); -END fifo_xlnx_512x36_2clk; - -ARCHITECTURE fifo_xlnx_512x36_2clk_a OF fifo_xlnx_512x36_2clk IS --- synthesis translate_off -component wrapped_fifo_xlnx_512x36_2clk - port ( - din: IN std_logic_VECTOR(35 downto 0); - rd_clk: IN std_logic; - rd_en: IN std_logic; - rst: IN std_logic; - wr_clk: IN std_logic; - wr_en: IN std_logic; - dout: OUT std_logic_VECTOR(35 downto 0); - empty: OUT std_logic; - full: OUT std_logic; - rd_data_count: OUT std_logic_VECTOR(8 downto 0); - wr_data_count: OUT std_logic_VECTOR(8 downto 0)); -end component; - --- Configuration specification - for all : wrapped_fifo_xlnx_512x36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral) - generic map( - c_has_int_clk => 0, - c_rd_freq => 1, - c_wr_response_latency => 1, - c_has_srst => 0, - c_has_rd_data_count => 1, - c_din_width => 36, - c_has_wr_data_count => 1, - c_full_flags_rst_val => 1, - c_implementation_type => 2, - c_family => "spartan3", - c_use_embedded_reg => 0, - c_has_wr_rst => 0, - c_wr_freq => 1, - c_use_dout_rst => 0, - c_underflow_low => 0, - c_has_meminit_file => 0, - c_has_overflow => 0, - c_preload_latency => 0, - c_dout_width => 36, - c_msgon_val => 1, - c_rd_depth => 512, - c_default_value => "BlankString", - c_mif_file_name => "BlankString", - c_has_underflow => 0, - c_has_rd_rst => 0, - c_has_almost_full => 0, - c_has_rst => 1, - c_data_count_width => 9, - c_has_wr_ack => 0, - c_use_ecc => 0, - c_wr_ack_low => 0, - c_common_clock => 0, - c_rd_pntr_width => 9, - c_use_fwft_data_count => 0, - c_has_almost_empty => 0, - c_rd_data_count_width => 9, - c_enable_rlocs => 0, - c_wr_pntr_width => 9, - c_overflow_low => 0, - c_prog_empty_type => 0, - c_optimization_mode => 0, - c_wr_data_count_width => 9, - c_preload_regs => 1, - c_dout_rst_val => "0", - c_has_data_count => 0, - c_prog_full_thresh_negate_val => 510, - c_wr_depth => 512, - c_prog_empty_thresh_negate_val => 5, - c_prog_empty_thresh_assert_val => 4, - c_has_valid => 0, - c_init_wr_pntr_val => 0, - c_prog_full_thresh_assert_val => 511, - c_use_fifo16_flags => 0, - c_has_backup => 0, - c_valid_low => 0, - c_prim_fifo_type => "512x36", - c_count_type => 0, - c_prog_full_type => 0, - c_memory_type => 1); --- synthesis translate_on -BEGIN --- synthesis translate_off -U0 : wrapped_fifo_xlnx_512x36_2clk - port map ( - din => din, - rd_clk => rd_clk, - rd_en => rd_en, - rst => rst, - wr_clk => wr_clk, - wr_en => wr_en, - dout => dout, - empty => empty, - full => full, - rd_data_count => rd_data_count, - wr_data_count => wr_data_count); --- synthesis translate_on - -END fifo_xlnx_512x36_2clk_a; - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vho b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vho deleted file mode 100644 index 70eac27a5..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vho +++ /dev/null @@ -1,76 +0,0 @@ --------------------------------------------------------------------------------- --- This file is owned and controlled by Xilinx and must be used -- --- solely for design, simulation, implementation and creation of -- --- design files limited to Xilinx devices or technologies. Use -- --- with non-Xilinx devices or technologies is expressly prohibited -- --- and immediately terminates your license. -- --- -- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- --- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- --- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- --- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- --- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- --- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- --- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- --- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- --- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- --- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- --- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- --- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- --- FOR A PARTICULAR PURPOSE. -- --- -- --- Xilinx products are not intended for use in life support -- --- appliances, devices, or systems. Use in such applications are -- --- expressly prohibited. -- --- -- --- (c) Copyright 1995-2007 Xilinx, Inc. -- --- All rights reserved. -- --------------------------------------------------------------------------------- --- The following code must appear in the VHDL architecture header: - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -component fifo_xlnx_512x36_2clk - port ( - din: IN std_logic_VECTOR(35 downto 0); - rd_clk: IN std_logic; - rd_en: IN std_logic; - rst: IN std_logic; - wr_clk: IN std_logic; - wr_en: IN std_logic; - dout: OUT std_logic_VECTOR(35 downto 0); - empty: OUT std_logic; - full: OUT std_logic; - rd_data_count: OUT std_logic_VECTOR(8 downto 0); - wr_data_count: OUT std_logic_VECTOR(8 downto 0)); -end component; - --- Synplicity black box declaration -attribute syn_black_box : boolean; -attribute syn_black_box of fifo_xlnx_512x36_2clk: component is true; - --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : fifo_xlnx_512x36_2clk - port map ( - din => din, - rd_clk => rd_clk, - rd_en => rd_en, - rst => rst, - wr_clk => wr_clk, - wr_en => wr_en, - dout => dout, - empty => empty, - full => full, - rd_data_count => rd_data_count, - wr_data_count => wr_data_count); --- INST_TAG_END ------ End INSTANTIATION Template ------------ - --- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating --- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to --- reference the XilinxCoreLib VHDL simulation library. For detailed --- instructions, please refer to the "CORE Generator Help". - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco deleted file mode 100644 index 5934ef285..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco +++ /dev/null @@ -1,82 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version K.39 -# Date: Thu Sep 3 17:24:24 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = Verilog -SET device = xc3s2000 -SET devicefamily = spartan3 -SET flowvendor = Other -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = fg456 -SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -5 -SET verilogsim = True -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 4.3 -# END Select -# BEGIN Parameters -CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET component_name=fifo_xlnx_512x36_2clk -CSET data_count=false -CSET data_count_width=10 -CSET disable_timing_violations=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=4 -CSET empty_threshold_negate_value=5 -CSET enable_ecc=false -CSET enable_int_clk=false -CSET fifo_implementation=Independent_Clocks_Block_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=511 -CSET full_threshold_negate_value=510 -CSET input_data_width=36 -CSET input_depth=512 -CSET output_data_width=36 -CSET output_depth=512 -CSET overflow_flag=false -CSET overflow_sense=Active_High -CSET performance_options=First_Word_Fall_Through -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET read_clock_frequency=1 -CSET read_data_count=true -CSET read_data_count_width=10 -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET underflow_flag=false -CSET underflow_sense=Active_High -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=true -CSET valid_flag=false -CSET valid_sense=Active_High -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=true -CSET write_data_count_width=10 -# END Parameters -GENERATE -# CRC: b7f2a9ba - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise deleted file mode 100644 index c18cf3bf0..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise +++ /dev/null @@ -1,30 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - - - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf deleted file mode 100644 index e69de29bb..000000000 diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc deleted file mode 100644 index d9277b0c3..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.6e 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- - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt deleted file mode 100644 index 2f8d522f6..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt +++ /dev/null @@ -1,12 +0,0 @@ -# Output products list for -_xmsgs/pn_parser.xmsgs -fifo_generator_ug175.pdf -fifo_xlnx_512x36_2clk_18to36.gise -fifo_xlnx_512x36_2clk_18to36.ngc -fifo_xlnx_512x36_2clk_18to36.v -fifo_xlnx_512x36_2clk_18to36.veo -fifo_xlnx_512x36_2clk_18to36.xco -fifo_xlnx_512x36_2clk_18to36.xise -fifo_xlnx_512x36_2clk_18to36_flist.txt -fifo_xlnx_512x36_2clk_18to36_readme.txt -fifo_xlnx_512x36_2clk_18to36_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt deleted file mode 100644 index 03829e876..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt +++ /dev/null @@ -1,47 +0,0 @@ -The following files were generated for 'fifo_xlnx_512x36_2clk_18to36' in directory -/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ - -fifo_generator_ug175.pdf: - Please see the core data sheet. - -fifo_xlnx_512x36_2clk_18to36.gise: - ISE Project Navigator support file. This is a generated file and should - not be edited directly. - -fifo_xlnx_512x36_2clk_18to36.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -fifo_xlnx_512x36_2clk_18to36.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -fifo_xlnx_512x36_2clk_18to36.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -fifo_xlnx_512x36_2clk_18to36.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -fifo_xlnx_512x36_2clk_18to36.xise: - ISE Project Navigator support file. This is a generated file and should - not be edited directly. - -fifo_xlnx_512x36_2clk_18to36_readme.txt: - Text file indicating the files generated and how they are used. - -fifo_xlnx_512x36_2clk_18to36_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - -fifo_xlnx_512x36_2clk_18to36_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl deleted file mode 100644 index 9b9b1f37a..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl +++ /dev/null @@ -1,68 +0,0 @@ -# The package naming convention is _xmdf -package provide fifo_xlnx_512x36_2clk_18to36_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::fifo_xlnx_512x36_2clk_18to36_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_18to36 -} -# ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_18to36 -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise deleted file mode 100644 index d0c862319..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise +++ /dev/null @@ -1,30 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - - - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf deleted file mode 100644 index e69de29bb..000000000 diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc deleted file mode 100644 index 00814f02e..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v deleted file mode 100644 index b3d994ae8..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v +++ /dev/null @@ -1,169 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2009 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file fifo_xlnx_512x36_2clk_36to18.v when simulating -// the core, fifo_xlnx_512x36_2clk_36to18. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module fifo_xlnx_512x36_2clk_36to18( - rst, - wr_clk, - rd_clk, - din, - wr_en, - rd_en, - dout, - full, - empty); - - -input rst; -input wr_clk; -input rd_clk; -input [35 : 0] din; -input wr_en; -input rd_en; -output [17 : 0] dout; -output full; -output empty; - -// synthesis translate_off - - FIFO_GENERATOR_V6_1 #( - .C_COMMON_CLOCK(0), - .C_COUNT_TYPE(0), - .C_DATA_COUNT_WIDTH(9), - .C_DEFAULT_VALUE("BlankString"), - .C_DIN_WIDTH(36), - .C_DOUT_RST_VAL("0"), - .C_DOUT_WIDTH(18), - .C_ENABLE_RLOCS(0), - .C_ENABLE_RST_SYNC(1), - .C_ERROR_INJECTION_TYPE(0), - .C_FAMILY("spartan3"), - .C_FULL_FLAGS_RST_VAL(0), - .C_HAS_ALMOST_EMPTY(0), - .C_HAS_ALMOST_FULL(0), - .C_HAS_BACKUP(0), - .C_HAS_DATA_COUNT(0), - .C_HAS_INT_CLK(0), - .C_HAS_MEMINIT_FILE(0), - .C_HAS_OVERFLOW(0), - .C_HAS_RD_DATA_COUNT(0), - .C_HAS_RD_RST(0), - .C_HAS_RST(1), - .C_HAS_SRST(0), - .C_HAS_UNDERFLOW(0), - .C_HAS_VALID(0), - .C_HAS_WR_ACK(0), - .C_HAS_WR_DATA_COUNT(0), - .C_HAS_WR_RST(0), - .C_IMPLEMENTATION_TYPE(2), - .C_INIT_WR_PNTR_VAL(0), - .C_MEMORY_TYPE(1), - .C_MIF_FILE_NAME("BlankString"), - .C_MSGON_VAL(1), - .C_OPTIMIZATION_MODE(0), - .C_OVERFLOW_LOW(0), - .C_PRELOAD_LATENCY(0), - .C_PRELOAD_REGS(1), - .C_PRIM_FIFO_TYPE("512x36"), - .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), - .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), - .C_PROG_EMPTY_TYPE(0), - .C_PROG_FULL_THRESH_ASSERT_VAL(509), - .C_PROG_FULL_THRESH_NEGATE_VAL(508), - .C_PROG_FULL_TYPE(0), - .C_RD_DATA_COUNT_WIDTH(10), - .C_RD_DEPTH(1024), - .C_RD_FREQ(1), - .C_RD_PNTR_WIDTH(10), - .C_UNDERFLOW_LOW(0), - .C_USE_DOUT_RST(1), - .C_USE_ECC(0), - .C_USE_EMBEDDED_REG(0), - .C_USE_FIFO16_FLAGS(0), - .C_USE_FWFT_DATA_COUNT(0), - .C_VALID_LOW(0), - .C_WR_ACK_LOW(0), - .C_WR_DATA_COUNT_WIDTH(9), - .C_WR_DEPTH(512), - .C_WR_FREQ(1), - .C_WR_PNTR_WIDTH(9), - .C_WR_RESPONSE_LATENCY(1)) - inst ( - .RST(rst), - .WR_CLK(wr_clk), - .RD_CLK(rd_clk), - .DIN(din), - .WR_EN(wr_en), - .RD_EN(rd_en), - .DOUT(dout), - .FULL(full), - .EMPTY(empty), - .BACKUP(), - .BACKUP_MARKER(), - .CLK(), - .SRST(), - .WR_RST(), - .RD_RST(), - .PROG_EMPTY_THRESH(), - .PROG_EMPTY_THRESH_ASSERT(), - .PROG_EMPTY_THRESH_NEGATE(), - .PROG_FULL_THRESH(), - .PROG_FULL_THRESH_ASSERT(), - .PROG_FULL_THRESH_NEGATE(), - .INT_CLK(), - .INJECTDBITERR(), - .INJECTSBITERR(), - .ALMOST_FULL(), - .WR_ACK(), - .OVERFLOW(), - .ALMOST_EMPTY(), - .VALID(), - .UNDERFLOW(), - .DATA_COUNT(), - .RD_DATA_COUNT(), - .WR_DATA_COUNT(), - .PROG_FULL(), - .PROG_EMPTY(), - .SBITERR(), - .DBITERR()); - - -// synthesis translate_on - -endmodule - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo deleted file mode 100644 index e93be1591..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo +++ /dev/null @@ -1,51 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2009 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fifo_xlnx_512x36_2clk_36to18 YourInstanceName ( - .rst(rst), - .wr_clk(wr_clk), - .rd_clk(rd_clk), - .din(din), // Bus [35 : 0] - .wr_en(wr_en), - .rd_en(rd_en), - .dout(dout), // Bus [17 : 0] - .full(full), - .empty(empty)); - -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file fifo_xlnx_512x36_2clk_36to18.v when simulating -// the core, fifo_xlnx_512x36_2clk_36to18. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco deleted file mode 100644 index d3115e7d5..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco +++ /dev/null @@ -1,84 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 12.1 -# Date: Thu Aug 12 21:06:13 2010 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = false -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc3s2000 -SET devicefamily = spartan3 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = fg456 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -5 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 6.1 -# END Select -# BEGIN Parameters -CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET component_name=fifo_xlnx_512x36_2clk_36to18 -CSET data_count=false -CSET data_count_width=9 -CSET disable_timing_violations=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=4 -CSET empty_threshold_negate_value=5 -CSET enable_ecc=false -CSET enable_int_clk=false -CSET enable_reset_synchronization=true -CSET fifo_implementation=Independent_Clocks_Block_RAM -CSET full_flags_reset_value=0 -CSET full_threshold_assert_value=509 -CSET full_threshold_negate_value=508 -CSET inject_dbit_error=false -CSET inject_sbit_error=false -CSET input_data_width=36 -CSET input_depth=512 -CSET output_data_width=18 -CSET output_depth=1024 -CSET overflow_flag=false -CSET overflow_sense=Active_High -CSET performance_options=First_Word_Fall_Through -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET read_clock_frequency=1 -CSET read_data_count=false -CSET read_data_count_width=10 -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET underflow_flag=false -CSET underflow_sense=Active_High -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=false -CSET valid_flag=false -CSET valid_sense=Active_High -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=false -CSET write_data_count_width=9 -# END Parameters -GENERATE -# CRC: a4e70980 diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise deleted file mode 100644 index cfe983130..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise +++ /dev/null @@ -1,72 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt deleted file mode 100644 index 54c85b15e..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt +++ /dev/null @@ -1,12 +0,0 @@ -# Output products list for -_xmsgs/pn_parser.xmsgs -fifo_generator_ug175.pdf -fifo_xlnx_512x36_2clk_36to18.gise -fifo_xlnx_512x36_2clk_36to18.ngc -fifo_xlnx_512x36_2clk_36to18.v -fifo_xlnx_512x36_2clk_36to18.veo -fifo_xlnx_512x36_2clk_36to18.xco -fifo_xlnx_512x36_2clk_36to18.xise -fifo_xlnx_512x36_2clk_36to18_flist.txt -fifo_xlnx_512x36_2clk_36to18_readme.txt -fifo_xlnx_512x36_2clk_36to18_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt deleted file mode 100644 index 3efc586bf..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt +++ /dev/null @@ -1,47 +0,0 @@ -The following files were generated for 'fifo_xlnx_512x36_2clk_36to18' in directory -/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ - -fifo_generator_ug175.pdf: - Please see the core data sheet. - -fifo_xlnx_512x36_2clk_36to18.gise: - ISE Project Navigator support file. This is a generated file and should - not be edited directly. - -fifo_xlnx_512x36_2clk_36to18.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -fifo_xlnx_512x36_2clk_36to18.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -fifo_xlnx_512x36_2clk_36to18.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -fifo_xlnx_512x36_2clk_36to18.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -fifo_xlnx_512x36_2clk_36to18.xise: - ISE Project Navigator support file. This is a generated file and should - not be edited directly. - -fifo_xlnx_512x36_2clk_36to18_readme.txt: - Text file indicating the files generated and how they are used. - -fifo_xlnx_512x36_2clk_36to18_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - -fifo_xlnx_512x36_2clk_36to18_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl deleted file mode 100644 index 5161c1826..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl +++ /dev/null @@ -1,68 +0,0 @@ -# The package naming convention is _xmdf -package provide fifo_xlnx_512x36_2clk_36to18_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::fifo_xlnx_512x36_2clk_36to18_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_36to18 -} -# ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_36to18 -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso deleted file mode 100644 index f1a6f7899..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso +++ /dev/null @@ -1,3 +0,0 @@ -blkmemdp_v6_2 -blk_mem_gen_v2_6 -fifo_generator_v4_3 diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt deleted file mode 100644 index d110a0158..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +++ /dev/null @@ -1,109 +0,0 @@ - - - - - - -
- - - - - - - - - - - - - - - - - -
-
- - - - - - - - - - - - - -
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- - - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt deleted file mode 100644 index b0975be2d..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Output products list for -fifo_xlnx_512x36_2clk.ngc -fifo_xlnx_512x36_2clk.v -fifo_xlnx_512x36_2clk.veo -fifo_xlnx_512x36_2clk.xco -fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -fifo_xlnx_512x36_2clk_flist.txt -fifo_xlnx_512x36_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise deleted file mode 100644 index 660fb2f65..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise +++ /dev/null @@ -1,28 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ncf deleted file mode 100644 index e69de29bb..000000000 diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc deleted file mode 100644 index 9cb73d5ce..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v deleted file mode 100644 index 6ec1e3f88..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v +++ /dev/null @@ -1,173 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2009 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file fifo_xlnx_512x36_2clk_prog_full.v when simulating -// the core, fifo_xlnx_512x36_2clk_prog_full. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module fifo_xlnx_512x36_2clk_prog_full( - rst, - wr_clk, - rd_clk, - din, - wr_en, - rd_en, - dout, - full, - almost_full, - empty, - prog_full); - - -input rst; -input wr_clk; -input rd_clk; -input [35 : 0] din; -input wr_en; -input rd_en; -output [35 : 0] dout; -output full; -output almost_full; -output empty; -output prog_full; - -// synthesis translate_off - - FIFO_GENERATOR_V6_1 #( - .C_COMMON_CLOCK(0), - .C_COUNT_TYPE(0), - .C_DATA_COUNT_WIDTH(9), - .C_DEFAULT_VALUE("BlankString"), - .C_DIN_WIDTH(36), - .C_DOUT_RST_VAL("0"), - .C_DOUT_WIDTH(36), - .C_ENABLE_RLOCS(0), - .C_ENABLE_RST_SYNC(1), - .C_ERROR_INJECTION_TYPE(0), - .C_FAMILY("spartan3"), - .C_FULL_FLAGS_RST_VAL(1), - .C_HAS_ALMOST_EMPTY(0), - .C_HAS_ALMOST_FULL(1), - .C_HAS_BACKUP(0), - .C_HAS_DATA_COUNT(0), - .C_HAS_INT_CLK(0), - .C_HAS_MEMINIT_FILE(0), - .C_HAS_OVERFLOW(0), - .C_HAS_RD_DATA_COUNT(0), - .C_HAS_RD_RST(0), - .C_HAS_RST(1), - .C_HAS_SRST(0), - .C_HAS_UNDERFLOW(0), - .C_HAS_VALID(0), - .C_HAS_WR_ACK(0), - .C_HAS_WR_DATA_COUNT(0), - .C_HAS_WR_RST(0), - .C_IMPLEMENTATION_TYPE(2), - .C_INIT_WR_PNTR_VAL(0), - .C_MEMORY_TYPE(1), - .C_MIF_FILE_NAME("BlankString"), - .C_MSGON_VAL(1), - .C_OPTIMIZATION_MODE(0), - .C_OVERFLOW_LOW(0), - .C_PRELOAD_LATENCY(0), - .C_PRELOAD_REGS(1), - .C_PRIM_FIFO_TYPE("512x36"), - .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), - .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), - .C_PROG_EMPTY_TYPE(0), - .C_PROG_FULL_THRESH_ASSERT_VAL(500), - .C_PROG_FULL_THRESH_NEGATE_VAL(499), - .C_PROG_FULL_TYPE(1), - .C_RD_DATA_COUNT_WIDTH(9), - .C_RD_DEPTH(512), - .C_RD_FREQ(1), - .C_RD_PNTR_WIDTH(9), - .C_UNDERFLOW_LOW(0), - .C_USE_DOUT_RST(1), - .C_USE_ECC(0), - .C_USE_EMBEDDED_REG(0), - .C_USE_FIFO16_FLAGS(0), - .C_USE_FWFT_DATA_COUNT(0), - .C_VALID_LOW(0), - .C_WR_ACK_LOW(0), - .C_WR_DATA_COUNT_WIDTH(9), - .C_WR_DEPTH(512), - .C_WR_FREQ(1), - .C_WR_PNTR_WIDTH(9), - .C_WR_RESPONSE_LATENCY(1)) - inst ( - .RST(rst), - .WR_CLK(wr_clk), - .RD_CLK(rd_clk), - .DIN(din), - .WR_EN(wr_en), - .RD_EN(rd_en), - .DOUT(dout), - .FULL(full), - .ALMOST_FULL(almost_full), - .EMPTY(empty), - .PROG_FULL(prog_full), - .BACKUP(), - .BACKUP_MARKER(), - .CLK(), - .SRST(), - .WR_RST(), - .RD_RST(), - .PROG_EMPTY_THRESH(), - .PROG_EMPTY_THRESH_ASSERT(), - .PROG_EMPTY_THRESH_NEGATE(), - .PROG_FULL_THRESH(), - .PROG_FULL_THRESH_ASSERT(), - .PROG_FULL_THRESH_NEGATE(), - .INT_CLK(), - .INJECTDBITERR(), - .INJECTSBITERR(), - .WR_ACK(), - .OVERFLOW(), - .ALMOST_EMPTY(), - .VALID(), - .UNDERFLOW(), - .DATA_COUNT(), - .RD_DATA_COUNT(), - .WR_DATA_COUNT(), - .PROG_EMPTY(), - .SBITERR(), - .DBITERR()); - - -// synthesis translate_on - -endmodule - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo deleted file mode 100644 index 64e6769d6..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo +++ /dev/null @@ -1,53 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2009 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fifo_xlnx_512x36_2clk_prog_full YourInstanceName ( - .rst(rst), - .wr_clk(wr_clk), - .rd_clk(rd_clk), - .din(din), // Bus [35 : 0] - .wr_en(wr_en), - .rd_en(rd_en), - .dout(dout), // Bus [35 : 0] - .full(full), - .almost_full(almost_full), - .empty(empty), - .prog_full(prog_full)); - -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file fifo_xlnx_512x36_2clk_prog_full.v when simulating -// the core, fifo_xlnx_512x36_2clk_prog_full. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco deleted file mode 100644 index f99c3c6fb..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco +++ /dev/null @@ -1,84 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 12.2 -# Date: Thu Nov 11 17:27:10 2010 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = false -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc3s2000 -SET devicefamily = spartan3 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = fg456 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -5 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 6.1 -# END Select -# BEGIN Parameters -CSET almost_empty_flag=false -CSET almost_full_flag=true -CSET component_name=fifo_xlnx_512x36_2clk_prog_full -CSET data_count=false -CSET data_count_width=9 -CSET disable_timing_violations=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=4 -CSET empty_threshold_negate_value=5 -CSET enable_ecc=false -CSET enable_int_clk=false -CSET enable_reset_synchronization=true -CSET fifo_implementation=Independent_Clocks_Block_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=500 -CSET full_threshold_negate_value=499 -CSET inject_dbit_error=false -CSET inject_sbit_error=false -CSET input_data_width=36 -CSET input_depth=512 -CSET output_data_width=36 -CSET output_depth=512 -CSET overflow_flag=false -CSET overflow_sense=Active_High -CSET performance_options=First_Word_Fall_Through -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant -CSET read_clock_frequency=1 -CSET read_data_count=false -CSET read_data_count_width=9 -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET underflow_flag=false -CSET underflow_sense=Active_High -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=false -CSET valid_flag=false -CSET valid_sense=Active_High -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=false -CSET write_data_count_width=9 -# END Parameters -GENERATE -# CRC: 6b9f6232 diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise deleted file mode 100644 index 91dbf5819..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise +++ /dev/null @@ -1,72 +0,0 @@ - - - -

- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt deleted file mode 100644 index 2eb837a3f..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt +++ /dev/null @@ -1,12 +0,0 @@ -# Output products list for -_xmsgs/pn_parser.xmsgs -fifo_generator_ug175.pdf -fifo_xlnx_512x36_2clk_prog_full.gise -fifo_xlnx_512x36_2clk_prog_full.ngc -fifo_xlnx_512x36_2clk_prog_full.v -fifo_xlnx_512x36_2clk_prog_full.veo -fifo_xlnx_512x36_2clk_prog_full.xco -fifo_xlnx_512x36_2clk_prog_full.xise -fifo_xlnx_512x36_2clk_prog_full_flist.txt -fifo_xlnx_512x36_2clk_prog_full_readme.txt -fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt deleted file mode 100644 index 33d50a91d..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt +++ /dev/null @@ -1,47 +0,0 @@ -The following files were generated for 'fifo_xlnx_512x36_2clk_prog_full' in directory -/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ - -fifo_generator_ug175.pdf: - Please see the core data sheet. - -fifo_xlnx_512x36_2clk_prog_full.gise: - ISE Project Navigator support file. This is a generated file and should - not be edited directly. - -fifo_xlnx_512x36_2clk_prog_full.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -fifo_xlnx_512x36_2clk_prog_full.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -fifo_xlnx_512x36_2clk_prog_full.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -fifo_xlnx_512x36_2clk_prog_full.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -fifo_xlnx_512x36_2clk_prog_full.xise: - ISE Project Navigator support file. This is a generated file and should - not be edited directly. - -fifo_xlnx_512x36_2clk_prog_full_readme.txt: - Text file indicating the files generated and how they are used. - -fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - -fifo_xlnx_512x36_2clk_prog_full_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl deleted file mode 100644 index e1aecccff..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl +++ /dev/null @@ -1,68 +0,0 @@ -# The package naming convention is _xmdf -package provide fifo_xlnx_512x36_2clk_prog_full_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::fifo_xlnx_512x36_2clk_prog_full_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_prog_full -} -# ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_prog_full -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_readme.txt deleted file mode 100644 index a250a74f5..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_readme.txt +++ /dev/null @@ -1,39 +0,0 @@ -The following files were generated for 'fifo_xlnx_512x36_2clk' in directory -/home/matt/gnuradio.git/usrp2/fpga/coregen/: - -fifo_xlnx_512x36_2clk.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -fifo_xlnx_512x36_2clk.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -fifo_xlnx_512x36_2clk.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -fifo_xlnx_512x36_2clk.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: - Please see the core data sheet. - -fifo_xlnx_512x36_2clk_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - -fifo_xlnx_512x36_2clk_readme.txt: - Text file indicating the files generated and how they are used. - -fifo_xlnx_512x36_2clk_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl deleted file mode 100644 index 8a0c0e3ff..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl +++ /dev/null @@ -1,68 +0,0 @@ -# The package naming convention is _xmdf -package provide fifo_xlnx_512x36_2clk_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::fifo_xlnx_512x36_2clk_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::fifo_xlnx_512x36_2clk_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk -} -# ::fifo_xlnx_512x36_2clk_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::fifo_xlnx_512x36_2clk_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.ngc deleted file mode 100644 index e8c55a1af..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.4e -$4;14g<,[o}e~g`n;"2*413&;$>"9 > %10?*nhel%fmyz cnpfc`h(|dz$Sni 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v deleted file mode 100644 index e84237689..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v +++ /dev/null @@ -1,169 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file fifo_xlnx_64x36_2clk.v when simulating -// the core, fifo_xlnx_64x36_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module fifo_xlnx_64x36_2clk( - din, - rd_clk, - rd_en, - rst, - wr_clk, - wr_en, - dout, - empty, - full, - rd_data_count, - wr_data_count); - - -input [35 : 0] din; -input rd_clk; -input rd_en; -input rst; -input wr_clk; -input wr_en; -output [35 : 0] dout; -output empty; -output full; -output [6 : 0] rd_data_count; -output [6 : 0] wr_data_count; - -// synthesis translate_off - - FIFO_GENERATOR_V4_3 #( - .C_COMMON_CLOCK(0), - .C_COUNT_TYPE(0), - .C_DATA_COUNT_WIDTH(7), - .C_DEFAULT_VALUE("BlankString"), - .C_DIN_WIDTH(36), - .C_DOUT_RST_VAL("0"), - .C_DOUT_WIDTH(36), - .C_ENABLE_RLOCS(0), - .C_FAMILY("spartan3"), - .C_FULL_FLAGS_RST_VAL(1), - .C_HAS_ALMOST_EMPTY(0), - .C_HAS_ALMOST_FULL(0), - .C_HAS_BACKUP(0), - .C_HAS_DATA_COUNT(0), - .C_HAS_INT_CLK(0), - .C_HAS_MEMINIT_FILE(0), - .C_HAS_OVERFLOW(0), - .C_HAS_RD_DATA_COUNT(1), - .C_HAS_RD_RST(0), - .C_HAS_RST(1), - .C_HAS_SRST(0), - .C_HAS_UNDERFLOW(0), - .C_HAS_VALID(0), - .C_HAS_WR_ACK(0), - .C_HAS_WR_DATA_COUNT(1), - .C_HAS_WR_RST(0), - .C_IMPLEMENTATION_TYPE(2), - .C_INIT_WR_PNTR_VAL(0), - .C_MEMORY_TYPE(2), - .C_MIF_FILE_NAME("BlankString"), - .C_MSGON_VAL(1), - .C_OPTIMIZATION_MODE(0), - .C_OVERFLOW_LOW(0), - .C_PRELOAD_LATENCY(0), - .C_PRELOAD_REGS(1), - .C_PRIM_FIFO_TYPE("512x36"), - .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), - .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), - .C_PROG_EMPTY_TYPE(0), - .C_PROG_FULL_THRESH_ASSERT_VAL(63), - .C_PROG_FULL_THRESH_NEGATE_VAL(62), - .C_PROG_FULL_TYPE(0), - .C_RD_DATA_COUNT_WIDTH(7), - .C_RD_DEPTH(64), - .C_RD_FREQ(1), - .C_RD_PNTR_WIDTH(6), - .C_UNDERFLOW_LOW(0), - .C_USE_DOUT_RST(1), - .C_USE_ECC(0), - .C_USE_EMBEDDED_REG(0), - .C_USE_FIFO16_FLAGS(0), - .C_USE_FWFT_DATA_COUNT(1), - .C_VALID_LOW(0), - .C_WR_ACK_LOW(0), - .C_WR_DATA_COUNT_WIDTH(7), - .C_WR_DEPTH(64), - .C_WR_FREQ(1), - .C_WR_PNTR_WIDTH(6), - .C_WR_RESPONSE_LATENCY(1)) - inst ( - .DIN(din), - .RD_CLK(rd_clk), - .RD_EN(rd_en), - .RST(rst), - .WR_CLK(wr_clk), - .WR_EN(wr_en), - .DOUT(dout), - .EMPTY(empty), - .FULL(full), - .RD_DATA_COUNT(rd_data_count), - .WR_DATA_COUNT(wr_data_count), - .CLK(), - .INT_CLK(), - .BACKUP(), - .BACKUP_MARKER(), - .PROG_EMPTY_THRESH(), - .PROG_EMPTY_THRESH_ASSERT(), - .PROG_EMPTY_THRESH_NEGATE(), - .PROG_FULL_THRESH(), - .PROG_FULL_THRESH_ASSERT(), - .PROG_FULL_THRESH_NEGATE(), - .RD_RST(), - .SRST(), - .WR_RST(), - .ALMOST_EMPTY(), - .ALMOST_FULL(), - .DATA_COUNT(), - .OVERFLOW(), - .PROG_EMPTY(), - .PROG_FULL(), - .VALID(), - .UNDERFLOW(), - .WR_ACK(), - .SBITERR(), - .DBITERR()); - - -// synthesis translate_on - -endmodule - diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.veo deleted file mode 100644 index 9c761370c..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.veo +++ /dev/null @@ -1,53 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fifo_xlnx_64x36_2clk YourInstanceName ( - .din(din), // Bus [35 : 0] - .rd_clk(rd_clk), - .rd_en(rd_en), - .rst(rst), - .wr_clk(wr_clk), - .wr_en(wr_en), - .dout(dout), // Bus [35 : 0] - .empty(empty), - .full(full), - .rd_data_count(rd_data_count), // Bus [6 : 0] - .wr_data_count(wr_data_count)); // Bus [6 : 0] - -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file fifo_xlnx_64x36_2clk.v when simulating -// the core, fifo_xlnx_64x36_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco deleted file mode 100644 index c6e9aae27..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco +++ /dev/null @@ -1,82 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version K.39 -# Date: Thu Sep 3 17:22:56 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = Verilog -SET device = xc3s2000 -SET devicefamily = spartan3 -SET flowvendor = Other -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = fg456 -SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -5 -SET verilogsim = True -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 4.3 -# END Select -# BEGIN Parameters -CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET component_name=fifo_xlnx_64x36_2clk -CSET data_count=false -CSET data_count_width=7 -CSET disable_timing_violations=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=4 -CSET empty_threshold_negate_value=5 -CSET enable_ecc=false -CSET enable_int_clk=false -CSET fifo_implementation=Independent_Clocks_Distributed_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=63 -CSET full_threshold_negate_value=62 -CSET input_data_width=36 -CSET input_depth=64 -CSET output_data_width=36 -CSET output_depth=64 -CSET overflow_flag=false -CSET overflow_sense=Active_High -CSET performance_options=First_Word_Fall_Through -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET read_clock_frequency=1 -CSET read_data_count=true -CSET read_data_count_width=7 -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET underflow_flag=false -CSET underflow_sense=Active_High -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=true -CSET valid_flag=false -CSET valid_sense=Active_High -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=true -CSET write_data_count_width=7 -# END Parameters -GENERATE -# CRC: 2bb925ae - diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso deleted file mode 100644 index f1a6f7899..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso +++ /dev/null @@ -1,3 +0,0 @@ -blkmemdp_v6_2 -blk_mem_gen_v2_6 -fifo_generator_v4_3 diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt deleted file mode 100644 index a23402f56..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +++ /dev/null @@ -1,104 +0,0 @@ - - - - - - -
- - - - - - - - - - - - - -
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- - - diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_flist.txt deleted file mode 100644 index 44e31eb6c..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_flist.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Output products list for -fifo_xlnx_64x36_2clk.ngc -fifo_xlnx_64x36_2clk.v -fifo_xlnx_64x36_2clk.veo -fifo_xlnx_64x36_2clk.xco -fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -fifo_xlnx_64x36_2clk_flist.txt -fifo_xlnx_64x36_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_readme.txt deleted file mode 100644 index 7734c0087..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_readme.txt +++ /dev/null @@ -1,39 +0,0 @@ -The following files were generated for 'fifo_xlnx_64x36_2clk' in directory -/home/matt/gnuradio.git/usrp2/fpga/coregen/: - -fifo_xlnx_64x36_2clk.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -fifo_xlnx_64x36_2clk.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -fifo_xlnx_64x36_2clk.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -fifo_xlnx_64x36_2clk.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: - Please see the core data sheet. - -fifo_xlnx_64x36_2clk_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - -fifo_xlnx_64x36_2clk_readme.txt: - Text file indicating the files generated and how they are used. - -fifo_xlnx_64x36_2clk_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. - diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl deleted file mode 100644 index ff5dfd3c2..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl +++ /dev/null @@ -1,68 +0,0 @@ -# The package naming convention is _xmdf -package provide fifo_xlnx_64x36_2clk_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::fifo_xlnx_64x36_2clk_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::fifo_xlnx_64x36_2clk_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_64x36_2clk -} -# ::fifo_xlnx_64x36_2clk_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::fifo_xlnx_64x36_2clk_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_64x36_2clk -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/pll_100_40_75.asy b/fpga/usrp2/coregen/pll_100_40_75.asy deleted file mode 100644 index 9cd1ec359..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75.asy +++ /dev/null @@ -1,29 +0,0 @@ -Version 4 -SymbolType BLOCK -TEXT 32 32 LEFT 4 pll_100_40_75 -RECTANGLE Normal 32 32 576 1088 -LINE Normal 0 80 32 80 -PIN 0 80 LEFT 36 -PINATTR PinName clk_in1 -PINATTR Polarity IN -LINE Normal 0 432 32 432 -PIN 0 432 LEFT 36 -PINATTR PinName reset -PINATTR Polarity IN -LINE Normal 608 80 576 80 -PIN 608 80 RIGHT 36 -PINATTR PinName clk_out1 -PINATTR Polarity OUT -LINE Normal 608 176 576 176 -PIN 608 176 RIGHT 36 -PINATTR PinName clk_out2 -PINATTR Polarity OUT -LINE Normal 608 272 576 272 -PIN 608 272 RIGHT 36 -PINATTR PinName clk_out3 -PINATTR Polarity OUT -LINE Normal 608 976 576 976 -PIN 608 976 RIGHT 36 -PINATTR PinName locked -PINATTR Polarity OUT - diff --git a/fpga/usrp2/coregen/pll_100_40_75.gise b/fpga/usrp2/coregen/pll_100_40_75.gise deleted file mode 100644 index c94415619..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75.gise +++ /dev/null @@ -1,31 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - - - - diff --git a/fpga/usrp2/coregen/pll_100_40_75.ucf b/fpga/usrp2/coregen/pll_100_40_75.ucf deleted file mode 100755 index d8590fabb..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75.ucf +++ /dev/null @@ -1,71 +0,0 @@ -# file: pll_100_40_75.ucf -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# Input clock periods. These duplicate the values entered for the -# input clocks. You can use these to time your system -#---------------------------------------------------------------- -NET "CLK_IN1" TNM_NET = "CLK_IN1"; -TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 25.000 ns HIGH 50% INPUT_JITTER 250.0ps; - -# Derived clock periods. These are commented out because they are -# automatically propogated by the tools -# However, if you'd like to use them for module level testing, you -# can copy them into your module level timing checks -#----------------------------------------------------------------- -# NET "clk_int[1]" TNM_NET = "CLK_OUT1"; -# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 100.000 MHz; - -# NET "clk_int[2]" TNM_NET = "CLK_OUT2"; -# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 40.000 MHz; -# NET "clk_int[3]" TNM_NET = "CLK_OUT3"; -# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 75.000 MHz; - -# FALSE PATH constraints -PIN "RESET" TIG; - diff --git a/fpga/usrp2/coregen/pll_100_40_75.v b/fpga/usrp2/coregen/pll_100_40_75.v deleted file mode 100755 index b400ece75..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75.v +++ /dev/null @@ -1,158 +0,0 @@ -// file: pll_100_40_75.v -// -// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// None -// -//---------------------------------------------------------------------------- -// "Output Output Phase Duty Pk-to-Pk Phase" -// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" -//---------------------------------------------------------------------------- -// CLK_OUT1___100.000______0.000______50.0______252.791____220.216 -// CLK_OUT2____40.000______0.000______50.0______309.264____220.216 -// CLK_OUT3____75.000______0.000______50.0______269.846____220.216 -// -//---------------------------------------------------------------------------- -// "Input Clock Freq (MHz) Input Jitter (UI)" -//---------------------------------------------------------------------------- -// __primary__________40.000____________0.010 - -`timescale 1ps/1ps - -(* CORE_GENERATION_INFO = "pll_100_40_75,clk_wiz_v4_1,{component_name=pll_100_40_75,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=25.000,clkin2_period=25.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *) -module pll_100_40_75 - (// Clock in ports - input CLK_IN1, - // Clock out ports - output CLK_OUT1, - output CLK_OUT2, - output CLK_OUT3, - // Status and control signals - input RESET, - output LOCKED - ); - - // Input buffering - //------------------------------------ - IBUFG clkin1_buf - (.O (clkin1), - .I (CLK_IN1)); - - - // Clocking primitive - //------------------------------------ - // Instantiation of the PLL primitive - // * Unused inputs are tied off - // * Unused outputs are labeled unused - wire [15:0] do_unused; - wire drdy_unused; - wire clkfbout; - wire clkfbout_buf; - wire clkout3_unused; - wire clkout4_unused; - wire clkout5_unused; - - PLL_BASE - #(.BANDWIDTH ("OPTIMIZED"), - .CLK_FEEDBACK ("CLKFBOUT"), - .COMPENSATION ("SYSTEM_SYNCHRONOUS"), - .DIVCLK_DIVIDE (1), - .CLKFBOUT_MULT (15), - .CLKFBOUT_PHASE (0.000), - .CLKOUT0_DIVIDE (6), - .CLKOUT0_PHASE (0.000), - .CLKOUT0_DUTY_CYCLE (0.500), - .CLKOUT1_DIVIDE (15), - .CLKOUT1_PHASE (0.000), - .CLKOUT1_DUTY_CYCLE (0.500), - .CLKOUT2_DIVIDE (8), - .CLKOUT2_PHASE (0.000), - .CLKOUT2_DUTY_CYCLE (0.500), - .CLKIN_PERIOD (25.000), - .REF_JITTER (0.010)) - pll_base_inst - // Output clocks - (.CLKFBOUT (clkfbout), - .CLKOUT0 (clkout0), - .CLKOUT1 (clkout1), - .CLKOUT2 (clkout2), - .CLKOUT3 (clkout3_unused), - .CLKOUT4 (clkout4_unused), - .CLKOUT5 (clkout5_unused), - // Status and control signals - .LOCKED (LOCKED), - .RST (RESET), - // Input clock control - .CLKFBIN (clkfbout_buf), - .CLKIN (clkin1)); - - - // Output buffering - //----------------------------------- - BUFG clkf_buf - (.O (clkfbout_buf), - .I (clkfbout)); - - BUFG clkout1_buf - (.O (CLK_OUT1), - .I (clkout0)); - - - BUFG clkout2_buf - (.O (CLK_OUT2), - .I (clkout1)); - - BUFG clkout3_buf - (.O (CLK_OUT3), - .I (clkout2)); - - - -endmodule diff --git a/fpga/usrp2/coregen/pll_100_40_75.veo b/fpga/usrp2/coregen/pll_100_40_75.veo deleted file mode 100755 index c6ebc5f5c..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75.veo +++ /dev/null @@ -1,82 +0,0 @@ -// -// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// None -// -//---------------------------------------------------------------------------- -// "Output Output Phase Duty Pk-to-Pk Phase" -// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" -//---------------------------------------------------------------------------- -// CLK_OUT1___100.000______0.000______50.0______252.791____220.216 -// CLK_OUT2____40.000______0.000______50.0______309.264____220.216 -// CLK_OUT3____75.000______0.000______50.0______269.846____220.216 -// -//---------------------------------------------------------------------------- -// "Input Clock Freq (MHz) Input Jitter (UI)" -//---------------------------------------------------------------------------- -// __primary__________40.000____________0.010 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG - - pll_100_40_75 instance_name - (// Clock in ports - .CLK_IN1(CLK_IN1), // IN - // Clock out ports - .CLK_OUT1(CLK_OUT1), // OUT - .CLK_OUT2(CLK_OUT2), // OUT - .CLK_OUT3(CLK_OUT3), // OUT - // Status and control signals - .RESET(RESET),// IN - .LOCKED(LOCKED)); // OUT -// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/fpga/usrp2/coregen/pll_100_40_75.xco b/fpga/usrp2/coregen/pll_100_40_75.xco deleted file mode 100644 index a3a0eb4fb..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75.xco +++ /dev/null @@ -1,266 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.1 -# Date: Mon Jun 25 01:21:52 2012 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:clk_wiz:3.5 -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc6slx75 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = csg484 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -3 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.5 -# END Select -# BEGIN Parameters -CSET calc_done=DONE -CSET clk_in_sel_port=CLK_IN_SEL -CSET clk_out1_port=CLK_OUT1 -CSET clk_out1_use_fine_ps_gui=false -CSET clk_out2_port=CLK_OUT2 -CSET clk_out2_use_fine_ps_gui=false -CSET clk_out3_port=CLK_OUT3 -CSET clk_out3_use_fine_ps_gui=false -CSET clk_out4_port=CLK_OUT4 -CSET clk_out4_use_fine_ps_gui=false -CSET clk_out5_port=CLK_OUT5 -CSET clk_out5_use_fine_ps_gui=false -CSET clk_out6_port=CLK_OUT6 -CSET clk_out6_use_fine_ps_gui=false -CSET clk_out7_port=CLK_OUT7 -CSET clk_out7_use_fine_ps_gui=false -CSET clk_valid_port=CLK_VALID -CSET clkfb_in_n_port=CLKFB_IN_N -CSET clkfb_in_p_port=CLKFB_IN_P -CSET clkfb_in_port=CLKFB_IN -CSET clkfb_in_signaling=SINGLE -CSET clkfb_out_n_port=CLKFB_OUT_N -CSET clkfb_out_p_port=CLKFB_OUT_P -CSET clkfb_out_port=CLKFB_OUT -CSET clkfb_stopped_port=CLKFB_STOPPED -CSET clkin1_jitter_ps=250.0 -CSET clkin1_ui_jitter=0.010 -CSET clkin2_jitter_ps=100.0 -CSET clkin2_ui_jitter=0.010 -CSET clkout1_drives=BUFG -CSET clkout1_requested_duty_cycle=50.0 -CSET clkout1_requested_out_freq=100.000 -CSET clkout1_requested_phase=0.000 -CSET clkout2_drives=BUFG -CSET clkout2_requested_duty_cycle=50.0 -CSET clkout2_requested_out_freq=40.000 -CSET clkout2_requested_phase=0.000 -CSET clkout2_used=true -CSET clkout3_drives=BUFG -CSET clkout3_requested_duty_cycle=50.0 -CSET clkout3_requested_out_freq=75.000 -CSET clkout3_requested_phase=0.000 -CSET clkout3_used=true -CSET clkout4_drives=BUFG -CSET clkout4_requested_duty_cycle=50.0 -CSET clkout4_requested_out_freq=75.000 -CSET clkout4_requested_phase=0.000 -CSET clkout4_used=false -CSET clkout5_drives=BUFG -CSET clkout5_requested_duty_cycle=50.0 -CSET clkout5_requested_out_freq=100.000 -CSET clkout5_requested_phase=0.000 -CSET clkout5_used=false -CSET clkout6_drives=BUFG -CSET clkout6_requested_duty_cycle=50.0 -CSET clkout6_requested_out_freq=100.000 -CSET clkout6_requested_phase=0.000 -CSET clkout6_used=false -CSET clkout7_drives=BUFG -CSET clkout7_requested_duty_cycle=50.0 -CSET clkout7_requested_out_freq=100.000 -CSET clkout7_requested_phase=0.000 -CSET clkout7_used=false -CSET clock_mgr_type=AUTO -CSET component_name=pll_100_40_75 -CSET daddr_port=DADDR -CSET dclk_port=DCLK -CSET dcm_clk_feedback=1X -CSET dcm_clk_out1_port=CLKFX -CSET dcm_clk_out2_port=CLK0 -CSET dcm_clk_out3_port=CLKFX -CSET dcm_clk_out4_port=CLKFX -CSET dcm_clk_out5_port=CLK0 -CSET dcm_clk_out6_port=CLK0 -CSET dcm_clkdv_divide=2.0 -CSET dcm_clkfx_divide=2 -CSET dcm_clkfx_multiply=5 -CSET dcm_clkgen_clk_out1_port=CLKFX -CSET dcm_clkgen_clk_out2_port=CLKFX -CSET dcm_clkgen_clk_out3_port=CLKFX -CSET dcm_clkgen_clkfx_divide=1 -CSET dcm_clkgen_clkfx_md_max=0.000 -CSET dcm_clkgen_clkfx_multiply=4 -CSET dcm_clkgen_clkfxdv_divide=2 -CSET dcm_clkgen_clkin_period=10.000 -CSET dcm_clkgen_notes=None -CSET dcm_clkgen_spread_spectrum=NONE -CSET dcm_clkgen_startup_wait=false -CSET dcm_clkin_divide_by_2=false -CSET dcm_clkin_period=25.000 -CSET dcm_clkout_phase_shift=NONE -CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS -CSET dcm_notes=None -CSET dcm_phase_shift=0 -CSET dcm_pll_cascade=NONE -CSET dcm_startup_wait=false -CSET den_port=DEN -CSET din_port=DIN -CSET dout_port=DOUT -CSET drdy_port=DRDY -CSET dwe_port=DWE -CSET feedback_source=FDBK_AUTO -CSET in_freq_units=Units_MHz -CSET in_jitter_units=Units_UI -CSET input_clk_stopped_port=INPUT_CLK_STOPPED -CSET jitter_options=UI -CSET jitter_sel=No_Jitter -CSET locked_port=LOCKED -CSET mmcm_bandwidth=OPTIMIZED -CSET mmcm_clkfbout_mult_f=4.000 -CSET mmcm_clkfbout_phase=0.000 -CSET mmcm_clkfbout_use_fine_ps=false -CSET mmcm_clkin1_period=10.000 -CSET mmcm_clkin2_period=10.000 -CSET mmcm_clkout0_divide_f=4.000 -CSET mmcm_clkout0_duty_cycle=0.500 -CSET mmcm_clkout0_phase=0.000 -CSET mmcm_clkout0_use_fine_ps=false -CSET mmcm_clkout1_divide=1 -CSET mmcm_clkout1_duty_cycle=0.500 -CSET mmcm_clkout1_phase=0.000 -CSET mmcm_clkout1_use_fine_ps=false -CSET mmcm_clkout2_divide=1 -CSET mmcm_clkout2_duty_cycle=0.500 -CSET mmcm_clkout2_phase=0.000 -CSET mmcm_clkout2_use_fine_ps=false -CSET mmcm_clkout3_divide=1 -CSET mmcm_clkout3_duty_cycle=0.500 -CSET mmcm_clkout3_phase=0.000 -CSET mmcm_clkout3_use_fine_ps=false -CSET mmcm_clkout4_cascade=false -CSET mmcm_clkout4_divide=1 -CSET mmcm_clkout4_duty_cycle=0.500 -CSET mmcm_clkout4_phase=0.000 -CSET mmcm_clkout4_use_fine_ps=false -CSET mmcm_clkout5_divide=1 -CSET mmcm_clkout5_duty_cycle=0.500 -CSET mmcm_clkout5_phase=0.000 -CSET mmcm_clkout5_use_fine_ps=false -CSET mmcm_clkout6_divide=1 -CSET mmcm_clkout6_duty_cycle=0.500 -CSET mmcm_clkout6_phase=0.000 -CSET mmcm_clkout6_use_fine_ps=false -CSET mmcm_clock_hold=false -CSET mmcm_compensation=ZHOLD -CSET mmcm_divclk_divide=1 -CSET mmcm_notes=None -CSET mmcm_ref_jitter1=0.010 -CSET mmcm_ref_jitter2=0.010 -CSET mmcm_startup_wait=false -CSET num_out_clks=3 -CSET override_dcm=false -CSET override_dcm_clkgen=false -CSET override_mmcm=false -CSET override_pll=false -CSET platform=lin -CSET pll_bandwidth=OPTIMIZED -CSET pll_clk_feedback=CLKFBOUT -CSET pll_clkfbout_mult=15 -CSET pll_clkfbout_phase=0.000 -CSET pll_clkin_period=25.000 -CSET pll_clkout0_divide=6 -CSET pll_clkout0_duty_cycle=0.500 -CSET pll_clkout0_phase=0.000 -CSET pll_clkout1_divide=15 -CSET pll_clkout1_duty_cycle=0.500 -CSET pll_clkout1_phase=0.000 -CSET pll_clkout2_divide=8 -CSET pll_clkout2_duty_cycle=0.500 -CSET pll_clkout2_phase=0.000 -CSET pll_clkout3_divide=8 -CSET pll_clkout3_duty_cycle=0.500 -CSET pll_clkout3_phase=0.000 -CSET pll_clkout4_divide=1 -CSET pll_clkout4_duty_cycle=0.500 -CSET pll_clkout4_phase=0.000 -CSET pll_clkout5_divide=1 -CSET pll_clkout5_duty_cycle=0.500 -CSET pll_clkout5_phase=0.000 -CSET pll_compensation=SYSTEM_SYNCHRONOUS -CSET pll_divclk_divide=1 -CSET pll_notes=None -CSET pll_ref_jitter=0.010 -CSET power_down_port=POWER_DOWN -CSET prim_in_freq=40.000 -CSET prim_in_jitter=0.010 -CSET prim_source=Single_ended_clock_capable_pin -CSET primary_port=CLK_IN1 -CSET primitive=MMCM -CSET primtype_sel=DCM_SP -CSET psclk_port=PSCLK -CSET psdone_port=PSDONE -CSET psen_port=PSEN -CSET psincdec_port=PSINCDEC -CSET relative_inclk=REL_PRIMARY -CSET reset_port=RESET -CSET secondary_in_freq=100.000 -CSET secondary_in_jitter=0.010 -CSET secondary_port=CLK_IN2 -CSET secondary_source=Single_ended_clock_capable_pin -CSET status_port=STATUS -CSET summary_strings=empty -CSET use_clk_valid=false -CSET use_clkfb_stopped=false -CSET use_dyn_phase_shift=false -CSET use_dyn_reconfig=false -CSET use_freeze=false -CSET use_freq_synth=true -CSET use_inclk_stopped=false -CSET use_inclk_switchover=false -CSET use_locked=true -CSET use_max_i_jitter=false -CSET use_min_o_jitter=false -CSET use_min_power=false -CSET use_phase_alignment=true -CSET use_power_down=false -CSET use_reset=true -CSET use_spread_spectrum=false -CSET use_status=false -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2011-12-28T09:11:49Z -# END Extra information -GENERATE -# CRC: e73fbe14 diff --git a/fpga/usrp2/coregen/pll_100_40_75.xdc b/fpga/usrp2/coregen/pll_100_40_75.xdc deleted file mode 100755 index 4cf03fee7..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75.xdc +++ /dev/null @@ -1,67 +0,0 @@ -# file: pll_100_40_75.xdc -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# Input clock periods. These duplicate the values entered for the -# input clocks. You can use these to time your system -#---------------------------------------------------------------- -create_clock -name CLK_IN1 -period 25.000 [get_ports CLK_IN1] -set_propagated_clock CLK_IN1 -set_input_jitter CLK_IN1 0.25 - -set_false_path -from [get_ports "RESET"] - -# Derived clock periods. These are commented out because they are -# automatically propogated by the tools -# However, if you'd like to use them for module level testing, you -# can copy them into your module level timing checks -#----------------------------------------------------------------- - -#----------------------------------------------------------------- - -#----------------------------------------------------------------- diff --git a/fpga/usrp2/coregen/pll_100_40_75.xise b/fpga/usrp2/coregen/pll_100_40_75.xise deleted file mode 100644 index 55dbd6ddb..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75.xise +++ /dev/null @@ -1,78 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/usrp2/coregen/pll_100_40_75/clk_wiz_v3_5_readme.txt b/fpga/usrp2/coregen/pll_100_40_75/clk_wiz_v3_5_readme.txt deleted file mode 100644 index 4e06648c2..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/clk_wiz_v3_5_readme.txt +++ /dev/null @@ -1,183 +0,0 @@ - Core name: Xilinx LogiCORE Clocking Wizard - Version: 3.5 - Release: ISE 14.1 - Release Date: April 24, 2012 - - -================================================================================ - -This document contains the following sections: - -1. Introduction -2. New Features - 2.1 ISE -3. Supported Devices - 3.1 ISE -4. Resolved Issues - 4.1 ISE -5. Known Issues - 5.1 ISE -6. Technical Support -7. Core Release History -8. Legal Disclaimer - -================================================================================ - - -1. INTRODUCTION - -For installation instructions for this release, please go to: - - http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm - -For system requirements: - - http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm - -This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.5 -solution. For the latest core updates, see the product page at: - - http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ - -................................................................................ - -2. NEW FEATURES - - - 2.1 ISE - - - ISE 14.1 software support - -................................................................................ - -3. SUPPORTED DEVICES - - - 3.1 ISE - - - The following device families are supported by the core for this release. - - All 7 Series devices - - - Zynq-7000 devices - Zynq-7000 - Defense Grade Zynq-7000Q (XQ) - - - All Virtex-6 devices - - - All Spartan-6 devices - - -................................................................................ - -4. RESOLVED ISSUES - - - 4.1 ISE - - - NA - -................................................................................ - -5. KNOWN ISSUES - - - 5.1 ISE - - - The most recent information, including known issues, workarounds, and - resolutions for this version is provided in the IP Release Notes Guide - located at - - www.xilinx.com/support/documentation/user_guides/xtp025.pdf - - -................................................................................ - -6. TECHNICAL SUPPORT - - -To obtain technical support, create a WebCase at www.xilinx.com/support. -Questions are routed to a team with expertise using this product. - -Xilinx provides technical support for use of this product when used -according to the guidelines described in the core documentation, and -cannot guarantee timing, functionality, or support of this product for -designs that do not follow specified guidelines. - - -................................................................................ - -7. CORE RELEASE HISTORY - - -Date By Version Description -================================================================================ -04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support -01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support -06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support -03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support -12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support -09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support -07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support -04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support -12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support -09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support -06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support -04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support -================================================================================ - -................................................................................ - -8. LEGAL DISCLAIMER - -(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved. - -This file contains confidential and proprietary information -of Xilinx, Inc. and is protected under U.S. and -international copyright and other intellectual property -laws. - -DISCLAIMER -This disclaimer is not a license and does not grant any -rights to the materials distributed herewith. Except as -otherwise provided in a valid license issued to you by -Xilinx, and to the maximum extent permitted by applicable -law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -(2) Xilinx shall not be liable (whether in contract or tort, -including negligence, or under any other theory of -liability) for any loss or damage of any kind or nature -related to, arising under or in connection with these -materials, including for any direct, or any indirect, -special, incidental, or consequential loss or damage -(including loss of data, profits, goodwill, or any type of -loss or damage suffered as a result of any action brought -by a third party) even if such damage or loss was -reasonably foreseeable or Xilinx had been advised of the -possibility of the same. - -CRITICAL APPLICATIONS -Xilinx products are not designed or intended to be fail- -safe, or for use in any application requiring fail-safe -performance, such as life-support or safety devices or -systems, Class III medical devices, nuclear facilities, -applications related to the deployment of airbags, or any -other applications that could lead to death, personal -injury, or severe property or environmental damage -(individually and collectively, "Critical -Applications"). Customer assumes the sole risk and -liability of any use of Xilinx products in Critical -Applications, subject only to applicable laws and -regulations governing limitations on product liability. - -THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -PART OF THIS FILE AT ALL TIMES. - diff --git a/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_gsg521.pdf b/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_gsg521.pdf deleted file mode 100644 index 998385638..000000000 Binary files a/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_gsg521.pdf and /dev/null differ diff --git a/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_readme.txt b/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_readme.txt deleted file mode 100644 index 4e06648c2..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_readme.txt +++ /dev/null @@ -1,183 +0,0 @@ - Core name: Xilinx LogiCORE Clocking Wizard - Version: 3.5 - Release: ISE 14.1 - Release Date: April 24, 2012 - - -================================================================================ - -This document contains the following sections: - -1. Introduction -2. New Features - 2.1 ISE -3. Supported Devices - 3.1 ISE -4. Resolved Issues - 4.1 ISE -5. Known Issues - 5.1 ISE -6. Technical Support -7. Core Release History -8. Legal Disclaimer - -================================================================================ - - -1. INTRODUCTION - -For installation instructions for this release, please go to: - - http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm - -For system requirements: - - http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm - -This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.5 -solution. For the latest core updates, see the product page at: - - http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ - -................................................................................ - -2. NEW FEATURES - - - 2.1 ISE - - - ISE 14.1 software support - -................................................................................ - -3. SUPPORTED DEVICES - - - 3.1 ISE - - - The following device families are supported by the core for this release. - - All 7 Series devices - - - Zynq-7000 devices - Zynq-7000 - Defense Grade Zynq-7000Q (XQ) - - - All Virtex-6 devices - - - All Spartan-6 devices - - -................................................................................ - -4. RESOLVED ISSUES - - - 4.1 ISE - - - NA - -................................................................................ - -5. KNOWN ISSUES - - - 5.1 ISE - - - The most recent information, including known issues, workarounds, and - resolutions for this version is provided in the IP Release Notes Guide - located at - - www.xilinx.com/support/documentation/user_guides/xtp025.pdf - - -................................................................................ - -6. TECHNICAL SUPPORT - - -To obtain technical support, create a WebCase at www.xilinx.com/support. -Questions are routed to a team with expertise using this product. - -Xilinx provides technical support for use of this product when used -according to the guidelines described in the core documentation, and -cannot guarantee timing, functionality, or support of this product for -designs that do not follow specified guidelines. - - -................................................................................ - -7. CORE RELEASE HISTORY - - -Date By Version Description -================================================================================ -04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support -01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support -06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support -03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support -12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support -09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support -07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support -04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support -12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support -09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support -06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support -04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support -================================================================================ - -................................................................................ - -8. LEGAL DISCLAIMER - -(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved. - -This file contains confidential and proprietary information -of Xilinx, Inc. and is protected under U.S. and -international copyright and other intellectual property -laws. - -DISCLAIMER -This disclaimer is not a license and does not grant any -rights to the materials distributed herewith. Except as -otherwise provided in a valid license issued to you by -Xilinx, and to the maximum extent permitted by applicable -law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -(2) Xilinx shall not be liable (whether in contract or tort, -including negligence, or under any other theory of -liability) for any loss or damage of any kind or nature -related to, arising under or in connection with these -materials, including for any direct, or any indirect, -special, incidental, or consequential loss or damage -(including loss of data, profits, goodwill, or any type of -loss or damage suffered as a result of any action brought -by a third party) even if such damage or loss was -reasonably foreseeable or Xilinx had been advised of the -possibility of the same. - -CRITICAL APPLICATIONS -Xilinx products are not designed or intended to be fail- -safe, or for use in any application requiring fail-safe -performance, such as life-support or safety devices or -systems, Class III medical devices, nuclear facilities, -applications related to the deployment of airbags, or any -other applications that could lead to death, personal -injury, or severe property or environmental damage -(individually and collectively, "Critical -Applications"). Customer assumes the sole risk and -liability of any use of Xilinx products in Critical -Applications, subject only to applicable laws and -regulations governing limitations on product liability. - -THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -PART OF THIS FILE AT ALL TIMES. - diff --git a/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html b/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html deleted file mode 100644 index 8dc6bb6ba..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html +++ /dev/null @@ -1,194 +0,0 @@ - - -clk_wiz_v3_5_vinfo - - - -

-		Core name: Xilinx LogiCORE Clocking Wizard
-                Version: 3.5
-                Release: ISE 14.1
-                Release Date: April 24, 2012
-
-
-================================================================================
-
-This document contains the following sections:
-
-1. Introduction
-2. New Features
-  2.1 ISE
-3. Supported Devices
-  3.1 ISE
-4. Resolved Issues
-  4.1 ISE
-5. Known Issues
-  5.1 ISE
-6. Technical Support
-7. Core Release History
-8. Legal Disclaimer
-
-================================================================================
-
-
-1. INTRODUCTION
-
-For installation instructions for this release, please go to:
-
-  www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
-
-For system requirements:
-
-   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
-
-This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.5
-solution. For the latest core updates, see the product page at:
-
-   www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
-
-................................................................................
-
-2. NEW FEATURES
-
-
-  2.1 ISE 
-  
-    - ISE 14.1 software support
-
-................................................................................
-
-3. SUPPORTED DEVICES
-
-
-  3.1 ISE 
-   
-  
-  The following device families are supported by the core for this release.
-  
-  All 7 Series devices
-
-
-  Zynq-7000 devices
-    Zynq-7000
-    Defense Grade Zynq-7000Q (XQ)
-
-
-  All Virtex-6 devices
-  
-  
-  All Spartan-6 devices
-  
-  
-................................................................................
-
-4. RESOLVED ISSUES
-
-
-  4.1 ISE 
-  
-  - NA
-
-................................................................................
-
-5. KNOWN ISSUES 
-
-
-  5.1 ISE 
-  
-  
-  The most recent information, including known issues, workarounds, and
-  resolutions for this version is provided in the IP Release Notes Guide
-  located at
-
-   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
-  
-  
-................................................................................
-
-6. TECHNICAL SUPPORT
-
-
-To obtain technical support, create a WebCase at www.xilinx.com/support.
-Questions are routed to a team with expertise using this product.
-
-Xilinx provides technical support for use of this product when used
-according to the guidelines described in the core documentation, and
-cannot guarantee timing, functionality, or support of this product for
-designs that do not follow specified guidelines.
-
-
-................................................................................
-
-7. CORE RELEASE HISTORY
-
-
-Date        By            Version      Description
-================================================================================
-04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
-01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
-06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
-03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
-12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
-09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
-07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
-04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
-12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
-09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
-06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
-04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
-================================================================================
-                          
-................................................................................
-
-8. LEGAL DISCLAIMER
-
-(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
-
-This file contains confidential and proprietary information
-of Xilinx, Inc. and is protected under U.S. and
-international copyright and other intellectual property
-laws.
-
-DISCLAIMER
-This disclaimer is not a license and does not grant any
-rights to the materials distributed herewith. Except as
-otherwise provided in a valid license issued to you by
-Xilinx, and to the maximum extent permitted by applicable
-law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-(2) Xilinx shall not be liable (whether in contract or tort,
-including negligence, or under any other theory of
-liability) for any loss or damage of any kind or nature
-related to, arising under or in connection with these
-materials, including for any direct, or any indirect,
-special, incidental, or consequential loss or damage
-(including loss of data, profits, goodwill, or any type of
-loss or damage suffered as a result of any action brought
-by a third party) even if such damage or loss was
-reasonably foreseeable or Xilinx had been advised of the
-possibility of the same.
-
-CRITICAL APPLICATIONS
-Xilinx products are not designed or intended to be fail-
-safe, or for use in any application requiring fail-safe
-performance, such as life-support or safety devices or
-systems, Class III medical devices, nuclear facilities,
-applications related to the deployment of airbags, or any
-other applications that could lead to death, personal
-injury, or severe property or environmental damage
-(individually and collectively, "Critical
-Applications"). Customer assumes the sole risk and
-liability of any use of Xilinx products in Critical
-Applications, subject only to applicable laws and
-regulations governing limitations on product liability.
-
-THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-PART OF THIS FILE AT ALL TIMES.
-
-
-
- - diff --git a/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.ucf b/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.ucf deleted file mode 100755 index 1892548b4..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.ucf +++ /dev/null @@ -1,72 +0,0 @@ -# file: pll_100_40_75_exdes.ucf -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# Input clock periods. These duplicate the values entered for the -# input clocks. You can use these to time your system -#---------------------------------------------------------------- -NET "CLK_IN1" TNM_NET = "CLK_IN1"; -TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 25.000 ns HIGH 50% INPUT_JITTER 250.0ps; - -# Derived clock periods. These are commented out because they are -# automatically propogated by the tools -# However, if you'd like to use them for module level testing, you -# can copy them into your module level timing checks -#----------------------------------------------------------------- -# NET "clk_int[1]" TNM_NET = "CLK_OUT1"; -# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 100.000 MHz; - -# NET "clk_int[2]" TNM_NET = "CLK_OUT2"; -# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 40.000 MHz; -# NET "clk_int[3]" TNM_NET = "CLK_OUT3"; -# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 75.000 MHz; - -# FALSE PATH constraints -PIN "COUNTER_RESET" TIG; -PIN "RESET" TIG; - diff --git a/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.v b/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.v deleted file mode 100755 index a79d6ab10..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.v +++ /dev/null @@ -1,160 +0,0 @@ -// file: pll_100_40_75_exdes.v -// -// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// - -//---------------------------------------------------------------------------- -// Clocking wizard example design -//---------------------------------------------------------------------------- -// This example design instantiates the created clocking network, where each -// output clock drives a counter. The high bit of each counter is ported. -//---------------------------------------------------------------------------- - -`timescale 1ps/1ps - -module pll_100_40_75_exdes - #( - parameter TCQ = 100 - ) - (// Clock in ports - input CLK_IN1, - // Reset that only drives logic in example design - input COUNTER_RESET, - output [3:1] CLK_OUT, - // High bits of counters driven by clocks - output [3:1] COUNT, - // Status and control signals - input RESET, - output LOCKED - ); - - // Parameters for the counters - //------------------------------- - // Counter width - localparam C_W = 16; - // Number of counters - localparam NUM_C = 3; - genvar count_gen; - // When the clock goes out of lock, reset the counters - wire reset_int = !LOCKED || RESET || COUNTER_RESET; - - reg [NUM_C:1] rst_sync; - reg [NUM_C:1] rst_sync_int; - reg [NUM_C:1] rst_sync_int1; - reg [NUM_C:1] rst_sync_int2; - - - // Declare the clocks and counters - wire [NUM_C:1] clk_int; - wire [NUM_C:1] clk; - reg [C_W-1:0] counter [NUM_C:1]; - - // Instantiation of the clocking network - //-------------------------------------- - pll_100_40_75 clknetwork - (// Clock in ports - .CLK_IN1 (CLK_IN1), - // Clock out ports - .CLK_OUT1 (clk_int[1]), - .CLK_OUT2 (clk_int[2]), - .CLK_OUT3 (clk_int[3]), - // Status and control signals - .RESET (RESET), - .LOCKED (LOCKED)); - - assign CLK_OUT = clk_int; - - // Connect the output clocks to the design - //----------------------------------------- - assign clk[1] = clk_int[1]; - assign clk[2] = clk_int[2]; - assign clk[3] = clk_int[3]; - - - // Reset synchronizer - //----------------------------------- - generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1 - always @(posedge reset_int or posedge clk[count_gen]) begin - if (reset_int) begin - rst_sync[count_gen] <= 1'b1; - rst_sync_int[count_gen]<= 1'b1; - rst_sync_int1[count_gen]<= 1'b1; - rst_sync_int2[count_gen]<= 1'b1; - end - else begin - rst_sync[count_gen] <= 1'b0; - rst_sync_int[count_gen] <= rst_sync[count_gen]; - rst_sync_int1[count_gen] <= rst_sync_int[count_gen]; - rst_sync_int2[count_gen] <= rst_sync_int1[count_gen]; - end - end - end - endgenerate - - - // Output clock sampling - //----------------------------------- - generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters - - always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin - if (rst_sync_int2[count_gen]) begin - counter[count_gen] <= #TCQ { C_W { 1'b 0 } }; - end else begin - counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1; - end - end - // alias the high bit of each counter to the corresponding - // bit in the output bus - assign COUNT[count_gen] = counter[count_gen][C_W-1]; - end - endgenerate - - - - - -endmodule diff --git a/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.xdc b/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.xdc deleted file mode 100755 index bd0f53e4e..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.xdc +++ /dev/null @@ -1,69 +0,0 @@ -# file: pll_100_40_75_exdes.xdc -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# Input clock periods. These duplicate the values entered for the -# input clocks. You can use these to time your system -#---------------------------------------------------------------- -create_clock -name CLK_IN1 -period 25.000 [get_ports CLK_IN1] -set_propagated_clock CLK_IN1 -set_input_jitter CLK_IN1 0.25 - -# FALSE PATH constraint added on COUNTER_RESET -set_false_path -from [get_ports "COUNTER_RESET"] -set_false_path -from [get_ports "RESET"] - -# Derived clock periods. These are commented out because they are -# automatically propogated by the tools -# However, if you'd like to use them for module level testing, you -# can copy them into your module level timing checks -#----------------------------------------------------------------- - -#----------------------------------------------------------------- - -#----------------------------------------------------------------- diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/implement.bat b/fpga/usrp2/coregen/pll_100_40_75/implement/implement.bat deleted file mode 100755 index a362117a4..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/implement/implement.bat +++ /dev/null @@ -1,90 +0,0 @@ -REM file: implement.bat -REM -REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -REM -REM This file contains confidential and proprietary information -REM of Xilinx, Inc. and is protected under U.S. and -REM international copyright and other intellectual property -REM laws. -REM -REM DISCLAIMER -REM This disclaimer is not a license and does not grant any -REM rights to the materials distributed herewith. Except as -REM otherwise provided in a valid license issued to you by -REM Xilinx, and to the maximum extent permitted by applicable -REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -REM (2) Xilinx shall not be liable (whether in contract or tort, -REM including negligence, or under any other theory of -REM liability) for any loss or damage of any kind or nature -REM related to, arising under or in connection with these -REM materials, including for any direct, or any indirect, -REM special, incidental, or consequential loss or damage -REM (including loss of data, profits, goodwill, or any type of -REM loss or damage suffered as a result of any action brought -REM by a third party) even if such damage or loss was -REM reasonably foreseeable or Xilinx had been advised of the -REM possibility of the same. -REM -REM CRITICAL APPLICATIONS -REM Xilinx products are not designed or intended to be fail- -REM safe, or for use in any application requiring fail-safe -REM performance, such as life-support or safety devices or -REM systems, Class III medical devices, nuclear facilities, -REM applications related to the deployment of airbags, or any -REM other applications that could lead to death, personal -REM injury, or severe property or environmental damage -REM (individually and collectively, "Critical -REM Applications"). Customer assumes the sole risk and -REM liability of any use of Xilinx products in Critical -REM Applications, subject only to applicable laws and -REM regulations governing limitations on product liability. -REM -REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -REM PART OF THIS FILE AT ALL TIMES. -REM - -REM ----------------------------------------------------------------------------- -REM Script to synthesize and implement the RTL provided for the clocking wizard -REM ----------------------------------------------------------------------------- - -REM Clean up the results directory -rmdir /S /Q results -mkdir results - -REM Copy unisim_comp.v file to results directory -copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\ - -REM Synthesize the Verilog Wrapper Files -echo 'Synthesizing Clocking Wizard design with XST' -xst -ifn xst.scr -move pll_100_40_75_exdes.ngc results\ - -REM Copy the constraints files generated by Coregen -echo 'Copying files from constraints directory to results directory' -copy ..\example_design\pll_100_40_75_exdes.ucf results\ - -cd results - -echo 'Running ngdbuild' -ngdbuild -uc pll_100_40_75_exdes.ucf pll_100_40_75_exdes - -echo 'Running map' -map -timing -pr b pll_100_40_75_exdes -o mapped.ncd - -echo 'Running par' -par -w mapped.ncd routed mapped.pcf - -echo 'Running trce' -trce -e 10 routed -o routed mapped.pcf - -echo 'Running design through bitgen' -bitgen -w routed - -echo 'Running netgen to create gate level model for the clocking wizard example design' -netgen -ofmt verilog -sim -sdf_anno false -tm pll_100_40_75_exdes -w routed.ncd routed.v -cd .. - diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/implement.sh b/fpga/usrp2/coregen/pll_100_40_75/implement/implement.sh deleted file mode 100755 index e3ff2ce97..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/implement/implement.sh +++ /dev/null @@ -1,91 +0,0 @@ -#!/bin/sh -# file: implement.sh -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -#----------------------------------------------------------------------------- -# Script to synthesize and implement the RTL provided for the clocking wizard -#----------------------------------------------------------------------------- - -# Clean up the results directory -rm -rf results -mkdir results - -# Copy unisim_comp.v file to results directory -cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/ - -# Synthesize the Verilog Wrapper Files -echo 'Synthesizing Clocking Wizard design with XST' -xst -ifn xst.scr -mv pll_100_40_75_exdes.ngc results/ - -# Copy the constraints files generated by Coregen -echo 'Copying files from constraints directory to results directory' -cp ../example_design/pll_100_40_75_exdes.ucf results/ - -cd results - -echo 'Running ngdbuild' -ngdbuild -uc pll_100_40_75_exdes.ucf pll_100_40_75_exdes - -echo 'Running map' -map -timing pll_100_40_75_exdes -o mapped.ncd - -echo 'Running par' -par -w mapped.ncd routed mapped.pcf - -echo 'Running trce' -trce -e 10 routed -o routed mapped.pcf - -echo 'Running design through bitgen' -bitgen -w routed - -echo 'Running netgen to create gate level model for the clocking wizard example design' -netgen -ofmt verilog -sim -sdf_anno false -tm pll_100_40_75_exdes -w routed.ncd routed.v - -cd .. diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.bat b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.bat deleted file mode 100755 index 8ac771810..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.bat +++ /dev/null @@ -1,58 +0,0 @@ -REM file: planAhead_ise.bat -REM -REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -REM -REM This file contains confidential and proprietary information -REM of Xilinx, Inc. and is protected under U.S. and -REM international copyright and other intellectual property -REM laws. -REM -REM DISCLAIMER -REM This disclaimer is not a license and does not grant any -REM rights to the materials distributed herewith. Except as -REM otherwise provided in a valid license issued to you by -REM Xilinx, and to the maximum extent permitted by applicable -REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -REM (2) Xilinx shall not be liable (whether in contract or tort, -REM including negligence, or under any other theory of -REM liability) for any loss or damage of any kind or nature -REM related to, arising under or in connection with these -REM materials, including for any direct, or any indirect, -REM special, incidental, or consequential loss or damage -REM (including loss of data, profits, goodwill, or any type of -REM loss or damage suffered as a result of any action brought -REM by a third party) even if such damage or loss was -REM reasonably foreseeable or Xilinx had been advised of the -REM possibility of the same. -REM -REM CRITICAL APPLICATIONS -REM Xilinx products are not designed or intended to be fail- -REM safe, or for use in any application requiring fail-safe -REM performance, such as life-support or safety devices or -REM systems, Class III medical devices, nuclear facilities, -REM applications related to the deployment of airbags, or any -REM other applications that could lead to death, personal -REM injury, or severe property or environmental damage -REM (individually and collectively, "Critical -REM Applications"). Customer assumes the sole risk and -REM liability of any use of Xilinx products in Critical -REM Applications, subject only to applicable laws and -REM regulations governing limitations on product liability. -REM -REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -REM PART OF THIS FILE AT ALL TIMES. -REM - -REM----------------------------------------------------------------------------- -REM Script to synthesize and implement the RTL provided for the clocking wizard -REM----------------------------------------------------------------------------- - -del \f results -mkdir results -cd results - -planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.sh b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.sh deleted file mode 100755 index 6c8c837d3..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.sh +++ /dev/null @@ -1,59 +0,0 @@ -#!/bin/sh -# file: planAhead_ise.sh -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -#----------------------------------------------------------------------------- -# Script to synthesize and implement the RTL provided for the clocking wizard -#----------------------------------------------------------------------------- - -rm -rf results -mkdir results -cd results - -planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.tcl b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.tcl deleted file mode 100755 index f4e6c57ae..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.tcl +++ /dev/null @@ -1,78 +0,0 @@ -# file: planAhead_ise.tcl -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -set projDir [file dirname [info script]] -set projName pll_100_40_75 -set topName pll_100_40_75_exdes -set device xc6slx75csg484-3 - -create_project $projName $projDir/results/$projName -part $device - -set_property design_mode RTL [get_filesets sources_1] - -## Source files -#set verilogSources [glob $srcDir/*.v] -import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/pll_100_40_75_exdes.v -import_files -fileset [get_filesets sources_1] -force -norecurse ../../../pll_100_40_75.v - - -#UCF file -import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/pll_100_40_75_exdes.ucf - -set_property top $topName [get_property srcset [current_run]] - -launch_runs -runs synth_1 -wait_on_run synth_1 - -set_property add_step Bitgen [get_runs impl_1] -launch_runs -runs impl_1 -wait_on_run impl_1 - - - diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.bat b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.bat deleted file mode 100755 index 42273f5d4..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.bat +++ /dev/null @@ -1,58 +0,0 @@ -REM file: planAhead_rdn.sh -REM -REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -REM -REM This file contains confidential and proprietary information -REM of Xilinx, Inc. and is protected under U.S. and -REM international copyright and other intellectual property -REM laws. -REM -REM DISCLAIMER -REM This disclaimer is not a license and does not grant any -REM rights to the materials distributed herewith. Except as -REM otherwise provided in a valid license issued to you by -REM Xilinx, and to the maximum extent permitted by applicable -REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -REM (2) Xilinx shall not be liable (whether in contract or tort, -REM including negligence, or under any other theory of -REM liability) for any loss or damage of any kind or nature -REM related to, arising under or in connection with these -REM materials, including for any direct, or any indirect, -REM special, incidental, or consequential loss or damage -REM (including loss of data, profits, goodwill, or any type of -REM loss or damage suffered as a result of any action brought -REM by a third party) even if such damage or loss was -REM reasonably foreseeable or Xilinx had been advised of the -REM possibility of the same. -REM -REM CRITICAL APPLICATIONS -REM Xilinx products are not designed or intended to be fail- -REM safe, or for use in any application requiring fail-safe -REM performance, such as life-support or safety devices or -REM systems, Class III medical devices, nuclear facilities, -REM applications related to the deployment of airbags, or any -REM other applications that could lead to death, personal -REM injury, or severe property or environmental damage -REM (individually and collectively, "Critical -REM Applications"). Customer assumes the sole risk and -REM liability of any use of Xilinx products in Critical -REM Applications, subject only to applicable laws and -REM regulations governing limitations on product liability. -REM -REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -REM PART OF THIS FILE AT ALL TIMES. -REM - -REM----------------------------------------------------------------------------- -REM Script to synthesize and implement the RTL provided for the XADC wizard -REM----------------------------------------------------------------------------- - -del \f results -mkdir results -cd results - -planAhead -mode batch -source ..\planAhead_rdn.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.sh b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.sh deleted file mode 100755 index f4c14729e..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.sh +++ /dev/null @@ -1,57 +0,0 @@ -#!/bin/sh -# file: planAhead_rdn.sh -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -#----------------------------------------------------------------------------- -# Script to synthesize and implement the RTL provided for the XADC wizard -#----------------------------------------------------------------------------- -rm -rf results -mkdir results -cd results -planAhead -mode batch -source ../planAhead_rdn.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.tcl b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.tcl deleted file mode 100755 index 56f9c65af..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.tcl +++ /dev/null @@ -1,69 +0,0 @@ -# file : planAhead_rdn.tcl -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -set device xc6slx75csg484-3 -set projName pll_100_40_75 -set design pll_100_40_75 -set projDir [file dirname [info script]] -create_project $projName $projDir/results/$projName -part $device -force -set_property design_mode RTL [current_fileset -srcset] -set top_module pll_100_40_75_exdes -set_property top pll_100_40_75_exdes [get_property srcset [current_run]] -add_files -norecurse {../../../pll_100_40_75.v} -add_files -norecurse {../../example_design/pll_100_40_75_exdes.v} -import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/pll_100_40_75_exdes.xdc} -synth_design -opt_design -place_design -route_design -write_sdf -rename_top_module pll_100_40_75_exdes -file routed.sdf -write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module pll_100_40_75_exdes -file routed.v -report_timing -nworst 30 -path_type full -file routed.twr -report_drc -file report.drc -write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/xst.prj b/fpga/usrp2/coregen/pll_100_40_75/implement/xst.prj deleted file mode 100755 index 8409c83dd..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/implement/xst.prj +++ /dev/null @@ -1,2 +0,0 @@ -verilog work ../../pll_100_40_75.v -verilog work ../example_design/pll_100_40_75_exdes.v diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/xst.scr b/fpga/usrp2/coregen/pll_100_40_75/implement/xst.scr deleted file mode 100755 index af176e2e4..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/implement/xst.scr +++ /dev/null @@ -1,9 +0,0 @@ -run --ifmt MIXED --top pll_100_40_75_exdes --p xc6slx75-csg484-3 --ifn xst.prj --ofn pll_100_40_75_exdes --keep_hierarchy soft --equivalent_register_removal no --max_fanout 65535 diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simcmds.tcl b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simcmds.tcl deleted file mode 100755 index 6692a790e..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simcmds.tcl +++ /dev/null @@ -1,8 +0,0 @@ -# file: simcmds.tcl - -# create the simulation script -vcd dumpfile isim.vcd -vcd dumpvars -m /pll_100_40_75_tb -l 0 -wave add / -run 50000ns -quit diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.bat b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.bat deleted file mode 100755 index 783ddc0e3..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.bat +++ /dev/null @@ -1,59 +0,0 @@ -REM file: simulate_isim.bat -REM -REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -REM -REM This file contains confidential and proprietary information -REM of Xilinx, Inc. and is protected under U.S. and -REM international copyright and other intellectual property -REM laws. -REM -REM DISCLAIMER -REM This disclaimer is not a license and does not grant any -REM rights to the materials distributed herewith. Except as -REM otherwise provided in a valid license issued to you by -REM Xilinx, and to the maximum extent permitted by applicable -REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -REM (2) Xilinx shall not be liable (whether in contract or tort, -REM including negligence, or under any other theory of -REM liability) for any loss or damage of any kind or nature -REM related to, arising under or in connection with these -REM materials, including for any direct, or any indirect, -REM special, incidental, or consequential loss or damage -REM (including loss of data, profits, goodwill, or any type of -REM loss or damage suffered as a result of any action brought -REM by a third party) even if such damage or loss was -REM reasonably foreseeable or Xilinx had been advised of the -REM possibility of the same. -REM -REM CRITICAL APPLICATIONS -REM Xilinx products are not designed or intended to be fail- -REM safe, or for use in any application requiring fail-safe -REM performance, such as life-support or safety devices or -REM systems, Class III medical devices, nuclear facilities, -REM applications related to the deployment of airbags, or any -REM other applications that could lead to death, personal -REM injury, or severe property or environmental damage -REM (individually and collectively, "Critical -REM Applications"). Customer assumes the sole risk and -REM liability of any use of Xilinx products in Critical -REM Applications, subject only to applicable laws and -REM regulations governing limitations on product liability. -REM -REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -REM PART OF THIS FILE AT ALL TIMES. -REM - -vlogcomp -work work %XILINX%\verilog\src\glbl.v -vlogcomp -work work ..\..\..\pll_100_40_75.v -vlogcomp -work work ..\..\example_design\pll_100_40_75_exdes.v -vlogcomp -work work ..\pll_100_40_75_tb.v - -REM compile the project -fuse work.pll_100_40_75_tb work.glbl -L unisims_ver -o pll_100_40_75_isim.exe - -REM run the simulation script -.\pll_100_40_75_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.sh deleted file mode 100755 index cb197ed97..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.sh +++ /dev/null @@ -1,61 +0,0 @@ -# file: simulate_isim.sh -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# lin -# create the project -vlogcomp -work work ${XILINX}/verilog/src/glbl.v -vlogcomp -work work ../../../pll_100_40_75.v -vlogcomp -work work ../../example_design/pll_100_40_75_exdes.v -vlogcomp -work work ../pll_100_40_75_tb.v - -# compile the project -fuse work.pll_100_40_75_tb work.glbl -L unisims_ver -o pll_100_40_75_isim.exe - -# run the simulation script -./pll_100_40_75_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.bat b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.bat deleted file mode 100755 index 756d94e7a..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.bat +++ /dev/null @@ -1,61 +0,0 @@ -REM file: simulate_mti.bat -REM -REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -REM -REM This file contains confidential and proprietary information -REM of Xilinx, Inc. and is protected under U.S. and -REM international copyright and other intellectual property -REM laws. -REM -REM DISCLAIMER -REM This disclaimer is not a license and does not grant any -REM rights to the materials distributed herewith. Except as -REM otherwise provided in a valid license issued to you by -REM Xilinx, and to the maximum extent permitted by applicable -REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -REM (2) Xilinx shall not be liable (whether in contract or tort, -REM including negligence, or under any other theory of -REM liability) for any loss or damage of any kind or nature -REM related to, arising under or in connection with these -REM materials, including for any direct, or any indirect, -REM special, incidental, or consequential loss or damage -REM (including loss of data, profits, goodwill, or any type of -REM loss or damage suffered as a result of any action brought -REM by a third party) even if such damage or loss was -REM reasonably foreseeable or Xilinx had been advised of the -REM possibility of the same. -REM -REM CRITICAL APPLICATIONS -REM Xilinx products are not designed or intended to be fail- -REM safe, or for use in any application requiring fail-safe -REM performance, such as life-support or safety devices or -REM systems, Class III medical devices, nuclear facilities, -REM applications related to the deployment of airbags, or any -REM other applications that could lead to death, personal -REM injury, or severe property or environmental damage -REM (individually and collectively, "Critical -REM Applications"). Customer assumes the sole risk and -REM liability of any use of Xilinx products in Critical -REM Applications, subject only to applicable laws and -REM regulations governing limitations on product liability. -REM -REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -REM PART OF THIS FILE AT ALL TIMES. -REM - -REM set up the working directory -vlib work - -REM compile all of the files -vlog -work work %XILINX%\verilog\src\glbl.v -vlog -work work ..\..\..\pll_100_40_75.v -vlog -work work ..\..\example_design\pll_100_40_75_exdes.v -vlog -work work ..\pll_100_40_75_tb.v - -REM run the simulation -vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.pll_100_40_75_tb work.glbl - diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.do b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.do deleted file mode 100755 index c74e73aa5..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.do +++ /dev/null @@ -1,65 +0,0 @@ -# file: simulate_mti.do -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# set up the working directory -set work work -vlib work - -# compile all of the files -vlog -work work $env(XILINX)/verilog/src/glbl.v -vlog -work work ../../../pll_100_40_75.v -vlog -work work ../../example_design/pll_100_40_75_exdes.v -vlog -work work ../pll_100_40_75_tb.v - -# run the simulation -vsim -t ps -voptargs="+acc" -L unisims_ver work.pll_100_40_75_tb work.glbl -do wave.do -log pll_100_40_75_tb/dut/counter -log -r /* -run 50000ns diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.sh deleted file mode 100755 index a49ca05c6..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.sh +++ /dev/null @@ -1,61 +0,0 @@ -#/bin/sh -# file: simulate_mti.sh -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -# set up the working directory -set work work -vlib work - -# compile all of the files -vlog -work work $XILINX/verilog/src/glbl.v -vlog -work work ../../../pll_100_40_75.v -vlog -work work ../../example_design/pll_100_40_75_exdes.v -vlog -work work ../pll_100_40_75_tb.v - -# run the simulation -vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.pll_100_40_75_tb work.glbl diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_ncsim.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_ncsim.sh deleted file mode 100755 index 5978c8eb7..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_ncsim.sh +++ /dev/null @@ -1,62 +0,0 @@ -#/bin/sh -# file: simulate_ncsim.sh -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# set up the working directory -mkdir work - -# compile all of the files -ncvlog -work work ${XILINX}/verilog/src/glbl.v -ncvlog -work work ../../../pll_100_40_75.v -ncvlog -work work ../../example_design/pll_100_40_75_exdes.v -ncvlog -work work ../pll_100_40_75_tb.v - -# elaborate and run the simulation -ncelab -work work -access +wc work.pll_100_40_75_tb work.glbl -ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.pll_100_40_75_tb diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_vcs.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_vcs.sh deleted file mode 100755 index bebd99d7d..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_vcs.sh +++ /dev/null @@ -1,72 +0,0 @@ -#!/bin/sh -# file: simulate_vcs.sh -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# remove old files -rm -rf simv* csrc DVEfiles AN.DB - -# compile all of the files -# Note that -sverilog is not strictly required- You can -# remove the -sverilog if you change the type of the -# localparam for the periods in the testbench file to -# [63:0] from time -vlogan -sverilog \ - ${XILINX}/verilog/src/glbl.v \ - ../../../pll_100_40_75.v \ - ../../example_design/pll_100_40_75_exdes.v \ - ../pll_100_40_75_tb.v - -# prepare the simulation -vcs +vcs+lic+wait -debug pll_100_40_75_tb glbl - -# run the simulation -./simv -ucli -i ucli_commands.key - -# launch the viewer -dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/ucli_commands.key b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/ucli_commands.key deleted file mode 100755 index b56d68a2d..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/ucli_commands.key +++ /dev/null @@ -1,5 +0,0 @@ -call {$vcdpluson} -call {$vcdplusmemon(pll_100_40_75_tb.dut.counter)} -run -call {$vcdplusclose} -quit diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/vcs_session.tcl b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/vcs_session.tcl deleted file mode 100755 index 19b1ea0f5..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/vcs_session.tcl +++ /dev/null @@ -1,18 +0,0 @@ -gui_open_window Wave -gui_sg_create pll_100_40_75_group -gui_list_add_group -id Wave.1 {pll_100_40_75_group} -gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.test_phase} -gui_set_radix -radix {ascii} -signals {pll_100_40_75_tb.test_phase} -gui_sg_addsignal -group pll_100_40_75_group {{Input_clocks}} -divider -gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.CLK_IN1} -gui_sg_addsignal -group pll_100_40_75_group {{Output_clocks}} -divider -gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.dut.clk} -gui_list_expand -id Wave.1 pll_100_40_75_tb.dut.clk -gui_sg_addsignal -group pll_100_40_75_group {{Status_control}} -divider -gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.RESET} -gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.LOCKED} -gui_sg_addsignal -group pll_100_40_75_group {{Counters}} -divider -gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.COUNT} -gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.dut.counter} -gui_list_expand -id Wave.1 pll_100_40_75_tb.dut.counter -gui_zoom -window Wave.1 -full diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.do b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.do deleted file mode 100755 index 4178de1c7..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.do +++ /dev/null @@ -1,60 +0,0 @@ -# file: wave.do -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -add wave -noupdate -format Literal -radix ascii /pll_100_40_75_tb/test_phase -add wave -noupdate -divider {Input clocks} -add wave -noupdate -format Logic /pll_100_40_75_tb/CLK_IN1 -add wave -noupdate -divider {Output clocks} -add wave -noupdate -format Literal -expand /pll_100_40_75_tb/dut/clk -add wave -noupdate -divider Status/control -add wave -noupdate -format Logic /pll_100_40_75_tb/RESET -add wave -noupdate -format Logic /pll_100_40_75_tb/LOCKED -add wave -noupdate -divider Counters -add wave -noupdate -format Literal -radix hexadecimal /pll_100_40_75_tb/COUNT -add wave -noupdate -format Literal -radix hexadecimal -expand /pll_100_40_75_tb/dut/counter diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.sv b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.sv deleted file mode 100755 index 57e72bdec..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.sv +++ /dev/null @@ -1,119 +0,0 @@ -# file: wave.sv -# -# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -# Get the windows set up -# -if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} { - window geometry "Design Browser 1" 1054x819+536+322 -} -window target "Design Browser 1" on -browser using {Design Browser 1} -browser set \ - -scope nc::pll_100_40_75_tb -browser yview see nc::pll_100_40_75_tb -browser timecontrol set -lock 0 - -if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} { - window geometry "Waveform 1" 1010x600+0+541 -} -window target "Waveform 1" on -waveform using {Waveform 1} -waveform sidebar visibility partial -waveform set \ - -primarycursor TimeA \ - -signalnames name \ - -signalwidth 175 \ - -units ns \ - -valuewidth 75 -cursor set -using TimeA -time 0 -waveform baseline set -time 0 -waveform xview limits 0 20000n - -# -# Define signal groups -# -catch {group new -name {Output clocks} -overlay 0} -catch {group new -name {Status/control} -overlay 0} -catch {group new -name {Counters} -overlay 0} - -set id [waveform add -signals [list {nc::pll_100_40_75_tb.CLK_IN1}]] - -group using {Output clocks} -group set -overlay 0 -group set -comment {} -group clear 0 end - -group insert \ - {pll_100_40_75_tb.dut.clk[1]} \ - {pll_100_40_75_tb.dut.clk[2]} \ {pll_100_40_75_tb.dut.clk[3]} -group using {Counters} -group set -overlay 0 -group set -comment {} -group clear 0 end - -group insert \ - {pll_100_40_75_tb.dut.counter[1]} \ - {pll_100_40_75_tb.dut.counter[2]} \ {pll_100_40_75_tb.dut.counter[3]} -group using {Status/control} -group set -overlay 0 -group set -comment {} -group clear 0 end - -group insert \ - {nc::pll_100_40_75_tb.RESET} {nc::pll_100_40_75_tb.LOCKED} - - -set id [waveform add -signals [list {nc::pll_100_40_75_tb.COUNT} ]] - -set id [waveform add -signals [list {nc::pll_100_40_75_tb.test_phase} ]] -waveform format $id -radix %a - -set groupId [waveform add -groups {{Input clocks}}] -set groupId [waveform add -groups {{Output clocks}}] -set groupId [waveform add -groups {{Status/control}}] -set groupId [waveform add -groups {{Counters}}] diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/pll_100_40_75_tb.v b/fpga/usrp2/coregen/pll_100_40_75/simulation/pll_100_40_75_tb.v deleted file mode 100755 index fe800f0cc..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/pll_100_40_75_tb.v +++ /dev/null @@ -1,143 +0,0 @@ -// file: pll_100_40_75_tb.v -// -// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// - -//---------------------------------------------------------------------------- -// Clocking wizard demonstration testbench -//---------------------------------------------------------------------------- -// This demonstration testbench instantiates the example design for the -// clocking wizard. Input clocks are toggled, which cause the clocking -// network to lock and the counters to increment. -//---------------------------------------------------------------------------- - -`timescale 1ps/1ps - -`define wait_lock @(posedge LOCKED) - -module pll_100_40_75_tb (); - - // Clock to Q delay of 100ps - localparam TCQ = 100; - - - // timescale is 1ps/1ps - localparam ONE_NS = 1000; - localparam PHASE_ERR_MARGIN = 100; // 100ps - // how many cycles to run - localparam COUNT_PHASE = 1024; - // we'll be using the period in many locations - localparam time PER1 = 25.000*ONE_NS; - localparam time PER1_1 = PER1/2; - localparam time PER1_2 = PER1 - PER1/2; - - // Declare the input clock signals - reg CLK_IN1 = 1; - - // The high bits of the sampling counters - wire [3:1] COUNT; - // Status and control signals - reg RESET = 0; - wire LOCKED; - reg COUNTER_RESET = 0; -wire [3:1] CLK_OUT; -//Freq Check using the M & D values setting and actual Frequency generated - - - // Input clock generation - //------------------------------------ - always begin - CLK_IN1 = #PER1_1 ~CLK_IN1; - CLK_IN1 = #PER1_2 ~CLK_IN1; - end - - // Test sequence - reg [15*8-1:0] test_phase = ""; - initial begin - // Set up any display statements using time to be readable - $timeformat(-12, 2, "ps", 10); - COUNTER_RESET = 0; - test_phase = "reset"; - RESET = 1; - #(PER1*6); - RESET = 0; - test_phase = "wait lock"; - `wait_lock; - #(PER1*6); - COUNTER_RESET = 1; - #(PER1*20) - COUNTER_RESET = 0; - - test_phase = "counting"; - #(PER1*COUNT_PHASE); - - $display("SIMULATION PASSED"); - $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); - $finish; - end - - // Instantiation of the example design containing the clock - // network and sampling counters - //--------------------------------------------------------- - pll_100_40_75_exdes - #( - .TCQ (TCQ) - ) dut - (// Clock in ports - .CLK_IN1 (CLK_IN1), - // Reset for logic in example design - .COUNTER_RESET (COUNTER_RESET), - .CLK_OUT (CLK_OUT), - // High bits of the counters - .COUNT (COUNT), - // Status and control signals - .RESET (RESET), - .LOCKED (LOCKED)); - -// Freq Check - -endmodule diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/pll_100_40_75_tb.v b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/pll_100_40_75_tb.v deleted file mode 100755 index 0e6be6e9d..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/pll_100_40_75_tb.v +++ /dev/null @@ -1,157 +0,0 @@ -// file: pll_100_40_75_tb.v -// -// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// - -//---------------------------------------------------------------------------- -// Clocking wizard demonstration testbench -//---------------------------------------------------------------------------- -// This demonstration testbench instantiates the example design for the -// clocking wizard. Input clocks are toggled, which cause the clocking -// network to lock and the counters to increment. -//---------------------------------------------------------------------------- - -`timescale 1ps/1ps - -`define wait_lock @(posedge LOCKED) - -module pll_100_40_75_tb (); - - // Clock to Q delay of 100ps - localparam TCQ = 100; - - - // timescale is 1ps/1ps - localparam ONE_NS = 1000; - localparam PHASE_ERR_MARGIN = 100; // 100ps - // how many cycles to run - localparam COUNT_PHASE = 1024; - // we'll be using the period in many locations - localparam time PER1 = 25.000*ONE_NS; - localparam time PER1_1 = PER1/2; - localparam time PER1_2 = PER1 - PER1/2; - - // Declare the input clock signals - reg CLK_IN1 = 1; - - // The high bits of the sampling counters - wire [3:1] COUNT; - // Status and control signals - reg RESET = 0; - wire LOCKED; - reg COUNTER_RESET = 0; -wire [3:1] CLK_OUT; -//Freq Check using the M & D values setting and actual Frequency generated - - reg [13:0] timeout_counter = 14'b00000000000000; - - // Input clock generation - //------------------------------------ - always begin - CLK_IN1 = #PER1_1 ~CLK_IN1; - CLK_IN1 = #PER1_2 ~CLK_IN1; - end - - // Test sequence - reg [15*8-1:0] test_phase = ""; - initial begin - // Set up any display statements using time to be readable - $timeformat(-12, 2, "ps", 10); - $display ("Timing checks are not valid"); - COUNTER_RESET = 0; - test_phase = "reset"; - RESET = 1; - #(PER1*6); - RESET = 0; - test_phase = "wait lock"; - `wait_lock; - #(PER1*6); - COUNTER_RESET = 1; - #(PER1*19.5) - COUNTER_RESET = 0; - #(PER1*1) - $display ("Timing checks are valid"); - test_phase = "counting"; - #(PER1*COUNT_PHASE); - - $display("SIMULATION PASSED"); - $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); - $finish; - end - - - always@(posedge CLK_IN1) begin - timeout_counter <= timeout_counter + 1'b1; - if (timeout_counter == 14'b10000000000000) begin - if (LOCKED != 1'b1) begin - $display("ERROR : NO LOCK signal"); - $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); - $finish; - end - end - end - - // Instantiation of the example design containing the clock - // network and sampling counters - //--------------------------------------------------------- - pll_100_40_75_exdes - dut - (// Clock in ports - .CLK_IN1 (CLK_IN1), - // Reset for logic in example design - .COUNTER_RESET (COUNTER_RESET), - .CLK_OUT (CLK_OUT), - // High bits of the counters - .COUNT (COUNT), - // Status and control signals - .RESET (RESET), - .LOCKED (LOCKED)); - - -// Freq Check - -endmodule diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/sdf_cmd_file b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/sdf_cmd_file deleted file mode 100755 index 61dacfed8..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/sdf_cmd_file +++ /dev/null @@ -1,2 +0,0 @@ -COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X", -SCOPE = pll_100_40_75_tb.dut; diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simcmds.tcl b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simcmds.tcl deleted file mode 100755 index 857329884..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simcmds.tcl +++ /dev/null @@ -1,9 +0,0 @@ -# file: simcmds.tcl - -# create the simulation script -vcd dumpfile isim.vcd -vcd dumpvars -m /pll_100_40_75_tb -l 0 -wave add / -run 50000ns -quit - diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_isim.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_isim.sh deleted file mode 100755 index e3b06d7c5..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_isim.sh +++ /dev/null @@ -1,62 +0,0 @@ -# file: simulate_isim.sh -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# create the project -vlogcomp -work work ${XILINX}/verilog/src/glbl.v -vlogcomp -work work ../../implement/results/routed.v -vlogcomp -work work pll_100_40_75_tb.v - -# compile the project -fuse work.pll_100_40_75_tb work.glbl -L secureip -L simprims_ver -o pll_100_40_75_isim.exe - -# run the simulation script -./pll_100_40_75_isim.exe -tclbatch simcmds.tcl -sdfmax /pll_100_40_75_tb/dut=../../implement/results/routed.sdf - -# run the simulation script -#./pll_100_40_75_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.bat b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.bat deleted file mode 100755 index 7e5890086..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.bat +++ /dev/null @@ -1,59 +0,0 @@ -REM file: simulate_mti.bat -REM -REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -REM -REM This file contains confidential and proprietary information -REM of Xilinx, Inc. and is protected under U.S. and -REM international copyright and other intellectual property -REM laws. -REM -REM DISCLAIMER -REM This disclaimer is not a license and does not grant any -REM rights to the materials distributed herewith. Except as -REM otherwise provided in a valid license issued to you by -REM Xilinx, and to the maximum extent permitted by applicable -REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -REM (2) Xilinx shall not be liable (whether in contract or tort, -REM including negligence, or under any other theory of -REM liability) for any loss or damage of any kind or nature -REM related to, arising under or in connection with these -REM materials, including for any direct, or any indirect, -REM special, incidental, or consequential loss or damage -REM (including loss of data, profits, goodwill, or any type of -REM loss or damage suffered as a result of any action brought -REM by a third party) even if such damage or loss was -REM reasonably foreseeable or Xilinx had been advised of the -REM possibility of the same. -REM -REM CRITICAL APPLICATIONS -REM Xilinx products are not designed or intended to be fail- -REM safe, or for use in any application requiring fail-safe -REM performance, such as life-support or safety devices or -REM systems, Class III medical devices, nuclear facilities, -REM applications related to the deployment of airbags, or any -REM other applications that could lead to death, personal -REM injury, or severe property or environmental damage -REM (individually and collectively, "Critical -REM Applications"). Customer assumes the sole risk and -REM liability of any use of Xilinx products in Critical -REM Applications, subject only to applicable laws and -REM regulations governing limitations on product liability. -REM -REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -REM PART OF THIS FILE AT ALL TIMES. -REM -# set up the working directory -set work work -vlib work - -REM compile all of the files -vlog -work work %XILINX%\verilog\src\glbl.v -vlog -work work ..\..\implement\results\routed.v -vlog -work work pll_100_40_75_tb.v - -REM run the simulation -vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax pll_100_40_75_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.pll_100_40_75_tb work.glbl diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.do b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.do deleted file mode 100755 index 03f8a3965..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.do +++ /dev/null @@ -1,65 +0,0 @@ -# file: simulate_mti.do -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# set up the working directory -set work work -vlib work - -# compile all of the files -vlog -work work $env(XILINX)/verilog/src/glbl.v -vlog -work work ../../implement/results/routed.v -vlog -work work pll_100_40_75_tb.v - -# run the simulation -vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax pll_100_40_75_tb/dut=../../implement/results/routed.sdf +no_notifier work.pll_100_40_75_tb work.glbl -#do wave.do -#log -r /* -run 50000ns - - diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.sh deleted file mode 100755 index 055768aa8..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.sh +++ /dev/null @@ -1,61 +0,0 @@ -#/bin/sh -# file: simulate_mti.sh -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# set up the working directory -set work work -vlib work - -# compile all of the files -vlog -work work $XILINX/verilog/src/glbl.v -vlog -work work ../../implement/results/routed.v -vlog -work work pll_100_40_75_tb.v - -# run the simulation -vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax pll_100_40_75_tb/dut=../../implement/results/routed.sdf +no_notifier work.pll_100_40_75_tb work.glbl diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_ncsim.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_ncsim.sh deleted file mode 100755 index aa3a2b441..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_ncsim.sh +++ /dev/null @@ -1,64 +0,0 @@ -#!/bin/sh -# file: simulate_ncsim.sh -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# set up the working directory -mkdir work - -# compile all of the files -ncvlog -work work ${XILINX}/verilog/src/glbl.v -ncvlog -work work ../../implement/results/routed.v -ncvlog -work work pll_100_40_75_tb.v - -# elaborate and run the simulation -ncsdfc ../../implement/results/routed.sdf - -ncelab -work work -access +wc -pulse_r 10 -nonotifier work.pll_100_40_75_tb work.glbl -sdf_cmd_file sdf_cmd_file -ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.pll_100_40_75_tb - diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_vcs.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_vcs.sh deleted file mode 100755 index 3cc21dd69..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_vcs.sh +++ /dev/null @@ -1,72 +0,0 @@ -#!/bin/sh -# file: simulate_vcs.sh -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# remove old files -rm -rf simv* csrc DVEfiles AN.DB - -# compile all of the files -# Note that -sverilog is not strictly required- You can -# remove the -sverilog if you change the type of the -# localparam for the periods in the testbench file to -# [63:0] from time - vlogan -sverilog \ - pll_100_40_75_tb.v \ - ../../implement/results/routed.v - - -# prepare the simulation -vcs -sdf max:pll_100_40_75_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \ - +libext+.v -debug pll_100_40_75_tb.v ../../implement/results/routed.v - -# run the simulation -./simv -ucli -i ucli_commands.key - -# launch the viewer -#dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/ucli_commands.key b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/ucli_commands.key deleted file mode 100755 index 0548d1733..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/ucli_commands.key +++ /dev/null @@ -1,5 +0,0 @@ - -call {$vcdpluson} -run 50000ns -call {$vcdplusclose} -quit diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/vcs_session.tcl b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/vcs_session.tcl deleted file mode 100755 index 1438f6bed..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/vcs_session.tcl +++ /dev/null @@ -1 +0,0 @@ -gui_open_window Wave diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/wave.do b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/wave.do deleted file mode 100755 index fe9b59354..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/wave.do +++ /dev/null @@ -1,72 +0,0 @@ -# file: wave.do -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate /pll_100_40_75_tb/CLK_IN1 -add wave -noupdate /pll_100_40_75_tb/COUNT -add wave -noupdate /pll_100_40_75_tb/LOCKED -add wave -noupdate /pll_100_40_75_tb/RESET -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {3223025 ps} 0} -configure wave -namecolwidth 238 -configure wave -valuecolwidth 107 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ps -update -WaveRestoreZoom {0 ps} {74848022 ps} diff --git a/fpga/usrp2/coregen/pll_100_40_75_exdes.ncf b/fpga/usrp2/coregen/pll_100_40_75_exdes.ncf deleted file mode 100644 index ddff6a6e9..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75_exdes.ncf +++ /dev/null @@ -1,73 +0,0 @@ -# file: pll_100_40_75_exdes.ucf -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# Input clock periods. These duplicate the values entered for the -# input clocks. You can use these to time your system -#---------------------------------------------------------------- -NET "CLK_IN1" TNM_NET = "CLK_IN1"; -TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 25.000 ns HIGH 50% INPUT_JITTER 250.0ps; - -# Derived clock periods. These are commented out because they are -# automatically propogated by the tools -# However, if you'd like to use them for module level testing, you -# can copy them into your module level timing checks -#----------------------------------------------------------------- -# NET "clk_int[1]" TNM_NET = "CLK_OUT1"; -# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 100.000 MHz; - -# NET "clk_int[2]" TNM_NET = "CLK_OUT2"; -# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 40.000 MHz; -# NET "clk_int[3]" TNM_NET = "CLK_OUT3"; -# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 75.000 MHz; - -# FALSE PATH constraints -PIN "COUNTER_RESET" TIG; -PIN "RESET" TIG; - - diff --git a/fpga/usrp2/coregen/pll_100_40_75_flist.txt b/fpga/usrp2/coregen/pll_100_40_75_flist.txt deleted file mode 100644 index 04c7f882d..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75_flist.txt +++ /dev/null @@ -1,54 +0,0 @@ -# Output products list for -_xmsgs/pn_parser.xmsgs -pll_100_40_75/clk_wiz_v3_5_readme.txt -pll_100_40_75/doc/clk_wiz_gsg521.pdf -pll_100_40_75/doc/clk_wiz_v3_5_readme.txt -pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html -pll_100_40_75/example_design/pll_100_40_75_exdes.ucf -pll_100_40_75/example_design/pll_100_40_75_exdes.v -pll_100_40_75/example_design/pll_100_40_75_exdes.xdc -pll_100_40_75/implement/implement.bat -pll_100_40_75/implement/implement.sh -pll_100_40_75/implement/planAhead_ise.bat -pll_100_40_75/implement/planAhead_ise.sh -pll_100_40_75/implement/planAhead_ise.tcl -pll_100_40_75/implement/planAhead_rdn.bat -pll_100_40_75/implement/planAhead_rdn.sh -pll_100_40_75/implement/planAhead_rdn.tcl -pll_100_40_75/implement/xst.prj -pll_100_40_75/implement/xst.scr -pll_100_40_75/simulation/functional/simcmds.tcl -pll_100_40_75/simulation/functional/simulate_isim.bat -pll_100_40_75/simulation/functional/simulate_isim.sh -pll_100_40_75/simulation/functional/simulate_mti.bat -pll_100_40_75/simulation/functional/simulate_mti.do -pll_100_40_75/simulation/functional/simulate_mti.sh -pll_100_40_75/simulation/functional/simulate_ncsim.sh -pll_100_40_75/simulation/functional/simulate_vcs.sh -pll_100_40_75/simulation/functional/ucli_commands.key -pll_100_40_75/simulation/functional/vcs_session.tcl -pll_100_40_75/simulation/functional/wave.do -pll_100_40_75/simulation/functional/wave.sv -pll_100_40_75/simulation/pll_100_40_75_tb.v -pll_100_40_75/simulation/timing/pll_100_40_75_tb.v -pll_100_40_75/simulation/timing/sdf_cmd_file -pll_100_40_75/simulation/timing/simcmds.tcl -pll_100_40_75/simulation/timing/simulate_isim.sh -pll_100_40_75/simulation/timing/simulate_mti.bat -pll_100_40_75/simulation/timing/simulate_mti.do -pll_100_40_75/simulation/timing/simulate_mti.sh -pll_100_40_75/simulation/timing/simulate_ncsim.sh -pll_100_40_75/simulation/timing/simulate_vcs.sh -pll_100_40_75/simulation/timing/ucli_commands.key -pll_100_40_75/simulation/timing/vcs_session.tcl -pll_100_40_75/simulation/timing/wave.do -pll_100_40_75.asy -pll_100_40_75.gise -pll_100_40_75.ucf -pll_100_40_75.v -pll_100_40_75.veo -pll_100_40_75.xco -pll_100_40_75.xdc -pll_100_40_75.xise -pll_100_40_75_flist.txt -pll_100_40_75_xmdf.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75_xmdf.tcl b/fpga/usrp2/coregen/pll_100_40_75_xmdf.tcl deleted file mode 100755 index 18eee6e1a..000000000 --- a/fpga/usrp2/coregen/pll_100_40_75_xmdf.tcl +++ /dev/null @@ -1,144 +0,0 @@ -# The package naming convention is _xmdf -package provide pll_100_40_75_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::pll_100_40_75_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::pll_100_40_75_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name pll_100_40_75 -} -# ::pll_100_40_75_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::pll_100_40_75_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/clk_wiz_readme.txt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/example_design/pll_100_40_75_exdes.ucf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/doc/clk_wiz_ds709.pdf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/doc/clk_wiz_gsg521.pdf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/example_design/pll_100_40_75_exdes.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/implement/implement.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/implement/implement.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/implement/xst.prj -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/implement/xst.scr -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/pll_100_40_75_tb.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simcmds.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simulate_isim.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simulate_mti.do -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simulate_ncsim.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simulate_vcs.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/ucli_commands.key -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/vcs_session.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/wave.do -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/wave.sv -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.asy -utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.ejp -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module pll_100_40_75 -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/custom/custom_dsp_rx.v b/fpga/usrp2/custom/custom_dsp_rx.v deleted file mode 100644 index 355adf008..000000000 --- a/fpga/usrp2/custom/custom_dsp_rx.v +++ /dev/null @@ -1,71 +0,0 @@ -// -// Copyright 2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -//COPY ME, CUSTOMIZE ME... - -//The following module effects the IO of the DDC chain. -//By default, this entire module is a simple pass-through. - -//To implement DSP logic before the DDC: -//Implement custom DSP between frontend and ddc input. - -//To implement DSP logic after the DDC: -//Implement custom DSP between ddc output and baseband. - -//To bypass the DDC with custom logic: -//Implement custom DSP between frontend and baseband. - -module custom_dsp_rx -#( - //frontend bus width - parameter WIDTH = 24 -) -( - //control signals - input clock, //dsp clock - input reset, //active high synchronous reset - input clear, //active high on packet control init - input enable, //active high when streaming enabled - - //user settings bus, controlled through user setting regs API - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - //full rate inputs directly from the RX frontend - input [WIDTH-1:0] frontend_i, - input [WIDTH-1:0] frontend_q, - - //full rate outputs directly to the DDC chain - output [WIDTH-1:0] ddc_in_i, - output [WIDTH-1:0] ddc_in_q, - - //strobed samples {I16,Q16} from the RX DDC chain - input [31:0] ddc_out_sample, - input ddc_out_strobe, //high on valid sample - output ddc_out_enable, //enables DDC module - - //strobbed baseband samples {I16,Q16} from this module - output [31:0] bb_sample, - output bb_strobe //high on valid sample -); - - assign ddc_in_i = frontend_i; - assign ddc_in_q = frontend_q; - assign bb_sample = ddc_out_sample; - assign bb_strobe = ddc_out_strobe; - assign ddc_out_enable = enable; - -endmodule //custom_dsp_rx diff --git a/fpga/usrp2/custom/custom_dsp_tx.v b/fpga/usrp2/custom/custom_dsp_tx.v deleted file mode 100644 index 0848a187f..000000000 --- a/fpga/usrp2/custom/custom_dsp_tx.v +++ /dev/null @@ -1,71 +0,0 @@ -// -// Copyright 2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -//COPY ME, CUSTOMIZE ME... - -//The following module effects the IO of the DUC chain. -//By default, this entire module is a simple pass-through. - -//To implement DSP logic before the DUC: -//Implement custom DSP between baseband and duc input. - -//To implement DSP logic after the DUC: -//Implement custom DSP between duc output and frontend. - -//To bypass the DUC with custom logic: -//Implement custom DSP between baseband and frontend. - -module custom_dsp_tx -#( - //frontend bus width - parameter WIDTH = 24 -) -( - //control signals - input clock, //dsp clock - input reset, //active high synchronous reset - input clear, //active high on packet control init - input enable, //active high when streaming enabled - - //user settings bus, controlled through user setting regs API - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - //full rate outputs directly to the TX frontend - output [WIDTH-1:0] frontend_i, - output [WIDTH-1:0] frontend_q, - - //full rate outputs directly from the DUC chain - input [WIDTH-1:0] duc_out_i, - input [WIDTH-1:0] duc_out_q, - - //strobed samples {I16,Q16} to the TX DUC chain - output [31:0] duc_in_sample, - input duc_in_strobe, //this is a backpressure signal - output duc_in_enable, //enables DUC module - - //strobbed baseband samples {I16,Q16} to this module - input [31:0] bb_sample, - output bb_strobe //this is a backpressure signal -); - - assign frontend_i = duc_out_i; - assign frontend_q = duc_out_q; - assign duc_in_sample = bb_sample; - assign bb_strobe = duc_in_strobe; - assign duc_in_enable = enable; - -endmodule //custom_dsp_tx diff --git a/fpga/usrp2/custom/custom_engine_rx.v b/fpga/usrp2/custom/custom_engine_rx.v deleted file mode 100644 index dfeaad2cd..000000000 --- a/fpga/usrp2/custom/custom_engine_rx.v +++ /dev/null @@ -1,53 +0,0 @@ -// -// Copyright 2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -//COPY ME, CUSTOMIZE ME... - -//The following module is used to re-write receive packets to the host. -//This module provides a packet-based ram interface for manipulating packets. -//The user writes a custom engine (state machine) to read the input packet, -//and to produce a new output packet. - -//By default, this entire module is a simple pass-through. - -module custom_engine_rx -#( - //buffer size for ram interface engine - parameter BUF_SIZE = 10 -) -( - //control signals - input clock, input reset, input clear, - - //user settings bus, controlled through user setting regs API - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - //ram interface for engine - output access_we, - output access_stb, - input access_ok, - output access_done, - output access_skip_read, - output [BUF_SIZE-1:0] access_adr, - input [BUF_SIZE-1:0] access_len, - output [35:0] access_dat_o, - input [35:0] access_dat_i -); - - assign access_done = access_ok; - -endmodule //custom_engine_rx diff --git a/fpga/usrp2/custom/custom_engine_tx.v b/fpga/usrp2/custom/custom_engine_tx.v deleted file mode 100644 index 9be728484..000000000 --- a/fpga/usrp2/custom/custom_engine_tx.v +++ /dev/null @@ -1,57 +0,0 @@ -// -// Copyright 2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -//COPY ME, CUSTOMIZE ME... - -//The following module is used to re-write transmit packets from the host. -//This module provides a packet-based ram interface for manipulating packets. -//The user writes a custom engine (state machine) to read the input packet, -//and to produce a new output packet. - -//By default, this entire module is a simple pass-through. - -module custom_engine_tx -#( - //buffer size for ram interface engine - parameter BUF_SIZE = 10, - - //the number of 32bit lines between start of buffer and vita header - //the metadata before the header should be preserved by the engine - parameter HEADER_OFFSET = 0 -) -( - //control signals - input clock, input reset, input clear, - - //user settings bus, controlled through user setting regs API - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - //ram interface for engine - output access_we, - output access_stb, - input access_ok, - output access_done, - output access_skip_read, - output [BUF_SIZE-1:0] access_adr, - input [BUF_SIZE-1:0] access_len, - output [35:0] access_dat_o, - input [35:0] access_dat_i -); - - assign access_done = access_ok; - -endmodule //custom_engine_tx diff --git a/fpga/usrp2/custom/power_trig.v b/fpga/usrp2/custom/power_trig.v deleted file mode 100644 index b38059030..000000000 --- a/fpga/usrp2/custom/power_trig.v +++ /dev/null @@ -1,130 +0,0 @@ -// -// Copyright 2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// This a power trigger module implemented on top of the custom dsp template. -// Power triggering is implemented after the existing DDC chain. -// Triggering is controlled via user settings registers. - -// Register 0: -// threshold for power trigger -// 32 bit unsigned fixed-point number of some arbitrary scaling - -module power_trig -#( - //frontend bus width - parameter WIDTH = 24, - parameter BASE = 0 -) -( - //control signals - input clock, //dsp clock - input reset, //active high synchronous reset - input clear, //active high on packet control init - input enable, //active high when streaming enabled - - //user settings bus, controlled through user setting regs API - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - //full rate inputs directly from the RX frontend - input [WIDTH-1:0] frontend_i, - input [WIDTH-1:0] frontend_q, - - //full rate outputs directly to the DDC chain - output [WIDTH-1:0] ddc_in_i, - output [WIDTH-1:0] ddc_in_q, - - //strobed samples {I16,Q16} from the RX DDC chain - input [31:0] ddc_out_sample, - input ddc_out_strobe, //high on valid sample - output ddc_out_enable, //enables DDC module - - //strobbed baseband samples {I16,Q16} from this module - output [31:0] bb_sample, - output bb_strobe //high on valid sample -); - - //leave frontend tied to existing ddc chain - assign ddc_in_i = frontend_i; - assign ddc_in_q = frontend_q; - - //ddc enable remains tied to global enable - assign ddc_out_enable = enable; - - //below we implement a power trigger between baseband samples and ddc output... - - reg [8:0] wr_addr; - wire [8:0] rd_addr; - reg triggered, triggerable; - wire trigger; - - wire [31:0] delayed_sample; - wire [31:0] thresh; - - setting_reg #(.my_addr(BASE+0)) sr_0 - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(thresh),.changed()); - - assign rd_addr = wr_addr + 1; // FIXME adjustable delay - - ram_2port #(.DWIDTH(32),.AWIDTH(9)) delay_line - (.clka(clk),.ena(1),.wea(ddc_out_strobe),.addra(wr_addr),.dia(ddc_out_sample),.doa(), - .clkb(clk),.enb(ddc_out_strobe),.web(1'b0),.addrb(rd_addr),.dib(32'hFFFF),.dob(delayed_sample)); - - always @(posedge clock) - if(reset | ~enable) - wr_addr <= 0; - else - if(ddc_out_strobe) - wr_addr <= wr_addr + 1; - - always @(posedge clock) - if(reset | ~enable) - triggerable <= 0; - else if(wr_addr == 9'h1FF) // Wait till we're nearly full - triggerable <= 1; - - - reg stb_d1, stb_d2; - always @(posedge clock) stb_d1 <= ddc_out_strobe; - always @(posedge clock) stb_d2 <= stb_d1; - - assign bb_sample = delayed_sample; - assign bb_strobe = stb_d1 & triggered; - - // Compute Mag - wire [17:0] mult_in = stb_d1 ? { ddc_out_sample[15],ddc_out_sample[15:0], 1'b0 } : - { ddc_out_sample[31], ddc_out_sample[31:16], 1'b0 }; - wire [35:0] prod; - reg [31:0] sum; - - MULT18X18S mult (.P(prod), .A(mult_in), .B(mult_in), .C(clock), .CE(ddc_out_strobe | stb_d1), .R(reset) ); - - always @(posedge clock) - if(stb_d1) - sum <= prod[35:4]; - else if(stb_d2) - sum <= sum + prod[35:4]; - - always @(posedge clock) - if(reset | ~enable | ~triggerable) - triggered <= 0; - else if(trigger) - triggered <= 1; - - assign trigger = (sum > thresh); - -endmodule // power_trig diff --git a/fpga/usrp2/custom/power_trig_tb.v b/fpga/usrp2/custom/power_trig_tb.v deleted file mode 100644 index b8f3385ce..000000000 --- a/fpga/usrp2/custom/power_trig_tb.v +++ /dev/null @@ -1,71 +0,0 @@ -// -// Copyright 2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module power_trig_tb(); - initial $dumpfile("power_trig_tb.vcd"); - initial $dumpvars(0,power_trig_tb); - - reg clk = 0; - always #10 clk <= ~clk; - reg rst = 1; - initial #100 rst <= 0; - - initial - begin - set_stb <= 0; - #1000; - set_stb <= 1; - end - - reg [31:0] sample_in; - reg strobe_in; - wire [31:0] sample_out; - wire strobe_out; - reg set_stb, run; - - power_trig #(.BASE(0)) power_trig - (.clk(clk), .reset(rst), .enable(1), - .set_stb(set_stb), .set_addr(0), .set_data(32'h000B_B000), - .run(run), - - .ddc_out_sample(sample_in), .ddc_out_strobe(strobe_in), - .bb_sample(sample_out), .bb_strobe(strobe_out)); - - initial sample_in <= 32'h0100_0300; - - always @(posedge clk) - if(~strobe_in) - sample_in <= sample_in + 32'h0001_0001; - - initial - #100000 $finish; - - initial - begin - run <= 0; - #2000 run <= 1; - #30000 run <= 0; - end - - always @(posedge clk) - if(rst | ~run) - strobe_in <= 0; - else - strobe_in <= ~strobe_in; - -endmodule // power_trig_tb diff --git a/fpga/usrp2/extramfifo/.gitignore b/fpga/usrp2/extramfifo/.gitignore deleted file mode 100644 index 94bbf6dcc..000000000 --- a/fpga/usrp2/extramfifo/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -fifo_extram36_tb -fifo_extram_tb -*.vcd diff --git a/fpga/usrp2/extramfifo/Makefile.srcs b/fpga/usrp2/extramfifo/Makefile.srcs deleted file mode 100644 index b255ef916..000000000 --- a/fpga/usrp2/extramfifo/Makefile.srcs +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright 2010 Ettus Research LLC -# - -################################################## -# Extram Sources -################################################## -EXTRAM_SRCS = $(abspath $(addprefix $(BASE_DIR)/../extramfifo/, \ -ext_fifo.v \ -nobl_if.v \ -nobl_fifo.v \ -icon.v \ -icon.xco \ -ila.v \ -ila.xco \ -refill_randomizer.v \ -)) diff --git a/fpga/usrp2/extramfifo/ext_fifo.v b/fpga/usrp2/extramfifo/ext_fifo.v deleted file mode 100644 index 620f4dddd..000000000 --- a/fpga/usrp2/extramfifo/ext_fifo.v +++ /dev/null @@ -1,188 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// -// FIFO backed by an off chip ZBT/NoBL SRAM. -// -// This module and its sub-hierarchy implment a FIFO capable of sustaining -// a data throughput rate of at least int_clk/2 * 36bits and bursts of int_clk * 36bits. -// -// This has been designed and tested for an int_clk of 100MHz and an ext_clk of 125MHz, -// your milage may vary with other clock ratio's especially those where int_clk < ext_clk. -// Testing has also exclusively used a rst signal synchronized to int_clk. -// -// Interface operation mimics a Xilinx FIFO configured as "First Word Fall Through", -// though signal naming differs. -// -// For FPGA use registers interfacing directly with signals prefixed "RAM_*" should be -// packed into the IO ring. -// - - //`define NO_EXT_FIFO - -module ext_fifo - #(parameter INT_WIDTH=36,EXT_WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19) - ( - input int_clk, - input ext_clk, - input rst, - input [EXT_WIDTH-1:0] RAM_D_pi, - output [EXT_WIDTH-1:0] RAM_D_po, - output RAM_D_poe, - output [RAM_DEPTH-1:0] RAM_A, - output RAM_WEn, - output RAM_CENn, - output RAM_LDn, - output RAM_OEn, - output RAM_CE1n, - input [INT_WIDTH-1:0] datain, - input src_rdy_i, // WRITE - output dst_rdy_o, // not FULL - output [INT_WIDTH-1:0] dataout, - output src_rdy_o, // not EMPTY - input dst_rdy_i, // READ - output reg [31:0] debug, - output reg [31:0] debug2 - ); - - wire [EXT_WIDTH-1:0] write_data; - wire [EXT_WIDTH-1:0] read_data; - wire full1, empty1; - wire almost_full2, almost_full2_spread, full2, empty2; - wire [FIFO_DEPTH-1:0] capacity; - wire space_avail; - wire data_avail; - - // These next 2 lines here purely because ICARUS is crap at handling generate statements. - // Empirically this has been determined to make simulations work. - wire read_input_fifo = space_avail & ~empty1; - wire write_output_fifo = data_avail; - - assign src_rdy_o = ~empty2; - assign dst_rdy_o = ~full1; - -`ifdef NO_EXT_FIFO - assign space_avail = ~full2; - assign data_avail = ~empty1; - assign read_data = write_data; -`else - - // External FIFO running at ext clock rate and 18 or 36 bit width. - nobl_fifo #(.WIDTH(EXT_WIDTH),.RAM_DEPTH(RAM_DEPTH),.FIFO_DEPTH(FIFO_DEPTH)) - nobl_fifo_i1 - ( - .clk(ext_clk), - .rst(rst), - .RAM_D_pi(RAM_D_pi), - .RAM_D_po(RAM_D_po), - .RAM_D_poe(RAM_D_poe), - .RAM_A(RAM_A), - .RAM_WEn(RAM_WEn), - .RAM_CENn(RAM_CENn), - .RAM_LDn(RAM_LDn), - .RAM_OEn(RAM_OEn), - .RAM_CE1n(RAM_CE1n), - .write_data(write_data), - .write_strobe(~empty1 ), - .space_avail(space_avail), - .read_data(read_data), - .read_strobe(~almost_full2_spread), - .data_avail(data_avail), - .capacity(capacity) - ); -`endif // !`ifdef NO_EXT_FIFO - - - generate - if (EXT_WIDTH == 18 && INT_WIDTH == 36) begin: fifo_g1 - // FIFO buffers data from UDP engine into external FIFO clock domain. - fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 ( - .rst(rst), - .wr_clk(int_clk), - .rd_clk(ext_clk), - .din(datain), // Bus [35 : 0] - .wr_en(src_rdy_i), - .rd_en(read_input_fifo), - .dout(write_data), // Bus [17 : 0] - .full(full1), - .empty(empty1)); - - - // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP. - fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 ( - .rst(rst), - .wr_clk(ext_clk), - .rd_clk(int_clk), - .din(read_data), // Bus [17 : 0] - .wr_en(write_output_fifo), - .rd_en(dst_rdy_i), - .dout(dataout), // Bus [35 : 0] - .full(full2), - .prog_full(almost_full2), - .empty(empty2)); - end // block: fifo_g1 - else if (EXT_WIDTH == 36 && INT_WIDTH == 36) begin: fifo_g1 - // FIFO buffers data from UDP engine into external FIFO clock domain. - fifo_xlnx_32x36_2clk fifo_xlnx_32x36_2clk_i1 ( - .rst(rst), - .wr_clk(int_clk), - .rd_clk(ext_clk), - .din(datain), // Bus [35 : 0] - .wr_en(src_rdy_i), - .rd_en(read_input_fifo), - .dout(write_data), // Bus [35 : 0] - .full(full1), - .empty(empty1)); - - // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP. - fifo_xlnx_512x36_2clk_prog_full fifo_xlnx_32x36_2clk_prog_full_i1 ( - .rst(rst), - .wr_clk(ext_clk), - .rd_clk(int_clk), - .din(read_data), // Bus [35 : 0] - .wr_en(write_output_fifo), - .rd_en(dst_rdy_i), - .dout(dataout), // Bus [35 : 0] - .full(full2), - .empty(empty2), - .prog_full(almost_full2)); - - end - endgenerate - - - refill_randomizer #(.BITS(7)) - refill_randomizer_i1 ( - .clk(ext_clk), - .rst(rst), - .full_in(almost_full2), - .full_out(almost_full2_spread) - ); - -// always @ (posedge int_clk) -// debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i }; - - always @ (posedge ext_clk) - // debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 }; - debug[31:0] <= {7'h0,src_rdy_i,read_input_fifo,write_output_fifo,dst_rdy_i,full2,almost_full2,empty2,full1,empty1,write_data[7:0],read_data[7:0]}; - - - always@ (posedge ext_clk) - // debug2[31:0] <= {write_data[15:0],read_data[15:0]}; - debug2[31:0] <= 0; - -endmodule // ext_fifo diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.cmd b/fpga/usrp2/extramfifo/ext_fifo_tb.cmd deleted file mode 100644 index 521f88f21..000000000 --- a/fpga/usrp2/extramfifo/ext_fifo_tb.cmd +++ /dev/null @@ -1,12 +0,0 @@ -/opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/glbl.v --y . --y ../coregen/ --y ../fifo --y ../models --y /home/ianb/usrp-fpga/usrp2/sdr_lib --y /home/ianb/usrp-fpga/usrp2/control_lib --y /home/ianb/usrp-fpga/usrp2/models --y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/unisims --y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src --y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/XilinxCoreLib - diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.prj b/fpga/usrp2/extramfifo/ext_fifo_tb.prj deleted file mode 100644 index a11a15b2f..000000000 --- a/fpga/usrp2/extramfifo/ext_fifo_tb.prj +++ /dev/null @@ -1,9 +0,0 @@ -verilog work "./ext_fifo_tb.v" -verilog work "./ext_fifo.v" -verilog work "./nobl_fifo.v" -verilog work "./nobl_if.v" -verilog work "../coregen/fifo_xlnx_512x36_2clk_36to18.v" -verilog work "../coregen/fifo_xlnx_512x36_2clk_18to36.v" -verilog work "../models/CY7C1356C/cy1356.v" -verilog work "../models/idt71v65603s150.v" -verilog work "$XILINX/verilog/src/glbl.v" diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.sav b/fpga/usrp2/extramfifo/ext_fifo_tb.sav deleted file mode 100644 index a54b40fc5..000000000 --- a/fpga/usrp2/extramfifo/ext_fifo_tb.sav +++ /dev/null @@ -1,30 +0,0 @@ -[timestart] 0 -[size] 1523 832 -[pos] -1 -1 -*-15.000000 66300 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] ext_fifo_tb. -[treeopen] ext_fifo_tb.ext_fifo_i1. -[treeopen] ext_fifo_tb.ext_fifo_i1.nobl_fifo_i1. -@28 -ext_fifo_tb.ext_fifo_i1.src_rdy_i -ext_fifo_tb.ext_fifo_i1.dst_rdy_o -@22 -ext_fifo_tb.ext_fifo_i1.datain[35:0] -@28 -ext_fifo_tb.ext_fifo_i1.src_rdy_o -ext_fifo_tb.ext_fifo_i1.dst_rdy_i -@22 -ext_fifo_tb.ext_fifo_i1.dataout[35:0] -ext_fifo_tb.ext_fifo_i1.RAM_A[17:0] -@28 -ext_fifo_tb.ext_fifo_i1.RAM_WEn -ext_fifo_tb.ext_fifo_i1.RAM_CE1n -@22 -ext_fifo_tb.ext_fifo_i1.RAM_D_pi[35:0] -ext_fifo_tb.ext_fifo_i1.RAM_D_po[35:0] -ext_fifo_tb.ext_fifo_i1.write_data[35:0] -@28 -ext_fifo_tb.ext_fifo_i1.full1 -ext_fifo_tb.ext_fifo_i1.empty1 -@29 -ext_fifo_tb.ext_fifo_i1.space_avail diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.sh b/fpga/usrp2/extramfifo/ext_fifo_tb.sh deleted file mode 100755 index dcfede37a..000000000 --- a/fpga/usrp2/extramfifo/ext_fifo_tb.sh +++ /dev/null @@ -1,2 +0,0 @@ -#fuse -prj ext_fifo_tb.prj -t work.glbl -t work.ext_fifo_tb -L unisims_ver -L xilinxcorelib_ver -o ext_fifo_tb -iverilog -c ext_fifo_tb.cmd -o ext_fifo_tb ext_fifo_tb.v diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.v b/fpga/usrp2/extramfifo/ext_fifo_tb.v deleted file mode 100644 index f6fe47297..000000000 --- a/fpga/usrp2/extramfifo/ext_fifo_tb.v +++ /dev/null @@ -1,432 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -`timescale 1ns / 1ps -`define USRP2 -//`define USRP2PLUS - -`ifdef USRP2 - `define INT_WIDTH 36 - `define EXT_WIDTH 18 - `define RAM_DEPTH 19 - `define FIFO_DEPTH 8 - `define DUMP_VCD_FULL - `define INT_CLK_PERIOD 5 - `define EXT_CLK_PERIOD 4 -`elsif USRP2PLUS - `define INT_WIDTH 36 - `define EXT_WIDTH 36 - `define RAM_DEPTH 18 - `define FIFO_DEPTH 8 - `define DUMP_VCD_FULL - `define INT_CLK_PERIOD 5 - `define EXT_CLK_PERIOD 5 -`endif // `ifdef USRP2 - - -module ext_fifo_tb(); - - reg int_clk; - reg ext_clk; - reg rst; - - wire [`EXT_WIDTH-1:0] RAM_D_pi; - wire [`EXT_WIDTH-1:0] RAM_D_po; - wire [`EXT_WIDTH-1:0] RAM_D; - wire RAM_D_poe; - wire [`RAM_DEPTH-1:0] RAM_A; - wire RAM_WEn; - wire RAM_CENn; - wire RAM_LDn; - wire RAM_OEn; - wire RAM_CE1n; - reg [`INT_WIDTH-1:0] datain; - reg src_rdy_i; // WRITE - wire dst_rdy_o; // not FULL - wire [`INT_WIDTH-1:0] dataout; - reg [`INT_WIDTH-1:0] ref_dataout; - wire src_rdy_o; // not EMPTY - reg dst_rdy_i; - integer ether_frame; - - // Clocks - // Int clock is 100MHz - // Ext clock is 125MHz - initial - begin - int_clk <= 0; - ext_clk <= 0; - ref_dataout <= 1; - src_rdy_i <= 0; - dst_rdy_i <= 0; - end - - always - #(`INT_CLK_PERIOD/2) int_clk <= ~int_clk; - - always - #(`EXT_CLK_PERIOD/2) ext_clk <= ~ext_clk; - - initial - begin - datain <= 0; - ether_frame <= 0; - - rst <= 1; - repeat (5) @(negedge int_clk); - rst <= 0; - @(negedge int_clk); - while (datain < 10000) - begin - @(negedge int_clk); - datain <= datain + dst_rdy_o; - src_rdy_i <= dst_rdy_o; - // Simulate inter-frame time - if (ether_frame == 1500) - begin - ether_frame <= 0; - repeat(1600) - begin - @(negedge int_clk); - src_rdy_i <= 0; - end - end - else - ether_frame <= ether_frame + dst_rdy_o; - end - end // initial begin - - - initial - begin - repeat (5) @(negedge int_clk); - dst_rdy_i <= 1; - - while (src_rdy_o !== 1) - @(negedge int_clk); - - // Fall through fifo, first output already valid - if (dataout !== ref_dataout) - $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); - ref_dataout <= ref_dataout + src_rdy_o ; - - // Decimate by 16 rate - while (ref_dataout < 2000) - begin - @(negedge int_clk); - ref_dataout <= ref_dataout + src_rdy_o ; - dst_rdy_i <= src_rdy_o; - if ((dataout !== ref_dataout) && src_rdy_o) - $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); - @(negedge int_clk); - dst_rdy_i <= 0; - repeat(14) @(negedge int_clk); - end // while (ref_dataout < 10000) - // Decimate by 8 rate - while (ref_dataout < 4000) - begin - @(negedge int_clk); - ref_dataout <= ref_dataout + src_rdy_o ; - dst_rdy_i <= src_rdy_o; - if ((dataout !== ref_dataout) && src_rdy_o) - $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); - @(negedge int_clk); - dst_rdy_i <= 0; - repeat(6) @(negedge int_clk); - end // while (ref_dataout < 10000) - // Decimate by 4 rate - while (ref_dataout < 6000) - begin - @(negedge int_clk); - ref_dataout <= ref_dataout + src_rdy_o ; - dst_rdy_i <= src_rdy_o; - if ((dataout !== ref_dataout) && src_rdy_o) - $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); - @(negedge int_clk); - dst_rdy_i <= 0; - repeat(2) @(negedge int_clk); - end // while (ref_dataout < 10000) - // Max rate - while (ref_dataout < 10000) - begin - @(negedge int_clk); - ref_dataout <= ref_dataout + src_rdy_o ; - dst_rdy_i <= src_rdy_o; - if ((dataout !== ref_dataout) && src_rdy_o) - $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); - - end // while (ref_dataout < 10000) - - @(negedge int_clk); - $finish; - - end - - -/* -----\/----- EXCLUDED -----\/----- - - initial - begin - rst <= 1; - repeat (5) @(negedge int_clk); - rst <= 0; - @(negedge int_clk); - repeat (4000) - begin - @(negedge int_clk); - datain <= datain + dst_rdy_o; - src_rdy_i <= dst_rdy_o; -// @(negedge int_clk); -// src_rdy_i <= 0; -// @(negedge int_clk); -// dst_rdy_i <= src_rdy_o; -// @(negedge int_clk); -// dst_rdy_i <= 0; -// repeat (2) @(negedge int_clk); - end // repeat (1000) - // Fall through fifo, first output already valid - if (dataout !== ref_dataout) - $display("Error: Expected %x, got %x",ref_dataout, dataout); - repeat (1000) - begin - @(negedge int_clk); - datain <= datain + dst_rdy_o ; - src_rdy_i <= dst_rdy_o; - @(negedge int_clk); - src_rdy_i <= 0; - @(negedge int_clk); - ref_dataout <= ref_dataout + src_rdy_o ; - dst_rdy_i <= src_rdy_o; - if ((dataout !== ref_dataout) && src_rdy_o) - $display("Error: Expected %x, got %x",ref_dataout, dataout); - @(negedge int_clk); - dst_rdy_i <= 0; -// repeat (2) @(negedge int_clk); - end // repeat (1000) - repeat (1000) - begin -// @(negedge int_clk); -// datain <= datain + 1; -// src_rdy_i <= 1; -// @(negedge int_clk); -// src_rdy_i <= 0; - @(negedge int_clk); - ref_dataout <= ref_dataout + src_rdy_o; - dst_rdy_i <= src_rdy_o; - if ((dataout !== ref_dataout) && src_rdy_o) - $display("Error: Expected %x, got %x",ref_dataout, dataout); - @(negedge int_clk); - dst_rdy_i <= 0; -// repeat (2) @(negedge int_clk); - end // repeat (1000) - - $finish; - - end // initial begin - - - -----/\----- EXCLUDED -----/\----- */ - /////////////////////////////////////////////////////////////////////////////////// - // Simulation control // - /////////////////////////////////////////////////////////////////////////////////// - `ifdef DUMP_LX2_TOP - // Set up output files - initial begin - $dumpfile("ext_fifo_tb.lx2"); - $dumpvars(1,ext_fifo_tb); - end - `endif - - `ifdef DUMP_LX2_FULL - // Set up output files - initial begin - $dumpfile("ext_fifo_tb.lx2"); - $dumpvars(0,ext_fifo_tb); - end - `endif - - `ifdef DUMP_VCD_TOP - // Set up output files - initial begin - $dumpfile("ext_fifo_tb.vcd"); - $dumpvars(1,ext_fifo_tb); - end - `endif - - `ifdef DUMP_VCD_TOP_PLUS_NEXT - // Set up output files - initial begin - $dumpfile("ext_fifo_tb.vcd"); - $dumpvars(2,ext_fifo_tb); - end - `endif - - - `ifdef DUMP_VCD_FULL - // Set up output files - initial begin - $dumpfile("ext_fifo_tb.vcd"); - $dumpvars(0,ext_fifo_tb); - end - `endif - - // Update display every 10 us - always #10000 $monitor("Time in uS ",$time/1000); - - wire [`EXT_WIDTH-1:0] RAM_D_pi_ext; - wire [`EXT_WIDTH-1:0] RAM_D_po_ext; - wire [`EXT_WIDTH-1:0] RAM_D_ext; - wire RAM_D_poe_ext; - - genvar i; - - // - // Instantiate IO for Bidirectional bus to SRAM - // - - generate - for (i=0;i<`EXT_WIDTH;i=i+1) - begin : gen_RAM_D_IO - - IOBUF #( - .DRIVE(12), - .IOSTANDARD("LVCMOS25"), - .SLEW("FAST") - ) - RAM_D_i ( - .O(RAM_D_pi_ext[i]), - .I(RAM_D_po_ext[i]), - .IO(RAM_D[i]), - .T(RAM_D_poe_ext) - ); - end // block: gen_RAM_D_IO - - endgenerate - - wire [`RAM_DEPTH-1:0] RAM_A_ext; - wire RAM_WEn_ext,RAM_LDn_ext,RAM_CE1n_ext,RAM_OEn_ext,RAM_CENn_ext; - - assign #1 RAM_D_pi = RAM_D_pi_ext; - - assign #1 RAM_D_po_ext = RAM_D_po; - - assign #1 RAM_D_poe_ext = RAM_D_poe; - - assign #2 RAM_WEn_ext = RAM_WEn; - - assign #2 RAM_LDn_ext = RAM_LDn; - - assign #2 RAM_CE1n_ext = RAM_CE1n; - - assign #2 RAM_OEn_ext = RAM_OEn; - - assign #2 RAM_CENn_ext = RAM_CENn; - - assign #2 RAM_A_ext = RAM_A; - - - generate - if (`EXT_WIDTH==18) begin: ram_tb_g1 - idt71v65603s150 idt71v65603s150_i1 - ( - .A(RAM_A_ext[17:0]), - .adv_ld_(RAM_LDn_ext), // advance (high) / load (low) - .bw1_(1'b0), - .bw2_(1'b0), - .bw3_(1'b1), - .bw4_(1'b1), // byte write enables (low) - .ce1_(RAM_CE1n_ext), - .ce2(1'b1), - .ce2_(1'b0), // chip enables - .cen_(RAM_CENn_ext), // clock enable (low) - .clk(ext_clk), // clock - .IO({RAM_D[16:9],RAM_D[7:0]}), - .IOP({RAM_D[17],RAM_D[8]}), // data bus - .lbo_(1'b0), // linear burst order (low) - .oe_(RAM_OEn_ext), // output enable (low) - .r_w_(RAM_WEn_ext) - ); // read (high) / write (low) - end // block: ram_tb_g1 - else if (`EXT_WIDTH==36) begin: ram_tb_g1 - idt71v65603s150 idt71v65603s150_i1 - ( - .A(RAM_A_ext[17:0]), - .adv_ld_(RAM_LDn_ext), // advance (high) / load (low) - .bw1_(1'b0), - .bw2_(1'b0), - .bw3_(1'b0), - .bw4_(1'b0), // byte write enables (low) - .ce1_(RAM_CE1n_ext), - .ce2(1'b1), - .ce2_(1'b0), // chip enables - .cen_(RAM_CENn_ext), // clock enable (low) - .clk(ext_clk), // clock - .IO(RAM_D[31:0]), - .IOP(RAM_D[35:32]), // data bus - .lbo_(1'b0), // linear burst order (low) - .oe_(RAM_OEn_ext), // output enable (low) - .r_w_(RAM_WEn_ext) - ); // read (high) / write (low) - end // block: ram_tb_g1 - - endgenerate - -/* -----\/----- EXCLUDED -----\/----- - - - cy1356 cy1356_i1 - ( .d(RAM_D), - .clk(ext_clk), - .a(RAM_A_ext), - .bws(2'b00), - .we_b(RAM_WEn_ext), - .adv_lb(RAM_LDn_ext), - .ce1b(RAM_CE1n_ext), - .ce2(1'b1), - .ce3b(1'b0), - .oeb(RAM_OEn_ext), - .cenb(RAM_CENn_ext), - .mode(1'b0) - ); - -----/\----- EXCLUDED -----/\----- */ - - - ext_fifo - #(.INT_WIDTH(`INT_WIDTH),.EXT_WIDTH(`EXT_WIDTH),.RAM_DEPTH(`RAM_DEPTH),.FIFO_DEPTH(`FIFO_DEPTH)) - ext_fifo_i1 - ( - .int_clk(int_clk), - .ext_clk(ext_clk), - .rst(rst), - .RAM_D_pi(RAM_D_pi), - .RAM_D_po(RAM_D_po), - .RAM_D_poe(RAM_D_poe), - .RAM_A(RAM_A), - .RAM_WEn(RAM_WEn), - .RAM_CENn(RAM_CENn), - .RAM_LDn(RAM_LDn), - .RAM_OEn(RAM_OEn), - .RAM_CE1n(RAM_CE1n), - .datain(datain), - .src_rdy_i(src_rdy_i), // WRITE - .dst_rdy_o(dst_rdy_o), // not FULL - .dataout(dataout), - .src_rdy_o(src_rdy_o), // not EMPTY - .dst_rdy_i(dst_rdy_i) - ); - -endmodule // ext_fifo_tb diff --git a/fpga/usrp2/extramfifo/icon.v b/fpga/usrp2/extramfifo/icon.v deleted file mode 100644 index 6537e9340..000000000 --- a/fpga/usrp2/extramfifo/icon.v +++ /dev/null @@ -1,1286 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -//////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor: Xilinx -// \ \ \/ Version: M.53d -// \ \ Application: netgen -// / / Filename: icon.v -// /___/ /\ Timestamp: Tue Jul 20 20:31:15 2010 -// \ \ / \ -// \___\/\___\ -// -// Command : -w -sim -ofmt verilog /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.ngc /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.v -// Device : xc3s2000-fg456-5 -// Input file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.ngc -// Output file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.v -// # of Modules : 1 -// Design Name : icon -// Xilinx : /opt/Xilinx/12.1/ISE_DS/ISE -// -// Purpose: -// This verilog netlist is a verification model and uses simulation -// primitives which may not represent the true implementation of the -// device, however the netlist is functionally correct and should not -// be modified. This file cannot be synthesized and should only be used -// with supported simulation tools. -// -// Reference: -// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 -// -//////////////////////////////////////////////////////////////////////////////// - -`timescale 1 ns/1 ps - -module icon ( -CONTROL0 -)/* synthesis syn_black_box syn_noprune=1 */; - inout [35 : 0] CONTROL0; - - // synthesis translate_off - - wire N1; - wire \U0/U_ICON/I_YES_BSCAN.U_BS/DRCK1 ; - wire \U0/U_ICON/U_CMD/iSEL_n ; - wire \U0/U_ICON/U_CMD/iTARGET_CE ; - wire \U0/U_ICON/U_CTRL_OUT/iDATA_VALID ; - wire \U0/U_ICON/U_STAT/iCMD_GRP0_SEL ; - wire \U0/U_ICON/U_STAT/iDATA_VALID ; - wire \U0/U_ICON/U_STAT/iSTATCMD_CE ; - wire \U0/U_ICON/U_STAT/iSTATCMD_CE_n ; - wire \U0/U_ICON/U_STAT/iSTAT_HIGH ; - wire \U0/U_ICON/U_STAT/iSTAT_LOW ; - wire \U0/U_ICON/U_STAT/iTDO_next ; - wire \U0/U_ICON/U_SYNC/iDATA_CMD_n ; - wire \U0/U_ICON/U_SYNC/iGOT_SYNC ; - wire \U0/U_ICON/U_SYNC/iGOT_SYNC_HIGH ; - wire \U0/U_ICON/U_SYNC/iGOT_SYNC_LOW ; - wire \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3_91 ; - wire \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4_92 ; - wire \U0/U_ICON/iCORE_ID_SEL[0] ; - wire \U0/U_ICON/iCORE_ID_SEL[15] ; - wire \U0/U_ICON/iDATA_CMD ; - wire \U0/U_ICON/iDATA_CMD_n ; - wire \U0/U_ICON/iSEL ; - wire \U0/U_ICON/iSEL_n ; - wire \U0/U_ICON/iSYNC ; - wire \U0/U_ICON/iTDI ; - wire \U0/U_ICON/iTDO ; - wire \U0/U_ICON/iTDO_next ; - wire \U0/iSHIFT_OUT ; - wire \U0/iUPDATE_OUT ; - wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_DRCK2_UNCONNECTED ; - wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_RESET_UNCONNECTED ; - wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_CAPTURE_UNCONNECTED ; - wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_SEL2_UNCONNECTED ; - wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT_O_UNCONNECTED ; - wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT_O_UNCONNECTED ; - wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT_O_UNCONNECTED ; - wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT_O_UNCONNECTED ; - wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT_O_UNCONNECTED ; - wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT_O_UNCONNECTED ; - wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT_O_UNCONNECTED ; - wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT_O_UNCONNECTED ; - wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT_O_UNCONNECTED ; - wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT_O_UNCONNECTED ; - wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT_O_UNCONNECTED ; - wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT_O_UNCONNECTED ; - wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT_O_UNCONNECTED ; - wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT_O_UNCONNECTED ; - wire [11 : 8] \U0/U_ICON/U_CMD/iTARGET ; - wire [1 : 0] \U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL ; - wire [5 : 1] \U0/U_ICON/U_STAT/U_STAT_CNT/CI ; - wire [5 : 0] \U0/U_ICON/U_STAT/U_STAT_CNT/D ; - wire [5 : 0] \U0/U_ICON/U_STAT/U_STAT_CNT/S ; - wire [3 : 0] \U0/U_ICON/U_STAT/iSTAT ; - wire [5 : 0] \U0/U_ICON/U_STAT/iSTAT_CNT ; - wire [6 : 0] \U0/U_ICON/U_SYNC/iSYNC_WORD ; - wire [1 : 0] \U0/U_ICON/iCOMMAND_GRP ; - wire [15 : 0] \U0/U_ICON/iCOMMAND_SEL ; - wire [3 : 0] \U0/U_ICON/iCORE_ID ; - wire [15 : 15] \U0/U_ICON/iTDO_VEC ; - GND XST_GND ( - .G(CONTROL0[2]) - ); - VCC XST_VCC ( - .P(N1) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_TDI_reg ( - .C(CONTROL0[0]), - .CE(N1), - .D(\U0/U_ICON/iTDI ), - .Q(CONTROL0[1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_TDO_reg ( - .C(CONTROL0[0]), - .CE(N1), - .D(\U0/U_ICON/iTDO_next ), - .Q(\U0/U_ICON/iTDO ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_iDATA_CMD ( - .C(\U0/iUPDATE_OUT ), - .CLR(\U0/U_ICON/iSEL_n ), - .D(\U0/U_ICON/iDATA_CMD_n ), - .Q(\U0/U_ICON/iDATA_CMD ) - ); - MUXF5 \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_2_f5 ( - .I0(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4_92 ), - .I1(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3_91 ), - .S(\U0/U_ICON/iCORE_ID [3]), - .O(\U0/U_ICON/iTDO_next ) - ); - LUT4 #( - .INIT ( 16'h0002 )) - \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4 ( - .I0(CONTROL0[3]), - .I1(\U0/U_ICON/iCORE_ID [0]), - .I2(\U0/U_ICON/iCORE_ID [1]), - .I3(\U0/U_ICON/iCORE_ID [2]), - .O(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4_92 ) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3 ( - .I0(\U0/U_ICON/iTDO_VEC [15]), - .I1(\U0/U_ICON/iCORE_ID [0]), - .I2(\U0/U_ICON/iCORE_ID [1]), - .I3(\U0/U_ICON/iCORE_ID [2]), - .O(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3_91 ) - ); - INV \U0/U_ICON/U_iSEL_n ( - .I(\U0/U_ICON/iSEL ), - .O(\U0/U_ICON/iSEL_n ) - ); - INV \U0/U_ICON/U_iDATA_CMD_n ( - .I(\U0/U_ICON/iDATA_CMD ), - .O(\U0/U_ICON/iDATA_CMD_n ) - ); - BSCAN_SPARTAN3 \U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS ( - .TDI(\U0/U_ICON/iTDI ), - .SHIFT(\U0/iSHIFT_OUT ), - .DRCK1(\U0/U_ICON/I_YES_BSCAN.U_BS/DRCK1 ), - .DRCK2(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_DRCK2_UNCONNECTED ), - .RESET(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_RESET_UNCONNECTED ), - .UPDATE(\U0/iUPDATE_OUT ), - .TDO1(\U0/U_ICON/iTDO ), - .TDO2(CONTROL0[2]), - .CAPTURE(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_CAPTURE_UNCONNECTED ), - .SEL1(\U0/U_ICON/iSEL ), - .SEL2(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_SEL2_UNCONNECTED ) - ); - icon_bscan_bufg \U0/U_ICON/I_YES_BSCAN.U_BS/I_USE_SOFTBSCAN_EQ0.I_USE_XST_TCK_WORKAROUND_EQ1.U_ICON_BSCAN_BUFG ( - .DRCK_LOCAL_I(\U0/U_ICON/I_YES_BSCAN.U_BS/DRCK1 ), - .DRCK_LOCAL_O(CONTROL0[0]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/U_ICON/U_SYNC/U_GOT_SYNC ( - .I0(\U0/U_ICON/U_SYNC/iGOT_SYNC_LOW ), - .I1(\U0/U_ICON/U_SYNC/iGOT_SYNC_HIGH ), - .O(\U0/U_ICON/U_SYNC/iGOT_SYNC ) - ); - LUT4 #( - .INIT ( 16'h0200 )) - \U0/U_ICON/U_SYNC/U_GOT_SYNC_L ( - .I0(\U0/U_ICON/U_SYNC/iSYNC_WORD [0]), - .I1(\U0/U_ICON/U_SYNC/iSYNC_WORD [1]), - .I2(\U0/U_ICON/U_SYNC/iSYNC_WORD [2]), - .I3(\U0/U_ICON/U_SYNC/iSYNC_WORD [3]), - .O(\U0/U_ICON/U_SYNC/iGOT_SYNC_LOW ) - ); - LUT4 #( - .INIT ( 16'h0400 )) - \U0/U_ICON/U_SYNC/U_GOT_SYNC_H ( - .I0(\U0/U_ICON/U_SYNC/iSYNC_WORD [4]), - .I1(\U0/U_ICON/U_SYNC/iSYNC_WORD [5]), - .I2(\U0/U_ICON/U_SYNC/iSYNC_WORD [6]), - .I3(CONTROL0[1]), - .O(\U0/U_ICON/U_SYNC/iGOT_SYNC_HIGH ) - ); - INV \U0/U_ICON/U_SYNC/U_iDATA_CMD_n ( - .I(\U0/U_ICON/iDATA_CMD ), - .O(\U0/U_ICON/U_SYNC/iDATA_CMD_n ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_SYNC/U_SYNC ( - .C(CONTROL0[0]), - .CE(\U0/U_ICON/U_SYNC/iGOT_SYNC ), - .D(N1), - .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), - .Q(\U0/U_ICON/iSYNC ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_SYNC/G_SYNC_WORD[0].I_NE0.U_FDR ( - .C(CONTROL0[0]), - .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [1]), - .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), - .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_SYNC/G_SYNC_WORD[1].I_NE0.U_FDR ( - .C(CONTROL0[0]), - .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [2]), - .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), - .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_SYNC/G_SYNC_WORD[2].I_NE0.U_FDR ( - .C(CONTROL0[0]), - .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [3]), - .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), - .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_SYNC/G_SYNC_WORD[3].I_NE0.U_FDR ( - .C(CONTROL0[0]), - .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [4]), - .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), - .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_SYNC/G_SYNC_WORD[4].I_NE0.U_FDR ( - .C(CONTROL0[0]), - .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [5]), - .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), - .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_SYNC/G_SYNC_WORD[5].I_NE0.U_FDR ( - .C(CONTROL0[0]), - .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [6]), - .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), - .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_SYNC/G_SYNC_WORD[6].I_EQ0.U_FDR ( - .C(CONTROL0[0]), - .D(CONTROL0[1]), - .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), - .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [6]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[0].U_HCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [0]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), - .O(CONTROL0[20]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[0].U_LCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [0]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), - .O(CONTROL0[4]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_HCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [1]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), - .O(CONTROL0[21]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_LCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [1]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), - .O(CONTROL0[5]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[2].U_HCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [2]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), - .O(CONTROL0[22]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[2].U_LCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [2]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), - .O(CONTROL0[6]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[3].U_HCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [3]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), - .O(CONTROL0[23]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[3].U_LCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [3]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), - .O(CONTROL0[7]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[4].U_HCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [4]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), - .O(CONTROL0[24]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[4].U_LCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [4]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), - .O(CONTROL0[8]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[5].U_HCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [5]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), - .O(CONTROL0[25]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[5].U_LCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [5]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), - .O(CONTROL0[9]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[6].U_HCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [6]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), - .O(CONTROL0[26]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[6].U_LCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [6]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), - .O(CONTROL0[10]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[7].U_HCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [7]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), - .O(CONTROL0[27]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[7].U_LCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [7]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), - .O(CONTROL0[11]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[8].U_HCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [8]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), - .O(CONTROL0[28]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[8].U_LCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [8]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), - .O(CONTROL0[12]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_HCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [9]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), - .O(CONTROL0[29]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [9]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), - .O(CONTROL0[13]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[10].U_HCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [10]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), - .O(CONTROL0[30]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[10].U_LCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [10]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), - .O(CONTROL0[14]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[11].U_HCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [11]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), - .O(CONTROL0[31]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[11].U_LCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [11]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), - .O(CONTROL0[15]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[12].U_HCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [12]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), - .O(CONTROL0[32]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[12].U_LCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [12]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), - .O(CONTROL0[16]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[13].U_HCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [13]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), - .O(CONTROL0[33]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[13].U_LCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [13]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), - .O(CONTROL0[17]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[14].U_HCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [14]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), - .O(CONTROL0[34]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[14].U_LCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [14]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), - .O(CONTROL0[18]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_HCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [15]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), - .O(CONTROL0[35]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_LCE ( - .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [15]), - .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), - .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), - .O(CONTROL0[19]) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/U_ICON/U_CTRL_OUT/U_CMDGRP1 ( - .I0(\U0/U_ICON/iCOMMAND_GRP [0]), - .I1(\U0/U_ICON/iCOMMAND_GRP [1]), - .O(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]) - ); - LUT2 #( - .INIT ( 4'h1 )) - \U0/U_ICON/U_CTRL_OUT/U_CMDGRP0 ( - .I0(\U0/U_ICON/iCOMMAND_GRP [0]), - .I1(\U0/U_ICON/iCOMMAND_GRP [1]), - .O(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/U_ICON/U_CTRL_OUT/U_DATA_VALID ( - .I0(\U0/U_ICON/iSYNC ), - .I1(\U0/iSHIFT_OUT ), - .O(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ) - ); - LUT4 #( - .INIT ( 16'h0001 )) - \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT ( - .I0(\U0/U_ICON/iCORE_ID [0]), - .I1(\U0/U_ICON/iCORE_ID [1]), - .I2(\U0/U_ICON/iCORE_ID [2]), - .I3(\U0/U_ICON/iCORE_ID [3]), - .O(\U0/U_ICON/iCORE_ID_SEL[0] ) - ); - LUT4 #( - .INIT ( 16'h0002 )) - \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT ( - .I0(\U0/U_ICON/iCORE_ID [0]), - .I1(\U0/U_ICON/iCORE_ID [1]), - .I2(\U0/U_ICON/iCORE_ID [2]), - .I3(\U0/U_ICON/iCORE_ID [3]), - .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT_O_UNCONNECTED ) - ); - LUT4 #( - .INIT ( 16'h0004 )) - \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT ( - .I0(\U0/U_ICON/iCORE_ID [0]), - .I1(\U0/U_ICON/iCORE_ID [1]), - .I2(\U0/U_ICON/iCORE_ID [2]), - .I3(\U0/U_ICON/iCORE_ID [3]), - .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT_O_UNCONNECTED ) - ); - LUT4 #( - .INIT ( 16'h0008 )) - \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT ( - .I0(\U0/U_ICON/iCORE_ID [0]), - .I1(\U0/U_ICON/iCORE_ID [1]), - .I2(\U0/U_ICON/iCORE_ID [2]), - .I3(\U0/U_ICON/iCORE_ID [3]), - .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT_O_UNCONNECTED ) - ); - LUT4 #( - .INIT ( 16'h0010 )) - \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT ( - .I0(\U0/U_ICON/iCORE_ID [0]), - .I1(\U0/U_ICON/iCORE_ID [1]), - .I2(\U0/U_ICON/iCORE_ID [2]), - .I3(\U0/U_ICON/iCORE_ID [3]), - .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT_O_UNCONNECTED ) - ); - LUT4 #( - .INIT ( 16'h0020 )) - \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT ( - .I0(\U0/U_ICON/iCORE_ID [0]), - .I1(\U0/U_ICON/iCORE_ID [1]), - .I2(\U0/U_ICON/iCORE_ID [2]), - .I3(\U0/U_ICON/iCORE_ID [3]), - .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT_O_UNCONNECTED ) - ); - LUT4 #( - .INIT ( 16'h0040 )) - \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT ( - .I0(\U0/U_ICON/iCORE_ID [0]), - .I1(\U0/U_ICON/iCORE_ID [1]), - .I2(\U0/U_ICON/iCORE_ID [2]), - .I3(\U0/U_ICON/iCORE_ID [3]), - .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT_O_UNCONNECTED ) - ); - LUT4 #( - .INIT ( 16'h0080 )) - \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT ( - .I0(\U0/U_ICON/iCORE_ID [0]), - .I1(\U0/U_ICON/iCORE_ID [1]), - .I2(\U0/U_ICON/iCORE_ID [2]), - .I3(\U0/U_ICON/iCORE_ID [3]), - .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT_O_UNCONNECTED ) - ); - LUT4 #( - .INIT ( 16'h0100 )) - \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT ( - .I0(\U0/U_ICON/iCORE_ID [0]), - .I1(\U0/U_ICON/iCORE_ID [1]), - .I2(\U0/U_ICON/iCORE_ID [2]), - .I3(\U0/U_ICON/iCORE_ID [3]), - .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT_O_UNCONNECTED ) - ); - LUT4 #( - .INIT ( 16'h0200 )) - \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT ( - .I0(\U0/U_ICON/iCORE_ID [0]), - .I1(\U0/U_ICON/iCORE_ID [1]), - .I2(\U0/U_ICON/iCORE_ID [2]), - .I3(\U0/U_ICON/iCORE_ID [3]), - .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT_O_UNCONNECTED ) - ); - LUT4 #( - .INIT ( 16'h0400 )) - \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT ( - .I0(\U0/U_ICON/iCORE_ID [0]), - .I1(\U0/U_ICON/iCORE_ID [1]), - .I2(\U0/U_ICON/iCORE_ID [2]), - .I3(\U0/U_ICON/iCORE_ID [3]), - .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT_O_UNCONNECTED ) - ); - LUT4 #( - .INIT ( 16'h0800 )) - \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT ( - .I0(\U0/U_ICON/iCORE_ID [0]), - .I1(\U0/U_ICON/iCORE_ID [1]), - .I2(\U0/U_ICON/iCORE_ID [2]), - .I3(\U0/U_ICON/iCORE_ID [3]), - .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT_O_UNCONNECTED ) - ); - LUT4 #( - .INIT ( 16'h1000 )) - \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT ( - .I0(\U0/U_ICON/iCORE_ID [0]), - .I1(\U0/U_ICON/iCORE_ID [1]), - .I2(\U0/U_ICON/iCORE_ID [2]), - .I3(\U0/U_ICON/iCORE_ID [3]), - .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT_O_UNCONNECTED ) - ); - LUT4 #( - .INIT ( 16'h2000 )) - \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT ( - .I0(\U0/U_ICON/iCORE_ID [0]), - .I1(\U0/U_ICON/iCORE_ID [1]), - .I2(\U0/U_ICON/iCORE_ID [2]), - .I3(\U0/U_ICON/iCORE_ID [3]), - .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT_O_UNCONNECTED ) - ); - LUT4 #( - .INIT ( 16'h4000 )) - \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT ( - .I0(\U0/U_ICON/iCORE_ID [0]), - .I1(\U0/U_ICON/iCORE_ID [1]), - .I2(\U0/U_ICON/iCORE_ID [2]), - .I3(\U0/U_ICON/iCORE_ID [3]), - .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT_O_UNCONNECTED ) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[15].U_LUT ( - .I0(\U0/U_ICON/iCORE_ID [0]), - .I1(\U0/U_ICON/iCORE_ID [1]), - .I2(\U0/U_ICON/iCORE_ID [2]), - .I3(\U0/U_ICON/iCORE_ID [3]), - .O(\U0/U_ICON/iCORE_ID_SEL[15] ) - ); - LUT4 #( - .INIT ( 16'h0001 )) - \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[0].U_LUT ( - .I0(\U0/U_ICON/U_CMD/iTARGET [8]), - .I1(\U0/U_ICON/U_CMD/iTARGET [9]), - .I2(\U0/U_ICON/U_CMD/iTARGET [10]), - .I3(\U0/U_ICON/U_CMD/iTARGET [11]), - .O(\U0/U_ICON/iCOMMAND_SEL [0]) - ); - LUT4 #( - .INIT ( 16'h0002 )) - \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[1].U_LUT ( - .I0(\U0/U_ICON/U_CMD/iTARGET [8]), - .I1(\U0/U_ICON/U_CMD/iTARGET [9]), - .I2(\U0/U_ICON/U_CMD/iTARGET [10]), - .I3(\U0/U_ICON/U_CMD/iTARGET [11]), - .O(\U0/U_ICON/iCOMMAND_SEL [1]) - ); - LUT4 #( - .INIT ( 16'h0004 )) - \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[2].U_LUT ( - .I0(\U0/U_ICON/U_CMD/iTARGET [8]), - .I1(\U0/U_ICON/U_CMD/iTARGET [9]), - .I2(\U0/U_ICON/U_CMD/iTARGET [10]), - .I3(\U0/U_ICON/U_CMD/iTARGET [11]), - .O(\U0/U_ICON/iCOMMAND_SEL [2]) - ); - LUT4 #( - .INIT ( 16'h0008 )) - \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[3].U_LUT ( - .I0(\U0/U_ICON/U_CMD/iTARGET [8]), - .I1(\U0/U_ICON/U_CMD/iTARGET [9]), - .I2(\U0/U_ICON/U_CMD/iTARGET [10]), - .I3(\U0/U_ICON/U_CMD/iTARGET [11]), - .O(\U0/U_ICON/iCOMMAND_SEL [3]) - ); - LUT4 #( - .INIT ( 16'h0010 )) - \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[4].U_LUT ( - .I0(\U0/U_ICON/U_CMD/iTARGET [8]), - .I1(\U0/U_ICON/U_CMD/iTARGET [9]), - .I2(\U0/U_ICON/U_CMD/iTARGET [10]), - .I3(\U0/U_ICON/U_CMD/iTARGET [11]), - .O(\U0/U_ICON/iCOMMAND_SEL [4]) - ); - LUT4 #( - .INIT ( 16'h0020 )) - \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[5].U_LUT ( - .I0(\U0/U_ICON/U_CMD/iTARGET [8]), - .I1(\U0/U_ICON/U_CMD/iTARGET [9]), - .I2(\U0/U_ICON/U_CMD/iTARGET [10]), - .I3(\U0/U_ICON/U_CMD/iTARGET [11]), - .O(\U0/U_ICON/iCOMMAND_SEL [5]) - ); - LUT4 #( - .INIT ( 16'h0040 )) - \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[6].U_LUT ( - .I0(\U0/U_ICON/U_CMD/iTARGET [8]), - .I1(\U0/U_ICON/U_CMD/iTARGET [9]), - .I2(\U0/U_ICON/U_CMD/iTARGET [10]), - .I3(\U0/U_ICON/U_CMD/iTARGET [11]), - .O(\U0/U_ICON/iCOMMAND_SEL [6]) - ); - LUT4 #( - .INIT ( 16'h0080 )) - \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[7].U_LUT ( - .I0(\U0/U_ICON/U_CMD/iTARGET [8]), - .I1(\U0/U_ICON/U_CMD/iTARGET [9]), - .I2(\U0/U_ICON/U_CMD/iTARGET [10]), - .I3(\U0/U_ICON/U_CMD/iTARGET [11]), - .O(\U0/U_ICON/iCOMMAND_SEL [7]) - ); - LUT4 #( - .INIT ( 16'h0100 )) - \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[8].U_LUT ( - .I0(\U0/U_ICON/U_CMD/iTARGET [8]), - .I1(\U0/U_ICON/U_CMD/iTARGET [9]), - .I2(\U0/U_ICON/U_CMD/iTARGET [10]), - .I3(\U0/U_ICON/U_CMD/iTARGET [11]), - .O(\U0/U_ICON/iCOMMAND_SEL [8]) - ); - LUT4 #( - .INIT ( 16'h0200 )) - \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[9].U_LUT ( - .I0(\U0/U_ICON/U_CMD/iTARGET [8]), - .I1(\U0/U_ICON/U_CMD/iTARGET [9]), - .I2(\U0/U_ICON/U_CMD/iTARGET [10]), - .I3(\U0/U_ICON/U_CMD/iTARGET [11]), - .O(\U0/U_ICON/iCOMMAND_SEL [9]) - ); - LUT4 #( - .INIT ( 16'h0400 )) - \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[10].U_LUT ( - .I0(\U0/U_ICON/U_CMD/iTARGET [8]), - .I1(\U0/U_ICON/U_CMD/iTARGET [9]), - .I2(\U0/U_ICON/U_CMD/iTARGET [10]), - .I3(\U0/U_ICON/U_CMD/iTARGET [11]), - .O(\U0/U_ICON/iCOMMAND_SEL [10]) - ); - LUT4 #( - .INIT ( 16'h0800 )) - \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[11].U_LUT ( - .I0(\U0/U_ICON/U_CMD/iTARGET [8]), - .I1(\U0/U_ICON/U_CMD/iTARGET [9]), - .I2(\U0/U_ICON/U_CMD/iTARGET [10]), - .I3(\U0/U_ICON/U_CMD/iTARGET [11]), - .O(\U0/U_ICON/iCOMMAND_SEL [11]) - ); - LUT4 #( - .INIT ( 16'h1000 )) - \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[12].U_LUT ( - .I0(\U0/U_ICON/U_CMD/iTARGET [8]), - .I1(\U0/U_ICON/U_CMD/iTARGET [9]), - .I2(\U0/U_ICON/U_CMD/iTARGET [10]), - .I3(\U0/U_ICON/U_CMD/iTARGET [11]), - .O(\U0/U_ICON/iCOMMAND_SEL [12]) - ); - LUT4 #( - .INIT ( 16'h2000 )) - \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[13].U_LUT ( - .I0(\U0/U_ICON/U_CMD/iTARGET [8]), - .I1(\U0/U_ICON/U_CMD/iTARGET [9]), - .I2(\U0/U_ICON/U_CMD/iTARGET [10]), - .I3(\U0/U_ICON/U_CMD/iTARGET [11]), - .O(\U0/U_ICON/iCOMMAND_SEL [13]) - ); - LUT4 #( - .INIT ( 16'h4000 )) - \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[14].U_LUT ( - .I0(\U0/U_ICON/U_CMD/iTARGET [8]), - .I1(\U0/U_ICON/U_CMD/iTARGET [9]), - .I2(\U0/U_ICON/U_CMD/iTARGET [10]), - .I3(\U0/U_ICON/U_CMD/iTARGET [11]), - .O(\U0/U_ICON/iCOMMAND_SEL [14]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[15].U_LUT ( - .I0(\U0/U_ICON/U_CMD/iTARGET [8]), - .I1(\U0/U_ICON/U_CMD/iTARGET [9]), - .I2(\U0/U_ICON/U_CMD/iTARGET [10]), - .I3(\U0/U_ICON/U_CMD/iTARGET [11]), - .O(\U0/U_ICON/iCOMMAND_SEL [15]) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/U_ICON/U_CMD/U_TARGET_CE ( - .I0(\U0/U_ICON/iDATA_CMD ), - .I1(\U0/iSHIFT_OUT ), - .O(\U0/U_ICON/U_CMD/iTARGET_CE ) - ); - INV \U0/U_ICON/U_CMD/U_SEL_n ( - .I(\U0/U_ICON/iSEL ), - .O(\U0/U_ICON/U_CMD/iSEL_n ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_CMD/G_TARGET[6].I_NE0.U_TARGET ( - .C(CONTROL0[0]), - .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), - .CLR(\U0/U_ICON/U_CMD/iSEL_n ), - .D(\U0/U_ICON/iCOMMAND_GRP [1]), - .Q(\U0/U_ICON/iCOMMAND_GRP [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_CMD/G_TARGET[7].I_NE0.U_TARGET ( - .C(CONTROL0[0]), - .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), - .CLR(\U0/U_ICON/U_CMD/iSEL_n ), - .D(\U0/U_ICON/U_CMD/iTARGET [8]), - .Q(\U0/U_ICON/iCOMMAND_GRP [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_CMD/G_TARGET[8].I_NE0.U_TARGET ( - .C(CONTROL0[0]), - .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), - .CLR(\U0/U_ICON/U_CMD/iSEL_n ), - .D(\U0/U_ICON/U_CMD/iTARGET [9]), - .Q(\U0/U_ICON/U_CMD/iTARGET [8]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET ( - .C(CONTROL0[0]), - .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), - .CLR(\U0/U_ICON/U_CMD/iSEL_n ), - .D(\U0/U_ICON/U_CMD/iTARGET [10]), - .Q(\U0/U_ICON/U_CMD/iTARGET [9]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET ( - .C(CONTROL0[0]), - .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), - .CLR(\U0/U_ICON/U_CMD/iSEL_n ), - .D(\U0/U_ICON/U_CMD/iTARGET [11]), - .Q(\U0/U_ICON/U_CMD/iTARGET [10]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET ( - .C(CONTROL0[0]), - .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), - .CLR(\U0/U_ICON/U_CMD/iSEL_n ), - .D(\U0/U_ICON/iCORE_ID [0]), - .Q(\U0/U_ICON/U_CMD/iTARGET [11]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET ( - .C(CONTROL0[0]), - .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), - .CLR(\U0/U_ICON/U_CMD/iSEL_n ), - .D(\U0/U_ICON/iCORE_ID [1]), - .Q(\U0/U_ICON/iCORE_ID [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_CMD/G_TARGET[13].I_NE0.U_TARGET ( - .C(CONTROL0[0]), - .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), - .CLR(\U0/U_ICON/U_CMD/iSEL_n ), - .D(\U0/U_ICON/iCORE_ID [2]), - .Q(\U0/U_ICON/iCORE_ID [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET ( - .C(CONTROL0[0]), - .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), - .CLR(\U0/U_ICON/U_CMD/iSEL_n ), - .D(\U0/U_ICON/iCORE_ID [3]), - .Q(\U0/U_ICON/iCORE_ID [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET ( - .C(CONTROL0[0]), - .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), - .CLR(\U0/U_ICON/U_CMD/iSEL_n ), - .D(CONTROL0[1]), - .Q(\U0/U_ICON/iCORE_ID [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_STAT/U_STAT_CNT/G[5].U_FDRE ( - .C(CONTROL0[0]), - .CE(N1), - .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [5]), - .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), - .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [5]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].U_FDRE ( - .C(CONTROL0[0]), - .CE(N1), - .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [4]), - .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), - .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [4]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].U_FDRE ( - .C(CONTROL0[0]), - .CE(N1), - .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [3]), - .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), - .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].U_FDRE ( - .C(CONTROL0[0]), - .CE(N1), - .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [2]), - .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), - .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].U_FDRE ( - .C(CONTROL0[0]), - .CE(N1), - .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [1]), - .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), - .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [1]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_FDRE ( - .C(CONTROL0[0]), - .CE(N1), - .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [0]), - .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), - .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [0]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/U_ICON/U_STAT/U_STAT_CNT/G[5].U_LUT ( - .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [5]), - .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [5]) - ); - XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[5].U_XORCY ( - .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [5]), - .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [5]), - .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [5]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].U_LUT ( - .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [4]), - .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [4]) - ); - MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].GnH.U_MUXCY ( - .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [4]), - .DI(CONTROL0[2]), - .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [4]), - .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [5]) - ); - XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].U_XORCY ( - .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [4]), - .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [4]), - .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [4]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].U_LUT ( - .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), - .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [3]) - ); - MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].GnH.U_MUXCY ( - .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [3]), - .DI(CONTROL0[2]), - .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [3]), - .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [4]) - ); - XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].U_XORCY ( - .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [3]), - .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [3]), - .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [3]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].U_LUT ( - .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), - .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [2]) - ); - MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].GnH.U_MUXCY ( - .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [2]), - .DI(CONTROL0[2]), - .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [2]), - .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [3]) - ); - XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].U_XORCY ( - .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [2]), - .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [2]), - .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [2]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].U_LUT ( - .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), - .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [1]) - ); - MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].GnH.U_MUXCY ( - .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [1]), - .DI(CONTROL0[2]), - .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [1]), - .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [2]) - ); - XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].U_XORCY ( - .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [1]), - .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [1]), - .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [1]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_LUT ( - .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), - .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [0]) - ); - MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].GnH.U_MUXCY ( - .CI(N1), - .DI(CONTROL0[2]), - .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [0]), - .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [1]) - ); - XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_XORCY ( - .CI(N1), - .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [0]), - .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [0]) - ); - MUXF6 \U0/U_ICON/U_STAT/U_TDO_next ( - .I0(\U0/U_ICON/U_STAT/iSTAT_LOW ), - .I1(\U0/U_ICON/U_STAT/iSTAT_HIGH ), - .S(\U0/U_ICON/U_STAT/iSTAT_CNT [5]), - .O(\U0/U_ICON/U_STAT/iTDO_next ) - ); - MUXF5 \U0/U_ICON/U_STAT/U_STAT_LOW ( - .I0(\U0/U_ICON/U_STAT/iSTAT [0]), - .I1(\U0/U_ICON/U_STAT/iSTAT [1]), - .S(\U0/U_ICON/U_STAT/iSTAT_CNT [4]), - .O(\U0/U_ICON/U_STAT/iSTAT_LOW ) - ); - MUXF5 \U0/U_ICON/U_STAT/U_STAT_HIGH ( - .I0(\U0/U_ICON/U_STAT/iSTAT [2]), - .I1(\U0/U_ICON/U_STAT/iSTAT [3]), - .S(\U0/U_ICON/U_STAT/iSTAT_CNT [4]), - .O(\U0/U_ICON/U_STAT/iSTAT_HIGH ) - ); - LUT4 #( - .INIT ( 16'h0101 )) - \U0/U_ICON/U_STAT/F_STAT[0].U_STAT ( - .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), - .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), - .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), - .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), - .O(\U0/U_ICON/U_STAT/iSTAT [0]) - ); - LUT4 #( - .INIT ( 16'hC101 )) - \U0/U_ICON/U_STAT/F_STAT[1].U_STAT ( - .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), - .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), - .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), - .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), - .O(\U0/U_ICON/U_STAT/iSTAT [1]) - ); - LUT4 #( - .INIT ( 16'h2100 )) - \U0/U_ICON/U_STAT/F_STAT[2].U_STAT ( - .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), - .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), - .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), - .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), - .O(\U0/U_ICON/U_STAT/iSTAT [2]) - ); - LUT4 #( - .INIT ( 16'h1610 )) - \U0/U_ICON/U_STAT/F_STAT[3].U_STAT ( - .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), - .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), - .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), - .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), - .O(\U0/U_ICON/U_STAT/iSTAT [3]) - ); - INV \U0/U_ICON/U_STAT/U_STATCMD_n ( - .I(\U0/U_ICON/U_STAT/iSTATCMD_CE ), - .O(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_ICON/U_STAT/U_STATCMD ( - .I0(\U0/U_ICON/U_STAT/iDATA_VALID ), - .I1(\U0/U_ICON/iCOMMAND_SEL [0]), - .I2(\U0/U_ICON/iCORE_ID_SEL[15] ), - .I3(\U0/U_ICON/U_STAT/iCMD_GRP0_SEL ), - .O(\U0/U_ICON/U_STAT/iSTATCMD_CE ) - ); - LUT2 #( - .INIT ( 4'h1 )) - \U0/U_ICON/U_STAT/U_CMDGRP0 ( - .I0(\U0/U_ICON/iCOMMAND_GRP [0]), - .I1(\U0/U_ICON/iCOMMAND_GRP [1]), - .O(\U0/U_ICON/U_STAT/iCMD_GRP0_SEL ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/U_ICON/U_STAT/U_DATA_VALID ( - .I0(\U0/U_ICON/iSYNC ), - .I1(\U0/iSHIFT_OUT ), - .O(\U0/U_ICON/U_STAT/iDATA_VALID ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/U_ICON/U_STAT/U_TDO ( - .C(CONTROL0[0]), - .CE(N1), - .D(\U0/U_ICON/U_STAT/iTDO_next ), - .Q(\U0/U_ICON/iTDO_VEC [15]) - ); - -// synthesis translate_on - -endmodule - -// synthesis translate_off - -`ifndef GLBL -`define GLBL - -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (weak1, weak0) GSR = GSR_int; - assign (weak1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule - -`endif - -// synthesis translate_on diff --git a/fpga/usrp2/extramfifo/icon.xco b/fpga/usrp2/extramfifo/icon.xco deleted file mode 100644 index fda273149..000000000 --- a/fpga/usrp2/extramfifo/icon.xco +++ /dev/null @@ -1,47 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 12.1 -# Date: Wed Jul 21 03:31:19 2010 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc3s2000 -SET devicefamily = spartan3 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = fg456 -SET removerpms = false -SET simulationfiles = Structural -SET speedgrade = -5 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a -# END Select -# BEGIN Parameters -CSET component_name=icon -CSET enable_jtag_bufg=true -CSET number_control_ports=1 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -GENERATE -# CRC: 799ba5a1 diff --git a/fpga/usrp2/extramfifo/ila.v b/fpga/usrp2/extramfifo/ila.v deleted file mode 100644 index b0d8f8d0c..000000000 --- a/fpga/usrp2/extramfifo/ila.v +++ /dev/null @@ -1,5544 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -//////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor: Xilinx -// \ \ \/ Version: M.53d -// \ \ Application: netgen -// / / Filename: ila.v -// /___/ /\ Timestamp: Wed Jul 21 11:51:09 2010 -// \ \ / \ -// \___\/\___\ -// -// Command : -w -sim -ofmt verilog /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.ngc /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.v -// Device : xc3s2000-fg456-5 -// Input file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.ngc -// Output file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.v -// # of Modules : 1 -// Design Name : ila -// Xilinx : /opt/Xilinx/12.1/ISE_DS/ISE -// -// Purpose: -// This verilog netlist is a verification model and uses simulation -// primitives which may not represent the true implementation of the -// device, however the netlist is functionally correct and should not -// be modified. This file cannot be synthesized and should only be used -// with supported simulation tools. -// -// Reference: -// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 -// -//////////////////////////////////////////////////////////////////////////////// - -`timescale 1 ns/1 ps - -module ila ( - CLK, CONTROL, TRIG0, TRIG1, TRIG2, TRIG3 -)/* synthesis syn_black_box syn_noprune=1 */; - input CLK; - inout [35 : 0] CONTROL; - input [7 : 0] TRIG0; - input [7 : 0] TRIG1; - input [7 : 0] TRIG2; - input [3 : 0] TRIG3; - - // synthesis translate_off - - wire N0; - wire N1; - wire N38; - wire N39; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DIN ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iOUT ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DIN ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DIN ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iOUT ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DIN ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iOUT ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DIN ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DIN ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/iCFG_DIN ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DIN ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DIN ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_CE ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[0] ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[1] ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[8] ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[0] ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[1] ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[8] ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[0] ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[1] ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[8] ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_CE ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_CE ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iCAP_WR_EN ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_IN ; - wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_OUT ; - wire \U0/I_NO_D.U_ILA/U_RST/HALT_pulse ; - wire \U0/I_NO_D.U_ILA/U_RST/POR ; - wire \U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ; - wire \U0/I_NO_D.U_ILA/U_RST/PRE_RESET1 ; - wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched ; - wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ; - wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ; - wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[0] ; - wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[1] ; - wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[2] ; - wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[4] ; - wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched ; - wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ; - wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ; - wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[0] ; - wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[2] ; - wire \U0/I_NO_D.U_ILA/U_STAT/ACTRESET_pulse ; - wire \U0/I_NO_D.U_ILA/U_STAT/ACT_dstat ; - wire \U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ; - wire \U0/I_NO_D.U_ILA/U_STAT/CAP_RESET_dly1 ; - wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0 ; - wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1 ; - wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL ; - wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ; - wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ; - wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ; - wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ; - wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ; - wire \U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ; - wire \U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ; - wire \U0/I_NO_D.U_ILA/U_STAT/NS_load ; - wire \U0/I_NO_D.U_ILA/U_STAT/TDO_mux_in<0>1 ; - wire \U0/I_NO_D.U_ILA/U_STAT/TDO_next ; - wire \U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10_443 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101_444 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11_445 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5_446 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13_447 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14_448 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3_449 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4_450 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6_451 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_452 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5_453 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_454 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_455 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5_456 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15_463 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2_464 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26_465 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36_466 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82_467 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5_470 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6_471 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_472 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_473 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f51 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_475 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121_476 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122_477 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5_478 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13_479 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131_480 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132_481 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14_482 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7_483 ; - wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6_484 ; - wire \U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE ; - wire \U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ; - wire \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1_535 ; - wire \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1_537 ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/iTRIGGER ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/iTRIGGER ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/DOUT_tmp ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/dout_tmp ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/DOUT_tmp ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/dout_tmp ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/DOUT_tmp ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/dout_tmp ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/DOUT_tmp ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<3> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<4> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ; - wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/dout_tmp ; - wire \U0/I_NO_D.U_ILA/U_TRIG/trigCondOut ; - wire \U0/I_NO_D.U_ILA/iARM ; - wire \U0/I_NO_D.U_ILA/iCAPTURE ; - wire \U0/I_NO_D.U_ILA/iCAP_DONE ; - wire \U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT ; - wire \U0/I_NO_D.U_ILA/iCAP_WR_EN ; - wire \U0/I_NO_D.U_ILA/iDATA_DOUT ; - wire \U0/I_NO_D.U_ILA/iSTAT_DOUT ; - wire \U0/I_NO_D.U_ILA/iTRIGGER ; - wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4_Q15_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_STAT/U_DSR_O_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B_O_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E_Q15_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<31>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<30>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<29>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<28>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<27>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<26>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<25>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<24>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<23>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<22>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<21>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<20>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<19>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<18>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<17>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<16>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<15>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<14>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<13>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<12>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<11>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<10>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<9>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<8>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<7>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<6>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<5>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<4>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<3>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<2>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<1>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<0>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<3>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<2>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<1>_UNCONNECTED ; - wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<0>_UNCONNECTED ; - wire [27 : 0] \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp ; - wire [13 : 1] \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI ; - wire [13 : 0] \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D ; - wire [13 : 0] \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S ; - wire [13 : 0] \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR ; - wire [3 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA ; - wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO ; - wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO ; - wire [3 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA ; - wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO ; - wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO ; - wire [7 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA ; - wire [7 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO ; - wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO ; - wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO ; - wire [7 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA ; - wire [7 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO ; - wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO ; - wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO ; - wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DATA ; - wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO ; - wire [3 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA ; - wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO ; - wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO ; - wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DATA ; - wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO ; - wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DATA ; - wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO ; - wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next ; - wire [8 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI ; - wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D ; - wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S ; - wire [8 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI ; - wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D ; - wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S ; - wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/cfg_data ; - wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData ; - wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/cfg_data ; - wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData ; - wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/cfg_data ; - wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData ; - wire [4 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data ; - wire [16 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec ; - wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR ; - wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT ; - wire [9 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data ; - wire [1 : 0] \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN ; - wire [1 : 0] \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN ; - wire [0 : 0] \U0/I_NO_D.U_ILA/U_RST/iRESET ; - wire [8 : 0] \U0/I_NO_D.U_ILA/U_STAT/NS_dstat ; - wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/STATE_dstat ; - wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN ; - wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly ; - wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT ; - wire [9 : 1] \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI ; - wire [9 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D ; - wire [9 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S ; - wire [16 : 0] \U0/I_NO_D.U_ILA/U_STAT/iSTAT ; - wire [9 : 0] \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT ; - wire [1 : 1] \U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCFG_DATA ; - wire [3 : 0] \U0/I_NO_D.U_ILA/U_TRIG/trigCondIn ; - wire [8 : 0] \U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES ; - wire [1 : 0] \U0/I_NO_D.U_ILA/iCAP_STATE ; - wire [8 : 0] \U0/I_NO_D.U_ILA/iCAP_WR_ADDR ; - wire [27 : 0] \U0/I_NO_D.U_ILA/iDATA ; - wire [7 : 0] \U0/I_NO_D.U_ILA/iRESET ; - wire [8 : 0] \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy ; - wire [8 : 0] \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut ; - wire [27 : 0] \U0/iTRIG_IN ; - GND XST_GND ( - .G(N0) - ); - VCC XST_VCC ( - .P(N1) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_WCNT_HCMP_Q ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP ), - .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_WCNT_LCMP_Q ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP ), - .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_SCNT_CMP_Q ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP ), - .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE0 ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iCAP_WR_EN ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1 ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iCAP_WR_EN ), - .R(\U0/I_NO_D.U_ILA/iRESET [7]), - .Q(\U0/I_NO_D.U_ILA/iCAP_WR_EN ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG0 ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_IN ), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_OUT ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG1 ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_OUT ), - .R(\U0/I_NO_D.U_ILA/iRESET [7]), - .Q(\U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iOUT ), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_STATE [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iOUT ), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_STATE [1]) - ); - LUT3 #( - .INIT ( 8'h20 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG ( - .I0(\U0/I_NO_D.U_ILA/iTRIGGER ), - .I1(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .I2(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_IN ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/I_NOLUT6.I_SRL_T2.U_SRLC16E ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [5]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/I_NOLUT6.I_SRL_T2.U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [4]), - .I1(CONTROL[9]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/I_NOLUT6.I_SRL_T2.U_SRLC16E ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/iCFG_DIN ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/I_NOLUT6.I_SRL_T2.U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [3]), - .I1(CONTROL[9]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/iCFG_DIN ) - ); - LUT3 #( - .INIT ( 8'hCA )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.U_MUXF7 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [1]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [0]), - .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iOUT ) - ); - MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF6 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [1]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [0]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [0]) - ); - MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF6 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [3]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [2]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [1]) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF5 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [1]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [0]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [0]) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF5 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [3]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [2]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [1]) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U2_MUXF5 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [5]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [4]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [2]) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U3_MUXF5 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [7]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [6]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [3]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF0_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [1]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [0]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [2]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG0_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [2]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [1]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [1]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF1_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [3]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [2]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [2]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG1_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [4]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [3]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [3]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF2_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [5]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [4]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [4]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG2_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [6]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [5]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [5]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF3_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [7]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [6]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [6]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG3_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DIN ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [7]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [7]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [1]), - .I1(CONTROL[9]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DIN ) - ); - LUT3 #( - .INIT ( 8'hCA )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.U_MUXF7 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [1]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [0]), - .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iOUT ) - ); - MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF6 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [1]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [0]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [0]) - ); - MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF6 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [3]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [2]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [1]) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF5 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [1]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [0]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [0]) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF5 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [3]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [2]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [1]) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U2_MUXF5 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [5]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [4]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [2]) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U3_MUXF5 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [7]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [6]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [3]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF0_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [1]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [0]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [1]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG0_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [2]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [1]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [1]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF1_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [3]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [2]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [2]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG1_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [4]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [3]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [3]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF2_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [5]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [4]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [4]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG2_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [6]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [5]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [5]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF3_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [7]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [6]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [6]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG3_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DIN ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [7]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [7]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [0]), - .I1(CONTROL[9]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DIN ) - ); - MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF6 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [1]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [0]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.U0_MUXF5 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [1]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [0]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [0]) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.U1_MUXF5 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [3]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [2]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [1]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF0_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [1]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [0]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [6]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG0_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [2]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [1]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [1]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF1_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [3]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [2]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [2]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG1_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DIN ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [3]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [3]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [5]), - .I1(CONTROL[9]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DIN ) - ); - MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF6 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [1]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [0]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.U0_MUXF5 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [1]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [0]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [0]) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.U1_MUXF5 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [3]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [2]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [1]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF0_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [1]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [0]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [3]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG0_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [2]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [1]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [1]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF1_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [3]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [2]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [2]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG1_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DIN ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [3]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [3]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [2]), - .I1(CONTROL[9]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DIN ) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF5 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [1]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [0]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_CE ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DATA [1]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [0]), - .Q15(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4_Q15_UNCONNECTED ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG_cs_cfglut4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DIN ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [1]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DATA [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [9]), - .I1(CONTROL[9]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DIN ) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF5 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [1]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [0]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_CE ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DATA [1]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [0]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [9]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG_cs_cfglut4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DIN ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [1]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DATA [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [8]), - .I1(CONTROL[9]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DIN ) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF5 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [1]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [0]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_CE ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DATA [1]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [0]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [8]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG_cs_cfglut4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DIN ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [1]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DATA [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [7]), - .I1(CONTROL[9]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DIN ) - ); - LUT3 #( - .INIT ( 8'hCA )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.U_MUXF6 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [1]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [0]), - .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iOUT ) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.U0_MUXF5 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [1]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [0]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [0]) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.U1_MUXF5 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [3]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [2]), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [1]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF0_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [1]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [0]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [7]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG0_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [2]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [1]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [1]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF1_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [3]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [2]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [2]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG1_CFGLUT4 ( - .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), - .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DIN ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [3]), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [3]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [6]), - .I1(CONTROL[9]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DIN ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iOUT ), - .R(N0), - .Q(\U0/I_NO_D.U_ILA/iCAP_DONE ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[8].U_FDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [8]), - .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].U_FDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [7]), - .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].U_FDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [6]), - .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].U_FDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [5]), - .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].U_FDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [4]), - .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].U_FDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [3]), - .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].U_FDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [2]), - .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].U_FDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [1]), - .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].U_FDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [0]), - .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[8].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [8]) - ); - XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[8].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [8]), - .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [8]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [8]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [7]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [7]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [7]), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [8]) - ); - XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [7]), - .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [7]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [7]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [6]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [6]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [6]), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [7]) - ); - XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [6]), - .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [6]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [6]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [5]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [5]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [5]), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [6]) - ); - XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [5]), - .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [5]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [5]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [4]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [4]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [4]), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [5]) - ); - XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [4]), - .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [4]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [4]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [3]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [3]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [3]), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [4]) - ); - XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [3]), - .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [3]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [3]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [2]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [2]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [2]), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [3]) - ); - XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [2]), - .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [2]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [2]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [1]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [1]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [1]), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [2]) - ); - XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [1]), - .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [1]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [1]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [0]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].GnH.U_MUXCY ( - .CI(N1), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [0]), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [1]) - ); - XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].U_XORCY ( - .CI(N1), - .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [0]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [0]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[8].U_FDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [8]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].U_FDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [7]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].U_FDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [6]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].U_FDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [5]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].U_FDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [4]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].U_FDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [3]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].U_FDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [2]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].U_FDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [1]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].U_FDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [0]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[8].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [8]) - ); - XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[8].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [8]), - .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [8]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [8]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [7]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [7]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [7]), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [8]) - ); - XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [7]), - .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [7]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [7]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [6]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [6]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [6]), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [7]) - ); - XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [6]), - .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [6]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [6]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [5]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [5]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [5]), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [6]) - ); - XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [5]), - .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [5]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [5]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [4]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [4]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [4]), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [5]) - ); - XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [4]), - .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [4]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [4]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [3]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [3]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [3]), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [4]) - ); - XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [3]), - .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [3]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [3]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [2]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [2]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [2]), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [3]) - ); - XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [2]), - .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [2]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [2]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [1]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [1]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [1]), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [2]) - ); - XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [1]), - .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [1]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [1]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [0]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].GnH.U_MUXCY ( - .CI(N1), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [0]), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [1]) - ); - XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].U_XORCY ( - .CI(N1), - .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [0]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [0]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[8] ), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( - .A0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]), - .A1(N1), - .A2(N1), - .A3(N1), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[8] ), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/cfg_data [1]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N1), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [0]), - .Q(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( - .CI(N1), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[0] ), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[1] ), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( - .A0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]), - .A1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]), - .A2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]), - .A3(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[0] ), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [1]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( - .A0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]), - .A1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]), - .A2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]), - .A3(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/cfg_data [1]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[1] ), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData ) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[8] ), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( - .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), - .A1(N1), - .A2(N1), - .A3(N1), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[8] ), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N1), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [2]), - .Q(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ) -, - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( - .CI(N1), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[0] ), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[1] ), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( - .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), - .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), - .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[0] ), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [3]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( - .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), - .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), - .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), - .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[1] ), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[8] ), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( - .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), - .A1(N1), - .A2(N1), - .A3(N1), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[8] ), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N1), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [4]), - .Q(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ) -, - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( - .CI(N1), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[0] ), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( - .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[1] ), - .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( - .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), - .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), - .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), - .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[0] ), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [0]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( - .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), - .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), - .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), - .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[1] ), - .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_BRK1 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [3]), - .I1(CONTROL[9]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_BRK0 ( - .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [1]), - .I1(CONTROL[9]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [2]) - ); - LUT3 #( - .INIT ( 8'hCA )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_CAP_ADDR_MUX ( - .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]), - .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [9]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [8]) - ); - LUT3 #( - .INIT ( 8'hCA )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_CAP_ADDR_MUX ( - .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]), - .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [8]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [7]) - ); - LUT3 #( - .INIT ( 8'hCA )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_CAP_ADDR_MUX ( - .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]), - .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [7]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [6]) - ); - LUT3 #( - .INIT ( 8'hCA )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_CAP_ADDR_MUX ( - .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]), - .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [6]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [5]) - ); - LUT3 #( - .INIT ( 8'hCA )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_CAP_ADDR_MUX ( - .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]), - .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [5]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [4]) - ); - LUT3 #( - .INIT ( 8'hCA )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_CAP_ADDR_MUX ( - .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]), - .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [4]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [3]) - ); - LUT3 #( - .INIT ( 8'hCA )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_CAP_ADDR_MUX ( - .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]), - .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [3]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [2]) - ); - LUT3 #( - .INIT ( 8'hCA )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_CAP_ADDR_MUX ( - .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [2]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [1]) - ); - LUT3 #( - .INIT ( 8'hCA )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_CAP_ADDR_MUX ( - .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), - .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]), - .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [1]), - .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [0]) - ); - SRL16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.I_SRL.U_SELX ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N1), - .CE(CONTROL[9]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [16]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_CAP_ADDR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [8]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_iCAP_ADDR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [8]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_CAP_ADDR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [7]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_iCAP_ADDR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [7]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_CAP_ADDR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [6]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_iCAP_ADDR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [6]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_CAP_ADDR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [5]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_iCAP_ADDR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [5]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_CAP_ADDR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [4]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_iCAP_ADDR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [4]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_CAP_ADDR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [3]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_iCAP_ADDR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [3]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_CAP_ADDR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [2]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_iCAP_ADDR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [2]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_CAP_ADDR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [1]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_iCAP_ADDR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [1]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_CAP_ADDR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [0]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_iCAP_ADDR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [0]), - .R(\U0/I_NO_D.U_ILA/iRESET [6]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[15].U_SEL ( - .C(CONTROL[0]), - .CE(CONTROL[9]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [15]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[14].U_SEL ( - .C(CONTROL[0]), - .CE(CONTROL[9]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [14]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[13].U_SEL ( - .C(CONTROL[0]), - .CE(CONTROL[9]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [13]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[12].U_SEL ( - .C(CONTROL[0]), - .CE(CONTROL[9]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [12]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[11].U_SEL ( - .C(CONTROL[0]), - .CE(CONTROL[9]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [11]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[10].U_SEL ( - .C(CONTROL[0]), - .CE(CONTROL[9]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [10]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[9].U_SEL ( - .C(CONTROL[0]), - .CE(CONTROL[9]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [9]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[8].U_SEL ( - .C(CONTROL[0]), - .CE(CONTROL[9]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [8]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[7].U_SEL ( - .C(CONTROL[0]), - .CE(CONTROL[9]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [7]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[6].U_SEL ( - .C(CONTROL[0]), - .CE(CONTROL[9]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [6]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[5].U_SEL ( - .C(CONTROL[0]), - .CE(CONTROL[9]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [5]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[4].U_SEL ( - .C(CONTROL[0]), - .CE(CONTROL[9]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [4]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[3].U_SEL ( - .C(CONTROL[0]), - .CE(CONTROL[9]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [3]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[2].U_SEL ( - .C(CONTROL[0]), - .CE(CONTROL[9]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [2]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[1].U_SEL ( - .C(CONTROL[0]), - .CE(CONTROL[9]), - .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [1]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[0].U_SEL ( - .C(CONTROL[0]), - .CE(CONTROL[9]), - .D(CONTROL[1]), - .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DSL2 ( - .C(CLK), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DSL3 ( - .C(CLK), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_CR ( - .C(CLK), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/iRESET [0]), - .Q(\U0/I_NO_D.U_ILA/U_STAT/CAP_RESET_dly1 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/G_NS[8].U_NSQ ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), - .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), - .R(\U0/I_NO_D.U_ILA/iARM ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [8]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/G_NS[7].U_NSQ ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), - .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), - .R(\U0/I_NO_D.U_ILA/iARM ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [7]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/G_NS[6].U_NSQ ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), - .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), - .R(\U0/I_NO_D.U_ILA/iARM ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [6]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/G_NS[5].U_NSQ ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), - .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), - .R(\U0/I_NO_D.U_ILA/iARM ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [5]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/G_NS[4].U_NSQ ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), - .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), - .R(\U0/I_NO_D.U_ILA/iARM ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [4]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/G_NS[3].U_NSQ ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), - .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), - .R(\U0/I_NO_D.U_ILA/iARM ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/G_NS[2].U_NSQ ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), - .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), - .R(\U0/I_NO_D.U_ILA/iARM ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/G_NS[1].U_NSQ ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), - .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), - .R(\U0/I_NO_D.U_ILA/iARM ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [1]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/G_NS[0].U_NSQ ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), - .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), - .R(\U0/I_NO_D.U_ILA/iARM ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [0]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STATE1 ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ), - .D(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), - .R(\U0/I_NO_D.U_ILA/iARM ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [1]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STATE0 ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ), - .D(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), - .R(\U0/I_NO_D.U_ILA/iARM ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [0]) - ); - FDRS #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_ARM ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ), - .R(\U0/I_NO_D.U_ILA/iRESET [0]), - .S(\U0/I_NO_D.U_ILA/iARM ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ) - ); - FDRS #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_TRIGGER ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ), - .R(\U0/I_NO_D.U_ILA/iRESET [0]), - .S(\U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ) - ); - FDRS #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_FULL ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ), - .R(\U0/I_NO_D.U_ILA/iARM ), - .S(\U0/I_NO_D.U_ILA/iCAP_DONE ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ) - ); - FDRS #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_ECR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ), - .R(\U0/I_NO_D.U_ILA/iARM ), - .S(N1), - .Q(\U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDCE ( - .C(CONTROL[0]), - .CE(N1), - .CLR(\U0/I_NO_D.U_ILA/iARM ), - .D(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0 ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDPE ( - .C(CONTROL[0]), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ), - .PRE(CONTROL[13]), - .Q(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1 ) - ); - LDC #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC ( - .CLR(\U0/I_NO_D.U_ILA/iARM ), - .D(N1), - .G(CONTROL[13]), - .Q(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_RISING ( - .C(CLK), - .CE(N1), - .CLR(\U0/I_NO_D.U_ILA/U_STAT/ACTRESET_pulse ), - .D(N1), - .Q(\U0/I_NO_D.U_ILA/U_STAT/ACT_dstat ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_TDO ( - .C(CONTROL[0]), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_STAT/TDO_next ), - .Q(\U0/I_NO_D.U_ILA/iSTAT_DOUT ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_GEN_DELAY[1].U_FD ( - .C(CLK), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [0]), - .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_RFDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ), - .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ), - .D(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [0]), - .R(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [1]), - .Q(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT1 ( - .C(CLK), - .CE(N1), - .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ), - .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [0]), - .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT0 ( - .C(CLK), - .CE(N1), - .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ), - .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_TFDRE ( - .C(CONTROL[0]), - .CE(CONTROL[5]), - .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ), - .D(CONTROL[5]), - .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/I_H2L.U_DOUT ( - .C(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [1]), - .R(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [0]), - .Q(\U0/I_NO_D.U_ILA/U_STAT/ACTRESET_pulse ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/U_DOUT1 ( - .C(CONTROL[0]), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [0]), - .Q(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/U_DOUT0 ( - .C(CONTROL[0]), - .CE(N1), - .D(CONTROL[5]), - .Q(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [0]) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4_450 ), - .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3_449 ), - .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), - .O(\U0/I_NO_D.U_ILA/U_STAT/TDO_mux_in<0>1 ) - ); - LUT4 #( - .INIT ( 16'h5140 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_455 ), - .I3(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_452 ), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4_450 ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1_535 ), - .I2(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5_446 ), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_452 ) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14_448 ), - .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13_447 ), - .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5_446 ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14_448 ) - ); - LUT3 #( - .INIT ( 8'h53 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [1]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [0]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13_447 ) - ); - LUT4 #( - .INIT ( 16'hFBEA )) - \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1_537 ), - .I3(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6_451 ), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3_449 ) - ); - MUXF6 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5_456 ), - .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5_453 ), - .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6_451 ) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11_445 ), - .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101_444 ), - .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5_456 ) - ); - LUT3 #( - .INIT ( 8'h53 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [1]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [0]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11_445 ) - ); - LUT3 #( - .INIT ( 8'h53 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [3]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [2]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101_444 ) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10_443 ), - .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_454 ), - .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5_453 ) - ); - LUT3 #( - .INIT ( 8'h53 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [5]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [4]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10_443 ) - ); - LUT3 #( - .INIT ( 8'h53 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [7]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [6]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_454 ) - ); - MUXF7 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6_471 ), - .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6_484 ), - .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7_483 ) - ); - MUXF6 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5_478 ), - .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f51 ), - .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6_471 ) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14_482 ), - .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132_481 ), - .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5_478 ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [0]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [1]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14_482 ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [2]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132_481 ) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_0 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131_480 ), - .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122_477 ), - .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f51 ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [4]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [5]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131_480 ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [6]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [7]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122_477 ) - ); - MUXF6 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_473 ), - .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5_470 ), - .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6_484 ) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13_479 ), - .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121_476 ), - .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_473 ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [8]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [9]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13_479 ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [10]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [11]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121_476 ) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_475 ), - .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_472 ), - .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5_470 ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [12]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [13]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_475 ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [14]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [15]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_472 ) - ); - LUT2 #( - .INIT ( 4'hE )) - \U0/I_NO_D.U_ILA/U_STAT/U_STATCMD ( - .I0(CONTROL[4]), - .I1(CONTROL[5]), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE ) - ); - INV \U0/I_NO_D.U_ILA/U_STAT/U_STATCMD_n ( - .I(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE ), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DSL ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ), - .I1(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ), - .O(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DSR ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ), - .I1(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ), - .O(\NLW_U0/I_NO_D.U_ILA/U_STAT/U_DSR_O_UNCONNECTED ) - ); - LUT4 #( - .INIT ( 16'h0F22 )) - \U0/I_NO_D.U_ILA/U_STAT/U_NSL ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ), - .I1(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ), - .I2(\U0/I_NO_D.U_ILA/U_STAT/CAP_RESET_dly1 ), - .I3(\U0/I_NO_D.U_ILA/iRESET [0]), - .O(\U0/I_NO_D.U_ILA/U_STAT/NS_load ) - ); - LUT4 #( - .INIT ( 16'h0030 )) - \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[16].I_STAT.U_STAT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [16]) - ); - LUT4 #( - .INIT ( 16'h1030 )) - \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[15].I_STAT.U_STAT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [15]) - ); - LUT4 #( - .INIT ( 16'h0070 )) - \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[14].I_STAT.U_STAT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [14]) - ); - LUT4 #( - .INIT ( 16'h1020 )) - \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[13].I_STAT.U_STAT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [13]) - ); - LUT4 #( - .INIT ( 16'h0070 )) - \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[12].I_STAT.U_STAT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [12]) - ); - LUT4 #( - .INIT ( 16'h1010 )) - \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[11].I_STAT.U_STAT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [11]) - ); - LUT4 #( - .INIT ( 16'h0070 )) - \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[10].I_STAT.U_STAT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [10]) - ); - LUT4 #( - .INIT ( 16'h100F )) - \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[9].I_STAT.U_STAT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [9]) - ); - LUT4 #( - .INIT ( 16'hFFF0 )) - \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[8].I_STAT.U_STAT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [8]) - ); - LUT4 #( - .INIT ( 16'h0004 )) - \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[7].I_STAT.U_STAT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [7]) - ); - LUT4 #( - .INIT ( 16'h3000 )) - \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[6].I_STAT.U_STAT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [6]) - ); - LUT4 #( - .INIT ( 16'h001F )) - \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[5].I_STAT.U_STAT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [5]) - ); - LUT4 #( - .INIT ( 16'hF001 )) - \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[4].I_STAT.U_STAT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [4]) - ); - LUT4 #( - .INIT ( 16'hB610 )) - \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[3].I_STAT.U_STAT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [3]) - ); - LUT4 #( - .INIT ( 16'h2100 )) - \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[2].I_STAT.U_STAT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [2]) - ); - LUT4 #( - .INIT ( 16'hC102 )) - \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[1].I_STAT.U_STAT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [1]) - ); - LUT4 #( - .INIT ( 16'h0101 )) - \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[0].I_STAT.U_STAT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [0]) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_CLEAR ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [1]), - .I1(CONTROL[5]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ) - ); - XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].U_XORCY ( - .CI(N1), - .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [0]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [0]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].GnH.U_MUXCY ( - .CI(N1), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [0]), - .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [1]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [0]) - ); - XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [1]), - .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [1]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [1]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [1]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [1]), - .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [2]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [1]) - ); - XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [2]), - .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [2]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [2]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [2]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [2]), - .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [3]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [2]) - ); - XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [3]), - .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [3]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [3]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [3]), - .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [4]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [3]) - ); - XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [4]), - .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [4]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [4]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [4]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [4]), - .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [5]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [4]) - ); - XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [5]), - .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [5]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [5]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [5]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [5]), - .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [6]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [5]) - ); - XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [6]), - .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [6]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [6]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [6]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [6]), - .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [7]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [6]) - ); - XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [7]), - .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [7]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [7]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [7]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [7]), - .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [8]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [7]) - ); - XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [8]), - .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [8]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [8]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [8]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [8]), - .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [9]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [8]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [8]) - ); - XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[9].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [9]), - .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [9]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [9]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[9].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [9]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].U_FDRE ( - .C(CONTROL[0]), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [0]), - .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].U_FDRE ( - .C(CONTROL[0]), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [1]), - .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].U_FDRE ( - .C(CONTROL[0]), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [2]), - .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].U_FDRE ( - .C(CONTROL[0]), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [3]), - .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].U_FDRE ( - .C(CONTROL[0]), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [4]), - .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].U_FDRE ( - .C(CONTROL[0]), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [5]), - .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].U_FDRE ( - .C(CONTROL[0]), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [6]), - .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].U_FDRE ( - .C(CONTROL[0]), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [7]), - .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].U_FDRE ( - .C(CONTROL[0]), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [8]), - .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [8]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[9].U_FDRE ( - .C(CONTROL[0]), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [9]), - .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), - .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_RST/U_POR ( - .C(CLK), - .D(N0), - .PRE(N0), - .Q(\U0/I_NO_D.U_ILA/U_RST/POR ) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_RST/iRESET [0]), - .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), - .Q(\U0/I_NO_D.U_ILA/iRESET [0]) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_RST/G_RST[1].U_RST ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/iRESET [0]), - .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), - .Q(\U0/I_NO_D.U_ILA/iRESET [1]) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_RST/G_RST[2].U_RST ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/iRESET [1]), - .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), - .Q(\U0/I_NO_D.U_ILA/iRESET [2]) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_RST/G_RST[3].U_RST ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/iRESET [2]), - .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), - .Q(\U0/I_NO_D.U_ILA/iRESET [3]) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_RST/G_RST[4].U_RST ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/iRESET [3]), - .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), - .Q(\U0/I_NO_D.U_ILA/iRESET [4]) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_RST/G_RST[5].U_RST ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/iRESET [4]), - .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), - .Q(\U0/I_NO_D.U_ILA/iRESET [5]) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_RST/G_RST[6].U_RST ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/iRESET [5]), - .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), - .Q(\U0/I_NO_D.U_ILA/iRESET [6]) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_RST/G_RST[7].U_RST ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/iRESET [6]), - .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), - .Q(\U0/I_NO_D.U_ILA/iRESET [7]) - ); - LUT3 #( - .INIT ( 8'hEF )) - \U0/I_NO_D.U_ILA/U_RST/U_PRST1 ( - .I0(\U0/I_NO_D.U_ILA/U_RST/HALT_pulse ), - .I1(\U0/I_NO_D.U_ILA/U_RST/POR ), - .I2(N1), - .O(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET1 ) - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/I_NO_D.U_ILA/U_RST/U_PRST0 ( - .I0(N0), - .I1(\U0/I_NO_D.U_ILA/iCAP_DONE ), - .I2(N0), - .I3(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET1 ), - .O(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/I_NO_D.U_ILA/U_RST/U_RST0 ( - .I0(\U0/I_NO_D.U_ILA/iARM ), - .I1(\U0/I_NO_D.U_ILA/iRESET [0]), - .O(\U0/I_NO_D.U_ILA/U_RST/iRESET [0]) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_CLEAR ( - .I0(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[2] ), - .I1(CONTROL[13]), - .O(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[2].U_FD ( - .C(CLK), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_RST/HALT_pulse ), - .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD ( - .C(CLK), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[0] ), - .Q(\U0/I_NO_D.U_ILA/U_RST/HALT_pulse ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_RFDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ), - .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ), - .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ), - .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[0] ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [0]), - .R(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [1]), - .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT1 ( - .C(CLK), - .CE(N1), - .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ), - .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [0]), - .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT0 ( - .C(CLK), - .CE(N1), - .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ), - .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched ), - .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_TFDRE ( - .C(CONTROL[0]), - .CE(CONTROL[13]), - .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ), - .D(CONTROL[13]), - .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_CLEAR ( - .I0(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[4] ), - .I1(CONTROL[12]), - .O(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[4].U_FD ( - .C(CLK), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/iARM ), - .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[4] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD ( - .C(CLK), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[2] ), - .Q(\U0/I_NO_D.U_ILA/iARM ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[2].U_FD ( - .C(CLK), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[1] ), - .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[1].U_FD ( - .C(CLK), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[0] ), - .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[1] ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_RFDRE ( - .C(CLK), - .CE(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ), - .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ), - .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ), - .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[0] ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [0]), - .R(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [1]), - .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT1 ( - .C(CLK), - .CE(N1), - .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ), - .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [0]), - .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT0 ( - .C(CLK), - .CE(N1), - .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ), - .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched ), - .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_TFDRE ( - .C(CONTROL[0]), - .CE(CONTROL[12]), - .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ), - .D(CONTROL[12]), - .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[13].U_FDRE ( - .C(CONTROL[0]), - .CE(CONTROL[6]), - .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [13]), - .R(CONTROL[14]), - .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [13]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].U_FDRE ( - .C(CONTROL[0]), - .CE(CONTROL[6]), - .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [12]), - .R(CONTROL[14]), - .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [12]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].U_FDRE ( - .C(CONTROL[0]), - .CE(CONTROL[6]), - .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [11]), - .R(CONTROL[14]), - .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [11]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].U_FDRE ( - .C(CONTROL[0]), - .CE(CONTROL[6]), - .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [10]), - .R(CONTROL[14]), - .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [10]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].U_FDRE ( - .C(CONTROL[0]), - .CE(CONTROL[6]), - .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [9]), - .R(CONTROL[14]), - .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [9]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].U_FDRE ( - .C(CONTROL[0]), - .CE(CONTROL[6]), - .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [8]), - .R(CONTROL[14]), - .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [8]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].U_FDRE ( - .C(CONTROL[0]), - .CE(CONTROL[6]), - .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [7]), - .R(CONTROL[14]), - .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [7]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].U_FDRE ( - .C(CONTROL[0]), - .CE(CONTROL[6]), - .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [6]), - .R(CONTROL[14]), - .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [6]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].U_FDRE ( - .C(CONTROL[0]), - .CE(CONTROL[6]), - .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [5]), - .R(CONTROL[14]), - .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [5]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].U_FDRE ( - .C(CONTROL[0]), - .CE(CONTROL[6]), - .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [4]), - .R(CONTROL[14]), - .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [4]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].U_FDRE ( - .C(CONTROL[0]), - .CE(CONTROL[6]), - .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [3]), - .R(CONTROL[14]), - .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].U_FDRE ( - .C(CONTROL[0]), - .CE(CONTROL[6]), - .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [2]), - .R(CONTROL[14]), - .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].U_FDRE ( - .C(CONTROL[0]), - .CE(CONTROL[6]), - .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [1]), - .R(CONTROL[14]), - .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [1]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].U_FDRE ( - .C(CONTROL[0]), - .CE(CONTROL[6]), - .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [0]), - .R(CONTROL[14]), - .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [0]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[13].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [13]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [13]) - ); - XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[13].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [13]), - .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [13]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [13]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [12]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [12]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [12]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [12]), - .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [13]) - ); - XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [12]), - .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [12]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [12]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [11]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [11]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [11]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [11]), - .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [12]) - ); - XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [11]), - .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [11]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [11]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [10]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [10]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [10]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [10]), - .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [11]) - ); - XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [10]), - .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [10]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [10]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [9]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [9]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [9]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [9]), - .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [10]) - ); - XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [9]), - .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [9]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [9]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [8]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [8]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [8]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [8]), - .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [9]) - ); - XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [8]), - .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [8]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [8]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [7]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [7]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [7]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [7]), - .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [8]) - ); - XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [7]), - .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [7]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [7]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [6]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [6]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [6]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [6]), - .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [7]) - ); - XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [6]), - .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [6]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [6]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [5]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [5]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [5]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [5]), - .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [6]) - ); - XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [5]), - .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [5]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [5]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [4]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [4]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [4]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [4]), - .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [5]) - ); - XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [4]), - .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [4]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [4]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [3]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [3]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [3]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [3]), - .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [4]) - ); - XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [3]), - .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [3]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [3]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [2]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [2]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [2]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [2]), - .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [3]) - ); - XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [2]), - .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [2]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [2]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [1]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [1]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].GnH.U_MUXCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [1]), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [1]), - .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [2]) - ); - XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].U_XORCY ( - .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [1]), - .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [1]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [1]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [0]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [0]) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].GnH.U_MUXCY ( - .CI(N1), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [0]), - .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [1]) - ); - XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].U_XORCY ( - .CI(N1), - .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [0]), - .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [0]) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [24]), - .PRE(CONTROL[23]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [25]), - .PRE(CONTROL[23]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [26]), - .PRE(CONTROL[23]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [27]), - .PRE(CONTROL[23]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_OREG.U_OREG ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ), - .S(\U0/I_NO_D.U_ILA/iRESET [0]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/DOUT_tmp ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N1), - .CE(CONTROL[23]), - .CLK(CONTROL[0]), - .D(CONTROL[1]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<4> ), - .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( - .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ), - .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ), - .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ), - .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ), - .CE(CONTROL[23]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<3> ), - .Q15 -(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ) - - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_YES_MUXH.U_MUXH ( - .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<4> ), - .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL ( - .CI(N1), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<3> ), - .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [0]), - .PRE(CONTROL[20]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [1]), - .PRE(CONTROL[20]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [2]), - .PRE(CONTROL[20]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [3]), - .PRE(CONTROL[20]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[4].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [4]), - .PRE(CONTROL[20]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[5].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [5]), - .PRE(CONTROL[20]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[6].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [6]), - .PRE(CONTROL[20]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[7].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [7]), - .PRE(CONTROL[20]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_OREG ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ), - .S(\U0/I_NO_D.U_ILA/iRESET [0]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/DOUT_tmp ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( - .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ), - .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ), - .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ), - .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ), - .CE(CONTROL[20]), - .CLK(CONTROL[0]), - .D(CONTROL[1]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), - .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( - .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ), - .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ), - .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ), - .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ), - .CE(CONTROL[20]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), - .Q15 -(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ) - - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( - .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), - .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( - .CI(N1), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), - .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ) - ); - XORCY \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_XORH ( - .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ), - .LI(N0), - .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [8]), - .PRE(CONTROL[21]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [9]), - .PRE(CONTROL[21]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [10]), - .PRE(CONTROL[21]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [11]), - .PRE(CONTROL[21]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[4].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [12]), - .PRE(CONTROL[21]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[5].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [13]), - .PRE(CONTROL[21]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[6].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [14]), - .PRE(CONTROL[21]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[7].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [15]), - .PRE(CONTROL[21]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_OREG ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ), - .S(\U0/I_NO_D.U_ILA/iRESET [0]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/DOUT_tmp ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( - .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ), - .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ), - .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ), - .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ), - .CE(CONTROL[21]), - .CLK(CONTROL[0]), - .D(CONTROL[1]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), - .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( - .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ), - .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ), - .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ), - .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ), - .CE(CONTROL[21]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), - .Q15 -(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ) - - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( - .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), - .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( - .CI(N1), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), - .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ) - ); - XORCY \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_XORH ( - .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ), - .LI(N0), - .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [16]), - .PRE(CONTROL[22]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [17]), - .PRE(CONTROL[22]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [18]), - .PRE(CONTROL[22]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [19]), - .PRE(CONTROL[22]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[4].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [20]), - .PRE(CONTROL[22]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[5].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [21]), - .PRE(CONTROL[22]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[6].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [22]), - .PRE(CONTROL[22]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[7].U_IREG ( - .C(CLK), - .CE(N1), - .D(\U0/iTRIG_IN [23]), - .PRE(CONTROL[22]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_OREG ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ), - .S(\U0/I_NO_D.U_ILA/iRESET [0]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/DOUT_tmp ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( - .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ), - .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ), - .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ), - .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ), - .CE(CONTROL[22]), - .CLK(CONTROL[0]), - .D(CONTROL[1]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), - .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( - .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ), - .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ), - .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ), - .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ), - .CE(CONTROL[22]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), - .Q15 -(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ) - - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( - .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), - .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ) - ); - MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( - .CI(N1), - .DI(N0), - .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), - .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ) - ); - XORCY \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_XORH ( - .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ), - .LI(N0), - .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[0].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [0]), - .Q(\U0/I_NO_D.U_ILA/iDATA [0]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[1].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [1]), - .Q(\U0/I_NO_D.U_ILA/iDATA [1]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[2].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [2]), - .Q(\U0/I_NO_D.U_ILA/iDATA [2]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[3].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [3]), - .Q(\U0/I_NO_D.U_ILA/iDATA [3]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[4].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [4]), - .Q(\U0/I_NO_D.U_ILA/iDATA [4]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[5].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [5]), - .Q(\U0/I_NO_D.U_ILA/iDATA [5]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[6].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [6]), - .Q(\U0/I_NO_D.U_ILA/iDATA [6]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[7].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [7]), - .Q(\U0/I_NO_D.U_ILA/iDATA [7]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[8].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [8]), - .Q(\U0/I_NO_D.U_ILA/iDATA [8]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[9].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [9]), - .Q(\U0/I_NO_D.U_ILA/iDATA [9]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[10].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [10]), - .Q(\U0/I_NO_D.U_ILA/iDATA [10]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[11].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [11]), - .Q(\U0/I_NO_D.U_ILA/iDATA [11]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[12].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [12]), - .Q(\U0/I_NO_D.U_ILA/iDATA [12]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[13].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [13]), - .Q(\U0/I_NO_D.U_ILA/iDATA [13]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[14].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [14]), - .Q(\U0/I_NO_D.U_ILA/iDATA [14]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[15].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [15]), - .Q(\U0/I_NO_D.U_ILA/iDATA [15]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[16].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [16]), - .Q(\U0/I_NO_D.U_ILA/iDATA [16]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[17].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [17]), - .Q(\U0/I_NO_D.U_ILA/iDATA [17]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[18].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [18]), - .Q(\U0/I_NO_D.U_ILA/iDATA [18]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[19].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [19]), - .Q(\U0/I_NO_D.U_ILA/iDATA [19]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[20].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [20]), - .Q(\U0/I_NO_D.U_ILA/iDATA [20]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[21].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [21]), - .Q(\U0/I_NO_D.U_ILA/iDATA [21]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[22].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [22]), - .Q(\U0/I_NO_D.U_ILA/iDATA [22]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[23].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [23]), - .Q(\U0/I_NO_D.U_ILA/iDATA [23]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[24].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [24]), - .Q(\U0/I_NO_D.U_ILA/iDATA [24]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[25].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [25]), - .Q(\U0/I_NO_D.U_ILA/iDATA [25]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[26].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [26]), - .Q(\U0/I_NO_D.U_ILA/iDATA [26]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[27].I_SRLT_NE_0.FF ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [27]), - .Q(\U0/I_NO_D.U_ILA/iDATA [27]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[0].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [0]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [0]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[1].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [1]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [1]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[2].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [2]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [2]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[3].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [3]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [3]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[4].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [4]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [4]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[5].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [5]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [5]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[6].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [6]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [6]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[7].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [7]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [7]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[8].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [8]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [8]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[9].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [9]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [9]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[10].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [10]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [10]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[11].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [11]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [11]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[12].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [12]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [12]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[13].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [13]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [13]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[14].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [14]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [14]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[15].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [15]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [15]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[16].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [16]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [16]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[17].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [17]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [17]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[18].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [18]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [18]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[19].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [19]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [19]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[20].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [20]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [20]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[21].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [21]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [21]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[22].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [22]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [22]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[23].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [23]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [23]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[24].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [24]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [24]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[25].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [25]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [25]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[26].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [26]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [26]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[27].I_SRLT_NE_0.DLY9 ( - .A0(N1), - .A1(N1), - .A2(N1), - .A3(N0), - .CLK(CLK), - .D(\U0/iTRIG_IN [27]), - .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [27]) - ); - LUT3 #( - .INIT ( 8'hCA )) - \U0/I_NO_D.U_ILA/U_DOUT ( - .I0(\U0/I_NO_D.U_ILA/iSTAT_DOUT ), - .I1(\U0/I_NO_D.U_ILA/iDATA_DOUT ), - .I2(CONTROL[6]), - .O(CONTROL[3]) - ); - LUT1 #( - .INIT ( 2'h1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B ( - .I0(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ), - .O(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B_O_UNCONNECTED ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E ( - .A0(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [0]), - .A1(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [1]), - .A2(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [2]), - .A3(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [3]), - .CE(CONTROL[8]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ), - .Q15 -(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E_Q15_UNCONNECTED ) - - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_LUT ( - .I0(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCFG_DATA [1]), - .I1(CONTROL[8]), - .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E ( - .A0(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [0]), - .A1(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [1]), - .A2(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [2]), - .A3(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [3]), - .CE(CONTROL[8]), - .CLK(CONTROL[0]), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ), - .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCFG_DATA [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_LUT ( - .I0(CONTROL[1]), - .I1(CONTROL[8]), - .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG ( - .C(CLK), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/DOUT_tmp ), - .PRE(\U0/I_NO_D.U_ILA/iRESET [1]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/dout_tmp ) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_NO.U_NO_MC_REG ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/dout_tmp ), - .S(\U0/I_NO_D.U_ILA/iRESET [2]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [2]) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG ( - .C(CLK), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/DOUT_tmp ), - .PRE(\U0/I_NO_D.U_ILA/iRESET [1]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/dout_tmp ) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_NO.U_NO_MC_REG ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/dout_tmp ), - .S(\U0/I_NO_D.U_ILA/iRESET [2]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [1]) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG ( - .C(CLK), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/DOUT_tmp ), - .PRE(\U0/I_NO_D.U_ILA/iRESET [1]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/dout_tmp ) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_NO.U_NO_MC_REG ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/dout_tmp ), - .S(\U0/I_NO_D.U_ILA/iRESET [2]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [0]) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG ( - .C(CLK), - .CE(N1), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/DOUT_tmp ), - .PRE(\U0/I_NO_D.U_ILA/iRESET [1]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/dout_tmp ) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_NO.U_NO_MC_REG ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/dout_tmp ), - .S(\U0/I_NO_D.U_ILA/iRESET [2]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_DLY ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ), - .R(\U0/I_NO_D.U_ILA/iRESET [3]), - .Q(\U0/I_NO_D.U_ILA/iCAPTURE ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_OUTREG.U_DOUT ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ), - .R(\U0/I_NO_D.U_ILA/iRESET [3]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/iTRIGGER ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TRIGQ ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/iTRIGGER ), - .R(\U0/I_NO_D.U_ILA/iRESET [4]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_OUTREG.U_DOUT ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ), - .R(\U0/I_NO_D.U_ILA/iRESET [3]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/iTRIGGER ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TRIGQ ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/iTRIGGER ), - .R(\U0/I_NO_D.U_ILA/iRESET [4]), - .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondOut ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/I_NO_D.U_ILA/U_TRIG/F_NO_TCMC.U_FDR ( - .C(CLK), - .D(\U0/I_NO_D.U_ILA/U_TRIG/trigCondOut ), - .R(\U0/I_NO_D.U_ILA/iRESET [5]), - .Q(\U0/I_NO_D.U_ILA/iTRIGGER ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ3.G_TW[3].U_TQ ( - .C(CLK), - .D(TRIG3[3]), - .PRE(N0), - .Q(\U0/iTRIG_IN [27]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ3.G_TW[2].U_TQ ( - .C(CLK), - .D(TRIG3[2]), - .PRE(N0), - .Q(\U0/iTRIG_IN [26]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ3.G_TW[1].U_TQ ( - .C(CLK), - .D(TRIG3[1]), - .PRE(N0), - .Q(\U0/iTRIG_IN [25]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ3.G_TW[0].U_TQ ( - .C(CLK), - .D(TRIG3[0]), - .PRE(N0), - .Q(\U0/iTRIG_IN [24]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ2.G_TW[7].U_TQ ( - .C(CLK), - .D(TRIG2[7]), - .PRE(N0), - .Q(\U0/iTRIG_IN [23]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ2.G_TW[6].U_TQ ( - .C(CLK), - .D(TRIG2[6]), - .PRE(N0), - .Q(\U0/iTRIG_IN [22]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ2.G_TW[5].U_TQ ( - .C(CLK), - .D(TRIG2[5]), - .PRE(N0), - .Q(\U0/iTRIG_IN [21]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ2.G_TW[4].U_TQ ( - .C(CLK), - .D(TRIG2[4]), - .PRE(N0), - .Q(\U0/iTRIG_IN [20]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ2.G_TW[3].U_TQ ( - .C(CLK), - .D(TRIG2[3]), - .PRE(N0), - .Q(\U0/iTRIG_IN [19]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ2.G_TW[2].U_TQ ( - .C(CLK), - .D(TRIG2[2]), - .PRE(N0), - .Q(\U0/iTRIG_IN [18]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ2.G_TW[1].U_TQ ( - .C(CLK), - .D(TRIG2[1]), - .PRE(N0), - .Q(\U0/iTRIG_IN [17]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ2.G_TW[0].U_TQ ( - .C(CLK), - .D(TRIG2[0]), - .PRE(N0), - .Q(\U0/iTRIG_IN [16]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ1.G_TW[7].U_TQ ( - .C(CLK), - .D(TRIG1[7]), - .PRE(N0), - .Q(\U0/iTRIG_IN [15]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ1.G_TW[6].U_TQ ( - .C(CLK), - .D(TRIG1[6]), - .PRE(N0), - .Q(\U0/iTRIG_IN [14]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ1.G_TW[5].U_TQ ( - .C(CLK), - .D(TRIG1[5]), - .PRE(N0), - .Q(\U0/iTRIG_IN [13]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ1.G_TW[4].U_TQ ( - .C(CLK), - .D(TRIG1[4]), - .PRE(N0), - .Q(\U0/iTRIG_IN [12]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ1.G_TW[3].U_TQ ( - .C(CLK), - .D(TRIG1[3]), - .PRE(N0), - .Q(\U0/iTRIG_IN [11]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ1.G_TW[2].U_TQ ( - .C(CLK), - .D(TRIG1[2]), - .PRE(N0), - .Q(\U0/iTRIG_IN [10]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ1.G_TW[1].U_TQ ( - .C(CLK), - .D(TRIG1[1]), - .PRE(N0), - .Q(\U0/iTRIG_IN [9]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ1.G_TW[0].U_TQ ( - .C(CLK), - .D(TRIG1[0]), - .PRE(N0), - .Q(\U0/iTRIG_IN [8]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ0.G_TW[7].U_TQ ( - .C(CLK), - .D(TRIG0[7]), - .PRE(N0), - .Q(\U0/iTRIG_IN [7]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ0.G_TW[6].U_TQ ( - .C(CLK), - .D(TRIG0[6]), - .PRE(N0), - .Q(\U0/iTRIG_IN [6]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ0.G_TW[5].U_TQ ( - .C(CLK), - .D(TRIG0[5]), - .PRE(N0), - .Q(\U0/iTRIG_IN [5]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ0.G_TW[4].U_TQ ( - .C(CLK), - .D(TRIG0[4]), - .PRE(N0), - .Q(\U0/iTRIG_IN [4]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ0.G_TW[3].U_TQ ( - .C(CLK), - .D(TRIG0[3]), - .PRE(N0), - .Q(\U0/iTRIG_IN [3]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ0.G_TW[2].U_TQ ( - .C(CLK), - .D(TRIG0[2]), - .PRE(N0), - .Q(\U0/iTRIG_IN [2]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ0.G_TW[1].U_TQ ( - .C(CLK), - .D(TRIG0[1]), - .PRE(N0), - .Q(\U0/iTRIG_IN [1]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/I_TQ0.G_TW[0].U_TQ ( - .C(CLK), - .D(TRIG0[0]), - .PRE(N0), - .Q(\U0/iTRIG_IN [0]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<0> ( - .I0(CONTROL[10]), - .I1(CONTROL[11]), - .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [0]) - ); - MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<0> ( - .CI(N1), - .DI(N0), - .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [0]), - .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [0]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<1> ( - .I0(CONTROL[12]), - .I1(CONTROL[13]), - .I2(CONTROL[9]), - .I3(CONTROL[14]), - .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [1]) - ); - MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<1> ( - .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [0]), - .DI(N0), - .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [1]), - .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [1]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<2> ( - .I0(CONTROL[15]), - .I1(CONTROL[16]), - .I2(CONTROL[8]), - .I3(CONTROL[17]), - .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [2]) - ); - MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<2> ( - .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [1]), - .DI(N0), - .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [2]), - .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [2]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<3> ( - .I0(CONTROL[18]), - .I1(CONTROL[21]), - .I2(CONTROL[7]), - .I3(CONTROL[19]), - .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [3]) - ); - MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3> ( - .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [2]), - .DI(N0), - .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [3]), - .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [3]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<4> ( - .I0(CONTROL[20]), - .I1(CONTROL[22]), - .I2(CONTROL[6]), - .I3(CONTROL[23]), - .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [4]) - ); - MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<4> ( - .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [3]), - .DI(N0), - .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [4]), - .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [4]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<5> ( - .I0(CONTROL[24]), - .I1(CONTROL[25]), - .I2(CONTROL[5]), - .I3(CONTROL[26]), - .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [5]) - ); - MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5> ( - .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [4]), - .DI(N0), - .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [5]), - .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [5]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<6> ( - .I0(CONTROL[27]), - .I1(CONTROL[28]), - .I2(CONTROL[2]), - .I3(CONTROL[29]), - .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [6]) - ); - MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<6> ( - .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [5]), - .DI(N0), - .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [6]), - .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [6]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<7> ( - .I0(CONTROL[30]), - .I1(CONTROL[31]), - .I2(CONTROL[1]), - .I3(CONTROL[32]), - .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [7]) - ); - MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7> ( - .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [6]), - .DI(N0), - .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [7]), - .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [7]) - ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<8> ( - .I0(CONTROL[33]), - .I1(CONTROL[34]), - .I2(CONTROL[4]), - .I3(CONTROL[35]), - .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [8]) - ); - MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8> ( - .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [7]), - .DI(N0), - .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [8]), - .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [8]) - ); - LUT4 #( - .INIT ( 16'hFEFF )) - \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [8]), - .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1_537 ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat1 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL ), - .I1(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0 ), - .I2(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1 ), - .O(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]), - .I1(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [8]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2_464 ) - ); - LUT4 #( - .INIT ( 16'h0001 )) - \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15_463 ) - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26_465 ) - ); - LUT4 #( - .INIT ( 16'hF222 )) - \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26_465 ), - .I1(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [8]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15_463 ), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [16]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36_466 ) - ); - LUT4 #( - .INIT ( 16'hAF8D )) - \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O129 ( - .I0(CONTROL[4]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2_464 ), - .I2(\U0/I_NO_D.U_ILA/U_STAT/TDO_mux_in<0>1 ), - .I3(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82_467 ), - .O(\U0/I_NO_D.U_ILA/U_STAT/TDO_next ) - ); - MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91 ( - .I0(N38), - .I1(N39), - .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_455 ) - ); - LUT3 #( - .INIT ( 8'h15 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_F ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ), - .O(N38) - ); - LUT4 #( - .INIT ( 16'h0145 )) - \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_G ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ), - .I3(\U0/I_NO_D.U_ILA/U_STAT/ACT_dstat ), - .O(N39) - ); - LUT4_L #( - .INIT ( 16'h3F50 )) - \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ), - .I1(\U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ), - .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), - .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), - .LO(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1_535 ) - ); - LUT4_L #( - .INIT ( 16'h3120 )) - \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82 ( - .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [8]), - .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]), - .I2(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36_466 ), - .I3(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7_483 ), - .LO(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82_467 ) - ); - RAMB16_S1_S36 #( - .INIT_B ( 36'h000000000 ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 1'h0 ), - .SIM_COLLISION_CHECK ( "ALL" ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .SRVAL_A ( 1'h0 ), - .WRITE_MODE_A ( "WRITE_FIRST" ), - .WRITE_MODE_B ( "WRITE_FIRST" ), - .SRVAL_B ( 36'h000000000 )) - \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i ( - .CLKA(CONTROL[0]), - .CLKB(CLK), - .ENA(CONTROL[6]), - .ENB(N1), - .WEB(\U0/I_NO_D.U_ILA/iCAP_WR_EN ), - .SSRA(N0), - .SSRB(N0), - .WEA(N0), - .DIPB({N0, N0, N0, N0}), - .ADDRA({\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [13], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [12], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [11], -\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [10], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [9], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [8], -\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [7], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [6], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [5], -\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [4], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [3], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [2], -\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [1], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [0]}), - .ADDRB({\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [8], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [7], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [6], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [5] -, \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [4], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [3], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [2], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [1], -\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [0]}), - .DIB({N0, N0, N0, \U0/I_NO_D.U_ILA/iDATA [27], \U0/I_NO_D.U_ILA/iDATA [26], \U0/I_NO_D.U_ILA/iDATA [25], \U0/I_NO_D.U_ILA/iDATA [24], -\U0/I_NO_D.U_ILA/iDATA [23], \U0/I_NO_D.U_ILA/iDATA [22], \U0/I_NO_D.U_ILA/iDATA [21], \U0/I_NO_D.U_ILA/iDATA [20], \U0/I_NO_D.U_ILA/iDATA [19], -\U0/I_NO_D.U_ILA/iDATA [18], \U0/I_NO_D.U_ILA/iDATA [17], \U0/I_NO_D.U_ILA/iDATA [16], \U0/I_NO_D.U_ILA/iDATA [15], \U0/I_NO_D.U_ILA/iDATA [14], -\U0/I_NO_D.U_ILA/iDATA [13], \U0/I_NO_D.U_ILA/iDATA [12], \U0/I_NO_D.U_ILA/iDATA [11], \U0/I_NO_D.U_ILA/iDATA [10], \U0/I_NO_D.U_ILA/iDATA [9], -\U0/I_NO_D.U_ILA/iDATA [8], \U0/I_NO_D.U_ILA/iDATA [7], \U0/I_NO_D.U_ILA/iDATA [6], \U0/I_NO_D.U_ILA/iDATA [5], \U0/I_NO_D.U_ILA/iDATA [4], -\U0/I_NO_D.U_ILA/iDATA [3], \U0/I_NO_D.U_ILA/iDATA [2], \U0/I_NO_D.U_ILA/iDATA [1], \U0/I_NO_D.U_ILA/iDATA [0], \U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT }), - .DOA({\U0/I_NO_D.U_ILA/iDATA_DOUT }), - .DIA({N0}), - .DOB({\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<31>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<30>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<29>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<28>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<27>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<26>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<25>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<24>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<23>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<22>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<21>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<20>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<19>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<18>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<17>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<16>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<15>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<14>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<13>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<12>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<11>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<10>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<9>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<8>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<7>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<6>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<5>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<4>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<3>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<2>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<1>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<0>_UNCONNECTED }), - .DOPB({\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<3>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<2>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<1>_UNCONNECTED , -\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<0>_UNCONNECTED }) - ); - -// synthesis translate_on - -endmodule - -// synthesis translate_off - -`ifndef GLBL -`define GLBL - -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (weak1, weak0) GSR = GSR_int; - assign (weak1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule - -`endif - -// synthesis translate_on diff --git a/fpga/usrp2/extramfifo/ila.xco b/fpga/usrp2/extramfifo/ila.xco deleted file mode 100644 index c8d4d2f75..000000000 --- a/fpga/usrp2/extramfifo/ila.xco +++ /dev/null @@ -1,130 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 12.1 -# Date: Wed Jul 21 18:51:14 2010 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc3s2000 -SET devicefamily = spartan3 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = fg456 -SET removerpms = false -SET simulationfiles = Structural -SET speedgrade = -5 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a -# END Select -# BEGIN Parameters -CSET component_name=ila -CSET counter_width_1=Disabled -CSET counter_width_10=Disabled -CSET counter_width_11=Disabled -CSET counter_width_12=Disabled -CSET counter_width_13=Disabled -CSET counter_width_14=Disabled -CSET counter_width_15=Disabled -CSET counter_width_16=Disabled -CSET counter_width_2=Disabled -CSET counter_width_3=Disabled -CSET counter_width_4=Disabled -CSET counter_width_5=Disabled -CSET counter_width_6=Disabled -CSET counter_width_7=Disabled -CSET counter_width_8=Disabled -CSET counter_width_9=Disabled -CSET data_port_width=0 -CSET data_same_as_trigger=true -CSET enable_storage_qualification=true -CSET enable_trigger_output_port=false -CSET exclude_from_data_storage_1=false -CSET exclude_from_data_storage_10=false -CSET exclude_from_data_storage_11=false -CSET exclude_from_data_storage_12=false -CSET exclude_from_data_storage_13=false -CSET exclude_from_data_storage_14=false -CSET exclude_from_data_storage_15=false -CSET exclude_from_data_storage_16=false -CSET exclude_from_data_storage_2=false -CSET exclude_from_data_storage_3=false -CSET exclude_from_data_storage_4=false -CSET exclude_from_data_storage_5=false -CSET exclude_from_data_storage_6=false -CSET exclude_from_data_storage_7=false -CSET exclude_from_data_storage_8=false -CSET exclude_from_data_storage_9=false -CSET match_type_1=basic -CSET match_type_10=basic -CSET match_type_11=basic -CSET match_type_12=basic -CSET match_type_13=basic -CSET match_type_14=basic -CSET match_type_15=basic -CSET match_type_16=basic -CSET match_type_2=basic -CSET match_type_3=basic -CSET match_type_4=basic -CSET match_type_5=basic -CSET match_type_6=basic -CSET match_type_7=basic -CSET match_type_8=basic -CSET match_type_9=basic -CSET match_units_1=1 -CSET match_units_10=1 -CSET match_units_11=1 -CSET match_units_12=1 -CSET match_units_13=1 -CSET match_units_14=1 -CSET match_units_15=1 -CSET match_units_16=1 -CSET match_units_2=1 -CSET match_units_3=1 -CSET match_units_4=1 -CSET match_units_5=1 -CSET match_units_6=1 -CSET match_units_7=1 -CSET match_units_8=1 -CSET match_units_9=1 -CSET max_sequence_levels=1 -CSET number_of_trigger_ports=4 -CSET sample_data_depth=512 -CSET sample_on=Rising -CSET trigger_port_width_1=8 -CSET trigger_port_width_10=8 -CSET trigger_port_width_11=8 -CSET trigger_port_width_12=8 -CSET trigger_port_width_13=8 -CSET trigger_port_width_14=8 -CSET trigger_port_width_15=8 -CSET trigger_port_width_16=8 -CSET trigger_port_width_2=8 -CSET trigger_port_width_3=8 -CSET trigger_port_width_4=4 -CSET trigger_port_width_5=8 -CSET trigger_port_width_6=8 -CSET trigger_port_width_7=8 -CSET trigger_port_width_8=8 -CSET trigger_port_width_9=8 -CSET use_rpms=true -# END Parameters -GENERATE -# CRC: 66151c7c diff --git a/fpga/usrp2/extramfifo/nobl_fifo.v b/fpga/usrp2/extramfifo/nobl_fifo.v deleted file mode 100644 index 469e3eab5..000000000 --- a/fpga/usrp2/extramfifo/nobl_fifo.v +++ /dev/null @@ -1,114 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// Since this FIFO uses a ZBT/NoBL SRAM for its storage which is a since port -// device it can only sustain data throughput at half the RAM clock rate. -// Fair arbitration to ensure this occurs is included in this logic and -// requests for transactions that can not be completed are held off. -// This FIFO requires a an external signal driving read_strobe that assures space for at least 6 -// reads since this the theopretical maximum number in flight due to pipeling. - -module nobl_fifo - #(parameter WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19) - ( - input clk, - input rst, - input [WIDTH-1:0] RAM_D_pi, - output [WIDTH-1:0] RAM_D_po, - output RAM_D_poe, - output [RAM_DEPTH-1:0] RAM_A, - output RAM_WEn, - output RAM_CENn, - output RAM_LDn, - output RAM_OEn, - output RAM_CE1n, - input [WIDTH-1:0] write_data, - input write_strobe, - output reg space_avail, - output [WIDTH-1:0] read_data, - input read_strobe, // Triggers a read, result in approximately 6 cycles. - output data_avail, // Qulaifys read data available this cycle on read_data. - output reg [FIFO_DEPTH-1:0] capacity - ); - - //reg [FIFO_DEPTH-1:0] capacity; - reg [FIFO_DEPTH-1:0] wr_pointer; - reg [FIFO_DEPTH-1:0] rd_pointer; - wire [RAM_DEPTH-1:0] address; - reg data_avail_int; // Internal not empty flag. - - assign read = read_strobe && data_avail_int; - assign write = write_strobe && space_avail; - - // When a read and write collision occur, supress the space_avail flag next cycle - // and complete write followed by read over 2 cycles. This forces balanced arbitration - // and makes for a simple logic design. - - always @(posedge clk) - if (rst) - begin - capacity <= (1 << FIFO_DEPTH) - 1; - wr_pointer <= 0; - rd_pointer <= 0; - space_avail <= 1; - data_avail_int <= 0; - end - else - begin - // No space available if: - // Capacity is already zero; Capacity is 1 and write is asserted (lookahead); both read and write are asserted (collision) - space_avail <= ~((capacity == 0) || (read&&write) || ((capacity == 1) && write) ); - // Capacity has 1 cycle delay so look ahead here for corner case of read of last item in FIFO. - data_avail_int <= ~((capacity == ((1 << FIFO_DEPTH)-1)) || ((capacity == ((1 << FIFO_DEPTH)-2)) && (~write && read)) ); - wr_pointer <= wr_pointer + write; - rd_pointer <= rd_pointer + (~write && read); - capacity <= capacity - write + (~write && read) ; - end // else: !if(rst) - - assign address = write ? wr_pointer : rd_pointer; - assign enable = write || read; - - - // - // Simple NoBL SRAM interface, 4 cycle read latency. - // Read/Write arbitration via temprary application of empty/full flags. - // - nobl_if #(.WIDTH(WIDTH),.DEPTH(RAM_DEPTH)) - nobl_if_i1 - ( - .clk(clk), - .rst(rst), - .RAM_D_pi(RAM_D_pi), - .RAM_D_po(RAM_D_po), - .RAM_D_poe(RAM_D_poe), - .RAM_A(RAM_A), - .RAM_WEn(RAM_WEn), - .RAM_CENn(RAM_CENn), - .RAM_LDn(RAM_LDn), - .RAM_OEn(RAM_OEn), - .RAM_CE1n(RAM_CE1n), - .address(address), - .data_out(write_data), - .data_in(read_data), - .data_in_valid(data_avail), - .write(write), - .enable(enable) - ); - - - -endmodule // nobl_fifo diff --git a/fpga/usrp2/extramfifo/nobl_if.v b/fpga/usrp2/extramfifo/nobl_if.v deleted file mode 100644 index 0a64d3857..000000000 --- a/fpga/usrp2/extramfifo/nobl_if.v +++ /dev/null @@ -1,165 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// Tested against an IDT 71v65603s150 in simulation and a Cypress 7C1356C in the real world. - -module nobl_if - #(parameter WIDTH=18,DEPTH=19) - ( - input clk, - input rst, - input [WIDTH-1:0] RAM_D_pi, - output [WIDTH-1:0] RAM_D_po, - output reg RAM_D_poe, - output [DEPTH-1:0] RAM_A, - output reg RAM_WEn, - output RAM_CENn, - output RAM_LDn, - output RAM_OEn, - output reg RAM_CE1n, - input [DEPTH-1:0] address, - input [WIDTH-1:0] data_out, - output reg [WIDTH-1:0] data_in, - output reg data_in_valid, - input write, - input enable - ); - - - reg enable_pipe1; - reg [DEPTH-1:0] address_pipe1; - reg write_pipe1; - reg [WIDTH-1:0] data_out_pipe1; - - reg enable_pipe2; - reg write_pipe2; - reg [WIDTH-1:0] data_out_pipe2; - - reg enable_pipe3; - reg write_pipe3; - reg [WIDTH-1:0] data_out_pipe3; - - assign RAM_LDn = 0; - // ZBT/NoBL RAM actually manages its own output enables very well. - assign RAM_OEn = 0; - - // gray code the address to reduce EMI - wire [DEPTH-1:0] address_gray; - - bin2gray #(.WIDTH(DEPTH)) bin2gray (.bin(address),.gray(address_gray)); - - - // - // Pipeline stage 1 - // - always @(posedge clk) - if (rst) - begin - enable_pipe1 <= 0; - address_pipe1 <= 0; - write_pipe1 <= 0; - data_out_pipe1 <= 0; - RAM_WEn <= 1; - RAM_CE1n <= 1; - - end - else - begin - enable_pipe1 <= enable; - RAM_CE1n <= ~enable; // Creates IOB flop - RAM_WEn <= ~write; // Creates IOB flop - - if (enable) - begin - address_pipe1 <= address_gray; - write_pipe1 <= write; -// RAM_WEn <= ~write; // Creates IOB flop - - - if (write) - data_out_pipe1 <= data_out; - end - end // always @ (posedge clk) - - // Pipeline 1 drives address, write_enable, chip_select on NoBL SRAM - assign RAM_A = address_pipe1; - assign RAM_CENn = 1'b0; - // assign RAM_WEn = ~write_pipe1; -// assign RAM_CE1n = ~enable_pipe1; - - // - // Pipeline stage2 - // - always @(posedge clk) - if (rst) - begin - enable_pipe2 <= 0; - data_out_pipe2 <= 0; - write_pipe2 <= 0; - end - else - begin - data_out_pipe2 <= data_out_pipe1; - write_pipe2 <= write_pipe1; - enable_pipe2 <= enable_pipe1; - end - - // - // Pipeline stage3 - // - always @(posedge clk) - if (rst) - begin - enable_pipe3 <= 0; - data_out_pipe3 <= 0; - write_pipe3 <= 0; - RAM_D_poe <= 0; - end - else - begin - data_out_pipe3 <= data_out_pipe2; - write_pipe3 <= write_pipe2; - enable_pipe3 <= enable_pipe2; - RAM_D_poe <= ~(write_pipe2 & enable_pipe2); // Active low driver enable in Xilinx. - end - - // Pipeline 3 drives write data on NoBL SRAM - assign RAM_D_po = data_out_pipe3; - - - // - // Pipeline stage4 - // - always @(posedge clk) - if (rst) - begin - data_in_valid <= 0; - data_in <= 0; - end - else - begin - data_in <= RAM_D_pi; - if (enable_pipe3 & ~write_pipe3) - begin - // Read data now available to be registered. - data_in_valid <= 1'b1; - end - else - data_in_valid <= 1'b0; - end // always @ (posedge clk) - -endmodule // nobl_if diff --git a/fpga/usrp2/extramfifo/refill_randomizer.v b/fpga/usrp2/extramfifo/refill_randomizer.v deleted file mode 100644 index 09728b8c0..000000000 --- a/fpga/usrp2/extramfifo/refill_randomizer.v +++ /dev/null @@ -1,83 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// -// EMI mitigation. -// Process FULL flag from FIFO so that de-assertion -// (FIFO now not FULL) is delayed by a pseudo random -// value, but assertion is passed straight through. -// - - -module refill_randomizer - #(parameter BITS=7) - ( - input clk, - input rst, - input full_in, - output full_out - ); - - wire feedback; - reg full_last; - wire full_deasserts; - reg [6:0] shift_reg; - reg [6:0] count; - reg delayed_fall; - - - always @(posedge clk) - full_last <= full_in; - - assign full_deasserts = full_last & ~full_in; - - // 7 bit LFSR - always @(posedge clk) - if (rst) - shift_reg <= 7'b1; - else - if (full_deasserts) - shift_reg <= {shift_reg[5:0],feedback}; - - assign feedback = ^(shift_reg & 7'h41); - - always @(posedge clk) - if (rst) - begin - count <= 1; - delayed_fall <= 1; - end - else if (full_deasserts) - begin - count <= shift_reg; - delayed_fall <= 1; - end - else if (count == 1) - begin - count <= 1; - delayed_fall <= 0; - end - else - begin - count <= count - 1; - delayed_fall <= 1; - end - - // Full_out goes instantly high if full_in does. However its fall is delayed. - assign full_out = (full_in == 1) || (full_last == 1) || delayed_fall; - -endmodule \ No newline at end of file diff --git a/fpga/usrp2/extramfifo/test_sram_if.v b/fpga/usrp2/extramfifo/test_sram_if.v deleted file mode 100644 index dcb881a92..000000000 --- a/fpga/usrp2/extramfifo/test_sram_if.v +++ /dev/null @@ -1,192 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// Instantiate this block at the core level to conduct closed -// loop testing of the AC performance of the USRP2 SRAM interface - - -`define WIDTH 18 -`define DEPTH 19 - -module test_sram_if - ( - input clk, - input rst, - input [`WIDTH-1:0] RAM_D_pi, - output [`WIDTH-1:0] RAM_D_po, - output RAM_D_poe, - output [`DEPTH-1:0] RAM_A, - output RAM_WEn, - output RAM_CENn, - output RAM_LDn, - output RAM_OEn, - output RAM_CE1n, - output reg correct - ); - - reg [`DEPTH-1:0] write_count; - reg [`DEPTH-1:0] read_count; - reg enable; - reg write; - reg write_cycle; - reg read_cycle; - reg enable_reads; - reg [18:0] address; - reg [17:0] data_out; - wire [17:0] data_in; - wire data_in_valid; - - reg [17:0] check_data; - reg [17:0] check_data_old; - reg [17:0] check_data_old2; - - // - // Create counter that generates both external modulo 2^19 address and modulo 2^18 data to test RAM. - // - - always @(posedge clk) - if (rst) - begin - write_count <= 19'h0; - read_count <= 19'h0; - end - else if (write_cycle) // Write cycle - if (write_count == 19'h7FFFF) - begin - write_count <= 19'h0; - end - else - begin - write_count <= write_count + 1'b1; - end - else if (read_cycle) // Read cycle - if (read_count == 19'h7FFFF) - begin - read_count <= 19'h0; - end - else - begin - read_count <= read_count + 1'b1; - end - - always @(posedge clk) - if (rst) - begin - enable_reads <= 0; - read_cycle <= 0; - write_cycle <= 0; - end - else - begin - write_cycle <= ~write_cycle; - if (enable_reads) - read_cycle <= write_cycle; - if (write_count == 15) // Enable reads 15 writes after reset terminates. - enable_reads <= 1; - end // else: !if(rst) - - always @(posedge clk) - if (rst) - begin - enable <= 0; - end - else if (write_cycle) - begin - address <= write_count; - data_out <= write_count[17:0]; - enable <= 1; - write <= 1; - end - else if (read_cycle) - begin - address <= read_count; - check_data <= read_count[17:0]; - check_data_old <= check_data; - check_data_old2 <= check_data_old; - enable <= 1; - write <= 0; - end - else - enable <= 0; - - always @(posedge clk) - if (data_in_valid) - begin - correct <= (data_in == check_data_old2); - end - - - nobl_if nobl_if_i1 - ( - .clk(clk), - .rst(rst), - .RAM_D_pi(RAM_D_pi), - .RAM_D_po(RAM_D_po), - .RAM_D_poe(RAM_D_poe), - .RAM_A(RAM_A), - .RAM_WEn(RAM_WEn), - .RAM_CENn(RAM_CENn), - .RAM_LDn(RAM_LDn), - .RAM_OEn(RAM_OEn), - .RAM_CE1n(RAM_CE1n), - .address(address), - .data_out(data_out), - .data_in(data_in), - .data_in_valid(data_in_valid), - .write(write), - .enable(enable) - ); - - - wire [35:0] CONTROL0; - reg [7:0] data_in_reg, data_out_reg, address_reg; - reg data_in_valid_reg,write_reg,enable_reg,correct_reg; - - always @(posedge clk) - begin - data_in_reg <= data_in[7:0]; - data_out_reg <= data_out[7:0]; - data_in_valid_reg <= data_in_valid; - write_reg <= write; - enable_reg <= enable; - correct_reg <= correct; - address_reg <= address; - - end - - - icon icon_i1 - ( - .CONTROL0(CONTROL0) - ); - - ila ila_i1 - ( - .CLK(clk), - .CONTROL(CONTROL0), - // .TRIG0(address_reg), - .TRIG0(data_in_reg[7:0]), - .TRIG1(data_out_reg[7:0]), - .TRIG2(address_reg[7:0]), - .TRIG3({data_in_valid_reg,write_reg,enable_reg,correct_reg}) - ); - - - -endmodule // test_sram_if - - \ No newline at end of file diff --git a/fpga/usrp2/fifo/.gitignore b/fpga/usrp2/fifo/.gitignore deleted file mode 100644 index 866f1faad..000000000 --- a/fpga/usrp2/fifo/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -*.vcd -*.lxt -a.out diff --git a/fpga/usrp2/fifo/Makefile.srcs b/fpga/usrp2/fifo/Makefile.srcs deleted file mode 100644 index 55ba0be2a..000000000 --- a/fpga/usrp2/fifo/Makefile.srcs +++ /dev/null @@ -1,42 +0,0 @@ -# -# Copyright 2010-2012 Ettus Research LLC -# - -################################################## -# FIFO Sources -################################################## -FIFO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../fifo/, \ -add_routing_header.v \ -buffer_int.v \ -buffer_int2.v \ -buffer_pool.v \ -crossbar36.v \ -dsp_framer36.v \ -fifo_2clock.v \ -fifo_2clock_cascade.v \ -ll8_shortfifo.v \ -fifo_short.v \ -fifo_long.v \ -fifo_cascade.v \ -fifo36_to_ll8.v \ -ll8_to_fifo36.v \ -fifo19_to_ll8.v \ -ll8_to_fifo19.v \ -fifo36_to_fifo19.v \ -fifo19_to_fifo36.v \ -fifo19_mux.v \ -fifo36_mux.v \ -fifo36_demux.v \ -packet_router.v \ -splitter36.v \ -valve36.v \ -fifo_pacer.v \ -packet_dispatcher36_x3.v \ -packet_dispatcher36_x4.v \ -packet_generator32.v \ -packet_generator.v \ -packet_verifier32.v \ -packet_verifier.v \ -fifo19_pad.v \ -packet_padder36.v \ -)) diff --git a/fpga/usrp2/fifo/add_routing_header.v b/fpga/usrp2/fifo/add_routing_header.v deleted file mode 100644 index ee6a635f5..000000000 --- a/fpga/usrp2/fifo/add_routing_header.v +++ /dev/null @@ -1,47 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module add_routing_header - #(parameter PORT_SEL = 0, - parameter PROT_ENG_FLAGS = 1) - (input clk, input reset, input clear, - input [35:0] data_i, input src_rdy_i, output dst_rdy_o, - output [35:0] data_o, output src_rdy_o, input dst_rdy_i); - - reg [1:0] line; - wire [1:0] port_sel_bits = PORT_SEL; - wire [15:0] len = data_i[15:0]; - - always @(posedge clk) - if(reset) - line <= PROT_ENG_FLAGS ? 0 : 1; - else - if(src_rdy_o & dst_rdy_i) - if(data_o[33]) - line <= PROT_ENG_FLAGS ? 0 : 1; - else - if(line != 3) - line <= line + 1; - - assign data_o = (line == 0) ? {4'b0001, 13'b0, port_sel_bits, 1'b1, len[13:0],2'b00} : - (line == 1) ? {3'b000, (PROT_ENG_FLAGS ? 1'b0: 1'b1), data_i[31:0]} : - data_i[35:0]; - - assign dst_rdy_o = dst_rdy_i & (line != 0); - assign src_rdy_o = src_rdy_i; - -endmodule // add_routing_header diff --git a/fpga/usrp2/fifo/buffer_int.v b/fpga/usrp2/fifo/buffer_int.v deleted file mode 100644 index c068226ec..000000000 --- a/fpga/usrp2/fifo/buffer_int.v +++ /dev/null @@ -1,184 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// FIFO Interface to the 2K buffer RAMs -// Read port is read-acknowledge -// FIXME do we want to be able to interleave reads and writes? - -module buffer_int - #(parameter BUF_NUM = 0, - parameter BUF_SIZE = 9) - (// Control Interface - input clk, - input rst, - input [31:0] ctrl_word, - input go, - output done, - output error, - output idle, - - // Buffer Interface - output en_o, - output we_o, - output reg [BUF_SIZE-1:0] addr_o, - output [31:0] dat_to_buf, - input [31:0] dat_from_buf, - - // Write FIFO Interface - input [31:0] wr_data_i, - input [3:0] wr_flags_i, - input wr_ready_i, - output wr_ready_o, - - // Read FIFO Interface - output [31:0] rd_data_o, - output [3:0] rd_flags_o, - output rd_ready_o, - input rd_ready_i - ); - - reg [31:0] ctrl_reg; - reg go_reg; - - always @(posedge clk) - go_reg <= go; - - always @(posedge clk) - if(rst) - ctrl_reg <= 0; - else - if(go & (ctrl_word[31:28] == BUF_NUM)) - ctrl_reg <= ctrl_word; - - wire [BUF_SIZE-1:0] firstline = ctrl_reg[BUF_SIZE-1:0]; - wire [BUF_SIZE-1:0] lastline = ctrl_reg[2*BUF_SIZE-1:BUF_SIZE]; - - wire read = ctrl_reg[22]; - wire write = ctrl_reg[23]; - wire clear = ctrl_reg[24]; - //wire [2:0] port = ctrl_reg[27:25]; // Ignored in this block - //wire [3:0] buff_num = ctrl_reg[31:28]; // Ignored here ? - - localparam IDLE = 3'd0; - localparam PRE_READ = 3'd1; - localparam READING = 3'd2; - localparam WRITING = 3'd3; - localparam ERROR = 3'd4; - localparam DONE = 3'd5; - - reg [2:0] state; - reg rd_sop, rd_eop; - wire wr_sop, wr_eop, wr_error; - reg [1:0] rd_occ; - wire [1:0] wr_occ; - - always @(posedge clk) - if(rst) - begin - state <= IDLE; - rd_sop <= 0; - rd_eop <= 0; - rd_occ <= 0; - end - else - if(clear) - begin - state <= IDLE; - rd_sop <= 0; - rd_eop <= 0; - rd_occ <= 0; - end - else - case(state) - IDLE : - if(go_reg & read) - begin - addr_o <= firstline; - state <= PRE_READ; - end - else if(go_reg & write) - begin - addr_o <= firstline; - state <= WRITING; - end - - PRE_READ : - begin - state <= READING; - addr_o <= addr_o + 1; - rd_occ <= 2'b00; - rd_sop <= 1; - rd_eop <= 0; - end - - READING : - if(rd_ready_i) - begin - rd_sop <= 0; - addr_o <= addr_o + 1; - if(addr_o == lastline) - begin - rd_eop <= 1; - // FIXME assign occ here - rd_occ <= 0; - end - else - rd_eop <= 0; - if(rd_eop) - state <= DONE; - end - - WRITING : - begin - if(wr_ready_i) - begin - addr_o <= addr_o + 1; - if(wr_error) - begin - state <= ERROR; - // Save OCC flags here - end - else if((addr_o == lastline)||wr_eop) - state <= DONE; - end // if (wr_ready_i) - end // case: WRITING - - endcase // case(state) - - assign dat_to_buf = wr_data_i; - assign rd_data_o = dat_from_buf; - - assign rd_flags_o = { rd_occ[1:0], rd_eop, rd_sop }; - assign rd_ready_o = (state == READING); - - assign wr_sop = wr_flags_i[0]; - assign wr_eop = wr_flags_i[1]; - assign wr_occ = wr_flags_i[3:2]; - assign wr_error = wr_sop & wr_eop; - assign wr_ready_o = (state == WRITING); - - assign we_o = (state == WRITING); - //assign we_o = (state == WRITING) && wr_ready_i; // always write to avoid timing issue - - assign en_o = ~((state==READING)& ~rd_ready_i); // FIXME potential critical path - - assign done = (state == DONE); - assign error = (state == ERROR); - assign idle = (state == IDLE); - -endmodule // buffer_int diff --git a/fpga/usrp2/fifo/buffer_int2.v b/fpga/usrp2/fifo/buffer_int2.v deleted file mode 100644 index 7dd528dd5..000000000 --- a/fpga/usrp2/fifo/buffer_int2.v +++ /dev/null @@ -1,194 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// FIFO Interface to the 2K buffer RAMs -// Read port is read-acknowledge -// FIXME do we want to be able to interleave reads and writes? - -module buffer_int2 - #(parameter BASE = 0, - parameter BUF_SIZE = 9) - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - output [31:0] status, - - // Wishbone interface to RAM - input wb_clk_i, - input wb_rst_i, - input wb_we_i, - input wb_stb_i, - input [15:0] wb_adr_i, - input [31:0] wb_dat_i, - output [31:0] wb_dat_o, - output reg wb_ack_o, - - // Write FIFO Interface - input [35:0] wr_data_i, - input wr_ready_i, - output wr_ready_o, - - // Read FIFO Interface - output [35:0] rd_data_o, - output rd_ready_o, - input rd_ready_i - ); - - reg [15:0] rd_addr, wr_addr; // Handle pkt bigger than buffer - wire [15:0] rd_addr_next = rd_addr + 1; - reg [15:0] rd_length; - - wire [31:0] ctrl; - wire wr_done, wr_error, wr_idle; - wire rd_done, rd_error, rd_idle; - wire we, en, go; - - wire read = ctrl[3]; - wire rd_clear = ctrl[2]; - wire write = ctrl[1]; - wire wr_clear = ctrl[0]; - - reg [2:0] rd_state, wr_state; - reg rd_sop, rd_eop; - wire wr_sop, wr_eop; - reg [1:0] rd_occ; - wire [1:0] wr_occ; - - localparam IDLE = 3'd0; - localparam PRE_READ = 3'd1; - localparam READING = 3'd2; - localparam WRITING = 3'd3; - localparam ERROR = 3'd4; - localparam DONE = 3'd5; - - // read state machine - always @(posedge clk) - if(rst | (rd_clear & go)) - begin - rd_state <= IDLE; - rd_sop <= 0; - rd_eop <= 0; - rd_occ <= 0; - end - else - case(rd_state) - IDLE : - if(go & read) - begin - rd_addr <= 0; - rd_state <= PRE_READ; - rd_length <= ctrl[31:16]; - end - - PRE_READ : - begin - rd_state <= READING; - rd_addr <= rd_addr_next; - rd_occ <= 2'b00; - rd_sop <= 1; - rd_eop <= 0; - end - - READING : - if(rd_ready_i) - begin - rd_sop <= 0; - rd_addr <= rd_addr_next; - if(rd_addr_next == rd_length) - begin - rd_eop <= 1; - // FIXME assign occ here - rd_occ <= 0; - end - else - rd_eop <= 0; - if(rd_eop) - rd_state <= DONE; - end - - endcase // case(rd_state) - - // write state machine - always @(posedge clk) - if(rst | (wr_clear & go)) - wr_state <= IDLE; - else - case(wr_state) - IDLE : - if(go & write) - begin - wr_addr <= 0; - wr_state <= WRITING; - end - - WRITING : - if(wr_ready_i) - begin - wr_addr <= wr_addr + 1; - if(wr_sop & wr_eop) - wr_state <= ERROR; // Should save OCC flags here - else if(wr_eop) - wr_state <= DONE; - end // if (wr_ready_i) - endcase // case(wr_state) - - assign rd_data_o[35:32] = { rd_occ[1:0], rd_eop, rd_sop }; - assign rd_ready_o = (rd_state == READING); - - assign wr_sop = wr_data_i[32]; - assign wr_eop = wr_data_i[33]; - assign wr_occ = wr_data_i[35:34]; - assign wr_ready_o = (wr_state == WRITING); - - assign we = (wr_state == WRITING); // always write to avoid timing issue - assign en = ~((rd_state==READING)& ~rd_ready_i); // FIXME potential critical path - - assign rd_done = (rd_state == DONE); - assign wr_done = (wr_state == DONE); - assign rd_error = (rd_state == ERROR); - assign wr_error = (wr_state == ERROR); - assign rd_idle = (rd_state == IDLE); - assign wr_idle = (wr_state == IDLE); - - wire [BUF_SIZE-1:0] wr_addr_clip = (|wr_addr[15:BUF_SIZE]) ? {BUF_SIZE{1'b1}} : wr_addr[BUF_SIZE-1:0]; - - ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer_in // CPU reads here - (.clka(wb_clk_i),.ena(wb_stb_i),.wea(1'b0), - .addra(wb_adr_i[BUF_SIZE+1:2]),.dia(0),.doa(wb_dat_o), - .clkb(clk),.enb(1'b1),.web(we), - .addrb(wr_addr_clip),.dib(wr_data_i[31:0]),.dob()); - - ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer_out // CPU writes here - (.clka(wb_clk_i),.ena(wb_stb_i),.wea(wb_we_i), - .addra(wb_adr_i[BUF_SIZE+1:2]),.dia(wb_dat_i),.doa(), - .clkb(clk),.enb(en),.web(1'b0), - .addrb(rd_addr[BUF_SIZE-1:0]),.dib(0),.dob(rd_data_o[31:0])); - - always @(posedge wb_clk_i) - if(wb_rst_i) - wb_ack_o <= 0; - else - wb_ack_o <= wb_stb_i & ~wb_ack_o; - - setting_reg #(.my_addr(BASE)) - sreg(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),.in(set_data), - .out(ctrl),.changed(go)); - - assign status = { wr_addr, - 8'b0,1'b0,rd_idle,rd_error,rd_done, 1'b0,wr_idle,wr_error,wr_done}; - -endmodule // buffer_int2 diff --git a/fpga/usrp2/fifo/buffer_int_tb.v b/fpga/usrp2/fifo/buffer_int_tb.v deleted file mode 100644 index 44f8be0a0..000000000 --- a/fpga/usrp2/fifo/buffer_int_tb.v +++ /dev/null @@ -1,435 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module buffer_int_tb (); - - reg clk = 0; - reg rst = 1; - - initial #100 rst = 0; - always #5 clk = ~clk; - - wire en, we; - wire [8:0] addr; - wire [31:0] fifo2buf, buf2fifo; - - wire [31:0] rd_data_o; - wire [3:0] rd_flags_o; - wire rd_sop_o, rd_eop_o; - reg rd_error_i = 0, rd_read_i = 0; - - reg [31:0] wr_data_i = 0; - wire [3:0] wr_flags_i; - reg wr_eop_i = 0, wr_sop_i = 0; - reg wr_write_i = 0; - wire wr_ready_o, wr_full_o; - - reg clear = 0, write = 0, read = 0; - reg [8:0] firstline = 0, lastline = 0; - wire [3:0] step = 1; - wire [31:0] ctrl_word = {4'b0,3'b0,clear,write,read,step,lastline,firstline}; - reg go = 0; - wire done, error; - - assign wr_flags_i = {2'b00, wr_eop_i, wr_sop_i}; - assign rd_sop_o = rd_flags_o[0]; - assign rd_eop_o = rd_flags_o[1]; - - buffer_int buffer_int - (.clk(clk),.rst(rst), - .ctrl_word(ctrl_word),.go(go), - .done(done),.error(error), - - // Buffer Interface - .en_o(en),.we_o(we),.addr_o(addr), - .dat_to_buf(fifo2buf),.dat_from_buf(buf2fifo), - - // Write FIFO Interface - .wr_data_i(wr_data_i), .wr_flags_i(wr_flags_i), .wr_write_i(wr_write_i), .wr_ready_o(wr_ready_o), - - // Read FIFO Interface - .rd_data_o(rd_data_o), .rd_flags_o(rd_flags_o), .rd_ready_o(rd_ready_o), .rd_read_i(rd_read_i) - ); - - reg ram_en = 0, ram_we = 0; - reg [8:0] ram_addr = 0; - reg [31:0] ram_data = 0; - - ram_2port #(.DWIDTH(32),.AWIDTH(9)) ram_2port - (.clka(clk), .ena(ram_en), .wea(ram_we), .addra(ram_addr), .dia(ram_data), .doa(), - .clkb(clk), .enb(en), .web(we), .addrb(addr), .dib(fifo2buf), .dob(buf2fifo) ); - - initial - begin - @(negedge rst); - @(posedge clk); - FillRAM; - - ResetBuffer; - SetBufferRead(5,10); - $display("Testing full read, no wait states."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(6,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(5,10); - $display("Testing full read, 2 wait states."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(6,2); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(5,10); - $display("Testing partial read, 0 wait states, then nothing after last."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(3,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(5,10); - $display("Testing partial read, 0 wait states, then done at same time as last."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(2,0); - ReadALine; - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(5,10); - $display("Testing partial read, 3 wait states, then error at same time as last."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(2,3); - rd_error_i <= 1; - ReadALine; - rd_error_i <= 0; - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(500,511); - $display("Testing full read, to the end of the buffer."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(12,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(0,511); - $display("Testing full read, start to end of the buffer."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(512,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(505,3); - $display("Testing full read, wraparound"); - while(!rd_sop_o) - @(posedge clk); - ReadLines(11,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(10,15); - $display("Testing Full Write, no wait states"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(6,0,72); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(18,23); - $display("Testing Full Write, 1 wait states"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(6,1,101); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(27,40); - $display("Testing Partial Write, 0 wait states"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(6,0,201); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(45,200); - $display("Testing Partial Write, 0 wait states, then done and write simultaneously"); - while(!wr_ready_o) - @(posedge clk); - wr_sop_i <= 1; wr_eop_i <= 0; - WriteLines(6,0,301); - wr_sop_i <= 0; wr_eop_i <= 1; - WriteALine(400); - wr_sop_i <= 0; wr_eop_i <= 0; - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(55,200); - $display("Testing Partial Write, 0 wait states, then error"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(6,0,501); - wr_sop_i <= 1; wr_eop_i <= 1; - WriteALine(400); - @(posedge clk); - repeat (10) - @(posedge clk); - wr_sop_i <= 0; wr_eop_i <= 0; - - ResetBuffer; - SetBufferRead(0,82); - $display("Testing read after all the writes"); - while(!rd_sop_o) - @(posedge clk); - ReadLines(83,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(508,4); - $display("Testing wraparound write"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(9,0,601); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(506,10); - $display("Reading wraparound write"); - while(!rd_sop_o) - @(posedge clk); - ReadLines(17,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(0,511); - $display("Testing Whole Buffer write"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(512,0,1000); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(0,511); - $display("Reading Whole Buffer write"); - while(!rd_sop_o) - @(posedge clk); - ReadLines(512,0); - repeat (10) - @(posedge clk); - - /* - ResetBuffer; - SetBufferWrite(5,10); - $display("Testing Write Too Many"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(12,0,2000); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(0,15); - $display("Reading back Write Too Many"); - while(!rd_sop_o) - @(posedge clk); - ReadLines(16,0); - repeat (10) - @(posedge clk); - */ - ResetBuffer; - SetBufferWrite(15,20); - $display("Testing Write One Less Than Full"); - while(!wr_ready_o) - @(posedge clk); - wr_sop_i <= 1; wr_eop_i <= 0; - WriteALine(400); - wr_sop_i <= 0; wr_eop_i <= 0; - WriteLines(3,0,2000); - wr_sop_i <= 0; wr_eop_i <= 1; - WriteALine(400); - wr_sop_i <= 0; wr_eop_i <= 0; - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(13,22); - $display("Reading back Write One Less Than Full"); - while(!rd_sop_o) - @(posedge clk); - ReadLines(10,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - repeat(100) - @(posedge clk); - $finish; - end - - always @(posedge clk) - if(rd_read_i == 1'd1) - $display("READ Buffer %d, rd_sop_o %d, rd_eop_o %d", rd_data_o, rd_sop_o, rd_eop_o); - - always @(posedge clk) - if(wr_write_i == 1'd1) - $display("WRITE Buffer %d, wr_ready_o %d, wr_full_o %d", wr_data_i, wr_ready_o, wr_full_o); - - initial begin - $dumpfile("buffer_int_tb.lxt"); - $dumpvars(0,buffer_int_tb); - end - - task FillRAM; - begin - ram_addr <= 0; - ram_data <= 0; - @(posedge clk); - ram_en <= 1; - ram_we <= 1; - @(posedge clk); - repeat (511) - begin - ram_addr <= ram_addr + 1; - ram_data <= ram_data + 1; - ram_en <= 1; - ram_we <= 1; - @(posedge clk); - end - ram_en <= 0; - ram_we <= 0; - @(posedge clk); - $display("Filled the RAM"); - end - endtask // FillRAM - - task ResetBuffer; - begin - clear <= 1; read <= 0; write <= 0; - go <= 1; - @(posedge clk); - go <= 0; - @(posedge clk); - $display("Buffer Reset"); - end - endtask // ClearBuffer - - task SetBufferWrite; - input [8:0] start; - input [8:0] stop; - begin - clear <= 0; read <= 0; write <= 1; - firstline <= start; - lastline <= stop; - go <= 1; - @(posedge clk); - go <= 0; - @(posedge clk); - $display("Buffer Set for Write"); - end - endtask // SetBufferWrite - - task SetBufferRead; - input [8:0] start; - input [8:0] stop; - begin - clear <= 0; read <= 1; write <= 0; - firstline <= start; - lastline <= stop; - go <= 1; - @(posedge clk); - go <= 0; - @(posedge clk); - $display("Buffer Set for Read"); - end - endtask // SetBufferRead - - task ReadALine; - begin - while(~rd_ready_o) - @(posedge clk); - #1 rd_read_i <= 1; - @(posedge clk); - rd_read_i <= 0; - end - endtask // ReadALine - - task ReadLines; - input [9:0] lines; - input [7:0] wait_states; - begin - $display("Read Lines: Number %d, Wait States %d",lines,wait_states); - repeat (lines) - begin - ReadALine; - repeat (wait_states) - @(posedge clk); - end - end - endtask // ReadLines - - task WriteALine; - input [31:0] value; - begin - while(~wr_ready_o) - @(posedge clk); - #1 wr_write_i <= 1; - wr_data_i <= value; - @(posedge clk); - wr_write_i <= 0; - end - endtask // WriteALine - - task WriteLines; - input [9:0] lines; - input [7:0] wait_states; - input [31:0] value; - begin - $display("Write Lines: Number %d, Wait States %d",lines,wait_states); - repeat(lines) - begin - value <= value + 1; - WriteALine(value); - repeat(wait_states) - @(posedge clk); - end - end - endtask // WriteLines - -endmodule // buffer_int_tb diff --git a/fpga/usrp2/fifo/buffer_pool.v b/fpga/usrp2/fifo/buffer_pool.v deleted file mode 100644 index 48f5bd69c..000000000 --- a/fpga/usrp2/fifo/buffer_pool.v +++ /dev/null @@ -1,300 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Buffer pool. Contains 8 buffers, each 2K (512 by 32). Each buffer -// is a dual-ported RAM. Port A on each of them is indirectly connected -// to the wishbone bus by a bridge. Port B may be connected any one of the -// 8 (4 rd, 4 wr) FIFO-like streaming interaces, or disconnected. The wishbone bus -// provides access to all 8 buffers, and also controls the connections -// between the ports and the buffers, allocating them as needed. - -// wb_adr is 16 bits -- -// bits 13:11 select which buffer -// bits 10:2 select line in buffer -// bits 1:0 are unused (32-bit access only) - -// BUF_SIZE is in address lines (i.e. log2 of number of lines). -// For S3 it should be 9 (512 words, 2KB) -// For V5 it should be at least 10 (1024 words, 4KB) or 11 (2048 words, 8KB) - -module buffer_pool - #(parameter BUF_SIZE = 9, - parameter SET_ADDR = 64) - (input wb_clk_i, - input wb_rst_i, - input wb_we_i, - input wb_stb_i, - input [15:0] wb_adr_i, - input [31:0] wb_dat_i, - output [31:0] wb_dat_o, - output reg wb_ack_o, - output wb_err_o, - output wb_rty_o, - - input stream_clk, - input stream_rst, - - input set_stb, input [7:0] set_addr, input [31:0] set_data, - output [31:0] status, - output sys_int_o, - - output [31:0] s0, output [31:0] s1, output [31:0] s2, output [31:0] s3, - output [31:0] s4, output [31:0] s5, output [31:0] s6, output [31:0] s7, - - // Write Interfaces - input [31:0] wr0_data_i, input [3:0] wr0_flags_i, input wr0_ready_i, output wr0_ready_o, - input [31:0] wr1_data_i, input [3:0] wr1_flags_i, input wr1_ready_i, output wr1_ready_o, - input [31:0] wr2_data_i, input [3:0] wr2_flags_i, input wr2_ready_i, output wr2_ready_o, - input [31:0] wr3_data_i, input [3:0] wr3_flags_i, input wr3_ready_i, output wr3_ready_o, - - // Read Interfaces - output [31:0] rd0_data_o, output [3:0] rd0_flags_o, output rd0_ready_o, input rd0_ready_i, - output [31:0] rd1_data_o, output [3:0] rd1_flags_o, output rd1_ready_o, input rd1_ready_i, - output [31:0] rd2_data_o, output [3:0] rd2_flags_o, output rd2_ready_o, input rd2_ready_i, - output [31:0] rd3_data_o, output [3:0] rd3_flags_o, output rd3_ready_o, input rd3_ready_i - ); - - wire [7:0] sel_a; - - wire [BUF_SIZE-1:0] buf_addra = wb_adr_i[BUF_SIZE+1:2]; // ignore address 1:0, 32-bit access only - wire [2:0] which_buf = wb_adr_i[BUF_SIZE+4:BUF_SIZE+2]; // address 15:14 selects the buffer pool - - decoder_3_8 dec(.sel(which_buf),.res(sel_a)); - - genvar i; - - wire go; - - reg [2:0] port[0:7]; - reg [3:0] read_src[0:3]; - reg [3:0] write_src[0:3]; - - wire [7:0] done; - wire [7:0] error; - wire [7:0] idle; - - wire [31:0] buf_doa[0:7]; - - wire [7:0] buf_enb; - wire [7:0] buf_web; - wire [BUF_SIZE-1:0] buf_addrb[0:7]; - wire [31:0] buf_dib[0:7]; - wire [31:0] buf_dob[0:7]; - - wire [31:0] wr_data_i[0:7]; - wire [3:0] wr_flags_i[0:7]; - wire [7:0] wr_ready_i; - wire [7:0] wr_ready_o; - - wire [31:0] rd_data_o[0:7]; - wire [3:0] rd_flags_o[0:7]; - wire [7:0] rd_ready_o; - wire [7:0] rd_ready_i; - - assign status = {8'd0,idle[7:0],error[7:0],done[7:0]}; - - assign s0 = buf_addrb[0]; - assign s1 = buf_addrb[1]; - assign s2 = buf_addrb[2]; - assign s3 = buf_addrb[3]; - assign s4 = buf_addrb[4]; - assign s5 = buf_addrb[5]; - assign s6 = buf_addrb[6]; - assign s7 = buf_addrb[7]; - - wire [31:0] fifo_ctrl; - setting_reg #(.my_addr(SET_ADDR)) - sreg(.clk(stream_clk),.rst(stream_rst),.strobe(set_stb),.addr(set_addr),.in(set_data), - .out(fifo_ctrl),.changed(go)); - - integer k; - always @(posedge stream_clk) - if(stream_rst) - for(k=0;k<8;k=k+1) - port[k] <= 4; // disabled - else - for(k=0;k<8;k=k+1) - if(go & (fifo_ctrl[31:28]==k)) - port[k] <= fifo_ctrl[27:25]; - - always @(posedge stream_clk) - if(stream_rst) - for(k=0;k<4;k=k+1) - read_src[k] <= 8; // disabled - else - for(k=0;k<4;k=k+1) - if(go & fifo_ctrl[22] & (fifo_ctrl[27:25]==k)) - read_src[k] <= fifo_ctrl[31:28]; - - always @(posedge stream_clk) - if(stream_rst) - for(k=0;k<4;k=k+1) - write_src[k] <= 8; // disabled - else - for(k=0;k<4;k=k+1) - if(go & fifo_ctrl[23] & (fifo_ctrl[27:25]==k)) - write_src[k] <= fifo_ctrl[31:28]; - - generate - for(i=0;i<8;i=i+1) - begin : gen_buffer - RAMB16_S36_S36 dpram - (.DOA(buf_doa[i]),.ADDRA(buf_addra),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0), - .ENA(wb_stb_i & sel_a[i]),.SSRA(0),.WEA(wb_we_i), - .DOB(buf_dob[i]),.ADDRB(buf_addrb[i]),.CLKB(stream_clk),.DIB(buf_dib[i]),.DIPB(4'h0), - .ENB(buf_enb[i]),.SSRB(0),.WEB(buf_web[i]) ); - -/* - ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer - (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[i]),.wea(wb_we_i), - .addra(buf_addra),.dia(wb_dat_i),.doa(buf_doa[i]), - .clkb(stream_clk),.enb(buf_enb[i]),.web(buf_web[i]), - .addrb(buf_addrb[i]),.dib(buf_dib[i]),.dob(buf_dob[i])); - - */ - - buffer_int #(.BUF_NUM(i),.BUF_SIZE(BUF_SIZE)) buffer_int - (.clk(stream_clk),.rst(stream_rst), - .ctrl_word(fifo_ctrl),.go(go & (fifo_ctrl[31:28]==i)), - .done(done[i]),.error(error[i]),.idle(idle[i]), - .en_o(buf_enb[i]), - .we_o(buf_web[i]), - .addr_o(buf_addrb[i]), - .dat_to_buf(buf_dib[i]), - .dat_from_buf(buf_dob[i]), - .wr_data_i(wr_data_i[i]), - .wr_flags_i(wr_flags_i[i]), - .wr_ready_i(wr_ready_i[i]), - .wr_ready_o(wr_ready_o[i]), - .rd_data_o(rd_data_o[i]), - .rd_flags_o(rd_flags_o[i]), - .rd_ready_o(rd_ready_o[i]), - .rd_ready_i(rd_ready_i[i]) ); - mux4 #(.WIDTH(37)) - mux4_wr (.en(~port[i][2]),.sel(port[i][1:0]), - .i0({wr0_data_i,wr0_flags_i,wr0_ready_i}), - .i1({wr1_data_i,wr1_flags_i,wr1_ready_i}), - .i2({wr2_data_i,wr2_flags_i,wr2_ready_i}), - .i3({wr3_data_i,wr3_flags_i,wr3_ready_i}), - .o({wr_data_i[i],wr_flags_i[i],wr_ready_i[i]}) ); - mux4 #(.WIDTH(1)) - mux4_rd (.en(~port[i][2]),.sel(port[i][1:0]), - .i0(rd0_ready_i),.i1(rd1_ready_i),.i2(rd2_ready_i),.i3(rd3_ready_i), - .o(rd_ready_i[i])); - end // block: gen_buffer - endgenerate - - //---------------------------------------------------------------------- - // Wishbone Outputs - - // Use the following lines if ram output and mux can be made fast enough - - assign wb_err_o = 1'b0; // Unused for now - assign wb_rty_o = 1'b0; // Unused for now - - always @(posedge wb_clk_i) - wb_ack_o <= wb_stb_i & ~wb_ack_o; - assign wb_dat_o = buf_doa[which_buf]; - - // Use this if we can't make the RAM+MUX fast enough - // reg [31:0] wb_dat_o_reg; - // reg stb_d1; - - // always @(posedge wb_clk_i) - // begin - // wb_dat_o_reg <= buf_doa[which_buf]; - // stb_d1 <= wb_stb_i; - // wb_ack_o <= (stb_d1 & ~wb_ack_o) | (wb_we_i & wb_stb_i); - // end - //assign wb_dat_o = wb_dat_o_reg; - - mux8 #(.WIDTH(1)) - mux8_wr0(.en(~write_src[0][3]),.sel(write_src[0][2:0]), - .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), - .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]), - .o(wr0_ready_o)); - - mux8 #(.WIDTH(1)) - mux8_wr1(.en(~write_src[1][3]),.sel(write_src[1][2:0]), - .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), - .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]), - .o(wr1_ready_o)); - - mux8 #(.WIDTH(1)) - mux8_wr2(.en(~write_src[2][3]),.sel(write_src[2][2:0]), - .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), - .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]), - .o(wr2_ready_o)); - - mux8 #(.WIDTH(1)) - mux8_wr3(.en(~write_src[3][3]),.sel(write_src[3][2:0]), - .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), - .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]), - .o(wr3_ready_o)); - - mux8 #(.WIDTH(37)) - mux8_rd0(.en(~read_src[0][3]),.sel(read_src[0][2:0]), - .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}), - .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}), - .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}), - .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}), - .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}), - .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}), - .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}), - .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}), - .o({rd0_data_o,rd0_flags_o,rd0_ready_o})); - - mux8 #(.WIDTH(37)) - mux8_rd1(.en(~read_src[1][3]),.sel(read_src[1][2:0]), - .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}), - .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}), - .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}), - .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}), - .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}), - .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}), - .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}), - .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}), - .o({rd1_data_o,rd1_flags_o,rd1_ready_o})); - - mux8 #(.WIDTH(37)) - mux8_rd2(.en(~read_src[2][3]),.sel(read_src[2][2:0]), - .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}), - .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}), - .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}), - .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}), - .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}), - .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}), - .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}), - .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}), - .o({rd2_data_o,rd2_flags_o,rd2_ready_o})); - - mux8 #(.WIDTH(37)) - mux8_rd3(.en(~read_src[3][3]),.sel(read_src[3][2:0]), - .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}), - .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}), - .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}), - .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}), - .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}), - .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}), - .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}), - .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}), - .o({rd3_data_o,rd3_flags_o,rd3_ready_o})); - - assign sys_int_o = (|error) | (|done); - -endmodule // buffer_pool diff --git a/fpga/usrp2/fifo/buffer_pool_tb.v b/fpga/usrp2/fifo/buffer_pool_tb.v deleted file mode 100644 index 0ee76689e..000000000 --- a/fpga/usrp2/fifo/buffer_pool_tb.v +++ /dev/null @@ -1,75 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module buffer_pool_tb(); - - wire wb_clk_i; - wire wb_rst_i; - wire wb_we_i; - wire wb_stb_i; - wire [15:0] wb_adr_i; - wire [31:0] wb_dat_i; - wire [31:0] wb_dat_o; - wire wb_ack_o; - wire wb_err_o; - wire wb_rty_o; - - wire stream_clk, stream_rst; - - wire set_stb; - wire [7:0] set_addr; - wire [31:0] set_data; - - wire [31:0] wr0_data, wr1_data, wr2_data, wr3_data; - wire [31:0] rd0_data, rd1_data, rd2_data, rd3_data; - wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; - wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; - wire wr0_ready, wr1_ready, wr2_ready, wr3_ready; - wire rd0_ready, rd1_ready, rd2_ready, rd3_ready; - wire wr0_write, wr1_write, wr2_write, wr3_write; - wire rd0_read, rd1_read, rd2_read, rd3_read; - - buffer_pool dut - (.wb_clk_i(wb_clk_i), - .wb_rst_i(wb_rst_i), - .wb_we_i(wb_we_i), - .wb_stb_i(wb_stb_i), - .wb_adr_i(wb_adr_i), - .wb_dat_i(wb_dat_i), - .wb_dat_o(wb_dat_o), - .wb_ack_o(wb_ack_o), - .wb_err_o(wb_err_o), - .wb_rty_o(wb_rty_o), - - .stream_clk(stream_clk), - .stream_rst(stream_rst), - - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - - .wr0_data_i(wr0_data), .wr0_write_i(wr0_write), .wr0_flags_i(wr0_flags), .wr0_ready_o(wr0_ready), - .wr1_data_i(wr1_data), .wr1_write_i(wr1_write), .wr1_flags_i(wr1_flags), .wr1_ready_o(wr1_ready), - .wr2_data_i(wr2_data), .wr2_write_i(wr2_write), .wr2_flags_i(wr2_flags), .wr2_ready_o(wr2_ready), - .wr3_data_i(wr3_data), .wr3_write_i(wr3_write), .wr3_flags_i(wr3_flags), .wr3_ready_o(wr3_ready), - - .rd0_data_o(rd0_data), .rd0_read_i(rd0_read), .rd0_flags_o(rd0_flags), .rd0_ready_o(rd0_ready), - .rd1_data_o(rd1_data), .rd1_read_i(rd1_read), .rd1_flags_o(rd1_flags), .rd1_ready_o(rd1_ready), - .rd2_data_o(rd2_data), .rd2_read_i(rd2_read), .rd2_flags_o(rd2_flags), .rd2_ready_o(rd2_ready), - .rd3_data_o(rd3_data), .rd3_read_i(rd3_read), .rd3_flags_o(rd3_flags), .rd3_ready_o(rd3_ready) - ); - -endmodule // buffer_pool_tb diff --git a/fpga/usrp2/fifo/crossbar36.v b/fpga/usrp2/fifo/crossbar36.v deleted file mode 100644 index 4e2aed7ce..000000000 --- a/fpga/usrp2/fifo/crossbar36.v +++ /dev/null @@ -1,59 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module crossbar36 - (input clk, input reset, input clear, - input cross, - input [35:0] data0_i, input src0_rdy_i, output dst0_rdy_o, - input [35:0] data1_i, input src1_rdy_i, output dst1_rdy_o, - output [35:0] data0_o, output src0_rdy_o, input dst0_rdy_i, - output [35:0] data1_o, output src1_rdy_o, input dst1_rdy_i); - - reg cross_int, active0, active1; - wire active0_next = (src0_rdy_i & dst0_rdy_o)? ~data0_i[33] : active0; - wire active1_next = (src1_rdy_i & dst1_rdy_o)? ~data1_i[33] : active1; - - assign data0_o = cross_int ? data1_i : data0_i; - assign data1_o = cross_int ? data0_i : data1_i; - - assign src0_rdy_o = cross_int ? src1_rdy_i : src0_rdy_i; - assign src1_rdy_o = cross_int ? src0_rdy_i : src1_rdy_i; - - assign dst0_rdy_o = cross_int ? dst1_rdy_i : dst0_rdy_i; - assign dst1_rdy_o = cross_int ? dst0_rdy_i : dst1_rdy_i; - - always @(posedge clk) - if(reset | clear) - active0 <= 0; - else - active0 <= active0_next; - - always @(posedge clk) - if(reset | clear) - active1 <= 0; - else - active1 <= active1_next; - - always @(posedge clk) - if(reset | clear) - cross_int <= 0; - else if(~active0_next & ~active1_next) - cross_int <= cross; - -endmodule // crossbar36 diff --git a/fpga/usrp2/fifo/dsp_framer36.v b/fpga/usrp2/fifo/dsp_framer36.v deleted file mode 100644 index ef7395551..000000000 --- a/fpga/usrp2/fifo/dsp_framer36.v +++ /dev/null @@ -1,89 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// This has 3 functions: -// Correct the VITA packet length -// [optional] Frame DSP packets with an header line to be handled by the protocol machine -// Hold on to the packet until there is a complete one before allowing to leave - -module dsp_framer36 - #(parameter BUF_SIZE = 9, - parameter PORT_SEL = 0, - parameter PROT_ENG_FLAGS = 1) - (input clk, input reset, input clear, - input [35:0] data_i, input src_rdy_i, output dst_rdy_o, - output [35:0] data_o, output src_rdy_o, input dst_rdy_i); - - wire dfifo_in_dst_rdy, dfifo_in_src_rdy, dfifo_out_dst_rdy, dfifo_out_src_rdy; - wire tfifo_in_dst_rdy, tfifo_in_src_rdy, tfifo_out_dst_rdy, tfifo_out_src_rdy; - - wire do_xfer_in = dfifo_in_src_rdy & dfifo_in_dst_rdy; - wire do_xfer_out = src_rdy_o & dst_rdy_i; - - wire have_space = dfifo_in_dst_rdy & tfifo_in_dst_rdy; - reg [15:0] pkt_len_in, pkt_len_out; - wire [15:0] tfifo_data; - wire [35:0] dfifo_out_data; - - assign dst_rdy_o = have_space; - assign dfifo_in_src_rdy = src_rdy_i & have_space; - - fifo_cascade #(.WIDTH(36), .SIZE(BUF_SIZE)) dfifo - (.clk(clk), .reset(reset), .clear(clear), - .datain(data_i), .src_rdy_i(dfifo_in_src_rdy), .dst_rdy_o(dfifo_in_dst_rdy), - .dataout(dfifo_out_data), .src_rdy_o(dfifo_out_src_rdy), .dst_rdy_i(dfifo_out_dst_rdy) ); - - fifo_short #(.WIDTH(16)) tfifo - (.clk(clk), .reset(reset), .clear(clear), - .datain(pkt_len_in), .src_rdy_i(tfifo_in_src_rdy), .dst_rdy_o(tfifo_in_dst_rdy), - .dataout(tfifo_data), .src_rdy_o(tfifo_out_src_rdy), .dst_rdy_i(tfifo_out_dst_rdy), - .space(), .occupied() ); - - // FIXME won't handle single-line packets, will show wrong length - always @(posedge clk) - if(reset | clear) - pkt_len_in <= 0; - else if(do_xfer_in) - if(data_i[32]) // sof - pkt_len_in <= 2; // fixes off by one since number is stored before increment - else - pkt_len_in <= pkt_len_in + 1; - - assign tfifo_in_src_rdy = do_xfer_in & data_i[33]; // store length when at eof in - assign tfifo_out_dst_rdy = do_xfer_out & data_o[33]; // remove length from list at eof out - - always @(posedge clk) - if(reset | clear) - pkt_len_out <= (PROT_ENG_FLAGS ? 1'b0 : 1'b1); - else if(do_xfer_out) - if(dfifo_out_data[33]) // eof - pkt_len_out <= (PROT_ENG_FLAGS ? 1'b0 : 1'b1); - else - pkt_len_out <= pkt_len_out + 1; - - assign dfifo_out_dst_rdy = do_xfer_out & (pkt_len_out != 0); - - wire [1:0] port_sel_bits = PORT_SEL; - - assign data_o = (pkt_len_out == 0) ? {3'b000, 1'b1, 13'b0, port_sel_bits, 1'b1, tfifo_data[13:0],2'b00} : - (pkt_len_out == 1) ? {3'b000, (PROT_ENG_FLAGS ? 1'b0: 1'b1), dfifo_out_data[31:16],tfifo_data} : - {dfifo_out_data[35:33], 1'b0, dfifo_out_data[31:0] }; - - assign src_rdy_o = dfifo_out_src_rdy & tfifo_out_src_rdy; - -endmodule // dsp_framer36 diff --git a/fpga/usrp2/fifo/fifo19_mux.v b/fpga/usrp2/fifo/fifo19_mux.v deleted file mode 100644 index a23ac2bb4..000000000 --- a/fpga/usrp2/fifo/fifo19_mux.v +++ /dev/null @@ -1,94 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Mux packets from multiple FIFO interfaces onto a single one. -// Can alternate or give priority to one port (port 0) -// In prio mode, port 1 will never get access if port 0 is always busy - -module fifo19_mux - #(parameter prio = 0) - (input clk, input reset, input clear, - input [18:0] data0_i, input src0_rdy_i, output dst0_rdy_o, - input [18:0] data1_i, input src1_rdy_i, output dst1_rdy_o, - output [18:0] data_o, output src_rdy_o, input dst_rdy_i); - - wire [18:0] data0_int, data1_int; - wire src0_rdy_int, dst0_rdy_int, src1_rdy_int, dst1_rdy_int; - - fifo_short #(.WIDTH(19)) mux_fifo_in0 - (.clk(clk), .reset(reset), .clear(clear), - .datain(data0_i), .src_rdy_i(src0_rdy_i), .dst_rdy_o(dst0_rdy_o), - .dataout(data0_int), .src_rdy_o(src0_rdy_int), .dst_rdy_i(dst0_rdy_int)); - - fifo_short #(.WIDTH(19)) mux_fifo_in1 - (.clk(clk), .reset(reset), .clear(clear), - .datain(data1_i), .src_rdy_i(src1_rdy_i), .dst_rdy_o(dst1_rdy_o), - .dataout(data1_int), .src_rdy_o(src1_rdy_int), .dst_rdy_i(dst1_rdy_int)); - - localparam MUX_IDLE0 = 0; - localparam MUX_DATA0 = 1; - localparam MUX_IDLE1 = 2; - localparam MUX_DATA1 = 3; - - reg [1:0] state; - - wire eof0 = data0_int[17]; - wire eof1 = data1_int[17]; - - wire [18:0] data_int; - wire src_rdy_int, dst_rdy_int; - - always @(posedge clk) - if(reset | clear) - state <= MUX_IDLE0; - else - case(state) - MUX_IDLE0 : - if(src0_rdy_int) - state <= MUX_DATA0; - else if(src1_rdy_int) - state <= MUX_DATA1; - - MUX_DATA0 : - if(src0_rdy_int & dst_rdy_int & eof0) - state <= prio ? MUX_IDLE0 : MUX_IDLE1; - - MUX_IDLE1 : - if(src1_rdy_int) - state <= MUX_DATA1; - else if(src0_rdy_int) - state <= MUX_DATA0; - - MUX_DATA1 : - if(src1_rdy_int & dst_rdy_int & eof1) - state <= MUX_IDLE0; - - default : - state <= MUX_IDLE0; - endcase // case (state) - - assign dst0_rdy_int = (state==MUX_DATA0) ? dst_rdy_int : 0; - assign dst1_rdy_int = (state==MUX_DATA1) ? dst_rdy_int : 0; - assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_int : (state==MUX_DATA1) ? src1_rdy_int : 0; - assign data_int = (state==MUX_DATA0) ? data0_int : data1_int; - - fifo_short #(.WIDTH(19)) mux_fifo - (.clk(clk), .reset(reset), .clear(clear), - .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), - .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); -endmodule // fifo19_mux diff --git a/fpga/usrp2/fifo/fifo19_pad.v b/fpga/usrp2/fifo/fifo19_pad.v deleted file mode 100644 index bb6e1fa92..000000000 --- a/fpga/usrp2/fifo/fifo19_pad.v +++ /dev/null @@ -1,83 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Pads a packet out to the minimum length -// Packets already longer than min length are unchanged - - -module fifo19_pad - #(parameter LENGTH=16, - parameter PAD_VALUE=0) - (input clk, input reset, input clear, - input [18:0] data_i, - input src_rdy_i, - output dst_rdy_o, - output [18:0] data_o, - output src_rdy_o, - input dst_rdy_i); - - reg [15:0] count; - reg [1:0] pad_state; - localparam PAD_IDLE = 0; - localparam PAD_TOOSHORT = 1; - localparam PAD_LONGENOUGH = 2; - localparam PAD_PADDING = 3; - - always @(posedge clk) - if(reset | clear) - pad_state <= PAD_IDLE; - else - case(pad_state) - PAD_IDLE : - begin - count <= 1; - pad_state <= PAD_TOOSHORT; - end - PAD_TOOSHORT : - if(src_rdy_i & dst_rdy_i) - begin - count <= count + 1; - if(data_i[17]) - pad_state <= PAD_PADDING; - else if(count == (LENGTH-1)) - pad_state <= PAD_LONGENOUGH; - end - PAD_PADDING : - if(dst_rdy_i) - begin - count <= count + 1; - if(count == LENGTH) - pad_state <= PAD_IDLE; - end - PAD_LONGENOUGH : - if(src_rdy_i & dst_rdy_i & data_i[17]) - pad_state <= PAD_IDLE; - endcase // case (pad_state) - - wire passthru = (pad_state == PAD_TOOSHORT) | (pad_state == PAD_LONGENOUGH); - - assign dst_rdy_o = passthru ? dst_rdy_i : 1'b0; - assign src_rdy_o = passthru ? src_rdy_i : (pad_state == PAD_PADDING); - - assign data_o[15:0] = (pad_state == PAD_PADDING) ? PAD_VALUE : data_i[15:0]; - assign data_o[16] = (count == 1); - assign data_o[17] = (pad_state == PAD_LONGENOUGH) ? data_i[17] : (count == LENGTH); - assign data_o[18] = (pad_state == PAD_LONGENOUGH) ? data_i[18] : 1'b0; - - -endmodule // fifo19_pad diff --git a/fpga/usrp2/fifo/fifo19_to_fifo36.v b/fpga/usrp2/fifo/fifo19_to_fifo36.v deleted file mode 100644 index 32734405a..000000000 --- a/fpga/usrp2/fifo/fifo19_to_fifo36.v +++ /dev/null @@ -1,127 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Parameter LE tells us if we are little-endian. -// Little-endian means send lower 16 bits first. -// Default is big endian (network order), send upper bits first. - -module fifo19_to_fifo36 - #(parameter LE=0) - (input clk, input reset, input clear, - input [18:0] f19_datain, - input f19_src_rdy_i, - output f19_dst_rdy_o, - - output [35:0] f36_dataout, - output f36_src_rdy_o, - input f36_dst_rdy_i, - output [31:0] debug - ); - - // Shortfifo on input to guarantee no deadlock - wire [18:0] f19_data_int; - wire f19_src_rdy_int, f19_dst_rdy_int; - - fifo_short #(.WIDTH(19)) head_fifo - (.clk(clk),.reset(reset),.clear(clear), - .datain(f19_datain), .src_rdy_i(f19_src_rdy_i), .dst_rdy_o(f19_dst_rdy_o), - .dataout(f19_data_int), .src_rdy_o(f19_src_rdy_int), .dst_rdy_i(f19_dst_rdy_int), - .space(),.occupied() ); - - // Actual f19 to f36 which could deadlock if not connected to shortfifos - reg f36_sof_int, f36_eof_int; - reg [1:0] f36_occ_int; - wire [35:0] f36_data_int; - wire f36_src_rdy_int, f36_dst_rdy_int; - - reg [1:0] state; - reg [15:0] dat0, dat1; - - wire f19_sof_int = f19_data_int[16]; - wire f19_eof_int = f19_data_int[17]; - wire f19_occ_int = f19_data_int[18]; - - wire xfer_out = f36_src_rdy_int & f36_dst_rdy_int; - - always @(posedge clk) - if(f19_src_rdy_int & ((state==0)|xfer_out)) - f36_sof_int <= f19_sof_int; - - always @(posedge clk) - if(f19_src_rdy_int & ((state != 2)|xfer_out)) - f36_eof_int <= f19_eof_int; - - always @(posedge clk) - if(reset) - begin - state <= 0; - f36_occ_int <= 0; - end - else - if(f19_src_rdy_int) - case(state) - 0 : - begin - dat0 <= f19_data_int; - if(f19_eof_int) - begin - state <= 2; - f36_occ_int <= f19_occ_int ? 2'b01 : 2'b10; - end - else - state <= 1; - end - 1 : - begin - dat1 <= f19_data_int; - state <= 2; - if(f19_eof_int) - f36_occ_int <= f19_occ_int ? 2'b11 : 2'b00; - end - 2 : - if(xfer_out) - begin - dat0 <= f19_data_int; - if(f19_eof_int) // remain in state 2 if we are at eof - f36_occ_int <= f19_occ_int ? 2'b01 : 2'b10; - else - state <= 1; - end - endcase // case(state) - else - if(xfer_out) - begin - state <= 0; - f36_occ_int <= 0; - end - - assign f19_dst_rdy_int = xfer_out | (state != 2); - assign f36_data_int = LE ? {f36_occ_int,f36_eof_int,f36_sof_int,dat1,dat0} : - {f36_occ_int,f36_eof_int,f36_sof_int,dat0,dat1}; - assign f36_src_rdy_int = (state == 2); - - assign debug = state; - - // Shortfifo on output to guarantee no deadlock - fifo_short #(.WIDTH(36)) tail_fifo - (.clk(clk),.reset(reset),.clear(clear), - .datain(f36_data_int), .src_rdy_i(f36_src_rdy_int), .dst_rdy_o(f36_dst_rdy_int), - .dataout(f36_dataout), .src_rdy_o(f36_src_rdy_o), .dst_rdy_i(f36_dst_rdy_i), - .space(),.occupied() ); - -endmodule // fifo19_to_fifo36 diff --git a/fpga/usrp2/fifo/fifo19_to_ll8.v b/fpga/usrp2/fifo/fifo19_to_ll8.v deleted file mode 100644 index 1ebb140c2..000000000 --- a/fpga/usrp2/fifo/fifo19_to_ll8.v +++ /dev/null @@ -1,70 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module fifo19_to_ll8 - (input clk, input reset, input clear, - input [18:0] f19_data, - input f19_src_rdy_i, - output f19_dst_rdy_o, - - output reg [7:0] ll_data, - output ll_sof_n, - output ll_eof_n, - output ll_src_rdy_n, - input ll_dst_rdy_n); - - wire ll_sof, ll_eof, ll_src_rdy; - assign ll_sof_n = ~ll_sof; - assign ll_eof_n = ~ll_eof; - assign ll_src_rdy_n = ~ll_src_rdy; - wire ll_dst_rdy = ~ll_dst_rdy_n; - - wire f19_sof = f19_data[16]; - wire f19_eof = f19_data[17]; - wire f19_occ = f19_data[18]; - - wire advance, end_early; - reg state; - - always @(posedge clk) - if(reset) - state <= 0; - else - if(advance) - if(ll_eof) - state <= 0; - else - state <= state + 1; - - always @* - case(state) - 0 : ll_data = f19_data[15:8]; - 1 : ll_data = f19_data[7:0]; - default : ll_data = f19_data[15:8]; - endcase // case (state) - - assign ll_sof = (state==0) & f19_sof; - assign ll_eof = f19_eof & ((f19_occ==1)|(state==1)); - - assign ll_src_rdy = f19_src_rdy_i; - - assign advance = ll_src_rdy & ll_dst_rdy; - assign f19_dst_rdy_o = advance & ((state==1)|ll_eof); - -endmodule // fifo19_to_ll8 - diff --git a/fpga/usrp2/fifo/fifo36_demux.v b/fpga/usrp2/fifo/fifo36_demux.v deleted file mode 100644 index 6f516691a..000000000 --- a/fpga/usrp2/fifo/fifo36_demux.v +++ /dev/null @@ -1,67 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Demux packets from a fifo based on the contents of the first line -// If first line matches the parameter and mask, send to data1, otherwise send to data0 - -module fifo36_demux - #(parameter match_data = 0, - parameter match_mask = 0) - (input clk, input reset, input clear, - input [35:0] data_i, input src_rdy_i, output dst_rdy_o, - output [35:0] data0_o, output src0_rdy_o, input dst0_rdy_i, - output [35:0] data1_o, output src1_rdy_o, input dst1_rdy_i); - - localparam DMX_IDLE = 0; - localparam DMX_DATA0 = 1; - localparam DMX_DATA1 = 2; - - reg [1:0] state; - - wire match = |( (data_i ^ match_data) & match_mask ); - wire eof = data_i[33]; - - always @(posedge clk) - if(reset | clear) - state <= DMX_IDLE; - else - case(state) - DMX_IDLE : - if(src_rdy_i) - if(match) - state <= DMX_DATA1; - else - state <= DMX_DATA0; - DMX_DATA0 : - if(src_rdy_i & dst0_rdy_i & eof) - state <= DMX_IDLE; - DMX_DATA1 : - if(src_rdy_i & dst1_rdy_i & eof) - state <= DMX_IDLE; - default : - state <= DMX_IDLE; - endcase // case (state) - - assign dst_rdy_o = (state==DMX_IDLE) ? 0 : (state==DMX_DATA0) ? dst0_rdy_i : dst1_rdy_i; - assign src0_rdy_o = (state==DMX_DATA0) ? src_rdy_i : 0; - assign src1_rdy_o = (state==DMX_DATA1) ? src_rdy_i : 0; - - assign data0_o = data_i; - assign data1_o = data_i; - -endmodule // fifo36_demux diff --git a/fpga/usrp2/fifo/fifo36_mux.v b/fpga/usrp2/fifo/fifo36_mux.v deleted file mode 100644 index cf7b2b4d1..000000000 --- a/fpga/usrp2/fifo/fifo36_mux.v +++ /dev/null @@ -1,94 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Mux packets from multiple FIFO interfaces onto a single one. -// Can alternate or give priority to one port (port 0) -// In prio mode, port 1 will never get access if port 0 is always busy - -module fifo36_mux - #(parameter prio = 0) - (input clk, input reset, input clear, - input [35:0] data0_i, input src0_rdy_i, output dst0_rdy_o, - input [35:0] data1_i, input src1_rdy_i, output dst1_rdy_o, - output [35:0] data_o, output src_rdy_o, input dst_rdy_i); - - wire [35:0] data0_int, data1_int; - wire src0_rdy_int, dst0_rdy_int, src1_rdy_int, dst1_rdy_int; - - fifo_short #(.WIDTH(36)) mux_fifo_in0 - (.clk(clk), .reset(reset), .clear(clear), - .datain(data0_i), .src_rdy_i(src0_rdy_i), .dst_rdy_o(dst0_rdy_o), - .dataout(data0_int), .src_rdy_o(src0_rdy_int), .dst_rdy_i(dst0_rdy_int)); - - fifo_short #(.WIDTH(36)) mux_fifo_in1 - (.clk(clk), .reset(reset), .clear(clear), - .datain(data1_i), .src_rdy_i(src1_rdy_i), .dst_rdy_o(dst1_rdy_o), - .dataout(data1_int), .src_rdy_o(src1_rdy_int), .dst_rdy_i(dst1_rdy_int)); - - localparam MUX_IDLE0 = 0; - localparam MUX_DATA0 = 1; - localparam MUX_IDLE1 = 2; - localparam MUX_DATA1 = 3; - - reg [1:0] state; - - wire eof0 = data0_int[33]; - wire eof1 = data1_int[33]; - - wire [35:0] data_int; - wire src_rdy_int, dst_rdy_int; - - always @(posedge clk) - if(reset | clear) - state <= MUX_IDLE0; - else - case(state) - MUX_IDLE0 : - if(src0_rdy_int) - state <= MUX_DATA0; - else if(src1_rdy_int) - state <= MUX_DATA1; - - MUX_DATA0 : - if(src0_rdy_int & dst_rdy_int & eof0) - state <= prio ? MUX_IDLE0 : MUX_IDLE1; - - MUX_IDLE1 : - if(src1_rdy_int) - state <= MUX_DATA1; - else if(src0_rdy_int) - state <= MUX_DATA0; - - MUX_DATA1 : - if(src1_rdy_int & dst_rdy_int & eof1) - state <= MUX_IDLE0; - - default : - state <= MUX_IDLE0; - endcase // case (state) - - assign dst0_rdy_int = (state==MUX_DATA0) ? dst_rdy_int : 0; - assign dst1_rdy_int = (state==MUX_DATA1) ? dst_rdy_int : 0; - assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_int : (state==MUX_DATA1) ? src1_rdy_int : 0; - assign data_int = (state==MUX_DATA0) ? data0_int : data1_int; - - fifo_short #(.WIDTH(36)) mux_fifo - (.clk(clk), .reset(reset), .clear(clear), - .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), - .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); -endmodule // fifo36_demux diff --git a/fpga/usrp2/fifo/fifo36_to_fifo19.v b/fpga/usrp2/fifo/fifo36_to_fifo19.v deleted file mode 100644 index cb93e10ad..000000000 --- a/fpga/usrp2/fifo/fifo36_to_fifo19.v +++ /dev/null @@ -1,80 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Parameter LE tells us if we are little-endian. -// Little-endian means send lower 16 bits first. -// Default is big endian (network order), send upper bits first. - -module fifo36_to_fifo19 - #(parameter LE=0) - (input clk, input reset, input clear, - input [35:0] f36_datain, - input f36_src_rdy_i, - output f36_dst_rdy_o, - - output [18:0] f19_dataout, - output f19_src_rdy_o, - input f19_dst_rdy_i ); - - wire [18:0] f19_data_int; - wire f19_src_rdy_int, f19_dst_rdy_int; - wire [35:0] f36_data_int; - wire f36_src_rdy_int, f36_dst_rdy_int; - - // Shortfifo on input to guarantee no deadlock - fifo_short #(.WIDTH(36)) head_fifo - (.clk(clk),.reset(reset),.clear(clear), - .datain(f36_datain), .src_rdy_i(f36_src_rdy_i), .dst_rdy_o(f36_dst_rdy_o), - .dataout(f36_data_int), .src_rdy_o(f36_src_rdy_int), .dst_rdy_i(f36_dst_rdy_int), - .space(),.occupied() ); - - // Main fifo36_to_fifo19, needs shortfifos to guarantee no deadlock - wire [1:0] f36_occ_int = f36_data_int[35:34]; - wire f36_sof_int = f36_data_int[32]; - wire f36_eof_int = f36_data_int[33]; - - reg phase; - wire half_line = f36_eof_int & ((f36_occ_int==1)|(f36_occ_int==2)); - - assign f19_data_int[15:0] = (LE ^ phase) ? f36_data_int[15:0] : f36_data_int[31:16]; - assign f19_data_int[16] = phase ? 0 : f36_sof_int; - assign f19_data_int[17] = phase ? f36_eof_int : half_line; - assign f19_data_int[18] = f19_data_int[17] & ((f36_occ_int==1)|(f36_occ_int==3)); - - assign f19_src_rdy_int = f36_src_rdy_int; - assign f36_dst_rdy_int = (phase | half_line) & f19_dst_rdy_int; - - wire f19_xfer = f19_src_rdy_int & f19_dst_rdy_int; - wire f36_xfer = f36_src_rdy_int & f36_dst_rdy_int; - - always @(posedge clk) - if(reset) - phase <= 0; - else if(f36_xfer) - phase <= 0; - else if(f19_xfer) - phase <= 1; - - // Shortfifo on output to guarantee no deadlock - fifo_short #(.WIDTH(19)) tail_fifo - (.clk(clk),.reset(reset),.clear(clear), - .datain(f19_data_int), .src_rdy_i(f19_src_rdy_int), .dst_rdy_o(f19_dst_rdy_int), - .dataout(f19_dataout), .src_rdy_o(f19_src_rdy_o), .dst_rdy_i(f19_dst_rdy_i), - .space(),.occupied() ); - -endmodule // fifo36_to_fifo19 diff --git a/fpga/usrp2/fifo/fifo36_to_fifo72.v b/fpga/usrp2/fifo/fifo36_to_fifo72.v deleted file mode 100644 index 237149cc2..000000000 --- a/fpga/usrp2/fifo/fifo36_to_fifo72.v +++ /dev/null @@ -1,142 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Parameter LE tells us if we are little-endian. -// Little-endian means send lower 16 bits first. -// Default is big endian (network order), send upper bits first. - -module fifo36_to_fifo72 - #(parameter LE=0) - (input clk, input reset, input clear, - input [35:0] f36_datain, - input f36_src_rdy_i, - output f36_dst_rdy_o, - - output [71:0] f72_dataout, - output f72_src_rdy_o, - input f72_dst_rdy_i, - output [31:0] debug - ); - - // Shortfifo on input to guarantee no deadlock - wire [35:0] f36_data_int; - wire f36_src_rdy_int, f36_dst_rdy_int; - - fifo_short #(.WIDTH(36)) head_fifo - (.clk(clk),.reset(reset),.clear(clear), - .datain(f36_datain), .src_rdy_i(f36_src_rdy_i), .dst_rdy_o(f36_dst_rdy_o), - .dataout(f36_data_int), .src_rdy_o(f36_src_rdy_int), .dst_rdy_i(f36_dst_rdy_int), - .space(),.occupied() ); - - // Actual f36 to f72 which could deadlock if not connected to shortfifos - reg f72_sof_int, f72_eof_int; - reg [2:0] f72_occ_int; - wire [71:0] f72_data_int; - wire f72_src_rdy_int, f72_dst_rdy_int; - - reg [1:0] state; - reg [31:0] dat0, dat1; - - wire f36_sof_int = f36_data_int[32]; - wire f36_eof_int = f36_data_int[33]; - wire [1:0] f36_occ_int = f36_data_int[35:34]; - - wire xfer_out = f72_src_rdy_int & f72_dst_rdy_int; - - always @(posedge clk) - if(f36_src_rdy_int & ((state==0)|xfer_out)) - f72_sof_int <= f36_sof_int; - - always @(posedge clk) - if(f36_src_rdy_int & ((state != 2)|xfer_out)) - f72_eof_int <= f36_eof_int; - - always @(posedge clk) - if(reset) - begin - state <= 0; - f72_occ_int <= 0; - end - else - if(f36_src_rdy_int) - case(state) - 0 : - begin - dat0 <= f36_data_int; - if(f36_eof_int) - begin - state <= 2; - case (f36_occ_int) - 0 : f72_occ_int <= 3'd4; - 1 : f72_occ_int <= 3'd1; - 2 : f72_occ_int <= 3'd2; - 3 : f72_occ_int <= 3'd3; - endcase // case (f36_occ_int) - end - else - state <= 1; - end - 1 : - begin - dat1 <= f36_data_int; - state <= 2; - if(f36_eof_int) - case (f36_occ_int) - 0 : f72_occ_int <= 3'd0; - 1 : f72_occ_int <= 3'd5; - 2 : f72_occ_int <= 3'd6; - 3 : f72_occ_int <= 3'd7; - endcase // case (f36_occ_int) - end - 2 : - if(xfer_out) - begin - dat0 <= f36_data_int; - if(f36_eof_int) // remain in state 2 if we are at eof - case (f36_occ_int) - 0 : f72_occ_int <= 3'd4; - 1 : f72_occ_int <= 3'd1; - 2 : f72_occ_int <= 3'd2; - 3 : f72_occ_int <= 3'd3; - endcase // case (f36_occ_int) - else - state <= 1; - end - endcase // case(state) - else - if(xfer_out) - begin - state <= 0; - f72_occ_int <= 0; - end - - assign f36_dst_rdy_int = xfer_out | (state != 2); - assign f72_data_int = LE ? {3'b000,f72_occ_int[2:0],f72_eof_int,f72_sof_int,dat1,dat0} : - {3'b000,f72_occ_int[2:0],f72_eof_int,f72_sof_int,dat0,dat1}; - assign f72_src_rdy_int = (state == 2); - - assign debug = state; - - // Shortfifo on output to guarantee no deadlock - fifo_short #(.WIDTH(72)) tail_fifo - (.clk(clk),.reset(reset),.clear(clear), - .datain(f72_data_int), .src_rdy_i(f72_src_rdy_int), .dst_rdy_o(f72_dst_rdy_int), - .dataout(f72_dataout), .src_rdy_o(f72_src_rdy_o), .dst_rdy_i(f72_dst_rdy_i), - .space(),.occupied() ); - -endmodule // fifo36_to_fifo72 diff --git a/fpga/usrp2/fifo/fifo36_to_ll8.v b/fpga/usrp2/fifo/fifo36_to_ll8.v deleted file mode 100644 index 5c2da812f..000000000 --- a/fpga/usrp2/fifo/fifo36_to_ll8.v +++ /dev/null @@ -1,92 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module fifo36_to_ll8 - (input clk, input reset, input clear, - input [35:0] f36_data, - input f36_src_rdy_i, - output f36_dst_rdy_o, - - output [7:0] ll_data, - output ll_sof, - output ll_eof, - output ll_src_rdy, - input ll_dst_rdy, - - output [31:0] debug); - - // Shortfifo on input to guarantee no deadlock - wire [35:0] f36_data_int; - wire f36_src_rdy_int, f36_dst_rdy_int; - reg [7:0] ll_data_int; - wire ll_sof_int, ll_eof_int, ll_src_rdy_int, ll_dst_rdy_int; - - fifo_short #(.WIDTH(36)) head_fifo - (.clk(clk),.reset(reset),.clear(clear), - .datain(f36_data), .src_rdy_i(f36_src_rdy_i), .dst_rdy_o(f36_dst_rdy_o), - .dataout(f36_data_int), .src_rdy_o(f36_src_rdy_int), .dst_rdy_i(f36_dst_rdy_int), - .space(),.occupied() ); - - // Actual fifo36 to ll8, can deadlock if not connected to shortfifo - wire [1:0] f36_occ_int = f36_data_int[35:34]; - wire f36_sof_int = f36_data_int[32]; - wire f36_eof_int = f36_data_int[33]; - wire advance, end_early; - reg [1:0] state; - - assign debug = {29'b0,state}; - - always @(posedge clk) - if(reset) - state <= 0; - else - if(advance) - if(ll_eof_int) - state <= 0; - else - state <= state + 1; - - always @* - case(state) - 0 : ll_data_int = f36_data_int[31:24]; - 1 : ll_data_int = f36_data_int[23:16]; - 2 : ll_data_int = f36_data_int[15:8]; - 3 : ll_data_int = f36_data_int[7:0]; - default : ll_data_int = f36_data_int[31:24]; - endcase // case (state) - - assign ll_sof_int = (state==0) & f36_sof_int; - assign ll_eof_int = f36_eof_int & (((state==0)&(f36_occ_int==1)) | - ((state==1)&(f36_occ_int==2)) | - ((state==2)&(f36_occ_int==3)) | - (state==3)); - - assign ll_src_rdy_int = f36_src_rdy_int; - - assign advance = ll_src_rdy_int & ll_dst_rdy_int; - assign f36_dst_rdy_int= advance & ((state==3)|ll_eof_int); - - // Short FIFO on output to guarantee no deadlock - ll8_shortfifo tail_fifo - (.clk(clk), .reset(reset), .clear(clear), - .datain(ll_data_int), .sof_i(ll_sof_int), .eof_i(ll_eof_int), - .error_i(0), .src_rdy_i(ll_src_rdy_int), .dst_rdy_o(ll_dst_rdy_int), - .dataout(ll_data), .sof_o(ll_sof), .eof_o(ll_eof), - .error_o(), .src_rdy_o(ll_src_rdy), .dst_rdy_i(ll_dst_rdy)); - -endmodule // fifo36_to_ll8 diff --git a/fpga/usrp2/fifo/fifo72_to_fifo36.v b/fpga/usrp2/fifo/fifo72_to_fifo36.v deleted file mode 100644 index c365f0196..000000000 --- a/fpga/usrp2/fifo/fifo72_to_fifo36.v +++ /dev/null @@ -1,80 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Parameter LE tells us if we are little-endian. -// Little-endian means send lower 16 bits first. -// Default is big endian (network order), send upper bits first. - -module fifo72_to_fifo36 - #(parameter LE=0) - (input clk, input reset, input clear, - input [71:0] f72_datain, - input f72_src_rdy_i, - output f72_dst_rdy_o, - - output [35:0] f36_dataout, - output f36_src_rdy_o, - input f36_dst_rdy_i ); - - wire [35:0] f36_data_int; - wire f36_src_rdy_int, f36_dst_rdy_int; - wire [71:0] f72_data_int; - wire f72_src_rdy_int, f72_dst_rdy_int; - - // Shortfifo on input to guarantee no deadlock - fifo_short #(.WIDTH(72)) head_fifo - (.clk(clk),.reset(reset),.clear(clear), - .datain(f72_datain), .src_rdy_i(f72_src_rdy_i), .dst_rdy_o(f72_dst_rdy_o), - .dataout(f72_data_int), .src_rdy_o(f72_src_rdy_int), .dst_rdy_i(f72_dst_rdy_int), - .space(),.occupied() ); - - // Main fifo72_to_fifo36, needs shortfifos to guarantee no deadlock - wire [2:0] f72_occ_int = f72_data_int[68:66]; - wire f72_sof_int = f72_data_int[64]; - wire f72_eof_int = f72_data_int[65]; - - reg phase; - wire half_line = f72_eof_int & ( (f72_occ_int==1)|(f72_occ_int==2)|(f72_occ_int==3)|(f72_occ_int==4) ); - - assign f36_data_int[31:0] = (LE ^ phase) ? f72_data_int[31:0] : f72_data_int[63:32]; - assign f36_data_int[32] = phase ? 0 : f72_sof_int; - assign f36_data_int[33] = phase ? f72_eof_int : half_line; - assign f36_data_int[35:34] = f36_data_int[33] ? f72_occ_int[1:0] : 2'b00; - - assign f36_src_rdy_int = f72_src_rdy_int; - assign f72_dst_rdy_int = (phase | half_line) & f36_dst_rdy_int; - - wire f36_xfer = f36_src_rdy_int & f36_dst_rdy_int; - wire f72_xfer = f72_src_rdy_int & f72_dst_rdy_int; - - always @(posedge clk) - if(reset) - phase <= 0; - else if(f72_xfer) - phase <= 0; - else if(f36_xfer) - phase <= 1; - - // Shortfifo on output to guarantee no deadlock - fifo_short #(.WIDTH(36)) tail_fifo - (.clk(clk),.reset(reset),.clear(clear), - .datain(f36_data_int), .src_rdy_i(f36_src_rdy_int), .dst_rdy_o(f36_dst_rdy_int), - .dataout(f36_dataout), .src_rdy_o(f36_src_rdy_o), .dst_rdy_i(f36_dst_rdy_i), - .space(),.occupied() ); - -endmodule // fifo72_to_fifo36 diff --git a/fpga/usrp2/fifo/fifo_19to36_tb.v b/fpga/usrp2/fifo/fifo_19to36_tb.v deleted file mode 100644 index 143b92b1b..000000000 --- a/fpga/usrp2/fifo/fifo_19to36_tb.v +++ /dev/null @@ -1,99 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module fifo_tb(); - - reg clk = 0; - reg rst = 1; - reg clear = 0; - initial #1000 rst = 0; - always #50 clk = ~clk; - - reg [18:0] f19a; - wire [18:0] f19b, f19c, f19d; - wire [35:0] f36a, f36b; - - reg f19a_sr = 0; - wire f19b_sr, f19c_sr, f19d_sr, f36a_sr, f36b_sr; - wire f19a_dr, f19b_dr, f19c_dr, f19d_dr, f36a_dr, f36b_dr; - - fifo_short #(.WIDTH(19)) fifo_short1 - (.clk(clk),.reset(rst),.clear(clear), - .datain(f19a),.src_rdy_i(f19a_sr),.dst_rdy_o(f19a_dr), - .dataout(f19b),.src_rdy_o(f19b_sr),.dst_rdy_i(f19b_dr) ); - - fifo19_to_fifo36 fifo19_to_fifo36 - (.clk(clk),.reset(rst),.clear(clear), - .f19_datain(f19b),.f19_src_rdy_i(f19b_sr),.f19_dst_rdy_o(f19b_dr), - .f36_dataout(f36a),.f36_src_rdy_o(f36a_sr),.f36_dst_rdy_i(f36a_dr) ); - - fifo_short #(.WIDTH(36)) fifo_short2 - (.clk(clk),.reset(rst),.clear(clear), - .datain(f36a),.src_rdy_i(f36a_sr),.dst_rdy_o(f36a_dr), - .dataout(f36b),.src_rdy_o(f36b_sr),.dst_rdy_i(f36b_dr) ); - - fifo36_to_fifo19 fifo36_to_fifo19 - (.clk(clk),.reset(rst),.clear(clear), - .f36_datain(f36b),.f36_src_rdy_i(f36b_sr),.f36_dst_rdy_o(f36b_dr), - .f19_dataout(f19c),.f19_src_rdy_o(f19c_sr),.f19_dst_rdy_i(f19c_dr) ); - - fifo_short #(.WIDTH(19)) fifo_short3 - (.clk(clk),.reset(rst),.clear(clear), - .datain(f19c),.src_rdy_i(f19c_sr),.dst_rdy_o(f19c_dr), - .dataout(f19d),.src_rdy_o(f19d_sr),.dst_rdy_i(f19d_dr) ); - - assign f19d_dr = 1; - - always @(posedge clk) - if(f19a_sr & f19a_dr) - $display("18IN: %h", f19a); - - always @(posedge clk) - if(f19d_sr & f19d_dr) - $display(" 18OUT: %h", f19d); - - always @(posedge clk) - if(f36b_sr & f36b_dr) - $display(" 36: %h", f36b); - - initial $dumpfile("fifo_tb.vcd"); - initial $dumpvars(0,fifo_tb); - - initial - begin - @(negedge rst); - @(posedge clk); - repeat (2) - begin - f19a <= 19'h1_AA01; - f19a_sr <= 1; - @(posedge clk); - f19a <= 19'h0_AA02; - repeat (4) - begin - @(posedge clk); - f19a <= f19a + 1; - end - f19a[18:16] <= 3'b010; - @(posedge clk); - f19a_sr <= 0; - f19a <= 19'h7_FFFF; - @(posedge clk); - end - #20000 $finish; - end -endmodule // longfifo_tb diff --git a/fpga/usrp2/fifo/fifo_2clock.v b/fpga/usrp2/fifo/fifo_2clock.v deleted file mode 100644 index 98aab18a5..000000000 --- a/fpga/usrp2/fifo/fifo_2clock.v +++ /dev/null @@ -1,141 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// FIXME ignores the AWIDTH (fifo size) parameter - -module fifo_2clock - #(parameter WIDTH=36, SIZE=6) - (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, - input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, - input arst); - - wire [SIZE:0] level_rclk, level_wclk; // xilinx adds an extra bit if you ask for accurate levels - wire full, empty, write, read; - - assign dst_rdy_o = ~full; - assign src_rdy_o = ~empty; - assign write = src_rdy_i & dst_rdy_o; - assign read = src_rdy_o & dst_rdy_i; - - generate - if((WIDTH <= 36) && (WIDTH > 19)) begin - wire [35:0] data_in_wide, data_out_wide; - assign data_in_wide[WIDTH-1:0] = datain; - assign dataout = data_out_wide[WIDTH-1:0]; - if(SIZE==9) - fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk - (.rst(arst), - .wr_clk(wclk),.din(data_in_wide),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(data_out_wide),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - else if(SIZE==11) - fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk - (.rst(arst), - .wr_clk(wclk),.din(data_in_wide),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(data_out_wide),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - else if(SIZE==6) - fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk - (.rst(arst), - .wr_clk(wclk),.din(data_in_wide),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(data_out_wide),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - else - fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk - (.rst(arst), - .wr_clk(wclk),.din(data_in_wide),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(data_out_wide),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - end - else if((WIDTH <= 19) && (SIZE <= 4)) begin - wire [18:0] data_in_wide, data_out_wide; - assign data_in_wide[WIDTH-1:0] = datain; - assign dataout = data_out_wide[WIDTH-1:0]; - fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk - (.rst(arst), - .wr_clk(wclk),.din(data_in_wide),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(data_out_wide),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - end - endgenerate - - assign occupied = {{(16-SIZE-1){1'b0}},level_rclk}; - assign space = ((1<. -// - - -module fifo_2clock_cascade - #(parameter WIDTH=32, SIZE=9) - (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, - output [15:0] space, output [15:0] short_space, - input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, - output [15:0] occupied, output [15:0] short_occupied, - input arst); - - wire [WIDTH-1:0] data_int1, data_int2; - wire src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2; - wire [SIZE-1:0] level_wclk, level_rclk; - wire [4:0] s1_space, s1_occupied, s2_space, s2_occupied; - wire [15:0] l_space, l_occupied; - - fifo_short #(.WIDTH(WIDTH)) shortfifo - (.clk(wclk), .reset(arst), .clear(0), - .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), - .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1), - .space(s1_space), .occupied(s1_occupied) ); - - fifo_2clock #(.WIDTH(WIDTH),.SIZE(SIZE)) fifo_2clock - (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .space(l_space), - .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .occupied(l_occupied), - .arst(arst) ); - - fifo_short #(.WIDTH(WIDTH)) shortfifo2 - (.clk(rclk), .reset(arst), .clear(0), - .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2), - .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), - .space(s2_space), .occupied(s2_occupied)); - - // Be conservative -- Only advertise space from input side of fifo, occupied from output side - assign space = {11'b0,s1_space} + l_space; - assign occupied = {11'b0,s2_occupied} + l_occupied; - - // For the fifo_extram, we only want to know the immediately adjacent space - assign short_space = {11'b0,s1_space}; - assign short_occupied = {11'b0,s2_occupied}; - -endmodule // fifo_2clock_cascade diff --git a/fpga/usrp2/fifo/fifo_cascade.v b/fpga/usrp2/fifo/fifo_cascade.v deleted file mode 100644 index 5a79c4090..000000000 --- a/fpga/usrp2/fifo/fifo_cascade.v +++ /dev/null @@ -1,69 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -// This FIFO exists to provide an intermediate point for the data on its -// long trek from one RAM (in the buffer pool) to another (in the longfifo) -// The shortfifo is more flexible in its placement since it is based on -// distributed RAM - -// This one has the shortfifo on both the in and out sides. -module fifo_cascade - #(parameter WIDTH=32, SIZE=9) - (input clk, input reset, input clear, - input [WIDTH-1:0] datain, - input src_rdy_i, - output dst_rdy_o, - output [WIDTH-1:0] dataout, - output src_rdy_o, - input dst_rdy_i, - output [15:0] space, - output [15:0] occupied); - - wire [WIDTH-1:0] data_int, data_int2; - wire src_rdy_1, dst_rdy_1, src_rdy_2, dst_rdy_2; - - wire [4:0] s1_space, s1_occupied, s2_space, s2_occupied; - wire [15:0] l_space, l_occupied; - - fifo_short #(.WIDTH(WIDTH)) head_fifo - (.clk(clk),.reset(reset),.clear(clear), - .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), - .dataout(data_int), .src_rdy_o(src_rdy_1), .dst_rdy_i(dst_rdy_1), - .space(s1_space),.occupied(s1_occupied) ); - - fifo_long #(.WIDTH(WIDTH),.SIZE(SIZE)) middle_fifo - (.clk(clk),.reset(reset),.clear(clear), - .datain(data_int), .src_rdy_i(src_rdy_1), .dst_rdy_o(dst_rdy_1), - .dataout(data_int2), .src_rdy_o(src_rdy_2), .dst_rdy_i(dst_rdy_2), - .space(l_space),.occupied(l_occupied) ); - - fifo_short #(.WIDTH(WIDTH)) tail_fifo - (.clk(clk),.reset(reset),.clear(clear), - .datain(data_int2), .src_rdy_i(src_rdy_2), .dst_rdy_o(dst_rdy_2), - .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), - .space(s2_space),.occupied(s2_occupied) ); - - assign space = {11'b0,s1_space} + {11'b0,s2_space} + l_space; - assign occupied = {11'b0,s1_occupied} + {11'b0,s2_occupied} + l_occupied; - -endmodule // cascadefifo2 - - - - diff --git a/fpga/usrp2/fifo/fifo_long.v b/fpga/usrp2/fifo/fifo_long.v deleted file mode 100644 index c4f0a1cc2..000000000 --- a/fpga/usrp2/fifo/fifo_long.v +++ /dev/null @@ -1,165 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// FIFO intended to be interchangeable with shortfifo, but -// based on block ram instead of SRL16's -// only one clock domain - -// Port A is write port, Port B is read port - -module fifo_long - #(parameter WIDTH=32, SIZE=9) - (input clk, input reset, input clear, - input [WIDTH-1:0] datain, - input src_rdy_i, - output dst_rdy_o, - output [WIDTH-1:0] dataout, - output src_rdy_o, - input dst_rdy_i, - - output reg [15:0] space, - output reg [15:0] occupied); - - wire write = src_rdy_i & dst_rdy_o; - wire read = dst_rdy_i & src_rdy_o; - wire full, empty; - - assign dst_rdy_o = ~full; - assign src_rdy_o = ~empty; - - // Read side states - localparam EMPTY = 0; - localparam PRE_READ = 1; - localparam READING = 2; - - reg [SIZE-1:0] wr_addr, rd_addr; - reg [1:0] read_state; - - reg empty_reg, full_reg; - always @(posedge clk) - if(reset) - wr_addr <= 0; - else if(clear) - wr_addr <= 0; - else if(write) - wr_addr <= wr_addr + 1; - - ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE)) - ram (.clka(clk), - .ena(1'b1), - .wea(write), - .addra(wr_addr), - .dia(datain), - .doa(), - - .clkb(clk), - .enb((read_state==PRE_READ)|read), - .web(0), - .addrb(rd_addr), - .dib({WIDTH{1'b1}}), - .dob(dataout)); - - always @(posedge clk) - if(reset) - begin - read_state <= EMPTY; - rd_addr <= 0; - empty_reg <= 1; - end - else - if(clear) - begin - read_state <= EMPTY; - rd_addr <= 0; - empty_reg <= 1; - end - else - case(read_state) - EMPTY : - if(write) - begin - //rd_addr <= wr_addr; - read_state <= PRE_READ; - end - PRE_READ : - begin - read_state <= READING; - empty_reg <= 0; - rd_addr <= rd_addr + 1; - end - - READING : - if(read) - if(rd_addr == wr_addr) - begin - empty_reg <= 1; - if(write) - read_state <= PRE_READ; - else - read_state <= EMPTY; - end - else - rd_addr <= rd_addr + 1; - endcase // case(read_state) - - wire [SIZE-1:0] dont_write_past_me = rd_addr - 3; - wire becoming_full = wr_addr == dont_write_past_me; - - always @(posedge clk) - if(reset) - full_reg <= 0; - else if(clear) - full_reg <= 0; - else if(read & ~write) - full_reg <= 0; - //else if(write & ~read & (wr_addr == (rd_addr-3))) - else if(write & ~read & becoming_full) - full_reg <= 1; - - //assign empty = (read_state != READING); - assign empty = empty_reg; - - // assign full = ((rd_addr - 1) == wr_addr); - assign full = full_reg; - - ////////////////////////////////////////////// - // space and occupied are for diagnostics only - // not guaranteed exact - - localparam NUMLINES = (1<. -// - - - -module fifo_pacer - (input clk, - input reset, - input [7:0] rate, - input enable, - input src1_rdy_i, output dst1_rdy_o, - output src2_rdy_o, input dst2_rdy_i, - output underrun, overrun); - - wire strobe; - - cic_strober strober (.clock(clk), .reset(reset), .enable(enable), - .rate(rate), .strobe_fast(1), .strobe_slow(strobe)); - - wire all_ready = src1_rdy_i & dst2_rdy_i; - assign dst1_rdy_o = all_ready & strobe; - assign src2_rdy_o = dst1_rdy_o; - - assign underrun = strobe & ~src1_rdy_i; - assign overrun = strobe & ~dst2_rdy_i; - -endmodule // fifo_pacer diff --git a/fpga/usrp2/fifo/fifo_short.v b/fpga/usrp2/fifo/fifo_short.v deleted file mode 100644 index 32f26beef..000000000 --- a/fpga/usrp2/fifo/fifo_short.v +++ /dev/null @@ -1,112 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module fifo_short - #(parameter WIDTH=32) - (input clk, input reset, input clear, - input [WIDTH-1:0] datain, - input src_rdy_i, - output dst_rdy_o, - output [WIDTH-1:0] dataout, - output src_rdy_o, - input dst_rdy_i, - - output reg [4:0] space, - output reg [4:0] occupied); - - reg full, empty; - wire write = src_rdy_i & dst_rdy_o; - wire read = dst_rdy_i & src_rdy_o; - - assign dst_rdy_o = ~full; - assign src_rdy_o = ~empty; - - reg [3:0] a; - genvar i; - - generate - for (i=0;i 00 = all 4 bytes - 01 = 1 byte - 10 = 2 bytes - 11 = 3 bytes - -fifo36 --> {OCC[1:0],EOP,SOP,DATA[31:0]} - OCC same as buffer interface - -fifo19 --> {OCC,EOP,SOP,DATA[15:0]} - Doesn't fit well into BRAM, dist RAM ok - OCC = 1 means last word is half full - = 0 means last word is full - -fifo18 --> {EOP,SOP,DATA[15:0]} - No half-word capability? Should we drop sop instead? - -Control Wires - Data into FIFO - SRC_RDY_i Upstream has data for me - DST_RDY_o I have space - Transfer occurs if SRC_RDI_i && DST_RDY_o - -Control Wires - Data out of FIFO - SRC_RDY_o I have data for downstream - DST_RDY_i Downstream has space - Transfer occurs if SRC_RDI_o && DST_RDY_i - diff --git a/fpga/usrp2/fifo/fifo_tb.v b/fpga/usrp2/fifo/fifo_tb.v deleted file mode 100644 index c63c201d0..000000000 --- a/fpga/usrp2/fifo/fifo_tb.v +++ /dev/null @@ -1,72 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module fifo_tb(); - - reg clk = 0; - reg rst = 1; - reg clear = 0; - initial #1000 rst = 0; - always #50 clk = ~clk; - - reg [31:0] f36_data = 0; - reg [1:0] f36_occ = 0; - reg f36_sof = 0, f36_eof = 0; - reg f36_src_rdy; - wire f36_dst_rdy; - - wire [7:0] ll_data; - wire ll_src_rdy, ll_dst_rdy, ll_sof, ll_eof; - wire [35:0] err_dat; - wire err_src_rdy, err_dst_rdy; - - fifo36_to_ll8 fifo36_to_ll8 - (.clk(clk),.reset(rst),.clear(clear), - .f36_data({f36_occ,f36_eof,f36_sof,f36_data}),.f36_src_rdy_i(f36_src_rdy),.f36_dst_rdy_o(f36_dst_rdy), - .ll_data(ll_data),.ll_sof(ll_sof),.ll_eof(ll_eof), - .ll_src_rdy(ll_src_rdy),.ll_dst_rdy(ll_dst_rdy)); - - assign ll_dst_rdy = 1; - - always @(posedge clk) - if(ll_src_rdy) - $display("LL: SOF %d, EOF %d, DAT %x",ll_sof,ll_eof,ll_data); - - initial $dumpfile("fifo_tb.vcd"); - initial $dumpvars(0,fifo_tb); - - initial - begin - @(negedge rst); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - f36_src_rdy <= 1; - {f36_occ,f36_eof,f36_sof,f36_data} <= { 2'b00,1'b0,1'b1,32'h00010203}; - @(posedge clk); - {f36_occ,f36_eof,f36_sof,f36_data} <= { 2'b00,1'b0,1'b0,32'h04050607}; - @(posedge clk); - {f36_occ,f36_eof,f36_sof,f36_data} <= { 2'b00,1'b0,1'b0,32'h08090a0b}; - @(posedge clk); - {f36_occ,f36_eof,f36_sof,f36_data} <= { 2'b11,1'b1,1'b0,32'h0c0d0e0f}; - @(posedge clk); - f36_src_rdy <= 0; - end - - initial #4000 $finish; -endmodule // longfifo_tb diff --git a/fpga/usrp2/fifo/ll8_shortfifo.v b/fpga/usrp2/fifo/ll8_shortfifo.v deleted file mode 100644 index 49b3a3139..000000000 --- a/fpga/usrp2/fifo/ll8_shortfifo.v +++ /dev/null @@ -1,30 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module ll8_shortfifo - (input clk, input reset, input clear, - input [7:0] datain, input sof_i, input eof_i, input error_i, input src_rdy_i, output dst_rdy_o, - output [7:0] dataout, output sof_o, output eof_o, output error_o, output src_rdy_o, input dst_rdy_i); - - fifo_short #(.WIDTH(11)) fifo_short - (.clk(clk), .reset(reset), .clear(clear), - .datain({error_i,eof_i,sof_i,datain}), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), - .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); - -endmodule // ll8_shortfifo diff --git a/fpga/usrp2/fifo/ll8_to_fifo19.v b/fpga/usrp2/fifo/ll8_to_fifo19.v deleted file mode 100644 index 4503d0c3d..000000000 --- a/fpga/usrp2/fifo/ll8_to_fifo19.v +++ /dev/null @@ -1,104 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module ll8_to_fifo19 - (input clk, input reset, input clear, - input [7:0] ll_data, - input ll_sof, - input ll_eof, - input ll_src_rdy, - output ll_dst_rdy, - - output [18:0] f19_data, - output f19_src_rdy_o, - input f19_dst_rdy_i ); - - // Short FIFO on input to guarantee no deadlock - wire [7:0] ll_data_int; - wire ll_sof_int, ll_eof_int, ll_src_rdy_int, ll_dst_rdy_int; - - ll8_shortfifo head_fifo - (.clk(clk), .reset(reset), .clear(clear), - .datain(ll_data), .sof_i(ll_sof), .eof_i(ll_eof), - .error_i(0), .src_rdy_i(ll_src_rdy), .dst_rdy_o(ll_dst_rdy), - .dataout(ll_data_int), .sof_o(ll_sof_int), .eof_o(ll_eof_int), - .error_o(), .src_rdy_o(ll_src_rdy_int), .dst_rdy_i(ll_dst_rdy_int)); - - // Actual ll8_to_fifo19 which could deadlock if not connected to a shortfifo - localparam XFER_EMPTY = 0; - localparam XFER_HALF = 1; - localparam XFER_HALF_WRITE = 3; - - wire [18:0] f19_data_int; - wire f19_sof_int, f19_eof_int, f19_occ_int, f19_src_rdy_int, f19_dst_rdy_int; - - wire xfer_out = f19_src_rdy_int & f19_dst_rdy_int; - wire xfer_in = ll_src_rdy_int & ll_dst_rdy_int; - reg hold_sof; - - reg [1:0] state; - reg [7:0] hold_reg; - - always @(posedge clk) - if(ll_src_rdy_int & (state==XFER_EMPTY)) - hold_reg <= ll_data_int; - - always @(posedge clk) - if(ll_sof_int & (state==XFER_EMPTY)) - hold_sof <= 1; - else if(xfer_out) - hold_sof <= 0; - - always @(posedge clk) - if(reset | clear) - state <= XFER_EMPTY; - else - case(state) - XFER_EMPTY : - if(ll_src_rdy_int) - if(ll_eof_int) - state <= XFER_HALF_WRITE; - else - state <= XFER_HALF; - XFER_HALF : - if(ll_src_rdy_int & f19_dst_rdy_int) - state <= XFER_EMPTY; - XFER_HALF_WRITE : - if(f19_dst_rdy_int) - state <= XFER_EMPTY; - endcase // case (state) - - assign ll_dst_rdy_int = (state==XFER_EMPTY) | ((state==XFER_HALF)&f19_dst_rdy_int); - assign f19_src_rdy_int= (state==XFER_HALF_WRITE) | ((state==XFER_HALF)&ll_src_rdy_int); - - assign f19_sof_int = hold_sof | (ll_sof_int & (state==XFER_HALF)); - assign f19_eof_int = (state == XFER_HALF_WRITE) | ll_eof_int; - assign f19_occ_int = (state == XFER_HALF_WRITE); - - assign f19_data_int = {f19_occ_int,f19_eof_int,f19_sof_int,hold_reg,ll_data_int}; - - // Shortfifo on output to guarantee no deadlock - fifo_short #(.WIDTH(19)) tail_fifo - (.clk(clk),.reset(reset),.clear(clear), - .datain(f19_data_int), .src_rdy_i(f19_src_rdy_int), .dst_rdy_o(f19_dst_rdy_int), - .dataout(f19_data), .src_rdy_o(f19_src_rdy_o), .dst_rdy_i(f19_dst_rdy_i), - .space(),.occupied() ); - - -endmodule // ll8_to_fifo19 - diff --git a/fpga/usrp2/fifo/ll8_to_fifo36.v b/fpga/usrp2/fifo/ll8_to_fifo36.v deleted file mode 100644 index b26f745d2..000000000 --- a/fpga/usrp2/fifo/ll8_to_fifo36.v +++ /dev/null @@ -1,114 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module ll8_to_fifo36 - (input clk, input reset, input clear, - input [7:0] ll_data, - input ll_sof_n, - input ll_eof_n, - input ll_src_rdy_n, - output ll_dst_rdy_n, - - output [35:0] f36_data, - output f36_src_rdy_o, - input f36_dst_rdy_i ); - - wire f36_write = f36_src_rdy_o & f36_dst_rdy_i; - - // Why anybody would use active low in an FPGA is beyond me... - wire ll_sof = ~ll_sof_n; - wire ll_eof = ~ll_eof_n; - wire ll_src_rdy = ~ll_src_rdy_n; - wire ll_dst_rdy; - assign ll_dst_rdy_n = ~ll_dst_rdy; - - reg f36_sof, f36_eof; - reg [1:0] f36_occ; - - - reg [2:0] state; - reg [7:0] dat0, dat1, dat2, dat3; - - always @(posedge clk) - if(ll_src_rdy & ((state==0)|f36_write)) - f36_sof <= ll_sof; - - always @(posedge clk) - if(ll_src_rdy & ((state !=4)|f36_write)) - f36_eof <= ll_eof; - - always @(posedge clk) - if(ll_eof) - f36_occ <= state[1:0] + 1; - else - f36_occ <= 0; - - always @(posedge clk) - if(reset) - state <= 0; - else - if(ll_src_rdy) - case(state) - 0 : - if(ll_eof) - state <= 4; - else - state <= 1; - 1 : - if(ll_eof) - state <= 4; - else - state <= 2; - 2 : - if(ll_eof) - state <= 4; - else - state <= 3; - 3 : state <= 4; - 4 : - if(f36_dst_rdy_i) - if(ll_eof) - state <= 4; - else - state <= 1; - endcase // case(state) - else - if(f36_write) - state <= 0; - - always @(posedge clk) - if(ll_src_rdy & (state==3)) - dat3 <= ll_data; - - always @(posedge clk) - if(ll_src_rdy & (state==2)) - dat2 <= ll_data; - - always @(posedge clk) - if(ll_src_rdy & (state==1)) - dat1 <= ll_data; - - always @(posedge clk) - if(ll_src_rdy & ((state==0) | f36_write)) - dat0 <= ll_data; - - assign ll_dst_rdy = f36_dst_rdy_i | (state != 4); - assign f36_data = {f36_occ,f36_eof,f36_sof,dat0,dat1,dat2,dat3}; // FIXME endianess - assign f36_src_rdy_o = (state == 4); - -endmodule // ll8_to_fifo36 diff --git a/fpga/usrp2/fifo/packet32_tb.v b/fpga/usrp2/fifo/packet32_tb.v deleted file mode 100644 index 8a7cfcec5..000000000 --- a/fpga/usrp2/fifo/packet32_tb.v +++ /dev/null @@ -1,44 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module packet32_tb(); - - wire [35:0] data; - wire src_rdy, dst_rdy; - - wire clear = 0; - reg clk = 0; - reg reset = 1; - - always #10 clk <= ~clk; - initial #1000 reset <= 0; - - initial $dumpfile("packet32_tb.vcd"); - initial $dumpvars(0,packet32_tb); - - wire [31:0] total, crc_err, seq_err, len_err; - - packet_generator32 pkt_gen (.clk(clk), .reset(reset), .clear(clear), - .data_o(data), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); - - packet_verifier32 pkt_ver (.clk(clk), .reset(reset), .clear(clear), - .data_i(data), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), - .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); - -endmodule // packet32_tb diff --git a/fpga/usrp2/fifo/packet_dispatcher36_x3.v b/fpga/usrp2/fifo/packet_dispatcher36_x3.v deleted file mode 100644 index 0f9e752c8..000000000 --- a/fpga/usrp2/fifo/packet_dispatcher36_x3.v +++ /dev/null @@ -1,294 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// Packet dispatcher with fifo36 interface and 3 outputs. -// -// The packet dispatcher expects 2-byte padded ethernet frames. -// The frames will be inspected at ethernet, IPv4, UDP, and VRT layers. -// Packets are dispatched into the following streams: -// * tx dsp stream -// * to cpu stream -// * to external stream -// * to both cpu and external -// -// The following registers are used for dispatcher control: -// * base + 0 = this ipv4 address (32 bits) -// * base + 1 = udp dst port (lower 16 bits) -// - -module packet_dispatcher36_x3 - #( - parameter BASE = 0 - ) - ( - //clocking and reset interface: - input clk, input rst, input clr, - - //setting register interface: - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - //input stream interfaces: - input [35:0] com_inp_data, input com_inp_valid, output com_inp_ready, - - //output stream interfaces: - output [35:0] ext_out_data, output ext_out_valid, input ext_out_ready, - output [35:0] dsp_out_data, output dsp_out_valid, input dsp_out_ready, - output [35:0] cpu_out_data, output cpu_out_valid, input cpu_out_ready - ); - - //setting register to program the IP address - wire [31:0] my_ip_addr; - setting_reg #(.my_addr(BASE+0)) sreg_ip_addr( - .clk(clk),.rst(rst), - .strobe(set_stb),.addr(set_addr),.in(set_data), - .out(my_ip_addr),.changed() - ); - - //setting register to program the UDP DSP port - wire [15:0] dsp_udp_port; - setting_reg #(.my_addr(BASE+1), .width(16)) sreg_data_port( - .clk(clk),.rst(rst), - .strobe(set_stb),.addr(set_addr),.in(set_data), - .out(dsp_udp_port),.changed() - ); - - //////////////////////////////////////////////////////////////////// - // Communication input inspector - // - inspect com input and send it to DSP, EXT, CPU, or BOTH - //////////////////////////////////////////////////////////////////// - localparam PD_STATE_READ_COM_PRE = 0; - localparam PD_STATE_READ_COM = 1; - localparam PD_STATE_WRITE_REGS = 2; - localparam PD_STATE_WRITE_LIVE = 3; - - localparam PD_DEST_DSP = 0; - localparam PD_DEST_EXT = 1; - localparam PD_DEST_CPU = 2; - localparam PD_DEST_BOF = 3; - - localparam PD_MAX_NUM_DREGS = 13; //padded_eth + ip + udp + seq + vrt_hdr - localparam PD_DREGS_DSP_OFFSET = 11; //offset to start dsp at - - //output inspector interfaces - wire [35:0] pd_out_dsp_data; - wire pd_out_dsp_valid; - wire pd_out_dsp_ready; - - wire [35:0] pd_out_ext_data; - wire pd_out_ext_valid; - wire pd_out_ext_ready; - - wire [35:0] pd_out_cpu_data; - wire pd_out_cpu_valid; - wire pd_out_cpu_ready; - - wire [35:0] pd_out_bof_data; - wire pd_out_bof_valid; - wire pd_out_bof_ready; - - reg [1:0] pd_state; - reg [1:0] pd_dest; - reg [3:0] pd_dreg_count; //data registers to buffer headers - wire [3:0] pd_dreg_count_next = pd_dreg_count + 1'b1; - wire pd_dreg_counter_done = (pd_dreg_count_next == PD_MAX_NUM_DREGS)? 1'b1 : 1'b0; - reg [35:0] pd_dregs [PD_MAX_NUM_DREGS-1:0]; - - reg is_eth_dst_mac_bcast; - reg is_eth_type_ipv4; - reg is_eth_ipv4_proto_udp; - reg is_eth_ipv4_dst_addr_here; - reg is_eth_udp_dst_port_here; - wire is_vrt_size_zero = (com_inp_data[15:0] == 16'h0); //needed on the same cycle, so it cant be registered - - //Inspector output flags special case: - //Inject SOF into flags at first DSP line. - wire [3:0] pd_out_flags = ( - (pd_dreg_count == PD_DREGS_DSP_OFFSET) && - (pd_dest == PD_DEST_DSP) - )? 4'b0001 : pd_dregs[pd_dreg_count][35:32]; - - //The communication inspector ouput data and valid signals: - //Mux between com input and data registers based on the state. - wire [35:0] pd_out_data = (pd_state == PD_STATE_WRITE_REGS)? - {pd_out_flags, pd_dregs[pd_dreg_count][31:0]} : com_inp_data - ; - wire pd_out_valid = - (pd_state == PD_STATE_WRITE_REGS)? 1'b1 : ( - (pd_state == PD_STATE_WRITE_LIVE)? com_inp_valid : ( - 1'b0)); - - //The communication inspector ouput ready signal: - //Mux between the various destination ready signals. - wire pd_out_ready = - (pd_dest == PD_DEST_DSP)? pd_out_dsp_ready : ( - (pd_dest == PD_DEST_EXT)? pd_out_ext_ready : ( - (pd_dest == PD_DEST_CPU)? pd_out_cpu_ready : ( - (pd_dest == PD_DEST_BOF)? pd_out_bof_ready : ( - 1'b0)))); - - //Always connected output data lines. - assign pd_out_dsp_data = pd_out_data; - assign pd_out_ext_data = pd_out_data; - assign pd_out_cpu_data = pd_out_data; - assign pd_out_bof_data = pd_out_data; - - //Destination output valid signals: - //Comes from inspector valid when destination is selected, and otherwise low. - assign pd_out_dsp_valid = (pd_dest == PD_DEST_DSP)? pd_out_valid : 1'b0; - assign pd_out_ext_valid = (pd_dest == PD_DEST_EXT)? pd_out_valid : 1'b0; - assign pd_out_cpu_valid = (pd_dest == PD_DEST_CPU)? pd_out_valid : 1'b0; - assign pd_out_bof_valid = (pd_dest == PD_DEST_BOF)? pd_out_valid : 1'b0; - - //The communication inspector ouput ready signal: - //Always ready when storing to data registers, - //comes from inspector ready output when live, - //and otherwise low. - assign com_inp_ready = - (pd_state == PD_STATE_READ_COM_PRE) ? 1'b1 : ( - (pd_state == PD_STATE_READ_COM) ? 1'b1 : ( - (pd_state == PD_STATE_WRITE_LIVE) ? pd_out_ready : ( - 1'b0))); - - //inspect the incoming data and mark register booleans - always @(posedge clk) - if (com_inp_ready & com_inp_valid) begin - case(pd_dreg_count) - 0: begin - is_eth_dst_mac_bcast <= (com_inp_data[15:0] == 16'hffff); - end - 1: begin - is_eth_dst_mac_bcast <= is_eth_dst_mac_bcast && (com_inp_data[31:0] == 32'hffffffff); - end - 3: begin - is_eth_type_ipv4 <= (com_inp_data[15:0] == 16'h800); - end - 6: begin - is_eth_ipv4_proto_udp <= (com_inp_data[23:16] == 8'h11); - end - 8: begin - is_eth_ipv4_dst_addr_here <= (com_inp_data[31:0] == my_ip_addr); - end - 9: begin - is_eth_udp_dst_port_here <= (com_inp_data[15:0] == dsp_udp_port); - end - endcase //pd_dreg_count - end - - always @(posedge clk) - if(rst | clr) begin - pd_state <= PD_STATE_READ_COM_PRE; - pd_dreg_count <= 0; - end - else begin - case(pd_state) - PD_STATE_READ_COM_PRE: begin - if (com_inp_ready & com_inp_valid & com_inp_data[32]) begin - pd_state <= PD_STATE_READ_COM; - pd_dreg_count <= pd_dreg_count_next; - pd_dregs[pd_dreg_count] <= com_inp_data; - end - end - - PD_STATE_READ_COM: begin - if (com_inp_ready & com_inp_valid) begin - pd_dregs[pd_dreg_count] <= com_inp_data; - if (pd_dreg_counter_done | com_inp_data[33]) begin - pd_state <= PD_STATE_WRITE_REGS; - pd_dreg_count <= 0; - - //---------- begin inspection decision -----------// - //EOF or bcast or not IPv4 or not UDP: - if ( - com_inp_data[33] || is_eth_dst_mac_bcast || - ~is_eth_type_ipv4 || ~is_eth_ipv4_proto_udp - ) begin - pd_dest <= PD_DEST_BOF; - end - - //not my IP address: - else if (~is_eth_ipv4_dst_addr_here) begin - pd_dest <= PD_DEST_EXT; - end - - //UDP data port and VRT: - else if (is_eth_udp_dst_port_here && ~is_vrt_size_zero) begin - pd_dest <= PD_DEST_DSP; - pd_dreg_count <= PD_DREGS_DSP_OFFSET; - end - - //other: - else begin - pd_dest <= PD_DEST_CPU; - end - //---------- end inspection decision -------------// - - end - else begin - pd_dreg_count <= pd_dreg_count_next; - end - end - end - - PD_STATE_WRITE_REGS: begin - if (pd_out_ready & pd_out_valid) begin - if (pd_out_data[33]) begin - pd_state <= PD_STATE_READ_COM_PRE; - pd_dreg_count <= 0; - end - else if (pd_dreg_counter_done) begin - pd_state <= PD_STATE_WRITE_LIVE; - pd_dreg_count <= 0; - end - else begin - pd_dreg_count <= pd_dreg_count_next; - end - end - end - - PD_STATE_WRITE_LIVE: begin - if (pd_out_ready & pd_out_valid & pd_out_data[33]) begin - pd_state <= PD_STATE_READ_COM_PRE; - end - end - - endcase //pd_state - end - - //connect this fast-path signals directly to the DSP out - assign dsp_out_data = pd_out_dsp_data; - assign dsp_out_valid = pd_out_dsp_valid; - assign pd_out_dsp_ready = dsp_out_ready; - - //////////////////////////////////////////////////////////////////// - // Splitter and output muxes for the bof packets - // - split the bof packets into two streams - // - mux split packets into cpu out and ext out - //////////////////////////////////////////////////////////////////// - - //dummy signals to join the the splitter and muxes below - wire [35:0] _split_to_ext_data, _split_to_cpu_data; - wire _split_to_ext_valid, _split_to_cpu_valid; - wire _split_to_ext_ready, _split_to_cpu_ready; - - splitter36 bof_out_splitter( - .clk(clk), .rst(rst), .clr(clr), - .inp_data(pd_out_bof_data), .inp_valid(pd_out_bof_valid), .inp_ready(pd_out_bof_ready), - .out0_data(_split_to_ext_data), .out0_valid(_split_to_ext_valid), .out0_ready(_split_to_ext_ready), - .out1_data(_split_to_cpu_data), .out1_valid(_split_to_cpu_valid), .out1_ready(_split_to_cpu_ready) - ); - - fifo36_mux ext_out_mux( - .clk(clk), .reset(rst), .clear(clr), - .data0_i(pd_out_ext_data), .src0_rdy_i(pd_out_ext_valid), .dst0_rdy_o(pd_out_ext_ready), - .data1_i(_split_to_ext_data), .src1_rdy_i(_split_to_ext_valid), .dst1_rdy_o(_split_to_ext_ready), - .data_o(ext_out_data), .src_rdy_o(ext_out_valid), .dst_rdy_i(ext_out_ready) - ); - - fifo36_mux cpu_out_mux( - .clk(clk), .reset(rst), .clear(clr), - .data0_i(pd_out_cpu_data), .src0_rdy_i(pd_out_cpu_valid), .dst0_rdy_o(pd_out_cpu_ready), - .data1_i(_split_to_cpu_data), .src1_rdy_i(_split_to_cpu_valid), .dst1_rdy_o(_split_to_cpu_ready), - .data_o(cpu_out_data), .src_rdy_o(cpu_out_valid), .dst_rdy_i(cpu_out_ready) - ); - -endmodule // packet_dispatcher36_x3 diff --git a/fpga/usrp2/fifo/packet_dispatcher36_x4.v b/fpga/usrp2/fifo/packet_dispatcher36_x4.v deleted file mode 100644 index 7eedb3e74..000000000 --- a/fpga/usrp2/fifo/packet_dispatcher36_x4.v +++ /dev/null @@ -1,316 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// Packet dispatcher with fifo36 interface and 4 outputs. -// -// The packet dispatcher expects 2-byte padded ethernet frames. -// The frames will be inspected at ethernet, IPv4, UDP, and VRT layers. -// Packets are dispatched into the following streams: -// * tx dsp stream -// * tx control stream -// * to cpu stream -// * to external stream -// * to both cpu and external -// -// The following registers are used for dispatcher control: -// * base + 0 = this ipv4 address (32 bits) -// * base + 1 = udp control port (upper 16 bits), udp dsp port (lower 16 bits) -// - -module packet_dispatcher36_x4 - #( - parameter BASE = 0 - ) - ( - //clocking and reset interface: - input clk, input rst, input clr, - - //setting register interface: - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - //input stream interfaces: - input [35:0] com_inp_data, input com_inp_valid, output com_inp_ready, - - //output stream interfaces: - output [35:0] ext_out_data, output ext_out_valid, input ext_out_ready, - output [35:0] dsp_out_data, output dsp_out_valid, input dsp_out_ready, - output [35:0] ctl_out_data, output ctl_out_valid, input ctl_out_ready, - output [35:0] cpu_out_data, output cpu_out_valid, input cpu_out_ready - ); - - //setting register to program the IP address - wire [31:0] my_ip_addr; - setting_reg #(.my_addr(BASE+0)) sreg_ip_addr( - .clk(clk),.rst(rst), - .strobe(set_stb),.addr(set_addr),.in(set_data), - .out(my_ip_addr),.changed() - ); - - //setting register to program the UDP DSP port - wire [15:0] dsp_udp_port, ctl_udp_port; - setting_reg #(.my_addr(BASE+1), .width(32)) sreg_data_port( - .clk(clk),.rst(rst), - .strobe(set_stb),.addr(set_addr),.in(set_data), - .out({ctl_udp_port, dsp_udp_port}),.changed() - ); - - //////////////////////////////////////////////////////////////////// - // Communication input inspector - // - inspect com input and send it to DSP, EXT, CPU, or BOTH - //////////////////////////////////////////////////////////////////// - localparam PD_STATE_READ_COM_PRE = 0; - localparam PD_STATE_READ_COM = 1; - localparam PD_STATE_WRITE_REGS = 2; - localparam PD_STATE_WRITE_LIVE = 3; - - localparam PD_DEST_DSP = 0; - localparam PD_DEST_EXT = 1; - localparam PD_DEST_CPU = 2; - localparam PD_DEST_BOF = 3; - localparam PD_DEST_CTL = 4; - - localparam PD_MAX_NUM_DREGS = 13; //padded_eth + ip + udp + seq + vrt_hdr - localparam PD_DREGS_DSP_OFFSET = 11; //offset to start dsp at - - //output inspector interfaces - wire [35:0] pd_out_dsp_data; - wire pd_out_dsp_valid; - wire pd_out_dsp_ready; - - wire [35:0] pd_out_ext_data; - wire pd_out_ext_valid; - wire pd_out_ext_ready; - - wire [35:0] pd_out_cpu_data; - wire pd_out_cpu_valid; - wire pd_out_cpu_ready; - - wire [35:0] pd_out_bof_data; - wire pd_out_bof_valid; - wire pd_out_bof_ready; - - wire [35:0] pd_out_ctl_data; - wire pd_out_ctl_valid; - wire pd_out_ctl_ready; - - reg [1:0] pd_state; - reg [2:0] pd_dest; - reg [3:0] pd_dreg_count; //data registers to buffer headers - wire [3:0] pd_dreg_count_next = pd_dreg_count + 1'b1; - wire pd_dreg_counter_done = (pd_dreg_count_next == PD_MAX_NUM_DREGS)? 1'b1 : 1'b0; - reg [35:0] pd_dregs [PD_MAX_NUM_DREGS-1:0]; - - reg is_eth_dst_mac_bcast; - reg is_eth_type_ipv4; - reg is_eth_ipv4_proto_udp; - reg is_eth_ipv4_dst_addr_here; - reg is_eth_udp_dsp_port_here; - reg is_eth_udp_ctl_port_here; - wire is_vrt_size_zero = (com_inp_data[15:0] == 16'h0); //needed on the same cycle, so it cant be registered - - //Inspector output flags special case: - //Inject SOF into flags at first DSP line. - wire [3:0] pd_out_flags = ( - (pd_dreg_count == PD_DREGS_DSP_OFFSET) && - (pd_dest == PD_DEST_DSP) - )? 4'b0001 : pd_dregs[pd_dreg_count][35:32]; - - //The communication inspector ouput data and valid signals: - //Mux between com input and data registers based on the state. - wire [35:0] pd_out_data = (pd_state == PD_STATE_WRITE_REGS)? - {pd_out_flags, pd_dregs[pd_dreg_count][31:0]} : com_inp_data - ; - wire pd_out_valid = - (pd_state == PD_STATE_WRITE_REGS)? 1'b1 : ( - (pd_state == PD_STATE_WRITE_LIVE)? com_inp_valid : ( - 1'b0)); - - //The communication inspector ouput ready signal: - //Mux between the various destination ready signals. - wire pd_out_ready = - (pd_dest == PD_DEST_DSP)? pd_out_dsp_ready : ( - (pd_dest == PD_DEST_EXT)? pd_out_ext_ready : ( - (pd_dest == PD_DEST_CPU)? pd_out_cpu_ready : ( - (pd_dest == PD_DEST_BOF)? pd_out_bof_ready : ( - (pd_dest == PD_DEST_CTL)? pd_out_ctl_ready : ( - 1'b0))))); - - //Always connected output data lines. - assign pd_out_dsp_data = pd_out_data; - assign pd_out_ext_data = pd_out_data; - assign pd_out_cpu_data = pd_out_data; - assign pd_out_bof_data = pd_out_data; - assign pd_out_ctl_data = pd_out_data; - - //Destination output valid signals: - //Comes from inspector valid when destination is selected, and otherwise low. - assign pd_out_dsp_valid = (pd_dest == PD_DEST_DSP)? pd_out_valid : 1'b0; - assign pd_out_ext_valid = (pd_dest == PD_DEST_EXT)? pd_out_valid : 1'b0; - assign pd_out_cpu_valid = (pd_dest == PD_DEST_CPU)? pd_out_valid : 1'b0; - assign pd_out_bof_valid = (pd_dest == PD_DEST_BOF)? pd_out_valid : 1'b0; - assign pd_out_ctl_valid = (pd_dest == PD_DEST_CTL)? pd_out_valid : 1'b0; - - //The communication inspector ouput ready signal: - //Always ready when storing to data registers, - //comes from inspector ready output when live, - //and otherwise low. - assign com_inp_ready = - (pd_state == PD_STATE_READ_COM_PRE) ? 1'b1 : ( - (pd_state == PD_STATE_READ_COM) ? 1'b1 : ( - (pd_state == PD_STATE_WRITE_LIVE) ? pd_out_ready : ( - 1'b0))); - - //inspect the incoming data and mark register booleans - always @(posedge clk) - if (com_inp_ready & com_inp_valid) begin - case(pd_dreg_count) - 0: begin - is_eth_dst_mac_bcast <= (com_inp_data[15:0] == 16'hffff); - end - 1: begin - is_eth_dst_mac_bcast <= is_eth_dst_mac_bcast && (com_inp_data[31:0] == 32'hffffffff); - end - 3: begin - is_eth_type_ipv4 <= (com_inp_data[15:0] == 16'h800); - end - 6: begin - is_eth_ipv4_proto_udp <= (com_inp_data[23:16] == 8'h11); - end - 8: begin - is_eth_ipv4_dst_addr_here <= (com_inp_data[31:0] == my_ip_addr); - end - 9: begin - is_eth_udp_dsp_port_here <= (com_inp_data[15:0] == dsp_udp_port); - is_eth_udp_ctl_port_here <= (com_inp_data[15:0] == ctl_udp_port); - end - endcase //pd_dreg_count - end - - always @(posedge clk) - if(rst | clr) begin - pd_state <= PD_STATE_READ_COM_PRE; - pd_dreg_count <= 0; - end - else begin - case(pd_state) - PD_STATE_READ_COM_PRE: begin - if (com_inp_ready & com_inp_valid & com_inp_data[32]) begin - pd_state <= PD_STATE_READ_COM; - pd_dreg_count <= pd_dreg_count_next; - pd_dregs[pd_dreg_count] <= com_inp_data; - end - end - - PD_STATE_READ_COM: begin - if (com_inp_ready & com_inp_valid) begin - pd_dregs[pd_dreg_count] <= com_inp_data; - if (pd_dreg_counter_done | com_inp_data[33]) begin - pd_state <= PD_STATE_WRITE_REGS; - pd_dreg_count <= 0; - - //---------- begin inspection decision -----------// - //EOF or bcast or not IPv4 or not UDP: - if ( - com_inp_data[33] || is_eth_dst_mac_bcast || - ~is_eth_type_ipv4 || ~is_eth_ipv4_proto_udp - ) begin - pd_dest <= PD_DEST_BOF; - end - - //not my IP address: - else if (~is_eth_ipv4_dst_addr_here) begin - pd_dest <= PD_DEST_EXT; - end - - //UDP control port and VRT: - else if (is_eth_udp_ctl_port_here && ~is_vrt_size_zero) begin - pd_dest <= PD_DEST_CTL; - pd_dreg_count <= PD_DREGS_DSP_OFFSET; - end - - //UDP data port and VRT: - else if (is_eth_udp_dsp_port_here && ~is_vrt_size_zero) begin - pd_dest <= PD_DEST_DSP; - pd_dreg_count <= PD_DREGS_DSP_OFFSET; - end - - //other: - else begin - pd_dest <= PD_DEST_CPU; - end - //---------- end inspection decision -------------// - - end - else begin - pd_dreg_count <= pd_dreg_count_next; - end - end - end - - PD_STATE_WRITE_REGS: begin - if (pd_out_ready & pd_out_valid) begin - if (pd_out_data[33]) begin - pd_state <= PD_STATE_READ_COM_PRE; - pd_dreg_count <= 0; - end - else if (pd_dreg_counter_done) begin - pd_state <= PD_STATE_WRITE_LIVE; - pd_dreg_count <= 0; - end - else begin - pd_dreg_count <= pd_dreg_count_next; - end - end - end - - PD_STATE_WRITE_LIVE: begin - if (pd_out_ready & pd_out_valid & pd_out_data[33]) begin - pd_state <= PD_STATE_READ_COM_PRE; - end - end - - endcase //pd_state - end - - //connect this fast-path signals directly to the DSP out - assign dsp_out_data = pd_out_dsp_data; - assign dsp_out_valid = pd_out_dsp_valid; - assign pd_out_dsp_ready = dsp_out_ready; - - assign ctl_out_data = pd_out_ctl_data; - assign ctl_out_valid = pd_out_ctl_valid; - assign pd_out_ctl_ready = ctl_out_ready; - - //////////////////////////////////////////////////////////////////// - // Splitter and output muxes for the bof packets - // - split the bof packets into two streams - // - mux split packets into cpu out and ext out - //////////////////////////////////////////////////////////////////// - - //dummy signals to join the the splitter and muxes below - wire [35:0] _split_to_ext_data, _split_to_cpu_data; - wire _split_to_ext_valid, _split_to_cpu_valid; - wire _split_to_ext_ready, _split_to_cpu_ready; - - splitter36 bof_out_splitter( - .clk(clk), .rst(rst), .clr(clr), - .inp_data(pd_out_bof_data), .inp_valid(pd_out_bof_valid), .inp_ready(pd_out_bof_ready), - .out0_data(_split_to_ext_data), .out0_valid(_split_to_ext_valid), .out0_ready(_split_to_ext_ready), - .out1_data(_split_to_cpu_data), .out1_valid(_split_to_cpu_valid), .out1_ready(_split_to_cpu_ready) - ); - - fifo36_mux ext_out_mux( - .clk(clk), .reset(rst), .clear(clr), - .data0_i(pd_out_ext_data), .src0_rdy_i(pd_out_ext_valid), .dst0_rdy_o(pd_out_ext_ready), - .data1_i(_split_to_ext_data), .src1_rdy_i(_split_to_ext_valid), .dst1_rdy_o(_split_to_ext_ready), - .data_o(ext_out_data), .src_rdy_o(ext_out_valid), .dst_rdy_i(ext_out_ready) - ); - - fifo36_mux cpu_out_mux( - .clk(clk), .reset(rst), .clear(clr), - .data0_i(pd_out_cpu_data), .src0_rdy_i(pd_out_cpu_valid), .dst0_rdy_o(pd_out_cpu_ready), - .data1_i(_split_to_cpu_data), .src1_rdy_i(_split_to_cpu_valid), .dst1_rdy_o(_split_to_cpu_ready), - .data_o(cpu_out_data), .src_rdy_o(cpu_out_valid), .dst_rdy_i(cpu_out_ready) - ); - -endmodule // packet_dispatcher36_x3 diff --git a/fpga/usrp2/fifo/packet_generator.v b/fpga/usrp2/fifo/packet_generator.v deleted file mode 100644 index 5e9d3c2ab..000000000 --- a/fpga/usrp2/fifo/packet_generator.v +++ /dev/null @@ -1,100 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module packet_generator - (input clk, input reset, input clear, - output reg [7:0] data_o, output sof_o, output eof_o, - input [127:0] header, - output src_rdy_o, input dst_rdy_i); - - localparam len = 32'd2000; - - reg [31:0] state; - reg [31:0] seq; - reg [31:0] crc_out; - wire calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF); - - - always @(posedge clk) - if(reset | clear) - seq <= 0; - else - if(eof_o & src_rdy_o & dst_rdy_i) - seq <= seq + 1; - - always @(posedge clk) - if(reset | clear) - state <= 0; - else - if(src_rdy_o & dst_rdy_i) - if(state == (len - 1)) - state <= 32'hFFFF_FFFC; - else - state <= state + 1; - - always @* - case(state) - 0 : data_o <= len[31:24]; - 1 : data_o <= len[23:16]; - 2 : data_o <= len[15:8]; - 3 : data_o <= len[7:0]; - 4 : data_o <= seq[31:24]; - 5 : data_o <= seq[23:16]; - 6 : data_o <= seq[15:8]; - 7 : data_o <= seq[7:0]; - 8 : data_o <= header[7:0]; - 9 : data_o <= header[15:8]; - 10 : data_o <= header[23:16]; - 11 : data_o <= header[31:24]; - 12 : data_o <= header[39:32]; - 13 : data_o <= header[47:40]; - 14 : data_o <= header[55:48]; - 15 : data_o <= header[63:56]; - 16 : data_o <= header[71:64]; - 17 : data_o <= header[79:72]; - 18 : data_o <= header[87:80]; - 19 : data_o <= header[95:88]; - 20 : data_o <= header[103:96]; - 21 : data_o <= header[111:104]; - 22 : data_o <= header[119:112]; - 23 : data_o <= header[127:120]; - - 32'hFFFF_FFFC : data_o <= crc_out[31:24]; - 32'hFFFF_FFFD : data_o <= crc_out[23:16]; - 32'hFFFF_FFFE : data_o <= crc_out[15:8]; - 32'hFFFF_FFFF : data_o <= crc_out[7:0]; - default : data_o <= state[7:0]; - endcase // case (state) - - assign src_rdy_o = 1; - assign sof_o = (state == 0); - assign eof_o = (state == 32'hFFFF_FFFF); - - wire clear_crc = eof_o & src_rdy_o & dst_rdy_i; - -// crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o), -// .calc(calc_crc), .crc_out(crc_out), .match()); - always @(posedge clk) - if(reset | clear | clear_crc) - crc_out <= 0; - else - if(calc_crc) - crc_out <= crc_out + data_o; - -endmodule // packet_generator diff --git a/fpga/usrp2/fifo/packet_generator32.v b/fpga/usrp2/fifo/packet_generator32.v deleted file mode 100644 index 7b4e3bd57..000000000 --- a/fpga/usrp2/fifo/packet_generator32.v +++ /dev/null @@ -1,40 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module packet_generator32 - (input clk, input reset, input clear, - input [127:0] header, - output [35:0] data_o, output src_rdy_o, input dst_rdy_i); - - wire [7:0] ll_data; - wire ll_sof, ll_eof, ll_src_rdy, ll_dst_rdy_n; - - packet_generator pkt_gen - (.clk(clk), .reset(reset), .clear(clear), - .data_o(ll_data), .sof_o(ll_sof), .eof_o(ll_eof), - .header(header), - .src_rdy_o(ll_src_rdy), .dst_rdy_i(~ll_dst_rdy_n)); - - ll8_to_fifo36 ll8_to_f36 - (.clk(clk), .reset(reset), .clear(clear), - .ll_data(ll_data), .ll_sof_n(~ll_sof), .ll_eof_n(~ll_eof), - .ll_src_rdy_n(~ll_src_rdy), .ll_dst_rdy_n(ll_dst_rdy_n), - .f36_data(data_o), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i)); - -endmodule // packet_generator32 diff --git a/fpga/usrp2/fifo/packet_padder36.v b/fpga/usrp2/fifo/packet_padder36.v deleted file mode 100644 index 6ded38781..000000000 --- a/fpga/usrp2/fifo/packet_padder36.v +++ /dev/null @@ -1,155 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// The packet padder 36 for use with RX VITA stream output. -// Packet padder understands the concept of USB LUTs, -// and will forward packets through the interface, -// adding zero padding as needed to properly flush. -// The padder will never write a packet across a LUT boundary. -// When flushing, padder writes out zeros until the LUT boundary. -// Requires that the input line0 be a VITA header, and SOF set. -// Flush when the LUT is partially filled and timeout is reached, -// or when the LUT is partially filled and the DSP is inactive. - -module packet_padder36 -#( - parameter BASE = 0, - - //default is 16K LUT - parameter DEFAULT_LINES32 = 4096, - - //default about 1ms at 64MHz clock - parameter DEFAULT_IDLE_CYC = 65536 -) -( - input clk, input reset, - - //setting bus - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - //input interface - input [35:0] data_i, - input src_rdy_i, - output dst_rdy_o, - - //output interface - output [35:0] data_o, - output src_rdy_o, - input dst_rdy_i, - - input always_flush -); - - wire lut_lines_changed; - wire [15:0] max_lut_lines32; - setting_reg #(.my_addr(BASE+0),.width(16),.at_reset(DEFAULT_LINES32)) sr_num_lines( - .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data), - .out(max_lut_lines32),.changed(lut_lines_changed)); - - wire idle_cyc_changed; - wire [17:0] idle_flush_cycles; - setting_reg #(.my_addr(BASE+1),.width(18),.at_reset(DEFAULT_IDLE_CYC)) sr_flush_cyc( - .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data), - .out(idle_flush_cycles),.changed(idle_cyc_changed)); - - //state machine definitions - localparam STATE_READ_HDR = 0; - localparam STATE_WRITE_HDR = 1; - localparam STATE_FORWARD = 2; - localparam STATE_WRITE_PAD = 3; - reg [1:0] state; - - //keep track of the outgoing lines - reg [15:0] line_count; - wire line_count_done = line_count == 1; - wire lut_is_empty = line_count == max_lut_lines32; - always @(posedge clk) begin - if (reset || lut_lines_changed) begin - line_count <= max_lut_lines32; - end - else if (src_rdy_o && dst_rdy_i) begin - line_count <= (line_count_done)? max_lut_lines32 : line_count - 1; - end - end - - //count the number of cycles since RX data so we can force a flush - reg [17:0] non_rx_cycles; - wire idle_timeout = (non_rx_cycles == idle_flush_cycles); - always @(posedge clk) begin - if(reset || state != STATE_READ_HDR || idle_cyc_changed) begin - non_rx_cycles <= 0; - end - else if (~idle_timeout) begin - non_rx_cycles <= non_rx_cycles + 1; - end - end - - //flush when we have written data to a LUT and either idle or non active DSP - wire force_flush = ~lut_is_empty && (idle_timeout || always_flush); - - //the padding state machine - reg [31:0] vita_hdr; - reg has_vita_hdr; - always @(posedge clk) begin - if (reset) begin - state <= STATE_READ_HDR; - end - else case(state) - - STATE_READ_HDR: begin - if (src_rdy_i && dst_rdy_o && data_i[32]) begin - vita_hdr <= data_i[31:0]; - has_vita_hdr <= 1; - state <= (data_i[15:0] > line_count)? STATE_WRITE_PAD : STATE_WRITE_HDR; - end - else if (force_flush) begin - has_vita_hdr <= 0; - state <= STATE_WRITE_PAD; - end - end - - STATE_WRITE_HDR: begin - if (src_rdy_o && dst_rdy_i) begin - state <= STATE_FORWARD; - end - end - - STATE_FORWARD: begin - if (src_rdy_i && dst_rdy_o && data_i[33]) begin - state <= STATE_READ_HDR; - end - end - - STATE_WRITE_PAD: begin - if (src_rdy_o && dst_rdy_i && line_count_done) begin - state <= (has_vita_hdr)? STATE_WRITE_HDR : STATE_READ_HDR; - end - end - - endcase //state - end - - //assign outgoing signals - assign dst_rdy_o = (state == STATE_READ_HDR)? 1 : ((state == STATE_FORWARD)? dst_rdy_i : 0); - assign src_rdy_o = (state == STATE_WRITE_HDR || state == STATE_WRITE_PAD)? 1 : ((state == STATE_FORWARD )? src_rdy_i : 0); - assign data_o = (state == STATE_WRITE_HDR)? {4'b0001, vita_hdr} : ((state == STATE_FORWARD)? data_i : 0); - -endmodule // packet_padder36 - - - - diff --git a/fpga/usrp2/fifo/packet_router.v b/fpga/usrp2/fifo/packet_router.v deleted file mode 100644 index 4c0fe14b1..000000000 --- a/fpga/usrp2/fifo/packet_router.v +++ /dev/null @@ -1,326 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module packet_router - #( - parameter BUF_SIZE = 9, - parameter UDP_BASE = 0, - parameter CTRL_BASE = 0 - ) - ( - //wishbone interface for memory mapped CPU frames - input wb_clk_i, - input wb_rst_i, - input wb_we_i, - input wb_stb_i, - input [15:0] wb_adr_i, - input [31:0] wb_dat_i, - output [31:0] wb_dat_o, - output wb_ack_o, - output wb_err_o, - output wb_rty_o, - - //setting register interface - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - input stream_clk, - input stream_rst, - input stream_clr, - - //output status register - output [31:0] status, - - output sys_int_o, //want an interrupt? - - output [31:0] debug, - - // Input Interfaces (in to router) - input [35:0] ser_inp_data, input ser_inp_valid, output ser_inp_ready, - input [35:0] dsp0_inp_data, input dsp0_inp_valid, output dsp0_inp_ready, - input [35:0] dsp1_inp_data, input dsp1_inp_valid, output dsp1_inp_ready, - input [35:0] eth_inp_data, input eth_inp_valid, output eth_inp_ready, - input [35:0] err_inp_data, input err_inp_valid, output err_inp_ready, - input [35:0] ctl_inp_data, input ctl_inp_valid, output ctl_inp_ready, - - // Output Interfaces (out of router) - output [35:0] ser_out_data, output ser_out_valid, input ser_out_ready, - output [35:0] dsp_out_data, output dsp_out_valid, input dsp_out_ready, - output [35:0] ctl_out_data, output ctl_out_valid, input ctl_out_ready, - output [35:0] eth_out_data, output eth_out_valid, input eth_out_ready - ); - - assign wb_err_o = 1'b0; // Unused for now - assign wb_rty_o = 1'b0; // Unused for now - - //////////////////////////////////////////////////////////////////// - // CPU interface to this packet router - //////////////////////////////////////////////////////////////////// - wire [35:0] cpu_inp_data, cpu_out_data; - wire cpu_inp_valid, cpu_out_valid; - wire cpu_inp_ready, cpu_out_ready; - - //////////////////////////////////////////////////////////////////// - // Communication interfaces - //////////////////////////////////////////////////////////////////// - wire [35:0] com_inp_data, com_out_data, udp_out_data; - wire com_inp_valid, com_out_valid, udp_out_valid; - wire com_inp_ready, com_out_ready, udp_out_ready; - - //////////////////////////////////////////////////////////////////// - // Control signals (setting registers and status signals) - // - handshake lines for the CPU communication - // - setting registers to program the inspector - //////////////////////////////////////////////////////////////////// - - //setting register for mode control - wire [31:0] _sreg_mode_ctrl; - wire master_mode_flag; - - setting_reg #(.my_addr(CTRL_BASE+0), .width(1)) sreg_mode_ctrl( - .clk(stream_clk),.rst(stream_rst), - .strobe(set_stb),.addr(set_addr),.in(set_data), - .out(master_mode_flag),.changed() - ); - - //assign status output signals - wire [31:0] cpu_iface_status; - assign status = { - cpu_iface_status[31:9], master_mode_flag, cpu_iface_status[7:0] - }; - - //////////////////////////////////////////////////////////////////// - // Communication input source crossbar - // When in master mode: - // - serdes input -> comm output combiner - // - ethernet input -> comm input inspector - // When in slave mode: - // - serdes input -> comm input inspector - // - ethernet input -> null sink - //////////////////////////////////////////////////////////////////// - - //streaming signals from the crossbar to the combiner - wire [35:0] ext_inp_data; - wire ext_inp_valid; - wire ext_inp_ready; - - //dummy signals for valve/xbar below - wire [35:0] _eth_inp_data; - wire _eth_inp_valid; - wire _eth_inp_ready; - - // dummy signals to connect fifo_short - wire [35:0] _com_inp_data; - wire _com_inp_valid; - wire _com_inp_ready; - - valve36 eth_inp_valve ( - .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .shutoff(~master_mode_flag), - .data_i(eth_inp_data), .src_rdy_i(eth_inp_valid), .dst_rdy_o(eth_inp_ready), - .data_o(_eth_inp_data), .src_rdy_o(_eth_inp_valid), .dst_rdy_i(_eth_inp_ready) - ); - - crossbar36 com_inp_xbar ( - .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .cross(~master_mode_flag), - .data0_i(_eth_inp_data), .src0_rdy_i(_eth_inp_valid), .dst0_rdy_o(_eth_inp_ready), - .data1_i(ser_inp_data), .src1_rdy_i(ser_inp_valid), .dst1_rdy_o(ser_inp_ready), - .data0_o(_com_inp_data), .src0_rdy_o(_com_inp_valid), .dst0_rdy_i(_com_inp_ready), - .data1_o(ext_inp_data), .src1_rdy_o(ext_inp_valid), .dst1_rdy_i(ext_inp_ready) - ); - - // short fifo in the packet inspection path to help timing - fifo_short #(.WIDTH(36)) com_inp_fifo - (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .datain(_com_inp_data), .src_rdy_i(_com_inp_valid), .dst_rdy_o(_com_inp_ready), - .dataout(com_inp_data), .src_rdy_o(com_inp_valid), .dst_rdy_i(com_inp_ready), - .space(), .occupied() ); - - //////////////////////////////////////////////////////////////////// - // Communication output sink crossbar - // When in master mode: - // - comm output -> ethernet output - // - insp output -> serdes output - // When in slave mode: - // - com output -> serdes output - // - insp output -> null sink - //////////////////////////////////////////////////////////////////// - - //streaming signals from the inspector to the crossbar - wire [35:0] ext_out_data; - wire ext_out_valid; - wire ext_out_ready; - - //dummy signals for valve/xbar below - wire [35:0] _eth_out_data; - wire _eth_out_valid; - wire _eth_out_ready; - - crossbar36 com_out_xbar ( - .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .cross(~master_mode_flag), - .data0_i(com_out_data), .src0_rdy_i(com_out_valid), .dst0_rdy_o(com_out_ready), - .data1_i(ext_out_data), .src1_rdy_i(ext_out_valid), .dst1_rdy_o(ext_out_ready), - .data0_o(_eth_out_data), .src0_rdy_o(_eth_out_valid), .dst0_rdy_i(_eth_out_ready), - .data1_o(ser_out_data), .src1_rdy_o(ser_out_valid), .dst1_rdy_i(ser_out_ready) - ); - - valve36 eth_out_valve ( - .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .shutoff(~master_mode_flag), - .data_i(_eth_out_data), .src_rdy_i(_eth_out_valid), .dst_rdy_o(_eth_out_ready), - .data_o(eth_out_data), .src_rdy_o(eth_out_valid), .dst_rdy_i(eth_out_ready) - ); - - //////////////////////////////////////////////////////////////////// - // Communication output source combiner (feeds UDP proto machine) - // - DSP input - // - CPU input - // - ERR input - //////////////////////////////////////////////////////////////////// - - //dummy signals to join the the muxes below - wire [35:0] _combiner0_data, _combiner1_data, _combiner2_data; - wire _combiner0_valid, _combiner1_valid, _combiner2_valid; - wire _combiner0_ready, _combiner1_ready, _combiner2_ready; - - fifo36_mux #(.prio(0)) // No priority, fair sharing - _com_output_combiner0( - .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .data0_i(err_inp_data), .src0_rdy_i(err_inp_valid), .dst0_rdy_o(err_inp_ready), - .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready), - .data_o(_combiner0_data), .src_rdy_o(_combiner0_valid), .dst_rdy_i(_combiner0_ready) - ); - - fifo36_mux #(.prio(0)) // No priority, fair sharing - _com_output_combiner2( - .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .data0_i(_combiner0_data), .src0_rdy_i(_combiner0_valid), .dst0_rdy_o(_combiner0_ready), - .data1_i(ctl_inp_data), .src1_rdy_i(ctl_inp_valid), .dst1_rdy_o(ctl_inp_ready), - .data_o(_combiner2_data), .src_rdy_o(_combiner2_valid), .dst_rdy_i(_combiner2_ready) - ); - - fifo36_mux #(.prio(0)) // No priority, fair sharing - _com_output_combiner1( - .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .data0_i(dsp0_inp_data), .src0_rdy_i(dsp0_inp_valid), .dst0_rdy_o(dsp0_inp_ready), - .data1_i(dsp1_inp_data), .src1_rdy_i(dsp1_inp_valid), .dst1_rdy_o(dsp1_inp_ready), - .data_o(_combiner1_data), .src_rdy_o(_combiner1_valid), .dst_rdy_i(_combiner1_ready) - ); - - fifo36_mux #(.prio(1)) // Give priority to err/cpu over dsp - com_output_source( - .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .data0_i(_combiner2_data), .src0_rdy_i(_combiner2_valid), .dst0_rdy_o(_combiner2_ready), - .data1_i(_combiner1_data), .src1_rdy_i(_combiner1_valid), .dst1_rdy_o(_combiner1_ready), - .data_o(udp_out_data), .src_rdy_o(udp_out_valid), .dst_rdy_i(udp_out_ready) - ); - - //////////////////////////////////////////////////////////////////// - // Interface CPU to memory mapped wishbone - // - Uses 1 setting register - //////////////////////////////////////////////////////////////////// - buffer_int2 #(.BASE(CTRL_BASE+3), .BUF_SIZE(BUF_SIZE)) cpu_to_wb( - .clk(stream_clk), .rst(stream_rst | stream_clr), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .status(cpu_iface_status), - // Wishbone interface to RAM - .wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i), - .wb_we_i(wb_we_i), .wb_stb_i(wb_stb_i), - .wb_adr_i(wb_adr_i), .wb_dat_i(wb_dat_i), - .wb_dat_o(wb_dat_o), .wb_ack_o(wb_ack_o), - // Write FIFO Interface (from PR and into WB) - .wr_data_i(cpu_out_data), - .wr_ready_i(cpu_out_valid), - .wr_ready_o(cpu_out_ready), - // Read FIFO Interface (from WB and into PR) - .rd_data_o(cpu_inp_data), - .rd_ready_o(cpu_inp_valid), - .rd_ready_i(cpu_inp_ready) - ); - - //////////////////////////////////////////////////////////////////// - // Packet Dispatcher - // - Uses 2 setting registers - // - provide buffering before cpu for random + small packet bursts - //////////////////////////////////////////////////////////////////// - wire [35:0] _cpu_out_data; - wire _cpu_out_valid; - wire _cpu_out_ready; - - packet_dispatcher36_x4 #(.BASE(CTRL_BASE+1)) packet_dispatcher( - .clk(stream_clk), .rst(stream_rst), .clr(stream_clr), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .com_inp_data(com_inp_data), .com_inp_valid(com_inp_valid), .com_inp_ready(com_inp_ready), - .ext_out_data(ext_out_data), .ext_out_valid(ext_out_valid), .ext_out_ready(ext_out_ready), - .dsp_out_data(dsp_out_data), .dsp_out_valid(dsp_out_valid), .dsp_out_ready(dsp_out_ready), - .ctl_out_data(ctl_out_data), .ctl_out_valid(ctl_out_valid), .ctl_out_ready(ctl_out_ready), - .cpu_out_data(_cpu_out_data), .cpu_out_valid(_cpu_out_valid), .cpu_out_ready(_cpu_out_ready) - ); - - fifo_cascade #(.WIDTH(36), .SIZE(9/*512 lines plenty for short pkts*/)) cpu_out_fifo ( - .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .datain(_cpu_out_data), .src_rdy_i(_cpu_out_valid), .dst_rdy_o(_cpu_out_ready), - .dataout(cpu_out_data), .src_rdy_o(cpu_out_valid), .dst_rdy_i(cpu_out_ready) - ); - - //////////////////////////////////////////////////////////////////// - // UDP TX Protocol machine - //////////////////////////////////////////////////////////////////// - - //dummy signals to connect the components below - wire [35:0] _com_out_data; - wire _com_out_valid, _com_out_ready; - - prot_eng_tx #(.BASE(UDP_BASE)) udp_prot_eng_tx - (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .datain(udp_out_data), .src_rdy_i(udp_out_valid), .dst_rdy_o(udp_out_ready), - .dataout(_com_out_data), .src_rdy_o(_com_out_valid), .dst_rdy_i(_com_out_ready) ); - - fifo36_mux com_out_mux( - .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .data0_i(ext_inp_data), .src0_rdy_i(ext_inp_valid), .dst0_rdy_o(ext_inp_ready), - .data1_i(_com_out_data), .src1_rdy_i(_com_out_valid), .dst1_rdy_o(_com_out_ready), - .data_o(com_out_data), .src_rdy_o(com_out_valid), .dst_rdy_i(com_out_ready) - ); - - //////////////////////////////////////////////////////////////////// - // Assign debugs - //////////////////////////////////////////////////////////////////// - - assign debug = { - //inputs to the router (12) - dsp0_inp_ready, dsp0_inp_valid, - dsp1_inp_ready, dsp1_inp_valid, - err_inp_ready, err_inp_valid, - ser_inp_ready, ser_inp_valid, - eth_inp_ready, eth_inp_valid, - cpu_inp_ready, cpu_inp_valid, - - //outputs from the router (8) - dsp_out_ready, dsp_out_valid, - ser_out_ready, ser_out_valid, - eth_out_ready, eth_out_valid, - cpu_out_ready, cpu_out_valid, - - //other interfaces (8) - ext_inp_ready, ext_inp_valid, - com_out_ready, com_out_valid, - ext_out_ready, ext_out_valid, - com_inp_ready, com_inp_valid, - - 4'b0 - }; - -endmodule // packet_router diff --git a/fpga/usrp2/fifo/packet_tb.v b/fpga/usrp2/fifo/packet_tb.v deleted file mode 100644 index ec0665e0a..000000000 --- a/fpga/usrp2/fifo/packet_tb.v +++ /dev/null @@ -1,46 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module packet_tb(); - - wire [7:0] data; - wire sof, eof, src_rdy, dst_rdy; - - wire clear = 0; - reg clk = 0; - reg reset = 1; - - always #10 clk <= ~clk; - initial #1000 reset <= 0; - - initial $dumpfile("packet_tb.vcd"); - initial $dumpvars(0,packet_tb); - - wire [31:0] total, crc_err, seq_err, len_err; - - packet_generator pkt_gen (.clk(clk), .reset(reset), .clear(clear), - .data_o(data), .sof_o(sof), .eof_o(eof), - .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); - - packet_verifier pkt_ver (.clk(clk), .reset(reset), .clear(clear), - .data_i(data), .sof_i(sof), .eof_i(eof), - .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), - .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); - -endmodule // packet_tb diff --git a/fpga/usrp2/fifo/packet_verifier.v b/fpga/usrp2/fifo/packet_verifier.v deleted file mode 100644 index 3cc7b0a04..000000000 --- a/fpga/usrp2/fifo/packet_verifier.v +++ /dev/null @@ -1,78 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -// Packet format -- -// Line 1 -- Length, 32 bits -// Line 2 -- Sequence number, 32 bits -// Last line -- CRC, 32 bits - -module packet_verifier - (input clk, input reset, input clear, - input [7:0] data_i, input sof_i, input eof_i, input src_rdy_i, output dst_rdy_o, - - output reg [31:0] total, - output reg [31:0] crc_err, - output reg [31:0] seq_err, - output reg [31:0] len_err); - - reg [31:0] seq_num; - reg [31:0] length; - wire first_byte, last_byte; - reg second_byte, last_byte_d1; - wire match_crc; - wire calc_crc = src_rdy_i & dst_rdy_o; - - crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), - .calc(calc_crc), .crc_out(), .match(match_crc)); - - assign first_byte = src_rdy_i & dst_rdy_o & sof_i; - assign last_byte = src_rdy_i & dst_rdy_o & eof_i; - assign dst_rdy_o = ~last_byte_d1; - - // stubs for now - wire match_seq = 1; - wire match_len = 1; - - always @(posedge clk) - if(reset | clear) - last_byte_d1 <= 0; - else - last_byte_d1 <= last_byte; - - always @(posedge clk) - if(reset | clear) - begin - total <= 0; - crc_err <= 0; - seq_err <= 0; - len_err <= 0; - end - else - if(last_byte_d1) - begin - total <= total + 1; - if(~match_crc) - crc_err <= crc_err + 1; - else if(~match_seq) - seq_err <= seq_err + 1; - else if(~match_len) - seq_err <= len_err + 1; - end - -endmodule // packet_verifier diff --git a/fpga/usrp2/fifo/packet_verifier32.v b/fpga/usrp2/fifo/packet_verifier32.v deleted file mode 100644 index 3579a9bcf..000000000 --- a/fpga/usrp2/fifo/packet_verifier32.v +++ /dev/null @@ -1,40 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module packet_verifier32 - (input clk, input reset, input clear, - input [35:0] data_i, input src_rdy_i, output dst_rdy_o, - output [31:0] total, output [31:0] crc_err, output [31:0] seq_err, output [31:0] len_err); - - wire [7:0] ll_data; - wire ll_sof, ll_eof, ll_src_rdy, ll_dst_rdy; - - fifo36_to_ll8 f36_to_ll8 - (.clk(clk), .reset(reset), .clear(clear), - .f36_data(data_i), .f36_src_rdy_i(src_rdy_i), .f36_dst_rdy_o(dst_rdy_o), - .ll_data(ll_data), .ll_sof(ll_sof), .ll_eof(ll_eof), - .ll_src_rdy(ll_src_rdy), .ll_dst_rdy(ll_dst_rdy)); - - packet_verifier pkt_ver - (.clk(clk), .reset(reset), .clear(clear), - .data_i(ll_data), .sof_i(ll_sof), .eof_i(ll_eof), - .src_rdy_i(ll_src_rdy), .dst_rdy_o(ll_dst_rdy), - .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); - -endmodule // packet_verifier32 diff --git a/fpga/usrp2/fifo/resp_packet_padder36.v b/fpga/usrp2/fifo/resp_packet_padder36.v deleted file mode 100644 index 18fc18291..000000000 --- a/fpga/usrp2/fifo/resp_packet_padder36.v +++ /dev/null @@ -1,88 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// PAD to NUM LINES - -module resp_packet_padder36 -#( - parameter NUM_LINES32 = 128 -) -( - input clk, input reset, - - //input interface - input [35:0] data_i, - input src_rdy_i, - output dst_rdy_o, - - //output interface - output [35:0] data_o, - output src_rdy_o, - input dst_rdy_i -); - - localparam STATE_FWD = 0; - localparam STATE_PAD = 1; - reg state; - - reg [15:0] counter; - - always @(posedge clk) begin - if (reset) begin - counter <= 0; - end - else if (src_rdy_o && dst_rdy_i) begin - if (data_o[33]) counter <= 0; - else counter <= counter + 1; - end - end - - always @(posedge clk) begin - if (reset) begin - state <= STATE_FWD; - end - else case(state) - - STATE_FWD: begin - if (src_rdy_i && dst_rdy_o && data_i[33] && ~data_o[33]) begin - state <= STATE_PAD; - end - end - - STATE_PAD: begin - if (src_rdy_o && dst_rdy_i && data_o[33]) begin - state <= STATE_FWD; - end - end - - endcase //state - end - - //assign data out - assign data_o[31:0] = (state == STATE_FWD)? data_i[31:0] : {32'b0}; - wire eof = (counter == (NUM_LINES32-1)); - assign data_o[35:32] = {data_i[35:34], eof, data_i[32]}; - - //assign ready - assign src_rdy_o = (state == STATE_FWD)? src_rdy_i : 1'b1; - assign dst_rdy_o = (state == STATE_FWD)? dst_rdy_i : 1'b0; - -endmodule // resp_packet_padder36 - - - - diff --git a/fpga/usrp2/fifo/splitter36.v b/fpga/usrp2/fifo/splitter36.v deleted file mode 100644 index d002d7afd..000000000 --- a/fpga/usrp2/fifo/splitter36.v +++ /dev/null @@ -1,85 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Split packets from a fifo based interface so it goes out identically on two interfaces - -module splitter36 - ( - input clk, input rst, input clr, - input [35:0] inp_data, input inp_valid, output inp_ready, - output [35:0] out0_data, output out0_valid, input out0_ready, - output [35:0] out1_data, output out1_valid, input out1_ready - ); - - localparam STATE_COPY_BOTH = 0; - localparam STATE_COPY_ZERO = 1; - localparam STATE_COPY_ONE = 2; - - reg [1:0] state; - reg [35:0] data_reg; - - assign out0_data = (state == STATE_COPY_BOTH)? inp_data : data_reg; - assign out1_data = (state == STATE_COPY_BOTH)? inp_data : data_reg; - - assign out0_valid = - (state == STATE_COPY_BOTH)? inp_valid : ( - (state == STATE_COPY_ZERO)? 1'b1 : ( - 1'b0)); - - assign out1_valid = - (state == STATE_COPY_BOTH)? inp_valid : ( - (state == STATE_COPY_ONE)? 1'b1 : ( - 1'b0)); - - assign inp_ready = (state == STATE_COPY_BOTH)? (out0_ready | out1_ready) : 1'b0; - - always @(posedge clk) - if (rst | clr) begin - state <= STATE_COPY_BOTH; - end - else begin - case (state) - - STATE_COPY_BOTH: begin - if ((out0_valid & out0_ready) & ~(out1_valid & out1_ready)) begin - state <= STATE_COPY_ONE; - end - else if (~(out0_valid & out0_ready) & (out1_valid & out1_ready)) begin - state <= STATE_COPY_ZERO; - end - data_reg <= inp_data; - end - - STATE_COPY_ZERO: begin - if (out0_valid & out0_ready) begin - state <= STATE_COPY_BOTH; - end - end - - STATE_COPY_ONE: begin - if (out1_valid & out1_ready) begin - state <= STATE_COPY_BOTH; - end - end - - endcase //state - end - - - -endmodule //splitter36 diff --git a/fpga/usrp2/fifo/valve36.v b/fpga/usrp2/fifo/valve36.v deleted file mode 100644 index 795fe511e..000000000 --- a/fpga/usrp2/fifo/valve36.v +++ /dev/null @@ -1,46 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module valve36 - (input clk, input reset, input clear, - input shutoff, - input [35:0] data_i, input src_rdy_i, output dst_rdy_o, - output [35:0] data_o, output src_rdy_o, input dst_rdy_i); - - reg shutoff_int, active; - wire active_next = (src_rdy_i & dst_rdy_o)? ~data_i[33] : active; - - assign data_o = data_i; - - assign dst_rdy_o = shutoff_int ? 1'b1 : dst_rdy_i; - assign src_rdy_o = shutoff_int ? 1'b0 : src_rdy_i; - - always @(posedge clk) - if(reset | clear) - active <= 0; - else - active <= active_next; - - always @(posedge clk) - if(reset | clear) - shutoff_int <= 0; - else if(~active_next) - shutoff_int <= shutoff; - -endmodule // valve36 diff --git a/fpga/usrp2/gpif/.gitignore b/fpga/usrp2/gpif/.gitignore deleted file mode 100644 index 421b858b6..000000000 --- a/fpga/usrp2/gpif/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -fuse* -isim* -*_tb diff --git a/fpga/usrp2/gpif/Makefile.srcs b/fpga/usrp2/gpif/Makefile.srcs deleted file mode 100644 index 7909fb5ff..000000000 --- a/fpga/usrp2/gpif/Makefile.srcs +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright 2010-2012 Ettus Research LLC -# - -################################################## -# SERDES Sources -################################################## -GPIF_SRCS = $(abspath $(addprefix $(BASE_DIR)/../gpif/, \ -packet_reframer.v \ -slave_fifo.v \ -fifo36_to_gpmc16.v \ -gpmc16_to_fifo36.v \ -)) diff --git a/fpga/usrp2/gpif/fifo36_to_gpmc16.v b/fpga/usrp2/gpif/fifo36_to_gpmc16.v deleted file mode 100644 index 4b4dc3109..000000000 --- a/fpga/usrp2/gpif/fifo36_to_gpmc16.v +++ /dev/null @@ -1,71 +0,0 @@ -// -// Copyright 2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module fifo36_to_gpmc16 -#( - parameter FIFO_SIZE = 9, - - //not ready until minimum xfers of occupancy available - parameter MIN_OCC16 = 2 -) -( - //input fifo interface - input fifo_clk, input fifo_rst, - input [35:0] in_data, - input in_src_rdy, - output in_dst_rdy, - - //output interface - input gpif_clk, input gpif_rst, - output [15:0] out_data, - output valid, - input enable, - output eof, - output reg has_data -); - - wire [15:0] fifo_occ; - - always @(posedge gpif_clk) - has_data <= (fifo_occ >= MIN_OCC16); - - wire [35:0] data_int; - wire src_rdy_int, dst_rdy_int; - - fifo_2clock_cascade #(.WIDTH(36), .SIZE(6)) fifo_2clk - (.wclk(fifo_clk), .datain(in_data), .src_rdy_i(in_src_rdy), .dst_rdy_o(in_dst_rdy), .space(), - .rclk(gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(), - .arst(fifo_rst | gpif_rst)); - - wire [18:0] data19_int; - wire data19_src_rdy_int, data19_dst_rdy_int; - - fifo36_to_fifo19 #(.LE(1)) f36_to_f19 - (.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0), - .f36_datain(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int), - .f19_dataout(data19_int), .f19_src_rdy_o(data19_src_rdy_int), .f19_dst_rdy_i(data19_dst_rdy_int) ); - - wire [17:0] data18_int; - fifo_cascade #(.WIDTH(18), .SIZE(FIFO_SIZE+1)) occ_ctrl_fifo - (.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0), - .datain(data19_int[17:0]), .src_rdy_i(data19_src_rdy_int), .dst_rdy_o(data19_dst_rdy_int), .space(), - .dataout(data18_int), .src_rdy_o(valid), .dst_rdy_i(enable), .occupied(fifo_occ)); - - assign out_data = data18_int[15:0]; - assign eof = data18_int[17]; - -endmodule //fifo_to_gpmc16 diff --git a/fpga/usrp2/gpif/gpif.v b/fpga/usrp2/gpif/gpif.v deleted file mode 100644 index e5b63d5a3..000000000 --- a/fpga/usrp2/gpif/gpif.v +++ /dev/null @@ -1,185 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -////////////////////////////////////////////////////////////////////////////////// - -module gpif - #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11) - (// GPIF signals - input gpif_clk, input gpif_rst, - inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy, - output [2:0] gpif_misc, - - // Wishbone signals - input wb_clk, input wb_rst, - output [15:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, - output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, - input [7:0] triggers, - - // FIFO interface - input fifo_clk, input fifo_rst, input clear_tx, input clear_rx, - output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, - input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, - input [35:0] tx_err_data_i, input tx_err_src_rdy_i, output tx_err_dst_rdy_o, - - output tx_underrun, output rx_overrun, - input [7:0] frames_per_packet, - output [31:0] debug0, output [31:0] debug1 - ); - - assign tx_underrun = 0; - assign rx_overrun = 0; - - wire WR = gpif_ctl[0]; - wire RD = gpif_ctl[1]; - wire OE = gpif_ctl[2]; - wire EP = gpif_ctl[3]; - - wire CF, CE, DF, DE; - - assign gpif_rdy = { CF, CE, DF, DE }; - - wire [15:0] gpif_d_out; - assign gpif_d = OE ? gpif_d_out : 16'bz; - - wire [15:0] gpif_d_copy = gpif_d; - - wire [31:0] debug_rd, debug_wr, debug_split0, debug_split1; - - // //////////////////////////////////////////////////////////////////// - // TX Data Path - - wire [18:0] tx19_data; - wire tx19_src_rdy, tx19_dst_rdy; - wire [35:0] tx36_data; - wire tx36_src_rdy, tx36_dst_rdy; - - wire [18:0] ctrl_data; - wire ctrl_src_rdy, ctrl_dst_rdy; - - gpif_wr gpif_wr - (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), - .gpif_data(gpif_d), .gpif_wr(WR), .gpif_ep(EP), - .gpif_full_d(DF), .gpif_full_c(CF), - - .sys_clk(fifo_clk), .sys_rst(fifo_rst), - .data_o(tx19_data), .src_rdy_o(tx19_src_rdy), .dst_rdy_i(tx19_dst_rdy), - .ctrl_o(ctrl_data), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy), - .debug(debug_wr) ); - - // join vita packets which are longer than one frame, drop frame padding - wire [18:0] refr_data; - wire refr_src_rdy, refr_dst_rdy; - - packet_reframer tx_packet_reframer - (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), - .data_i(tx19_data), .src_rdy_i(tx19_src_rdy), .dst_rdy_o(tx19_dst_rdy), - .data_o(refr_data), .src_rdy_o(refr_src_rdy), .dst_rdy_i(refr_dst_rdy)); - - fifo19_to_fifo36 #(.LE(1)) f19_to_f36 - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .f19_datain(refr_data), .f19_src_rdy_i(refr_src_rdy), .f19_dst_rdy_o(refr_dst_rdy), - .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); - - fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 - (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), - .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy), - .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i)); - - // //////////////////////////////////////////// - // RX Data Path - - wire [35:0] rx36_data; - wire rx36_src_rdy, rx36_dst_rdy; - wire [18:0] rx19_data, splt_data; - wire rx19_src_rdy, rx19_dst_rdy, splt_src_rdy, splt_dst_rdy; - wire [18:0] resp_data, resp_int1, resp_int2; - wire resp_src_rdy, resp_dst_rdy; - wire resp_src_rdy_int1, resp_dst_rdy_int1, resp_src_rdy_int2, resp_dst_rdy_int2; - - fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 - (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), - .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), - .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); - - fifo36_to_fifo19 #(.LE(1)) f36_to_f19 - (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), - .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), - .f19_dataout(rx19_data), .f19_src_rdy_o(rx19_src_rdy), .f19_dst_rdy_i(rx19_dst_rdy) ); - - packet_splitter #(.FRAME_LEN(256)) packet_splitter - (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), - .frames_per_packet(frames_per_packet), - .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy), - .data_o(splt_data), .src_rdy_o(splt_src_rdy), .dst_rdy_i(splt_dst_rdy), - .debug0(debug_split0), .debug1(debug_split1)); - - gpif_rd gpif_rd - (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), - .gpif_data(gpif_d_out), .gpif_rd(RD), .gpif_ep(EP), - .gpif_empty_d(DE), .gpif_empty_c(CE), .gpif_flush(gpif_misc[0]), - - .sys_clk(fifo_clk), .sys_rst(fifo_rst), - .data_i(splt_data), .src_rdy_i(splt_src_rdy), .dst_rdy_o(splt_dst_rdy), - .resp_i(resp_data), .resp_src_rdy_i(resp_src_rdy), .resp_dst_rdy_o(resp_dst_rdy), - .debug(debug_rd) ); - - // //////////////////////////////////////////////////////////////////// - // FIFO to Wishbone interface - - fifo_to_wb fifo_to_wb - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .data_i(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy), - .data_o(resp_int1), .src_rdy_o(resp_src_rdy_int1), .dst_rdy_i(resp_dst_rdy_int1), - .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), .wb_sel_o(wb_sel_o), - .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i), - .triggers(triggers), - .debug0(), .debug1()); - - wire [18:0] tx_err19_data; - wire tx_err19_src_rdy, tx_err19_dst_rdy; - - fifo36_to_fifo19 #(.LE(1)) f36_to_f19_txerr - (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), - .f36_datain(tx_err_data_i), .f36_src_rdy_i(tx_err_src_rdy_i), .f36_dst_rdy_o(tx_err_dst_rdy_o), - .f19_dataout(tx_err19_data), .f19_src_rdy_o(tx_err19_src_rdy), .f19_dst_rdy_i(tx_err19_dst_rdy) ); - - fifo19_mux #(.prio(0)) mux_err_stream - (.clk(wb_clk), .reset(wb_rst), .clear(0), - .data0_i(resp_int1), .src0_rdy_i(resp_src_rdy_int1), .dst0_rdy_o(resp_dst_rdy_int1), - .data1_i(tx_err19_data), .src1_rdy_i(tx_err19_src_rdy), .dst1_rdy_o(tx_err19_dst_rdy), - .data_o(resp_int2), .src_rdy_o(resp_src_rdy_int2), .dst_rdy_i(resp_dst_rdy_int2)); - - fifo19_pad #(.LENGTH(16)) fifo19_pad - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .data_i(resp_int2), .src_rdy_i(resp_src_rdy_int2), .dst_rdy_o(resp_dst_rdy_int2), - .data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy)); - - // //////////////////////////////////////////// - // DEBUG - - //assign debug0 = { rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy, gpif_ctl[3:0], gpif_rdy[3:0], - // gpif_d_copy[15:0] }; - - //assign debug1 = { { debug_rd[15:8] }, - // { debug_rd[7:0] }, - // { rx_src_rdy_i, rx_dst_rdy_o, rx36_src_rdy, rx36_dst_rdy, rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy}, - // { tx_src_rdy_o, tx_dst_rdy_i, tx19_src_rdy, tx19_dst_rdy, tx36_src_rdy, tx36_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy} }; - - assign debug0 = { gpif_ctl[3:0], gpif_rdy[3:0], debug_split0[23:0] }; - assign debug1 = { gpif_misc[0], debug_rd[14:0], debug_split1[15:8], debug_split1[7:0] }; -endmodule // gpif diff --git a/fpga/usrp2/gpif/gpif_rd.v b/fpga/usrp2/gpif/gpif_rd.v deleted file mode 100644 index b05c3cfb6..000000000 --- a/fpga/usrp2/gpif/gpif_rd.v +++ /dev/null @@ -1,111 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module gpif_rd - (input gpif_clk, input gpif_rst, - output [15:0] gpif_data, input gpif_rd, input gpif_ep, - output reg gpif_empty_d, output reg gpif_empty_c, - output reg gpif_flush, - - input sys_clk, input sys_rst, - input [18:0] data_i, input src_rdy_i, output dst_rdy_o, - input [18:0] resp_i, input resp_src_rdy_i, output resp_dst_rdy_o, - output [31:0] debug - ); - - wire [18:0] data_o; // occ bit indicates flush - wire [17:0] resp_o; // no occ bit - wire final_rdy_data, final_rdy_resp; - - // 33/257 Bug Fix - reg [8:0] read_count; - always @(negedge gpif_clk) - if(gpif_rst) - read_count <= 0; - else if(gpif_rd) - read_count <= read_count + 1; - else - read_count <= 0; - - // Data Path - wire [18:0] data_int; - wire src_rdy_int, dst_rdy_int; - fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) rd_fifo_2clk - (.wclk(sys_clk), .datain(data_i[18:0]), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(), - .rclk(~gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(), - .arst(sys_rst)); - - reg [7:0] packet_count; - wire consume_data_line = gpif_rd & ~gpif_ep & ~read_count[8]; - wire produce_eop = src_rdy_int & dst_rdy_int & data_int[17]; - wire consume_sop = consume_data_line & final_rdy_data & data_o[16]; - wire consume_eop = consume_data_line & final_rdy_data & data_o[17]; - - fifo_cascade #(.WIDTH(19), .SIZE(10)) rd_fifo - (.clk(~gpif_clk), .reset(gpif_rst), .clear(0), - .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), - .dataout(data_o), .src_rdy_o(final_rdy_data), .dst_rdy_i(consume_data_line), .occupied()); - - always @(negedge gpif_clk) - if(gpif_rst) - packet_count <= 0; - else - if(produce_eop & ~consume_sop) - packet_count <= packet_count + 1; - else if(consume_sop & ~produce_eop) - packet_count <= packet_count - 1; - - always @(negedge gpif_clk) - if(gpif_rst) - gpif_empty_d <= 1; - else - gpif_empty_d <= ~|packet_count; - - // Use occ bit to signal a gpif flush - always @(negedge gpif_clk) - if(gpif_rst) - gpif_flush <= 0; - else if(consume_eop & data_o[18]) - gpif_flush <= ~gpif_flush; - - // Response Path - wire [15:0] resp_fifolevel; - wire consume_resp_line = gpif_rd & gpif_ep & ~read_count[4]; - - fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) resp_fifo_2clk - (.wclk(sys_clk), .datain(resp_i[17:0]), .src_rdy_i(resp_src_rdy_i), .dst_rdy_o(resp_dst_rdy_o), .space(), - .rclk(~gpif_clk), .dataout(resp_o), - .src_rdy_o(final_rdy_resp), .dst_rdy_i(consume_resp_line), .occupied(resp_fifolevel), - .arst(sys_rst)); - - // FIXME -- handle short packets - - always @(negedge gpif_clk) - if(gpif_rst) - gpif_empty_c <= 1; - else - gpif_empty_c <= resp_fifolevel < 16; - - // Output Mux - assign gpif_data = gpif_ep ? resp_o[15:0] : data_o[15:0]; - - assign debug = { { 16'd0 }, - { data_int[17:16], data_o[17:16], packet_count[3:0] }, - { consume_sop, consume_eop, final_rdy_data, data_o[18], consume_data_line, consume_resp_line, src_rdy_int, dst_rdy_int} }; - -endmodule // gpif_rd diff --git a/fpga/usrp2/gpif/gpif_tb.v b/fpga/usrp2/gpif/gpif_tb.v deleted file mode 100644 index 686284c2b..000000000 --- a/fpga/usrp2/gpif/gpif_tb.v +++ /dev/null @@ -1,142 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module gpif_tb(); - - reg sys_clk = 0; - reg sys_rst = 1; - reg gpif_clk = 0; - reg gpif_rst = 1; - - reg [15:0] gpif_data; - reg WR = 0, EP = 0; - - wire CF, DF; - - wire gpif_full_d, gpif_full_c; - wire [18:0] data_o, ctrl_o, data_splt; - wire src_rdy, dst_rdy, src_rdy_splt, dst_rdy_splt; - wire ctrl_src_rdy, ctrl_dst_rdy; - - assign ctrl_dst_rdy = 1; - - initial $dumpfile("gpif_tb.vcd"); - initial $dumpvars(0,gpif_tb); - - initial #1000 gpif_rst = 0; - initial #1000 sys_rst = 0; - always #64 gpif_clk <= ~gpif_clk; - always #47.9 sys_clk <= ~sys_clk; - - wire [18:0] data_int; - wire src_rdy_int, dst_rdy_int; - - assign dst_rdy_splt = 1; - - gpif_wr gpif_write - (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), - .gpif_data(gpif_data), .gpif_wr(WR), .gpif_ep(EP), - .gpif_full_d(DF), .gpif_full_c(CF), - - .sys_clk(sys_clk), .sys_rst(sys_rst), - .data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), - .ctrl_o(ctrl_o), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy) ); - - packet_reframer tx_packet_reframer - (.clk(sys_clk), .reset(sys_rst), .clear(0), - .data_i(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), - .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); - - packet_splitter #(.FRAME_LEN(256)) rx_packet_splitter - (.clk(sys_clk), .reset(sys_rst), .clear(0), - .frames_per_packet(2), - .data_i(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), - .data_o(data_splt), .src_rdy_o(src_rdy_splt), .dst_rdy_i(dst_rdy_splt)); - - always @(posedge sys_clk) - if(ctrl_src_rdy & ctrl_dst_rdy) - $display("CTRL: %x",ctrl_o); - - always @(posedge sys_clk) - if(src_rdy_splt & dst_rdy_splt) - begin - if(data_splt[16]) - $display("<-------- DATA SOF--------->"); - $display("DATA: %x",data_splt); - if(data_splt[17]) - $display("<-------- DATA EOF--------->"); - end - - initial - begin - #10000; - repeat (1) - begin - @(posedge gpif_clk); - - WR <= 1; - gpif_data <= 256; // Length - @(posedge gpif_clk); - gpif_data <= 16'h00; - @(posedge gpif_clk); - repeat(254) - begin - gpif_data <= gpif_data + 1; - @(posedge gpif_clk); - end - WR <= 0; - - while(DF) - @(posedge gpif_clk); - repeat (16) - @(posedge gpif_clk); - - WR <= 1; - repeat(256) - begin - gpif_data <= gpif_data - 1; - @(posedge gpif_clk); - end - WR <= 0; - - -/* - while(DF) - @(posedge gpif_clk); - - repeat (20) - @(posedge gpif_clk); - WR <= 1; - gpif_data <= 16'h5; - @(posedge gpif_clk); - gpif_data <= 16'h00; - @(posedge gpif_clk); - repeat(254) - begin - gpif_data <= gpif_data - 1; - @(posedge gpif_clk); - end - WR <= 0; - */ - end - end // initial begin - - initial #200000 $finish; - - -endmodule // gpif_tb diff --git a/fpga/usrp2/gpif/gpif_wr.v b/fpga/usrp2/gpif/gpif_wr.v deleted file mode 100644 index 89fae282e..000000000 --- a/fpga/usrp2/gpif/gpif_wr.v +++ /dev/null @@ -1,95 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module gpif_wr - (input gpif_clk, input gpif_rst, - input [15:0] gpif_data, input gpif_wr, input gpif_ep, - output reg gpif_full_d, output reg gpif_full_c, - - input sys_clk, input sys_rst, - output [18:0] data_o, output src_rdy_o, input dst_rdy_i, - output [18:0] ctrl_o, output ctrl_src_rdy_o, input ctrl_dst_rdy_i, - output [31:0] debug ); - - reg wr_reg, ep_reg; - reg [15:0] gpif_data_reg; - - always @(posedge gpif_clk) - begin - ep_reg <= gpif_ep; - wr_reg <= gpif_wr; - gpif_data_reg <= gpif_data; - end - - reg [9:0] write_count; - - always @(posedge gpif_clk) - if(gpif_rst) - write_count <= 0; - else if(wr_reg) - write_count <= write_count + 1; - else - write_count <= 0; - - reg sop; - wire eop = (write_count == 255); - wire eop_ctrl = (write_count == 15); - - always @(posedge gpif_clk) - sop <= gpif_wr & ~wr_reg; - - // Data Path - wire [15:0] fifo_space; - always @(posedge gpif_clk) - if(gpif_rst) - gpif_full_d <= 1; - else - gpif_full_d <= fifo_space < 256; - - wire [17:0] data_int; - wire src_rdy_int, dst_rdy_int; - - fifo_cascade #(.WIDTH(18), .SIZE(10)) wr_fifo - (.clk(gpif_clk), .reset(gpif_rst), .clear(0), - .datain({eop,sop,gpif_data_reg}), .src_rdy_i(~ep_reg & wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space), - .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied()); - - fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) wr_fifo_2clk - (.wclk(gpif_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), - .rclk(sys_clk), .dataout(data_o[17:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), - .arst(sys_rst)); - assign data_o[18] = 1'b0; - - // Control Path - wire [15:0] ctrl_fifo_space; - always @(posedge gpif_clk) - if(gpif_rst) - gpif_full_c <= 1; - else - gpif_full_c <= ctrl_fifo_space < 16; - - fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) ctrl_fifo_2clk - (.wclk(gpif_clk), .datain({1'b0,eop_ctrl,sop,gpif_data_reg}), - .src_rdy_i(ep_reg & wr_reg & ~write_count[4]), .dst_rdy_o(), .space(ctrl_fifo_space), - .rclk(sys_clk), .dataout(ctrl_o[18:0]), - .src_rdy_o(ctrl_src_rdy_o), .dst_rdy_i(ctrl_dst_rdy_i), .occupied(), - .arst(sys_rst)); - - assign debug = { 16'd0, ep_reg, wr_reg, eop, sop, (~ep_reg & wr_reg & ~write_count[8]), src_rdy_int, dst_rdy_int, write_count[8:0]}; - -endmodule // gpif_wr diff --git a/fpga/usrp2/gpif/gpif_wr_tb.v b/fpga/usrp2/gpif/gpif_wr_tb.v deleted file mode 100644 index 171bb96a1..000000000 --- a/fpga/usrp2/gpif/gpif_wr_tb.v +++ /dev/null @@ -1,110 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module gpif_wr_tb(); - - reg sys_clk = 0; - reg sys_rst = 1; - reg gpif_clk = 0; - reg gpif_rst = 1; - - reg [15:0] gpif_data; - reg WR = 0, EP = 0; - - wire CF, DF; - - wire gpif_full_d, gpif_full_c; - wire [18:0] data_o, ctrl_o; - wire src_rdy, dst_rdy; - wire ctrl_src_rdy, ctrl_dst_rdy; - - assign ctrl_dst_rdy = 1; - assign dst_rdy = 1; - - initial $dumpfile("gpif_wr_tb.vcd"); - initial $dumpvars(0,gpif_wr_tb); - - initial #1000 gpif_rst = 0; - initial #1000 sys_rst = 0; - always #64 gpif_clk <= ~gpif_clk; - always #47.9 sys_clk <= ~sys_clk; - - wire [18:0] data_int; - wire src_rdy_int, dst_rdy_int; - - gpif_wr gpif_write - (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), - .gpif_data(gpif_data), .gpif_wr(WR), .gpif_ep(EP), - .gpif_full_d(DF), .gpif_full_c(CF), - - .sys_clk(sys_clk), .sys_rst(sys_rst), - .data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), - .ctrl_o(ctrl_o), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy) ); - - packet_reframer tx_packet_reframer - (.clk(sys_clk), .reset(sys_rst), .clear(0), - .data_i(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), - .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); - - always @(posedge sys_clk) - if(ctrl_src_rdy & ctrl_dst_rdy) - $display("CTRL: %x",ctrl_o); - - always @(posedge sys_clk) - if(src_rdy & dst_rdy) - begin - if(data_o[16]) - $display("<-------- DATA SOF--------->"); - $display("DATA: %x",data_o); - if(data_o[17]) - $display("<-------- DATA EOF--------->"); - end - - initial - begin - #10000; - repeat (1) - begin - WR <= 1; - gpif_data <= 10; // Length - @(posedge gpif_clk); - gpif_data <= 16'h00; - @(posedge gpif_clk); - repeat(254) - begin - gpif_data <= gpif_data + 1; - @(posedge gpif_clk); - end - WR <= 0; - repeat (20) - @(posedge gpif_clk); - WR <= 1; - gpif_data <= 16'h5; - @(posedge gpif_clk); - repeat(254) - begin - gpif_data <= gpif_data - 1; - @(posedge gpif_clk); - end - end - end // initial begin - - initial #100000 $finish; - - -endmodule // gpif_wr_tb diff --git a/fpga/usrp2/gpif/gpmc16_to_fifo36.v b/fpga/usrp2/gpif/gpmc16_to_fifo36.v deleted file mode 100644 index 933891715..000000000 --- a/fpga/usrp2/gpif/gpmc16_to_fifo36.v +++ /dev/null @@ -1,64 +0,0 @@ -// -// Copyright 2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module gpmc16_to_fifo36 -#( - parameter FIFO_SIZE = 9, - - //not ready until minimum xfers of space available - parameter MIN_SPACE16 = 128 -) -( - //input interface - input gpif_clk, input gpif_rst, - input [15:0] in_data, - input valid, - output reg ready, - - //output fifo interface - input fifo_clk, input fifo_rst, - output [35:0] out_data, - output out_src_rdy, - input out_dst_rdy -); - - wire [35:0] data_int; - wire src_rdy_int, dst_rdy_int; - wire [18:0] refr_data; - wire refr_src_rdy, refr_dst_rdy; - - wire [15:0] fifo_space; - - always @(posedge gpif_clk) - ready <= (fifo_space >= MIN_SPACE16/2); - - packet_reframer packet_reframer - (.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0), - .data_i(in_data), .src_rdy_i(valid), .dst_rdy_o(), - .data_o(refr_data), .src_rdy_o(refr_src_rdy), .dst_rdy_i(refr_dst_rdy)); - - fifo19_to_fifo36 #(.LE(1)) f19_to_f36 - (.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0), - .f19_datain(refr_data), .f19_src_rdy_i(refr_src_rdy), .f19_dst_rdy_o(refr_dst_rdy), - .f36_dataout(data_int), .f36_src_rdy_o(src_rdy_int), .f36_dst_rdy_i(dst_rdy_int)); - - fifo_2clock_cascade #(.WIDTH(36), .SIZE(FIFO_SIZE)) fifo_2clk - (.wclk(gpif_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(fifo_space), - .rclk(fifo_clk), .dataout(out_data), .src_rdy_o(out_src_rdy), .dst_rdy_i(out_dst_rdy), .occupied(), - .arst(fifo_rst | gpif_rst)); - -endmodule //fifo_to_gpmc16 diff --git a/fpga/usrp2/gpif/lint b/fpga/usrp2/gpif/lint deleted file mode 100755 index 4316c89a9..000000000 --- a/fpga/usrp2/gpif/lint +++ /dev/null @@ -1,2 +0,0 @@ -iverilog -Wall -y . -y ../fifo/ -y ../control_lib/ -y ../models/ -y ../coregen/ -y ../simple_gemac/ -y ../sdr_lib/ -y ../vrt/ gpif.v 2>&1 | grep -v coregen | grep -v models - diff --git a/fpga/usrp2/gpif/packet_padder36.v b/fpga/usrp2/gpif/packet_padder36.v deleted file mode 100644 index c785f7ea6..000000000 --- a/fpga/usrp2/gpif/packet_padder36.v +++ /dev/null @@ -1,130 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// The packet padder 36 for use with slave fifo32 -// Packet padder understands the concept of LUTs, -// and will forward packets through the interface, -// adding zero padding as needed to properly flush. -// The padder will never write a packet across a LUT boundary. -// When flushing, padder writes out zeros until the LUT boundary. -// Requires that the input line0 be a VITA header, and SOF set. -// Flush when the LUT is partially filled and timeout is reached, -// or when the LUT is partially filled and the DSP is inactive. - -module packet_padder36 -#( - parameter RX_IDLE_FLUSH_CYCLES = 65536, //about 1ms at 64MHz clock - parameter MAX_LUT_LINES32 = 4096 //how many 32bit lines in a LUT -) -( - input clk, input reset, - input [35:0] data_i, - input src_rdy_i, - output dst_rdy_o, - output [35:0] data_o, - output src_rdy_o, - input dst_rdy_i, - input rx_dsp_active -); - - //state machine definitions - localparam STATE_READ_HDR = 0; - localparam STATE_WRITE_HDR = 1; - localparam STATE_FORWARD = 2; - localparam STATE_WRITE_PAD = 3; - reg [1:0] state; - - //keep track of the outgoing lines - reg [15:0] line_count; - wire line_count_done = line_count == 1; - wire lut_is_empty = line_count == MAX_LUT_LINES32; - always @(posedge clk) begin - if (reset) begin - line_count <= MAX_LUT_LINES32; - end - else if (src_rdy_o && dst_rdy_i) begin - line_count <= (line_count_done)? MAX_LUT_LINES32 : line_count - 1; - end - end - - //count the number of cycles since RX data so we can force a flush - reg [17:0] non_rx_cycles; - wire idle_timeout = (non_rx_cycles == RX_IDLE_FLUSH_CYCLES); - always @(posedge clk) begin - if(reset || state != STATE_READ_HDR) begin - non_rx_cycles <= 0; - end - else if (~idle_timeout) begin - non_rx_cycles <= non_rx_cycles + 1; - end - end - - //flush when we have written data to a LUT and either idle or non active DSP - wire force_flush = ~lut_is_empty && (idle_timeout || ~rx_dsp_active); - - //the padding state machine - reg [31:0] vita_hdr; - reg has_vita_hdr; - always @(posedge clk) begin - if (reset) begin - state <= STATE_READ_HDR; - end - else case(state) - - STATE_READ_HDR: begin - if (src_rdy_i && dst_rdy_o && data_i[32]) begin - vita_hdr <= data_i[31:0]; - has_vita_hdr <= 1; - state <= (data_i[15:0] > line_count)? state <= STATE_WRITE_PAD : STATE_WRITE_HDR; - end - else if (force_flush) begin - has_vita_hdr <= 0; - state <= STATE_WRITE_PAD; - end - end - - STATE_WRITE_HDR: begin - if (src_rdy_o && dst_rdy_i) begin - state <= STATE_FORWARD; - end - end - - STATE_FORWARD: begin - if (src_rdy_i && dst_rdy_o && data_i[33]) begin - state <= STATE_READ_HDR; - end - end - - STATE_WRITE_PAD: begin - if (src_rdy_o && dst_rdy_i && line_count_done) begin - state <= (has_vita_hdr)? STATE_WRITE_HDR : STATE_READ_HDR; - end - end - - endcase //state - end - - //assign outgoing signals - assign dst_rdy_o = (state == STATE_READ_HDR)? 1 : ((state == STATE_FORWARD)? dst_rdy_i : 0); - assign src_rdy_o = (state == STATE_WRITE_HDR || state == STATE_WRITE_PAD)? 1 : ((state == STATE_FORWARD )? src_rdy_i : 0); - assign data_o = (state == STATE_WRITE_HDR)? {4'b0001, vita_hdr} : ((state == STATE_FORWARD)? data_i : 0); - -endmodule // packet_padder36 - - - - diff --git a/fpga/usrp2/gpif/packet_reframer.v b/fpga/usrp2/gpif/packet_reframer.v deleted file mode 100644 index e0ce9e174..000000000 --- a/fpga/usrp2/gpif/packet_reframer.v +++ /dev/null @@ -1,70 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Join vita packets longer than one GPIF frame - -module packet_reframer - (input clk, input reset, input clear, - input [15:0] data_i, - input src_rdy_i, - output dst_rdy_o, - output [18:0] data_o, - output src_rdy_o, - input dst_rdy_i, - output reg state, - output eof_out, - output reg [15:0] length); - - //reg state; - //reg [15:0] length; - - localparam RF_IDLE = 0; - localparam RF_PKT = 1; - - always @(posedge clk) - if(reset | clear) - state <= RF_IDLE; - else - if(src_rdy_i & dst_rdy_i) - case(state) - RF_IDLE : - begin - length <= {data_i[14:0],1'b0}; - state <= RF_PKT; - end - RF_PKT : - begin - if(eof_out) state <= RF_IDLE; - length <= length - 1; - end - endcase // case (state) - - assign dst_rdy_o = dst_rdy_i; // this is a little pessimistic but ok - assign src_rdy_o = src_rdy_i; - - wire occ_out = 0; - assign eof_out = (state == RF_PKT) & (length == 2); - wire sof_out = (state == RF_IDLE); - assign data_o = {occ_out, eof_out, sof_out, data_i[15:0]}; - - -endmodule // packet_reframer - - - - diff --git a/fpga/usrp2/gpif/packet_splitter.v b/fpga/usrp2/gpif/packet_splitter.v deleted file mode 100644 index ba4c8cded..000000000 --- a/fpga/usrp2/gpif/packet_splitter.v +++ /dev/null @@ -1,123 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Split vita packets longer than one GPIF frame, add padding on short frames - -module packet_splitter - #(parameter FRAME_LEN=256) - (input clk, input reset, input clear, - input [7:0] frames_per_packet, - input [18:0] data_i, - input src_rdy_i, - output dst_rdy_o, - output [18:0] data_o, - output src_rdy_o, - input dst_rdy_i, - output [31:0] debug0, - output [31:0] debug1); - - reg [1:0] state; - reg [15:0] length; - reg [15:0] frame_len; - reg [7:0] frame_count; - - localparam PS_IDLE = 0; - localparam PS_FRAME = 1; - localparam PS_NEW_FRAME = 2; - localparam PS_PAD = 3; - - wire eof_i = data_i[17]; - - always @(posedge clk) - if(reset | clear) - begin - state <= PS_IDLE; - frame_count <= 0; - end - else - case(state) - PS_IDLE : - if(src_rdy_i & dst_rdy_i) - begin - length <= { data_i[14:0],1'b0}; - frame_len <= FRAME_LEN; - state <= PS_FRAME; - frame_count <= 1; - end - PS_FRAME : - if(src_rdy_i & dst_rdy_i) - if((frame_len == 2) & ((length == 2) | eof_i)) - state <= PS_IDLE; - else if(frame_len == 2) - begin - length <= length - 1; - state <= PS_NEW_FRAME; - frame_count <= frame_count + 1; - end - else if((length == 2)|eof_i) - begin - frame_len <= frame_len - 1; - state <= PS_PAD; - end - else - begin - frame_len <= frame_len - 1; - length <= length - 1; - end - PS_NEW_FRAME : - if(src_rdy_i & dst_rdy_i) - begin - frame_len <= FRAME_LEN; - if((length == 2)|eof_i) - state <= PS_PAD; - else - begin - state <= PS_FRAME; - length <= length - 1; - end // else: !if((length == 2)|eof_i) - end // if (src_rdy_i & dst_rdy_i) - - PS_PAD : - if(dst_rdy_i) - if(frame_len == 2) - state <= PS_IDLE; - else - frame_len <= frame_len - 1; - - endcase // case (state) - - wire next_state_is_idle = dst_rdy_i & (frame_len==2) & - ( (state==PS_PAD) | ( (state==PS_FRAME) & src_rdy_i & ((length==2)|eof_i) ) ); - - - - - assign dst_rdy_o = dst_rdy_i & (state != PS_PAD); - assign src_rdy_o = src_rdy_i | (state == PS_PAD); - - wire eof_out = (frame_len == 2) & (state != PS_IDLE) & (state != PS_NEW_FRAME); - wire sof_out = (state == PS_IDLE) | (state == PS_NEW_FRAME); - wire occ_out = eof_out & next_state_is_idle & (frames_per_packet != frame_count); - - wire [15:0] data_out = data_i[15:0]; - assign data_o = {occ_out, eof_out, sof_out, data_out}; - - assign debug0 = { 8'd0, dst_rdy_o, src_rdy_o, next_state_is_idle, eof_out, sof_out, occ_out, state[1:0], frame_count[7:0], frames_per_packet[7:0] }; - assign debug1 = { length[15:0], frame_len[15:0] }; - -endmodule // packet_splitter diff --git a/fpga/usrp2/gpif/packet_splitter_tb.v b/fpga/usrp2/gpif/packet_splitter_tb.v deleted file mode 100644 index 329b58e0d..000000000 --- a/fpga/usrp2/gpif/packet_splitter_tb.v +++ /dev/null @@ -1,137 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module packet_splitter_tb(); - - reg sys_clk = 0; - reg sys_rst = 1; - reg gpif_clk = 0; - reg gpif_rst = 1; - - reg [15:0] gpif_data; - reg WR = 0, EP = 0; - - wire CF, DF; - - wire gpif_full_d, gpif_full_c; - wire [18:0] data_o, ctrl_o, data_splt; - wire src_rdy, dst_rdy, src_rdy_splt, dst_rdy_splt; - wire ctrl_src_rdy, ctrl_dst_rdy; - - assign ctrl_dst_rdy = 1; - - initial $dumpfile("packet_splitter_tb.vcd"); - initial $dumpvars(0,packet_splitter_tb); - - initial #1000 gpif_rst = 0; - initial #1000 sys_rst = 0; - always #64 gpif_clk <= ~gpif_clk; - always #47.9 sys_clk <= ~sys_clk; - - wire [35:0] data_int; - wire src_rdy_int, dst_rdy_int; - - assign dst_rdy_splt = 1; - - vita_pkt_gen vita_pkt_gen - (.clk(sys_clk), .reset(sys_rst) , .clear(0), - .len(512),.data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int)); - - fifo36_to_fifo19 #(.LE(1)) f36_to_f19 - (.clk(sys_clk), .reset(sys_rst), .clear(0), - .f36_datain(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int), - .f19_dataout(data_o), .f19_src_rdy_o(src_rdy), .f19_dst_rdy_i(dst_rdy)); - - packet_splitter #(.FRAME_LEN(13)) rx_packet_splitter - (.clk(sys_clk), .reset(sys_rst), .clear(0), - .frames_per_packet(4), - .data_i(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), - .data_o(data_splt), .src_rdy_o(src_rdy_splt), .dst_rdy_i(dst_rdy_splt)); - - always @(posedge sys_clk) - if(ctrl_src_rdy & ctrl_dst_rdy) - $display("CTRL: %x",ctrl_o); - - always @(posedge sys_clk) - if(src_rdy_splt & dst_rdy_splt) - begin - if(data_splt[16]) - $display("<-------- DATA SOF--------->"); - $display("DATA: %x",data_splt); - if(data_splt[17]) - $display("<-------- DATA EOF--------->"); - end - - initial - begin - #10000; - repeat (1) - begin - @(posedge gpif_clk); - - WR <= 1; - gpif_data <= 256; // Length - @(posedge gpif_clk); - gpif_data <= 16'h00; - @(posedge gpif_clk); - repeat(254) - begin - gpif_data <= gpif_data + 1; - @(posedge gpif_clk); - end - WR <= 0; - - while(DF) - @(posedge gpif_clk); - repeat (16) - @(posedge gpif_clk); - - WR <= 1; - repeat(256) - begin - gpif_data <= gpif_data - 1; - @(posedge gpif_clk); - end - WR <= 0; - - -/* - while(DF) - @(posedge gpif_clk); - - repeat (20) - @(posedge gpif_clk); - WR <= 1; - gpif_data <= 16'h5; - @(posedge gpif_clk); - gpif_data <= 16'h00; - @(posedge gpif_clk); - repeat(254) - begin - gpif_data <= gpif_data - 1; - @(posedge gpif_clk); - end - WR <= 0; - */ - end - end // initial begin - - initial #200000 $finish; - - -endmodule // packet_splitter_tb diff --git a/fpga/usrp2/gpif/slave_fifo.v b/fpga/usrp2/gpif/slave_fifo.v deleted file mode 100644 index c10b79ab4..000000000 --- a/fpga/usrp2/gpif/slave_fifo.v +++ /dev/null @@ -1,276 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -////////////////////////////////////////////////////////////////////////////////// - -//this is a FIFO master interface for the FX2 in "slave fifo" mode. - -module slave_fifo - #( - //how many cycles max in a transfer state - parameter DATA_XFER_COUNT = 256, - parameter CTRL_XFER_COUNT = 32, - - //sizes for fifo36 2 clock cascade fifos - parameter DATA_RX_FIFO_SIZE = 9, - parameter DATA_TX_FIFO_SIZE = 9, - parameter CTRL_RX_FIFO_SIZE = 9, - parameter CTRL_TX_FIFO_SIZE = 9 - ) - (// GPIF signals - input gpif_clk, input gpif_rst, - inout [15:0] gpif_d, - input [3:0] gpif_ctl, - output reg sloe, output reg slrd, output reg slwr, output reg pktend, output reg [1:0] fifoadr, - - // FIFO interface - input fifo_clk, input fifo_rst, - output [35:0] tx_data, output tx_src_rdy, input tx_dst_rdy, - input [35:0] rx_data, input rx_src_rdy, output rx_dst_rdy, - output [35:0] ctrl_data, output ctrl_src_rdy, input ctrl_dst_rdy, - input [35:0] resp_data, input resp_src_rdy, output resp_dst_rdy, - - output [31:0] debug - ); - - wire FX2_DE_pre = ~gpif_ctl[0]; //EP2 FX2 FIFO empty (FLAGA) - wire FX2_CE_pre = ~gpif_ctl[1]; //EP4 FX2 FIFO empty (FLAGB) - wire FX2_DF_pre = ~gpif_ctl[2]; //EP6 FX2 FIFO full (FLAGC) - wire FX2_CF_pre = ~gpif_ctl[3]; //EP8 FX2 FIFO full (FLAGD) - - reg FX2_DE, FX2_CE, FX2_DF, FX2_CF; - always @(posedge gpif_clk) begin - FX2_DE <= FX2_DE_pre; //EP2 FX2 FIFO empty (FLAGA) - FX2_CE <= FX2_CE_pre; //EP4 FX2 FIFO empty (FLAGB) - FX2_DF <= FX2_DF_pre; //EP6 FX2 FIFO full (FLAGC) - FX2_CF <= FX2_CF_pre; //EP8 FX2 FIFO full (FLAGD) - end - - wire [15:0] gpif_d_out_ctrl, gpif_d_out_data; - reg [15:0] gpif_d_out, gpif_d_in; - - // //////////////////////////////////////////////////////////////////// - // GPIF bus master state machine - - wire rx_valid, resp_valid; - reg tx_valid, ctrl_valid; - wire tx_ready, ctrl_ready; - reg rx_enable, resp_enable; - wire rx_data_enough_occ; - - reg [9:0] transfer_count; //number of lines (a line is 16 bits) in active transfer - - reg [3:0] state; //state machine current state - localparam STATE_IDLE = 0; - localparam STATE_THINK = 1; - localparam STATE_DATA_RX = 2; - localparam STATE_DATA_TX = 3; - localparam STATE_CTRL_RX = 4; - localparam STATE_CTRL_TX = 5; - localparam STATE_DATA_TX_SLOE = 6; - localparam STATE_CTRL_TX_SLOE = 7; - localparam STATE_DATA_RX_ADR = 8; - localparam STATE_CTRL_RX_ADR = 9; - - //logs the last bus user for xfer fairness - //we only care about data rx vs. tx since ctrl pkts are so short - reg last_data_bus_hog; - localparam BUS_HOG_RX = 0; - localparam BUS_HOG_TX = 1; - - wire resp_eof; - reg [1:0] idle_count; - - // ////////////////////////////////////////////////////////////// - // FX2 slave FIFO bus master state machine - // - always @(posedge gpif_clk) - if(gpif_rst) begin - state <= STATE_IDLE; - sloe <= 1; - slrd <= 1; - slwr <= 1; - pktend <= 1; - rx_enable <= 0; - tx_valid <= 0; - ctrl_valid <= 0; - resp_enable <= 0; - idle_count <= 0; - end - else case (state) - STATE_IDLE: begin - transfer_count <= 0; - sloe <= 1; - slrd <= 1; - slwr <= 1; - pktend <= 1; - rx_enable <= 0; - tx_valid <= 0; - ctrl_valid <= 0; - resp_enable <= 0; - if (idle_count == 2'b11) state <= STATE_THINK; - idle_count <= idle_count + 1; - end - - STATE_THINK: begin - - idle_count <= 0; - - //handle transitions to other states - if(ctrl_ready & ~FX2_CE) begin //if there's room in the ctrl fifo and the FX2 has ctrl data - state <= STATE_CTRL_TX_SLOE; - fifoadr <= 2'b01; - sloe <= 0; - end - else if(resp_valid & ~FX2_CF) begin //if the ctrl fifo has data and the FX2 isn't full - state <= STATE_CTRL_RX_ADR; - fifoadr <= 2'b11; - end - else if(tx_ready & ~FX2_DE & last_data_bus_hog == BUS_HOG_RX) begin //if there's room in the data fifo and the FX2 has data - state <= STATE_DATA_TX_SLOE; - last_data_bus_hog <= BUS_HOG_TX; - fifoadr <= 2'b00; - sloe <= 0; - end - else if(rx_data_enough_occ & ~FX2_DF & last_data_bus_hog == BUS_HOG_TX) begin //if the data fifo has data and the FX2 isn't full - state <= STATE_DATA_RX_ADR; - last_data_bus_hog <= BUS_HOG_RX; - fifoadr <= 2'b10; - end - else if(tx_ready & ~FX2_DE) begin - state <= STATE_DATA_TX_SLOE; - last_data_bus_hog <= BUS_HOG_TX; - fifoadr <= 2'b00; - sloe <= 0; - end - else if(rx_data_enough_occ & ~FX2_DF) begin - state <= STATE_DATA_RX_ADR; - last_data_bus_hog <= BUS_HOG_RX; - fifoadr <= 2'b10; - end - end - - STATE_DATA_TX_SLOE: begin //just to assert SLOE one cycle before SLRD - state <= STATE_DATA_TX; - slrd <= 0; - end - - STATE_CTRL_TX_SLOE: begin - state <= STATE_CTRL_TX; - slrd <= 0; - end - - STATE_DATA_RX_ADR: begin //just to assert FIFOADR one cycle before SLWR - state <= STATE_DATA_RX; - rx_enable <= 1; - end - - STATE_CTRL_RX_ADR: begin - state <= STATE_CTRL_RX; - resp_enable <= 1; - end - - STATE_DATA_RX: begin - if (FX2_DF_pre || ~rx_valid || transfer_count == DATA_XFER_COUNT-1) begin - state <= STATE_IDLE; - rx_enable <= 0; - end - gpif_d_out <= gpif_d_out_data; - slwr <= ~rx_valid; - transfer_count <= transfer_count + 1; - end - - STATE_DATA_TX: begin - if (FX2_DE_pre || transfer_count == DATA_XFER_COUNT-1) begin - state <= STATE_IDLE; - slrd <= 1; - end - gpif_d_in <= gpif_d; - tx_valid <= 1; - transfer_count <= transfer_count + 1; - end - - STATE_CTRL_RX: begin - if (FX2_CF_pre || ~resp_valid || resp_eof || transfer_count == CTRL_XFER_COUNT-1) begin - state <= STATE_IDLE; - resp_enable <= 0; - end - pktend <= ~resp_eof; - gpif_d_out <= gpif_d_out_ctrl; - slwr <= ~resp_valid; - transfer_count <= transfer_count + 1; - end - - STATE_CTRL_TX: begin - if (FX2_CE_pre || transfer_count == CTRL_XFER_COUNT-1) begin - state <= STATE_IDLE; - slrd <= 1; - end - gpif_d_in <= gpif_d; - ctrl_valid <= 1; - transfer_count <= transfer_count + 1; - end - endcase - - // GPIF output data lines, tristate - assign gpif_d = (sloe)? gpif_d_out[15:0] : 16'bz; - - // //////////////////////////////////////////////////////////////////// - // TX Data Path - - gpmc16_to_fifo36 #(.FIFO_SIZE(DATA_TX_FIFO_SIZE), .MIN_SPACE16(DATA_XFER_COUNT)) fifo36_to_gpmc16_tx( - .gpif_clk(gpif_clk), .gpif_rst(gpif_rst), - .in_data(gpif_d_in), .ready(tx_ready), .valid(tx_valid), - .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), - .out_data(tx_data), .out_src_rdy(tx_src_rdy), .out_dst_rdy(tx_dst_rdy) - ); - - // //////////////////////////////////////////// - // RX Data Path - - fifo36_to_gpmc16 #(.FIFO_SIZE(DATA_RX_FIFO_SIZE), .MIN_OCC16(DATA_XFER_COUNT)) fifo36_to_gpmc16_rx( - .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), - .in_data(rx_data), .in_src_rdy(rx_src_rdy), .in_dst_rdy(rx_dst_rdy), - .gpif_clk(gpif_clk), .gpif_rst(gpif_rst), - .has_data(rx_data_enough_occ), - .out_data(gpif_d_out_data), .valid(rx_valid), .enable(rx_enable) - ); - - // //////////////////////////////////////////////////////////////////// - // CTRL TX Data Path - - gpmc16_to_fifo36 #(.FIFO_SIZE(CTRL_TX_FIFO_SIZE), .MIN_SPACE16(CTRL_XFER_COUNT)) fifo36_to_gpmc16_ctrl( - .gpif_clk(gpif_clk), .gpif_rst(gpif_rst), - .in_data(gpif_d_in), .ready(ctrl_ready), .valid(ctrl_valid), - .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), - .out_data(ctrl_data), .out_src_rdy(ctrl_src_rdy), .out_dst_rdy(ctrl_dst_rdy) - ); - - // //////////////////////////////////////////// - // CTRL RX Data Path - - fifo36_to_gpmc16 #(.FIFO_SIZE(CTRL_RX_FIFO_SIZE)) fifo36_to_gpmc16_resp( - .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), - .in_data(resp_data), .in_src_rdy(resp_src_rdy), .in_dst_rdy(resp_dst_rdy), - .gpif_clk(gpif_clk), .gpif_rst(gpif_rst), - .out_data(gpif_d_out_ctrl), .valid(resp_valid), .enable(resp_enable), - .eof(resp_eof) - ); - - assign debug = 0; - -endmodule // slave_fifo diff --git a/fpga/usrp2/gpmc/.gitignore b/fpga/usrp2/gpmc/.gitignore deleted file mode 100644 index 3e14fa4f7..000000000 --- a/fpga/usrp2/gpmc/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -*.gif - diff --git a/fpga/usrp2/gpmc/Makefile.srcs b/fpga/usrp2/gpmc/Makefile.srcs deleted file mode 100644 index 39b37db58..000000000 --- a/fpga/usrp2/gpmc/Makefile.srcs +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright 2010-2012 Ettus Research LLC -# - -################################################## -# GPMC Sources -################################################## -GPMC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../gpmc/, \ -cross_clock_reader.v \ -fifo_to_gpmc.v \ -gpmc.v \ -gpmc_to_fifo.v \ -)) diff --git a/fpga/usrp2/gpmc/cross_clock_reader.v b/fpga/usrp2/gpmc/cross_clock_reader.v deleted file mode 100644 index b4cdb79c5..000000000 --- a/fpga/usrp2/gpmc/cross_clock_reader.v +++ /dev/null @@ -1,46 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module cross_clock_reader - #( - parameter WIDTH = 1, - parameter DEFAULT = 0 - ) - ( - input clk, input rst, - input [WIDTH-1:0] in, - output reg [WIDTH-1:0] out - ); - - reg [WIDTH-1:0] shadow0, shadow1; - reg [2:0] count; - - always @(posedge clk) begin - if (rst) begin - out <= DEFAULT; - shadow0 <= DEFAULT; - shadow1 <= DEFAULT; - count <= 0; - end - else if (shadow0 == shadow1) count <= count + 1; - else count <= 0; - shadow0 <= in; - shadow1 <= shadow0; - if (count == 3'b111) out <= shadow1; - end - -endmodule //cross_clock_reader diff --git a/fpga/usrp2/gpmc/fifo_to_gpmc.v b/fpga/usrp2/gpmc/fifo_to_gpmc.v deleted file mode 100644 index 26443a702..000000000 --- a/fpga/usrp2/gpmc/fifo_to_gpmc.v +++ /dev/null @@ -1,160 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -//////////////////////////////////////////////////////////////////////// -// FIFO to GPMC -// -// Reads frames from FIFO interface and writes them into BRAM pages. -// The GPMC is asynchronously alerted when a BRAM page has been filled. -// -// EM_CLK: -// A GPMC read transaction consists of two EM_CLK cycles (idle low). -// -// EM_OE: -// Output enable is actually the combination of ~NOE & ~NCS. -// The output enable is only active for the second rising edge, -// to ensure one edge per transaction to transition on. -// -// EM_D: -// The BRAM performs a read on the first rising edge into EM_D. -// Then, data will then be read on the next rising edge by GPMC. -// -// EM_A: -// On the first rising edge of EM_CLK, the address is held. -// On the second rising edge, the address is set for the next transaction. -//////////////////////////////////////////////////////////////////////// - -module fifo_to_gpmc - #(parameter PTR_WIDTH = 2, parameter ADDR_WIDTH = 10, parameter LAST_ADDR = 10'h3ff) - (input clk, input reset, input clear, input arst, - input [17:0] data_i, input src_rdy_i, output dst_rdy_o, - output [15:0] EM_D, input [ADDR_WIDTH:1] EM_A, input EM_CLK, input EM_OE, - output reg data_available); - - //states for the GPMC side of things - wire [17:0] data_o; - reg gpmc_state; - reg [ADDR_WIDTH:1] addr; - reg [PTR_WIDTH:0] gpmc_ptr, next_gpmc_ptr; - localparam GPMC_STATE_START = 0; - localparam GPMC_STATE_EMPTY = 1; - - //states for the FIFO side of things - reg fifo_state; - reg [ADDR_WIDTH-1:0] counter; - reg [PTR_WIDTH:0] fifo_ptr; - localparam FIFO_STATE_CLAIM = 0; - localparam FIFO_STATE_FILL = 1; - - //------------------------------------------------------------------ - // State machine to control the data from GPMC to BRAM - //------------------------------------------------------------------ - always @(posedge EM_CLK or posedge arst) begin - if (arst) begin - gpmc_state <= GPMC_STATE_START; - gpmc_ptr <= 0; - next_gpmc_ptr <= 0; - addr <= 0; - end - else if (EM_OE) begin - addr <= EM_A + 1; - case(gpmc_state) - - GPMC_STATE_START: begin - if (EM_A == 0) begin - gpmc_state <= GPMC_STATE_EMPTY; - next_gpmc_ptr <= gpmc_ptr + 1; - end - end - - GPMC_STATE_EMPTY: begin - if (addr == LAST_ADDR) begin - gpmc_state <= GPMC_STATE_START; - gpmc_ptr <= next_gpmc_ptr; - addr <= 0; - end - end - - endcase //gpmc_state - end //EM_OE - end //always - - //------------------------------------------------------------------ - // High when the gpmc pointer has not caught up to the fifo pointer. - //------------------------------------------------------------------ - wire [PTR_WIDTH:0] safe_gpmc_ptr; - cross_clock_reader #(.WIDTH(PTR_WIDTH+1)) read_gpmc_ptr - (.clk(clk), .rst(reset | clear), .in(gpmc_ptr), .out(safe_gpmc_ptr)); - - wire bram_available_to_fill = (fifo_ptr ^ (1 << PTR_WIDTH)) != safe_gpmc_ptr; - - //------------------------------------------------------------------ - // Glich free generation of data available signal: - // Data is available when the pointers dont match. - //------------------------------------------------------------------ - wire [PTR_WIDTH:0] safe_next_gpmc_ptr; - cross_clock_reader #(.WIDTH(PTR_WIDTH+1)) read_next_gpmc_ptr - (.clk(clk), .rst(reset | clear), .in(next_gpmc_ptr), .out(safe_next_gpmc_ptr)); - - always @(posedge clk) - if (reset | clear) data_available <= 0; - else data_available <= safe_next_gpmc_ptr != fifo_ptr; - - //------------------------------------------------------------------ - // State machine to control the data from BRAM to FIFO - //------------------------------------------------------------------ - always @(posedge clk) begin - if (reset | clear) begin - fifo_state <= FIFO_STATE_CLAIM; - fifo_ptr <= 0; - counter <= 0; - end - else begin - case(fifo_state) - - FIFO_STATE_CLAIM: begin - if (bram_available_to_fill) fifo_state <= FIFO_STATE_FILL; - counter <= 0; - end - - FIFO_STATE_FILL: begin - if (src_rdy_i && dst_rdy_o && data_i[17]) begin - fifo_state <= FIFO_STATE_CLAIM; - fifo_ptr <= fifo_ptr + 1; - end - if (src_rdy_i && dst_rdy_o) begin - counter <= counter + 1; - end - end - - endcase //fifo_state - end - end //always - - assign dst_rdy_o = fifo_state == FIFO_STATE_FILL; - - //assign data from bram output - assign EM_D = data_o[15:0]; - - //instantiate dual ported bram for async read + write - ram_2port #(.DWIDTH(18),.AWIDTH(PTR_WIDTH + ADDR_WIDTH)) async_fifo_bram - (.clka(clk),.ena(1'b1),.wea(src_rdy_i && dst_rdy_o), - .addra({fifo_ptr[PTR_WIDTH-1:0], counter}),.dia(data_i),.doa(), - .clkb(EM_CLK),.enb(1'b1),.web(1'b0), - .addrb({gpmc_ptr[PTR_WIDTH-1:0], addr}),.dib(18'h3ffff),.dob(data_o)); - -endmodule // fifo_to_gpmc diff --git a/fpga/usrp2/gpmc/gpmc.v b/fpga/usrp2/gpmc/gpmc.v deleted file mode 100644 index 2f22889cc..000000000 --- a/fpga/usrp2/gpmc/gpmc.v +++ /dev/null @@ -1,167 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -////////////////////////////////////////////////////////////////////////////////// - -module gpmc - #(parameter TXFIFOSIZE = 11, - parameter RXFIFOSIZE = 11, - parameter ADDR_WIDTH = 10, - parameter BUSDEBUG = 1) - (// GPMC signals - input arst, - input EM_CLK, inout [15:0] EM_D, input [ADDR_WIDTH:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, - - // GPIOs for FIFO signalling - output rx_have_data, output tx_have_space, output resp_have_data, - - // FIFO interface - input fifo_clk, input fifo_rst, - output [35:0] tx_data, output tx_src_rdy, input tx_dst_rdy, - input [35:0] rx_data, input rx_src_rdy, output rx_dst_rdy, - output [35:0] ctrl_data, output ctrl_src_rdy, input ctrl_dst_rdy, - input [35:0] resp_data, input resp_src_rdy, output resp_dst_rdy, - - output [31:0] debug - ); - - wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); - wire [15:0] EM_D_data; - wire [15:0] EM_D_ctrl; - - assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_data : EM_D_ctrl; - - // CS4 is RAM_2PORT for DATA PATH (high-speed data) - // Writes go into one RAM, reads come from the other - // CS6 is for CONTROL PATH (slow) - - // //////////////////////////////////////////// - // TX Data Path - - wire [17:0] tx18_data; - wire tx18_src_rdy, tx18_dst_rdy; - wire [35:0] txb_data; - wire txb_src_rdy, txb_dst_rdy; - - gpmc_to_fifo #(.ADDR_WIDTH(10), .LAST_ADDR(10'h3ff), .PTR_WIDTH(2)) gpmc_to_fifo - (.EM_D(EM_D), .EM_A(EM_A[10:1]), .EM_CLK(EM_CLK), .EM_WE(~EM_NCS4 & ~EM_NWE), - .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst), - .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), - .have_space(tx_have_space)); - - fifo19_to_fifo36 #(.LE(1)) f19_to_f36 // Little endian because ARM is LE - (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), - .f19_datain({1'b0,tx18_data}), .f19_src_rdy_i(tx18_src_rdy), .f19_dst_rdy_o(tx18_dst_rdy), - .f36_dataout(txb_data), .f36_src_rdy_o(txb_src_rdy), .f36_dst_rdy_i(txb_dst_rdy)); - - fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_buffering( - .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), - .datain(txb_data), .src_rdy_i(txb_src_rdy), .dst_rdy_o(txb_dst_rdy), - .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) - ); - - // //////////////////////////////////////////// - // RX Data Path - - wire [17:0] rx18_data; - wire rx18_src_rdy, rx18_dst_rdy; - wire [35:0] rxb_data; - wire rxb_src_rdy, rxb_dst_rdy; - wire dummy; - - fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_buffering( - .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), - .datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy), - .dataout(rxb_data), .src_rdy_o(rxb_src_rdy), .dst_rdy_i(rxb_dst_rdy) - ); - - fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE - (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), - .f36_datain(rxb_data), .f36_src_rdy_i(rxb_src_rdy), .f36_dst_rdy_o(rxb_dst_rdy), - .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); - - fifo_to_gpmc #(.ADDR_WIDTH(ADDR_WIDTH), .LAST_ADDR(10'h3ff)) fifo_to_gpmc - (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst), - .data_i(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), - .EM_D(EM_D_data), .EM_A(EM_A), .EM_CLK(EM_CLK), .EM_OE(~EM_NCS4 & ~EM_NOE), - .data_available(rx_have_data)); - - // //////////////////////////////////////////// - // Control path on CS6 - - // //////////////////////////////////////////////////////////////////// - // CTRL TX Data Path - - wire [17:0] ctrl18_data; - wire ctrl18_src_rdy, ctrl18_dst_rdy; - wire [35:0] ctrlb_data; - wire ctrlb_src_rdy, ctrlb_dst_rdy; - - gpmc_to_fifo #(.PTR_WIDTH(5), .ADDR_WIDTH(5), .LAST_ADDR(5'h0f)) ctrl_gpmc_to_fifo - (.EM_D(EM_D), .EM_A(EM_A[5:1]), .EM_CLK(EM_CLK), .EM_WE(~EM_NCS6 & ~EM_NWE), - .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst), - .data_o(ctrl18_data), .src_rdy_o(ctrl18_src_rdy), .dst_rdy_i(ctrl18_dst_rdy), - .have_space(/*always*/)); - - fifo19_to_fifo36 #(.LE(1)) ctrl_f19_to_f36 // Little endian because ARM is LE - (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), - .f19_datain({1'b0,ctrl18_data}), .f19_src_rdy_i(ctrl18_src_rdy), .f19_dst_rdy_o(ctrl18_dst_rdy), - .f36_dataout(ctrlb_data), .f36_src_rdy_o(ctrlb_src_rdy), .f36_dst_rdy_i(ctrlb_dst_rdy)); - - fifo_cascade #(.WIDTH(36), .SIZE(9)) ctrl_buffering( - .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), - .datain(ctrlb_data), .src_rdy_i(ctrlb_src_rdy), .dst_rdy_o(ctrlb_dst_rdy), - .dataout(ctrl_data), .src_rdy_o(ctrl_src_rdy), .dst_rdy_i(ctrl_dst_rdy) - ); - - // //////////////////////////////////////////// - // CTRL RX Data Path - - wire [17:0] resp18_data; - wire resp18_src_rdy, resp18_dst_rdy; - wire [35:0] respb_data; - wire respb_src_rdy, respb_dst_rdy; - wire resp_dummy; - - fifo_cascade #(.WIDTH(36), .SIZE(9)) resp_buffering( - .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), - .datain(resp_data), .src_rdy_i(resp_src_rdy), .dst_rdy_o(resp_dst_rdy), - .dataout(respb_data), .src_rdy_o(respb_src_rdy), .dst_rdy_i(respb_dst_rdy) - ); - - fifo36_to_fifo19 #(.LE(1)) resp_f36_to_f19 // Little endian because ARM is LE - (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), - .f36_datain(respb_data), .f36_src_rdy_i(respb_src_rdy), .f36_dst_rdy_o(respb_dst_rdy), - .f19_dataout({resp_dummy,resp18_data}), .f19_src_rdy_o(resp18_src_rdy), .f19_dst_rdy_i(resp18_dst_rdy) ); - - fifo_to_gpmc #(.PTR_WIDTH(5), .ADDR_WIDTH(5), .LAST_ADDR(5'h0f)) resp_fifo_to_gpmc - (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst), - .data_i(resp18_data), .src_rdy_i(resp18_src_rdy), .dst_rdy_o(resp18_dst_rdy), - .EM_D(EM_D_ctrl), .EM_A(EM_A[5:1]), .EM_CLK(EM_CLK), .EM_OE(~EM_NCS6 & ~EM_NOE), - .data_available(resp_have_data)); -//* - assign debug = { - EM_D, - //resp18_data[15:0], //16 - EM_A, //10 - //resp18_data[17:16], resp18_src_rdy, resp18_dst_rdy, //4 - EM_NCS4, EM_NCS6, EM_NWE, EM_NOE, //4 - EM_CLK, resp_have_data //2 - }; -//*/ -endmodule // gpmc diff --git a/fpga/usrp2/gpmc/gpmc_to_fifo.v b/fpga/usrp2/gpmc/gpmc_to_fifo.v deleted file mode 100644 index d1897faec..000000000 --- a/fpga/usrp2/gpmc/gpmc_to_fifo.v +++ /dev/null @@ -1,177 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -//////////////////////////////////////////////////////////////////////// -// GPMC to FIFO -// -// Reads frames from BRAM pages and writes them into FIFO interface. -// The GPMC is asynchronously alerted when a BRAM page is available. -// -// EM_CLK: -// A GPMC write transaction consists of one EM_CLK cycle (idle low). -// -// EM_WE: -// Write enable is actually the combination of ~NWE & ~NCS. -// The write enable is active for the entire transaction. -// -// EM_D: -// Data is set on the rising edge and written into BRAM on the falling edge. -// -// EM_A: -// Address is set on the rising edge and read by BRAM on the falling edge. -//////////////////////////////////////////////////////////////////////// - -module gpmc_to_fifo - #(parameter PTR_WIDTH = 2, parameter ADDR_WIDTH = 10, parameter LAST_ADDR = 10'h3ff) - (input [15:0] EM_D, input [ADDR_WIDTH:1] EM_A, input EM_CLK, input EM_WE, - input clk, input reset, input clear, input arst, - output [17:0] data_o, output src_rdy_o, input dst_rdy_i, - output reg have_space); - - //states for the GPMC side of things - reg gpmc_state; - reg [ADDR_WIDTH:1] addr; - reg [PTR_WIDTH:0] gpmc_ptr, next_gpmc_ptr; - localparam GPMC_STATE_START = 0; - localparam GPMC_STATE_FILL = 1; - - //states for the FIFO side of things - reg [1:0] fifo_state; - reg [ADDR_WIDTH-1:0] counter; - reg [ADDR_WIDTH-1:0] last_counter; - reg [ADDR_WIDTH-1:0] last_xfer; - reg [PTR_WIDTH:0] fifo_ptr; - localparam FIFO_STATE_CLAIM = 0; - localparam FIFO_STATE_EMPTY = 1; - localparam FIFO_STATE_PRE = 2; - - //------------------------------------------------------------------ - // State machine to control the data from GPMC to BRAM - //------------------------------------------------------------------ - always @(negedge EM_CLK or posedge arst) begin - if (arst) begin - gpmc_state <= GPMC_STATE_START; - gpmc_ptr <= 0; - next_gpmc_ptr <= 0; - addr <= 0; - end - else if (EM_WE) begin - addr <= EM_A + 1; - case(gpmc_state) - - GPMC_STATE_START: begin - if (EM_A == 0) begin - gpmc_state <= GPMC_STATE_FILL; - next_gpmc_ptr <= gpmc_ptr + 1; - end - end - - GPMC_STATE_FILL: begin - if (addr == LAST_ADDR) begin - gpmc_state <= GPMC_STATE_START; - gpmc_ptr <= next_gpmc_ptr; - addr <= 0; - end - end - - endcase //gpmc_state - end //EM_WE - end //always - - //------------------------------------------------------------------ - // A block ram is available to empty when the pointers dont match. - //------------------------------------------------------------------ - wire [PTR_WIDTH:0] safe_gpmc_ptr; - cross_clock_reader #(.WIDTH(PTR_WIDTH+1)) read_gpmc_ptr - (.clk(clk), .rst(reset | clear), .in(gpmc_ptr), .out(safe_gpmc_ptr)); - - wire bram_available_to_empty = safe_gpmc_ptr != fifo_ptr; - - //------------------------------------------------------------------ - // Glich free generation of have space signal: - // High when the fifo pointer has not caught up to the gpmc pointer. - //------------------------------------------------------------------ - wire [PTR_WIDTH:0] safe_next_gpmc_ptr; - cross_clock_reader #(.WIDTH(PTR_WIDTH+1)) read_next_gpmc_ptr - (.clk(clk), .rst(reset | clear), .in(next_gpmc_ptr), .out(safe_next_gpmc_ptr)); - - wire [PTR_WIDTH:0] fifo_ptr_next = fifo_ptr + 1; - always @(posedge clk) - if (reset | clear) have_space <= 0; - else have_space <= (fifo_ptr ^ (1 << PTR_WIDTH)) != safe_next_gpmc_ptr; - - //------------------------------------------------------------------ - // State machine to control the data from BRAM to FIFO - //------------------------------------------------------------------ - always @(posedge clk) begin - if (reset | clear) begin - fifo_state <= FIFO_STATE_CLAIM; - fifo_ptr <= 0; - counter <= 0; - end - else begin - case(fifo_state) - - FIFO_STATE_CLAIM: begin - if (bram_available_to_empty && data_o[16]) fifo_state <= FIFO_STATE_PRE; - counter <= 0; - end - - FIFO_STATE_PRE: begin - fifo_state <= FIFO_STATE_EMPTY; - counter <= counter + 1; - end - - FIFO_STATE_EMPTY: begin - if (src_rdy_o && dst_rdy_i && data_o[17]) begin - fifo_state <= FIFO_STATE_CLAIM; - fifo_ptr <= fifo_ptr + 1; - counter <= 0; - end - else if (src_rdy_o && dst_rdy_i) begin - counter <= counter + 1; - end - end - - endcase //fifo_state - end - end //always - - wire enable = (fifo_state != FIFO_STATE_EMPTY) || dst_rdy_i; - - assign src_rdy_o = fifo_state == FIFO_STATE_EMPTY; - - //instantiate dual ported bram for async read + write - ram_2port #(.DWIDTH(16),.AWIDTH(PTR_WIDTH + ADDR_WIDTH)) async_fifo_bram - (.clka(~EM_CLK),.ena(1'b1),.wea(EM_WE), - .addra({gpmc_ptr[PTR_WIDTH-1:0], addr}),.dia(EM_D),.doa(), - .clkb(clk),.enb(enable),.web(1'b0), - .addrb({fifo_ptr[PTR_WIDTH-1:0], counter}),.dib(18'h3ffff),.dob(data_o[15:0])); - - //store the vita length -> last xfer count - always @(posedge clk) begin - if (src_rdy_o && dst_rdy_i && data_o[16]) begin - last_xfer <= {data_o[ADDR_WIDTH-2:0], 1'b0}; - end - end - - //logic for start and end of frame - always @(posedge clk) if (enable) last_counter <= counter; - assign data_o[17] = !data_o[16] && ((last_counter + 1'b1) == last_xfer); - assign data_o[16] = last_counter == 0; - -endmodule // gpmc_to_fifo diff --git a/fpga/usrp2/models/BUFG.v b/fpga/usrp2/models/BUFG.v deleted file mode 100644 index a935c6285..000000000 --- a/fpga/usrp2/models/BUFG.v +++ /dev/null @@ -1,33 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFG.v,v 1.5 2005/03/14 22:32:51 yanx Exp $ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2004 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 8.1i (I.13) -// \ \ Description : Xilinx Functional Simulation Library Component -// / / Global Clock Buffer -// /___/ /\ Filename : BUFG.v -// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004 -// \___\/\___\ -// -// Revision: -// 03/23/04 - Initial version. -// End Revision - -`timescale 100 ps / 10 ps - - -module BUFG (O, I); - - output O; - - input I; - - buf B1 (O, I); - - -endmodule - diff --git a/fpga/usrp2/models/CY7C1356C/cy1356.inp b/fpga/usrp2/models/CY7C1356C/cy1356.inp deleted file mode 100644 index a55ffac39..000000000 --- a/fpga/usrp2/models/CY7C1356C/cy1356.inp +++ /dev/null @@ -1,140 +0,0 @@ -/*Address inputs only 0=LOW - "Data is in HEX, four bytes (LSB,MSB)" 1=HIGH - ZZZZZZZZZZZZZZZZ=Tri-state G-WRITE = Global Write - XXXXXXXXXXXXXXXX= Don't care B-WRITE = Byte Write - YYYY=unknown BG-WRITE = BURST GLOBAL WRITE - BB-WRITE = BURST BYTE WRITE - -*/ -// CE3# BW2# ADV/LD# -// CEN# CE2 WE# -// Add IN OUT CE1# BW1# -0000000000000000_XXXXXXXXXXXXXXXX_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0 -0000000000000001_XXXXXXXXXXXXXXXX_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0 -0000000000000010_0000000000000000_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0 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-0000000000000001_xxxxxxxxxxxxxxxx_0001000100010001_0_0_1_0_0_1_1_0 -0000000000000001_0001XXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0_0_1_0_0_0_1_0 -0000000000000001_XXXX0010XXXXXXXX_xxxxxxxxxxxxxxxx_0_0_1_0_0_1_0_0 -0000000000000001_XXXXXXXX0011XXXX_xxxxxxxxxxxxxxxx_0_0_1_0_1_X_X_0 -0000000000000000_XXXXXXXXXXXX0100_xxxxxxxxxxxxxxxx_0_0_1_0_1_X_X_0 -XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0001001000110100_0_X_X_X_X_X_X_1 -XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0110011001100110_0_X_X_X_X_X_X_1 -XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0001001000110100_0_X_X_X_X_X_X_1 -XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0010001000100010_0_1_X_X_X_X_X_0 -xxxxxxxxxxxxxxxx_xxxxxxxxxxxxxxxx_0011001100110011_0_1_x_x_x_x_x_x -xxxxxxxxxxxxxxxx_xxxxxxxxxxxxxxxx_ZZZZZZZZZZZZZZZZ_0_1_x_x_x_x_x_x -//Lines =126 - - diff --git a/fpga/usrp2/models/CY7C1356C/cy1356.v b/fpga/usrp2/models/CY7C1356C/cy1356.v deleted file mode 100644 index ab7ace610..000000000 --- a/fpga/usrp2/models/CY7C1356C/cy1356.v +++ /dev/null @@ -1,502 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -`define sb200 -//************************************************************************ -//************************************************************************ -//** This model is the property of Cypress Semiconductor Corp and is ** -//** protected by the US copyright laws, any unauthorized copying and ** -//** distribution is prohibited. Cypress reserves the right to change ** -//** any of the functional specifications without any prior notice. ** -//** Cypress is not liable for any damages which may result from the ** -//** use of this functional model. ** -//** ** -//** File Name : CY7C1356 ** -//** ** -//** Revision : 1.0 - 08/03/2004 ** -//** ** -//** The timings are to be selected by the user depending upon the ** -//** frequency of operation from the datasheet. ** -//** ** -//** Model : CY7C1356C - NoBL Pipelined SRAM ** -//** Queries : MPD Applications ** -//** Website: www.cypress.com/support ** -//************************************************************************ -//************************************************************************ - -`timescale 1ns / 10ps - -// NOTE : Any setup/hold errors will force input signal to x state -// or if results indeterminant (write addr) core is reset x - -// define fixed values - -`define wordsize (18 -1) // -`define no_words (1048576 -1) // 1M x 18 RAM - -module cy1356 ( d, clk, a, bws, we_b, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode); - -inout [`wordsize:0] d; -input clk, // clock input (R) - we_b, // byte write enable(L) - adv_lb, // burst(H)/load(L) address - ce1b, // chip enable(L) - ce2, // chip enable(H) - ce3b, // chip enable(L) - oeb, // async output enable(L)(read) - cenb, // clock enable(L) - mode; // interleave(H)/linear(L) burst -input [1:0] bws; // byte write select(L) -input [18:0] a; // address bus - -// *** NOTE DEVICE OPERATES #0.01 AFTER CLOCK *** -// *** THEREFORE DELAYS HAVE TO TAKE THIS INTO ACCOUNT *** - - -//********************************************************************** -// Timings for 225MHz -//********************************************************************** -`ifdef sb225 - `define teohz #2.8 - `define teolz #0 - `define tchz #2.8 - `define tclz #1.25 - - `define tco #2.8 - `define tdoh #1.25 - `define tas 1.4 - `define tah 0.4 -`endif -//*********************************************************************** -// Timings for 200MHz -//********************************************************************** -`ifdef sb200 - `define teohz #3.2 - `define teolz #0 - `define tchz #3.2 - `define tclz #1.5 - - `define tco #3.2 - `define tdoh #1.5 - - `define tas 1.5 - `define tah 0.5 -`endif -//*********************************************************************** - -//********************************************************************** -// This model is configured for 166 MHz Operation (CY7C1356-166). -//********************************************************************** -`ifdef sb166 - `define teohz #3.5 - `define teolz #0 - `define tchz #3.5 - `define tclz #1.5 - - `define tco #3.5 - `define tdoh #1.5 - - `define tas 1.5 - `define tah 0.5 -`endif - -reg notifier; // error support reg's -reg noti1_0; -reg noti1_1; -reg noti1_2; -reg noti1_3; -reg noti1_4; -reg noti1_5; -reg noti1_6; -reg noti2; - - -wire chipen; // combined chip enable (high for an active chip) - -reg chipen_d; // _d = delayed -reg chipen_o; // _o = operational = delayed sig or _d sig - -wire writestate; // holds 1 if any of writebus is low -reg writestate_d; -reg writestate_o; - -wire loadcyc; // holds 1 for load cycles (setup and hold checks) -wire writecyc; // holds 1 for write cycles (setup and hold checks) -wire [1:0] bws; // holds the bws values - -wire [1:0] writebusb; // holds the "internal" bws bus based on we_b -reg [1:0] writebusb_d; -reg [1:0] writebusb_o; - -wire [2:0] operation; // holds chipen, adv_ld and writestate -reg [2:0] operation_d; -reg [2:0] operation_o; - -wire [18:0] a; // address input bus -reg [18:0] a_d; -reg [18:0] a_o; - -reg [`wordsize:0] do; // data output reg -reg [`wordsize:0] di; // data input bus -reg [`wordsize:0] dd; // data delayed bus - -wire tristate; // tristate output (on a bytewise basis) when asserted -reg cetri; // register set by chip disable which sets the tristate -reg oetri; // register set by oe which sets the tristate -reg enable; // register to make the ram enabled when equal to 1 -reg [18:0] addreg; // register to hold the input address -reg [`wordsize:0] pipereg; // register for the output data - -reg [`wordsize:0] mem [0:`no_words]; // RAM array - -reg [`wordsize:0] writeword; // temporary holding register for the write data -reg burstinit; // register to hold a[0] for burst type -reg [18:0] i; // temporary register used to write to all mem locs. -reg writetri; // tristate -reg lw, bw; // pipelined write functions -reg we_bl; - - -wire [`wordsize:0] d = !tristate ? do[`wordsize:0] : 18'bz ; // data bus - -assign chipen = (adv_lb == 1 ) ? chipen_d : - ~ce1b & ce2 & ~ce3b ; - -assign writestate = ~& writebusb; - -assign operation = {chipen, adv_lb, writestate}; - -assign writebusb[1:0] = ( we_b ==0 & adv_lb ==0) ? bws[1:0]: - ( we_b ==1 & adv_lb ==0) ? 2'b11 : - ( we_bl ==0 & adv_lb ==1) ? bws[1:0]: - ( we_bl ==1 & adv_lb ==1) ? 2'b11 : - 2'bxx ; - -assign loadcyc = chipen & !cenb; - -assign writecyc = writestate_d & enable & ~cenb & chipen; // check - -assign tristate = cetri | writetri | oetri; - -pullup (mode); - -// formers for notices/errors etc -// -//$display("NOTICE : xxx :"); -//$display("WARNING : xxx :"); -//$display("ERROR *** : xxx :"); - - -// initialize the output to be tri-state, ram to be disabled - -initial - begin -// signals - - writetri = 0; - cetri = 1; - enable = 0; - lw = 0; - bw = 0; - -// error signals - - notifier = 0; - noti1_0 = 0; - noti1_1 = 0; - noti1_2 = 0; - noti1_3 = 0; - noti1_4 = 0; - noti1_5 = 0; - noti1_6 = 0; - noti2 = 0; - -end - - - -// asynchronous OE - -always @(oeb) -begin - if (oeb == 1) - oetri <= `teohz 1; - else - oetri <= `teolz 0; -end - -// *** SETUP / HOLD VIOLATIONS *** - -always @(noti2) -begin -$display("NOTICE : 020 : Data bus corruption"); - force d =18'bx; - #1; - release d; -end - -always @(noti1_0) -begin -$display("NOTICE : 010 : Byte write corruption"); - force bws = 2'bx; - #1; - release bws; -end - -always @(noti1_1) -begin -$display("NOTICE : 011 : Byte enable corruption"); - force we_b = 1'bx; - #1; - release we_b; -end - -always @(noti1_2) -begin -$display("NOTICE : 012 : CE1B corruption"); - force ce1b =1'bx; - #1; - release ce1b; -end - -always @(noti1_3) -begin -$display("NOTICE : 013 : CE2 corruption"); - force ce2 =1'bx; - #1; - release ce2; -end - -always @(noti1_4) -begin -$display("NOTICE : 014 : CE3B corruption"); - force ce3b =1'bx; - #1; - release ce3b; -end - -always @(noti1_5) -begin -$display("NOTICE : 015 : CENB corruption"); - force cenb =1'bx; - #1; - release cenb; -end - -always @(noti1_6) -begin -$display("NOTICE : 016 : ADV_LB corruption"); - force adv_lb = 1'bx; - #1; - release adv_lb; -end - -// synchronous functions from clk edge - -always @(posedge clk) -if (!cenb) -begin -#0.01; - // latch conditions on adv_lb - - if (adv_lb) - we_bl <= we_bl; - else - we_bl <= we_b; - - chipen_d <= chipen; - - - chipen_o <= chipen; - writestate_o <= writestate; - writestate_d <= writestate_o; - writebusb_o <= writebusb; - writebusb_d <= writebusb_o; - operation_o <= operation; - a_o <= a; - a_d <= a_o; - di = d; - - // execute previously pipelined fns - - if (lw) begin - loadwrite; - lw =0; - end - - if (bw) begin - burstwrite; - bw =0; - end - - // decode input/piplined state - - casex (operation_o) - 3'b0?? : turnoff; - 3'b101 : setlw; - 3'b111 : setbw; - 3'b100 : loadread; - 3'b110 : burstread; - default : unknown; // output unknown values and display an error message - endcase - - do <= `tco pipereg; - -end - -// *** task section *** - -task read; -begin - if (enable) cetri <= `tclz 0; - writetri <= `tchz 0; - do <= `tdoh 18'hx; - pipereg = mem[addreg]; -end -endtask - -task write; -begin - if (enable) cetri <= `tclz 0; - writeword = mem[addreg]; // set up a word to hold the data for the current location - /* overwrite the current word for the bytes being written to */ - if (!writebusb_d[1]) writeword[17:9] = di[17:9]; - if (!writebusb_d[0]) writeword[8:0] = di[8:0]; - writeword = writeword & writeword; //convert z to x states - mem[addreg] = writeword; // store the new word into the memory location - //writetri <= `tchz 1; // tristate the outputs -end -endtask - -task setlw; -begin - lw =1; - writetri <= `tchz 1; // tristate the outputs -end -endtask - -task setbw; -begin - bw =1; - writetri <= `tchz 1; // tristate the outputs -end -endtask - -task loadread; -begin - burstinit = a_o[0]; - addreg = a_o; - enable = 1; - read; -end -endtask - -task loadwrite; -begin - burstinit = a_d[0]; - addreg = a_d; - enable = 1; - write; -end -endtask - -task burstread; -begin - burst; - read; -end -endtask - -task burstwrite; -begin - burst; - write; -end -endtask - -task unknown; -begin - do = 18'bx; - // $display ("Unknown function: Operation = %b\n", operation); -end -endtask - -task turnoff; -begin - enable = 0; - cetri <= `tchz 1; - pipereg = 18'h0; -end -endtask - -task burst; -begin - if (burstinit == 0 || mode == 0) - begin - case (addreg[1:0]) - 2'b00: addreg[1:0] = 2'b01; - 2'b01: addreg[1:0] = 2'b10; - 2'b10: addreg[1:0] = 2'b11; - 2'b11: addreg[1:0] = 2'b00; - default: addreg[1:0] = 2'bxx; - endcase - end - else - begin - case (addreg[1:0]) - 2'b00: addreg[1:0] = 2'b11; - 2'b01: addreg[1:0] = 2'b00; - 2'b10: addreg[1:0] = 2'b01; - 2'b11: addreg[1:0] = 2'b10; - default: addreg[1:0] = 2'bxx; - endcase - end -end -endtask - -// IO checks - -specify -// specify the setup and hold checks - -// notifier will wipe memory as result is indeterminent - -$setuphold(posedge clk &&& loadcyc, a, `tas, `tah, notifier); - -// noti1 should make ip = 'bx; - -$setuphold(posedge clk, bws, `tas, `tah, noti1_0); - -$setuphold(posedge clk, we_b, `tas, `tah, noti1_1); -$setuphold(posedge clk, ce1b, `tas, `tah, noti1_2); -$setuphold(posedge clk, ce2, `tas, `tah, noti1_3); -$setuphold(posedge clk, ce3b, `tas, `tah, noti1_4); - -// noti2 should make d = 18'hxxxxx; - -$setuphold(posedge clk &&& writecyc, d, `tas, `tah, noti2); - -// add extra tests here. - -$setuphold(posedge clk, cenb, `tas, `tah, noti1_5); -$setuphold(posedge clk, adv_lb, `tas, `tah, noti1_6); - -endspecify - -endmodule - - diff --git a/fpga/usrp2/models/CY7C1356C/readme.txt b/fpga/usrp2/models/CY7C1356C/readme.txt deleted file mode 100644 index 3578c80dc..000000000 --- a/fpga/usrp2/models/CY7C1356C/readme.txt +++ /dev/null @@ -1,33 +0,0 @@ -*************************** -Cypress Semiconductor -MPD Applications -Verilog model for NoBL SRAM CY7C1356 -Created: August 04, 2004 -Rev: 1.0 -*************************** - -This is the verilog model for the CY7C1356 along with the testbench and test vectors. - -Contact support@cypress.com if you have any questions. - -This directory has 4 files. including this readme. - -1)cy7c1356c.v -> Verilog model for CY7C1356c - -2)cy1356.inp -> Test Vector File used for testing the verilog model - -3)testbench.v -> Test bench used for testing the verilog model - - -COMPILING METHOD : ------------------- - - verilog +define+
- - Ex: - verilog +define+sb133 CY7C1356c.v testbench.v - -VERIFIED WITH: --------------- - -VERILOG-XL 2.2 \ No newline at end of file diff --git a/fpga/usrp2/models/CY7C1356C/testbench.v b/fpga/usrp2/models/CY7C1356C/testbench.v deleted file mode 100644 index 01e0cbe00..000000000 --- a/fpga/usrp2/models/CY7C1356C/testbench.v +++ /dev/null @@ -1,206 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -`timescale 1ns / 10ps - - -// -// CY7C1356 -// Simulatiom of Verilog model -// -// - -// -// test bench for US vector input -// -// - -// define speed 166MHz - -`define tx10 #6 -`define tx08 #4.8 -`define tx05 #3 -`define tx04 #2.4 -`define tx02 #1.2 - -/* -`define tx10 #4.0 // period -`define tx08 #3.2 //0.8 period -`define tx05 #2.0 //0.5 period 250MHZ -`define tx04 #1.6 //0.4 period -`define tx02 #0.8 //0.2 period - -`define tx10 #4.4 // period -`define tx08 #3.52 //0.8 period -`define tx05 #2.2 //0.5 period 225MHZ -`define tx04 #1.76 //0.4 period -`define tx02 #0.88 //0.2 period - -`define tx10 #5 // period -`define tx08 #4 //0.8 period -`define tx05 #2.5 //0.5 period 200MHZ -`define tx04 #2.0 //0.4 period -`define tx02 #1.0 //0.2 period -*/ - - -module rw_test; - -`define num_vectors 126 -`define impi {a[15:0],io[15:0],tsti[15:0],cenb,ce1b,ce2,ce3b,bweb,bwb,adv_lb} - - -reg [57:1] lsim_vectors [1:`num_vectors]; - - -reg clk; -reg adv_lb; -reg ce1b; //cs1b -reg ce2; //cs2 -reg ce3b; //cs3b -reg [1:0] bwb; -reg bweb; -reg oeb; -reg ftb; -reg mode; //lbob -reg cenb; //zz -reg tp42; //sclk -reg tp39; //se -reg tp38; //tm -reg [19:0] a; -reg [17:0] io; -reg [17:0] tsti; -reg vddq; -reg vssqr; -reg iosel; - - -wire [17:0] d = iosel ? io[17:0] : 18'bz; - -reg noti3; -reg strb,j; -integer vector,i; - - - -cy1356 testram ( d, clk, a, bwb, bweb, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode); - -initial -begin - $dumpfile("dumpfile.dump"); - $dumpvars(0,rw_test); -end - -initial -begin -io = 18'bz; -ftb = 1; -oeb = 0; -a[19:16] = 4'h0; -mode = 0; -strb = 0; -tp38 = 0; -tp39 = 0; -tp42 = 0; -`tx02; -forever `tx05 strb = ~strb; -end - -initial -begin -clk = 0; -forever `tx05 clk =~clk; -end - -initial - begin - - $readmemb("cy1356.inp", lsim_vectors); //load input vector file - - `impi = lsim_vectors[1]; //apply 1st test vector - - for (vector = 2; vector <= `num_vectors; vector = vector + 1) - @(posedge strb) - begin - - `impi = lsim_vectors[vector]; - - - - io[16:13] = io[07:04]; - io[12:09] = io[07:04]; - io[07:04] = io[03:00]; - io[03:00] = io[03:00]; - - io[17] = io[16] ^^ io[15] ^^ io[14] ^^ io[13] ^^ io[11] ^^ io[11] ^^ io[10] ^^ io[9]; - io[8] = io[7] ^^ io[6] ^^ io[5] ^^ io[4] ^^ io[3] ^^ io[2] ^^ io[1] ^^ io[0]; - - tsti[16:13] = tsti[07:04]; - tsti[12:09] = tsti[07:04]; - tsti[07:04] = tsti[03:00]; - tsti[03:00] = tsti[03:00]; - - tsti[17] = tsti[16] ^^ tsti[15] ^^ tsti[14] ^^ tsti[13] ^^ tsti[11] ^^ tsti[11] ^^ tsti[10] ^^ tsti[9]; - tsti[8] = tsti[7] ^^ tsti[6] ^^ tsti[5] ^^ tsti[4] ^^ tsti[3] ^^ tsti[2] ^^ tsti[1] ^^ tsti[0]; - - if (io === 18'hxxxxx) - iosel = `tx05 0; - else - iosel = `tx05 1; - - end - #15 $finish; // This prevents simulation beyond end of test patterns - end - -always@(posedge clk) -begin - - if (io !== 18'hxxxxx) //input cycle - begin - $display("NOTICE : 001 : line = %d OK",vector -1); - end - else //do the test - begin - if (d == tsti) - begin - $display("NOTICE : 002 : line = %d OK",vector -1); - end - else - begin - j =0; - for (i =0;i< 18; i=i+1) - begin - if(tsti[i] !== 1'bx) - begin - if (d[i] !== tsti[i]) j = 1; - end - else - j = 0; - end - if (j) - $display("ERROR *** : 003 : line = %d data = %b test = %b",vector -1,d,tsti); - else - $display("NOTICE : 003 : line = %d OK",vector -1); - end - end -end - -endmodule - - - - diff --git a/fpga/usrp2/models/DCM_SP.v b/fpga/usrp2/models/DCM_SP.v deleted file mode 100644 index 2142fa736..000000000 --- a/fpga/usrp2/models/DCM_SP.v +++ /dev/null @@ -1,1244 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/DCM_SP.v,v 1.9.4.3 2007/04/11 20:30:19 yanx Exp $ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2004 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 9.2i (J.36) -// \ \ Description : Xilinx Function Simulation Library Component -// / / Digital Clock Manager -// /___/ /\ Filename : DCM_SP.v -// \ \ / \ Timestamp : -// \___\/\___\ -// -// Revision: -// 02/28/06 - Initial version. -// 05/09/06 - Add clkin_ps_mkup and clkin_ps_mkup_win for phase shifting (CR 229789). -// 06/14/06 - Add clkin_ps_mkup_flag for multiple cycle delays (CR233283). -// 07/21/06 - Change range of variable phase shifting to +/- integer of 20*(Period-3ns). -// Give warning not support initial phase shifting for variable phase shifting. -// (CR 235216). -// 09/22/06 - Add lock_period and lock_fb to clkfb_div block (CR 418722). -// 12/19/06 - Add clkfb_div_en for clkfb2x divider (CR431210). -// 04/06/07 - Enable the clock out in clock low time after reset in model -// clock_divide_by_2 (CR 437471). -// End Revision - - -`timescale 1 ps / 1 ps - -module DCM_SP ( - CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, - CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS, - CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST); - -parameter CLKDV_DIVIDE = 2.0; -parameter integer CLKFX_DIVIDE = 1; -parameter integer CLKFX_MULTIPLY = 4; -parameter CLKIN_DIVIDE_BY_2 = "FALSE"; -parameter CLKIN_PERIOD = 10.0; // non-simulatable -parameter CLKOUT_PHASE_SHIFT = "NONE"; -parameter CLK_FEEDBACK = "1X"; -parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; // non-simulatable -parameter DFS_FREQUENCY_MODE = "LOW"; -parameter DLL_FREQUENCY_MODE = "LOW"; -parameter DSS_MODE = "NONE"; // non-simulatable -parameter DUTY_CYCLE_CORRECTION = "TRUE"; -parameter FACTORY_JF = 16'hC080; // non-simulatable -parameter integer MAXPERCLKIN = 1000000; // non-modifiable simulation parameter -parameter integer MAXPERPSCLK = 100000000; // non-modifiable simulation parameter -parameter integer PHASE_SHIFT = 0; -parameter integer SIM_CLKIN_CYCLE_JITTER = 300; // non-modifiable simulation parameter -parameter integer SIM_CLKIN_PERIOD_JITTER = 1000; // non-modifiable simulation parameter -parameter STARTUP_WAIT = "FALSE"; // non-simulatable - - -localparam PS_STEP = 25; - -input CLKFB, CLKIN, DSSEN; -input PSCLK, PSEN, PSINCDEC, RST; - -output CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90; -output CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE; -output [7:0] STATUS; - -reg CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90; -reg CLKDV, CLKFX, CLKFX180; - -wire locked_out_out; -wire clkfb_in, clkin_in, dssen_in; -wire psclk_in, psen_in, psincdec_in, rst_in; -reg clk0_out; -reg clk2x_out, clkdv_out; -reg clkfx_out, clkfx180_en; -reg rst_flag; -reg locked_out, psdone_out, ps_overflow_out, ps_lock; -reg clkfb_div, clkfb_chk, clkfb_div_en; -integer clkdv_cnt; - -reg [1:0] clkfb_type; -reg [8:0] divide_type; -reg clkin_type; -reg [1:0] ps_type; -reg [3:0] deskew_adjust_mode; -reg dfs_mode_type; -reg dll_mode_type; -reg clk1x_type; -integer ps_in; - -reg lock_period, lock_delay, lock_clkin, lock_clkfb; -reg first_time_locked; -reg en_status; -reg ps_overflow_out_ext; -reg clkin_lost_out_ext; -reg clkfx_lost_out_ext; -reg [1:0] lock_out; -reg lock_out1_neg; -reg lock_fb, lock_ps, lock_ps_dly, lock_fb_dly, lock_fb_dly_tmp; -reg fb_delay_found; -reg clock_stopped; -reg clkin_chkin, clkfb_chkin; - -wire chk_enable, chk_rst; -wire clkin_div; -wire lock_period_pulse; -wire lock_period_dly, lock_period_dly1; - -reg clkin_ps, clkin_ps_tmp, clkin_ps_mkup, clkin_ps_mkup_win, clkin_ps_mkup_flag; -reg clkin_fb; - -time FINE_SHIFT_RANGE; -//time ps_delay, ps_delay_init, ps_delay_md, ps_delay_all, ps_max_range; -integer ps_delay, ps_delay_init, ps_delay_md, ps_delay_all, ps_max_range; -integer ps_delay_last; -integer ps_acc; -time clkin_edge; -time clkin_div_edge; -time clkin_ps_edge; -time delay_edge; -time clkin_period [2:0]; -time period; -integer period_int, period_int2, period_int3, period_ps_tmp; -time period_div; -integer period_orig_int; -time period_orig; -time period_ps; -time clkout_delay; -time fb_delay; -time period_fx, remain_fx; -time period_dv_high, period_dv_low; -time cycle_jitter, period_jitter; - -reg clkin_window, clkfb_window; -reg [2:0] rst_reg; -reg [12:0] numerator, denominator, gcd; -reg [23:0] i, n, d, p; - -reg notifier; - -initial begin - #1; - if ($realtime == 0) begin - $display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps."); - $display ("In order to simulate the DCM_SP, the simulator resolution must be set to 1ps or smaller."); - $finish; - end -end - -initial begin - case (2.0) - 1.5 : divide_type = 'd3; - 2.0 : divide_type = 'd4; - 2.5 : divide_type = 'd5; - 3.0 : divide_type = 'd6; - 3.5 : divide_type = 'd7; - 4.0 : divide_type = 'd8; - 4.5 : divide_type = 'd9; - 5.0 : divide_type = 'd10; - 5.5 : divide_type = 'd11; - 6.0 : divide_type = 'd12; - 6.5 : divide_type = 'd13; - 7.0 : divide_type = 'd14; - 7.5 : divide_type = 'd15; - 8.0 : divide_type = 'd16; - 9.0 : divide_type = 'd18; - 10.0 : divide_type = 'd20; - 11.0 : divide_type = 'd22; - 12.0 : divide_type = 'd24; - 13.0 : divide_type = 'd26; - 14.0 : divide_type = 'd28; - 15.0 : divide_type = 'd30; - 16.0 : divide_type = 'd32; - default : begin - $display("Attribute Syntax Error : The attribute CLKDV_DIVIDE on DCM_SP instance %m is set to %0.1f. Legal values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0.", CLKDV_DIVIDE); - $finish; - end - endcase - - if ((CLKFX_DIVIDE <= 0) || (32 < CLKFX_DIVIDE)) begin - $display("Attribute Syntax Error : The attribute CLKFX_DIVIDE on DCM_SP instance %m is set to %d. Legal values for this attribute are 1 ... 32.", CLKFX_DIVIDE); - $finish; - end - - if ((CLKFX_MULTIPLY <= 1) || (32 < CLKFX_MULTIPLY)) begin - $display("Attribute Syntax Error : The attribute CLKFX_MULTIPLY on DCM_SP instance %m is set to %d. Legal values for this attribute are 2 ... 32.", CLKFX_MULTIPLY); - $finish; - end - - case (CLKIN_DIVIDE_BY_2) - "false" : clkin_type = 0; - "FALSE" : clkin_type = 0; - "true" : clkin_type = 1; - "TRUE" : clkin_type = 1; - default : begin - $display("Attribute Syntax Error : The attribute CLKIN_DIVIDE_BY_2 on DCM_SP instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKIN_DIVIDE_BY_2); - $finish; - end - endcase - - case (CLKOUT_PHASE_SHIFT) - "NONE" : begin - ps_in = 256; - ps_type = 0; - end - "none" : begin - ps_in = 256; - ps_type = 0; - end - "FIXED" : begin - ps_in = PHASE_SHIFT + 256; - ps_type = 1; - end - "fixed" : begin - ps_in = PHASE_SHIFT + 256; - ps_type = 1; - end - "VARIABLE" : begin - ps_in = PHASE_SHIFT + 256; - ps_type = 2; - end - "variable" : begin - ps_in = PHASE_SHIFT + 256; - ps_type = 2; - if (PHASE_SHIFT != 0) - $display("Attribute Syntax Warning : The attribute PHASE_SHIFT on DCM_SP instance %m is set to %d. The maximum variable phase shift range is only valid when initial phase shift PHASE_SHIFT is zero.", PHASE_SHIFT); - end - default : begin - $display("Attribute Syntax Error : The attribute CLKOUT_PHASE_SHIFT on DCM_SP instance %m is set to %s. Legal values for this attribute are NONE, FIXED or VARIABLE.", CLKOUT_PHASE_SHIFT); - $finish; - end - endcase - - - case (CLK_FEEDBACK) - "none" : clkfb_type = 2'b00; - "NONE" : clkfb_type = 2'b00; - "1x" : clkfb_type = 2'b01; - "1X" : clkfb_type = 2'b01; - "2x" : clkfb_type = 2'b10; - "2X" : clkfb_type = 2'b10; - default : begin - $display("Attribute Syntax Error : The attribute CLK_FEEDBACK on DCM_SP instance %m is set to %s. Legal values for this attribute are NONE, 1X or 2X.", CLK_FEEDBACK); - $finish; - end - endcase - - case (DESKEW_ADJUST) - "source_synchronous" : deskew_adjust_mode = 8; - "SOURCE_SYNCHRONOUS" : deskew_adjust_mode = 8; - "system_synchronous" : deskew_adjust_mode = 11; - "SYSTEM_SYNCHRONOUS" : deskew_adjust_mode = 11; - "0" : deskew_adjust_mode = 0; - "1" : deskew_adjust_mode = 1; - "2" : deskew_adjust_mode = 2; - "3" : deskew_adjust_mode = 3; - "4" : deskew_adjust_mode = 4; - "5" : deskew_adjust_mode = 5; - "6" : deskew_adjust_mode = 6; - "7" : deskew_adjust_mode = 7; - "8" : deskew_adjust_mode = 8; - "9" : deskew_adjust_mode = 9; - "10" : deskew_adjust_mode = 10; - "11" : deskew_adjust_mode = 11; - "12" : deskew_adjust_mode = 12; - "13" : deskew_adjust_mode = 13; - "14" : deskew_adjust_mode = 14; - "15" : deskew_adjust_mode = 15; - default : begin - $display("Attribute Syntax Error : The attribute DESKEW_ADJUST on DCM_SP instance %m is set to %s. Legal values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 0 ... 15.", DESKEW_ADJUST); - $finish; - end - endcase - - case (DFS_FREQUENCY_MODE) - "high" : dfs_mode_type = 1; - "HIGH" : dfs_mode_type = 1; - "low" : dfs_mode_type = 0; - "LOW" : dfs_mode_type = 0; - default : begin - $display("Attribute Syntax Error : The attribute DFS_FREQUENCY_MODE on DCM_SP instance %m is set to %s. Legal values for this attribute are HIGH or LOW.", DFS_FREQUENCY_MODE); - $finish; - end - endcase - - period_jitter = SIM_CLKIN_PERIOD_JITTER; - cycle_jitter = SIM_CLKIN_CYCLE_JITTER; - - case (DLL_FREQUENCY_MODE) - "high" : dll_mode_type = 1; - "HIGH" : dll_mode_type = 1; - "low" : dll_mode_type = 0; - "LOW" : dll_mode_type = 0; - default : begin - $display("Attribute Syntax Error : The attribute DLL_FREQUENCY_MODE on DCM_SP instance %m is set to %s. Legal values for this attribute are HIGH or LOW.", DLL_FREQUENCY_MODE); - $finish; - end - endcase - - if ((dll_mode_type ==1) && (clkfb_type == 2'b10)) begin - $display("Attribute Syntax Error : The attributes DLL_FREQUENCY_MODE on DCM_SP instance %m is set to %s and CLK_FEEDBACK is set to %s. CLK_FEEDBACK 2X is not supported when DLL_FREQUENCY_MODE is HIGH.", DLL_FREQUENCY_MODE, CLK_FEEDBACK); - $finish; - end - - case (DSS_MODE) - "none" : ; - "NONE" : ; - default : begin - $display("Attribute Syntax Error : The attribute DSS_MODE on DCM_SP instance %m is set to %s. Legal values for this attribute is NONE.", DSS_MODE); - $finish; - end - endcase - - case (DUTY_CYCLE_CORRECTION) - "false" : clk1x_type = 0; - "FALSE" : clk1x_type = 0; - "true" : clk1x_type = 1; - "TRUE" : clk1x_type = 1; - default : begin - $display("Attribute Syntax Error : The attribute DUTY_CYCLE_CORRECTION on DCM_SP instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DUTY_CYCLE_CORRECTION); - $finish; - end - endcase - - if ((PHASE_SHIFT < -255) || (PHASE_SHIFT > 255)) begin - $display("Attribute Syntax Error : The attribute PHASE_SHIFT on DCM_SP instance %m is set to %d. Legal values for this attribute are -255 ... 255.", PHASE_SHIFT); - $display("Error : PHASE_SHIFT = %d is not -255 ... 255.", PHASE_SHIFT); - $finish; - end - - case (STARTUP_WAIT) - "false" : ; - "FALSE" : ; - "true" : ; - "TRUE" : ; - default : begin - $display("Attribute Syntax Error : The attribute STARTUP_WAIT on DCM_SP instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", STARTUP_WAIT); - $finish; - end - endcase -end - -// -// fx parameters -// - -initial begin - gcd = 1; - for (i = 2; i <= CLKFX_MULTIPLY; i = i + 1) begin - if (((CLKFX_MULTIPLY % i) == 0) && ((CLKFX_DIVIDE % i) == 0)) - gcd = i; - end - numerator = CLKFX_MULTIPLY / gcd; - denominator = CLKFX_DIVIDE / gcd; -end - -// -// input wire delays -// - -buf b_clkin (clkin_in, CLKIN); -buf b_clkfb (clkfb_in, CLKFB); -buf b_dssen (dssen_in, DSSEN); -buf b_psclk (psclk_in, PSCLK); -buf b_psen (psen_in, PSEN); -buf b_psincdec (psincdec_in, PSINCDEC); -buf b_rst (rst_in, RST); -buf #100 b_LOCKED (LOCKED, locked_out_out); -buf #100 b_PSDONE (PSDONE, psdone_out); -buf b_ps_overflow (STATUS[0], ps_overflow_out_ext); -buf b_clkin_lost (STATUS[1], clkin_lost_out_ext); -buf b_clkfx_lost (STATUS[2], clkfx_lost_out_ext); - -assign STATUS[7:3] = 5'b0; - -dcm_sp_clock_divide_by_2 i_clock_divide_by_2 (clkin_in, clkin_type, clkin_div, rst_in); - -dcm_sp_maximum_period_check #("CLKIN", MAXPERCLKIN) i_max_clkin (clkin_in, rst_in); -dcm_sp_maximum_period_check #("PSCLK", MAXPERPSCLK) i_max_psclk (psclk_in, rst_in); - -dcm_sp_clock_lost i_clkin_lost (clkin_in, first_time_locked, clkin_lost_out, rst_in); -dcm_sp_clock_lost i_clkfx_lost (CLKFX, first_time_locked, clkfx_lost_out, rst_in); - -always @(rst_in or en_status or clkfx_lost_out or clkin_lost_out or ps_overflow_out) - if (rst_in == 1 || en_status == 0) begin - ps_overflow_out_ext = 0; - clkin_lost_out_ext = 0; - clkfx_lost_out_ext = 0; - end - else - begin - ps_overflow_out_ext = ps_overflow_out; - clkin_lost_out_ext = clkin_lost_out; - clkfx_lost_out_ext = clkfx_lost_out; - end - -always @(posedge rst_in or posedge LOCKED) - if (rst_in == 1) - en_status <= 0; - else - en_status <= 1; - - -always @(clkin_div) - clkin_ps_tmp <= #(ps_delay_md) clkin_div; - -always @(clkin_ps_tmp or clkin_ps_mkup or clkin_ps_mkup_win) - if (clkin_ps_mkup_win) - clkin_ps = clkin_ps_mkup; - else - clkin_ps = clkin_ps_tmp; - -always @(ps_delay_last or period_int or ps_delay) begin - period_int2 = 2 * period_int; - period_int3 = 3 * period_int; - if ((ps_delay_last >= period_int && ps_delay < period_int) || - (ps_delay_last >= period_int2 && ps_delay < period_int2) || - (ps_delay_last >= period_int3 && ps_delay < period_int3)) - clkin_ps_mkup_flag = 1; - else - clkin_ps_mkup_flag = 0; -end - -always @(posedge clkin_div or negedge clkin_div) begin - if (ps_type == 2'b10) begin - if ((ps_delay_last > 0 && ps_delay <= 0 ) || clkin_ps_mkup_flag == 1) begin - if (clkin_div) begin - clkin_ps_mkup_win <= 1; - clkin_ps_mkup <= 1; - #1; - @(negedge clkin_div) begin - clkin_ps_mkup_win <= 1; - clkin_ps_mkup <= 0; - end - end - else begin - clkin_ps_mkup_win <= 0; - clkin_ps_mkup <= 0; - #1; - @(posedge clkin_div) begin - clkin_ps_mkup_win <= 1; - clkin_ps_mkup <= 1; - end - @(negedge clkin_div) begin - clkin_ps_mkup_win <= 1; - clkin_ps_mkup <= 0; - end - end - end - else begin - clkin_ps_mkup_win <= 0; - clkin_ps_mkup <= 0; - end - ps_delay_last <= ps_delay; - end -end - -always @(clkin_ps or lock_fb) - clkin_fb = clkin_ps & lock_fb; - -always @(negedge clkfb_in or posedge rst_in) - if (rst_in) - clkfb_div_en <= 0; - else - if (lock_fb_dly && lock_period && lock_fb && ~clkin_ps) - clkfb_div_en <= 1; - -always @(posedge clkfb_in or posedge rst_in) - if (rst_in) - clkfb_div <= 0; - else - if (clkfb_div_en ) - clkfb_div <= ~clkfb_div; - -always @(clkfb_in or clkfb_div ) - if (clkfb_type == 2'b10 ) - clkfb_chk = clkfb_div; - else - clkfb_chk = clkfb_in & lock_fb_dly; - -always @(posedge clkin_fb or posedge chk_rst) - if (chk_rst) - clkin_chkin <= 0; - else - clkin_chkin <= 1; - -always @(posedge clkfb_chk or posedge chk_rst) - if (chk_rst) - clkfb_chkin <= 0; - else - clkfb_chkin <= 1; - - assign chk_rst = (rst_in==1 || clock_stopped==1 ) ? 1 : 0; - assign chk_enable = (clkin_chkin == 1 && clkfb_chkin == 1 && - lock_ps ==1 && lock_fb ==1 && lock_fb_dly == 1) ? 1 : 0; - -always @(posedge clkin_div or posedge rst_in) - if (rst_in) begin - period_div <= 0; - clkin_div_edge <= 0; - end - else - if ( clkin_div ==1 ) begin - clkin_div_edge <= $time; - if (($time - clkin_div_edge) <= (1.5 * period_div)) - period_div <= $time - clkin_div_edge; - else if ((period_div == 0) && (clkin_div_edge != 0)) - period_div <= $time - clkin_div_edge; - end - -always @(posedge clkin_ps or posedge rst_in) - if (rst_in) begin - period_ps <= 0; - clkin_ps_edge <= 0; - end - else - if (clkin_ps == 1 ) begin - clkin_ps_edge <= $time; - if (($time - clkin_ps_edge) <= (1.5 * period_ps)) - period_ps <= $time - clkin_ps_edge; - else if ((period_ps == 0) && (clkin_ps_edge != 0)) - period_ps <= $time - clkin_ps_edge; - end - -always @(posedge clkin_ps) begin - lock_ps <= lock_period; - lock_ps_dly <= lock_ps; - lock_fb <= lock_ps_dly; - lock_fb_dly_tmp <= lock_fb; -end - -always @(negedge clkin_ps or posedge rst_in) - if (rst_in) - lock_fb_dly <= 1'b0; - else - lock_fb_dly <= #(period/4) lock_fb_dly_tmp; - - -always @(period or fb_delay ) - if (fb_delay == 0) - clkout_delay = 0; - else - clkout_delay = period - fb_delay; - -// -// generate master reset signal -// - -always @(posedge clkin_in) begin - rst_reg[0] <= rst_in; - rst_reg[1] <= rst_reg[0] & rst_in; - rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst_in; -end - -reg rst_tmp1, rst_tmp2; -initial -begin -rst_tmp1 = 0; -rst_tmp2 = 0; -rst_flag = 0; -end - -always @(rst_in) -begin - if (rst_in) - rst_flag = 0; - - rst_tmp1 = rst_in; - if (rst_tmp1 == 0 && rst_tmp2 == 1) begin - if ((rst_reg[2] & rst_reg[1] & rst_reg[0]) == 0) begin - rst_flag = 1; - $display("Input Error : RST on instance %m must be asserted for 3 CLKIN clock cycles."); - end - end - rst_tmp2 = rst_tmp1; -end - -initial begin - CLK0 = 0; - CLK180 = 0; - CLK270 = 0; - CLK2X = 0; - CLK2X180 = 0; - CLK90 = 0; - CLKDV = 0; - CLKFX = 0; - CLKFX180 = 0; - clk0_out = 0; - clk2x_out = 0; - clkdv_out = 0; - clkdv_cnt = 0; - clkfb_window = 0; - clkfx_out = 0; - clkfx180_en = 0; - clkin_div_edge = 0; - clkin_period[0] = 0; - clkin_period[1] = 0; - clkin_period[2] = 0; - clkin_edge = 0; - clkin_ps_edge = 0; - clkin_window = 0; - clkout_delay = 0; - clock_stopped = 1; - fb_delay = 0; - fb_delay_found = 0; - lock_clkfb = 0; - lock_clkin = 0; - lock_delay = 0; - lock_fb = 0; - lock_fb_dly = 0; - lock_out = 2'b00; - lock_out1_neg = 0; - lock_period = 0; - lock_ps = 0; - lock_ps_dly = 0; - locked_out = 0; - period = 0; - period_int = 0; - period_int2 = 0; - period_int3 = 0; - period_div = 0; - period_fx = 0; - period_orig = 0; - period_orig_int = 0; - period_ps = 0; - psdone_out = 0; - ps_delay = 0; - ps_delay_md = 0; - ps_delay_init = 0; - ps_acc = 0; - ps_delay_all = 0; - ps_lock = 0; - ps_overflow_out = 0; - ps_overflow_out_ext = 0; - clkin_lost_out_ext = 0; - clkfx_lost_out_ext = 0; - rst_reg = 3'b000; - first_time_locked = 0; - en_status = 0; - clkfb_div = 0; - clkin_chkin = 0; - clkfb_chkin = 0; - clkin_ps_mkup = 0; - clkin_ps_mkup_win = 0; - clkin_ps_mkup_flag = 0; - ps_delay_last = 0; - clkin_ps_tmp = 0; -end - -// RST less than 3 cycles, lock = x - - assign locked_out_out = (rst_flag) ? 1'bx : locked_out; - -// -// detect_first_time_locked -// -always @(posedge locked_out) - if (first_time_locked == 0) - first_time_locked <= 1; - -// -// phase shift parameters -// - -always @(posedge lock_period) - ps_delay_init <= ps_in * period_orig /256; - - -always @(period) begin - period_int = period; - if (clkin_type==1) - period_ps_tmp = 2 * period; - else - period_ps_tmp = period; - - if (period_ps_tmp > 3000) - ps_max_range = 20 * (period_ps_tmp - 3000)/1000; - else - ps_max_range = 0; -end - -always @(ps_delay or rst_in or period_int or lock_period) - if ( rst_in) - ps_delay_md = 0; - else if (lock_period) begin - ps_delay_md = period_int + ps_delay % period_int; - end - -always @(posedge psclk_in or posedge rst_in or posedge lock_period_pulse) - if (rst_in) begin - ps_delay <= 0; - ps_overflow_out <= 0; - ps_acc <= 0; - end - else if (lock_period_pulse) - ps_delay <= ps_delay_init; - else - if (ps_type == 2'b10) - if (psen_in) begin - if (ps_lock == 1) - $display(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift."); - else if (lock_ps) begin - if (psincdec_in == 1) begin - if (ps_acc > ps_max_range) - ps_overflow_out <= 1; - else begin - ps_delay <= ps_delay + PS_STEP; - ps_acc <= ps_acc + 1; - ps_overflow_out <= 0; - end - ps_lock <= 1; - end - else if (psincdec_in == 0) begin - if (ps_acc < -ps_max_range) - ps_overflow_out <= 1; - else begin - ps_delay <= ps_delay - PS_STEP; - ps_acc <= ps_acc - 1; - ps_overflow_out <= 0; - end - ps_lock <= 1; - end - end - end - -always @(posedge ps_lock) begin - @(posedge clkin_ps) - @(posedge psclk_in) - @(posedge psclk_in) - @(posedge psclk_in) - psdone_out <= 1; - @(posedge psclk_in) - psdone_out <= 0; - ps_lock <= 0; -end - -// -// determine clock period -// - -always @(posedge clkin_div or negedge clkin_div or posedge rst_in) - if (rst_in == 1) begin - clkin_period[0] <= 0; - clkin_period[1] <= 0; - clkin_period[2] <= 0; - clkin_edge <= 0; - end - else - if (clkin_div == 1) begin - clkin_edge <= $time; - clkin_period[2] <= clkin_period[1]; - clkin_period[1] <= clkin_period[0]; - if (clkin_edge != 0) - clkin_period[0] <= $time - clkin_edge; - end - else if (clkin_div == 0) - if (lock_period == 1) - if (100000000 < clkin_period[0]/1000) - begin - end - else if ((period_orig * 2 < clkin_period[0]) && (clock_stopped == 0)) begin - clkin_period[0] <= clkin_period[1]; - end - -always @(negedge clkin_div or posedge rst_in) - if (rst_in == 1) begin - lock_period <= 0; - clock_stopped <= 1; - end - else begin - if (lock_period == 1'b0) begin - if ((clkin_period[0] != 0) && - (clkin_period[0] - cycle_jitter <= clkin_period[1]) && - (clkin_period[1] <= clkin_period[0] + cycle_jitter) && - (clkin_period[1] - cycle_jitter <= clkin_period[2]) && - (clkin_period[2] <= clkin_period[1] + cycle_jitter)) begin - lock_period <= 1; - period_orig <= (clkin_period[0] + - clkin_period[1] + - clkin_period[2]) / 3; - period <= clkin_period[0]; - end - end - else if (lock_period == 1'b1) begin - if (100000000 < (clkin_period[0] / 1000)) begin - $display(" Warning : CLKIN stopped toggling on instance %m exceeds %d ms. Current CLKIN Period = %1.3f ns.", 100, clkin_period[0] / 1000.0); - lock_period <= 0; - @(negedge rst_reg[2]); - end - else if ((period_orig * 2 < clkin_period[0]) && clock_stopped == 1'b0) begin - clock_stopped <= 1'b1; - end - else if ((clkin_period[0] < period_orig - period_jitter) || - (period_orig + period_jitter < clkin_period[0])) begin - $display(" Warning : Input Clock Period Jitter on instance %m exceeds %1.3f ns. Locked CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", period_jitter / 1000.0, period_orig / 1000.0, clkin_period[0] / 1000.0); - lock_period <= 0; - @(negedge rst_reg[2]); - end - else if ((clkin_period[0] < clkin_period[1] - cycle_jitter) || - (clkin_period[1] + cycle_jitter < clkin_period[0])) begin - $display(" Warning : Input Clock Cycle-Cycle Jitter on instance %m exceeds %1.3f ns. Previous CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", cycle_jitter / 1000.0, clkin_period[1] / 1000.0, clkin_period[0] / 1000.0); - lock_period <= 0; - @(negedge rst_reg[2]); - end - else begin - period <= clkin_period[0]; - clock_stopped <= 1'b0; - end - end -end - - assign #1 lock_period_dly1 = lock_period; - assign #(period/2) lock_period_dly = lock_period_dly1; - assign lock_period_pulse = (lock_period_dly1==1 && lock_period_dly==0) ? 1 : 0; - -// -// determine clock delay -// - -//always @(posedge lock_period or posedge rst_in) -always @(posedge lock_ps_dly or posedge rst_in) - if (rst_in) begin - fb_delay <= 0; - fb_delay_found <= 0; - end - else begin - if (lock_period && clkfb_type != 2'b00) begin - if (clkfb_type == 2'b01) begin - @(posedge CLK0 or rst_in) - delay_edge = $time; - end - else if (clkfb_type == 2'b10) begin - @(posedge CLK2X or rst_in) - delay_edge = $time; - end - @(posedge clkfb_in or rst_in) begin - fb_delay <= ($time - delay_edge) % period_orig; - fb_delay_found <= 1; - end - end - end - -// -// determine feedback lock -// - -always @(posedge clkfb_chk or posedge rst_in) - if (rst_in) - clkfb_window <= 0; - else begin - clkfb_window <= 1; - #cycle_jitter clkfb_window <= 0; - end - -always @(posedge clkin_fb or posedge rst_in) - if (rst_in) - clkin_window <= 0; - else begin - clkin_window <= 1; - #cycle_jitter clkin_window <= 0; - end - -always @(posedge clkin_fb or posedge rst_in) - if (rst_in) - lock_clkin <= 0; - else begin - #1 - if ((clkfb_window && fb_delay_found) || (clkin_lost_out == 1'b1 && lock_out[0]==1'b1)) - lock_clkin <= 1; - else - if (chk_enable==1) - lock_clkin <= 0; - end - -always @(posedge clkfb_chk or posedge rst_in) - if (rst_in) - lock_clkfb <= 0; - else begin - #1 - if ((clkin_window && fb_delay_found) || (clkin_lost_out == 1'b1 && lock_out[0]==1'b1)) - lock_clkfb <= 1; - else - if (chk_enable ==1) - lock_clkfb <= 0; - end - -always @(negedge clkin_fb or posedge rst_in) - if (rst_in) - lock_delay <= 0; - else - lock_delay <= lock_clkin || lock_clkfb; - -// -// generate lock signal -// - -always @(posedge clkin_ps or posedge rst_in) - if (rst_in) begin - lock_out <= 2'b0; - locked_out <=0; - end - else begin - if (clkfb_type == 2'b00) - lock_out[0] <= lock_period; - else - lock_out[0] <= lock_period & lock_delay & lock_fb; - lock_out[1] <= lock_out[0]; - locked_out <= lock_out[1]; - end - -always @(negedge clkin_ps or posedge rst_in) - if (rst_in) - lock_out1_neg <= 0; - else - lock_out1_neg <= lock_out[1]; - - -// -// generate the clk1x_out -// - -always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in) - if (rst_in) - clk0_out <= 0; - else - if (clkin_ps ==1) - if (clk1x_type==1 && lock_out[0]) begin - clk0_out <= 1; - #(period / 2) - clk0_out <= 0; - end - else - clk0_out <= 1; - else - if (clkin_ps == 0 && ((clk1x_type && lock_out[0]) == 0 || (lock_out[0]== 1 && lock_out[1]== 0))) - clk0_out <= 0; - -// -// generate the clk2x_out -// - -always @(posedge clkin_ps or posedge rst_in) - if (rst_in) - clk2x_out <= 0; - else begin - clk2x_out <= 1; - #(period / 4) - clk2x_out <= 0; - #(period / 4) - clk2x_out <= 1; - #(period / 4) - clk2x_out <= 0; - end - -// -// generate the clkdv_out -// - -always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in) - if (rst_in) begin - clkdv_out <= 1'b0; - clkdv_cnt <= 0; - end - else - if (lock_out1_neg) begin - if (clkdv_cnt >= divide_type -1) - clkdv_cnt <= 0; - else - clkdv_cnt <= clkdv_cnt + 1; - - if (clkdv_cnt < divide_type /2) - clkdv_out <= 1'b1; - else - if ( (divide_type[0] == 1'b1) && dll_mode_type == 1'b0) - clkdv_out <= #(period/4) 1'b0; - else - clkdv_out <= 1'b0; - end - - -// -// generate fx output signal -// - -always @(lock_period or period or denominator or numerator) begin - if (lock_period == 1'b1) begin - period_fx = (period * denominator) / (numerator * 2); - remain_fx = (period * denominator) % (numerator * 2); - end -end - -always @(posedge clkin_ps or posedge clkin_lost_out or posedge rst_in ) - if (rst_in == 1) - clkfx_out = 1'b0; - else if (clkin_lost_out == 1'b1 ) begin - if (locked_out == 1) - @(negedge rst_reg[2]); - end - else - if (lock_out[1] == 1) begin - clkfx_out = 1'b1; - for (p = 0; p < (numerator * 2 - 1); p = p + 1) begin - #(period_fx); - if (p < remain_fx) - #1; - clkfx_out = !clkfx_out; - end - if (period_fx > (period / 2)) begin - #(period_fx - (period / 2)); - end - end - -// -// generate all output signal -// - -always @(rst_in) -if (rst_in) begin - assign CLK0 = 0; - assign CLK90 = 0; - assign CLK180 = 0; - assign CLK270 = 0; - assign CLK2X = 0; - assign CLK2X180 =0; - assign CLKDV = 0; - assign CLKFX = 0; - assign CLKFX180 = 0; -end -else begin - deassign CLK0; - deassign CLK90; - deassign CLK180; - deassign CLK270; - deassign CLK2X; - deassign CLK2X180; - deassign CLKDV; - deassign CLKFX; - deassign CLKFX180; -end - -always @(clk0_out) begin - CLK0 <= #(clkout_delay) clk0_out && (clkfb_type != 2'b00); - CLK90 <= #(clkout_delay + period / 4) clk0_out && !dll_mode_type && (clkfb_type != 2'b00); - CLK180 <= #(clkout_delay) ~clk0_out && (clkfb_type != 2'b00); - CLK270 <= #(clkout_delay + period / 4) ~clk0_out && !dll_mode_type && (clkfb_type != 2'b00); - end - -always @(clk2x_out) begin - CLK2X <= #(clkout_delay) clk2x_out && !dll_mode_type && (clkfb_type != 2'b00); - CLK2X180 <= #(clkout_delay) ~clk2x_out && !dll_mode_type && (clkfb_type != 2'b00); -end - -always @(clkdv_out) - CLKDV <= #(clkout_delay) clkdv_out && (clkfb_type != 2'b00); - -always @(clkfx_out ) - CLKFX <= #(clkout_delay) clkfx_out; - -always @( clkfx_out or first_time_locked or locked_out) - if ( ~first_time_locked) - CLKFX180 = 0; - else - CLKFX180 <= #(clkout_delay) ~clkfx_out; - - -endmodule - -////////////////////////////////////////////////////// - -module dcm_sp_clock_divide_by_2 (clock, clock_type, clock_out, rst); -input clock; -input clock_type; -input rst; -output clock_out; - -reg clock_out; -reg clock_div2; -reg [2:0] rst_reg; -wire clk_src; - -initial begin - clock_out = 1'b0; - clock_div2 = 1'b0; -end - -always @(posedge clock) - clock_div2 <= ~clock_div2; - -always @(posedge clock) begin - rst_reg[0] <= rst; - rst_reg[1] <= rst_reg[0] & rst; - rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst; -end - -assign clk_src = (clock_type) ? clock_div2 : clock; - -always @(clk_src or rst or rst_reg) - if (rst == 1'b0) - clock_out = clk_src; - else if (rst == 1'b1) begin - clock_out = 1'b0; - @(negedge rst_reg[2]); - if (clk_src == 1'b1) - @(negedge clk_src); - end - - -endmodule - -module dcm_sp_maximum_period_check (clock, rst); -parameter clock_name = ""; -parameter maximum_period = 0; -input clock; -input rst; - -time clock_edge; -time clock_period; - -initial begin - clock_edge = 0; - clock_period = 0; -end - -always @(posedge clock) begin - clock_edge <= $time; -// clock_period <= $time - clock_edge; - clock_period = $time - clock_edge; - if (clock_period > maximum_period ) begin - if (rst == 0) - $display(" Warning : Input clock period of %1.3f ns, on the %s port of instance %m exceeds allowed value of %1.3f ns at time %1.3f ns.", clock_period/1000.0, clock_name, maximum_period/1000.0, $time/1000.0); - end -end -endmodule - -module dcm_sp_clock_lost (clock, enable, lost, rst); -input clock; -input enable; -input rst; -output lost; - -time clock_edge; -reg [63:0] period; -reg clock_low, clock_high; -reg clock_posedge, clock_negedge; -reg lost_r, lost_f, lost; -reg clock_second_pos, clock_second_neg; - -initial begin - clock_edge = 0; - clock_high = 0; - clock_low = 0; - lost_r = 0; - lost_f = 0; - period = 0; - clock_posedge = 0; - clock_negedge = 0; - clock_second_pos = 0; - clock_second_neg = 0; -end - -always @(posedge clock or posedge rst) - if (rst==1) - period <= 0; - else begin - clock_edge <= $time; - if (period != 0 && (($time - clock_edge) <= (1.5 * period))) - period <= $time - clock_edge; - else if (period != 0 && (($time - clock_edge) > (1.5 * period))) - period <= 0; - else if ((period == 0) && (clock_edge != 0) && clock_second_pos == 1) - period <= $time - clock_edge; - end - - -always @(posedge clock or posedge rst) - if (rst) - lost_r <= 0; - else - if (enable == 1 && clock_second_pos == 1) begin - #1; - if ( period != 0) - lost_r <= 0; - #((period * 9.1) / 10) - if ((clock_low != 1'b1) && (clock_posedge != 1'b1) && rst == 0) - lost_r <= 1; - end - -always @(posedge clock or negedge clock or posedge rst) - if (rst) begin - clock_second_pos <= 0; - clock_second_neg <= 0; - end - else if (clock) - clock_second_pos <= 1; - else if (~clock) - clock_second_neg <= 1; - -always @(negedge clock or posedge rst) - if (rst==1) begin - lost_f <= 0; - end - else begin - if (enable == 1 && clock_second_neg == 1) begin - if ( period != 0) - lost_f <= 0; - #((period * 9.1) / 10) - if ((clock_high != 1'b1) && (clock_negedge != 1'b1) && rst == 0) - lost_f <= 1; - end - end - -always @( lost_r or lost_f or enable) -begin - if (enable == 1) - lost = lost_r | lost_f; - else - lost = 0; -end - - -always @(posedge clock or negedge clock or posedge rst) - if (rst==1) begin - clock_low <= 1'b0; - clock_high <= 1'b0; - clock_posedge <= 1'b0; - clock_negedge <= 1'b0; - end - else begin - if (clock ==1) begin - clock_low <= 1'b0; - clock_high <= 1'b1; - clock_posedge <= 1'b0; - clock_negedge <= 1'b1; - end - else if (clock == 0) begin - clock_low <= 1'b1; - clock_high <= 1'b0; - clock_posedge <= 1'b1; - clock_negedge <= 1'b0; - end -end - - -endmodule diff --git a/fpga/usrp2/models/FIFO_GENERATOR_V4_3.v b/fpga/usrp2/models/FIFO_GENERATOR_V4_3.v deleted file mode 100644 index bcb9af8a7..000000000 --- a/fpga/usrp2/models/FIFO_GENERATOR_V4_3.v +++ /dev/null @@ -1,3494 +0,0 @@ -/* - * $RDCfile: $ $Revision: 1.1.2.15 $ $Date: 2007/07/25 15:58:33 $ - ******************************************************************************* - * - * FIFO Generator v3.3 - Verilog Behavioral Model - * - ******************************************************************************* - * - * Copyright(C) 2006 by Xilinx, Inc. All rights reserved. - * This text/file contains proprietary, confidential - * information of Xilinx, Inc., is distributed under - * license from Xilinx, Inc., and may be used, copied - * and/or disclosed only pursuant to the terms of a valid - * license agreement with Xilinx, Inc. Xilinx hereby - * grants you a license to use this text/file solely for - * design, simulation, implementation and creation of - * design files limited to Xilinx devices or technologies. - * Use with non-Xilinx devices or technologies is expressly - * prohibited and immediately terminates your license unless - * covered by a separate agreement. - * - * Xilinx is providing theis design, code, or information - * "as-is" solely for use in developing programs and - * solutions for Xilinx devices, with no obligation on the - * part of Xilinx to provide support. By providing this design, - * code, or information as one possible implementation of - * this feature, application or standard. Xilinx is making no - * representation that this implementation is free from any - * claims of infringement. You are responsible for obtaining - * any rights you may require for your implementation. - * Xilinx expressly disclaims any warranty whatsoever with - * respect to the adequacy of the implementation, including - * but not limited to any warranties or representations that this - * implementation is free from claims of infringement, implied - * warranties of merchantability or fitness for a particular - * purpose. - * - * Xilinx products are not intended for use in life support - * appliances, devices, or systems. Use in such applications is - * expressly prohibited. - * - * This copyright and support notice must be retained as part - * of this text at all times. (c)Copyright 1995-2006 Xilinx, Inc. - * All rights reserved. - * - ******************************************************************************* - * - * Filename: fifo_generator_v4_3_bhv.v - * - * Description: - * The verilog behavioral model for the FIFO generator core. - * - ******************************************************************************* - */ - -`timescale 1ps/1ps - -/******************************************************************************* - * Declaration of top-level module - ******************************************************************************/ -module FIFO_GENERATOR_V4_3 -( - BACKUP, - BACKUP_MARKER, - CLK, - DIN, - PROG_EMPTY_THRESH, - PROG_EMPTY_THRESH_ASSERT, - PROG_EMPTY_THRESH_NEGATE, - PROG_FULL_THRESH, - PROG_FULL_THRESH_ASSERT, - PROG_FULL_THRESH_NEGATE, - RD_CLK, - RD_EN, - RD_RST, - RST, - SRST, - WR_CLK, - WR_EN, - WR_RST, - INT_CLK, - - ALMOST_EMPTY, - ALMOST_FULL, - DATA_COUNT, - DOUT, - EMPTY, - FULL, - OVERFLOW, - PROG_EMPTY, - PROG_FULL, - RD_DATA_COUNT, - UNDERFLOW, - VALID, - WR_ACK, - WR_DATA_COUNT, - SBITERR, - DBITERR - ); - - /**************************************************************************** - * Definition of Ports - * - * - ***************************************************************************** - * Definition of Parameters - * - * - *****************************************************************************/ - - /**************************************************************************** - * Declare user parameters and their defaults - *****************************************************************************/ - parameter C_COMMON_CLOCK = 0; - parameter C_COUNT_TYPE = 0; - parameter C_DATA_COUNT_WIDTH = 2; - parameter C_DEFAULT_VALUE = ""; - parameter C_DIN_WIDTH = 8; - parameter C_DOUT_RST_VAL = ""; - parameter C_DOUT_WIDTH = 8; - parameter C_ENABLE_RLOCS = 0; - - parameter C_FAMILY = "virtex2"; - //Not allowed in Verilog model - - parameter C_HAS_ALMOST_EMPTY = 0; - parameter C_HAS_ALMOST_FULL = 0; - parameter C_HAS_BACKUP = 0; - parameter C_HAS_DATA_COUNT = 0; - parameter C_HAS_MEMINIT_FILE = 0; - parameter C_HAS_OVERFLOW = 0; - parameter C_HAS_RD_DATA_COUNT = 0; - parameter C_HAS_RD_RST = 0; - parameter C_HAS_RST = 0; - parameter C_HAS_SRST = 0; - parameter C_HAS_UNDERFLOW = 0; - parameter C_HAS_VALID = 0; - parameter C_HAS_WR_ACK = 0; - parameter C_HAS_WR_DATA_COUNT = 0; - parameter C_HAS_WR_RST = 0; - parameter C_IMPLEMENTATION_TYPE = 0; - parameter C_INIT_WR_PNTR_VAL = 0; - parameter C_MEMORY_TYPE = 1; - parameter C_MIF_FILE_NAME = ""; - parameter C_OPTIMIZATION_MODE = 0; - parameter C_OVERFLOW_LOW = 0; - parameter C_PRELOAD_LATENCY = 1; - parameter C_PRELOAD_REGS = 0; - parameter C_PRIM_FIFO_TYPE = 512; - parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; - parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; - parameter C_PROG_EMPTY_TYPE = 0; - parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; - parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; - parameter C_PROG_FULL_TYPE = 0; - parameter C_RD_DATA_COUNT_WIDTH = 2; - parameter C_RD_DEPTH = 256; - parameter C_RD_FREQ = 1; - parameter C_RD_PNTR_WIDTH = 8; - parameter C_UNDERFLOW_LOW = 0; - parameter C_USE_FIFO16_FLAGS = 0; - parameter C_VALID_LOW = 0; - parameter C_WR_ACK_LOW = 0; - parameter C_WR_DATA_COUNT_WIDTH = 2; - parameter C_WR_DEPTH = 256; - parameter C_WR_FREQ = 1; - parameter C_WR_PNTR_WIDTH = 8; - parameter C_WR_RESPONSE_LATENCY = 1; - parameter C_USE_ECC = 0; - parameter C_FULL_FLAGS_RST_VAL = 1; - parameter C_HAS_INT_CLK = 0; - parameter C_USE_EMBEDDED_REG = 0; - parameter C_USE_FWFT_DATA_COUNT = 0; - - //There are 2 Verilog behavioral models - // 0 = Synchronous FIFO/ShiftRam FIFO - // 1 = Asynchronous FIFO - parameter C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE==0 ? 0 : - (C_IMPLEMENTATION_TYPE==1 ? 0 : - (C_IMPLEMENTATION_TYPE==2 ? 1 : 0))); - - - /****************************************************************************** - * Declare Input and Output Ports - *****************************************************************************/ - input CLK; - input BACKUP; - input BACKUP_MARKER; - input [C_DIN_WIDTH-1:0] DIN; - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; - input RD_CLK; - input RD_EN; - input RD_RST; - input RST; - input SRST; - input WR_CLK; - input WR_EN; - input WR_RST; - input INT_CLK; - - output ALMOST_EMPTY; - output ALMOST_FULL; - output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; - output [C_DOUT_WIDTH-1:0] DOUT; - output EMPTY; - output FULL; - output OVERFLOW; - output PROG_EMPTY; - output PROG_FULL; - output VALID; - output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; - output UNDERFLOW; - output WR_ACK; - output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; - output SBITERR; - output DBITERR; - - - wire ALMOST_EMPTY; - wire ALMOST_FULL; - wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; - wire [C_DOUT_WIDTH-1:0] DOUT; - wire EMPTY; - wire FULL; - wire OVERFLOW; - wire PROG_EMPTY; - wire PROG_FULL; - wire VALID; - wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; - wire UNDERFLOW; - wire WR_ACK; - wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; - - - wire RD_CLK_P0_IN; - wire RST_P0_IN; - wire RD_EN_FIFO_IN; - wire RD_EN_P0_IN; - - wire ALMOST_EMPTY_FIFO_OUT; - wire ALMOST_FULL_FIFO_OUT; - wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; - wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; - wire EMPTY_FIFO_OUT; - wire FULL_FIFO_OUT; - wire OVERFLOW_FIFO_OUT; - wire PROG_EMPTY_FIFO_OUT; - wire PROG_FULL_FIFO_OUT; - wire VALID_FIFO_OUT; - wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; - wire UNDERFLOW_FIFO_OUT; - wire WR_ACK_FIFO_OUT; - wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; - - - //*************************************************************************** - // Internal Signals - // The core uses either the internal_ wires or the preload0_ wires depending - // on whether the core uses Preload0 or not. - // When using preload0, the internal signals connect the internal core to - // the preload logic, and the external core's interfaces are tied to the - // preload0 signals from the preload logic. - //*************************************************************************** - wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; - wire VALID_P0_OUT; - wire EMPTY_P0_OUT; - wire ALMOSTEMPTY_P0_OUT; - reg EMPTY_P0_OUT_Q; - reg ALMOSTEMPTY_P0_OUT_Q; - wire UNDERFLOW_P0_OUT; - wire RDEN_P0_OUT; - wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; - wire EMPTY_P0_IN; - - assign SBITERR = 1'b0; - assign DBITERR = 1'b0; - -// choose the base FIFO implementation for simulation -generate -case (C_VERILOG_IMPL) -0 : begin : block1 - fifo_generator_v4_3_bhv_ver_ss - #( - C_COMMON_CLOCK, - C_COUNT_TYPE, - C_DATA_COUNT_WIDTH, - C_DEFAULT_VALUE, - C_DIN_WIDTH, - C_DOUT_RST_VAL, - C_DOUT_WIDTH, - C_ENABLE_RLOCS, - C_FAMILY,//Not allowed in Verilog model - C_HAS_ALMOST_EMPTY, - C_HAS_ALMOST_FULL, - C_HAS_BACKUP, - C_HAS_DATA_COUNT, - C_HAS_MEMINIT_FILE, - C_HAS_OVERFLOW, - C_HAS_RD_DATA_COUNT, - C_HAS_RD_RST, - C_HAS_RST, - C_HAS_SRST, - C_HAS_UNDERFLOW, - C_HAS_VALID, - C_HAS_WR_ACK, - C_HAS_WR_DATA_COUNT, - C_HAS_WR_RST, - C_IMPLEMENTATION_TYPE, - C_INIT_WR_PNTR_VAL, - C_MEMORY_TYPE, - C_MIF_FILE_NAME, - C_OPTIMIZATION_MODE, - C_OVERFLOW_LOW, - C_PRELOAD_LATENCY, - C_PRELOAD_REGS, - C_PROG_EMPTY_THRESH_ASSERT_VAL, - C_PROG_EMPTY_THRESH_NEGATE_VAL, - C_PROG_EMPTY_TYPE, - C_PROG_FULL_THRESH_ASSERT_VAL, - C_PROG_FULL_THRESH_NEGATE_VAL, - C_PROG_FULL_TYPE, - C_RD_DATA_COUNT_WIDTH, - C_RD_DEPTH, - C_RD_PNTR_WIDTH, - C_UNDERFLOW_LOW, - C_VALID_LOW, - C_WR_ACK_LOW, - C_WR_DATA_COUNT_WIDTH, - C_WR_DEPTH, - C_WR_PNTR_WIDTH, - C_WR_RESPONSE_LATENCY, - C_FULL_FLAGS_RST_VAL, - C_USE_EMBEDDED_REG - ) - gen_ss - ( - .CLK (CLK), - .RST (RST), - .SRST (SRST), - .DIN (DIN), - .WR_EN (WR_EN), - .RD_EN (RD_EN_FIFO_IN), - .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), - .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), - .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), - .PROG_FULL_THRESH (PROG_FULL_THRESH), - .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), - .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), - .DOUT (DOUT_FIFO_OUT), - .FULL (FULL_FIFO_OUT), - .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), - .WR_ACK (WR_ACK_FIFO_OUT), - .OVERFLOW (OVERFLOW_FIFO_OUT), - .EMPTY (EMPTY_FIFO_OUT), - .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), - .VALID (VALID_FIFO_OUT), - .UNDERFLOW (UNDERFLOW_FIFO_OUT), - .DATA_COUNT (DATA_COUNT_FIFO_OUT), - .PROG_FULL (PROG_FULL_FIFO_OUT), - .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) - ); -end -1 : begin : block1 - fifo_generator_v4_3_bhv_ver_as - #( - C_COMMON_CLOCK, - C_COUNT_TYPE, - C_DATA_COUNT_WIDTH, - C_DEFAULT_VALUE, - C_DIN_WIDTH, - C_DOUT_RST_VAL, - C_DOUT_WIDTH, - C_ENABLE_RLOCS, - C_FAMILY,//Not allowed in Verilog model - C_HAS_ALMOST_EMPTY, - C_HAS_ALMOST_FULL, - C_HAS_BACKUP, - C_HAS_DATA_COUNT, - C_HAS_MEMINIT_FILE, - C_HAS_OVERFLOW, - C_HAS_RD_DATA_COUNT, - C_HAS_RD_RST, - C_HAS_RST, - C_HAS_UNDERFLOW, - C_HAS_VALID, - C_HAS_WR_ACK, - C_HAS_WR_DATA_COUNT, - C_HAS_WR_RST, - C_IMPLEMENTATION_TYPE, - C_INIT_WR_PNTR_VAL, - C_MEMORY_TYPE, - C_MIF_FILE_NAME, - C_OPTIMIZATION_MODE, - C_OVERFLOW_LOW, - C_PRELOAD_LATENCY, - C_PRELOAD_REGS, - C_PROG_EMPTY_THRESH_ASSERT_VAL, - C_PROG_EMPTY_THRESH_NEGATE_VAL, - C_PROG_EMPTY_TYPE, - C_PROG_FULL_THRESH_ASSERT_VAL, - C_PROG_FULL_THRESH_NEGATE_VAL, - C_PROG_FULL_TYPE, - C_RD_DATA_COUNT_WIDTH, - C_RD_DEPTH, - C_RD_PNTR_WIDTH, - C_UNDERFLOW_LOW, - C_VALID_LOW, - C_WR_ACK_LOW, - C_WR_DATA_COUNT_WIDTH, - C_WR_DEPTH, - C_WR_PNTR_WIDTH, - C_WR_RESPONSE_LATENCY, - C_FULL_FLAGS_RST_VAL, - C_USE_FWFT_DATA_COUNT, - C_USE_EMBEDDED_REG - ) - gen_as - ( - .WR_CLK (WR_CLK), - .RD_CLK (RD_CLK), - .RST (RST), - .DIN (DIN), - .WR_EN (WR_EN), - .RD_EN (RD_EN_FIFO_IN), - .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), - .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), - .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), - .PROG_FULL_THRESH (PROG_FULL_THRESH), - .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), - .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), - .DOUT (DOUT_FIFO_OUT), - .FULL (FULL_FIFO_OUT), - .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), - .WR_ACK (WR_ACK_FIFO_OUT), - .OVERFLOW (OVERFLOW_FIFO_OUT), - .EMPTY (EMPTY_FIFO_OUT), - .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), - .VALID (VALID_FIFO_OUT), - .UNDERFLOW (UNDERFLOW_FIFO_OUT), - .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), - .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), - .PROG_FULL (PROG_FULL_FIFO_OUT), - .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) - ); -end - -default : begin : block1 - fifo_generator_v4_3_bhv_ver_as - #( - C_COMMON_CLOCK, - C_COUNT_TYPE, - C_DATA_COUNT_WIDTH, - C_DEFAULT_VALUE, - C_DIN_WIDTH, - C_DOUT_RST_VAL, - C_DOUT_WIDTH, - C_ENABLE_RLOCS, - C_FAMILY,//Not allowed in Verilog model - C_HAS_ALMOST_EMPTY, - C_HAS_ALMOST_FULL, - C_HAS_BACKUP, - C_HAS_DATA_COUNT, - C_HAS_MEMINIT_FILE, - C_HAS_OVERFLOW, - C_HAS_RD_DATA_COUNT, - C_HAS_RD_RST, - C_HAS_RST, - C_HAS_UNDERFLOW, - C_HAS_VALID, - C_HAS_WR_ACK, - C_HAS_WR_DATA_COUNT, - C_HAS_WR_RST, - C_IMPLEMENTATION_TYPE, - C_INIT_WR_PNTR_VAL, - C_MEMORY_TYPE, - C_MIF_FILE_NAME, - C_OPTIMIZATION_MODE, - C_OVERFLOW_LOW, - C_PRELOAD_LATENCY, - C_PRELOAD_REGS, - C_PROG_EMPTY_THRESH_ASSERT_VAL, - C_PROG_EMPTY_THRESH_NEGATE_VAL, - C_PROG_EMPTY_TYPE, - C_PROG_FULL_THRESH_ASSERT_VAL, - C_PROG_FULL_THRESH_NEGATE_VAL, - C_PROG_FULL_TYPE, - C_RD_DATA_COUNT_WIDTH, - C_RD_DEPTH, - C_RD_PNTR_WIDTH, - C_UNDERFLOW_LOW, - C_VALID_LOW, - C_WR_ACK_LOW, - C_WR_DATA_COUNT_WIDTH, - C_WR_DEPTH, - C_WR_PNTR_WIDTH, - C_WR_RESPONSE_LATENCY, - C_FULL_FLAGS_RST_VAL, - C_USE_FWFT_DATA_COUNT, - C_USE_EMBEDDED_REG - ) - gen_as - ( - .WR_CLK (WR_CLK), - .RD_CLK (RD_CLK), - .RST (RST), - .DIN (DIN), - .WR_EN (WR_EN), - .RD_EN (RD_EN_FIFO_IN), - .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), - .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), - .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), - .PROG_FULL_THRESH (PROG_FULL_THRESH), - .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), - .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), - .DOUT (DOUT_FIFO_OUT), - .FULL (FULL_FIFO_OUT), - .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), - .WR_ACK (WR_ACK_FIFO_OUT), - .OVERFLOW (OVERFLOW_FIFO_OUT), - .EMPTY (EMPTY_FIFO_OUT), - .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), - .VALID (VALID_FIFO_OUT), - .UNDERFLOW (UNDERFLOW_FIFO_OUT), - .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), - .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), - .PROG_FULL (PROG_FULL_FIFO_OUT), - .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) - ); -end - -endcase -endgenerate - - -//************************************************************************** -// Connect Internal Signals -// (Signals labeled internal_*) -// In the normal case, these signals tie directly to the FIFO's inputs and -// outputs. -// In the case of Preload Latency 0 or 1, there are intermediate -// signals between the internal FIFO and the preload logic. -//************************************************************************** - -generate -if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) - begin : block2 - -fifo_generator_v4_3_bhv_ver_preload0 - #( - C_DOUT_RST_VAL, - C_DOUT_WIDTH, - C_HAS_RST, - C_VALID_LOW, - C_UNDERFLOW_LOW - ) - fgpl0 -( - .RD_CLK (RD_CLK_P0_IN), - .RD_RST (RST_P0_IN), - .RD_EN (RD_EN_P0_IN), - .FIFOEMPTY (EMPTY_P0_IN), - .FIFODATA (DATA_P0_IN), - .USERDATA (DATA_P0_OUT), - .USERVALID (VALID_P0_OUT), - .USEREMPTY (EMPTY_P0_OUT), - .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), - .USERUNDERFLOW (UNDERFLOW_P0_OUT), - .RAMVALID (RAMVALID_P0_OUT), - .FIFORDEN (RDEN_P0_OUT) - ); - - assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); - assign RST_P0_IN = RST; - assign RD_EN_P0_IN = RD_EN; - - assign RD_EN_FIFO_IN = RDEN_P0_OUT; - - assign DOUT = DATA_P0_OUT; - assign DATA_P0_IN = DOUT_FIFO_OUT; - assign VALID = VALID_P0_OUT ; - assign EMPTY = EMPTY_P0_OUT; - assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; - assign EMPTY_P0_IN = EMPTY_FIFO_OUT; - assign UNDERFLOW = UNDERFLOW_P0_OUT ; - - always @ (posedge RD_CLK or posedge RST) - begin - if (RST) - begin - EMPTY_P0_OUT_Q <= 1; - ALMOSTEMPTY_P0_OUT_Q <= 1; - end - else - begin - EMPTY_P0_OUT_Q <= EMPTY_P0_OUT; - ALMOSTEMPTY_P0_OUT_Q <= ALMOSTEMPTY_P0_OUT; - end - end - - end -else - begin : block2 - - assign RD_CLK_P0_IN = 0; - assign RST_P0_IN = 0; - assign RD_EN_P0_IN = 0; - - assign RD_EN_FIFO_IN = RD_EN; - - assign DOUT = DOUT_FIFO_OUT; - assign DATA_P0_IN = 0; - assign VALID = VALID_FIFO_OUT; - assign EMPTY = EMPTY_FIFO_OUT; - assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; - assign EMPTY_P0_IN = 0; - assign UNDERFLOW = UNDERFLOW_FIFO_OUT; - - end -endgenerate - - -//Connect Data Count Signals -generate -if (C_USE_FWFT_DATA_COUNT==1) begin : block3 - assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); -end -else begin : block3 - assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; -end -endgenerate - -generate -if (C_USE_FWFT_DATA_COUNT==1) begin : block4 - assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; -end -else begin : block4 - assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; -end -endgenerate - - - assign FULL = FULL_FIFO_OUT; - assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; - assign WR_ACK = WR_ACK_FIFO_OUT; - assign OVERFLOW = OVERFLOW_FIFO_OUT; - assign PROG_FULL = PROG_FULL_FIFO_OUT; - assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; - assign DATA_COUNT = DATA_COUNT_FIFO_OUT; - - - // if an asynchronous FIFO has been selected, display a message that the FIFO - // will not be cycle-accurate in simulation - initial begin - //if (C_IMPLEMENTATION_TYPE == 1) begin //bug in v3.1 - if (C_IMPLEMENTATION_TYPE == 2) begin //fixed in v3.2 (IP2_Im) - $display("Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time); - end else if (C_IMPLEMENTATION_TYPE == 3 || C_IMPLEMENTATION_TYPE == 4) begin - $display("Failure in %m at time %t: Use of Virtex-4 and Virtex-5 built-in FIFO configurations is currently not supported. Please use the structural simulation model. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time); - $finish; - end - - end - -endmodule //fifo_generator_v4_3_bhv_ver - - - - - - -/******************************************************************************* - * Declaration of asynchronous FIFO Module - ******************************************************************************/ -module fifo_generator_v4_3_bhv_ver_as - ( - WR_CLK, RD_CLK, RST, DIN, WR_EN, RD_EN, - PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, - PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, - DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, ALMOST_EMPTY, VALID, - UNDERFLOW, RD_DATA_COUNT, WR_DATA_COUNT, PROG_FULL, PROG_EMPTY - ); - - /***************************************************************************** - * Declare user parameters and their defaults - *****************************************************************************/ - parameter C_COMMON_CLOCK = 0; - parameter C_COUNT_TYPE = 0; - parameter C_DATA_COUNT_WIDTH = 2; - parameter C_DEFAULT_VALUE = ""; - parameter C_DIN_WIDTH = 8; - parameter C_DOUT_RST_VAL = ""; - parameter C_DOUT_WIDTH = 8; - parameter C_ENABLE_RLOCS = 0; - parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model - parameter C_HAS_ALMOST_EMPTY = 0; - parameter C_HAS_ALMOST_FULL = 0; - parameter C_HAS_BACKUP = 0; - parameter C_HAS_DATA_COUNT = 0; - parameter C_HAS_MEMINIT_FILE = 0; - parameter C_HAS_OVERFLOW = 0; - parameter C_HAS_RD_DATA_COUNT = 0; - parameter C_HAS_RD_RST = 0; - parameter C_HAS_RST = 0; - parameter C_HAS_UNDERFLOW = 0; - parameter C_HAS_VALID = 0; - parameter C_HAS_WR_ACK = 0; - parameter C_HAS_WR_DATA_COUNT = 0; - parameter C_HAS_WR_RST = 0; - parameter C_IMPLEMENTATION_TYPE = 0; - parameter C_INIT_WR_PNTR_VAL = 0; - parameter C_MEMORY_TYPE = 1; - parameter C_MIF_FILE_NAME = ""; - parameter C_OPTIMIZATION_MODE = 0; - parameter C_OVERFLOW_LOW = 0; - parameter C_PRELOAD_LATENCY = 1; - parameter C_PRELOAD_REGS = 0; - parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; - parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; - parameter C_PROG_EMPTY_TYPE = 0; - parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; - parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; - parameter C_PROG_FULL_TYPE = 0; - parameter C_RD_DATA_COUNT_WIDTH = 2; - parameter C_RD_DEPTH = 256; - parameter C_RD_PNTR_WIDTH = 8; - parameter C_UNDERFLOW_LOW = 0; - parameter C_VALID_LOW = 0; - parameter C_WR_ACK_LOW = 0; - parameter C_WR_DATA_COUNT_WIDTH = 2; - parameter C_WR_DEPTH = 256; - parameter C_WR_PNTR_WIDTH = 8; - parameter C_WR_RESPONSE_LATENCY = 1; - parameter C_FULL_FLAGS_RST_VAL = 1; - parameter C_USE_FWFT_DATA_COUNT = 0; - parameter C_USE_EMBEDDED_REG = 0; - - /***************************************************************************** - * Declare Input and Output Ports - *****************************************************************************/ - input [C_DIN_WIDTH-1:0] DIN; - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; - input RD_CLK; - input RD_EN; - input RST; - input WR_CLK; - input WR_EN; - output ALMOST_EMPTY; - output ALMOST_FULL; - output [C_DOUT_WIDTH-1:0] DOUT; - output EMPTY; - output FULL; - output OVERFLOW; - output PROG_EMPTY; - output PROG_FULL; - output VALID; - output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; - output UNDERFLOW; - output WR_ACK; - output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; - - /******************************************************************************* - * Input and output register declarations - ******************************************************************************/ - /******************************************************************************* - * Parameters used as constants - ******************************************************************************/ - //When RST is present, set FULL reset value to '1'. - //If core has no RST, make sure FULL powers-on as '0'. - parameter C_DEPTH_RATIO_WR = - (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; - parameter C_DEPTH_RATIO_RD = - (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; - parameter C_FIFO_WR_DEPTH = - (C_COMMON_CLOCK) ? - C_WR_DEPTH : C_WR_DEPTH - 1; - parameter C_FIFO_RD_DEPTH = - (C_COMMON_CLOCK) ? - C_RD_DEPTH : C_RD_DEPTH - 1; - - - // EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD - // WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1 - // WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling) - // WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4 - // WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8 - parameter EXTRA_WORDS = (C_DEPTH_RATIO_RD > 1)? 1:(2 * C_DEPTH_RATIO_WR); - // extra_words_dc = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD - // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC - // -----------------|------------------|-----------------|--------------- - // 1 | 8 | C_RD_PNTR_WIDTH | 2 - // 1 | 4 | C_RD_PNTR_WIDTH | 2 - // 1 | 2 | C_RD_PNTR_WIDTH | 2 - // 1 | 1 | C_WR_PNTR_WIDTH | 2 - // 2 | 1 | C_WR_PNTR_WIDTH | 4 - // 4 | 1 | C_WR_PNTR_WIDTH | 8 - // 8 | 1 | C_WR_PNTR_WIDTH | 16 - parameter EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR)? - 2:(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); - - - //Memory which will be used to simulate a FIFO - reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; - reg [31:0] num_wr_bits; - reg [31:0] num_rd_bits; - reg [31:0] next_num_wr_bits; - reg [31:0] next_num_rd_bits; - reg [31:0] wr_ptr; - reg [31:0] rd_ptr; - reg [31:0] wr_ptr_rdclk; - reg [31:0] wr_ptr_rdclk_next; - reg [31:0] rd_ptr_wrclk; - reg [31:0] rd_ptr_wrclk_next; - wire [31:0] num_read_words = num_rd_bits/C_DOUT_WIDTH; - wire [31:0] num_read_words_dc_i; - wire [31:0] num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; - wire [31:0] num_read_words_fwft_dc = (num_rd_bits/C_DOUT_WIDTH+2); - wire [31:0] num_read_words_pe = - num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); - wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; - wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized - = num_read_words_dc_i[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; - wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_fwft - = num_read_words_dc_i[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; - wire [31:0] num_write_words = num_wr_bits/C_DIN_WIDTH; - wire [31:0] num_write_words_dc_i; - wire [31:0] num_write_words_dc = 1+(num_wr_bits-1)/C_DIN_WIDTH;//roof of num_wr_bits/C_DIN_WIDTH - wire [31:0] num_write_words_fwft_dc = - (num_wr_bits/C_DIN_WIDTH*C_DEPTH_RATIO_RD+2*C_DEPTH_RATIO_WR)/C_DEPTH_RATIO_RD; - wire [31:0] num_write_words_pf = - num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); - wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; - wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized - = num_write_words_dc_i[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; - wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_fwft - = num_write_words_dc_i[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; - wire [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; - wire [31:0] log2_reads_per_write = log2_val(reads_per_write); - wire [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; - wire [31:0] log2_writes_per_read = log2_val(writes_per_read); - - /******************************************************************************* - * Internal Registers and wires - ******************************************************************************/ - wire wr_ack_i; - wire overflow_i; - wire underflow_i; - wire valid_i; - wire valid_out; - reg valid_d1; - /******************************************************************************* - * Internal registers and wires for internal reset logics - ******************************************************************************/ - reg rd_rst_asreg =0; - reg rd_rst_asreg_d1 =0; - reg rd_rst_asreg_d2 =0; - reg rd_rst_reg =0; - reg rd_rst_d1 =0; - reg wr_rst_asreg =0; - reg wr_rst_asreg_d1 =0; - reg wr_rst_asreg_d2 =0; - reg wr_rst_reg =0; - reg wr_rst_d1 =0; - wire rd_rst_comb; - wire rd_rst_i; - wire wr_rst_comb; - wire wr_rst_i; - - - - //Special ideal FIFO signals - reg [C_DOUT_WIDTH-1:0] ideal_dout; - wire [C_DOUT_WIDTH-1:0] ideal_dout_out; - reg [C_DOUT_WIDTH-1:0] ideal_dout_d1; - reg ideal_wr_ack; - reg ideal_valid; - reg ideal_overflow; - reg ideal_underflow; - reg ideal_full; - reg ideal_empty; - reg ideal_almost_full; - reg ideal_almost_empty; - reg ideal_prog_full; - reg ideal_prog_empty; - - //MSBs of the counts - reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count; - reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count; - - //user specified value for reseting the size of the fifo - reg [C_DOUT_WIDTH-1:0] dout_reset_val; - - //temporary registers for WR_RESPONSE_LATENCY feature - - integer tmp_wr_listsize; - integer tmp_rd_listsize; - - //Signal for registered version of prog full and empty - reg prog_full_d; - reg prog_empty_d; - - //Threshold values for Programmable Flags - integer prog_empty_actual_thresh_assert; - integer prog_empty_actual_thresh_negate; - integer prog_full_actual_thresh_assert; - integer prog_full_actual_thresh_negate; - - - /**************************************************************************** - * Function Declarations - ***************************************************************************/ - - task write_fifo; - begin - memory[wr_ptr] <= DIN; - if (wr_ptr == 0) begin - wr_ptr <= C_WR_DEPTH - 1; - end else begin - wr_ptr <= wr_ptr - 1; - end - end - endtask // write_fifo - - task read_fifo; - integer i; - reg [C_DOUT_WIDTH-1:0] tmp_dout; - reg [C_DIN_WIDTH-1:0] memory_read; - reg [31:0] tmp_rd_ptr; - reg [31:0] rd_ptr_high; - reg [31:0] rd_ptr_low; - begin - // output is wider than input - if (reads_per_write == 0) begin - tmp_dout = 0; - tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); - for (i = writes_per_read - 1; i >= 0; i = i - 1) begin - tmp_dout = tmp_dout << C_DIN_WIDTH; - tmp_dout = tmp_dout | memory[tmp_rd_ptr]; - if (tmp_rd_ptr == 0) begin - tmp_rd_ptr = C_WR_DEPTH - 1; - end else begin - tmp_rd_ptr = tmp_rd_ptr - 1; - end - end - - // output is symmetric - end else if (reads_per_write == 1) begin - tmp_dout = memory[rd_ptr]; - - // input is wider than output - end else begin - rd_ptr_high = rd_ptr >> log2_reads_per_write; - rd_ptr_low = rd_ptr & (reads_per_write - 1); - memory_read = memory[rd_ptr_high]; - tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); - end - ideal_dout <= tmp_dout; - if (rd_ptr == 0) begin - rd_ptr <= C_RD_DEPTH - 1; - end else begin - rd_ptr <= rd_ptr - 1; - end - end - endtask - - /**************************************************************************** - * log2_val - * Returns the 'log2' value for the input value for the supported ratios - ***************************************************************************/ - function [31:0] log2_val; - input [31:0] binary_val; - - begin - if (binary_val == 8) begin - log2_val = 3; - end else if (binary_val == 4) begin - log2_val = 2; - end else begin - log2_val = 1; - end - end - endfunction - - /************************************************************************* - * hexstr_conv - * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) - ***********************************************************************/ - function [C_DOUT_WIDTH-1:0] hexstr_conv; - input [(C_DOUT_WIDTH*8)-1:0] def_data; - - integer index,i,j; - reg [3:0] bin; - - begin - index = 0; - hexstr_conv = 'b0; - for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) - begin - case (def_data[7:0]) - 8'b00000000 : - begin - bin = 4'b0000; - i = -1; - end - 8'b00110000 : bin = 4'b0000; - 8'b00110001 : bin = 4'b0001; - 8'b00110010 : bin = 4'b0010; - 8'b00110011 : bin = 4'b0011; - 8'b00110100 : bin = 4'b0100; - 8'b00110101 : bin = 4'b0101; - 8'b00110110 : bin = 4'b0110; - 8'b00110111 : bin = 4'b0111; - 8'b00111000 : bin = 4'b1000; - 8'b00111001 : bin = 4'b1001; - 8'b01000001 : bin = 4'b1010; - 8'b01000010 : bin = 4'b1011; - 8'b01000011 : bin = 4'b1100; - 8'b01000100 : bin = 4'b1101; - 8'b01000101 : bin = 4'b1110; - 8'b01000110 : bin = 4'b1111; - 8'b01100001 : bin = 4'b1010; - 8'b01100010 : bin = 4'b1011; - 8'b01100011 : bin = 4'b1100; - 8'b01100100 : bin = 4'b1101; - 8'b01100101 : bin = 4'b1110; - 8'b01100110 : bin = 4'b1111; - default : - begin - bin = 4'bx; - end - endcase - for( j=0; j<4; j=j+1) - begin - if ((index*4)+j < C_DOUT_WIDTH) - begin - hexstr_conv[(index*4)+j] = bin[j]; - end - end - index = index + 1; - def_data = def_data >> 8; - end - end - endfunction - - /************************************************************************* - * Initialize Signals for clean power-on simulation - *************************************************************************/ - initial - begin - num_wr_bits = 0; - num_rd_bits = 0; - next_num_wr_bits = 0; - next_num_rd_bits = 0; - rd_ptr = C_RD_DEPTH - 1; - wr_ptr = C_WR_DEPTH - 1; - rd_ptr_wrclk = rd_ptr; - wr_ptr_rdclk = wr_ptr; - dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); - ideal_dout = dout_reset_val; - ideal_wr_ack = 1'b0; - ideal_valid = 1'b0; - ideal_overflow = 1'b0; - ideal_underflow = 1'b0; - //Modified the start-up value of FULL to '0' in v3.2 (IP2_Im) - //ideal_full = C_FULL_RESET_VAL; //was in v3.1 - ideal_full = 1'b0; //v3.2 - ideal_empty = 1'b1; - //Modified the start-up value of ALMOST_FULL to '0' in v3.2 (IP2_Im) - //ideal_almost_full = C_ALMOST_FULL_RESET_VAL; //was in v3.1 - ideal_almost_full = 1'b0; //v3.2 - ideal_almost_empty = 1'b1; - ideal_wr_count = 0; - ideal_rd_count = 0; - //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) - //ideal_prog_full = C_PROG_FULL_RESET_VAL; //was in v3.1 - ideal_prog_full = 1'b0; //v3.2 - ideal_prog_empty = 1'b1; - //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) - //Therefore, prog_full_d has to start-up at '0' too - //prog_full_d = C_PROG_FULL_RESET_VAL; //was in v3.1 - prog_full_d = 1'b0; //v3.2 - prog_empty_d = 1'b1; - end - - - - /************************************************************************* - * Assign Internal ideal signals to output ports - *************************************************************************/ - assign ideal_dout_out= (C_PRELOAD_LATENCY==2 && - (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? - ideal_dout_d1: ideal_dout; - assign DOUT = ideal_dout_out; - assign FULL = ideal_full; - assign EMPTY = ideal_empty; - assign ALMOST_FULL = ideal_almost_full; - assign ALMOST_EMPTY = ideal_almost_empty; - assign num_write_words_sized_i=C_USE_FWFT_DATA_COUNT? - num_write_words_sized_fwft:num_write_words_sized; - assign num_read_words_sized_i=C_USE_FWFT_DATA_COUNT? - num_read_words_sized_fwft:num_read_words_sized; - assign num_write_words_dc_i = C_USE_FWFT_DATA_COUNT? - num_write_words_fwft_dc: num_write_words_dc; - assign num_read_words_dc_i = C_USE_FWFT_DATA_COUNT? - num_read_words_fwft_dc: num_read_words_dc; - assign WR_DATA_COUNT = ideal_wr_count; - assign RD_DATA_COUNT = ideal_rd_count; - assign PROG_FULL = ideal_prog_full; - assign PROG_EMPTY = ideal_prog_empty; - - //Handshaking signals can be active low, depending on _LOW parameters - assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; - assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; - assign valid_out = (C_PRELOAD_LATENCY==2 && - (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? - valid_d1: valid_i; - assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; - assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; - - assign WR_ACK = wr_ack_i ? !C_WR_ACK_LOW : C_WR_ACK_LOW; - assign wr_ack_i = (C_WR_RESPONSE_LATENCY==1) ? ideal_wr_ack : - (WR_EN & !FULL); - assign OVERFLOW = overflow_i ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; - assign overflow_i = (C_WR_RESPONSE_LATENCY==1) ? ideal_overflow : - (WR_EN & FULL); - - /******************************************************************************* - * Internal reset logics - ******************************************************************************/ - assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg; - assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg; - assign wr_rst_i = C_HAS_RST ? wr_rst_reg : 0; - assign rd_rst_i = C_HAS_RST ? rd_rst_reg : 0; - - - always @(posedge RD_CLK or posedge rd_rst_i) begin - if (rd_rst_i == 1'b1) begin - valid_d1 <= 1'b0; - end else begin - valid_d1 <= valid_i; - end - end - always @(posedge RD_CLK or posedge rd_rst_i) begin - if (rd_rst_i == 1'b1) begin - ideal_dout_d1 <= dout_reset_val; - end else begin - ideal_dout_d1 <= ideal_dout; - end - end - - always @(posedge WR_CLK or posedge RST) begin - if (RST == 1'b1) begin - wr_rst_asreg <= 1'b1; - end else begin - if (wr_rst_asreg_d1 == 1'b1) begin - wr_rst_asreg <= 1'b0; - end else begin - wr_rst_asreg <= wr_rst_asreg; - end - end - end - - always @(posedge WR_CLK) begin - wr_rst_asreg_d1 <= wr_rst_asreg; - wr_rst_asreg_d2 <= wr_rst_asreg_d1; - end - - always @(posedge WR_CLK or posedge wr_rst_comb) begin - if (wr_rst_comb == 1'b1) begin - wr_rst_reg <= 1'b1; - end else begin - wr_rst_reg <= 1'b0; - end - end - - always @(posedge WR_CLK or posedge wr_rst_i) begin - if (wr_rst_i == 1'b1) begin - wr_rst_d1 <= 1'b1; - end else begin - wr_rst_d1 <= wr_rst_i; - end - end - always @(posedge RD_CLK or posedge RST) begin - if (RST == 1'b1) begin - rd_rst_asreg <= 1'b1; - end else begin - if (rd_rst_asreg_d1 == 1'b1) begin - rd_rst_asreg <= 1'b0; - end else begin - rd_rst_asreg <= rd_rst_asreg; - end - end - end - - always @(posedge RD_CLK) begin - rd_rst_asreg_d1 <= rd_rst_asreg; - rd_rst_asreg_d2 <= rd_rst_asreg_d1; - end - - always @(posedge RD_CLK or posedge rd_rst_comb) begin - if (rd_rst_comb == 1'b1) begin - rd_rst_reg <= 1'b1; - end else begin - rd_rst_reg <= 1'b0; - end - end - - //Generate overflow and underflow flags seperately - //because they don't support async rst - always @(posedge WR_CLK) begin - ideal_overflow <= WR_EN & ideal_full; - end - always @(posedge RD_CLK) begin - ideal_underflow <= ideal_empty & RD_EN; - end - - /******************************************************************************* - * Write and Read Logics - ******************************************************************************/ - always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w - - /****** Reset fifo (case 1)***************************************/ - if (wr_rst_i == 1'b1) begin - num_wr_bits <= 0; - next_num_wr_bits <= 0; - wr_ptr <= C_WR_DEPTH - 1; - rd_ptr_wrclk <= C_RD_DEPTH - 1; - ideal_wr_ack <= 0; - ideal_full <= C_FULL_FLAGS_RST_VAL; - ideal_almost_full <= C_FULL_FLAGS_RST_VAL; - ideal_wr_count <= 0; - - ideal_prog_full <= C_FULL_FLAGS_RST_VAL; - prog_full_d <= C_FULL_FLAGS_RST_VAL; - - end else begin //wr_rst_i==0 - - //Determine the current number of words in the FIFO - tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : - num_wr_bits/C_DIN_WIDTH; - rd_ptr_wrclk_next = rd_ptr; - if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin - next_num_wr_bits = num_wr_bits - - C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH - - rd_ptr_wrclk_next); - end else begin - next_num_wr_bits = num_wr_bits - - C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); - end - - //If this is a write, handle the write by adding the value - // to the linked list, and updating all outputs appropriately - if (WR_EN == 1'b1) begin - if (ideal_full == 1'b1) begin - - //If the FIFO is full, do NOT perform the write, - // update flags accordingly - if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD - >= C_FIFO_WR_DEPTH) begin - //write unsuccessful - do not change contents - - //Do not acknowledge the write - ideal_wr_ack <= 0; - //Reminder that FIFO is still full - ideal_full <= 1'b1; - ideal_almost_full <= 1'b1; - - ideal_wr_count <= num_write_words_sized_i; - - //If the FIFO is one from full, but reporting full - end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == - C_FIFO_WR_DEPTH-1) begin - //No change to FIFO - - //Write not successful - ideal_wr_ack <= 0; - //With DEPTH-1 words in the FIFO, it is almost_full - ideal_full <= 1'b0; - ideal_almost_full <= 1'b1; - - ideal_wr_count <= num_write_words_sized_i; - - - //If the FIFO is completely empty, but it is - // reporting FULL for some reason (like reset) - end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= - C_FIFO_WR_DEPTH-2) begin - //No change to FIFO - - //Write not successful - ideal_wr_ack <= 0; - //FIFO is really not close to full, so change flag status. - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - ideal_wr_count <= num_write_words_sized_i; - end //(tmp_wr_listsize == 0) - - end else begin - - //If the FIFO is full, do NOT perform the write, - // update flags accordingly - if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= - C_FIFO_WR_DEPTH) begin - //write unsuccessful - do not change contents - - //Do not acknowledge the write - ideal_wr_ack <= 0; - //Reminder that FIFO is still full - ideal_full <= 1'b1; - ideal_almost_full <= 1'b1; - - ideal_wr_count <= num_write_words_sized_i; - - //If the FIFO is one from full - end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == - C_FIFO_WR_DEPTH-1) begin - //Add value on DIN port to FIFO - write_fifo; - next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; - - //Write successful, so issue acknowledge - // and no error - ideal_wr_ack <= 1; - //This write is CAUSING the FIFO to go full - ideal_full <= 1'b1; - ideal_almost_full <= 1'b1; - - ideal_wr_count <= num_write_words_sized_i; - - //If the FIFO is 2 from full - end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == - C_FIFO_WR_DEPTH-2) begin - //Add value on DIN port to FIFO - write_fifo; - next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; - //Write successful, so issue acknowledge - // and no error - ideal_wr_ack <= 1; - //Still 2 from full - ideal_full <= 1'b0; - //2 from full, and writing, so set almost_full - ideal_almost_full <= 1'b1; - - ideal_wr_count <= num_write_words_sized_i; - - //If the FIFO is not close to being full - end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < - C_FIFO_WR_DEPTH-2) begin - //Add value on DIN port to FIFO - write_fifo; - next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; - //Write successful, so issue acknowledge - // and no error - ideal_wr_ack <= 1; - //Not even close to full. - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - ideal_wr_count <= num_write_words_sized_i; - - end - - end - - end else begin //(WR_EN == 1'b1) - - //If user did not attempt a write, then do not - // give ack or err - ideal_wr_ack <= 0; - - //Implied statements: - //ideal_empty <= ideal_empty; - //ideal_almost_empty <= ideal_almost_empty; - - //Check for full - if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH) - ideal_full <= 1'b1; - else - ideal_full <= 1'b0; - - //Check for almost_full - if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH-1) - ideal_almost_full <= 1'b1; - else - ideal_almost_full <= 1'b0; - - ideal_wr_count <= num_write_words_sized_i; - end - - /********************************************************* - * Programmable FULL flags - *********************************************************/ - //Single Programmable Full Constant Threshold - if (C_PROG_FULL_TYPE==1) begin - if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; - prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; - end else begin - prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL; - prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL; - end - - //Two Programmable Full Constant Thresholds - end else if (C_PROG_FULL_TYPE==2) begin - if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; - prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL-EXTRA_WORDS; - end else begin - prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL; - prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL; - end - - //Single Programmable Full Threshold Input - end else if (C_PROG_FULL_TYPE==3) begin - if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - prog_full_actual_thresh_assert = PROG_FULL_THRESH-EXTRA_WORDS; - prog_full_actual_thresh_negate = PROG_FULL_THRESH-EXTRA_WORDS; - end else begin - prog_full_actual_thresh_assert = PROG_FULL_THRESH; - prog_full_actual_thresh_negate = PROG_FULL_THRESH; - end - - //Two Programmable Full Threshold Inputs - end else if (C_PROG_FULL_TYPE==4) begin - if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT-EXTRA_WORDS; - prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE-EXTRA_WORDS; - end else begin - prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT; - prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE; - end - end //C_PROG_FULL_TYPE - - if (num_write_words_pf==0) begin - prog_full_d <= 1'b0; - end else begin - if (((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) - == prog_full_actual_thresh_assert-1) && WR_EN) begin - prog_full_d <= 1'b1; - end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) - >= prog_full_actual_thresh_assert) begin - prog_full_d <= 1'b1; - end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) - < prog_full_actual_thresh_negate) begin - prog_full_d <= 1'b0; - end - end - - if (wr_rst_d1==1 && wr_rst_i==0) begin - ideal_prog_full <= 0; - end else begin - ideal_prog_full <= prog_full_d; - end - num_wr_bits <= next_num_wr_bits; - rd_ptr_wrclk <= rd_ptr; - - end //wr_rst_i==0 - end // write always - - always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r - - /****** Reset fifo (case 1)***************************************/ - if (rd_rst_i) begin - num_rd_bits <= 0; - next_num_rd_bits <= 0; - rd_ptr <= C_RD_DEPTH -1; - wr_ptr_rdclk <= C_WR_DEPTH -1; - ideal_dout <= dout_reset_val; - ideal_valid <= 1'b0; - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - ideal_rd_count <= 0; - - ideal_prog_empty <= 1'b1; - prog_empty_d <= 1; - - - end else begin //rd_rst_i==0 - - //Determine the current number of words in the FIFO - tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : - num_rd_bits/C_DOUT_WIDTH; - wr_ptr_rdclk_next = wr_ptr; - - if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin - next_num_rd_bits = num_rd_bits + - C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH - - wr_ptr_rdclk_next); - end else begin - next_num_rd_bits = num_rd_bits + - C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); - end - - /*****************************************************************/ - // Read Operation - Read Latency 1 - /*****************************************************************/ - if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin - - if (RD_EN == 1'b1) begin - - if (ideal_empty == 1'b1) begin - - //If the FIFO is completely empty, and is reporting empty - if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) - begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= 1'b0; - //Reminder that FIFO is still empty - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - end // if (tmp_rd_listsize <= 0) - - //If the FIFO is one from empty, but it is reporting empty - else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) - begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= 1'b0; - //Note that FIFO is no longer empty, but is almost empty (has one word left) - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - - end // if (tmp_rd_listsize == 1) - - //If the FIFO is two from empty, and is reporting empty - else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) - begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= 1'b0; - //Fifo has two words, so is neither empty or almost empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - ideal_rd_count <= num_read_words_sized_i; - - end // if (tmp_rd_listsize == 2) - - //If the FIFO is not close to empty, but is reporting that it is - // Treat the FIFO as empty this time, but unset EMPTY flags. - if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) - end // else: if(ideal_empty == 1'b1) - - else //if (ideal_empty == 1'b0) - begin - - //If the FIFO is completely full, and we are successfully reading from it - if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) - begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= 1'b1; - //Not close to empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - ideal_rd_count <= num_read_words_sized_i; - - end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) - - //If the FIFO is not close to being empty - else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) - begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= 1'b1; - //Not close to empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - ideal_rd_count <= num_read_words_sized_i; - - end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) - - //If the FIFO is two from empty - else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) - begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= 1'b1; - //Fifo is not yet empty. It is going almost_empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - - end // if (tmp_rd_listsize == 2) - - //If the FIFO is one from empty - else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) - begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= 1'b1; - //Note that FIFO is GOING empty - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - - end // if (tmp_rd_listsize == 1) - - - //If the FIFO is completely empty - else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) - begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= 1'b0; - //Reminder that FIFO is still empty - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - - end // if (tmp_rd_listsize <= 0) - - end // if (ideal_empty == 1'b0) - - end //(RD_EN == 1'b1) - - else //if (RD_EN == 1'b0) - begin - //If user did not attempt a read, do not give an ack or err - ideal_valid <= 1'b0; - - //Check for empty - if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) - ideal_empty <= 1'b1; - else - ideal_empty <= 1'b0; - - //Check for almost_empty - if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1) - ideal_almost_empty <= 1'b1; - else - ideal_almost_empty <= 1'b0; - - ideal_rd_count <= num_read_words_sized_i; - - end // else: !if(RD_EN == 1'b1) - - /*****************************************************************/ - // Read Operation - Read Latency 0 - /*****************************************************************/ - end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - if (RD_EN == 1'b1) begin - - if (ideal_empty == 1'b1) begin - - //If the FIFO is completely empty, and is reporting empty - if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= 1'b0; - //Reminder that FIFO is still empty - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - - //If the FIFO is one from empty, but it is reporting empty - end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= 1'b0; - //Note that FIFO is no longer empty, but is almost empty (has one word left) - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - - //If the FIFO is two from empty, and is reporting empty - end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= 1'b0; - //Fifo has two words, so is neither empty or almost empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - ideal_rd_count <= num_read_words_sized_i; - - //If the FIFO is not close to empty, but is reporting that it is - // Treat the FIFO as empty this time, but unset EMPTY flags. - end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && - (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) - - end else begin - - //If the FIFO is completely full, and we are successfully reading from it - if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= 1'b1; - //Not close to empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - ideal_rd_count <= num_read_words_sized_i; - - //If the FIFO is not close to being empty - end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && - (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= 1'b1; - //Not close to empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - ideal_rd_count <= num_read_words_sized_i; - - //If the FIFO is two from empty - end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= 1'b1; - //Fifo is not yet empty. It is going almost_empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - - //If the FIFO is one from empty - end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= 1'b1; - //Note that FIFO is GOING empty - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - - //If the FIFO is completely empty - end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= 1'b0; - //Reminder that FIFO is still empty - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - - end // if (tmp_rd_listsize <= 0) - - end // if (ideal_empty == 1'b0) - - end else begin//(RD_EN == 1'b0) - - - //If user did not attempt a read, do not give an ack or err - ideal_valid <= 1'b0; - - //Check for empty - if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) - ideal_empty <= 1'b1; - else - ideal_empty <= 1'b0; - - //Check for almost_empty - if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1) - ideal_almost_empty <= 1'b1; - else - ideal_almost_empty <= 1'b0; - - ideal_rd_count <= num_read_words_sized_i; - - end // else: !if(RD_EN == 1'b1) - end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) - - - /********************************************************* - * Programmable EMPTY flags - *********************************************************/ - //Determine the Assert and Negate thresholds for Programmable Empty - // (Subtract 2 read-sized words when using Preload 0) - - //Single Programmable Empty Constant Threshold - if (C_PROG_EMPTY_TYPE==1) begin - if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; - prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; - end - else begin - prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; - prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL; - end - - //Two Programmable Empty Constant Thresholds - end else if (C_PROG_EMPTY_TYPE==2) begin - if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; - prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL-2; - end - else begin - prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; - prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL; - end - - //Single Programmable Empty Constant Threshold - end else if (C_PROG_EMPTY_TYPE==3) begin - if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH-2; - prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH-2; - end - else begin - prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH; - prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH; - - end - //Two Programmable Empty Constant Thresholds - end else if (C_PROG_EMPTY_TYPE==4) begin - if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT-2; - prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE-2; - end - else begin - prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT; - prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE; - end - end - - if ((num_read_words_pe/C_DEPTH_RATIO_WR == prog_empty_actual_thresh_assert+1) - && RD_EN) begin - prog_empty_d <= 1'b1; - end else if (num_read_words_pe/C_DEPTH_RATIO_WR - <= prog_empty_actual_thresh_assert) begin - prog_empty_d <= 1'b1; - end else if (num_read_words_pe/C_DEPTH_RATIO_WR - > prog_empty_actual_thresh_negate) begin - prog_empty_d <= 1'b0; - end - - - ideal_prog_empty <= prog_empty_d; - num_rd_bits <= next_num_rd_bits; - wr_ptr_rdclk <= wr_ptr; - end //rd_rst_i==0 - end //always - -endmodule // fifo_generator_v4_3_bhv_ver_as - - -/******************************************************************************* - * Declaration of top-level module - ******************************************************************************/ -module fifo_generator_v4_3_bhv_ver_ss - ( - CLK, RST, SRST, DIN, WR_EN, RD_EN, - PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, - PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, - DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, - ALMOST_EMPTY, VALID, UNDERFLOW, DATA_COUNT, - PROG_FULL, PROG_EMPTY - ); - -/****************************************************************************** - * Declare user parameters and their defaults - *****************************************************************************/ - parameter C_COMMON_CLOCK = 0; - parameter C_COUNT_TYPE = 0; - parameter C_DATA_COUNT_WIDTH = 2; - parameter C_DEFAULT_VALUE = ""; - parameter C_DIN_WIDTH = 8; - parameter C_DOUT_RST_VAL = ""; - parameter C_DOUT_WIDTH = 8; - parameter C_ENABLE_RLOCS = 0; - parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model - parameter C_HAS_ALMOST_EMPTY = 0; - parameter C_HAS_ALMOST_FULL = 0; - parameter C_HAS_BACKUP = 0; - parameter C_HAS_DATA_COUNT = 0; - parameter C_HAS_MEMINIT_FILE = 0; - parameter C_HAS_OVERFLOW = 0; - parameter C_HAS_RD_DATA_COUNT = 0; - parameter C_HAS_RD_RST = 0; - parameter C_HAS_RST = 0; - parameter C_HAS_SRST = 0; - parameter C_HAS_UNDERFLOW = 0; - parameter C_HAS_VALID = 0; - parameter C_HAS_WR_ACK = 0; - parameter C_HAS_WR_DATA_COUNT = 0; - parameter C_HAS_WR_RST = 0; - parameter C_IMPLEMENTATION_TYPE = 0; - parameter C_INIT_WR_PNTR_VAL = 0; - parameter C_MEMORY_TYPE = 1; - parameter C_MIF_FILE_NAME = ""; - parameter C_OPTIMIZATION_MODE = 0; - parameter C_OVERFLOW_LOW = 0; - parameter C_PRELOAD_LATENCY = 1; - parameter C_PRELOAD_REGS = 0; - parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; - parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; - parameter C_PROG_EMPTY_TYPE = 0; - parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; - parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; - parameter C_PROG_FULL_TYPE = 0; - parameter C_RD_DATA_COUNT_WIDTH = 2; - parameter C_RD_DEPTH = 256; - parameter C_RD_PNTR_WIDTH = 8; - parameter C_UNDERFLOW_LOW = 0; - parameter C_VALID_LOW = 0; - parameter C_WR_ACK_LOW = 0; - parameter C_WR_DATA_COUNT_WIDTH = 2; - parameter C_WR_DEPTH = 256; - parameter C_WR_PNTR_WIDTH = 8; - parameter C_WR_RESPONSE_LATENCY = 1; - parameter C_FULL_FLAGS_RST_VAL = 1; - parameter C_USE_EMBEDDED_REG = 0; - - -/****************************************************************************** - * Declare Input and Output Ports - *****************************************************************************/ - input CLK; - input [C_DIN_WIDTH-1:0] DIN; - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; - input RD_EN; - input RST; - input SRST; - input WR_EN; - output ALMOST_EMPTY; - output ALMOST_FULL; - output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; - output [C_DOUT_WIDTH-1:0] DOUT; - output EMPTY; - output FULL; - output OVERFLOW; - output PROG_EMPTY; - output PROG_FULL; - output VALID; - output UNDERFLOW; - output WR_ACK; - -/******************************************************************************* - * Input and output register declarations - ******************************************************************************/ -/******************************************************************************* - * Parameters used as constants - ******************************************************************************/ - //When RST is present, set FULL reset value to '1'. - //If core has no RST, make sure FULL powers-on as '0'. - //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not - //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. - // Therefore, during SRST, all the FULL flags reset to 0. - parameter C_HAS_FAST_FIFO = 0; - parameter C_FIFO_WR_DEPTH = (C_COMMON_CLOCK) ? C_WR_DEPTH : C_WR_DEPTH - 1; - parameter C_FIFO_RD_DEPTH = (C_COMMON_CLOCK) ? C_RD_DEPTH : C_RD_DEPTH - 1; - - /**************************************************************************** - * Internal Registers and wires - ***************************************************************************/ - wire wr_ack_i; - wire overflow_i; - wire underflow_i; - wire valid_i; - wire valid_out; - reg valid_d1; - wire srst_i; - /******************************************************************************* - * Internal registers and wires for internal reset logics - ******************************************************************************/ - reg rst_asreg =0; - reg rst_asreg_d1 =0; - reg rst_asreg_d2 =0; - reg rst_reg =0; - reg rst_d1 =0; - wire rst_comb; - wire rst_i; - - - //Memory which will be used to simulate a FIFO - reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; - reg [31:0] num_bits; - reg [31:0] wr_ptr; - reg [31:0] rd_ptr; - wire [31:0] num_read_words = num_bits/C_DOUT_WIDTH; - reg [31:0] num_read_words_q; - wire [31:0] num_write_words = num_bits/C_DIN_WIDTH; - reg [31:0] num_write_words_q; - //Removed power_on_timer in v3.2 (IP2_Im). For all reset types (Async, Sync, or no reset), the power-on values of the flags in the core are modified so that the core is ready to use from the very first clock cycle. - //reg [3:0] power_on_timer; - - //Special ideal FIFO signals - reg [C_DOUT_WIDTH-1:0] ideal_dout; - reg [C_DOUT_WIDTH-1:0] ideal_dout_d1; - wire [C_DOUT_WIDTH-1:0] ideal_dout_out; - reg ideal_wr_ack; - reg ideal_valid; - reg ideal_overflow; - reg ideal_underflow; - reg ideal_full; - reg ideal_empty; - reg ideal_almost_full; - reg ideal_almost_empty; - reg ideal_prog_full; - reg ideal_prog_empty; - - - //MSBs of the counts - wire [C_DATA_COUNT_WIDTH-1:0] ideal_d_count; - - //user specified value for reseting the size of the fifo - reg [C_DOUT_WIDTH-1:0] dout_reset_val; - - - //temporary registers for WR_RESPONSE_LATENCY feature - reg ideal_wr_ack_q; - reg ideal_overflow_q; - - reg prog_full_d; - reg prog_empty_d; - - //Delayed version of RST - reg rst_q; - reg rst_qq; - - /**************************************************************************** - * Function Declarations - ***************************************************************************/ - task write_fifo; - begin - memory[wr_ptr] <= DIN; - if (wr_ptr == 0) begin - wr_ptr <= C_WR_DEPTH - 1; - end else begin - wr_ptr <= wr_ptr - 1; - end - end - endtask // write_fifo - - task read_fifo; - begin - ideal_dout <= memory[rd_ptr]; - if (rd_ptr == 0) begin - rd_ptr <= C_RD_DEPTH - 1; - end else begin - rd_ptr <= rd_ptr - 1; - end - end - endtask - - /**************************************************************************** - * log2_val - * Returns the 'log2' value for the input value for the supported ratios - ***************************************************************************/ - function [31:0] log2_val; - input [31:0] binary_val; - - begin - if (binary_val == 8) begin - log2_val = 3; - end else if (binary_val == 4) begin - log2_val = 2; - end else begin - log2_val = 1; - end - end - endfunction - - /**************************************************************************** - * hexstr_conv - * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) - ***************************************************************************/ - function [C_DOUT_WIDTH-1:0] hexstr_conv; - input [(C_DOUT_WIDTH*8)-1:0] def_data; - - integer index,i,j; - reg [3:0] bin; - - begin - index = 0; - hexstr_conv = 'b0; - for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) - begin - case (def_data[7:0]) - 8'b00000000 : - begin - bin = 4'b0000; - i = -1; - end - 8'b00110000 : bin = 4'b0000; - 8'b00110001 : bin = 4'b0001; - 8'b00110010 : bin = 4'b0010; - 8'b00110011 : bin = 4'b0011; - 8'b00110100 : bin = 4'b0100; - 8'b00110101 : bin = 4'b0101; - 8'b00110110 : bin = 4'b0110; - 8'b00110111 : bin = 4'b0111; - 8'b00111000 : bin = 4'b1000; - 8'b00111001 : bin = 4'b1001; - 8'b01000001 : bin = 4'b1010; - 8'b01000010 : bin = 4'b1011; - 8'b01000011 : bin = 4'b1100; - 8'b01000100 : bin = 4'b1101; - 8'b01000101 : bin = 4'b1110; - 8'b01000110 : bin = 4'b1111; - 8'b01100001 : bin = 4'b1010; - 8'b01100010 : bin = 4'b1011; - 8'b01100011 : bin = 4'b1100; - 8'b01100100 : bin = 4'b1101; - 8'b01100101 : bin = 4'b1110; - 8'b01100110 : bin = 4'b1111; - default : - begin - bin = 4'bx; - end - endcase - for( j=0; j<4; j=j+1) - begin - if ((index*4)+j < C_DOUT_WIDTH) - begin - hexstr_conv[(index*4)+j] = bin[j]; - end - end - index = index + 1; - def_data = def_data >> 8; - end - end - endfunction - - /***************************************************************************** - * Initialize Signals - ****************************************************************************/ - initial begin - num_bits = 0; - num_read_words_q = 0; - num_write_words_q = 0; - rd_ptr = C_RD_DEPTH -1; - wr_ptr = C_WR_DEPTH -1; - dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); - ideal_dout = dout_reset_val; - ideal_wr_ack = 1'b0; - ideal_valid = 1'b0; - valid_d1 = 1'b0; - ideal_overflow = 1'b0; - ideal_underflow = 1'b0; - //Modified the start-up value of FULL to '0' in v3.2 (IP2_Im) - //ideal_full = C_FULL_RESET_VAL; //was in v3.1 - ideal_full = 1'b0; //v3.2 - ideal_empty = 1'b1; - //Modified the start-up value of ALMOST_FULL to '0' in v3.2 (IP2_Im) - //ideal_almost_full = C_ALMOST_FULL_RESET_VAL; //was in v3.1 - ideal_almost_full = 1'b0; - ideal_almost_empty = 1'b1; - //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) - //ideal_prog_full = C_PROG_FULL_RESET_VAL; //was in v3.1 - ideal_prog_full = 1'b0; //v3.2 - ideal_prog_empty = 1'b1; - - //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) - //Therefore, prog_full_d is also changed - //prog_full_d = C_PROG_FULL_RESET_VAL; //was in v3.1 - prog_full_d = 1'b0; //v3.2 - prog_empty_d = 1'b1; - - //Removed in v3.2 - //power_on_timer = C_HAS_RST ? 4'h3 : 4'h0; - - //Added these initial values in v3.2 to make it consistent with the synchronization flop stages in the core. - rst_q = 1'b0; - rst_qq = 1'b0; - end - - - /***************************************************************************** - * Assign Internal ideal signals to output ports - ****************************************************************************/ - assign ideal_dout_out= (C_USE_EMBEDDED_REG==1 && - (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? - ideal_dout_d1: ideal_dout; - assign DOUT = ideal_dout_out; - //was in v3.1 - //assign FULL = (power_on_timer) ? C_FULL_RESET_VAL : ideal_full; - //v3.2 - assign FULL = ideal_full; - - assign EMPTY = ideal_empty; - //was in v3.1 - //assign ALMOST_FULL = (power_on_timer) ? C_ALMOST_FULL_RESET_VAL : ideal_almost_full; - //v3.2 - assign ALMOST_FULL = ideal_almost_full; - - assign ALMOST_EMPTY = ideal_almost_empty; - - assign ideal_d_count = num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; - assign DATA_COUNT = ideal_d_count; - - //was in v3.1 - //assign PROG_FULL = (power_on_timer) ? C_PROG_FULL_RESET_VAL : ideal_prog_full; - //v3.2 - assign PROG_FULL = ideal_prog_full; - - assign PROG_EMPTY = ideal_prog_empty; - - //Handshaking signals can be active low, depending on _LOW parameters - assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; - assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; - assign valid_out = (C_PRELOAD_LATENCY==2 && - (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? - valid_d1: valid_i; - assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; - assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; - - assign WR_ACK = wr_ack_i ? !C_WR_ACK_LOW : C_WR_ACK_LOW; - assign wr_ack_i = (C_WR_RESPONSE_LATENCY==2) ? ideal_wr_ack_q : - (C_WR_RESPONSE_LATENCY==1) ? ideal_wr_ack : - (WR_EN & !FULL); - assign OVERFLOW = overflow_i ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; - assign overflow_i = (C_WR_RESPONSE_LATENCY==2) ? ideal_overflow_q : - (C_WR_RESPONSE_LATENCY==1) ? ideal_overflow : - (WR_EN & FULL); - - assign srst_i = C_HAS_SRST ? SRST : 0; - - /******************************************************************************* - * Internal reset logics - ******************************************************************************/ - assign rst_comb = !rst_asreg_d2 && rst_asreg; - assign rst_i = C_HAS_RST ? rst_reg : 0; - - always @(posedge CLK or posedge rst_i) begin - if (rst_i == 1'b1) begin - valid_d1 <= 1'b0; - end else begin - if (srst_i) begin - valid_d1 <= 1'b0; - end else begin - valid_d1 <= valid_i; - end - end - end - always @(posedge CLK or posedge rst_i) begin - if (rst_i == 1'b1) begin - ideal_dout_d1 <= dout_reset_val; - end else begin - if (srst_i) begin - ideal_dout_d1 <= dout_reset_val; - end else begin - ideal_dout_d1 <= ideal_dout; - end - end - end - - always @(posedge CLK or posedge RST) begin - if (RST == 1'b1) begin - rst_asreg <= 1'b1; - end else begin - if (rst_asreg_d1 == 1'b1) begin - rst_asreg <= 1'b0; - end else begin - rst_asreg <= rst_asreg; - end - end - end - - always @(posedge CLK) begin - rst_asreg_d1 <= rst_asreg; - rst_asreg_d2 <= rst_asreg_d1; - end - - always @(posedge CLK or posedge rst_comb) begin - if (rst_comb == 1'b1) begin - rst_reg <= 1'b1; - end else begin - rst_reg <= 1'b0; - end - end - - - /******************************************************************************* - * Write and Read Logics - ******************************************************************************/ - - always @(posedge CLK or posedge rst_i) - begin : gen_wr_ack_resp - - //Register reset - rst_q <= rst_i; - rst_qq <= rst_q; - - //Register output signals to achieve desired WR_RESPONSE latency - if (C_WR_RESPONSE_LATENCY == 2) begin - if (rst_i == 1) begin - ideal_wr_ack_q <= 0; - ideal_overflow_q <= 0; - end else begin - ideal_wr_ack_q <= ideal_wr_ack; - ideal_overflow_q <= ideal_overflow; - end - end - - //Removed in v3.2 - /* - if (rst_i == 1) begin - power_on_timer <= 0; - end else if (power_on_timer > 0) begin - power_on_timer <= power_on_timer -1; - end else begin - power_on_timer <= 0; - end - */ - end // block: gen_wr_ack_resp - - // block memory has a synchronous reset - always @(posedge CLK) begin : gen_fifo_blkmemdout - //Changed the latency of during async reset to '1' instead of '2' to make it consistent with the core. - //if (rst_i || rst_q || rst_qq) begin //was in v3.1 - if (rst_i || rst_q || srst_i) begin //v3.2 - /******Initialize Read Domain Signals************************************/ - if (C_MEMORY_TYPE == 1) begin - ideal_dout <= dout_reset_val; - end - //v3.2 - //end else begin - //if (C_MEMORY_TYPE == 1 && power_on_timer >= 2) begin //was in v3.1 - // if (C_MEMORY_TYPE == 1) begin //v3.2 - // ideal_dout <= dout_reset_val; - // end - end - end - - always @(posedge CLK or posedge rst_i) begin : gen_fifo - - /****** Reset fifo - Asynchronous Reset*************************************/ - //Changed the latency of during async reset to '1' instead of '2' to make it consistent with the core. - //if (rst_i || rst_q || rst_qq) begin //was in v3.1 - //if (rst_i || rst_q) begin //v3.2 - if (rst_i ) begin //v3.2 - /******Initialize Generic FIFO constructs********************************/ - num_bits <= 0; - wr_ptr <= C_WR_DEPTH - 1; - rd_ptr <= C_RD_DEPTH - 1; - num_read_words_q <= 0; - num_write_words_q <= 0; - - - /******Initialize Write Domain Signals***********************************/ - ideal_wr_ack <= 0; - ideal_full <= C_FULL_FLAGS_RST_VAL; - ideal_almost_full <= C_FULL_FLAGS_RST_VAL; - - /******Initialize Read Domain Signals************************************/ - if (C_MEMORY_TYPE != 1) begin - ideal_dout <= dout_reset_val; - end - ideal_valid <= 1'b0; - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - end else begin - if (srst_i) begin - // SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. - if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin - /******Initialize Generic FIFO constructs********************************/ - num_bits <= 0; - wr_ptr <= C_WR_DEPTH - 1; - rd_ptr <= C_RD_DEPTH - 1; - num_read_words_q <= 0; - num_write_words_q <= 0; - - /******Initialize Write Domain Signals***********************************/ - ideal_wr_ack <= 0; - ideal_full <= 0; //'0' - ideal_almost_full <= 0; //'0' - - /******Initialize Read Domain Signals************************************/ - //Reset DOUT of Sync DRAM. Sync BRAM DOUT was reset in the above always block. - if (C_MEMORY_TYPE == 2) begin - ideal_dout <= dout_reset_val; - end - ideal_valid <= 1'b0; - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - end - - end else begin //normal operating conditions - /**********************************************************************/ - // Synchronous FIFO Condition #1 : Writing and not reading - /**********************************************************************/ - if (WR_EN & ~RD_EN) begin - - /*********************************/ - //If the FIFO is full, do NOT perform the write, - // update flags accordingly - /*********************************/ - if (num_write_words >= C_FIFO_WR_DEPTH) begin - ideal_wr_ack <= 0; - - //still full - ideal_full <= 1'b1; - ideal_almost_full <= 1'b1; - - //write unsuccessful - do not change contents - - // no read attempted - ideal_valid <= 1'b0; - - //Not near empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - - /*********************************/ - //If the FIFO is reporting FULL - // (Startup condition) - /*********************************/ - end else if ((num_write_words < C_FIFO_WR_DEPTH) && (ideal_full == 1'b1)) begin - ideal_wr_ack <= 0; - - //still full - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //write unsuccessful - do not change contents - - // no read attempted - ideal_valid <= 1'b0; - - //FIFO EMPTY in this state can not be determined - //ideal_empty <= 1'b0; - //ideal_almost_empty <= 1'b0; - - - /*********************************/ - //If the FIFO is one from full - /*********************************/ - end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin - //good write - ideal_wr_ack <= 1; - - //FIFO is one from FULL and going FULL - ideal_full <= 1'b1; - ideal_almost_full <= 1'b1; - - //Add input data - write_fifo; - - // no read attempted - ideal_valid <= 1'b0; - - //Not near empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - num_bits <= num_bits + C_DIN_WIDTH; - - /*********************************/ - //If the FIFO is 2 from full - /*********************************/ - end else if (num_write_words == C_FIFO_WR_DEPTH-2) begin - //good write - ideal_wr_ack <= 1; - - //2 from full, and writing, so set almost_full - ideal_full <= 1'b0; - ideal_almost_full <= 1'b1; - - //Add input data - write_fifo; - - //no read attempted - ideal_valid <= 1'b0; - - //Not near empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - num_bits <= num_bits + C_DIN_WIDTH; - - /*********************************/ - //If the FIFO is ALMOST EMPTY - /*********************************/ - end else if (num_read_words == 1) begin - //good write - ideal_wr_ack <= 1; - - //Not near FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //Add input data - write_fifo; - - // no read attempted - ideal_valid <= 1'b0; - - //Leaving ALMOST_EMPTY - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - num_bits <= num_bits + C_DIN_WIDTH; - - /*********************************/ - //If the FIFO is EMPTY - /*********************************/ - end else if (num_read_words == 0) begin - // good write - ideal_wr_ack <= 1; - - //Not near FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //Add input data - write_fifo; - - // no read attempted - ideal_valid <= 1'b0; - - //Leaving EMPTY (still ALMOST_EMPTY) - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b1; - - num_bits <= num_bits + C_DIN_WIDTH; - - /*********************************/ - //If the FIFO is not near EMPTY or FULL - /*********************************/ - end else begin - // good write - ideal_wr_ack <= 1; - - //Not near FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //Add input data - write_fifo; - - // no read attempted - ideal_valid <= 1'b0; - - //Not near EMPTY - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - num_bits <= num_bits + C_DIN_WIDTH; - - end // average case - - - /**********************************************************************/ - // Synchronous FIFO Condition #2 : Reading and not writing - /**********************************************************************/ - end else if (~WR_EN & RD_EN) begin - - /*********************************/ - //If the FIFO is EMPTY - /*********************************/ - if ((num_read_words == 0) || (ideal_empty == 1'b1)) begin - //no write attemped - ideal_wr_ack <= 0; - - //FIFO is not near FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //Read will fail - ideal_valid <= 1'b0; - - //FIFO is still empty - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - //No read - - /*********************************/ - //If the FIFO is ALMOST EMPTY - /*********************************/ - end else if (num_read_words == 1) begin - //no write attempted - ideal_wr_ack <= 0; - - //FIFO is not near FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //Read successful - ideal_valid <= 1'b1; - - //This read will make FIFO go empty - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - //Get the data from the FIFO - read_fifo; - num_bits <= num_bits - C_DIN_WIDTH; - - - /*********************************/ - //If the FIFO is 2 from EMPTY - /*********************************/ - end else if (num_read_words == 2) begin - - //no write attempted - ideal_wr_ack <= 0; - - //FIFO is not near FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //Read successful - ideal_valid <= 1'b1; - - //FIFO is going ALMOST_EMPTY - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b1; - - //Get the data from the FIFO - read_fifo; - num_bits <= num_bits - C_DOUT_WIDTH; - - - - /*********************************/ - //If the FIFO is one from full - /*********************************/ - end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin - - //no write attempted - ideal_wr_ack <= 0; - - //FIFO is leaving ALMOST FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //Read successful - ideal_valid <= 1'b1; - - //Not near empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - //Read from the FIFO - read_fifo; - num_bits <= num_bits - C_DOUT_WIDTH; - - - /*********************************/ - // FIFO is FULL - /*********************************/ - end else if (num_write_words >= C_FIFO_WR_DEPTH) - begin - //no write attempted - ideal_wr_ack <= 0; - - //FIFO is leaving FULL, but is still ALMOST_FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b1; - - //Read successful - ideal_valid <= 1'b1; - - //Not near empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - //Read from the FIFO - read_fifo; - num_bits <= num_bits - C_DOUT_WIDTH; - - /*********************************/ - //If the FIFO is not near EMPTY or FULL - /*********************************/ - end else begin - //no write attemped - ideal_wr_ack <= 0; - - //Not near empty - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //Read successful - ideal_valid <= 1'b1; - - //Not near empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - //Read from the FIFO - read_fifo; - num_bits <= num_bits - C_DOUT_WIDTH; - - - end // average read - - - /**********************************************************************/ - // Synchronous FIFO Condition #3 : Reading and writing - /**********************************************************************/ - end else if (WR_EN & RD_EN) begin - - /*********************************/ - // FIFO is FULL - /*********************************/ - if (num_write_words >= C_FIFO_WR_DEPTH) begin - - ideal_wr_ack <= 0; - - //Read will be successful, so FIFO will leave FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b1; - - //Read successful - ideal_valid <= 1'b1; - - //Not near empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - //Read from the FIFO - read_fifo; - num_bits <= num_bits - C_DOUT_WIDTH; - - - /*********************************/ - // FIFO is reporting FULL, but it is empty - // (This is a special case, when coming out of RST - /*********************************/ - end else if ((num_write_words == 0) && (ideal_full == 1'b1)) begin - - ideal_wr_ack <= 0; - - //Read will be successful, so FIFO will leave FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //Read unsuccessful - ideal_valid <= 1'b0; - - //Report empty condition - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - //Do not read from empty FIFO - // Read from the FIFO - - - /*********************************/ - //If the FIFO is one from full - /*********************************/ - end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin - - //Write successful - ideal_wr_ack <= 1; - - //FIFO will remain ALMOST_FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b1; - - // put the data into the FIFO - write_fifo; - - //Read successful - ideal_valid <= 1'b1; - - //Not near empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - //Read from the FIFO - read_fifo; - num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; - - /*********************************/ - //If the FIFO is ALMOST EMPTY - /*********************************/ - end else if (num_read_words == 1) begin - - //Write successful - ideal_wr_ack <= 1; - - // Not near FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - // put the data into the FIFO - write_fifo; - - //Read successful - ideal_valid <= 1'b1; - - //FIFO will stay ALMOST_EMPTY - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b1; - - //Read from the FIFO - read_fifo; - num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; - - - /*********************************/ - //If the FIFO is EMPTY - /*********************************/ - end else if (num_read_words == 0) begin - - //Write successful - ideal_wr_ack <= 1; - - // Not near FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - // put the data into the FIFO - write_fifo; - - //Read will fail - ideal_valid <= 1'b0; - - //FIFO will leave EMPTY - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b1; - - // No read - num_bits <= num_bits + C_DIN_WIDTH; - - - /*********************************/ - //If the FIFO is not near EMPTY or FULL - /*********************************/ - end else begin - - //Write successful - ideal_wr_ack <= 1; - - // Not near FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - // put the data into the FIFO - write_fifo; - - //Read successful - ideal_valid <= 1'b1; - - // Not near EMPTY - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - //Read from the FIFO - read_fifo; - num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; - - end // average case - - /**********************************************************************/ - // Synchronous FIFO Condition #4 : Not reading or writing - /*** - *******************************************************************/ - end else begin - - /*********************************/ - // FIFO is FULL - /*********************************/ - if (num_write_words >= C_FIFO_WR_DEPTH) begin - - //No write - ideal_wr_ack <= 0; - ideal_full <= 1'b1; - ideal_almost_full <= 1'b1; - - //No read - ideal_valid <= 1'b0; - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - //No change to memory - - /*********************************/ - //If the FIFO is one from full - /*********************************/ - end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin - - //No write - ideal_wr_ack <= 0; - ideal_full <= 1'b0; - ideal_almost_full <= 1'b1; - - //No read - ideal_valid <= 1'b0; - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - //No change to memory - - /*********************************/ - //If the FIFO is ALMOST EMPTY - /*********************************/ - end else if (num_read_words == 1) begin - //No write - ideal_wr_ack <= 0; - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //No read - ideal_valid <= 1'b0; - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b1; - - //No change to memory - - end // almost empty - - - /*********************************/ - //If the FIFO is EMPTY - /*********************************/ - else if (num_read_words == 0) - begin - //No write - ideal_wr_ack <= 0; - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //No read - ideal_valid <= 1'b0; - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - //No change to memory - - /*********************************/ - //If the FIFO is not near EMPTY or FULL - /*********************************/ - end else begin - - //No write - ideal_wr_ack <= 0; - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //No read - ideal_valid <= 1'b0; - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - //No change to memory - - end // average case - - end // neither reading or writing - - num_read_words_q <= num_read_words; - num_write_words_q <= num_write_words; - - end //normal operating conditions - end - - end // block: gen_fifo - - //Generate overflow and underflow flags seperately - //because they don't support async rst - always @(posedge CLK) begin - ideal_overflow <= WR_EN & ideal_full; - ideal_underflow <= ideal_empty & RD_EN; - end - - always @(posedge CLK or posedge rst_i) begin : gen_fifo_p - - /****** Reset fifo - Async Reset****************************************/ - //The latency of de-assertion of the flags is reduced by 1 to be consistent with the core. - //if (rst_i || rst_q) begin //was in v3.1 - if (rst_i) begin //v3.2 - ideal_prog_full <= C_FULL_FLAGS_RST_VAL; - ideal_prog_empty <= 1'b1; - prog_full_d <= C_FULL_FLAGS_RST_VAL; - prog_empty_d <= 1'b1; - - end else begin - if (srst_i) begin - //SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. - if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin - ideal_prog_full <= 1'b0; - ideal_prog_empty <= 1'b1; - prog_full_d <= 1'b0; - prog_empty_d <= 1'b1; - end - end else begin - - /***************************************************************** - * Programmable FULL flags - ****************************************************************/ - //Single constant threshold - if (C_PROG_FULL_TYPE == 1) begin - if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1) - && WR_EN && !RD_EN) begin - prog_full_d <= 1'b1; - end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL) - && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin //v3.2 - prog_full_d <= 1'b0; - end - - //Dual constant thresholds - end else if (C_PROG_FULL_TYPE == 2) begin - if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1) - && WR_EN && !RD_EN) begin - prog_full_d <= 1'b1; - end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL) - && RD_EN && !WR_EN) begin - prog_full_d <= 1'b0; - end - - //Single input threshold - end else if (C_PROG_FULL_TYPE == 3) begin - if ((num_write_words == PROG_FULL_THRESH-1) - && WR_EN && !RD_EN) begin - prog_full_d <= 1'b1; - end else if ((num_write_words == PROG_FULL_THRESH) - && !WR_EN && RD_EN) begin - prog_full_d <= 1'b0; - end else if (num_write_words >= PROG_FULL_THRESH) begin - prog_full_d <= 1'b1; - end else if (num_write_words < PROG_FULL_THRESH) begin - prog_full_d <= 1'b0; - end - - //Dual input thresholds - end else begin - if ((num_write_words == PROG_FULL_THRESH_ASSERT-1) - && WR_EN && !RD_EN) begin - prog_full_d <= 1'b1; - end else if ((num_write_words == PROG_FULL_THRESH_NEGATE) - && !WR_EN && RD_EN)begin - prog_full_d <= 1'b0; - end else if (num_write_words >= PROG_FULL_THRESH_ASSERT) begin - prog_full_d <= 1'b1; - end else if (num_write_words < PROG_FULL_THRESH_NEGATE) begin - prog_full_d <= 1'b0; - end - end - - /***************************************************************** - * Programmable EMPTY flags - ****************************************************************/ - //Single constant threshold - if (C_PROG_EMPTY_TYPE == 1) begin - if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) - && RD_EN && !WR_EN) begin - prog_empty_d <= 1'b1; - end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL) - && WR_EN && !RD_EN) begin - prog_empty_d <= 1'b0; - end - //Dual constant thresholds - end else if (C_PROG_EMPTY_TYPE == 2) begin - if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) - && RD_EN && !WR_EN) begin - prog_empty_d <= 1'b1; - end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL) - && !RD_EN && WR_EN) begin - prog_empty_d <= 1'b0; - end - - //Single input threshold - end else if (C_PROG_EMPTY_TYPE == 3) begin - if ((num_read_words == PROG_EMPTY_THRESH+1) - && RD_EN && !WR_EN) begin - prog_empty_d <= 1'b1; - end else if ((num_read_words == PROG_EMPTY_THRESH) - && !RD_EN && WR_EN) begin - prog_empty_d <= 1'b0; - end else if (num_read_words <= PROG_EMPTY_THRESH) begin - prog_empty_d <= 1'b1; - end else if (num_read_words > PROG_EMPTY_THRESH)begin - prog_empty_d <= 1'b0; - end - - //Dual input thresholds - end else begin - if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin - prog_empty_d <= 1'b1; - end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1) - && RD_EN && !WR_EN) begin - prog_empty_d <= 1'b1; - end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE)begin - prog_empty_d <= 1'b0; - end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE) - && !RD_EN && WR_EN) begin - prog_empty_d <= 1'b0; - end - end - - ideal_prog_empty <= prog_empty_d; - if (rst_q && !rst_i) begin - ideal_prog_full <= 1'b0; - end else begin - ideal_prog_full <= prog_full_d; - end - - end //if (srst_i) begin - end //if (rst_i) begin - end //always @(posedge CLK or posedge rst_i) begin : gen_fifo_p -endmodule // fifo_generator_v4_3_bhv_ver_ss - - -module fifo_generator_v4_3_bhv_ver_preload0 - ( - RD_CLK, - RD_RST, - RD_EN, - FIFOEMPTY, - FIFODATA, - USERDATA, - USERVALID, - USERUNDERFLOW, - USEREMPTY, - USERALMOSTEMPTY, - RAMVALID, - FIFORDEN - ); - - - parameter C_DOUT_RST_VAL = ""; - parameter C_DOUT_WIDTH = 8; - parameter C_HAS_RST = 0; - parameter C_USERVALID_LOW = 0; - parameter C_USERUNDERFLOW_LOW = 0; - - - input RD_CLK; - input RD_RST; - input RD_EN; - input FIFOEMPTY; - input [C_DOUT_WIDTH-1:0] FIFODATA; - output [C_DOUT_WIDTH-1:0] USERDATA; - output USERVALID; - output USERUNDERFLOW; - output USEREMPTY; - output USERALMOSTEMPTY; - output RAMVALID; - output FIFORDEN; - - wire RD_CLK; - wire RD_RST; - wire RD_EN; - wire FIFOEMPTY; - wire [C_DOUT_WIDTH-1:0] FIFODATA; - reg [C_DOUT_WIDTH-1:0] USERDATA; - wire USERVALID; - wire USERUNDERFLOW; - wire USEREMPTY; - wire USERALMOSTEMPTY; - wire RAMVALID; - wire FIFORDEN; - - wire preloadstage1; - wire preloadstage2; - reg ram_valid_i; - reg read_data_valid_i; - wire ram_regout_en; - wire ram_rd_en; - reg empty_i = 1'b1; - reg empty_q = 1'b1; - reg rd_en_q = 1'b0; //Fix for CR:236270 in v3.2 //prasanna - reg almost_empty_i = 1'b1; - reg almost_empty_q = 1'b1; - wire rd_rst_i; - - -/************************************************************************* -* FUNCTIONS -*************************************************************************/ - - /************************************************************************* - * hexstr_conv - * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) - ***********************************************************************/ - function [C_DOUT_WIDTH-1:0] hexstr_conv; - input [(C_DOUT_WIDTH*8)-1:0] def_data; - - integer index,i,j; - reg [3:0] bin; - - begin - index = 0; - hexstr_conv = 'b0; - for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) - begin - case (def_data[7:0]) - 8'b00000000 : - begin - bin = 4'b0000; - i = -1; - end - 8'b00110000 : bin = 4'b0000; - 8'b00110001 : bin = 4'b0001; - 8'b00110010 : bin = 4'b0010; - 8'b00110011 : bin = 4'b0011; - 8'b00110100 : bin = 4'b0100; - 8'b00110101 : bin = 4'b0101; - 8'b00110110 : bin = 4'b0110; - 8'b00110111 : bin = 4'b0111; - 8'b00111000 : bin = 4'b1000; - 8'b00111001 : bin = 4'b1001; - 8'b01000001 : bin = 4'b1010; - 8'b01000010 : bin = 4'b1011; - 8'b01000011 : bin = 4'b1100; - 8'b01000100 : bin = 4'b1101; - 8'b01000101 : bin = 4'b1110; - 8'b01000110 : bin = 4'b1111; - 8'b01100001 : bin = 4'b1010; - 8'b01100010 : bin = 4'b1011; - 8'b01100011 : bin = 4'b1100; - 8'b01100100 : bin = 4'b1101; - 8'b01100101 : bin = 4'b1110; - 8'b01100110 : bin = 4'b1111; - default : - begin - bin = 4'bx; - end - endcase - for( j=0; j<4; j=j+1) - begin - if ((index*4)+j < C_DOUT_WIDTH) - begin - hexstr_conv[(index*4)+j] = bin[j]; - end - end - index = index + 1; - def_data = def_data >> 8; - end - end - endfunction - -initial - begin - ram_valid_i = 1'b0; - read_data_valid_i = 1'b0; - USERDATA = hexstr_conv(C_DOUT_RST_VAL); - end - - - //****************************************************************************** - // connect up optional reset - //****************************************************************************** - assign rd_rst_i = C_HAS_RST ? RD_RST : 0; - - - //****************************************************************************** - // preloadstage2 indicates that stage2 needs to be updated. This is true - // whenever read_data_valid is false, and RAM_valid is true. - //****************************************************************************** - assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN); - - //****************************************************************************** - // preloadstage1 indicates that stage1 needs to be updated. This is true - // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is - // false (indicating that Stage1 needs updating), or preloadstage2 is active - // (indicating that Stage2 is going to update, so Stage1, therefore, must - // also be updated to keep it valid. - //****************************************************************************** - assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); - - //****************************************************************************** - // Calculate RAM_REGOUT_EN - // The output registers are controlled by the ram_regout_en signal. - // These registers should be updated either when the output in Stage2 is - // invalid (preloadstage2), OR when the user is reading, in which case the - // Stage2 value will go invalid unless it is replenished. - //****************************************************************************** - assign ram_regout_en = preloadstage2; - - //****************************************************************************** - // Calculate RAM_RD_EN - // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to - // update the value in Stage1. - // One case when this happens is when preloadstage1=true, which indicates - // that the data in Stage1 or Stage2 is invalid, and needs to automatically - // be updated. - // The other case is when the user is reading from the FIFO, which guarantees - // that Stage1 or Stage2 will be invalid on the next clock cycle, unless it is - // replinished by data from the memory. So, as long as the RAM has data in it, - // a read of the RAM should occur. - //****************************************************************************** - assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; - - //****************************************************************************** - // Calculate RAMVALID_P0_OUT - // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. - // - // If the RAM is being read from on this clock cycle (ram_rd_en=1), then - // RAMVALID_P0_OUT is certainly going to be true. - // If the RAM is not being read from, but the output registers are being - // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, - // therefore causing RAMVALID_P0_OUT to be false. - // Otherwise, RAMVALID_P0_OUT will remain unchanged. - //****************************************************************************** - always @ (posedge RD_CLK or posedge rd_rst_i) - begin // PROCESS regout_valid - if (rd_rst_i) // asynchronous reset (active high) - ram_valid_i <= 1'b0; - else - begin - if (ram_rd_en == 1'b1) - ram_valid_i <= 1'b1; - else - if (ram_regout_en == 1'b1) - ram_valid_i <= 1'b0; - else - ram_valid_i <= ram_valid_i; - end //rd_rst_i - end //always - - //****************************************************************************** - // Calculate READ_DATA_VALID - // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. - // Stage2 has valid data whenever Stage1 had valid data and ram_regout_en_i=1, - // such that the data in Stage1 is propogated into Stage2. - //****************************************************************************** - always @ (posedge RD_CLK or posedge rd_rst_i) - begin - if (rd_rst_i) - read_data_valid_i <= 1'b0; - else - read_data_valid_i <= ram_valid_i | (read_data_valid_i & ~RD_EN); - end //always - - - //***************************************************************************** - // Calculate EMPTY - // Defined as the inverse of READ_DATA_VALID - // - // Description: - // - // If read_data_valid_i indicates that the output is not valid, - // and there is no valid data on the output of the ram to preload it - // with, then we will report empty. - // - // If there is no valid data on the output of the ram and we are - // reading, then the FIFO will go empty. - // - //***************************************************************************** - always @ (posedge RD_CLK or posedge rd_rst_i) - begin - if (rd_rst_i) // asynchronous reset (active high) - begin - empty_i <= 1'b1; - empty_q <= 1'b1; - end - else // rising clock edge - begin - empty_i <= (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); - empty_q <= empty_i; - end - end //always - - //Fix for CR:236270 //prasanna - //Register RD_EN from user to calculate USERUNDERFLOW. - always @ (posedge RD_CLK or posedge rd_rst_i) - begin - if (rd_rst_i) // asynchronous reset (active high) - begin - rd_en_q <= 1'b0; - end - else // rising clock edge - begin - rd_en_q <= RD_EN; - end - end //always - - - //***************************************************************************** - // Calculate user_almost_empty - // user_almost_empty is defined such that, unless more words are written - // to the FIFO, the next read will cause the FIFO to go EMPTY. - // - // In most cases, whenever the output registers are updated (due to a user - // read or a preload condition), then user_almost_empty will update to - // whatever RAM_EMPTY is. - // - // The exception is when the output is valid, the user is not reading, and - // Stage1 is not empty. In this condition, Stage1 will be preloaded from the - // memory, so we need to make sure user_almost_empty deasserts properly under - // this condition. - //***************************************************************************** - always @ (posedge RD_CLK or posedge rd_rst_i) - begin - if (rd_rst_i) // asynchronous reset (active high) - begin - almost_empty_i <= 1'b1; - almost_empty_q <= 1'b1; - end - else // rising clock edge - begin - if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) - begin - almost_empty_i <= FIFOEMPTY; - end - almost_empty_q <= empty_i; - end - end //always - - - assign USEREMPTY = empty_i; - assign USERALMOSTEMPTY = almost_empty_i; - assign FIFORDEN = ram_rd_en; - assign RAMVALID = ram_valid_i; - assign USERVALID = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i; - //assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & RD_EN) : empty_q & RD_EN; //Bug in v3.1 (CR:236270) - assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; //Fix for CR:236270 in v3.2 //prasanna - - always @ (posedge RD_CLK or posedge rd_rst_i) - begin - if (rd_rst_i) // asynchronous reset (active high) - USERDATA <= hexstr_conv(C_DOUT_RST_VAL); - else // rising clock edge - if (ram_regout_en) - USERDATA <= FIFODATA; - end //always - - - - - -endmodule diff --git a/fpga/usrp2/models/FIFO_GENERATOR_V6_1.v b/fpga/usrp2/models/FIFO_GENERATOR_V6_1.v deleted file mode 100644 index 65bbac447..000000000 --- a/fpga/usrp2/models/FIFO_GENERATOR_V6_1.v +++ /dev/null @@ -1,4575 +0,0 @@ -/* - ******************************************************************************* - * - * FIFO Generator - Verilog Behavioral Model - * - ******************************************************************************* - * - * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. - * - * This file contains confidential and proprietary information - * of Xilinx, Inc. and is protected under U.S. and - * international copyright and other intellectual property - * laws. - * - * DISCLAIMER - * This disclaimer is not a license and does not grant any - * rights to the materials distributed herewith. Except as - * otherwise provided in a valid license issued to you by - * Xilinx, and to the maximum extent permitted by applicable - * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND - * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES - * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING - * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- - * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and - * (2) Xilinx shall not be liable (whether in contract or tort, - * including negligence, or under any other theory of - * liability) for any loss or damage of any kind or nature - * related to, arising under or in connection with these - * materials, including for any direct, or any indirect, - * special, incidental, or consequential loss or damage - * (including loss of data, profits, goodwill, or any type of - * loss or damage suffered as a result of any action brought - * by a third party) even if such damage or loss was - * reasonably foreseeable or Xilinx had been advised of the - * possibility of the same. - * - * CRITICAL APPLICATIONS - * Xilinx products are not designed or intended to be fail- - * safe, or for use in any application requiring fail-safe - * performance, such as life-support or safety devices or - * systems, Class III medical devices, nuclear facilities, - * applications related to the deployment of airbags, or any - * other applications that could lead to death, personal - * injury, or severe property or environmental damage - * (individually and collectively, "Critical - * Applications"). Customer assumes the sole risk and - * liability of any use of Xilinx products in Critical - * Applications, subject only to applicable laws and - * regulations governing limitations on product liability. - * - * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS - * PART OF THIS FILE AT ALL TIMES. - * - ******************************************************************************* - ******************************************************************************* - * - * Filename: FIFO_GENERATOR_V6_1.v - * - * Author : Xilinx - * - ******************************************************************************* - * Structure: - * - * fifo_generator_v6_1.vhd - * | - * +-fifo_generator_v6_1_bhv_ver_as - * | - * +-fifo_generator_v6_1_bhv_ver_ss - * | - * +-fifo_generator_v6_1_bhv_ver_preload0 - * - ******************************************************************************* - * Description: - * - * The Verilog behavioral model for the FIFO Generator. - * - * The behavioral model has three parts: - * - The behavioral model for independent clocks FIFOs (_as) - * - The behavioral model for common clock FIFOs (_ss) - * - The "preload logic" block which implements First-word Fall-through - * - ******************************************************************************* - * Description: - * The verilog behavioral model for the FIFO generator core. - * - ******************************************************************************* - */ - -`timescale 1ps/1ps -`ifndef TCQ - `define TCQ 100 -`endif - - -/******************************************************************************* - * Declaration of top-level module - ******************************************************************************/ -module FIFO_GENERATOR_V6_1 - #( - parameter C_COMMON_CLOCK = 0, - parameter C_COUNT_TYPE = 0, - parameter C_DATA_COUNT_WIDTH = 2, - parameter C_DEFAULT_VALUE = "", - parameter C_DIN_WIDTH = 8, - parameter C_DOUT_RST_VAL = "", - parameter C_DOUT_WIDTH = 8, - parameter C_ENABLE_RLOCS = 0, - parameter C_FAMILY = "virtex6", //Not allowed in Verilog model - parameter C_FULL_FLAGS_RST_VAL = 1, - parameter C_HAS_ALMOST_EMPTY = 0, - parameter C_HAS_ALMOST_FULL = 0, - parameter C_HAS_BACKUP = 0, - parameter C_HAS_DATA_COUNT = 0, - parameter C_HAS_INT_CLK = 0, - parameter C_HAS_MEMINIT_FILE = 0, - parameter C_HAS_OVERFLOW = 0, - parameter C_HAS_RD_DATA_COUNT = 0, - parameter C_HAS_RD_RST = 0, - parameter C_HAS_RST = 0, - parameter C_HAS_SRST = 0, - parameter C_HAS_UNDERFLOW = 0, - parameter C_HAS_VALID = 0, - parameter C_HAS_WR_ACK = 0, - parameter C_HAS_WR_DATA_COUNT = 0, - parameter C_HAS_WR_RST = 0, - parameter C_IMPLEMENTATION_TYPE = 0, - parameter C_INIT_WR_PNTR_VAL = 0, - parameter C_MEMORY_TYPE = 1, - parameter C_MIF_FILE_NAME = "", - parameter C_OPTIMIZATION_MODE = 0, - parameter C_OVERFLOW_LOW = 0, - parameter C_PRELOAD_LATENCY = 1, - parameter C_PRELOAD_REGS = 0, - parameter C_PRIM_FIFO_TYPE = "", - parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, - parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, - parameter C_PROG_EMPTY_TYPE = 0, - parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, - parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, - parameter C_PROG_FULL_TYPE = 0, - parameter C_RD_DATA_COUNT_WIDTH = 2, - parameter C_RD_DEPTH = 256, - parameter C_RD_FREQ = 1, - parameter C_RD_PNTR_WIDTH = 8, - parameter C_UNDERFLOW_LOW = 0, - parameter C_USE_DOUT_RST = 0, - parameter C_USE_ECC = 0, - parameter C_USE_EMBEDDED_REG = 0, - parameter C_USE_FIFO16_FLAGS = 0, - parameter C_USE_FWFT_DATA_COUNT = 0, - parameter C_VALID_LOW = 0, - parameter C_WR_ACK_LOW = 0, - parameter C_WR_DATA_COUNT_WIDTH = 2, - parameter C_WR_DEPTH = 256, - parameter C_WR_FREQ = 1, - parameter C_WR_PNTR_WIDTH = 8, - parameter C_WR_RESPONSE_LATENCY = 1, - parameter C_MSGON_VAL = 1, - parameter C_ENABLE_RST_SYNC = 1, - parameter C_ERROR_INJECTION_TYPE = 0 - ) - - ( - input BACKUP, - input BACKUP_MARKER, - input CLK, - input RST, - input SRST, - input WR_CLK, - input WR_RST, - input RD_CLK, - input RD_RST, - input [C_DIN_WIDTH-1:0] DIN, - input WR_EN, - input RD_EN, - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, - input INT_CLK, - input INJECTDBITERR, - input INJECTSBITERR, - - output [C_DOUT_WIDTH-1:0] DOUT, - output FULL, - output ALMOST_FULL, - output WR_ACK, - output OVERFLOW, - output EMPTY, - output ALMOST_EMPTY, - output VALID, - output UNDERFLOW, - output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT, - output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, - output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, - output PROG_FULL, - output PROG_EMPTY, - output SBITERR, - output DBITERR - ); - -/* - ****************************************************************************** - * Definition of Parameters - ****************************************************************************** - * C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) - * C_COUNT_TYPE : *not used - * C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus - * C_DEFAULT_VALUE : *not used - * C_DIN_WIDTH : Width of DIN bus - * C_DOUT_RST_VAL : Reset value of DOUT - * C_DOUT_WIDTH : Width of DOUT bus - * C_ENABLE_RLOCS : *not used - * C_FAMILY : not used in bhv model - * C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) - * C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag - * C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag - * C_HAS_BACKUP : *not used - * C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus - * C_HAS_INT_CLK : not used in bhv model - * C_HAS_MEMINIT_FILE : *not used - * C_HAS_OVERFLOW : 1=Core has OVERFLOW flag - * C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus - * C_HAS_RD_RST : *not used - * C_HAS_RST : 1=Core has Async Rst - * C_HAS_SRST : 1=Core has Sync Rst - * C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag - * C_HAS_VALID : 1=Core has VALID flag - * C_HAS_WR_ACK : 1=Core has WR_ACK flag - * C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus - * C_HAS_WR_RST : *not used - * C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram - * 1=Common-Clock ShiftRam - * 2=Indep. Clocks Bram/Dram - * 3=Virtex-4 Built-in - * 4=Virtex-5 Built-in - * C_INIT_WR_PNTR_VAL : *not used - * C_MEMORY_TYPE : 1=Block RAM - * 2=Distributed RAM - * 3=Shift RAM - * 4=Built-in FIFO - * C_MIF_FILE_NAME : *not used - * C_OPTIMIZATION_MODE : *not used - * C_OVERFLOW_LOW : 1=OVERFLOW active low - * C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 - * C_PRELOAD_REGS : 1=Use output registers - * C_PRIM_FIFO_TYPE : not used in bhv model - * C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold - * C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold - * C_PROG_EMPTY_TYPE : 0=No programmable empty - * 1=Single prog empty thresh constant - * 2=Multiple prog empty thresh constants - * 3=Single prog empty thresh input - * 4=Multiple prog empty thresh inputs - * C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold - * C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold - * C_PROG_FULL_TYPE : 0=No prog full - * 1=Single prog full thresh constant - * 2=Multiple prog full thresh constants - * 3=Single prog full thresh input - * 4=Multiple prog full thresh inputs - * C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus - * C_RD_DEPTH : Depth of read interface (2^N) - * C_RD_FREQ : not used in bhv model - * C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) - * C_UNDERFLOW_LOW : 1=UNDERFLOW active low - * C_USE_DOUT_RST : 1=Resets DOUT on RST - * C_USE_ECC : Used for error injection purpose - * C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register - * C_USE_FIFO16_FLAGS : not used in bhv model - * C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count - * C_VALID_LOW : 1=VALID active low - * C_WR_ACK_LOW : 1=WR_ACK active low - * C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus - * C_WR_DEPTH : Depth of write interface (2^N) - * C_WR_FREQ : not used in bhv model - * C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) - * C_WR_RESPONSE_LATENCY : *not used - * C_MSGON_VAL : *not used by bhv model - * C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST - * 1 = Use RST - * C_ERROR_INJECTION_TYPE : 0 = No error injection - * 1 = Single bit error injection only - * 2 = Double bit error injection only - * 3 = Single and double bit error injection - ****************************************************************************** - * Definition of Ports - ****************************************************************************** - * BACKUP : Not used - * BACKUP_MARKER: Not used - * CLK : Clock - * DIN : Input data bus - * PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag - * PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag - * PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag - * PROG_FULL_THRESH : Threshold for Programmable Full Flag - * PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag - * PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag - * RD_CLK : Read Domain Clock - * RD_EN : Read enable - * RD_RST : Read Reset - * RST : Asynchronous Reset - * SRST : Synchronous Reset - * WR_CLK : Write Domain Clock - * WR_EN : Write enable - * WR_RST : Write Reset - * INT_CLK : Internal Clock - * INJECTSBITERR: Inject Signle bit error - * INJECTDBITERR: Inject Double bit error - * ALMOST_EMPTY : One word remaining in FIFO - * ALMOST_FULL : One empty space remaining in FIFO - * DATA_COUNT : Number of data words in fifo( synchronous to CLK) - * DOUT : Output data bus - * EMPTY : Empty flag - * FULL : Full flag - * OVERFLOW : Last write rejected - * PROG_EMPTY : Programmable Empty Flag - * PROG_FULL : Programmable Full Flag - * RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) - * UNDERFLOW : Last read rejected - * VALID : Last read acknowledged, DOUT bus VALID - * WR_ACK : Last write acknowledged - * WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) - * SBITERR : Single Bit ECC Error Detected - * DBITERR : Double Bit ECC Error Detected - ****************************************************************************** - */ - - - /***************************************************************************** - * Derived parameters - ****************************************************************************/ - //There are 2 Verilog behavioral models - // 0 = Common-Clock FIFO/ShiftRam FIFO - // 1 = Independent Clocks FIFO - parameter C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0; - - //Internal reset signals - reg rd_rst_asreg = 0; - reg rd_rst_asreg_d1 = 0; - reg rd_rst_asreg_d2 = 0; - reg rd_rst_reg = 0; - wire rd_rst_comb; - reg rd_rst_d1 = 0; - reg wr_rst_asreg = 0; - reg wr_rst_asreg_d1 = 0; - reg wr_rst_asreg_d2 = 0; - reg wr_rst_reg = 0; - wire wr_rst_comb; - wire wr_rst_i; - wire rd_rst_i; - wire rst_i; - - //Internal reset signals - reg rst_asreg = 0; - reg rst_asreg_d1 = 0; - reg rst_asreg_d2 = 0; - reg rst_reg = 0; - wire rst_comb; - wire rst_full_gen_i; - wire rst_full_ff_i; - - wire RD_CLK_P0_IN; - wire RST_P0_IN; - wire RD_EN_FIFO_IN; - wire RD_EN_P0_IN; - - wire ALMOST_EMPTY_FIFO_OUT; - wire ALMOST_FULL_FIFO_OUT; - wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; - wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; - wire EMPTY_FIFO_OUT; - wire FULL_FIFO_OUT; - wire OVERFLOW_FIFO_OUT; - wire PROG_EMPTY_FIFO_OUT; - wire PROG_FULL_FIFO_OUT; - wire VALID_FIFO_OUT; - wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; - wire UNDERFLOW_FIFO_OUT; - wire WR_ACK_FIFO_OUT; - wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; - - - //*************************************************************************** - // Internal Signals - // The core uses either the internal_ wires or the preload0_ wires depending - // on whether the core uses Preload0 or not. - // When using preload0, the internal signals connect the internal core to - // the preload logic, and the external core's interfaces are tied to the - // preload0 signals from the preload logic. - //*************************************************************************** - wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; - wire VALID_P0_OUT; - wire EMPTY_P0_OUT; - wire ALMOSTEMPTY_P0_OUT; - reg EMPTY_P0_OUT_Q; - reg ALMOSTEMPTY_P0_OUT_Q; - wire UNDERFLOW_P0_OUT; - wire RDEN_P0_OUT; - wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; - wire EMPTY_P0_IN; - reg [31:0] DATA_COUNT_FWFT; - reg SS_FWFT_WR ; - reg SS_FWFT_RD ; - - wire sbiterr_fifo_out; - wire dbiterr_fifo_out; - - // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR. - assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ? - INJECTSBITERR : 0; - assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ? - INJECTDBITERR : 0; - - -// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL -// parameter (1=Independent Clocks, 0=Common Clock) - - localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL; -generate -case (C_VERILOG_IMPL) -0 : begin : block1 - //Common Clock Behavioral Model - fifo_generator_v6_1_bhv_ver_ss - #( - C_DATA_COUNT_WIDTH, - C_DIN_WIDTH, - C_DOUT_RST_VAL, - C_DOUT_WIDTH, -// C_FULL_FLAGS_RST_VAL, - FULL_FLAGS_RST_VAL, - C_HAS_ALMOST_EMPTY, - C_HAS_ALMOST_FULL, - C_HAS_DATA_COUNT, - C_HAS_OVERFLOW, - C_HAS_RD_DATA_COUNT, - C_HAS_RST, - C_HAS_SRST, - C_HAS_UNDERFLOW, - C_HAS_VALID, - C_HAS_WR_ACK, - C_HAS_WR_DATA_COUNT, - C_IMPLEMENTATION_TYPE, - C_MEMORY_TYPE, - C_OVERFLOW_LOW, - C_PRELOAD_LATENCY, - C_PRELOAD_REGS, - C_PROG_EMPTY_THRESH_ASSERT_VAL, - C_PROG_EMPTY_THRESH_NEGATE_VAL, - C_PROG_EMPTY_TYPE, - C_PROG_FULL_THRESH_ASSERT_VAL, - C_PROG_FULL_THRESH_NEGATE_VAL, - C_PROG_FULL_TYPE, - C_RD_DATA_COUNT_WIDTH, - C_RD_DEPTH, - C_RD_PNTR_WIDTH, - C_UNDERFLOW_LOW, - C_USE_DOUT_RST, - C_USE_EMBEDDED_REG, - C_USE_FWFT_DATA_COUNT, - C_VALID_LOW, - C_WR_ACK_LOW, - C_WR_DATA_COUNT_WIDTH, - C_WR_DEPTH, - C_WR_PNTR_WIDTH, - C_USE_ECC, - C_ENABLE_RST_SYNC, - C_ERROR_INJECTION_TYPE - ) - gen_ss - ( - .CLK (CLK), - .RST (rst_i), - .SRST (SRST), - .RST_FULL_GEN (rst_full_gen_i), - .RST_FULL_FF (rst_full_ff_i), - .DIN (DIN), - .WR_EN (WR_EN), - .RD_EN (RD_EN_FIFO_IN), - .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), - .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), - .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), - .PROG_FULL_THRESH (PROG_FULL_THRESH), - .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), - .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), - .INJECTSBITERR (inject_sbit_err), - .INJECTDBITERR (inject_dbit_err), - .DOUT (DOUT_FIFO_OUT), - .FULL (FULL_FIFO_OUT), - .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), - .WR_ACK (WR_ACK_FIFO_OUT), - .OVERFLOW (OVERFLOW_FIFO_OUT), - .EMPTY (EMPTY_FIFO_OUT), - .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), - .VALID (VALID_FIFO_OUT), - .UNDERFLOW (UNDERFLOW_FIFO_OUT), - .DATA_COUNT (DATA_COUNT_FIFO_OUT), - .PROG_FULL (PROG_FULL_FIFO_OUT), - .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), - .SBITERR (sbiterr_fifo_out), - .DBITERR (dbiterr_fifo_out) - ); -end -1 : begin : block1 - //Independent Clocks Behavioral Model - fifo_generator_v6_1_bhv_ver_as - #( - C_DATA_COUNT_WIDTH, - C_DIN_WIDTH, - C_DOUT_RST_VAL, - C_DOUT_WIDTH, - C_FULL_FLAGS_RST_VAL, - C_HAS_ALMOST_EMPTY, - C_HAS_ALMOST_FULL, - C_HAS_DATA_COUNT, - C_HAS_OVERFLOW, - C_HAS_RD_DATA_COUNT, - C_HAS_RST, - C_HAS_UNDERFLOW, - C_HAS_VALID, - C_HAS_WR_ACK, - C_HAS_WR_DATA_COUNT, - C_IMPLEMENTATION_TYPE, - C_MEMORY_TYPE, - C_OVERFLOW_LOW, - C_PRELOAD_LATENCY, - C_PRELOAD_REGS, - C_PROG_EMPTY_THRESH_ASSERT_VAL, - C_PROG_EMPTY_THRESH_NEGATE_VAL, - C_PROG_EMPTY_TYPE, - C_PROG_FULL_THRESH_ASSERT_VAL, - C_PROG_FULL_THRESH_NEGATE_VAL, - C_PROG_FULL_TYPE, - C_RD_DATA_COUNT_WIDTH, - C_RD_DEPTH, - C_RD_PNTR_WIDTH, - C_UNDERFLOW_LOW, - C_USE_DOUT_RST, - C_USE_EMBEDDED_REG, - C_USE_FWFT_DATA_COUNT, - C_VALID_LOW, - C_WR_ACK_LOW, - C_WR_DATA_COUNT_WIDTH, - C_WR_DEPTH, - C_WR_PNTR_WIDTH, - C_USE_ECC, - C_ENABLE_RST_SYNC, - C_ERROR_INJECTION_TYPE - ) - gen_as - ( - .WR_CLK (WR_CLK), - .RD_CLK (RD_CLK), - .RST (rst_i), - .RST_FULL_GEN (rst_full_gen_i), - .RST_FULL_FF (rst_full_ff_i), - .WR_RST (wr_rst_i), - .RD_RST (rd_rst_i), - .DIN (DIN), - .WR_EN (WR_EN), - .RD_EN (RD_EN_FIFO_IN), - .RD_EN_USER (RD_EN), - .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), - .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), - .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), - .PROG_FULL_THRESH (PROG_FULL_THRESH), - .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), - .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), - .INJECTSBITERR (inject_sbit_err), - .INJECTDBITERR (inject_dbit_err), - .USER_EMPTY_FB (EMPTY_P0_OUT), - .DOUT (DOUT_FIFO_OUT), - .FULL (FULL_FIFO_OUT), - .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), - .WR_ACK (WR_ACK_FIFO_OUT), - .OVERFLOW (OVERFLOW_FIFO_OUT), - .EMPTY (EMPTY_FIFO_OUT), - .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), - .VALID (VALID_FIFO_OUT), - .UNDERFLOW (UNDERFLOW_FIFO_OUT), - .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), - .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), - .PROG_FULL (PROG_FULL_FIFO_OUT), - .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), - .SBITERR (sbiterr_fifo_out), - .DBITERR (dbiterr_fifo_out) - ); -end - -default : begin : block1 - //Independent Clocks Behavioral Model - fifo_generator_v6_1_bhv_ver_as - #( - C_DATA_COUNT_WIDTH, - C_DIN_WIDTH, - C_DOUT_RST_VAL, - C_DOUT_WIDTH, - C_FULL_FLAGS_RST_VAL, - C_HAS_ALMOST_EMPTY, - C_HAS_ALMOST_FULL, - C_HAS_DATA_COUNT, - C_HAS_OVERFLOW, - C_HAS_RD_DATA_COUNT, - C_HAS_RST, - C_HAS_UNDERFLOW, - C_HAS_VALID, - C_HAS_WR_ACK, - C_HAS_WR_DATA_COUNT, - C_IMPLEMENTATION_TYPE, - C_MEMORY_TYPE, - C_OVERFLOW_LOW, - C_PRELOAD_LATENCY, - C_PRELOAD_REGS, - C_PROG_EMPTY_THRESH_ASSERT_VAL, - C_PROG_EMPTY_THRESH_NEGATE_VAL, - C_PROG_EMPTY_TYPE, - C_PROG_FULL_THRESH_ASSERT_VAL, - C_PROG_FULL_THRESH_NEGATE_VAL, - C_PROG_FULL_TYPE, - C_RD_DATA_COUNT_WIDTH, - C_RD_DEPTH, - C_RD_PNTR_WIDTH, - C_UNDERFLOW_LOW, - C_USE_DOUT_RST, - C_USE_EMBEDDED_REG, - C_USE_FWFT_DATA_COUNT, - C_VALID_LOW, - C_WR_ACK_LOW, - C_WR_DATA_COUNT_WIDTH, - C_WR_DEPTH, - C_WR_PNTR_WIDTH, - C_USE_ECC, - C_ENABLE_RST_SYNC, - C_ERROR_INJECTION_TYPE - ) - gen_as - ( - .WR_CLK (WR_CLK), - .RD_CLK (RD_CLK), - .RST (rst_i), - .RST_FULL_GEN (rst_full_gen_i), - .RST_FULL_FF (rst_full_ff_i), - .WR_RST (wr_rst_i), - .RD_RST (rd_rst_i), - .DIN (DIN), - .WR_EN (WR_EN), - .RD_EN (RD_EN_FIFO_IN), - .RD_EN_USER (RD_EN), - .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), - .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), - .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), - .PROG_FULL_THRESH (PROG_FULL_THRESH), - .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), - .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), - .INJECTSBITERR (inject_sbit_err), - .INJECTDBITERR (inject_dbit_err), - .USER_EMPTY_FB (EMPTY_P0_OUT), - .DOUT (DOUT_FIFO_OUT), - .FULL (FULL_FIFO_OUT), - .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), - .WR_ACK (WR_ACK_FIFO_OUT), - .OVERFLOW (OVERFLOW_FIFO_OUT), - .EMPTY (EMPTY_FIFO_OUT), - .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), - .VALID (VALID_FIFO_OUT), - .UNDERFLOW (UNDERFLOW_FIFO_OUT), - .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), - .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), - .PROG_FULL (PROG_FULL_FIFO_OUT), - .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), - .SBITERR (sbiterr_fifo_out), - .DBITERR (dbiterr_fifo_out) - ); -end - -endcase -endgenerate - - - //************************************************************************** - // Connect Internal Signals - // (Signals labeled internal_*) - // In the normal case, these signals tie directly to the FIFO's inputs and - // outputs. - // In the case of Preload Latency 0 or 1, there are intermediate - // signals between the internal FIFO and the preload logic. - //************************************************************************** - - - //*********************************************** - // If First-Word Fall-Through, instantiate - // the preload0 (FWFT) module - //*********************************************** - generate - if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin : block2 - - - fifo_generator_v6_1_bhv_ver_preload0 - #( - C_DOUT_RST_VAL, - C_DOUT_WIDTH, - C_HAS_RST, - C_ENABLE_RST_SYNC, - C_HAS_SRST, - C_USE_DOUT_RST, - C_USE_ECC, - C_VALID_LOW, - C_UNDERFLOW_LOW, - C_MEMORY_TYPE - ) - fgpl0 - ( - .RD_CLK (RD_CLK_P0_IN), - .RD_RST (RST_P0_IN), - .SRST (SRST), - .RD_EN (RD_EN_P0_IN), - .FIFOEMPTY (EMPTY_P0_IN), - .FIFODATA (DATA_P0_IN), - .FIFOSBITERR (sbiterr_fifo_out), - .FIFODBITERR (dbiterr_fifo_out), - .USERDATA (DATA_P0_OUT), - .USERVALID (VALID_P0_OUT), - .USEREMPTY (EMPTY_P0_OUT), - .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), - .USERUNDERFLOW (UNDERFLOW_P0_OUT), - .RAMVALID (RAMVALID_P0_OUT), - .FIFORDEN (RDEN_P0_OUT), - .USERSBITERR (SBITERR), - .USERDBITERR (DBITERR) - ); - - - //*********************************************** - // Connect inputs to preload (FWFT) module - //*********************************************** - //Connect the RD_CLK of the Preload (FWFT) module to CLK if we - // have a common-clock FIFO, or RD_CLK if we have an - // independent clock FIFO - assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); - assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0; - assign RD_EN_P0_IN = RD_EN; - assign EMPTY_P0_IN = EMPTY_FIFO_OUT; - assign DATA_P0_IN = DOUT_FIFO_OUT; - - //*********************************************** - // Connect outputs from preload (FWFT) module - //*********************************************** - assign DOUT = DATA_P0_OUT; - assign VALID = VALID_P0_OUT ; - assign EMPTY = EMPTY_P0_OUT; - assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; - assign UNDERFLOW = UNDERFLOW_P0_OUT ; - - assign RD_EN_FIFO_IN = RDEN_P0_OUT; - - - //*********************************************** - // Create DATA_COUNT from First-Word Fall-Through - // data count - //*********************************************** - assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT: - (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : - DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1]; - - //*********************************************** - // Create DATA_COUNT from First-Word Fall-Through - // data count - //*********************************************** - always @ (posedge RD_CLK or posedge RST_P0_IN) begin - if (RST_P0_IN) begin - EMPTY_P0_OUT_Q <= #`TCQ 1; - ALMOSTEMPTY_P0_OUT_Q <= #`TCQ 1; - end else begin - EMPTY_P0_OUT_Q <= #`TCQ EMPTY_P0_OUT; - ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT; - end - end //always - - - //*********************************************** - // logic for common-clock data count when FWFT is selected - //*********************************************** - initial begin - SS_FWFT_RD = 1'b0; - DATA_COUNT_FWFT = 0 ; - SS_FWFT_WR = 1'b0 ; - end //initial - - - //*********************************************** - // common-clock data count is implemented as an - // up-down counter. SS_FWFT_WR and SS_FWFT_RD - // are the up/down enables for the counter. - //*********************************************** - always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT) begin - if (C_VALID_LOW == 1) begin - SS_FWFT_RD = RD_EN && ~VALID_P0_OUT ; - end else begin - SS_FWFT_RD = RD_EN && VALID_P0_OUT ; - end - SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ; - end - - //*********************************************** - // common-clock data count is implemented as an - // up-down counter for FWFT. This always block - // calculates the counter. - //*********************************************** - always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin - if (RST_P0_IN) begin - DATA_COUNT_FWFT <= #`TCQ 0; - end else begin - if (SRST && (C_HAS_SRST == 1) ) begin - DATA_COUNT_FWFT <= #`TCQ 0; - end else begin - case ( {SS_FWFT_WR, SS_FWFT_RD}) - 2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; - 2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ; - 2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ; - 2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; - endcase - end //if SRST - end //IF RST - end //always - - - end else begin : block2 //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) - - //*********************************************** - // If NOT First-Word Fall-Through, wire the outputs - // of the internal _ss or _as FIFO directly to the - // output, and do not instantiate the preload0 - // module. - //*********************************************** - - assign RD_CLK_P0_IN = 0; - assign RST_P0_IN = 0; - assign RD_EN_P0_IN = 0; - - assign RD_EN_FIFO_IN = RD_EN; - - assign DOUT = DOUT_FIFO_OUT; - assign DATA_P0_IN = 0; - assign VALID = VALID_FIFO_OUT; - assign EMPTY = EMPTY_FIFO_OUT; - assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; - assign EMPTY_P0_IN = 0; - assign UNDERFLOW = UNDERFLOW_FIFO_OUT; - assign DATA_COUNT = DATA_COUNT_FIFO_OUT; - assign SBITERR = sbiterr_fifo_out; - assign DBITERR = dbiterr_fifo_out; - - end //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) - endgenerate - - - //*********************************************** - // Connect user flags to internal signals - //*********************************************** - - //If we are using extra logic for the FWFT data count, then override the - //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. - //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY. - generate - if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ) begin : block3 - assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); - end //block3 - endgenerate - - //If we are using extra logic for the FWFT data count, then override the - //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. - //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. - generate - if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) ) begin : block30 - assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT); - end //block30 - endgenerate - - //If we are not using extra logic for the FWFT data count, - //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the - //internal FIFO instance - generate - if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31 - assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; - end - endgenerate - - //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal - //FIFO instance - generate - if (C_USE_FWFT_DATA_COUNT==1) begin : block4 - assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; - end - else begin : block4 - assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; - end - endgenerate - - - //Connect other flags to the internal FIFO instance - assign FULL = FULL_FIFO_OUT; - assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; - assign WR_ACK = WR_ACK_FIFO_OUT; - assign OVERFLOW = OVERFLOW_FIFO_OUT; - assign PROG_FULL = PROG_FULL_FIFO_OUT; - assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; - - - // if an asynchronous FIFO has been selected, display a message that the FIFO - // will not be cycle-accurate in simulation - initial begin - if (C_IMPLEMENTATION_TYPE == 2) begin - $display("WARNING: Behavioral models for independent clock FIFO configurations are not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information."); - end else if (C_MEMORY_TYPE == 4) begin - $display("FAILURE : Behavioral models for Virtex-4, Virtex-5 and Virtex-6 built-in FIFO configurations is currently not supported. Please select the structural simulation model option in CORE Generator. You can enable this in CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information."); - $finish; - end - end //initial - - /************************************************************************** - * Internal reset logic - **************************************************************************/ - assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0; - assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0; - assign rst_i = C_HAS_RST ? rst_reg : 0; - - wire rst_2_sync; - wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK; - generate - if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync - always @* begin - wr_rst_reg <= WR_RST; - rd_rst_reg <= RD_RST; - rst_reg <= 1'b0; - end - assign rst_2_sync = WR_RST; - end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : gic_rst - assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg; - assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg; - assign rst_2_sync = RST; - - always @(posedge WR_CLK or posedge RST) begin - if (RST == 1'b1) begin - wr_rst_asreg <= #`TCQ 1'b1; - end else begin - if (wr_rst_asreg_d1 == 1'b1) begin - wr_rst_asreg <= #`TCQ 1'b0; - end else begin - wr_rst_asreg <= #`TCQ wr_rst_asreg; - end - end - end - - always @(posedge WR_CLK) begin - wr_rst_asreg_d1 <= #`TCQ wr_rst_asreg; - wr_rst_asreg_d2 <= #`TCQ wr_rst_asreg_d1; - end - - always @(posedge WR_CLK or posedge wr_rst_comb) begin - if (wr_rst_comb == 1'b1) begin - wr_rst_reg <= #`TCQ 1'b1; - end else begin - wr_rst_reg <= #`TCQ 1'b0; - end - end - - always @(posedge RD_CLK or posedge RST) begin - if (RST == 1'b1) begin - rd_rst_asreg <= #`TCQ 1'b1; - end else begin - if (rd_rst_asreg_d1 == 1'b1) begin - rd_rst_asreg <= #`TCQ 1'b0; - end else begin - rd_rst_asreg <= #`TCQ rd_rst_asreg; - end - end - end - - always @(posedge RD_CLK) begin - rd_rst_asreg_d1 <= #`TCQ rd_rst_asreg; - rd_rst_asreg_d2 <= #`TCQ rd_rst_asreg_d1; - end - - always @(posedge RD_CLK or posedge rd_rst_comb) begin - if (rd_rst_comb == 1'b1) begin - rd_rst_reg <= #`TCQ 1'b1; - end else begin - rd_rst_reg <= #`TCQ 1'b0; - end - end - end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : gcc_rst - assign rst_comb = !rst_asreg_d2 && rst_asreg; - assign rst_2_sync = RST; - - always @(posedge CLK or posedge RST) begin - if (RST == 1'b1) begin - rst_asreg <= #`TCQ 1'b1; - end else begin - if (rst_asreg_d1 == 1'b1) begin - rst_asreg <= #`TCQ 1'b0; - end else begin - rst_asreg <= #`TCQ rst_asreg; - end - end - end - - always @(posedge CLK) begin - rst_asreg_d1 <= #`TCQ rst_asreg; - rst_asreg_d2 <= #`TCQ rst_asreg_d1; - end - - always @(posedge CLK or posedge rst_comb) begin - if (rst_comb == 1'b1) begin - rst_reg <= #`TCQ 1'b1; - end else begin - rst_reg <= #`TCQ 1'b0; - end - end - end - endgenerate - - reg rst_d1 = 1'b0; - reg rst_d2 = 1'b0; - reg rst_d3 = 1'b0; - reg rst_d4 = 1'b0; - generate - if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1 - // RST_FULL_GEN replaces the reset falling edge detection used to de-assert - // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1. - - // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL & - // PROG_FULL - - always @ (posedge rst_2_sync or posedge clk_2_sync) begin - if (rst_2_sync) begin - rst_d1 <= 1'b1; - rst_d2 <= 1'b1; - rst_d3 <= 1'b1; - rst_d4 <= 1'b0; - end else begin - if (SRST) begin - rst_d1 <= #`TCQ 1'b1; - rst_d2 <= #`TCQ 1'b1; - rst_d3 <= #`TCQ 1'b1; - rst_d4 <= #`TCQ 1'b0; - end else begin - rst_d1 <= #`TCQ 1'b0; - rst_d2 <= #`TCQ rst_d1; - rst_d3 <= #`TCQ rst_d2; - rst_d4 <= #`TCQ rst_d3; - end - end - end - assign rst_full_ff_i = (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ; - assign rst_full_gen_i = rst_d4; - - end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full - assign rst_full_gen_i = 1'b0; - assign rst_full_ff_i = (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i; - end - endgenerate - -endmodule //FIFO_GENERATOR_V6_1 - - - -/******************************************************************************* - * Declaration of Independent-Clocks FIFO Module - ******************************************************************************/ -module fifo_generator_v6_1_bhv_ver_as - - /*************************************************************************** - * Declare user parameters and their defaults - ***************************************************************************/ - #( - parameter C_DATA_COUNT_WIDTH = 2, - parameter C_DIN_WIDTH = 8, - parameter C_DOUT_RST_VAL = "", - parameter C_DOUT_WIDTH = 8, - parameter C_FULL_FLAGS_RST_VAL = 1, - parameter C_HAS_ALMOST_EMPTY = 0, - parameter C_HAS_ALMOST_FULL = 0, - parameter C_HAS_DATA_COUNT = 0, - parameter C_HAS_OVERFLOW = 0, - parameter C_HAS_RD_DATA_COUNT = 0, - parameter C_HAS_RST = 0, - parameter C_HAS_UNDERFLOW = 0, - parameter C_HAS_VALID = 0, - parameter C_HAS_WR_ACK = 0, - parameter C_HAS_WR_DATA_COUNT = 0, - parameter C_IMPLEMENTATION_TYPE = 0, - parameter C_MEMORY_TYPE = 1, - parameter C_OVERFLOW_LOW = 0, - parameter C_PRELOAD_LATENCY = 1, - parameter C_PRELOAD_REGS = 0, - parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, - parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, - parameter C_PROG_EMPTY_TYPE = 0, - parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, - parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, - parameter C_PROG_FULL_TYPE = 0, - parameter C_RD_DATA_COUNT_WIDTH = 2, - parameter C_RD_DEPTH = 256, - parameter C_RD_PNTR_WIDTH = 8, - parameter C_UNDERFLOW_LOW = 0, - parameter C_USE_DOUT_RST = 0, - parameter C_USE_EMBEDDED_REG = 0, - parameter C_USE_FWFT_DATA_COUNT = 0, - parameter C_VALID_LOW = 0, - parameter C_WR_ACK_LOW = 0, - parameter C_WR_DATA_COUNT_WIDTH = 2, - parameter C_WR_DEPTH = 256, - parameter C_WR_PNTR_WIDTH = 8, - parameter C_USE_ECC = 0, - parameter C_ENABLE_RST_SYNC = 1, - parameter C_ERROR_INJECTION_TYPE = 0 - ) - - /*************************************************************************** - * Declare Input and Output Ports - ***************************************************************************/ - ( - input [C_DIN_WIDTH-1:0] DIN, - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, - input RD_CLK, - input RD_EN, - input RD_EN_USER, - input RST, - input RST_FULL_GEN, - input RST_FULL_FF, - input WR_RST, - input RD_RST, - input WR_CLK, - input WR_EN, - input INJECTDBITERR, - input INJECTSBITERR, - input USER_EMPTY_FB, - output reg ALMOST_EMPTY = 1'b1, - output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL, - output [C_DOUT_WIDTH-1:0] DOUT, - output reg EMPTY = 1'b1, - output reg FULL = C_FULL_FLAGS_RST_VAL, - output OVERFLOW, - output PROG_EMPTY, - output PROG_FULL, - output VALID, - output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, - output UNDERFLOW, - output WR_ACK, - output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, - output SBITERR, - output DBITERR - ); - - reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0; - reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0; - reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0; - - - /*************************************************************************** - * Parameters used as constants - **************************************************************************/ - //When RST is present, set FULL reset value to '1'. - //If core has no RST, make sure FULL powers-on as '0'. - parameter C_DEPTH_RATIO_WR = - (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; - parameter C_DEPTH_RATIO_RD = - (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; - parameter C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; - parameter C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; - - // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC - // -----------------|------------------|-----------------|--------------- - // 1 | 8 | C_RD_PNTR_WIDTH | 2 - // 1 | 4 | C_RD_PNTR_WIDTH | 2 - // 1 | 2 | C_RD_PNTR_WIDTH | 2 - // 1 | 1 | C_WR_PNTR_WIDTH | 2 - // 2 | 1 | C_WR_PNTR_WIDTH | 4 - // 4 | 1 | C_WR_PNTR_WIDTH | 8 - // 8 | 1 | C_WR_PNTR_WIDTH | 16 - - localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; - wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); - - parameter [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; - - parameter [31:0] log2_reads_per_write = log2_val(reads_per_write); - - parameter [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; - - parameter [31:0] log2_writes_per_read = log2_val(writes_per_read); - - - - /************************************************************************** - * FIFO Contents Tracking and Data Count Calculations - *************************************************************************/ - - // Memory which will be used to simulate a FIFO - reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; - // Local parameters used to determine whether to inject ECC error or not - localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; - localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; - localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; - // Array that holds the error injection type (single/double bit error) on - // a specific write operation, which is returned on read to corrupt the - // output data. - reg [1:0] ecc_err[C_WR_DEPTH-1:0]; - - //The amount of data stored in the FIFO at any time is given - // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK - // domain. - //num_wr_bits is calculated by considering the total words in the FIFO, - // and the state of the read pointer (which may not have yet crossed clock - // domains.) - //num_rd_bits is calculated by considering the total words in the FIFO, - // and the state of the write pointer (which may not have yet crossed clock - // domains.) - reg [31:0] num_wr_bits; - reg [31:0] num_rd_bits; - reg [31:0] next_num_wr_bits; - reg [31:0] next_num_rd_bits; - - //The write pointer - tracks write operations - // (Works opposite to core: wr_ptr is a DOWN counter) - reg [31:0] wr_ptr; - reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. - reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; - reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; - reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; - wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; - reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; - wire wr_rst_i = WR_RST; - reg wr_rst_d1 =0; - - //The read pointer - tracks read operations - // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) - reg [31:0] rd_ptr; - reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. - reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; - reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; - reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; - reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; - wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; - reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; - wire rd_rst_i = RD_RST; - wire ram_rd_en; - reg ram_rd_en_d1 = 1'b0; - - - // Delayed ram_rd_en is needed only for STD Embedded register option - generate - if (C_PRELOAD_LATENCY == 2) begin : grd_d - always @ (posedge RD_CLK or posedge rd_rst_i) begin - if (rd_rst_i) - ram_rd_en_d1 <= #`TCQ 1'b0; - else - ram_rd_en_d1 <= #`TCQ ram_rd_en; - end - end - endgenerate - - // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation - generate - if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth - assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; - assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0; - end else begin : rdl // Read depth lesser than or equal to write depth - assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; - end - endgenerate - - // Generate Empty and Almost Empty - // ram_rd_en used to determine EMPTY should depend on the EMPTY. - assign ram_rd_en = RD_EN & !EMPTY; - assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1)))); - assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2)))); - - // Register Empty and Almost Empty - always @ (posedge RD_CLK or posedge rd_rst_i) - begin - if (rd_rst_i) begin - EMPTY <= #`TCQ 1'b1; - ALMOST_EMPTY <= #`TCQ 1'b1; - rd_data_count_int <= #`TCQ {C_RD_PNTR_WIDTH-1{1'b0}}; - end else begin - rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0}; - - if (empty_int) - EMPTY <= #`TCQ 1'b1; - else - EMPTY <= #`TCQ 1'b0; - - if (!EMPTY) begin - if (almost_empty_int) - ALMOST_EMPTY <= #`TCQ 1'b1; - else - ALMOST_EMPTY <= #`TCQ 1'b0; - end - end // rd_rst_i - end // always - - // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation - generate - if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth - assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; - assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0; - end else begin : wdl // Write depth lesser than or equal to read depth - assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; - end - endgenerate - - // Generate FULL and ALMOST_FULL - // ram_wr_en used to determine FULL should depend on the FULL. - assign ram_wr_en = WR_EN & !FULL; - assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2)))); - assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3)))); - - // Register FULL and ALMOST_FULL Empty - always @ (posedge WR_CLK or posedge RST_FULL_FF) - begin - if (RST_FULL_FF) begin - FULL <= #`TCQ C_FULL_FLAGS_RST_VAL; - ALMOST_FULL <= #`TCQ C_FULL_FLAGS_RST_VAL; - wr_data_count_int <= #`TCQ {C_WR_DATA_COUNT_WIDTH-1{1'b0}}; - end else begin - wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0}; - if (full_int) begin - FULL <= #`TCQ 1'b1; - end else begin - FULL <= #`TCQ 1'b0; - end - - if (RST_FULL_GEN) begin - ALMOST_FULL <= #`TCQ 1'b0; - end else if (!FULL) begin - if (almost_full_int) - ALMOST_FULL <= #`TCQ 1'b1; - else - ALMOST_FULL <= #`TCQ 1'b0; - end - end // wr_rst_i - end // always - - // Determine which stage in FWFT registers are valid - reg stage1_valid = 0; - reg stage2_valid = 0; - generate - if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc - always @ (posedge RD_CLK or posedge rd_rst_i) begin - if (rd_rst_i) begin - stage1_valid <= #`TCQ 0; - stage2_valid <= #`TCQ 0; - end else begin - - if (!stage1_valid && !stage2_valid) begin - if (!EMPTY) - stage1_valid <= #`TCQ 1'b1; - else - stage1_valid <= #`TCQ 1'b0; - end else if (stage1_valid && !stage2_valid) begin - if (EMPTY) begin - stage1_valid <= #`TCQ 1'b0; - stage2_valid <= #`TCQ 1'b1; - end else begin - stage1_valid <= #`TCQ 1'b1; - stage2_valid <= #`TCQ 1'b1; - end - end else if (!stage1_valid && stage2_valid) begin - if (EMPTY && RD_EN_USER) begin - stage1_valid <= #`TCQ 1'b0; - stage2_valid <= #`TCQ 1'b0; - end else if (!EMPTY && RD_EN_USER) begin - stage1_valid <= #`TCQ 1'b1; - stage2_valid <= #`TCQ 1'b0; - end else if (!EMPTY && !RD_EN_USER) begin - stage1_valid <= #`TCQ 1'b1; - stage2_valid <= #`TCQ 1'b1; - end else begin - stage1_valid <= #`TCQ 1'b0; - stage2_valid <= #`TCQ 1'b1; - end - end else if (stage1_valid && stage2_valid) begin - if (EMPTY && RD_EN_USER) begin - stage1_valid <= #`TCQ 1'b0; - stage2_valid <= #`TCQ 1'b1; - end else begin - stage1_valid <= #`TCQ 1'b1; - stage2_valid <= #`TCQ 1'b1; - end - end else begin - stage1_valid <= #`TCQ 1'b0; - stage2_valid <= #`TCQ 1'b0; - end - end // rd_rst_i - end // always - end - endgenerate - - //Pointers passed into opposite clock domain - reg [31:0] wr_ptr_rdclk; - reg [31:0] wr_ptr_rdclk_next; - reg [31:0] rd_ptr_wrclk; - reg [31:0] rd_ptr_wrclk_next; - - //Amount of data stored in the FIFO scaled to the narrowest (deepest) port - // (Do not include data in FWFT stages) - //Used to calculate PROG_EMPTY. - wire [31:0] num_read_words_pe = - num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); - - //Amount of data stored in the FIFO scaled to the narrowest (deepest) port - // (Do not include data in FWFT stages) - //Used to calculate PROG_FULL. - wire [31:0] num_write_words_pf = - num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); - - /************************** - * Read Data Count - *************************/ - - reg [31:0] num_read_words_dc; - reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; - - always @(num_rd_bits) begin - if (C_USE_FWFT_DATA_COUNT) begin - - //If using extra logic for FWFT Data Counts, - // then scale FIFO contents to read domain, - // and add two read words for FWFT stages - //This value is only a temporary value and not used in the code. - num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); - - //Trim the read words for use with RD_DATA_COUNT - num_read_words_sized_i = - num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; - - end else begin - - //If not using extra logic for FWFT Data Counts, - // then scale FIFO contents to read domain. - //This value is only a temporary value and not used in the code. - num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; - - //Trim the read words for use with RD_DATA_COUNT - num_read_words_sized_i = - num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; - - end //if (C_USE_FWFT_DATA_COUNT) - end //always - - - /************************** - * Write Data Count - *************************/ - - reg [31:0] num_write_words_dc; - reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; - - always @(num_wr_bits) begin - if (C_USE_FWFT_DATA_COUNT) begin - - //Calculate the Data Count value for the number of write words, - // when using First-Word Fall-Through with extra logic for Data - // Counts. This takes into consideration the number of words that - // are expected to be stored in the FWFT register stages (it always - // assumes they are filled). - //This value is scaled to the Write Domain. - //The expression (((A-1)/B))+1 divides A/B, but takes the - // ceiling of the result. - //When num_wr_bits==0, set the result manually to prevent - // division errors. - //EXTRA_WORDS_DC is the number of words added to write_words - // due to FWFT. - //This value is only a temporary value and not used in the code. - num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; - - //Trim the write words for use with WR_DATA_COUNT - num_write_words_sized_i = - num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; - - end else begin - - //Calculate the Data Count value for the number of write words, when NOT - // using First-Word Fall-Through with extra logic for Data Counts. This - // calculates only the number of words in the internal FIFO. - //The expression (((A-1)/B))+1 divides A/B, but takes the - // ceiling of the result. - //This value is scaled to the Write Domain. - //When num_wr_bits==0, set the result manually to prevent - // division errors. - //This value is only a temporary value and not used in the code. - num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; - - //Trim the read words for use with RD_DATA_COUNT - num_write_words_sized_i = - num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; - - end //if (C_USE_FWFT_DATA_COUNT) - end //always - - - - /*************************************************************************** - * Internal registers and wires - **************************************************************************/ - - //Temporary signals used for calculating the model's outputs. These - //are only used in the assign statements immediately following wire, - //parameter, and function declarations. - wire [C_DOUT_WIDTH-1:0] ideal_dout_out; - wire valid_i; - wire valid_out; - wire underflow_i; - - //Ideal FIFO signals. These are the raw output of the behavioral model, - //which behaves like an ideal FIFO. - reg [1:0] err_type = 0; - reg [1:0] err_type_d1 = 0; - reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; - reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; - reg ideal_wr_ack = 0; - reg ideal_valid = 0; - reg ideal_overflow = 0; - reg ideal_underflow = 0; - reg ideal_prog_full = 0; - reg ideal_prog_empty = 1; - reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0; - reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0; - - //Assorted reg values for delayed versions of signals - reg valid_d1 = 0; - - - //user specified value for reseting the size of the fifo - reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; - - //temporary registers for WR_RESPONSE_LATENCY feature - - integer tmp_wr_listsize; - integer tmp_rd_listsize; - - //Signal for registered version of prog full and empty - - //Threshold values for Programmable Flags - integer prog_empty_actual_thresh_assert; - integer prog_empty_actual_thresh_negate; - integer prog_full_actual_thresh_assert; - integer prog_full_actual_thresh_negate; - - - /**************************************************************************** - * Function Declarations - ***************************************************************************/ - - /************************************************************************** - * write_fifo - * This task writes a word to the FIFO memory and updates the - * write pointer. - * FIFO size is relative to write domain. - ***************************************************************************/ - task write_fifo; - begin - memory[wr_ptr] <= DIN; - wr_pntr <= #`TCQ wr_pntr + 1; - // Store the type of error injection (double/single) on write - case (C_ERROR_INJECTION_TYPE) - 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; - 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; - 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; - default: ecc_err[wr_ptr] <= 0; - endcase - // (Works opposite to core: wr_ptr is a DOWN counter) - if (wr_ptr == 0) begin - wr_ptr <= C_WR_DEPTH - 1; - end else begin - wr_ptr <= wr_ptr - 1; - end - end - endtask // write_fifo - - /************************************************************************** - * read_fifo - * This task reads a word from the FIFO memory and updates the read - * pointer. It's output is the ideal_dout bus. - * FIFO size is relative to write domain. - ***************************************************************************/ - task read_fifo; - integer i; - reg [C_DOUT_WIDTH-1:0] tmp_dout; - reg [C_DIN_WIDTH-1:0] memory_read; - reg [31:0] tmp_rd_ptr; - reg [31:0] rd_ptr_high; - reg [31:0] rd_ptr_low; - reg [1:0] tmp_ecc_err; - begin - rd_pntr <= #`TCQ rd_pntr + 1; - // output is wider than input - if (reads_per_write == 0) begin - tmp_dout = 0; - tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); - for (i = writes_per_read - 1; i >= 0; i = i - 1) begin - tmp_dout = tmp_dout << C_DIN_WIDTH; - tmp_dout = tmp_dout | memory[tmp_rd_ptr]; - - // (Works opposite to core: rd_ptr is a DOWN counter) - if (tmp_rd_ptr == 0) begin - tmp_rd_ptr = C_WR_DEPTH - 1; - end else begin - tmp_rd_ptr = tmp_rd_ptr - 1; - end - end - - // output is symmetric - end else if (reads_per_write == 1) begin - tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; - // Retreive the error injection type. Based on the error injection type - // corrupt the output data. - tmp_ecc_err = ecc_err[rd_ptr]; - if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin - if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error - if (C_DOUT_WIDTH == 1) - tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; - else if (C_DOUT_WIDTH == 2) - tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; - else - tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; - end else begin - tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; - end - err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; - end else begin - err_type <= 0; - end - - // input is wider than output - end else begin - rd_ptr_high = rd_ptr >> log2_reads_per_write; - rd_ptr_low = rd_ptr & (reads_per_write - 1); - memory_read = memory[rd_ptr_high]; - tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); - end - ideal_dout <= tmp_dout; - - // (Works opposite to core: rd_ptr is a DOWN counter) - if (rd_ptr == 0) begin - rd_ptr <= C_RD_DEPTH - 1; - end else begin - rd_ptr <= rd_ptr - 1; - end - end - endtask - - /************************************************************************** - * log2_val - * Returns the 'log2' value for the input value for the supported ratios - ***************************************************************************/ - function [31:0] log2_val; - input [31:0] binary_val; - - begin - if (binary_val == 8) begin - log2_val = 3; - end else if (binary_val == 4) begin - log2_val = 2; - end else begin - log2_val = 1; - end - end - endfunction - - /*********************************************************************** - * hexstr_conv - * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) - ***********************************************************************/ - function [C_DOUT_WIDTH-1:0] hexstr_conv; - input [(C_DOUT_WIDTH*8)-1:0] def_data; - - integer index,i,j; - reg [3:0] bin; - - begin - index = 0; - hexstr_conv = 'b0; - for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) - begin - case (def_data[7:0]) - 8'b00000000 : - begin - bin = 4'b0000; - i = -1; - end - 8'b00110000 : bin = 4'b0000; - 8'b00110001 : bin = 4'b0001; - 8'b00110010 : bin = 4'b0010; - 8'b00110011 : bin = 4'b0011; - 8'b00110100 : bin = 4'b0100; - 8'b00110101 : bin = 4'b0101; - 8'b00110110 : bin = 4'b0110; - 8'b00110111 : bin = 4'b0111; - 8'b00111000 : bin = 4'b1000; - 8'b00111001 : bin = 4'b1001; - 8'b01000001 : bin = 4'b1010; - 8'b01000010 : bin = 4'b1011; - 8'b01000011 : bin = 4'b1100; - 8'b01000100 : bin = 4'b1101; - 8'b01000101 : bin = 4'b1110; - 8'b01000110 : bin = 4'b1111; - 8'b01100001 : bin = 4'b1010; - 8'b01100010 : bin = 4'b1011; - 8'b01100011 : bin = 4'b1100; - 8'b01100100 : bin = 4'b1101; - 8'b01100101 : bin = 4'b1110; - 8'b01100110 : bin = 4'b1111; - default : - begin - bin = 4'bx; - end - endcase - for( j=0; j<4; j=j+1) - begin - if ((index*4)+j < C_DOUT_WIDTH) - begin - hexstr_conv[(index*4)+j] = bin[j]; - end - end - index = index + 1; - def_data = def_data >> 8; - end - end - endfunction - - /************************************************************************* - * Initialize Signals for clean power-on simulation - *************************************************************************/ - initial begin - num_wr_bits = 0; - num_rd_bits = 0; - next_num_wr_bits = 0; - next_num_rd_bits = 0; - rd_ptr = C_RD_DEPTH - 1; - wr_ptr = C_WR_DEPTH - 1; - wr_pntr = 0; - rd_pntr = 0; - rd_ptr_wrclk = rd_ptr; - wr_ptr_rdclk = wr_ptr; - dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); - ideal_dout = dout_reset_val; - err_type = 0; - ideal_dout_d1 = dout_reset_val; - ideal_wr_ack = 1'b0; - ideal_valid = 1'b0; - valid_d1 = 1'b0; - ideal_overflow = 1'b0; - ideal_underflow = 1'b0; - ideal_wr_count = 0; - ideal_rd_count = 0; - ideal_prog_full = 1'b0; - ideal_prog_empty = 1'b1; - end - - - /************************************************************************* - * Connect the module inputs and outputs to the internal signals of the - * behavioral model. - *************************************************************************/ - //Inputs - /* - wire [C_DIN_WIDTH-1:0] DIN; - wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; - wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; - wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; - wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; - wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; - wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; - wire RD_CLK; - wire RD_EN; - wire RST; - wire WR_CLK; - wire WR_EN; - */ - - //*************************************************************************** - // Dout may change behavior based on latency - //*************************************************************************** - assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 && - (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? - ideal_dout_d1: ideal_dout; - assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; - - //*************************************************************************** - // Assign SBITERR and DBITERR based on latency - //*************************************************************************** - assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && - (C_PRELOAD_LATENCY == 2 && - (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? - err_type_d1[0]: err_type[0]; - assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && - (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? - err_type_d1[1]: err_type[1]; - - - //*************************************************************************** - // Overflow may be active-low - //*************************************************************************** - generate - if (C_HAS_OVERFLOW==1) begin : blockOF1 - assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; - end - endgenerate - - assign PROG_EMPTY = ideal_prog_empty; - assign PROG_FULL = ideal_prog_full; - - //*************************************************************************** - // Valid may change behavior based on latency or active-low - //*************************************************************************** - generate - if (C_HAS_VALID==1) begin : blockVL1 - assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; - assign valid_out = (C_PRELOAD_LATENCY==2 && - (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? - valid_d1: valid_i; - assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; - end - endgenerate - - - //*************************************************************************** - // Underflow may change behavior based on latency or active-low - //*************************************************************************** - generate - if (C_HAS_UNDERFLOW==1) begin : blockUF1 - assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; - assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; - end - endgenerate - - //*************************************************************************** - // Write acknowledge may be active low - //*************************************************************************** - generate - if (C_HAS_WR_ACK==1) begin : blockWK1 - assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; - end - endgenerate - - - //*************************************************************************** - // Generate RD_DATA_COUNT if Use Extra Logic option is selected - //*************************************************************************** - generate - if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext - - reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0; - reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0; - wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp; - wire [C_PNTR_WIDTH:0] diff_wr_rd; - reg [C_PNTR_WIDTH:0] wr_data_count_i = 0; - always @* begin - if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin - adjusted_wr_pntr = wr_pntr; - adjusted_rd_pntr = 0; - adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; - end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin - adjusted_rd_pntr = rd_pntr_wr; - adjusted_wr_pntr = 0; - adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; - end else begin - adjusted_wr_pntr = wr_pntr; - adjusted_rd_pntr = rd_pntr_wr; - end - end // always @* - - assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr; - assign diff_wr_rd = {1'b0,diff_wr_rd_tmp}; - - always @ (posedge wr_rst_i or posedge WR_CLK) - begin - if (wr_rst_i) - wr_data_count_i <= #`TCQ 0; - else - wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC; - end // always @ (posedge WR_CLK or posedge WR_CLK) - - always @* begin - if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) - wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0]; - else - wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; - end // always @* - end // wdc_fwft_ext - endgenerate - - //*************************************************************************** - // Generate RD_DATA_COUNT if Use Extra Logic option is selected - //*************************************************************************** - reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0; - - generate - if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext - reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; - wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; - wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; - always @* begin - if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin - adjusted_wr_pntr_rd = 0; - adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; - end else begin - adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; - end - end // always @* - - assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; - assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; - - always @ (posedge rd_rst_i or posedge RD_CLK) - begin - if (rd_rst_i) begin - rdc_fwft_ext_as <= #`TCQ 0; - end else begin - if (!stage2_valid) - rdc_fwft_ext_as <= #`TCQ 0; - else if (!stage1_valid && stage2_valid) - rdc_fwft_ext_as <= #`TCQ 1; - else - rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2; - end - end // always @ (posedge WR_CLK or posedge WR_CLK) - end // rdc_fwft_ext - endgenerate - - //*************************************************************************** - // Assign the read data count value only if it is selected, - // otherwise output zeros. - //*************************************************************************** - generate - if (C_HAS_RD_DATA_COUNT == 1) begin : grdc - assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ? - rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] : - rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; - end - endgenerate - - generate - if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc - assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH-1{1'b0}}; - end - endgenerate - - //*************************************************************************** - // Assign the write data count value only if it is selected, - // otherwise output zeros - //*************************************************************************** - generate - if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc - assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ? - wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] : - wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH]; - end - endgenerate - - generate - if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc - assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH-1{1'b0}}; - end - endgenerate - - - /************************************************************************** - * Assorted registers for delayed versions of signals - **************************************************************************/ - //Capture delayed version of valid - generate - if (C_HAS_VALID==1) begin : blockVL2 - always @(posedge RD_CLK or posedge rd_rst_i) begin - if (rd_rst_i == 1'b1) begin - valid_d1 <= #`TCQ 1'b0; - end else begin - valid_d1 <= #`TCQ valid_i; - end - end - end - endgenerate - - //Capture delayed version of dout - always @(posedge RD_CLK or posedge rd_rst_i) begin - if (rd_rst_i == 1'b1) begin - // Reset err_type only if ECC is not selected - if (C_USE_ECC == 0) - err_type_d1 <= #`TCQ 0; - end else if (ram_rd_en_d1) begin - ideal_dout_d1 <= #`TCQ ideal_dout; - err_type_d1 <= #`TCQ err_type; - end - end - - /************************************************************************** - * Overflow and Underflow Flag calculation - * (handled separately because they don't support rst) - **************************************************************************/ - generate - if (C_HAS_OVERFLOW==1) begin : blockOF2 - always @(posedge WR_CLK) begin - ideal_overflow <= #`TCQ WR_EN & FULL; - end - end - endgenerate - - generate - if (C_HAS_UNDERFLOW==1) begin : blockUF2 - always @(posedge RD_CLK) begin - ideal_underflow <= #`TCQ EMPTY & RD_EN; - end - end - endgenerate - - /************************************************************************** - * Write Domain Logic - **************************************************************************/ - reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0; - always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w - - /****** Reset fifo (case 1)***************************************/ - if (wr_rst_i == 1'b1) begin - num_wr_bits <= #`TCQ 0; - next_num_wr_bits = #`TCQ 0; - wr_ptr <= #`TCQ C_WR_DEPTH - 1; - rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; - ideal_wr_ack <= #`TCQ 0; - ideal_wr_count <= #`TCQ 0; - tmp_wr_listsize = #`TCQ 0; - rd_ptr_wrclk_next <= #`TCQ 0; - wr_pntr <= #`TCQ 0; - wr_pntr_rd1 <= #`TCQ 0; - rd_pntr_wr2 <= #`TCQ 0; - rd_pntr_wr3 <= #`TCQ 0; - rd_pntr_wr4 <= #`TCQ 0; - rd_pntr_wr <= #`TCQ 0; - - - end else begin //wr_rst_i==0 - - wr_pntr_rd1 <= #`TCQ wr_pntr; - - // Synchronize the rd_pntr in read domain - rd_pntr_wr2 <= #`TCQ rd_pntr_wr1; - rd_pntr_wr3 <= #`TCQ rd_pntr_wr2; - rd_pntr_wr4 <= #`TCQ rd_pntr_wr2; - rd_pntr_wr <= #`TCQ rd_pntr_wr4; - - - - //Determine the current number of words in the FIFO - tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : - num_wr_bits/C_DIN_WIDTH; - rd_ptr_wrclk_next = rd_ptr; - if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin - next_num_wr_bits = num_wr_bits - - C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH - - rd_ptr_wrclk_next); - end else begin - next_num_wr_bits = num_wr_bits - - C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); - end - - //If this is a write, handle the write by adding the value - // to the linked list, and updating all outputs appropriately - if (WR_EN == 1'b1) begin - if (FULL == 1'b1) begin - - //If the FIFO is full, do NOT perform the write, - // update flags accordingly - if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD - >= C_FIFO_WR_DEPTH) begin - //write unsuccessful - do not change contents - - //Do not acknowledge the write - ideal_wr_ack <= #`TCQ 0; - //Reminder that FIFO is still full - - ideal_wr_count <= #`TCQ num_write_words_sized_i; - - //If the FIFO is one from full, but reporting full - end else - if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == - C_FIFO_WR_DEPTH-1) begin - //No change to FIFO - - //Write not successful - ideal_wr_ack <= #`TCQ 0; - //With DEPTH-1 words in the FIFO, it is almost_full - - ideal_wr_count <= #`TCQ num_write_words_sized_i; - - - //If the FIFO is completely empty, but it is - // reporting FULL for some reason (like reset) - end else - if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= - C_FIFO_WR_DEPTH-2) begin - //No change to FIFO - - //Write not successful - ideal_wr_ack <= #`TCQ 0; - //FIFO is really not close to full, so change flag status. - - ideal_wr_count <= #`TCQ num_write_words_sized_i; - end //(tmp_wr_listsize == 0) - - end else begin - - //If the FIFO is full, do NOT perform the write, - // update flags accordingly - if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= - C_FIFO_WR_DEPTH) begin - //write unsuccessful - do not change contents - - //Do not acknowledge the write - ideal_wr_ack <= #`TCQ 0; - //Reminder that FIFO is still full - - ideal_wr_count <= #`TCQ num_write_words_sized_i; - - //If the FIFO is one from full - end else - if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == - C_FIFO_WR_DEPTH-1) begin - //Add value on DIN port to FIFO - write_fifo; - next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; - - //Write successful, so issue acknowledge - // and no error - ideal_wr_ack <= #`TCQ 1; - //This write is CAUSING the FIFO to go full - - ideal_wr_count <= #`TCQ num_write_words_sized_i; - - //If the FIFO is 2 from full - end else - if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == - C_FIFO_WR_DEPTH-2) begin - //Add value on DIN port to FIFO - write_fifo; - next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; - //Write successful, so issue acknowledge - // and no error - ideal_wr_ack <= #`TCQ 1; - //Still 2 from full - - ideal_wr_count <= #`TCQ num_write_words_sized_i; - - //If the FIFO is not close to being full - end else - if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < - C_FIFO_WR_DEPTH-2) begin - //Add value on DIN port to FIFO - write_fifo; - next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; - //Write successful, so issue acknowledge - // and no error - ideal_wr_ack <= #`TCQ 1; - //Not even close to full. - - ideal_wr_count <= num_write_words_sized_i; - - end - - end - - end else begin //(WR_EN == 1'b1) - - //If user did not attempt a write, then do not - // give ack or err - ideal_wr_ack <= #`TCQ 0; - ideal_wr_count <= #`TCQ num_write_words_sized_i; - end - num_wr_bits <= #`TCQ next_num_wr_bits; - rd_ptr_wrclk <= #`TCQ rd_ptr; - - end //wr_rst_i==0 - end // write always - - - /*************************************************************************** - * Programmable FULL flags - ***************************************************************************/ - - always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf - - if (RST_FULL_FF == 1'b1) begin - diff_pntr <= 0; - ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; - end else begin - if (ram_wr_en) - diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1); - else if (!ram_wr_en) - diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr); - - if (RST_FULL_GEN) - ideal_prog_full <= #`TCQ 0; - //Single Programmable Full Constant Threshold - else if (C_PROG_FULL_TYPE == 1) begin - if (FULL == 0) begin - if (diff_pntr >= C_PROG_FULL_THRESH_ASSERT_VAL) - ideal_prog_full <= #`TCQ 1; - else - ideal_prog_full <= #`TCQ 0; - end else - ideal_prog_full <= #`TCQ ideal_prog_full; - //Two Programmable Full Constant Thresholds - end else if (C_PROG_FULL_TYPE == 2) begin - if (FULL == 0) begin - if (diff_pntr >= C_PROG_FULL_THRESH_ASSERT_VAL) - ideal_prog_full <= #`TCQ 1; - else if (diff_pntr < C_PROG_FULL_THRESH_NEGATE_VAL) - ideal_prog_full <= #`TCQ 0; - else - ideal_prog_full <= #`TCQ ideal_prog_full; - end else - ideal_prog_full <= #`TCQ ideal_prog_full; - //Single Programmable Full Threshold Input - end else if (C_PROG_FULL_TYPE == 3) begin - if (FULL == 0) begin - if (diff_pntr >= PROG_FULL_THRESH) - ideal_prog_full <= #`TCQ 1; - else - ideal_prog_full <= #`TCQ 0; - end else - ideal_prog_full <= #`TCQ ideal_prog_full; - //Two Programmable Full Threshold Inputs - end else if (C_PROG_FULL_TYPE == 4) begin - if (FULL == 0) begin - if (diff_pntr >= PROG_FULL_THRESH_ASSERT) - ideal_prog_full <= #`TCQ 1; - else if (diff_pntr < PROG_FULL_THRESH_NEGATE) - ideal_prog_full <= #`TCQ 0; - else - ideal_prog_full <= #`TCQ ideal_prog_full; - end else - ideal_prog_full <= #`TCQ ideal_prog_full; - end // C_PROG_FULL_TYPE - - end //wr_rst_i==0 - end // - - - /************************************************************************** - * Read Domain Logic - **************************************************************************/ - - - /********************************************************* - * Programmable EMPTY flags - *********************************************************/ - //Determine the Assert and Negate thresholds for Programmable Empty - - reg [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val = 0; - reg [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val = 0; - reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0; - always @* begin - - if (C_PROG_EMPTY_TYPE == 3) begin - - // If empty input threshold is selected, then subtract 2 for FWFT to - // compensate the FWFT stage, otherwise assign the input value. - if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) // FWFT - pe_thr_assert_val <= PROG_EMPTY_THRESH - 2'h2; - else - pe_thr_assert_val <= PROG_EMPTY_THRESH; - - end else if (C_PROG_EMPTY_TYPE == 4) begin - - // If empty input threshold is selected, then subtract 2 for FWFT to - // compensate the FWFT stage, otherwise assign the input value. - if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT - pe_thr_assert_val <= PROG_EMPTY_THRESH_ASSERT - 2'h2; - pe_thr_negate_val <= PROG_EMPTY_THRESH_NEGATE - 2'h2; - end else begin - pe_thr_assert_val <= PROG_EMPTY_THRESH_ASSERT; - pe_thr_negate_val <= PROG_EMPTY_THRESH_NEGATE; - end - end else begin - - if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT - pe_thr_assert_val <= C_PROG_EMPTY_THRESH_ASSERT_VAL - 2; - pe_thr_negate_val <= C_PROG_EMPTY_THRESH_NEGATE_VAL - 2; - end else begin - pe_thr_assert_val <= C_PROG_EMPTY_THRESH_ASSERT_VAL; - pe_thr_negate_val <= C_PROG_EMPTY_THRESH_NEGATE_VAL; - end - end - end // always @* - - always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe - - if (rd_rst_i) begin - diff_pntr_rd <= #`TCQ 0; - ideal_prog_empty <= #`TCQ 1'b1; - end else begin - if (ram_rd_en) - diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1; - else if (!ram_rd_en) - diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr); - else - diff_pntr_rd <= #`TCQ diff_pntr_rd; - - if (C_PROG_EMPTY_TYPE == 1) begin - if (EMPTY == 0) begin - if (diff_pntr_rd <= pe_thr_assert_val) - ideal_prog_empty <= #`TCQ 1; - else - ideal_prog_empty <= #`TCQ 0; - end else - ideal_prog_empty <= #`TCQ ideal_prog_empty; - end else if (C_PROG_EMPTY_TYPE == 2) begin - if (EMPTY == 0) begin - if (diff_pntr_rd <= pe_thr_assert_val) - ideal_prog_empty <= #`TCQ 1; - else if (diff_pntr_rd > pe_thr_negate_val) - ideal_prog_empty <= #`TCQ 0; - else - ideal_prog_empty <= #`TCQ ideal_prog_empty; - end else - ideal_prog_empty <= #`TCQ ideal_prog_empty; - end else if (C_PROG_EMPTY_TYPE == 3) begin - if (EMPTY == 0) begin - if (diff_pntr_rd <= pe_thr_assert_val) - ideal_prog_empty <= #`TCQ 1; - else - ideal_prog_empty <= #`TCQ 0; - end else - ideal_prog_empty <= #`TCQ ideal_prog_empty; - end else if (C_PROG_EMPTY_TYPE == 4) begin - if (EMPTY == 0) begin - if (diff_pntr_rd >= pe_thr_assert_val) - ideal_prog_empty <= #`TCQ 1; - else if (diff_pntr_rd > pe_thr_negate_val) - ideal_prog_empty <= #`TCQ 0; - else - ideal_prog_empty <= #`TCQ ideal_prog_empty; - end else - ideal_prog_empty <= #`TCQ ideal_prog_empty; - end //C_PROG_EMPTY_TYPE - end - end - - // block memory has a synchronous reset - always @(posedge RD_CLK) begin : gen_fifo_blkmemdout - // make it consistent with the core. - if (rd_rst_i) begin - // Reset err_type only if ECC is not selected - if (C_USE_ECC == 0 && C_MEMORY_TYPE < 2) - err_type <= #`TCQ 0; - - // BRAM resets synchronously - if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin - ideal_dout <= #`TCQ dout_reset_val; - ideal_dout_d1 <= #`TCQ dout_reset_val; - end - end - end //always - - always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r - - /****** Reset fifo (case 1)***************************************/ - if (rd_rst_i) begin - num_rd_bits <= #`TCQ 0; - next_num_rd_bits = #`TCQ 0; - rd_ptr <= #`TCQ C_RD_DEPTH -1; - rd_pntr <= #`TCQ 0; - rd_pntr_wr1 <= #`TCQ 0; - wr_pntr_rd2 <= #`TCQ 0; - wr_pntr_rd3 <= #`TCQ 0; - wr_pntr_rd <= #`TCQ 0; - wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; - - // DRAM resets asynchronously - if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1) - ideal_dout <= #`TCQ dout_reset_val; - - // Reset err_type only if ECC is not selected - if (C_USE_ECC == 0) - err_type <= #`TCQ 0; - ideal_valid <= #`TCQ 1'b0; - ideal_rd_count <= #`TCQ 0; - - end else begin //rd_rst_i==0 - - rd_pntr_wr1 <= #`TCQ rd_pntr; - - // Synchronize the wr_pntr in read domain - wr_pntr_rd2 <= #`TCQ wr_pntr_rd1; - wr_pntr_rd3 <= #`TCQ wr_pntr_rd2; - wr_pntr_rd <= #`TCQ wr_pntr_rd3; - - - - //Determine the current number of words in the FIFO - tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : - num_rd_bits/C_DOUT_WIDTH; - wr_ptr_rdclk_next = wr_ptr; - - if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin - next_num_rd_bits = num_rd_bits + - C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH - - wr_ptr_rdclk_next); - end else begin - next_num_rd_bits = num_rd_bits + - C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); - end - - /*****************************************************************/ - // Read Operation - Read Latency 1 - /*****************************************************************/ - if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin - ideal_valid <= #`TCQ 1'b0; - - if (ram_rd_en == 1'b1) begin - - if (EMPTY == 1'b1) begin - - //If the FIFO is completely empty, and is reporting empty - if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) - begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= #`TCQ 1'b0; - //Reminder that FIFO is still empty - - ideal_rd_count <= #`TCQ num_read_words_sized_i; - end // if (tmp_rd_listsize <= 0) - - //If the FIFO is one from empty, but it is reporting empty - else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) - begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= #`TCQ 1'b0; - //Note that FIFO is no longer empty, but is almost empty (has one word left) - - ideal_rd_count <= #`TCQ num_read_words_sized_i; - - end // if (tmp_rd_listsize == 1) - - //If the FIFO is two from empty, and is reporting empty - else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) - begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= #`TCQ 1'b0; - //Fifo has two words, so is neither empty or almost empty - - ideal_rd_count <= #`TCQ num_read_words_sized_i; - - end // if (tmp_rd_listsize == 2) - - //If the FIFO is not close to empty, but is reporting that it is - // Treat the FIFO as empty this time, but unset EMPTY flags. - if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) - end // else: if(ideal_empty == 1'b1) - - else //if (ideal_empty == 1'b0) - begin - - //If the FIFO is completely full, and we are successfully reading from it - if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) - begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= #`TCQ 1'b1; - //Not close to empty - - ideal_rd_count <= #`TCQ num_read_words_sized_i; - - end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) - - //If the FIFO is not close to being empty - else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) - begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= #`TCQ 1'b1; - //Not close to empty - - ideal_rd_count <= #`TCQ num_read_words_sized_i; - - end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) - - //If the FIFO is two from empty - else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) - begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= #`TCQ 1'b1; - //Fifo is not yet empty. It is going almost_empty - - ideal_rd_count <= #`TCQ num_read_words_sized_i; - - end // if (tmp_rd_listsize == 2) - - //If the FIFO is one from empty - else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) - begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= #`TCQ 1'b1; - //Note that FIFO is GOING empty - - ideal_rd_count <= #`TCQ num_read_words_sized_i; - - end // if (tmp_rd_listsize == 1) - - - //If the FIFO is completely empty - else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) - begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= #`TCQ 1'b0; - - ideal_rd_count <= #`TCQ num_read_words_sized_i; - - end // if (tmp_rd_listsize <= 0) - - end // if (ideal_empty == 1'b0) - - end //(RD_EN == 1'b1) - - else //if (RD_EN == 1'b0) - begin - //If user did not attempt a read, do not give an ack or err - ideal_valid <= #`TCQ 1'b0; - - ideal_rd_count <= #`TCQ num_read_words_sized_i; - - end // else: !if(RD_EN == 1'b1) - - /*****************************************************************/ - // Read Operation - Read Latency 0 - /*****************************************************************/ - end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - ideal_valid <= #`TCQ 1'b0; - if (ram_rd_en == 1'b1) begin - - if (EMPTY == 1'b1) begin - - //If the FIFO is completely empty, and is reporting empty - if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= #`TCQ 1'b0; - //Reminder that FIFO is still empty - - ideal_rd_count <= #`TCQ num_read_words_sized_i; - - //If the FIFO is one from empty, but it is reporting empty - end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= #`TCQ 1'b0; - //Note that FIFO is no longer empty, but is almost empty (has one word left) - - ideal_rd_count <= #`TCQ num_read_words_sized_i; - - //If the FIFO is two from empty, and is reporting empty - end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= #`TCQ 1'b0; - //Fifo has two words, so is neither empty or almost empty - - ideal_rd_count <= #`TCQ num_read_words_sized_i; - - //If the FIFO is not close to empty, but is reporting that it is - // Treat the FIFO as empty this time, but unset EMPTY flags. - end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && - (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) - - end else begin - - //If the FIFO is completely full, and we are successfully reading from it - if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= #`TCQ 1'b1; - //Not close to empty - - ideal_rd_count <= #`TCQ num_read_words_sized_i; - - //If the FIFO is not close to being empty - end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && - (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= #`TCQ 1'b1; - //Not close to empty - - ideal_rd_count <= #`TCQ num_read_words_sized_i; - - //If the FIFO is two from empty - end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= #`TCQ 1'b1; - //Fifo is not yet empty. It is going almost_empty - - ideal_rd_count <= #`TCQ num_read_words_sized_i; - - //If the FIFO is one from empty - end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= #`TCQ 1'b1; - //Note that FIFO is GOING empty - - ideal_rd_count <= #`TCQ num_read_words_sized_i; - - //If the FIFO is completely empty - end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= #`TCQ 1'b0; - //Reminder that FIFO is still empty - - ideal_rd_count <= #`TCQ num_read_words_sized_i; - - end // if (tmp_rd_listsize <= 0) - - end // if (ideal_empty == 1'b0) - - end else begin//(RD_EN == 1'b0) - - - //If user did not attempt a read, do not give an ack or err - ideal_valid <= #`TCQ 1'b0; - ideal_rd_count <= #`TCQ num_read_words_sized_i; - - end // else: !if(RD_EN == 1'b1) - end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) - - num_rd_bits <= #`TCQ next_num_rd_bits; - wr_ptr_rdclk <= #`TCQ wr_ptr; - end //rd_rst_i==0 - end //always - -endmodule // fifo_generator_v6_1_bhv_ver_as - - -/******************************************************************************* - * Declaration of top-level module - ******************************************************************************/ -module fifo_generator_v6_1_bhv_ver_ss - - /************************************************************************** - * Declare user parameters and their defaults - *************************************************************************/ - #( - parameter C_DATA_COUNT_WIDTH = 2, - parameter C_DIN_WIDTH = 8, - parameter C_DOUT_RST_VAL = "", - parameter C_DOUT_WIDTH = 8, - parameter C_FULL_FLAGS_RST_VAL = 1, - parameter C_HAS_ALMOST_EMPTY = 0, - parameter C_HAS_ALMOST_FULL = 0, - parameter C_HAS_DATA_COUNT = 0, - parameter C_HAS_OVERFLOW = 0, - parameter C_HAS_RD_DATA_COUNT = 0, - parameter C_HAS_RST = 0, - parameter C_HAS_SRST = 0, - parameter C_HAS_UNDERFLOW = 0, - parameter C_HAS_VALID = 0, - parameter C_HAS_WR_ACK = 0, - parameter C_HAS_WR_DATA_COUNT = 0, - parameter C_IMPLEMENTATION_TYPE = 0, - parameter C_MEMORY_TYPE = 1, - parameter C_OVERFLOW_LOW = 0, - parameter C_PRELOAD_LATENCY = 1, - parameter C_PRELOAD_REGS = 0, - parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, - parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, - parameter C_PROG_EMPTY_TYPE = 0, - parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, - parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, - parameter C_PROG_FULL_TYPE = 0, - parameter C_RD_DATA_COUNT_WIDTH = 2, - parameter C_RD_DEPTH = 256, - parameter C_RD_PNTR_WIDTH = 8, - parameter C_UNDERFLOW_LOW = 0, - parameter C_USE_DOUT_RST = 0, - parameter C_USE_EMBEDDED_REG = 0, - parameter C_USE_FWFT_DATA_COUNT = 0, - parameter C_VALID_LOW = 0, - parameter C_WR_ACK_LOW = 0, - parameter C_WR_DATA_COUNT_WIDTH = 2, - parameter C_WR_DEPTH = 256, - parameter C_WR_PNTR_WIDTH = 8, - parameter C_USE_ECC = 0, - parameter C_ENABLE_RST_SYNC = 1, - parameter C_ERROR_INJECTION_TYPE = 0 - ) - - /************************************************************************** - * Declare Input and Output Ports - *************************************************************************/ - ( - //Inputs - input CLK, - input [C_DIN_WIDTH-1:0] DIN, - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, - input RD_EN, - input RST, - input RST_FULL_GEN, - input RST_FULL_FF, - input SRST, - input WR_EN, - input INJECTDBITERR, - input INJECTSBITERR, - - //Outputs - output ALMOST_EMPTY, - output ALMOST_FULL, - output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT, - output [C_DOUT_WIDTH-1:0] DOUT, - output EMPTY, - output FULL, - output OVERFLOW, - output PROG_EMPTY, - output PROG_FULL, - output VALID, - output UNDERFLOW, - output WR_ACK, - output SBITERR, - output DBITERR - ); - - - /*************************************************************************** - * Parameters used as constants - **************************************************************************/ - //When RST is present, set FULL reset value to '1'. - //If core has no RST, make sure FULL powers-on as '0'. - //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not - //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. - // Therefore, during SRST, all the FULL flags reset to 0. - parameter C_HAS_FAST_FIFO = 0; - parameter C_FIFO_WR_DEPTH = C_WR_DEPTH; - parameter C_FIFO_RD_DEPTH = C_RD_DEPTH; - - /************************************************************************** - * FIFO Contents Tracking and Data Count Calculations - *************************************************************************/ - // Memory which will be used to simulate a FIFO - reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; - // Local parameters used to determine whether to inject ECC error or not - localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; - localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; - localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; - // Array that holds the error injection type (single/double bit error) on - // a specific write operation, which is returned on read to corrupt the - // output data. - reg [1:0] ecc_err[C_WR_DEPTH-1:0]; - - //The amount of data stored in the FIFO at any time is given - // by num_bits. - //num_bits is calculated by from the total words in the FIFO. - reg [31:0] num_bits; - - //The write pointer - tracks write operations - // (Works opposite to core: wr_ptr is a DOWN counter) - reg [31:0] wr_ptr; - - //The write pointer - tracks read operations - // (Works opposite to core: rd_ptr is a DOWN counter) - reg [31:0] rd_ptr; - - /************************** - * Data Count - *************************/ - //Amount of data stored in the FIFO scaled to read words - wire [31:0] num_read_words = num_bits/C_DOUT_WIDTH; - //num_read_words delayed 1 clock cycle - reg [31:0] num_read_words_q; - - //Amount of data stored in the FIFO scaled to write words - wire [31:0] num_write_words = num_bits/C_DIN_WIDTH; - //num_write_words delayed 1 clock cycle - reg [31:0] num_write_words_q; - - - /************************************************************************** - * Internal Registers and wires - *************************************************************************/ - - //Temporary signals used for calculating the model's outputs. These - //are only used in the assign statements immediately following wire, - //parameter, and function declarations. - wire underflow_i; - wire valid_i; - wire valid_out; - - //Ideal FIFO signals. These are the raw output of the behavioral model, - //which behaves like an ideal FIFO. - reg [1:0] err_type = 0; - reg [1:0] err_type_d1 = 0; - reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; - reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; - wire [C_DOUT_WIDTH-1:0] ideal_dout_out; - wire fwft_enabled; - reg ideal_wr_ack = 0; - reg ideal_valid = 0; - reg ideal_overflow = 0; - reg ideal_underflow = 0; - reg ideal_full = 0; - reg ideal_empty = 1; - reg ideal_almost_full = 0; - reg ideal_almost_empty = 1; - reg ideal_prog_full = 0; - reg ideal_prog_empty = 1; - - //Assorted reg values for delayed versions of signals - reg valid_d1 = 0; - reg prog_full_d = 0; - reg prog_empty_d = 1; - - wire rst_i; - wire srst_i; - - //Delayed version of RST - reg rst_q; - reg rst_qq; - - //user specified value for reseting the size of the fifo - reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; - - - /**************************************************************************** - * Function Declarations - ***************************************************************************/ - - /************************************************************************** - * write_fifo - * This task writes a word to the FIFO memory and updates the - * write pointer. - * FIFO size is relative to write domain. - ***************************************************************************/ - task write_fifo; - reg [1:0] corrupted_data; - begin - memory[wr_ptr] <= DIN; - // Store the type of error injection (double/single) on write - case (C_ERROR_INJECTION_TYPE) - 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; - 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; - 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; - default: ecc_err[wr_ptr] <= 0; - endcase - if (wr_ptr == 0) begin - wr_ptr <= C_WR_DEPTH - 1; - end else begin - wr_ptr <= wr_ptr - 1; - end - end - endtask // write_fifo - - /************************************************************************** - * read_fifo - * This task reads a word from the FIFO memory and updates the read - * pointer. It's output is the ideal_dout bus. - * FIFO size is relative to write domain. - ***************************************************************************/ - task read_fifo; - reg [C_DOUT_WIDTH-1:0] tmp_dout; - reg [1:0] tmp_ecc_err; - begin - tmp_dout = memory[rd_ptr][C_DOUT_WIDTH-1:0]; - // Retreive the error injection type. Based on the error injection type - // corrupt the output data. - tmp_ecc_err = ecc_err[rd_ptr]; - if (ENABLE_ERR_INJECTION) begin - if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error - if (C_DOUT_WIDTH == 1) - tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; - else if (C_DOUT_WIDTH == 2) - tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; - else - tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; - end else begin - tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; - end - err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; - end else begin - err_type <= 0; - end - ideal_dout <= tmp_dout; - - if (rd_ptr == 0) begin - rd_ptr <= C_RD_DEPTH - 1; - end else begin - rd_ptr <= rd_ptr - 1; - end - end - endtask - - /**************************************************************************** - * log2_val - * Returns the 'log2' value for the input value for the supported ratios - ***************************************************************************/ - function [31:0] log2_val; - input [31:0] binary_val; - - begin - if (binary_val == 8) begin - log2_val = 3; - end else if (binary_val == 4) begin - log2_val = 2; - end else begin - log2_val = 1; - end - end - endfunction - - /**************************************************************************** - * hexstr_conv - * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) - ***************************************************************************/ - function [C_DOUT_WIDTH-1:0] hexstr_conv; - input [(C_DOUT_WIDTH*8)-1:0] def_data; - - integer index,i,j; - reg [3:0] bin; - - begin - index = 0; - hexstr_conv = 'b0; - for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) - begin - case (def_data[7:0]) - 8'b00000000 : - begin - bin = 4'b0000; - i = -1; - end - 8'b00110000 : bin = 4'b0000; - 8'b00110001 : bin = 4'b0001; - 8'b00110010 : bin = 4'b0010; - 8'b00110011 : bin = 4'b0011; - 8'b00110100 : bin = 4'b0100; - 8'b00110101 : bin = 4'b0101; - 8'b00110110 : bin = 4'b0110; - 8'b00110111 : bin = 4'b0111; - 8'b00111000 : bin = 4'b1000; - 8'b00111001 : bin = 4'b1001; - 8'b01000001 : bin = 4'b1010; - 8'b01000010 : bin = 4'b1011; - 8'b01000011 : bin = 4'b1100; - 8'b01000100 : bin = 4'b1101; - 8'b01000101 : bin = 4'b1110; - 8'b01000110 : bin = 4'b1111; - 8'b01100001 : bin = 4'b1010; - 8'b01100010 : bin = 4'b1011; - 8'b01100011 : bin = 4'b1100; - 8'b01100100 : bin = 4'b1101; - 8'b01100101 : bin = 4'b1110; - 8'b01100110 : bin = 4'b1111; - default : - begin - bin = 4'bx; - end - endcase - for( j=0; j<4; j=j+1) - begin - if ((index*4)+j < C_DOUT_WIDTH) - begin - hexstr_conv[(index*4)+j] = bin[j]; - end - end - index = index + 1; - def_data = def_data >> 8; - end - end - endfunction - - - /************************************************************************* - * Initialize Signals for clean power-on simulation - *************************************************************************/ - initial begin - num_bits = 0; - num_read_words_q = 0; - num_write_words_q = 0; - rd_ptr = C_RD_DEPTH -1; - wr_ptr = C_WR_DEPTH -1; - dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); - ideal_dout = dout_reset_val; - err_type = 0; - ideal_wr_ack = 1'b0; - ideal_valid = 1'b0; - valid_d1 = 1'b0; - ideal_overflow = 1'b0; - ideal_underflow = 1'b0; - ideal_full = 1'b0; - ideal_empty = 1'b1; - ideal_almost_full = 1'b0; - ideal_almost_empty = 1'b1; - ideal_prog_full = 1'b0; - ideal_prog_empty = 1'b1; - prog_full_d = 1'b0; - prog_empty_d = 1'b1; - rst_q = 1'b0; - rst_qq = 1'b0; - end - - - /************************************************************************* - * Connect the module inputs and outputs to the internal signals of the - * behavioral model. - *************************************************************************/ - //Inputs - /* - wire CLK; - wire [C_DIN_WIDTH-1:0] DIN; - wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; - wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; - wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; - wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; - wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; - wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; - wire RD_EN; - wire RST; - wire WR_EN; - */ - - //Outputs - generate - if (C_HAS_ALMOST_EMPTY==1) begin : blockAE10 - assign ALMOST_EMPTY = ideal_almost_empty; - end - endgenerate - - generate - if (C_HAS_ALMOST_FULL==1) begin : blockAF10 - assign ALMOST_FULL = ideal_almost_full; - end - endgenerate - - //Dout may change behavior based on latency - assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? - 1: 0; - assign ideal_dout_out= ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && - (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? - ideal_dout_d1: ideal_dout; - assign DOUT = ideal_dout_out; - - // Assign SBITERR and DBITERR based on latency - assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && - ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && - (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? - err_type_d1[0]: err_type[0]; - assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && - ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && - (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? - err_type_d1[1]: err_type[1]; - - assign EMPTY = ideal_empty; - assign FULL = ideal_full; - - //Overflow may be active-low - generate - if (C_HAS_OVERFLOW==1) begin : blockOF10 - assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; - end - endgenerate - - assign PROG_EMPTY = ideal_prog_empty; - assign PROG_FULL = ideal_prog_full; - - //Valid may change behavior based on latency or active-low - generate - if (C_HAS_VALID==1) begin : blockVL10 - assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; - assign valid_out = (C_PRELOAD_LATENCY==2 && - (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? - valid_d1: valid_i; - assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; - end - endgenerate - - //Trim data count differently depending on set widths - generate - if ((C_HAS_DATA_COUNT == 1) && - (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH)) begin : blockDC1 - always @(num_read_words) - DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH:0]; - end else if (C_HAS_DATA_COUNT == 1) begin : blockDC2 - always @(num_read_words) - DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; - end //if - endgenerate - - //Underflow may change behavior based on latency or active-low - generate - if (C_HAS_UNDERFLOW==1) begin : blockUF10 - assign underflow_i = ideal_underflow; - assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; - end - endgenerate - - - //Write acknowledge may be active low - generate - if (C_HAS_WR_ACK==1) begin : blockWK10 - assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; - end - endgenerate - - - /***************************************************************************** - * Internal reset logic - ****************************************************************************/ - assign srst_i = C_HAS_SRST ? SRST : 0; - assign rst_i = C_HAS_RST ? RST : 0; - - /************************************************************************** - * Assorted registers for delayed versions of signals - **************************************************************************/ - //Capture delayed version of valid - generate - if (C_HAS_VALID==1) begin : blockVL20 - always @(posedge CLK or posedge rst_i) begin - if (rst_i == 1'b1) begin - valid_d1 <= #`TCQ 1'b0; - end else begin - if (srst_i) begin - valid_d1 <= #`TCQ 1'b0; - end else begin - valid_d1 <= #`TCQ valid_i; - end - end - end // always @ (posedge CLK or posedge rst_i) - end - endgenerate - - - // block memory has a synchronous reset - always @(posedge CLK) begin : gen_fifo_blkmemdout_emb - // make it consistent with the core. - if (rst_i || srst_i) begin - // BRAM resets synchronously - if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin - ideal_dout_d1 <= #`TCQ dout_reset_val; - end - end - end //always - - reg ram_rd_en_d1 = 1'b0; - //Capture delayed version of dout - always @(posedge CLK or posedge rst_i) begin - if (rst_i == 1'b1) begin - // Reset err_type only if ECC is not selected - if (C_USE_ECC == 0) - err_type_d1 <= #`TCQ 0; - - // DRAM and SRAM reset asynchronously - if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) - ideal_dout_d1 <= #`TCQ dout_reset_val; - - ram_rd_en_d1 <= #`TCQ 1'b0; - end else begin - ram_rd_en_d1 <= #`TCQ RD_EN & !EMPTY; - if (srst_i) begin - ram_rd_en_d1 <= #`TCQ 1'b0; - // Reset err_type only if ECC is not selected - if (C_USE_ECC == 0) - err_type_d1 <= #`TCQ 0; - // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above - if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) - ideal_dout_d1 <= #`TCQ dout_reset_val; - end else if (ram_rd_en_d1) begin - ideal_dout_d1 <= #`TCQ ideal_dout; - err_type_d1 <= #`TCQ err_type; - end - end - end - - /************************************************************************** - * Overflow and Underflow Flag calculation - * (handled separately because they don't support rst) - **************************************************************************/ - generate - if (C_HAS_OVERFLOW==1) begin : blockOF20 - always @(posedge CLK) begin - ideal_overflow <= #`TCQ WR_EN & ideal_full; - end - end - endgenerate - - generate - if (C_HAS_UNDERFLOW==1) begin : blockUF20 - always @(posedge CLK) begin - ideal_underflow <= #`TCQ ideal_empty & RD_EN; - end - end - endgenerate - - /************************************************************************* - * Write and Read Logic - ************************************************************************/ - always @(posedge CLK or posedge rst_i) - begin : gen_wr_ack_resp - - //Register reset - rst_q <= #`TCQ rst_i; - rst_qq <= #`TCQ rst_q; - - end // block: gen_wr_ack_resp - - // block memory has a synchronous reset - always @(posedge CLK) begin : gen_fifo_blkmemdout - //Changed the latency of during async reset to '1' instead of '2' to - // make it consistent with the core. - if (rst_i || rst_q || srst_i) begin - // Reset err_type only if ECC is not selected - if (C_USE_ECC == 0 && C_MEMORY_TYPE == 1) - err_type <= #`TCQ 0; - /******Initialize Read Domain Signals*********************************/ - if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin - ideal_dout <= #`TCQ dout_reset_val; - end - end - end //always - - // FULL_FLAG_RESET value given for SRST as well. - reg srst_i_d1 = 0; - reg srst_i_d2 = 0; - always @(posedge CLK or posedge RST_FULL_FF) begin : gen_fifo - - /****** Reset fifo - Asynchronous Reset**********************************/ - //Changed the latency of during async reset to '1' instead of '2' to - // make it consistent with the core. - if (RST_FULL_FF) begin //v3.2 - /******Initialize Generic FIFO constructs*****************************/ - num_bits <= #`TCQ 0; - wr_ptr <= #`TCQ C_WR_DEPTH - 1; - rd_ptr <= #`TCQ C_RD_DEPTH - 1; - num_read_words_q <= #`TCQ 0; - num_write_words_q <= #`TCQ 0; - // Reset err_type only if ECC is not selected - if (C_USE_ECC == 0 && C_MEMORY_TYPE != 1) - err_type <= #`TCQ 0; - - - /******Initialize Write Domain Signals********************************/ - ideal_wr_ack <= #`TCQ 0; - ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; - ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; - - /******Initialize Read Domain Signals*********************************/ - // DRAM and SRAM reset asynchronously - if (C_USE_DOUT_RST == 1 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3)) begin - ideal_dout <= #`TCQ dout_reset_val; - end - ideal_valid <= #`TCQ 1'b0; - ideal_empty <= #`TCQ 1'b1; - ideal_almost_empty <= #`TCQ 1'b1; - - end else begin - // Register SRST twice to be consistant with RST behavior - srst_i_d1 <= #`TCQ srst_i; - srst_i_d2 <= #`TCQ srst_i_d1; - if (srst_i) begin - // SRST is available only for Sync BRAM, DRAM and SRAM. - if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) begin - /******Initialize Generic FIFO constructs***********************/ - num_bits <= #`TCQ 0; - wr_ptr <= #`TCQ C_WR_DEPTH - 1; - rd_ptr <= #`TCQ C_RD_DEPTH - 1; - num_read_words_q <= #`TCQ 0; - num_write_words_q <= #`TCQ 0; - // Reset err_type only if ECC is not selected - if (C_USE_ECC == 0) - err_type <= #`TCQ 0; - - /******Initialize Write Domain Signals**************************/ - ideal_wr_ack <= #`TCQ 0; - ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; - ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; - - /******Initialize Read Domain Signals***************************/ - //Reset DOUT of Sync DRAM/Shift RAM. Sync BRAM DOUT was reset in the - // above always block. - if (C_USE_DOUT_RST == 1 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3)) begin - ideal_dout <= #`TCQ dout_reset_val; - end - ideal_valid <= #`TCQ 1'b0; - ideal_empty <= #`TCQ 1'b1; - ideal_almost_empty <= #`TCQ 1'b1; - end - - end else if ((srst_i_d1 || srst_i_d2) && (C_FULL_FLAGS_RST_VAL == 1)) begin //Hold full flag reset value set during RST/SRST - ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; - ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; - end else begin //normal operating conditions - /********************************************************************/ - // Synchronous FIFO Condition #1 : Writing and not reading - /********************************************************************/ - ideal_valid <= #`TCQ 1'b0; - if (WR_EN & ~RD_EN) begin - - /*********************************/ - //If the FIFO is full, do NOT perform the write, - // update flags accordingly - /*********************************/ - if (num_write_words >= C_FIFO_WR_DEPTH) begin - ideal_wr_ack <= #`TCQ 0; - - //still full - ideal_full <= #`TCQ 1'b1; - ideal_almost_full <= #`TCQ 1'b1; - - //write unsuccessful - do not change contents - - // no read attempted - ideal_valid <= #`TCQ 1'b0; - - //Not near empty - ideal_empty <= #`TCQ 1'b0; - ideal_almost_empty <= #`TCQ 1'b0; - - - /*********************************/ - //If the FIFO is reporting FULL - // (Startup condition) - /*********************************/ - end else if ((num_write_words < C_FIFO_WR_DEPTH) && (ideal_full == 1'b1)) begin - ideal_wr_ack <= #`TCQ 0; - - //still full - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b0; - - //write unsuccessful - do not change contents - - // no read attempted - ideal_valid <= #`TCQ 1'b0; - - //FIFO EMPTY in this state can not be determined - //ideal_empty <= 1'b0; - //ideal_almost_empty <= 1'b0; - - - /*********************************/ - //If the FIFO is one from full - /*********************************/ - end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin - //good write - ideal_wr_ack <= #`TCQ 1; - - //FIFO is one from FULL and going FULL - ideal_full <= #`TCQ 1'b1; - ideal_almost_full <= #`TCQ 1'b1; - - //Add input data - write_fifo; - - // no read attempted - ideal_valid <= #`TCQ 1'b0; - - //Not near empty - ideal_empty <= #`TCQ 1'b0; - ideal_almost_empty <= #`TCQ 1'b0; - - num_bits <= num_bits + C_DIN_WIDTH; - - /*********************************/ - //If the FIFO is 2 from full - /*********************************/ - end else if (num_write_words == C_FIFO_WR_DEPTH-2) begin - //good write - ideal_wr_ack <= #`TCQ 1; - - //2 from full, and writing, so set almost_full - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b1; - - //Add input data - write_fifo; - - //no read attempted - ideal_valid <= #`TCQ 1'b0; - - //Not near empty - ideal_empty <= #`TCQ 1'b0; - ideal_almost_empty <= #`TCQ 1'b0; - - num_bits <= #`TCQ num_bits + C_DIN_WIDTH; - - /*********************************/ - //If the FIFO is ALMOST EMPTY - /*********************************/ - end else if (num_read_words == 1) begin - //good write - ideal_wr_ack <= #`TCQ 1; - - //Not near FULL - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b0; - - //Add input data - write_fifo; - - // no read attempted - ideal_valid <= #`TCQ 1'b0; - - //Leaving ALMOST_EMPTY - ideal_empty <= #`TCQ 1'b0; - ideal_almost_empty <= #`TCQ 1'b0; - - num_bits <= #`TCQ num_bits + C_DIN_WIDTH; - - /*********************************/ - //If the FIFO is EMPTY - /*********************************/ - end else if (num_read_words == 0) begin - // good write - ideal_wr_ack <= #`TCQ 1; - - //Not near FULL - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b0; - - //Add input data - write_fifo; - - // no read attempted - ideal_valid <= #`TCQ 1'b0; - - //Leaving EMPTY (still ALMOST_EMPTY) - ideal_empty <= #`TCQ 1'b0; - ideal_almost_empty <= #`TCQ 1'b1; - - num_bits <= #`TCQ num_bits + C_DIN_WIDTH; - - /*********************************/ - //If the FIFO is not near EMPTY or FULL - /*********************************/ - end else begin - // good write - ideal_wr_ack <= #`TCQ 1; - - //Not near FULL - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b0; - - //Add input data - write_fifo; - - // no read attempted - ideal_valid <= #`TCQ 1'b0; - - //Not near EMPTY - ideal_empty <= #`TCQ 1'b0; - ideal_almost_empty <= #`TCQ 1'b0; - - num_bits <= #`TCQ num_bits + C_DIN_WIDTH; - - end // average case - - - /******************************************************************/ - // Synchronous FIFO Condition #2 : Reading and not writing - /******************************************************************/ - end else if (~WR_EN & RD_EN) begin - - /*********************************/ - //If the FIFO is EMPTY - /*********************************/ - if ((num_read_words == 0) || (ideal_empty == 1'b1)) begin - //no write attemped - ideal_wr_ack <= #`TCQ 0; - - //FIFO is not near FULL - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b0; - - //Read will fail - ideal_valid <= #`TCQ 1'b0; - - //FIFO is still empty - ideal_empty <= #`TCQ 1'b1; - ideal_almost_empty <= #`TCQ 1'b1; - - //No read - - /*********************************/ - //If the FIFO is ALMOST EMPTY - /*********************************/ - end else if (num_read_words == 1) begin - //no write attempted - ideal_wr_ack <= #`TCQ 0; - - //FIFO is not near FULL - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b0; - - //Read successful - ideal_valid <= #`TCQ 1'b1; - - //This read will make FIFO go empty - ideal_empty <= #`TCQ 1'b1; - ideal_almost_empty <= #`TCQ 1'b1; - - //Get the data from the FIFO - read_fifo; - num_bits <= #`TCQ num_bits - C_DIN_WIDTH; - - - /*********************************/ - //If the FIFO is 2 from EMPTY - /*********************************/ - end else if (num_read_words == 2) begin - - //no write attempted - ideal_wr_ack <= #`TCQ 0; - - //FIFO is not near FULL - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b0; - - //Read successful - ideal_valid <= #`TCQ 1'b1; - - //FIFO is going ALMOST_EMPTY - ideal_empty <= #`TCQ 1'b0; - ideal_almost_empty <= #`TCQ 1'b1; - - //Get the data from the FIFO - read_fifo; - num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; - - - - /*********************************/ - //If the FIFO is one from full - /*********************************/ - end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin - - //no write attempted - ideal_wr_ack <= #`TCQ 0; - - //FIFO is leaving ALMOST FULL - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b0; - - //Read successful - ideal_valid <= #`TCQ 1'b1; - - //Not near empty - ideal_empty <= #`TCQ 1'b0; - ideal_almost_empty <= #`TCQ 1'b0; - - //Read from the FIFO - read_fifo; - num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; - - - /*********************************/ - // FIFO is FULL - /*********************************/ - end else if (num_write_words >= C_FIFO_WR_DEPTH) - begin - //no write attempted - ideal_wr_ack <= #`TCQ 0; - - //FIFO is leaving FULL, but is still ALMOST_FULL - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b1; - - //Read successful - ideal_valid <= #`TCQ 1'b1; - - //Not near empty - ideal_empty <= #`TCQ 1'b0; - ideal_almost_empty <= #`TCQ 1'b0; - - //Read from the FIFO - read_fifo; - num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; - - /*********************************/ - //If the FIFO is not near EMPTY or FULL - /*********************************/ - end else begin - //no write attemped - ideal_wr_ack <= #`TCQ 0; - - //Not near empty - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b0; - - //Read successful - ideal_valid <= #`TCQ 1'b1; - - //Not near empty - ideal_empty <= #`TCQ 1'b0; - ideal_almost_empty <= #`TCQ 1'b0; - - //Read from the FIFO - read_fifo; - num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; - - - end // average read - - - /******************************************************************/ - // Synchronous FIFO Condition #3 : Reading and writing - /******************************************************************/ - end else if (WR_EN & RD_EN) begin - - /*********************************/ - // FIFO is FULL - /*********************************/ - if (num_write_words >= C_FIFO_WR_DEPTH) begin - - ideal_wr_ack <= #`TCQ 0; - - //Read will be successful, so FIFO will leave FULL - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b1; - - //Read successful - ideal_valid <= #`TCQ 1'b1; - - //Not near empty - ideal_empty <= #`TCQ 1'b0; - ideal_almost_empty <= #`TCQ 1'b0; - - //Read from the FIFO - read_fifo; - num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; - - - /*********************************/ - // FIFO is reporting FULL, but it is empty - // (This is a special case, when coming out of RST - /*********************************/ - end else if ((num_write_words == 0) && (ideal_full == 1'b1)) begin - - ideal_wr_ack <= #`TCQ 0; - - //Read will be successful, so FIFO will leave FULL - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b0; - - //Read unsuccessful - ideal_valid <= #`TCQ 1'b0; - - //Report empty condition - ideal_empty <= #`TCQ 1'b1; - ideal_almost_empty <= #`TCQ 1'b1; - - //Do not read from empty FIFO - // Read from the FIFO - - - /*********************************/ - //If the FIFO is one from full - /*********************************/ - end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin - - //Write successful - ideal_wr_ack <= #`TCQ 1; - - //FIFO will remain ALMOST_FULL - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b1; - - // put the data into the FIFO - write_fifo; - - //Read successful - ideal_valid <= #`TCQ 1'b1; - - //Not near empty - ideal_empty <= #`TCQ 1'b0; - ideal_almost_empty <= #`TCQ 1'b0; - - //Read from the FIFO - read_fifo; - num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; - - /*********************************/ - //If the FIFO is ALMOST EMPTY - /*********************************/ - end else if (num_read_words == 1) begin - - //Write successful - ideal_wr_ack <= #`TCQ 1; - - // Not near FULL - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b0; - - // put the data into the FIFO - write_fifo; - - //Read successful - ideal_valid <= #`TCQ 1'b1; - - //FIFO will stay ALMOST_EMPTY - ideal_empty <= #`TCQ 1'b0; - ideal_almost_empty <= #`TCQ 1'b1; - - //Read from the FIFO - read_fifo; - num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; - - - /*********************************/ - //If the FIFO is EMPTY - /*********************************/ - end else if (num_read_words == 0) begin - - //Write successful - ideal_wr_ack <= #`TCQ 1; - - // Not near FULL - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b0; - - // put the data into the FIFO - write_fifo; - - //Read will fail - ideal_valid <= #`TCQ 1'b0; - - //FIFO will leave EMPTY - ideal_empty <= #`TCQ 1'b0; - ideal_almost_empty <= #`TCQ 1'b1; - - // No read - num_bits <= #`TCQ num_bits + C_DIN_WIDTH; - - - /*********************************/ - //If the FIFO is not near EMPTY or FULL - /*********************************/ - end else begin - - //Write successful - ideal_wr_ack <= #`TCQ 1; - - // Not near FULL - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b0; - - // put the data into the FIFO - write_fifo; - - //Read successful - ideal_valid <= #`TCQ 1'b1; - - // Not near EMPTY - ideal_empty <= #`TCQ 1'b0; - ideal_almost_empty <= #`TCQ 1'b0; - - //Read from the FIFO - read_fifo; - num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; - - end // average case - - /******************************************************************/ - // Synchronous FIFO Condition #4 : Not reading or writing - /******************************************************************/ - end else begin - - /*********************************/ - // FIFO is FULL - /*********************************/ - if (num_write_words >= C_FIFO_WR_DEPTH) begin - - //No write - ideal_wr_ack <= #`TCQ 0; - ideal_full <= #`TCQ 1'b1; - ideal_almost_full <= #`TCQ 1'b1; - - //No read - ideal_valid <= #`TCQ 1'b0; - ideal_empty <= #`TCQ 1'b0; - ideal_almost_empty <= #`TCQ 1'b0; - - //No change to memory - - /*********************************/ - //If the FIFO is one from full - /*********************************/ - end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin - - //No write - ideal_wr_ack <= #`TCQ 0; - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b1; - - //No read - ideal_valid <= #`TCQ 1'b0; - ideal_empty <= #`TCQ 1'b0; - ideal_almost_empty <= #`TCQ 1'b0; - - //No change to memory - - /*********************************/ - //If the FIFO is ALMOST EMPTY - /*********************************/ - end else if (num_read_words == 1) begin - //No write - ideal_wr_ack <= #`TCQ 0; - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b0; - - //No read - ideal_valid <= #`TCQ 1'b0; - ideal_empty <= #`TCQ 1'b0; - ideal_almost_empty <= #`TCQ 1'b1; - - //No change to memory - - end // almost empty - - - /*********************************/ - //If the FIFO is EMPTY - /*********************************/ - else if (num_read_words == 0) - begin - //No write - ideal_wr_ack <= #`TCQ 0; - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b0; - - //No read - ideal_valid <= #`TCQ 1'b0; - ideal_empty <= #`TCQ 1'b1; - ideal_almost_empty <= #`TCQ 1'b1; - - //No change to memory - - /*********************************/ - //If the FIFO is not near EMPTY or FULL - /*********************************/ - end else begin - - //No write - ideal_wr_ack <= #`TCQ 0; - ideal_full <= #`TCQ 1'b0; - ideal_almost_full <= #`TCQ 1'b0; - - //No read - ideal_valid <= #`TCQ 1'b0; - ideal_empty <= #`TCQ 1'b0; - ideal_almost_empty <= #`TCQ 1'b0; - - //No change to memory - - end // average case - - end // neither reading or writing - - num_read_words_q <= #`TCQ num_read_words; - num_write_words_q <= #`TCQ num_write_words; - - end //normal operating conditions - end - - end // block: gen_fifo - - - always @(posedge CLK or posedge RST_FULL_FF) begin : gen_fifo_p - - /****** Reset fifo - Async Reset****************************************/ - //The latency of de-assertion of the flags is reduced by 1 to be - // consistent with the core. - if (RST_FULL_FF) begin - ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; - ideal_prog_empty <= #`TCQ 1'b1; - prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; - prog_empty_d <= #`TCQ 1'b1; - - end else begin - if (srst_i) begin - //SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. - if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) begin - ideal_prog_empty <= #`TCQ 1'b1; - prog_empty_d <= #`TCQ 1'b1; - ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; - prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; - end - end else if ((srst_i_d1 || srst_i_d2) && (C_FULL_FLAGS_RST_VAL == 1)) begin - ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; - prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; - end else begin - - /*************************************************************** - * Programmable FULL flags - ****************************************************************/ - //calculation for standard fifo and latency =2 - if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin - //Single constant threshold - if (C_PROG_FULL_TYPE == 1) begin - if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1) - && WR_EN && !RD_EN) begin - prog_full_d <= #`TCQ 1'b1; - end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL) - && RD_EN && !WR_EN) || (RST_FULL_GEN)) begin - prog_full_d <= #`TCQ 1'b0; - end - - //Dual constant thresholds - end else if (C_PROG_FULL_TYPE == 2) begin - if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1) - && WR_EN && !RD_EN) begin - prog_full_d <= #`TCQ 1'b1; - end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL) - && RD_EN && !WR_EN) begin - prog_full_d <= #`TCQ 1'b0; - end - - //Single input threshold - end else if (C_PROG_FULL_TYPE == 3) begin - if ((num_write_words == PROG_FULL_THRESH-1) - && WR_EN && !RD_EN) begin - prog_full_d <= #`TCQ 1'b1; - end else if ((num_write_words == PROG_FULL_THRESH) - && !WR_EN && RD_EN) begin - prog_full_d <= #`TCQ 1'b0; - end else if (num_write_words >= PROG_FULL_THRESH) begin - prog_full_d <= #`TCQ 1'b1; - end else if (num_write_words < PROG_FULL_THRESH) begin - prog_full_d <= #`TCQ 1'b0; - end - - //Dual input thresholds - end else begin - if ((num_write_words == PROG_FULL_THRESH_ASSERT-1) - && WR_EN && !RD_EN) begin - prog_full_d <= #`TCQ 1'b1; - end else if ((num_write_words == PROG_FULL_THRESH_NEGATE) - && !WR_EN && RD_EN)begin - prog_full_d <= #`TCQ 1'b0; - end else if (num_write_words >= PROG_FULL_THRESH_ASSERT) begin - prog_full_d <= #`TCQ 1'b1; - end else if (num_write_words < PROG_FULL_THRESH_NEGATE) begin - prog_full_d <= #`TCQ 1'b0; - end - end - end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) - - - //calculation for FWFT fifo - if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - if (C_PROG_FULL_TYPE == 1) begin - if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) - && WR_EN && !RD_EN) begin - prog_full_d <= #`TCQ 1'b1; - end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL - 2) - && RD_EN && !WR_EN) || (RST_FULL_GEN)) begin - prog_full_d <= #`TCQ 1'b0; - end - - //Dual constant thresholds - end else if (C_PROG_FULL_TYPE == 2) begin - if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) - && WR_EN && !RD_EN) begin - prog_full_d <= #`TCQ 1'b1; - end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL - 2) - && RD_EN && !WR_EN) begin - prog_full_d <= #`TCQ 1'b0; - end - - //Single input threshold - end else if (C_PROG_FULL_TYPE == 3) begin - if ((num_write_words == PROG_FULL_THRESH-1 - 2) - && WR_EN && !RD_EN) begin - prog_full_d <= #`TCQ 1'b1; - end else if ((num_write_words == PROG_FULL_THRESH - 2) - && !WR_EN && RD_EN) begin - prog_full_d <= #`TCQ 1'b0; - end else if (num_write_words >= PROG_FULL_THRESH - 2) begin - prog_full_d <= #`TCQ 1'b1; - end else if (num_write_words < PROG_FULL_THRESH - 2) begin - prog_full_d <= #`TCQ 1'b0; - end - - //Dual input thresholds - end else begin - if ((num_write_words == PROG_FULL_THRESH_ASSERT-1 - 2) - && WR_EN && !RD_EN) begin - prog_full_d <= #`TCQ 1'b1; - end else if ((num_write_words == PROG_FULL_THRESH_NEGATE - 2) - && !WR_EN && RD_EN)begin - prog_full_d <= #`TCQ 1'b0; - end else if (num_write_words >= PROG_FULL_THRESH_ASSERT - 2) begin - prog_full_d <= #`TCQ 1'b1; - end else if (num_write_words < PROG_FULL_THRESH_NEGATE - 2) begin - prog_full_d <= #`TCQ 1'b0; - end - end - end // (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) - - /***************************************************************** - * Programmable EMPTY flags - ****************************************************************/ - //calculation for standard fifo and latency = 2 - if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin - //Single constant threshold - if (C_PROG_EMPTY_TYPE == 1) begin - if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) - && RD_EN && !WR_EN) begin - prog_empty_d <= #`TCQ 1'b1; - end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL) - && WR_EN && !RD_EN) begin - prog_empty_d <= #`TCQ 1'b0; - end - //Dual constant thresholds - end else if (C_PROG_EMPTY_TYPE == 2) begin - if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) - && RD_EN && !WR_EN) begin - prog_empty_d <= #`TCQ 1'b1; - end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL) - && !RD_EN && WR_EN) begin - prog_empty_d <= #`TCQ 1'b0; - end - - //Single input threshold - end else if (C_PROG_EMPTY_TYPE == 3) begin - if ((num_read_words == PROG_EMPTY_THRESH+1) - && RD_EN && !WR_EN) begin - prog_empty_d <= #`TCQ 1'b1; - end else if ((num_read_words == PROG_EMPTY_THRESH) - && !RD_EN && WR_EN) begin - prog_empty_d <= #`TCQ 1'b0; - end else if (num_read_words <= PROG_EMPTY_THRESH) begin - prog_empty_d <= #`TCQ 1'b1; - end else if (num_read_words > PROG_EMPTY_THRESH)begin - prog_empty_d <= #`TCQ 1'b0; - end - - //Dual input thresholds - end else begin - if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin - prog_empty_d <= #`TCQ 1'b1; - end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1) - && RD_EN && !WR_EN) begin - prog_empty_d <= #`TCQ 1'b1; - end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE)begin - prog_empty_d <= #`TCQ 1'b0; - end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE) - && !RD_EN && WR_EN) begin - prog_empty_d <= #`TCQ 1'b0; - end - end - end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) - - //calculation for FWFT fifo - if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - //Single constant threshold - if (C_PROG_EMPTY_TYPE == 1) begin - if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) - && RD_EN && !WR_EN) begin - prog_empty_d <= #`TCQ 1'b1; - end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL - 2) - && WR_EN && !RD_EN) begin - prog_empty_d <= #`TCQ 1'b0; - end - //Dual constant thresholds - end else if (C_PROG_EMPTY_TYPE == 2) begin - if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) - && RD_EN && !WR_EN) begin - prog_empty_d <= #`TCQ 1'b1; - end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL - 2) - && !RD_EN && WR_EN) begin - prog_empty_d <= #`TCQ 1'b0; - end - - //Single input threshold - end else if (C_PROG_EMPTY_TYPE == 3) begin - if ((num_read_words == PROG_EMPTY_THRESH+1 - 2) - && RD_EN && !WR_EN) begin - prog_empty_d <= #`TCQ 1'b1; - end else if ((num_read_words == PROG_EMPTY_THRESH - 2) - && !RD_EN && WR_EN) begin - prog_empty_d <= #`TCQ 1'b0; - end else if (num_read_words <= PROG_EMPTY_THRESH - 2) begin - prog_empty_d <= #`TCQ 1'b1; - end else if (num_read_words > PROG_EMPTY_THRESH - 2)begin - prog_empty_d <= #`TCQ 1'b0; - end - - //Dual input thresholds - end else begin - if (num_read_words <= PROG_EMPTY_THRESH_ASSERT - 2) begin - prog_empty_d <= #`TCQ 1'b1; - end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1 - 2) - && RD_EN && !WR_EN) begin - prog_empty_d <= #`TCQ 1'b1; - end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE - 2)begin - prog_empty_d <= #`TCQ 1'b0; - end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE - 2) - && !RD_EN && WR_EN) begin - prog_empty_d <= #`TCQ 1'b0; - end - end - end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) - - ideal_prog_empty <= prog_empty_d; - if (RST_FULL_GEN) begin - ideal_prog_full <= #`TCQ 1'b0; - prog_full_d <= #`TCQ 1'b0; - end else begin - ideal_prog_full <= #`TCQ prog_full_d; - end - - end //if (srst_i) begin - end //if (rst_i) begin - end //always @(posedge CLK or posedge rst_i) begin : gen_fifo_p -endmodule // fifo_generator_v6_1_bhv_ver_ss - - - -/************************************************************************** - * First-Word Fall-Through module (preload 0) - **************************************************************************/ -module fifo_generator_v6_1_bhv_ver_preload0 - ( - RD_CLK, - RD_RST, - SRST, - RD_EN, - FIFOEMPTY, - FIFODATA, - FIFOSBITERR, - FIFODBITERR, - USERDATA, - USERVALID, - USERUNDERFLOW, - USEREMPTY, - USERALMOSTEMPTY, - RAMVALID, - FIFORDEN, - USERSBITERR, - USERDBITERR - ); - - parameter C_DOUT_RST_VAL = ""; - parameter C_DOUT_WIDTH = 8; - parameter C_HAS_RST = 0; - parameter C_ENABLE_RST_SYNC = 0; - parameter C_HAS_SRST = 0; - parameter C_USE_DOUT_RST = 0; - parameter C_USE_ECC = 0; - parameter C_USERVALID_LOW = 0; - parameter C_USERUNDERFLOW_LOW = 0; - parameter C_MEMORY_TYPE = 0; - - //Inputs - input RD_CLK; - input RD_RST; - input SRST; - input RD_EN; - input FIFOEMPTY; - input [C_DOUT_WIDTH-1:0] FIFODATA; - input FIFOSBITERR; - input FIFODBITERR; - - //Outputs - output [C_DOUT_WIDTH-1:0] USERDATA; - output USERVALID; - output USERUNDERFLOW; - output USEREMPTY; - output USERALMOSTEMPTY; - output RAMVALID; - output FIFORDEN; - output USERSBITERR; - output USERDBITERR; - - //Inputs - wire RD_CLK; - wire RD_RST; - wire RD_EN; - wire FIFOEMPTY; - wire [C_DOUT_WIDTH-1:0] FIFODATA; - wire FIFOSBITERR; - wire FIFODBITERR; - - //Outputs - reg [C_DOUT_WIDTH-1:0] USERDATA; - wire USERVALID; - wire USERUNDERFLOW; - wire USEREMPTY; - wire USERALMOSTEMPTY; - wire RAMVALID; - wire FIFORDEN; - reg USERSBITERR; - reg USERDBITERR; - - //Internal signals - wire preloadstage1; - wire preloadstage2; - reg ram_valid_i; - reg read_data_valid_i; - wire ram_regout_en; - wire ram_rd_en; - reg empty_i = 1'b1; - reg empty_q = 1'b1; - reg rd_en_q = 1'b0; - reg almost_empty_i = 1'b1; - reg almost_empty_q = 1'b1; - wire rd_rst_i; - wire srst_i; - - -/************************************************************************* -* FUNCTIONS -*************************************************************************/ - - /************************************************************************* - * hexstr_conv - * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) - ***********************************************************************/ - function [C_DOUT_WIDTH-1:0] hexstr_conv; - input [(C_DOUT_WIDTH*8)-1:0] def_data; - - integer index,i,j; - reg [3:0] bin; - - begin - index = 0; - hexstr_conv = 'b0; - for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) - begin - case (def_data[7:0]) - 8'b00000000 : - begin - bin = 4'b0000; - i = -1; - end - 8'b00110000 : bin = 4'b0000; - 8'b00110001 : bin = 4'b0001; - 8'b00110010 : bin = 4'b0010; - 8'b00110011 : bin = 4'b0011; - 8'b00110100 : bin = 4'b0100; - 8'b00110101 : bin = 4'b0101; - 8'b00110110 : bin = 4'b0110; - 8'b00110111 : bin = 4'b0111; - 8'b00111000 : bin = 4'b1000; - 8'b00111001 : bin = 4'b1001; - 8'b01000001 : bin = 4'b1010; - 8'b01000010 : bin = 4'b1011; - 8'b01000011 : bin = 4'b1100; - 8'b01000100 : bin = 4'b1101; - 8'b01000101 : bin = 4'b1110; - 8'b01000110 : bin = 4'b1111; - 8'b01100001 : bin = 4'b1010; - 8'b01100010 : bin = 4'b1011; - 8'b01100011 : bin = 4'b1100; - 8'b01100100 : bin = 4'b1101; - 8'b01100101 : bin = 4'b1110; - 8'b01100110 : bin = 4'b1111; - default : - begin - bin = 4'bx; - end - endcase - for( j=0; j<4; j=j+1) - begin - if ((index*4)+j < C_DOUT_WIDTH) - begin - hexstr_conv[(index*4)+j] = bin[j]; - end - end - index = index + 1; - def_data = def_data >> 8; - end - end - endfunction - - - //************************************************************************* - // Set power-on states for regs - //************************************************************************* - initial begin - ram_valid_i = 1'b0; - read_data_valid_i = 1'b0; - USERDATA = hexstr_conv(C_DOUT_RST_VAL); - USERSBITERR = 1'b0; - USERDBITERR = 1'b0; - end //initial - - //*************************************************************************** - // connect up optional reset - //*************************************************************************** - assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0; - assign srst_i = C_HAS_SRST ? SRST : 0; - - - //*************************************************************************** - // preloadstage2 indicates that stage2 needs to be updated. This is true - // whenever read_data_valid is false, and RAM_valid is true. - //*************************************************************************** - assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN); - - //*************************************************************************** - // preloadstage1 indicates that stage1 needs to be updated. This is true - // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is - // false (indicating that Stage1 needs updating), or preloadstage2 is active - // (indicating that Stage2 is going to update, so Stage1, therefore, must - // also be updated to keep it valid. - //*************************************************************************** - assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); - - //*************************************************************************** - // Calculate RAM_REGOUT_EN - // The output registers are controlled by the ram_regout_en signal. - // These registers should be updated either when the output in Stage2 is - // invalid (preloadstage2), OR when the user is reading, in which case the - // Stage2 value will go invalid unless it is replenished. - //*************************************************************************** - assign ram_regout_en = preloadstage2; - - //*************************************************************************** - // Calculate RAM_RD_EN - // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to - // update the value in Stage1. - // One case when this happens is when preloadstage1=true, which indicates - // that the data in Stage1 or Stage2 is invalid, and needs to automatically - // be updated. - // The other case is when the user is reading from the FIFO, which - // guarantees that Stage1 or Stage2 will be invalid on the next clock - // cycle, unless it is replinished by data from the memory. So, as long - // as the RAM has data in it, a read of the RAM should occur. - //*************************************************************************** - assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; - - //*************************************************************************** - // Calculate RAMVALID_P0_OUT - // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. - // - // If the RAM is being read from on this clock cycle (ram_rd_en=1), then - // RAMVALID_P0_OUT is certainly going to be true. - // If the RAM is not being read from, but the output registers are being - // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, - // therefore causing RAMVALID_P0_OUT to be false. - // Otherwise, RAMVALID_P0_OUT will remain unchanged. - //*************************************************************************** - // PROCESS regout_valid - always @ (posedge RD_CLK or posedge rd_rst_i) begin - if (rd_rst_i) begin - // asynchronous reset (active high) - ram_valid_i <= #`TCQ 1'b0; - end else begin - if (srst_i) begin - // synchronous reset (active high) - ram_valid_i <= #`TCQ 1'b0; - end else begin - if (ram_rd_en == 1'b1) begin - ram_valid_i <= #`TCQ 1'b1; - end else begin - if (ram_regout_en == 1'b1) - ram_valid_i <= #`TCQ 1'b0; - else - ram_valid_i <= #`TCQ ram_valid_i; - end - end //srst_i - end //rd_rst_i - end //always - - //*************************************************************************** - // Calculate READ_DATA_VALID - // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. - // Stage2 has valid data whenever Stage1 had valid data and - // ram_regout_en_i=1, such that the data in Stage1 is propogated - // into Stage2. - //*************************************************************************** - always @ (posedge RD_CLK or posedge rd_rst_i) begin - if (rd_rst_i) - read_data_valid_i <= #`TCQ 1'b0; - else if (srst_i) - read_data_valid_i <= #`TCQ 1'b0; - else - read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN); - end //always - - - //************************************************************************** - // Calculate EMPTY - // Defined as the inverse of READ_DATA_VALID - // - // Description: - // - // If read_data_valid_i indicates that the output is not valid, - // and there is no valid data on the output of the ram to preload it - // with, then we will report empty. - // - // If there is no valid data on the output of the ram and we are - // reading, then the FIFO will go empty. - // - //************************************************************************** - always @ (posedge RD_CLK or posedge rd_rst_i) begin - if (rd_rst_i) begin - // asynchronous reset (active high) - empty_i <= #`TCQ 1'b1; - end else begin - if (srst_i) begin - // synchronous reset (active high) - empty_i <= #`TCQ 1'b1; - end else begin - // rising clock edge - empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); - end - end - end //always - - // Register RD_EN from user to calculate USERUNDERFLOW. - // Register empty_i to calculate USERUNDERFLOW. - always @ (posedge RD_CLK) begin - rd_en_q <= #`TCQ RD_EN; - empty_q <= #`TCQ empty_i; - end //always - - - //*************************************************************************** - // Calculate user_almost_empty - // user_almost_empty is defined such that, unless more words are written - // to the FIFO, the next read will cause the FIFO to go EMPTY. - // - // In most cases, whenever the output registers are updated (due to a user - // read or a preload condition), then user_almost_empty will update to - // whatever RAM_EMPTY is. - // - // The exception is when the output is valid, the user is not reading, and - // Stage1 is not empty. In this condition, Stage1 will be preloaded from the - // memory, so we need to make sure user_almost_empty deasserts properly under - // this condition. - //*************************************************************************** - always @ (posedge RD_CLK or posedge rd_rst_i) - begin - if (rd_rst_i) begin // asynchronous reset (active high) - almost_empty_i <= #`TCQ 1'b1; - almost_empty_q <= #`TCQ 1'b1; - end else begin // rising clock edge - if (srst_i) begin // synchronous reset (active high) - almost_empty_i <= #`TCQ 1'b1; - almost_empty_q <= #`TCQ 1'b1; - end else begin - if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin - almost_empty_i <= #`TCQ FIFOEMPTY; - end - almost_empty_q <= #`TCQ empty_i; - end - end - end //always - - - assign USEREMPTY = empty_i; - assign USERALMOSTEMPTY = almost_empty_i; - assign FIFORDEN = ram_rd_en; - assign RAMVALID = ram_valid_i; - assign USERVALID = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i; - assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; - - // BRAM resets synchronously - always @ (posedge RD_CLK) - begin - if (rd_rst_i || srst_i) begin - if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) - USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); - end - end //always - - - always @ (posedge RD_CLK or posedge rd_rst_i) - begin - if (rd_rst_i) begin //asynchronous reset (active high) - if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF - USERSBITERR <= #`TCQ 0; - USERDBITERR <= #`TCQ 0; - end - // DRAM resets asynchronously - if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) //asynchronous reset (active high) - USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); - end else begin // rising clock edge - if (srst_i) begin - if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF - USERSBITERR <= #`TCQ 0; - USERDBITERR <= #`TCQ 0; - end - if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) - USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); - end else begin - if (ram_regout_en) begin - USERDATA <= #`TCQ FIFODATA; - USERSBITERR <= #`TCQ FIFOSBITERR; - USERDBITERR <= #`TCQ FIFODBITERR; - end - end - end - end //always - -endmodule - diff --git a/fpga/usrp2/models/IBUFG.v b/fpga/usrp2/models/IBUFG.v deleted file mode 100644 index c21cc1dc8..000000000 --- a/fpga/usrp2/models/IBUFG.v +++ /dev/null @@ -1,59 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG.v,v 1.7 2007/05/23 21:43:34 patrickp Exp $ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2004 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 10.1 -// \ \ Description : Xilinx Functional Simulation Library Component -// / / Input Clock Buffer -// /___/ /\ Filename : IBUFG.v -// \ \ / \ Timestamp : Thu Mar 25 16:42:24 PST 2004 -// \___\/\___\ -// -// Revision: -// 03/23/04 - Initial version. -// 05/23/07 - Changed timescale to 1 ps / 1 ps. - -`timescale 1 ps / 1 ps - - -module IBUFG (O, I); - - parameter CAPACITANCE = "DONT_CARE"; - parameter IBUF_DELAY_VALUE = "0"; - parameter IOSTANDARD = "DEFAULT"; - - output O; - input I; - - buf B1 (O, I); - - initial begin - - case (CAPACITANCE) - - "LOW", "NORMAL", "DONT_CARE" : ; - default : begin - $display("Attribute Syntax Error : The attribute CAPACITANCE on IBUFG instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); - $finish; - end - - endcase - - - case (IBUF_DELAY_VALUE) - - "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ; - default : begin - $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUFG instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE); - $finish; - end - - endcase - - end // initial begin - -endmodule diff --git a/fpga/usrp2/models/IBUFGDS.v b/fpga/usrp2/models/IBUFGDS.v deleted file mode 100644 index 01c108c8d..000000000 --- a/fpga/usrp2/models/IBUFGDS.v +++ /dev/null @@ -1,87 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS.v,v 1.8 2007/07/26 23:22:55 fphillip Exp $ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2004 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 10.1 -// \ \ Description : Xilinx Functional Simulation Library Component -// / / Differential Signaling Input Clock Buffer -// /___/ /\ Filename : IBUFGDS.v -// \ \ / \ Timestamp : Thu Mar 25 16:42:24 PST 2004 -// \___\/\___\ -// -// Revision: -// 03/23/04 - Initial version. -// 05/23/07 - Changed timescale to 1 ps / 1 ps. -// 07/26/07 - Add else to handle x case for o_out (CR 424214). -// End Revision - - -`timescale 1 ps / 1 ps - - -module IBUFGDS (O, I, IB); - - parameter CAPACITANCE = "DONT_CARE"; - parameter DIFF_TERM = "FALSE"; - parameter IBUF_DELAY_VALUE = "0"; - parameter IOSTANDARD = "DEFAULT"; - - output O; - input I, IB; - - reg o_out; - - buf b_0 (O, o_out); - - initial begin - - case (CAPACITANCE) - - "LOW", "NORMAL", "DONT_CARE" : ; - default : begin - $display("Attribute Syntax Error : The attribute CAPACITANCE on IBUFGDS instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); - $finish; - end - - endcase - - - case (DIFF_TERM) - - "TRUE", "FALSE" : ; - default : begin - $display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFGDS instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM); - $finish; - end - - endcase - - - case (IBUF_DELAY_VALUE) - - "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ; - default : begin - $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUFGDS instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE); - $finish; - end - - endcase - - end - - always @(I or IB) begin - if (I == 1'b1 && IB == 1'b0) - o_out <= I; - else if (I == 1'b0 && IB == 1'b1) - o_out <= I; - else if (I == 1'bx && IB == 1'bx) - o_out <= 1'bx; - end - -endmodule - - diff --git a/fpga/usrp2/models/IDDR2.v b/fpga/usrp2/models/IDDR2.v deleted file mode 100644 index 727f1c568..000000000 --- a/fpga/usrp2/models/IDDR2.v +++ /dev/null @@ -1,172 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/spartan4/IDDR2.v,v 1.1 2004/06/21 21:45:36 wloo Exp $ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2004 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 10.1 -// \ \ Description : Xilinx Functional Simulation Library Component -// / / Dual Data Rate Input D Flip-Flop -// /___/ /\ Filename : IDDR2.v -// \ \ / \ Timestamp : Thu Mar 25 16:43:51 PST 2004 -// \___\/\___\ -// -// Revision: -// 03/23/04 - Initial version. - -`timescale 1 ps / 1 ps - -module IDDR2 (Q0, Q1, C0, C1, CE, D, R, S); - - output Q0; - output Q1; - - input C0; - input C1; - input CE; - input D; - tri0 GSR = glbl.GSR; - input R; - input S; - - parameter DDR_ALIGNMENT = "NONE"; - parameter INIT_Q0 = 1'b0; - parameter INIT_Q1 = 1'b0; - parameter SRTYPE = "SYNC"; - - reg q0_out, q1_out; - reg q0_out_int, q1_out_int; - reg q0_c1_out_int, q1_c0_out_int; - - buf buf_q0 (Q0, q0_out); - buf buf_q1 (Q1, q1_out); - - - initial begin - - if ((INIT_Q0 != 1'b0) && (INIT_Q0 != 1'b1)) begin - $display("Attribute Syntax Error : The attribute INIT_Q0 on IDDR2 instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q0); - $finish; - end - - if ((INIT_Q1 != 1'b0) && (INIT_Q1 != 1'b1)) begin - $display("Attribute Syntax Error : The attribute INIT_Q0 on IDDR2 instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q1); - $finish; - end - - if ((DDR_ALIGNMENT != "C1") && (DDR_ALIGNMENT != "C0") && (DDR_ALIGNMENT != "NONE")) begin - $display("Attribute Syntax Error : The attribute DDR_ALIGNMENT on IDDR2 instance %m is set to %s. Legal values for this attribute are C0, C1 or NONE.", DDR_ALIGNMENT); - $finish; - end - - if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin - $display("Attribute Syntax Error : The attribute SRTYPE on IDDR2 instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE); - $finish; - end - - end // initial begin - - - always @(GSR or R or S) begin - - if (GSR == 1) begin - - assign q0_out_int = INIT_Q0; - assign q1_out_int = INIT_Q1; - assign q0_c1_out_int = INIT_Q0; - assign q1_c0_out_int = INIT_Q1; - - end - else begin - - deassign q0_out_int; - deassign q1_out_int; - deassign q0_c1_out_int; - deassign q1_c0_out_int; - - if (SRTYPE == "ASYNC") begin - if (R == 1) begin - assign q0_out_int = 0; - assign q1_out_int = 0; - assign q0_c1_out_int = 0; - assign q1_c0_out_int = 0; - end - else if (R == 0 && S == 1) begin - assign q0_out_int = 1; - assign q1_out_int = 1; - assign q0_c1_out_int = 1; - assign q1_c0_out_int = 1; - end - end // if (SRTYPE == "ASYNC") - - end // if (GSR == 1'b0) - - end // always @ (GSR or R or S) - - - always @(posedge C0) begin - if (R == 1 && SRTYPE == "SYNC") begin - q0_out_int <= 0; - q1_c0_out_int <= 0; - end - else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin - q0_out_int <= 1; - q1_c0_out_int <= 1; - end - else if (CE == 1 && R == 0 && S == 0) begin - q0_out_int <= D; - q1_c0_out_int <= q1_out_int; - end - end // always @ (posedge C0) - - - always @(posedge C1) begin - if (R == 1 && SRTYPE == "SYNC") begin - q1_out_int <= 0; - q0_c1_out_int <= 0; - end - else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin - q1_out_int <= 1; - q0_c1_out_int <= 1; - end - else if (CE == 1 && R == 0 && S == 0) begin - q1_out_int <= D; - q0_c1_out_int <= q0_out_int; - end - end // always @ (posedge C1) - - - always @(q0_out_int or q1_out_int or q1_c0_out_int or q0_c1_out_int) begin - - case (DDR_ALIGNMENT) - "NONE" : begin - q0_out <= q0_out_int; - q1_out <= q1_out_int; - end - "C0" : begin - q0_out <= q0_out_int; - q1_out <= q1_c0_out_int; - end - "C1" : begin - q0_out <= q0_c1_out_int; - q1_out <= q1_out_int; - end - endcase // case(DDR_ALIGNMENT) - - end // always @ (q0_out_int or q1_out_int or q1_c0_out_int or q0_c1_out_int) - - - specify - - if (C0) (C0 => Q0) = (100, 100); - if (C0) (C0 => Q1) = (100, 100); - if (C1) (C1 => Q1) = (100, 100); - if (C1) (C1 => Q0) = (100, 100); - specparam PATHPULSE$ = 0; - - endspecify - -endmodule // IDDR2 - diff --git a/fpga/usrp2/models/IOBUF.v b/fpga/usrp2/models/IOBUF.v deleted file mode 100644 index 1195dfb17..000000000 --- a/fpga/usrp2/models/IOBUF.v +++ /dev/null @@ -1,83 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF.v,v 1.9 2007/05/23 21:43:39 patrickp Exp $ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2004 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 10.1 -// \ \ Description : Xilinx Functional Simulation Library Component -// / / Bi-Directional Buffer -// /___/ /\ Filename : IOBUF.v -// \ \ / \ Timestamp : Thu Mar 25 16:42:37 PST 2004 -// \___\/\___\ -// -// Revision: -// 03/23/04 - Initial version. -// 02/22/06 - CR#226003 - Added integer, real parameter type -// 05/23/07 - Changed timescale to 1 ps / 1 ps. -// 05/23/07 - Added wire declaration for internal signals. - -`timescale 1 ps / 1 ps - - -module IOBUF (O, IO, I, T); - - parameter CAPACITANCE = "DONT_CARE"; - parameter integer DRIVE = 12; - parameter IBUF_DELAY_VALUE = "0"; - parameter IFD_DELAY_VALUE = "AUTO"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - - output O; - inout IO; - input I, T; - - wire ts; - - //tri0 GTS = glbl.GTS; - - or O1 (ts, GTS, T); - bufif0 T1 (IO, I, ts); - - buf B1 (O, IO); - - initial begin - - case (CAPACITANCE) - - "LOW", "NORMAL", "DONT_CARE" : ; - default : begin - $display("Attribute Syntax Error : The attribute CAPACITANCE on IOBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); - $finish; - end - - endcase - - case (IBUF_DELAY_VALUE) - - "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ; - default : begin - $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE); - $finish; - end - - endcase - - - case (IFD_DELAY_VALUE) - - "AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ; - default : begin - $display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE); - $finish; - end - - endcase - - end // initial begin - -endmodule - diff --git a/fpga/usrp2/models/M24LC024B.v b/fpga/usrp2/models/M24LC024B.v deleted file mode 100644 index 5531f80fc..000000000 --- a/fpga/usrp2/models/M24LC024B.v +++ /dev/null @@ -1,476 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// Modified 11/14/07 to simulate the 24lc024, which responds to the address pins - -// ******************************************************************************************************* -// ** ** -// ** M24LC024B.v - 24LC02B 2K-BIT I2C SERIAL EEPROM (VCC = +2.5V TO +5.5V) ** -// ** ** -// ******************************************************************************************************* -// ** ** -// ** COPYRIGHT (c) 2003 YOUNG ENGINEERING ** -// ** ALL RIGHTS RESERVED ** -// ** ** -// ** THIS PROGRAM IS CONFIDENTIAL AND A TRADE SECRET OF YOUNG ENGINEERING. THE RECEIPT OR ** -// ** POSSESSION OF THIS PROGRAM DOES NOT CONVEY ANY RIGHTS TO REPRODUCE OR DISCLOSE ITS ** -// ** CONTENTS, OR TO MANUFACTURE, USE, OR SELL ANYTHING THAT IT MAY DESCRIBE, IN WHOLE OR IN ** -// ** PART, WITHOUT THE SPECIFIC WRITTEN CONSENT OF YOUNG ENGINEERING. ** -// ** ** -// ******************************************************************************************************* -// ** Revision : 1.1 ** -// ** Modified Date : 07/19/2004 ** -// ** Revision History: ** -// ** ** -// ** 02/01/2003: Initial design ** -// ** 07/19/2004: Fixed the timing checks and the open-drain modeling for SDA. ** -// ** ** -// ******************************************************************************************************* -// ** TABLE OF CONTENTS ** -// ******************************************************************************************************* -// **---------------------------------------------------------------------------------------------------** -// ** DECLARATIONS ** -// **---------------------------------------------------------------------------------------------------** -// **---------------------------------------------------------------------------------------------------** -// ** INITIALIZATION ** -// **---------------------------------------------------------------------------------------------------** -// **---------------------------------------------------------------------------------------------------** -// ** CORE LOGIC ** -// **---------------------------------------------------------------------------------------------------** -// ** 1.01: START Bit Detection ** -// ** 1.02: STOP Bit Detection ** -// ** 1.03: Input Shift Register ** -// ** 1.04: Input Bit Counter ** -// ** 1.05: Control Byte Register ** -// ** 1.06: Byte Address Register ** -// ** 1.07: Write Data Buffer ** -// ** 1.08: Acknowledge Generator ** -// ** 1.09: Acknowledge Detect ** -// ** 1.10: Write Cycle Timer ** -// ** 1.11: Write Cycle Processor ** -// ** 1.12: Read Data Multiplexor ** -// ** 1.13: Read Data Processor ** -// ** 1.14: SDA Data I/O Buffer ** -// ** ** -// **---------------------------------------------------------------------------------------------------** -// ** DEBUG LOGIC ** -// **---------------------------------------------------------------------------------------------------** -// ** 2.01: Memory Data Bytes ** -// ** 2.02: Write Data Buffer ** -// ** ** -// **---------------------------------------------------------------------------------------------------** -// ** TIMING CHECKS ** -// **---------------------------------------------------------------------------------------------------** -// ** ** -// ******************************************************************************************************* - - -`timescale 1ns/10ps - -module M24LC024B (A0, A1, A2, WP, SDA, SCL, RESET); - - input A0; // unconnected pin - input A1; // unconnected pin - input A2; // unconnected pin - - input WP; // write protect pin - - inout SDA; // serial data I/O - input SCL; // serial data clock - - input RESET; // system reset - - -// ******************************************************************************************************* -// ** DECLARATIONS ** -// ******************************************************************************************************* - - reg SDA_DO; // serial data - output - reg SDA_OE; // serial data - output enable - - wire SDA_DriveEnable; // serial data output enable - reg SDA_DriveEnableDlyd; // serial data output enable - delayed - - reg [03:00] BitCounter; // serial bit counter - - reg START_Rcvd; // START bit received flag - reg STOP_Rcvd; // STOP bit received flag - reg CTRL_Rcvd; // control byte received flag - reg ADDR_Rcvd; // byte address received flag - reg MACK_Rcvd; // master acknowledge received flag - - reg WrCycle; // memory write cycle - reg RdCycle; // memory read cycle - - reg [07:00] ShiftRegister; // input data shift register - - reg [07:00] ControlByte; // control byte register - wire RdWrBit; // read/write control bit - - reg [07:00] StartAddress; // memory access starting address - reg [02:00] PageAddress; // memory page address - - reg [07:00] WrDataByte [0:7]; // memory write data buffer - wire [07:00] RdDataByte; // memory read data - - reg [15:00] WrCounter; // write buffer counter - - reg [02:00] WrPointer; // write buffer pointer - reg [07:00] RdPointer; // read address pointer - - reg WriteActive; // memory write cycle active - - reg [07:00] MemoryBlock [0:255]; // EEPROM data memory array - - integer LoopIndex; // iterative loop index - - integer tAA; // timing parameter - integer tWC; // timing parameter - - -// ******************************************************************************************************* -// ** INITIALIZATION ** -// ******************************************************************************************************* - - initial tAA = 900; // SCL to SDA output delay - initial tWC = 5000000; // memory write cycle time - //initial tWC = 50000; // shortened memory write cycle time to speed up sims - - initial begin - SDA_DO = 0; - SDA_OE = 0; - end - - initial begin - START_Rcvd = 0; - STOP_Rcvd = 0; - CTRL_Rcvd = 0; - ADDR_Rcvd = 0; - MACK_Rcvd = 0; - end - - initial begin - BitCounter = 0; - ControlByte = 0; - end - - initial begin - WrCycle = 0; - RdCycle = 0; - - WriteActive = 0; - end - - -// ******************************************************************************************************* -// ** CORE LOGIC ** -// ******************************************************************************************************* -// ------------------------------------------------------------------------------------------------------- -// 1.01: START Bit Detection -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SDA) begin - if (SCL == 1) begin - START_Rcvd <= 1; - STOP_Rcvd <= 0; - CTRL_Rcvd <= 0; - ADDR_Rcvd <= 0; - MACK_Rcvd <= 0; - - WrCycle <= #1 0; - RdCycle <= #1 0; - - BitCounter <= 0; - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.02: STOP Bit Detection -// ------------------------------------------------------------------------------------------------------- - - always @(posedge SDA) begin - if (SCL == 1) begin - START_Rcvd <= 0; - STOP_Rcvd <= 1; - CTRL_Rcvd <= 0; - ADDR_Rcvd <= 0; - MACK_Rcvd <= 0; - - WrCycle <= #1 0; - RdCycle <= #1 0; - - BitCounter <= 10; - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.03: Input Shift Register -// ------------------------------------------------------------------------------------------------------- - - always @(posedge SCL) begin - ShiftRegister[00] <= SDA; - ShiftRegister[01] <= ShiftRegister[00]; - ShiftRegister[02] <= ShiftRegister[01]; - ShiftRegister[03] <= ShiftRegister[02]; - ShiftRegister[04] <= ShiftRegister[03]; - ShiftRegister[05] <= ShiftRegister[04]; - ShiftRegister[06] <= ShiftRegister[05]; - ShiftRegister[07] <= ShiftRegister[06]; - end - -// ------------------------------------------------------------------------------------------------------- -// 1.04: Input Bit Counter -// ------------------------------------------------------------------------------------------------------- - - always @(posedge SCL) begin - if (BitCounter < 10) BitCounter <= BitCounter + 1; - end - -// ------------------------------------------------------------------------------------------------------- -// 1.05: Control Byte Register -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (START_Rcvd & (BitCounter == 8)) begin - if (!WriteActive & (ShiftRegister[07:04] == 4'b1010) - & (ShiftRegister[3:1] == {A2,A1,A0})) begin - if (ShiftRegister[00] == 0) WrCycle <= 1; - if (ShiftRegister[00] == 1) RdCycle <= 1; - - ControlByte <= ShiftRegister[07:00]; - - CTRL_Rcvd <= 1; - end - - START_Rcvd <= 0; - end - end - - assign RdWrBit = ControlByte[00]; - -// ------------------------------------------------------------------------------------------------------- -// 1.06: Byte Address Register -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (CTRL_Rcvd & (BitCounter == 8)) begin - if (RdWrBit == 0) begin - StartAddress <= ShiftRegister[07:00]; - RdPointer <= ShiftRegister[07:00]; - - ADDR_Rcvd <= 1; - end - - WrCounter <= 0; - WrPointer <= 0; - - CTRL_Rcvd <= 0; - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.07: Write Data Buffer -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (ADDR_Rcvd & (BitCounter == 8)) begin - if ((WP == 0) & (RdWrBit == 0)) begin - WrDataByte[WrPointer] <= ShiftRegister[07:00]; - - WrCounter <= WrCounter + 1; - WrPointer <= WrPointer + 1; - end - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.08: Acknowledge Generator -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (!WriteActive) begin - if (BitCounter == 8) begin - if (WrCycle | (START_Rcvd & (ShiftRegister[07:04] == 4'b1010))) begin - SDA_DO <= 0; - SDA_OE <= 1; - end - end - if (BitCounter == 9) begin - BitCounter <= 0; - - if (!RdCycle) begin - SDA_DO <= 0; - SDA_OE <= 0; - end - end - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.09: Acknowledge Detect -// ------------------------------------------------------------------------------------------------------- - - always @(posedge SCL) begin - if (RdCycle & (BitCounter == 8)) begin - if ((SDA == 0) & (SDA_OE == 0)) MACK_Rcvd <= 1; - end - end - - always @(negedge SCL) MACK_Rcvd <= 0; - -// ------------------------------------------------------------------------------------------------------- -// 1.10: Write Cycle Timer -// ------------------------------------------------------------------------------------------------------- - - always @(posedge STOP_Rcvd) begin - if (WrCycle & (WP == 0) & (WrCounter > 0)) begin - WriteActive = 1; - #(tWC); - WriteActive = 0; - end - end - - always @(posedge STOP_Rcvd) begin - #(1.0); - STOP_Rcvd = 0; - end - -// ------------------------------------------------------------------------------------------------------- -// 1.11: Write Cycle Processor -// ------------------------------------------------------------------------------------------------------- - - always @(posedge WriteActive) begin - for (LoopIndex = 0; LoopIndex < WrCounter; LoopIndex = LoopIndex + 1) begin - PageAddress = StartAddress[02:00] + LoopIndex; - - MemoryBlock[{StartAddress[07:03],PageAddress[02:00]}] = WrDataByte[LoopIndex[02:00]]; - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.12: Read Data Multiplexor -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (BitCounter == 8) begin - if (WrCycle & ADDR_Rcvd) begin - RdPointer <= StartAddress + WrPointer + 1; - end - if (RdCycle) begin - RdPointer <= RdPointer + 1; - end - end - end - - assign RdDataByte = MemoryBlock[RdPointer[07:00]]; - -// ------------------------------------------------------------------------------------------------------- -// 1.13: Read Data Processor -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (RdCycle) begin - if (BitCounter == 8) begin - SDA_DO <= 0; - SDA_OE <= 0; - end - else if (BitCounter == 9) begin - SDA_DO <= RdDataByte[07]; - - if (MACK_Rcvd) SDA_OE <= 1; - end - else begin - SDA_DO <= RdDataByte[7-BitCounter]; - end - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.14: SDA Data I/O Buffer -// ------------------------------------------------------------------------------------------------------- - - bufif1 (SDA, 1'b0, SDA_DriveEnableDlyd); - - assign SDA_DriveEnable = !SDA_DO & SDA_OE; - always @(SDA_DriveEnable) SDA_DriveEnableDlyd <= #(tAA) SDA_DriveEnable; - - -// ******************************************************************************************************* -// ** DEBUG LOGIC ** -// ******************************************************************************************************* -// ------------------------------------------------------------------------------------------------------- -// 2.01: Memory Data Bytes -// ------------------------------------------------------------------------------------------------------- - - wire [07:00] MemoryByte00 = MemoryBlock[00]; - wire [07:00] MemoryByte01 = MemoryBlock[01]; - wire [07:00] MemoryByte02 = MemoryBlock[02]; - wire [07:00] MemoryByte03 = MemoryBlock[03]; - wire [07:00] MemoryByte04 = MemoryBlock[04]; - wire [07:00] MemoryByte05 = MemoryBlock[05]; - wire [07:00] MemoryByte06 = MemoryBlock[06]; - wire [07:00] MemoryByte07 = MemoryBlock[07]; - - wire [07:00] MemoryByte08 = MemoryBlock[08]; - wire [07:00] MemoryByte09 = MemoryBlock[09]; - wire [07:00] MemoryByte0A = MemoryBlock[10]; - wire [07:00] MemoryByte0B = MemoryBlock[11]; - wire [07:00] MemoryByte0C = MemoryBlock[12]; - wire [07:00] MemoryByte0D = MemoryBlock[13]; - wire [07:00] MemoryByte0E = MemoryBlock[14]; - wire [07:00] MemoryByte0F = MemoryBlock[15]; - -// ------------------------------------------------------------------------------------------------------- -// 2.02: Write Data Buffer -// ------------------------------------------------------------------------------------------------------- - - wire [07:00] WriteData_0 = WrDataByte[00]; - wire [07:00] WriteData_1 = WrDataByte[01]; - wire [07:00] WriteData_2 = WrDataByte[02]; - wire [07:00] WriteData_3 = WrDataByte[03]; - wire [07:00] WriteData_4 = WrDataByte[04]; - wire [07:00] WriteData_5 = WrDataByte[05]; - wire [07:00] WriteData_6 = WrDataByte[06]; - wire [07:00] WriteData_7 = WrDataByte[07]; - - -// ******************************************************************************************************* -// ** TIMING CHECKS ** -// ******************************************************************************************************* - - wire TimingCheckEnable = (RESET == 0) & (SDA_OE == 0); - - specify - specparam - tHI = 600, // SCL pulse width - high - tLO = 1300, // SCL pulse width - low - tSU_STA = 600, // SCL to SDA setup time - tHD_STA = 600, // SCL to SDA hold time - tSU_DAT = 100, // SDA to SCL setup time - tSU_STO = 600; // SCL to SDA setup time - - $width (posedge SCL, tHI); - $width (negedge SCL, tLO); - - $setup (SCL, negedge SDA &&& TimingCheckEnable, tSU_STA); - $setup (SDA, posedge SCL &&& TimingCheckEnable, tSU_DAT); - $setup (SCL, posedge SDA &&& TimingCheckEnable, tSU_STO); - - $hold (negedge SDA &&& TimingCheckEnable, SCL, tHD_STA); - endspecify - -endmodule diff --git a/fpga/usrp2/models/M24LC02B.v b/fpga/usrp2/models/M24LC02B.v deleted file mode 100644 index 00ed6f44a..000000000 --- a/fpga/usrp2/models/M24LC02B.v +++ /dev/null @@ -1,472 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// ******************************************************************************************************* -// ** ** -// ** M24LC02B.v - 24LC02B 2K-BIT I2C SERIAL EEPROM (VCC = +2.5V TO +5.5V) ** -// ** ** -// ******************************************************************************************************* -// ** ** -// ** COPYRIGHT (c) 2003 YOUNG ENGINEERING ** -// ** ALL RIGHTS RESERVED ** -// ** ** -// ** THIS PROGRAM IS CONFIDENTIAL AND A TRADE SECRET OF YOUNG ENGINEERING. THE RECEIPT OR ** -// ** POSSESSION OF THIS PROGRAM DOES NOT CONVEY ANY RIGHTS TO REPRODUCE OR DISCLOSE ITS ** -// ** CONTENTS, OR TO MANUFACTURE, USE, OR SELL ANYTHING THAT IT MAY DESCRIBE, IN WHOLE OR IN ** -// ** PART, WITHOUT THE SPECIFIC WRITTEN CONSENT OF YOUNG ENGINEERING. ** -// ** ** -// ******************************************************************************************************* -// ** Revision : 1.1 ** -// ** Modified Date : 07/19/2004 ** -// ** Revision History: ** -// ** ** -// ** 02/01/2003: Initial design ** -// ** 07/19/2004: Fixed the timing checks and the open-drain modeling for SDA. ** -// ** ** -// ******************************************************************************************************* -// ** TABLE OF CONTENTS ** -// ******************************************************************************************************* -// **---------------------------------------------------------------------------------------------------** -// ** DECLARATIONS ** -// **---------------------------------------------------------------------------------------------------** -// **---------------------------------------------------------------------------------------------------** -// ** INITIALIZATION ** -// **---------------------------------------------------------------------------------------------------** -// **---------------------------------------------------------------------------------------------------** -// ** CORE LOGIC ** -// **---------------------------------------------------------------------------------------------------** -// ** 1.01: START Bit Detection ** -// ** 1.02: STOP Bit Detection ** -// ** 1.03: Input Shift Register ** -// ** 1.04: Input Bit Counter ** -// ** 1.05: Control Byte Register ** -// ** 1.06: Byte Address Register ** -// ** 1.07: Write Data Buffer ** -// ** 1.08: Acknowledge Generator ** -// ** 1.09: Acknowledge Detect ** -// ** 1.10: Write Cycle Timer ** -// ** 1.11: Write Cycle Processor ** -// ** 1.12: Read Data Multiplexor ** -// ** 1.13: Read Data Processor ** -// ** 1.14: SDA Data I/O Buffer ** -// ** ** -// **---------------------------------------------------------------------------------------------------** -// ** DEBUG LOGIC ** -// **---------------------------------------------------------------------------------------------------** -// ** 2.01: Memory Data Bytes ** -// ** 2.02: Write Data Buffer ** -// ** ** -// **---------------------------------------------------------------------------------------------------** -// ** TIMING CHECKS ** -// **---------------------------------------------------------------------------------------------------** -// ** ** -// ******************************************************************************************************* - - -`timescale 1ns/10ps - -module M24LC02B (A0, A1, A2, WP, SDA, SCL, RESET); - - input A0; // unconnected pin - input A1; // unconnected pin - input A2; // unconnected pin - - input WP; // write protect pin - - inout SDA; // serial data I/O - input SCL; // serial data clock - - input RESET; // system reset - - -// ******************************************************************************************************* -// ** DECLARATIONS ** -// ******************************************************************************************************* - - reg SDA_DO; // serial data - output - reg SDA_OE; // serial data - output enable - - wire SDA_DriveEnable; // serial data output enable - reg SDA_DriveEnableDlyd; // serial data output enable - delayed - - reg [03:00] BitCounter; // serial bit counter - - reg START_Rcvd; // START bit received flag - reg STOP_Rcvd; // STOP bit received flag - reg CTRL_Rcvd; // control byte received flag - reg ADDR_Rcvd; // byte address received flag - reg MACK_Rcvd; // master acknowledge received flag - - reg WrCycle; // memory write cycle - reg RdCycle; // memory read cycle - - reg [07:00] ShiftRegister; // input data shift register - - reg [07:00] ControlByte; // control byte register - wire RdWrBit; // read/write control bit - - reg [07:00] StartAddress; // memory access starting address - reg [02:00] PageAddress; // memory page address - - reg [07:00] WrDataByte [0:7]; // memory write data buffer - wire [07:00] RdDataByte; // memory read data - - reg [15:00] WrCounter; // write buffer counter - - reg [02:00] WrPointer; // write buffer pointer - reg [07:00] RdPointer; // read address pointer - - reg WriteActive; // memory write cycle active - - reg [07:00] MemoryBlock [0:255]; // EEPROM data memory array - - integer LoopIndex; // iterative loop index - - integer tAA; // timing parameter - integer tWC; // timing parameter - - -// ******************************************************************************************************* -// ** INITIALIZATION ** -// ******************************************************************************************************* - - initial tAA = 900; // SCL to SDA output delay - initial tWC = 5000000; // memory write cycle time - - initial begin - SDA_DO = 0; - SDA_OE = 0; - end - - initial begin - START_Rcvd = 0; - STOP_Rcvd = 0; - CTRL_Rcvd = 0; - ADDR_Rcvd = 0; - MACK_Rcvd = 0; - end - - initial begin - BitCounter = 0; - ControlByte = 0; - end - - initial begin - WrCycle = 0; - RdCycle = 0; - - WriteActive = 0; - end - - -// ******************************************************************************************************* -// ** CORE LOGIC ** -// ******************************************************************************************************* -// ------------------------------------------------------------------------------------------------------- -// 1.01: START Bit Detection -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SDA) begin - if (SCL == 1) begin - START_Rcvd <= 1; - STOP_Rcvd <= 0; - CTRL_Rcvd <= 0; - ADDR_Rcvd <= 0; - MACK_Rcvd <= 0; - - WrCycle <= #1 0; - RdCycle <= #1 0; - - BitCounter <= 0; - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.02: STOP Bit Detection -// ------------------------------------------------------------------------------------------------------- - - always @(posedge SDA) begin - if (SCL == 1) begin - START_Rcvd <= 0; - STOP_Rcvd <= 1; - CTRL_Rcvd <= 0; - ADDR_Rcvd <= 0; - MACK_Rcvd <= 0; - - WrCycle <= #1 0; - RdCycle <= #1 0; - - BitCounter <= 10; - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.03: Input Shift Register -// ------------------------------------------------------------------------------------------------------- - - always @(posedge SCL) begin - ShiftRegister[00] <= SDA; - ShiftRegister[01] <= ShiftRegister[00]; - ShiftRegister[02] <= ShiftRegister[01]; - ShiftRegister[03] <= ShiftRegister[02]; - ShiftRegister[04] <= ShiftRegister[03]; - ShiftRegister[05] <= ShiftRegister[04]; - ShiftRegister[06] <= ShiftRegister[05]; - ShiftRegister[07] <= ShiftRegister[06]; - end - -// ------------------------------------------------------------------------------------------------------- -// 1.04: Input Bit Counter -// ------------------------------------------------------------------------------------------------------- - - always @(posedge SCL) begin - if (BitCounter < 10) BitCounter <= BitCounter + 1; - end - -// ------------------------------------------------------------------------------------------------------- -// 1.05: Control Byte Register -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (START_Rcvd & (BitCounter == 8)) begin - if (!WriteActive & (ShiftRegister[07:04] == 4'b1010)) begin - if (ShiftRegister[00] == 0) WrCycle <= 1; - if (ShiftRegister[00] == 1) RdCycle <= 1; - - ControlByte <= ShiftRegister[07:00]; - - CTRL_Rcvd <= 1; - end - - START_Rcvd <= 0; - end - end - - assign RdWrBit = ControlByte[00]; - -// ------------------------------------------------------------------------------------------------------- -// 1.06: Byte Address Register -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (CTRL_Rcvd & (BitCounter == 8)) begin - if (RdWrBit == 0) begin - StartAddress <= ShiftRegister[07:00]; - RdPointer <= ShiftRegister[07:00]; - - ADDR_Rcvd <= 1; - end - - WrCounter <= 0; - WrPointer <= 0; - - CTRL_Rcvd <= 0; - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.07: Write Data Buffer -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (ADDR_Rcvd & (BitCounter == 8)) begin - if ((WP == 0) & (RdWrBit == 0)) begin - WrDataByte[WrPointer] <= ShiftRegister[07:00]; - - WrCounter <= WrCounter + 1; - WrPointer <= WrPointer + 1; - end - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.08: Acknowledge Generator -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (!WriteActive) begin - if (BitCounter == 8) begin - if (WrCycle | (START_Rcvd & (ShiftRegister[07:04] == 4'b1010))) begin - SDA_DO <= 0; - SDA_OE <= 1; - end - end - if (BitCounter == 9) begin - BitCounter <= 0; - - if (!RdCycle) begin - SDA_DO <= 0; - SDA_OE <= 0; - end - end - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.09: Acknowledge Detect -// ------------------------------------------------------------------------------------------------------- - - always @(posedge SCL) begin - if (RdCycle & (BitCounter == 8)) begin - if ((SDA == 0) & (SDA_OE == 0)) MACK_Rcvd <= 1; - end - end - - always @(negedge SCL) MACK_Rcvd <= 0; - -// ------------------------------------------------------------------------------------------------------- -// 1.10: Write Cycle Timer -// ------------------------------------------------------------------------------------------------------- - - always @(posedge STOP_Rcvd) begin - if (WrCycle & (WP == 0) & (WrCounter > 0)) begin - WriteActive = 1; - #(tWC); - WriteActive = 0; - end - end - - always @(posedge STOP_Rcvd) begin - #(1.0); - STOP_Rcvd = 0; - end - -// ------------------------------------------------------------------------------------------------------- -// 1.11: Write Cycle Processor -// ------------------------------------------------------------------------------------------------------- - - always @(posedge WriteActive) begin - for (LoopIndex = 0; LoopIndex < WrCounter; LoopIndex = LoopIndex + 1) begin - PageAddress = StartAddress[02:00] + LoopIndex; - - MemoryBlock[{StartAddress[07:03],PageAddress[02:00]}] = WrDataByte[LoopIndex[02:00]]; - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.12: Read Data Multiplexor -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (BitCounter == 8) begin - if (WrCycle & ADDR_Rcvd) begin - RdPointer <= StartAddress + WrPointer + 1; - end - if (RdCycle) begin - RdPointer <= RdPointer + 1; - end - end - end - - assign RdDataByte = MemoryBlock[RdPointer[07:00]]; - -// ------------------------------------------------------------------------------------------------------- -// 1.13: Read Data Processor -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (RdCycle) begin - if (BitCounter == 8) begin - SDA_DO <= 0; - SDA_OE <= 0; - end - else if (BitCounter == 9) begin - SDA_DO <= RdDataByte[07]; - - if (MACK_Rcvd) SDA_OE <= 1; - end - else begin - SDA_DO <= RdDataByte[7-BitCounter]; - end - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.14: SDA Data I/O Buffer -// ------------------------------------------------------------------------------------------------------- - - bufif1 (SDA, 1'b0, SDA_DriveEnableDlyd); - - assign SDA_DriveEnable = !SDA_DO & SDA_OE; - always @(SDA_DriveEnable) SDA_DriveEnableDlyd <= #(tAA) SDA_DriveEnable; - - -// ******************************************************************************************************* -// ** DEBUG LOGIC ** -// ******************************************************************************************************* -// ------------------------------------------------------------------------------------------------------- -// 2.01: Memory Data Bytes -// ------------------------------------------------------------------------------------------------------- - - wire [07:00] MemoryByte00 = MemoryBlock[00]; - wire [07:00] MemoryByte01 = MemoryBlock[01]; - wire [07:00] MemoryByte02 = MemoryBlock[02]; - wire [07:00] MemoryByte03 = MemoryBlock[03]; - wire [07:00] MemoryByte04 = MemoryBlock[04]; - wire [07:00] MemoryByte05 = MemoryBlock[05]; - wire [07:00] MemoryByte06 = MemoryBlock[06]; - wire [07:00] MemoryByte07 = MemoryBlock[07]; - - wire [07:00] MemoryByte08 = MemoryBlock[08]; - wire [07:00] MemoryByte09 = MemoryBlock[09]; - wire [07:00] MemoryByte0A = MemoryBlock[10]; - wire [07:00] MemoryByte0B = MemoryBlock[11]; - wire [07:00] MemoryByte0C = MemoryBlock[12]; - wire [07:00] MemoryByte0D = MemoryBlock[13]; - wire [07:00] MemoryByte0E = MemoryBlock[14]; - wire [07:00] MemoryByte0F = MemoryBlock[15]; - -// ------------------------------------------------------------------------------------------------------- -// 2.02: Write Data Buffer -// ------------------------------------------------------------------------------------------------------- - - wire [07:00] WriteData_0 = WrDataByte[00]; - wire [07:00] WriteData_1 = WrDataByte[01]; - wire [07:00] WriteData_2 = WrDataByte[02]; - wire [07:00] WriteData_3 = WrDataByte[03]; - wire [07:00] WriteData_4 = WrDataByte[04]; - wire [07:00] WriteData_5 = WrDataByte[05]; - wire [07:00] WriteData_6 = WrDataByte[06]; - wire [07:00] WriteData_7 = WrDataByte[07]; - - -// ******************************************************************************************************* -// ** TIMING CHECKS ** -// ******************************************************************************************************* - - wire TimingCheckEnable = (RESET == 0) & (SDA_OE == 0); - - specify - specparam - tHI = 600, // SCL pulse width - high - tLO = 1300, // SCL pulse width - low - tSU_STA = 600, // SCL to SDA setup time - tHD_STA = 600, // SCL to SDA hold time - tSU_DAT = 100, // SDA to SCL setup time - tSU_STO = 600; // SCL to SDA setup time - - $width (posedge SCL, tHI); - $width (negedge SCL, tLO); - - $setup (SCL, negedge SDA &&& TimingCheckEnable, tSU_STA); - $setup (SDA, posedge SCL &&& TimingCheckEnable, tSU_DAT); - $setup (SCL, posedge SDA &&& TimingCheckEnable, tSU_STO); - - $hold (negedge SDA &&& TimingCheckEnable, SCL, tHD_STA); - endspecify - -endmodule diff --git a/fpga/usrp2/models/MULT18X18S.v b/fpga/usrp2/models/MULT18X18S.v deleted file mode 100644 index 3ce2a267a..000000000 --- a/fpga/usrp2/models/MULT18X18S.v +++ /dev/null @@ -1,37 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Model of the Xilinx mult18x18s for signed 18x18 bit multiplies, -// As in the Spartan 3 series - -module MULT18X18S - (output reg signed [35:0] P, - input signed [17:0] A, - input signed [17:0] B, - input C, // Clock - input CE, // Clock Enable - input R // Synchronous Reset - ); - - always @(posedge C) - if(R) - P <= 36'sd0; - else if(CE) - P <= A * B; - -endmodule // MULT18X18S diff --git a/fpga/usrp2/models/ODDR2.v b/fpga/usrp2/models/ODDR2.v deleted file mode 100644 index 67e71761d..000000000 --- a/fpga/usrp2/models/ODDR2.v +++ /dev/null @@ -1,157 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/spartan4/ODDR2.v,v 1.1 2004/06/21 21:45:36 wloo Exp $ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2004 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 10.1 -// \ \ Description : Xilinx Functional Simulation Library Component -// / / Dual Data Rate Output D Flip-Flop -// /___/ /\ Filename : ODDR2.v -// \ \ / \ Timestamp : Thu Mar 25 16:43:52 PST 2004 -// \___\/\___\ -// -// Revision: -// 03/23/04 - Initial version. - -`timescale 1 ps / 1 ps - -module ODDR2 (Q, C0, C1, CE, D0, D1, R, S); - - output Q; - - input C0; - input C1; - input CE; - input D0; - input D1; - tri0 GSR = glbl.GSR; - input R; - input S; - - parameter DDR_ALIGNMENT = "NONE"; - parameter INIT = 1'b0; - parameter SRTYPE = "SYNC"; - - reg q_out, q_d0_c1_out_int, q_d1_c0_out_int; - - buf buf_q (Q, q_out); - - - initial begin - - if ((INIT != 1'b0) && (INIT != 1'b1)) begin - $display("Attribute Syntax Error : The attribute INIT on ODDR2 instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT); - $finish; - end - - if ((DDR_ALIGNMENT != "NONE") && (DDR_ALIGNMENT != "C0") && (DDR_ALIGNMENT != "C1")) begin - $display("Attribute Syntax Error : The attribute DDR_ALIGNMENT on ODDR2 instance %m is set to %s. Legal values for this attribute are NONE, C0 or C1.", DDR_ALIGNMENT); - $finish; - end - - if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin - $display("Attribute Syntax Error : The attribute SRTYPE on ODDR2 instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE); - $finish; - end - - end // initial begin - - - always @(GSR or R or S) begin - - if (GSR == 1) begin - - assign q_out = INIT; - assign q_d0_c1_out_int = INIT; - assign q_d1_c0_out_int = INIT; - - end - else begin - - deassign q_out; - deassign q_d0_c1_out_int; - deassign q_d1_c0_out_int; - - if (SRTYPE == "ASYNC") begin - if (R == 1) begin - assign q_out = 0; - assign q_d0_c1_out_int = 0; - assign q_d1_c0_out_int = 0; - end - else if (R == 0 && S == 1) begin - assign q_out = 1; - assign q_d0_c1_out_int = 1; - assign q_d1_c0_out_int = 1; - end - end // if (SRTYPE == "ASYNC") - - end // if (GSR == 1'b0) - - end // always @ (GSR or R or S) - - - always @(posedge C0) begin - - if (R == 1 && SRTYPE == "SYNC") begin - q_out <= 0; - q_d1_c0_out_int <= 0; - end - else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin - q_out <= 1; - q_d1_c0_out_int <= 1; - end - else if (CE == 1 && R == 0 && S == 0) begin - - if (DDR_ALIGNMENT == "C1") - q_out <= q_d0_c1_out_int; - else begin - q_out <= D0; - - if (DDR_ALIGNMENT == "C0") - q_d1_c0_out_int <= D1; - end - - end // if (CE == 1 && R == 0 && S == 0) - - end // always @ (posedge C0) - - - always @(posedge C1) begin - - if (R == 1 && SRTYPE == "SYNC") begin - q_out <= 0; - q_d0_c1_out_int <= 0; - end - else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin - q_out <= 1; - q_d0_c1_out_int <= 1; - end - else if (CE == 1 && R == 0 && S == 0) begin - - if (DDR_ALIGNMENT == "C0") - q_out <= q_d1_c0_out_int; - else begin - q_out <= D1; - - if (DDR_ALIGNMENT == "C1") - q_d0_c1_out_int <= D0; - end - - end // if (CE == 1 && R == 0 && S == 0) - - end // always @ (negedge c_in) - - - specify - - if (C0) (C0 => Q) = (100, 100); - if (C1) (C1 => Q) = (100, 100); - specparam PATHPULSE$ = 0; - - endspecify - -endmodule // ODDR2 - diff --git a/fpga/usrp2/models/PLL_ADV.v b/fpga/usrp2/models/PLL_ADV.v deleted file mode 100644 index d6a26e541..000000000 --- a/fpga/usrp2/models/PLL_ADV.v +++ /dev/null @@ -1,2142 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/PLL_ADV.v,v 1.43.4.1 2007/12/07 01:25:16 yanx Exp $ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2004 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 10.1 -// \ \ Description : Xilinx Function Simulation Library Component -// / / Phase Lock Loop Clock -// /___/ /\ Filename : PLL_ADV.v -// \ \ / \ Timestamp : Thu Mar 25 16:44:07 PST 2004 -// \___\/\___\ -// -// Revision: -// 03/15/05 - Initial version. -// 10/14/05 - Add REL pin. -// 11/07/05 - Add PMCD. -// 12/02/05 - Change parameter default values. Add DRP read/write. -// 12/22/05 - CR 222805 222809 fix. -// 01/03/06 - Change RST_DEASSER_CLK value to CLKIN1 and CLKFB (BT#735). -// 01/11/06 - Remove GSR from reset logic of PLL (CR 223099). -// 01/26/06 - Add reset to locked logic (CR224502). -// 02/16/06 - Support -360 6o +360 phase shifting (CR 225765) -// 03/10/06 - Add parameter type declaration (CR 226003) -// 03/17/06 - Using assign/deassign to reset pll_locked_tmp2 and reduce -// lock time by MD (CR 224502). -// 04/19/06 - Change i to i1 and i2 in clkvco_lk. (CR230260). -// 07/17/06 - Remove i2 and first 4 clkvco_lk cycle generation (CR234931). -// 08/23/06 - Use clkout_en_tmp to generate clkout_en0; Use block statement to -// reset clock stop counter and flag. (CR422250) -// 09/19/06 - md_product update (CR 424286). -// 09/27/06 - Add error check for RESET_ON_LOSS_OF_LOCK (CR 425255). -// 11/10/06 - Keep 3 digits for real in duty cycle check function. (CR 428703). -// 01/12/07 - Add CLKOUT_DESKEW_ADJUST parameters (CR 432189). -// 03/30/07 - Fix error message for CLKSEL change in RST=0 (CR 436927). -// 04/09/07 - Enhance error message for RESET_ON_LOSS_OF_LOCK (CR 437405). -// 04/10/07 - Using assign/deassign to reset signals with # delay (CR 437660). -// 05/22/07 - Add setup check for REL (438781). -// 06/04/07 - Add wire declaration to internal signal. -// 06/8/07 - Generate clkfb_tst when GSR=0; -// - Chang VCOCLK_FREQ_MAX and VCOCLK_FREQ_MIN to parameter for simprim (BT1485). -// 06/18/07 - Improve error message for VCO (CR ). Initialize DRP mem (CR ). -// - Add CLKFBIN pulse width check (BT1476). -// 06/28/07 - Initial DRP memory (CR 434042), Error message improve (CR 438250). -// 07/11/07 - change daddr_in to 5 bits (CR 443757). -// 08/02/07 - Remove numbers from CLKOUT DESKEW_ADJUST check (CR443161). -// 08/21/07 - Not check CLKIN period when PMCD mode set (445101). -// Fix DUTY_CYCLE_MAX formula in case of divider larger than O_MAX_HT_LT (CR445945). -// Add warning if phase shift over pll ability (63 vco) (CR446037). -// 09/20/07 - Seperate fb_delay and delay_edge to handle 0 fb_delay (CR448938) -// 10/23/07 - Add warnings to initial phase shift calculation (CR448965) -// 11/01/07 - Remove zero check for CLKOUTx dly register bit15-8 (CR434042) -// 12/06/07 - Add I/O buf to simprim (CR456124) -// End Revision - - -`timescale 1 ps / 1 ps -`define PLL_LOCK_TIME 7 - - -module PLL_ADV ( - CLKFBDCM, - CLKFBOUT, - CLKOUT0, - CLKOUT1, - CLKOUT2, - CLKOUT3, - CLKOUT4, - CLKOUT5, - CLKOUTDCM0, - CLKOUTDCM1, - CLKOUTDCM2, - CLKOUTDCM3, - CLKOUTDCM4, - CLKOUTDCM5, - DO, - DRDY, - LOCKED, - CLKFBIN, - CLKIN1, - CLKIN2, - CLKINSEL, - DADDR, - DCLK, - DEN, - DI, - DWE, - REL, - RST -); - -parameter BANDWIDTH = "OPTIMIZED"; -parameter CLKFBOUT_DESKEW_ADJUST = "NONE"; -parameter CLKOUT0_DESKEW_ADJUST = "NONE"; -parameter CLKOUT1_DESKEW_ADJUST = "NONE"; -parameter CLKOUT2_DESKEW_ADJUST = "NONE"; -parameter CLKOUT3_DESKEW_ADJUST = "NONE"; -parameter CLKOUT4_DESKEW_ADJUST = "NONE"; -parameter CLKOUT5_DESKEW_ADJUST = "NONE"; -parameter integer CLKFBOUT_MULT = 1; -parameter real CLKFBOUT_PHASE = 0.0; -parameter real CLKIN1_PERIOD = 0.000; -parameter real CLKIN2_PERIOD = 0.000; -parameter integer CLKOUT0_DIVIDE = 1; -parameter real CLKOUT0_DUTY_CYCLE = 0.5; -parameter real CLKOUT0_PHASE = 0.0; -parameter integer CLKOUT1_DIVIDE = 1; -parameter real CLKOUT1_DUTY_CYCLE = 0.5; -parameter real CLKOUT1_PHASE = 0.0; -parameter integer CLKOUT2_DIVIDE = 1; -parameter real CLKOUT2_DUTY_CYCLE = 0.5; -parameter real CLKOUT2_PHASE = 0.0; -parameter integer CLKOUT3_DIVIDE = 1; -parameter real CLKOUT3_DUTY_CYCLE = 0.5; -parameter real CLKOUT3_PHASE = 0.0; -parameter integer CLKOUT4_DIVIDE = 1; -parameter real CLKOUT4_DUTY_CYCLE = 0.5; -parameter real CLKOUT4_PHASE = 0.0; -parameter integer CLKOUT5_DIVIDE = 1; -parameter real CLKOUT5_DUTY_CYCLE = 0.5; -parameter real CLKOUT5_PHASE = 0.0; -parameter COMPENSATION = "SYSTEM_SYNCHRONOUS"; -parameter integer DIVCLK_DIVIDE = 1; -parameter EN_REL = "FALSE"; -parameter PLL_PMCD_MODE = "FALSE"; -parameter real REF_JITTER = 0.100; -parameter RESET_ON_LOSS_OF_LOCK = "FALSE"; -parameter RST_DEASSERT_CLK = "CLKIN1"; - -localparam VCOCLK_FREQ_MAX = 1100; -localparam VCOCLK_FREQ_MIN = 400; - -output CLKFBDCM; -output CLKFBOUT; -output CLKOUT0; -output CLKOUT1; -output CLKOUT2; -output CLKOUT3; -output CLKOUT4; -output CLKOUT5; -output CLKOUTDCM0; -output CLKOUTDCM1; -output CLKOUTDCM2; -output CLKOUTDCM3; -output CLKOUTDCM4; -output CLKOUTDCM5; -output DRDY; -output LOCKED; -output [15:0] DO; - -input CLKFBIN; -input CLKIN1; -input CLKIN2; -input CLKINSEL; -input DCLK; -input DEN; -input DWE; -input REL; -input RST; -input [15:0] DI; -input [4:0] DADDR; - -localparam VCOCLK_FREQ_TARGET = 800; -localparam CLKIN_FREQ_MAX = 1000; -localparam CLKIN_FREQ_MIN = 1; //need check speed file, current is TBD -localparam CLKPFD_FREQ_MAX = 550; -localparam CLKPFD_FREQ_MIN = 1; //need check speed file, current is TBD -localparam M_MIN = 1; -localparam M_MAX = 74; -localparam D_MIN = 1; -localparam D_MAX = 52; -localparam O_MIN = 1; -localparam O_MAX = 128; -localparam O_MAX_HT_LT = 64; -localparam REF_CLK_JITTER_MAX = 350; -localparam REF_CLK_JITTER_SCALE = 0.1; -localparam MAX_FEEDBACK_DELAY = 10.0; -localparam MAX_FEEDBACK_DELAY_SCALE = 1.0; - -tri0 GSR = glbl.GSR; - -reg [4:0] daddr_lat; -reg valid_daddr; -reg drdy_out; -reg drp_lock, drp_lock1; -reg [15:0] dr_sram [31:0]; -reg [160:0] tmp_string; - -wire CLKFBIN, CLKIN1, CLKIN2, CLKINSEL ; -wire rst_in, RST, orig_rst_in ; -wire locked_out; -wire clkvco_lk_rst; - -reg clk0_out, clk1_out, clk2_out, clk3_out, clk4_out, clk5_out; -reg clkfb_out, clkfbm1_out; -reg clkout_en, clkout_en1, clkout_en0, clkout_en0_tmp; -integer clkout_cnt, clkin_cnt, clkin_lock_cnt; -integer clkout_en_time, locked_en_time, lock_cnt_max; -reg clkvco_lk, clkvco_free, clkvco; -reg fbclk_tmp; - -reg rst_in1, rst_unlock, rst_on_loss; -time rst_edge, rst_ht; - -reg fb_delay_found, fb_delay_found_tmp; -reg clkfb_tst; -real fb_delay_max; -time fb_delay, clkvco_delay, val_tmp, dly_tmp, fbm1_comp_delay; -time clkin_edge, delay_edge; - -real period_clkin; -integer clkin_period [4:0]; -integer period_vco, period_vco_half, period_vco_max, period_vco_min; -integer period_vco1, period_vco2, period_vco3, period_vco4; -integer period_vco5, period_vco6, period_vco7; -integer period_vco_target, period_vco_target_half; -integer period_fb, period_avg; - -real clkvco_freq_init_chk, clkfbm1pm_rl; -real tmp_real; -integer i, j, i1, i2; -integer md_product, md_product_dbl, clkin_stop_max, clkfb_stop_max; - -time pll_locked_delay, clkin_dly_t, clkfb_dly_t; -reg clkpll_dly, clkfbin_dly; -wire pll_unlock; -reg pll_locked_tmp1, pll_locked_tmp2; -reg lock_period; -reg pll_locked_tm, unlock_recover; -reg clkin_stopped_p, clkin_stopped_n; -reg clkfb_stopped_p, clkfb_stopped_n; -wire clkin_stopped, clkfb_stopped; -reg clkpll_jitter_unlock; -integer clkstop_cnt_p, clkstop_cnt_n, clkfbstop_cnt_p, clkfbstop_cnt_n; -integer clkin_jit, REF_CLK_JITTER_MAX_tmp; - -wire REL, DWE, DEN, DCLK, rel_o_mux_clk_tmp, clka1_in, clkb1_in; -wire init_trig, clkpll_tmp, clkpll, clk0in, clk1in, clk2in, clk3in, clk4in, clk5in; -wire clkfbm1in, clkfbm1ps_en; - - -reg clkout0_out; -reg clkout1_out; -reg clkout2_out; -reg clkout3_out; -reg clkout4_out; -reg clkout5_out; - -reg clka1_out, clkb1_out, clka1d2_out, clka1d4_out, clka1d8_out; -reg clkdiv_rel_rst, qrel_o_reg1, qrel_o_reg2, qrel_o_reg3, rel_o_mux_sel; -reg pmcd_mode; -reg chk_ok; - -wire rel_rst_o, rel_o_mux_clk; -wire clk0ps_en, clk1ps_en, clk2ps_en, clk3ps_en, clk4ps_en, clk5ps_en; - -reg [7:0] clkout_mux; -reg [2:0] clk0pm_sel, clk1pm_sel, clk2pm_sel, clk3pm_sel, clk4pm_sel, clk5pm_sel; -reg [2:0] clkfbm1pm_sel; -reg clk0_edge, clk1_edge, clk2_edge, clk3_edge, clk4_edge, clk5_edge; -reg clkfbm1_edge, clkind_edge; -reg clk0_nocnt, clk1_nocnt, clk2_nocnt, clk3_nocnt, clk4_nocnt, clk5_nocnt; -reg clkfbm1_nocnt, clkind_nocnt; -reg clkind_edget, clkind_nocntt; -reg [5:0] clk0_dly_cnt, clkout0_dly; -reg [5:0] clk1_dly_cnt, clkout1_dly; -reg [5:0] clk2_dly_cnt, clkout2_dly; -reg [5:0] clk3_dly_cnt, clkout3_dly; -reg [5:0] clk4_dly_cnt, clkout4_dly; -reg [5:0] clk5_dly_cnt, clkout5_dly; -reg [6:0] clk0_ht, clk0_lt; -reg [6:0] clk1_ht, clk1_lt; -reg [6:0] clk2_ht, clk2_lt; -reg [6:0] clk3_ht, clk3_lt; -reg [6:0] clk4_ht, clk4_lt; -reg [6:0] clk5_ht, clk5_lt; -reg [5:0] clkfbm1_dly_cnt, clkfbm1_dly; -reg [6:0] clkfbm1_ht, clkfbm1_lt; -reg [7:0] clkind_ht, clkind_lt; -reg [7:0] clkind_htt, clkind_ltt; -reg [7:0] clk0_ht1, clk0_cnt, clk0_div, clk0_div1; -reg [7:0] clk1_ht1, clk1_cnt, clk1_div, clk1_div1; -reg [7:0] clk2_ht1, clk2_cnt, clk2_div, clk2_div1; -reg [7:0] clk3_ht1, clk3_cnt, clk3_div, clk3_div1; -reg [7:0] clk4_ht1, clk4_cnt, clk4_div, clk4_div1; -reg [7:0] clk5_ht1, clk5_cnt, clk5_div, clk5_div1; -reg [7:0] clkfbm1_ht1, clkfbm1_cnt, clkfbm1_div, clkfbm1_div1; -reg [7:0] clkind_div; -reg [3:0] pll_cp, pll_res; -reg [1:0] pll_lfhf; -reg [1:0] pll_cpres = 2'b01; - -reg notifier; -wire [15:0] do_out, di_in; -wire clkin1_in, clkin2_in, clkfb_in, clkinsel_in, dwe_in, den_in, dclk_in; -wire [4:0] daddr_in; -wire rel_in, gsr_in, rst_input; - - assign #100 LOCKED = locked_out; - assign #100 DRDY = drdy_out; - assign #100 DO = do_out; - assign clkin1_in = CLKIN1; - assign clkin2_in = CLKIN2; - assign clkfb_in = CLKFBIN; - assign clkinsel_in = CLKINSEL; - assign rst_input = RST; - assign daddr_in = DADDR; - assign di_in = DI; - assign dwe_in = DWE; - assign den_in = DEN; - assign dclk_in = DCLK; - assign rel_in = REL; - - - -initial begin - #1; - if ($realtime == 0) begin - $display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps."); - $display ("In order to simulate the PLL_ADV, the simulator resolution must be set to 1ps or smaller."); - $finish; - end -end - -initial begin - - case (COMPENSATION) - "SYSTEM_SYNCHRONOUS" : ; - "SOURCE_SYNCHRONOUS" : ; - "INTERNAL" : ; - "EXTERNAL" : ; - "DCM2PLL" : ; - "PLL2DCM" : ; - default : begin - $display("Attribute Syntax Error : The Attribute COMPENSATION on PLL_ADV instance %m is set to %s. Legal values for this attribute are SYSTEM_SYNCHRONOUS, SOURCE_SYNCHRONOUS, INTERNAL, EXTERNAL, DCM2PLL or PLL2DCM.", COMPENSATION); - $finish; - end - endcase - - case (BANDWIDTH) - "HIGH" : ; - "LOW" : ; - "OPTIMIZED" : ; - default : begin - $display("Attribute Syntax Error : The Attribute BANDWIDTH on PLL_ADV instance %m is set to %s. Legal values for this attribute are HIGH, LOW or OPTIMIZED.", BANDWIDTH); - $finish; - end - endcase - - case (CLKOUT0_DESKEW_ADJUST) - "NONE" : ; - "PPC" : ; - default : begin - $display("Attribute Syntax Error : The Attribute CLKOUT0_DESKEW_ADJUST on PLL_ADV instance %m is set to %s. Legal values for this attribute are NONE or PPC.", CLKOUT0_DESKEW_ADJUST); - $finish; - end - endcase - - case (CLKOUT1_DESKEW_ADJUST) - "NONE" : ; - "PPC" : ; - default : begin - $display("Attribute Syntax Error : The Attribute CLKOUT1_DESKEW_ADJUST on PLL_ADV instance %m is set to %s. Legal values for this attribute are NONE or PPC .", CLKOUT1_DESKEW_ADJUST); - $finish; - end - endcase - - case (CLKOUT2_DESKEW_ADJUST) - "NONE" : ; - "PPC" : ; - default : begin - $display("Attribute Syntax Error : The Attribute CLKOUT2_DESKEW_ADJUST on PLL_ADV instance %m is set to %s. Legal values for this attribute are NONE or PPC.", CLKOUT2_DESKEW_ADJUST); - $finish; - end - endcase - - case (CLKOUT3_DESKEW_ADJUST) - "NONE" : ; - "PPC" : ; - default : begin - $display("Attribute Syntax Error : The Attribute CLKOUT3_DESKEW_ADJUST on PLL_ADV instance %m is set to %s. Legal values for this attribute are NONE or PPC.", CLKOUT3_DESKEW_ADJUST); - $finish; - end - endcase - - case (CLKOUT4_DESKEW_ADJUST) - "NONE" : ; - "PPC" : ; - default : begin - $display("Attribute Syntax Error : The Attribute CLKOUT4_DESKEW_ADJUST on PLL_ADV instance %m is set to %s. Legal values for this attribute are NONE or PPC.", CLKOUT4_DESKEW_ADJUST); - $finish; - end - endcase - - case (CLKOUT5_DESKEW_ADJUST) - "NONE" : ; - "PPC" : ; - default : begin - $display("Attribute Syntax Error : The Attribute CLKOUT5_DESKEW_ADJUST on PLL_ADV instance %m is set to %s. Legal values for this attribute are NONE or PPC.", CLKOUT5_DESKEW_ADJUST); - $finish; - end - endcase - - case (CLKFBOUT_DESKEW_ADJUST) - "NONE" : ; - "PPC" : ; - default : begin - $display("Attribute Syntax Error : The Attribute CLKFBOUT_DESKEW_ADJUST on PLL_ADV instance %m is set to %s. Legal values for this attribute are NONE or PPC.", CLKFBOUT_DESKEW_ADJUST); - $finish; - end - endcase - - - case (PLL_PMCD_MODE) - "TRUE" : pmcd_mode = 1'b1; - "FALSE" : pmcd_mode = 1'b0; - default : begin - $display("Attribute Syntax Error : The Attribute PLL_PMCD_MODE on PLL_ADV instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", PLL_PMCD_MODE); - $finish; - end - endcase - - tmp_string = "CLKOUT0_DIVIDE"; - chk_ok = para_int_pmcd_chk(CLKOUT0_DIVIDE, tmp_string, 1, 128, pmcd_mode, 8); - tmp_string = "CLKOUT0_PHASE"; - chk_ok = para_real_pmcd_chk(CLKOUT0_PHASE, tmp_string, -360.0, 360.0, pmcd_mode, 0.0); - tmp_string = "CLKOUT0_DUTY_CYCLE"; - chk_ok = para_real_pmcd_chk(CLKOUT0_DUTY_CYCLE, tmp_string, 0.0, 1.0, pmcd_mode, 0.5); - - tmp_string = "CLKOUT1_DIVIDE"; - chk_ok = para_int_pmcd_chk(CLKOUT1_DIVIDE, tmp_string, 1, 128, pmcd_mode, 4); - tmp_string = "CLKOUT1_PHASE"; - chk_ok = para_real_pmcd_chk(CLKOUT1_PHASE, tmp_string, -360.0, 360.0, pmcd_mode, 0.0); - tmp_string = "CLKOUT1_DUTY_CYCLE"; - chk_ok = para_real_pmcd_chk(CLKOUT1_DUTY_CYCLE, tmp_string, 0.0, 1.0, pmcd_mode, 0.5); - - tmp_string = "CLKOUT2_DIVIDE"; - chk_ok = para_int_pmcd_chk(CLKOUT2_DIVIDE, tmp_string, 1, 128, pmcd_mode, 2); - tmp_string = "CLKOUT2_PHASE"; - chk_ok = para_real_pmcd_chk(CLKOUT2_PHASE, tmp_string, -360.0, 360.0, pmcd_mode, 0.0); - tmp_string = "CLKOUT2_DUTY_CYCLE"; - chk_ok = para_real_pmcd_chk(CLKOUT2_DUTY_CYCLE, tmp_string, 0.0, 1.0, pmcd_mode, 0.5); - - tmp_string = "CLKOUT3_DIVIDE"; - chk_ok = para_int_pmcd_chk(CLKOUT3_DIVIDE, tmp_string, 1, 128, pmcd_mode, 1); - tmp_string = "CLKOUT3_PHASE"; - chk_ok = para_real_pmcd_chk(CLKOUT3_PHASE, tmp_string, -360.0, 360.0, pmcd_mode, 0.0); - tmp_string = "CLKOUT3_DUTY_CYCLE"; - chk_ok = para_real_pmcd_chk(CLKOUT3_DUTY_CYCLE, tmp_string, 0.0, 1.0, pmcd_mode, 0.5); - - tmp_string = "CLKOUT4_DIVIDE"; - chk_ok = para_int_range_chk(CLKOUT4_DIVIDE, tmp_string, 1, 128); - tmp_string = "CLKOUT4_PHASE"; - chk_ok = para_real_range_chk(CLKOUT4_PHASE, tmp_string, -360.0, 360.0); - tmp_string = "CLKOUT4_DUTY_CYCLE"; - chk_ok = para_real_range_chk(CLKOUT4_DUTY_CYCLE, tmp_string, 0.0, 1.0); - - tmp_string = "CLKOUT5_DIVIDE"; - chk_ok = para_int_range_chk (CLKOUT5_DIVIDE, tmp_string, 1, 128); - tmp_string = "CLKOUT5_PHASE"; - chk_ok = para_real_range_chk(CLKOUT5_PHASE, tmp_string, -360.0, 360.0); - tmp_string = "CLKOUT5_DUTY_CYCLE"; - chk_ok = para_real_range_chk (CLKOUT5_DUTY_CYCLE, tmp_string, 0.0, 1.0); - - tmp_string = "CLKFBOUT_MULT"; - chk_ok = para_int_pmcd_chk(CLKFBOUT_MULT, tmp_string, 1, 74, pmcd_mode, 1); - tmp_string = "CLKFBOUT_PHASE"; - chk_ok = para_real_pmcd_chk(CLKFBOUT_PHASE, tmp_string, -360.0, 360.0, pmcd_mode, 0.0); - tmp_string = "DIVCLK_DIVIDE"; - chk_ok = para_int_range_chk (DIVCLK_DIVIDE, tmp_string, 1, 52); - - tmp_string = "REF_JITTER"; - chk_ok = para_real_range_chk (REF_JITTER, tmp_string, 0.0, 0.999); - if (((CLKIN1_PERIOD < 1.0) || (CLKIN1_PERIOD > 52.630)) && (pmcd_mode == 0)) begin - $display("Attribute Syntax Error : CLKIN1_PERIOD is not in range 1.0 ... 52.630."); - end - - if (((CLKIN2_PERIOD < 1.0) || (CLKIN2_PERIOD > 52.630)) && (pmcd_mode == 0)) begin - $display("Attribute Syntax Error : CLKIN1_PERIOD is not in range 1.0 ... 52.630."); - end - - - case (RESET_ON_LOSS_OF_LOCK) - "FALSE" : rst_on_loss = 1'b0; -// "TRUE" : if (pmcd_mode) rst_on_loss = 1'b0; else rst_on_loss = 1'b1; - default : begin - $display("Attribute Syntax Error : The Attribute RESET_ON_LOSS_OF_LOCK on PLL_ADV instance %m is set to %s. This attribute must always be set to FALSE for X_PLL_ADV to function correctly. Please correct the setting for the attribute and re-run the simulation.", RESET_ON_LOSS_OF_LOCK); - $finish; - end - endcase - - case (CLKFBOUT_MULT) - 1 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1101; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b0101; pll_res = 4'b1111; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0101; pll_res = 4'b1111; pll_lfhf = 2'b11; end - 2 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1110; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b1111; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b1111; pll_lfhf = 2'b11; end - 3 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0110; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b0111; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0110; pll_res = 4'b0101; pll_lfhf = 2'b11; end - 4 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1010; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1101; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0111; pll_res = 4'b1001; pll_lfhf = 2'b11; end - 5 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1100; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b0101; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1101; pll_res = 4'b1001; pll_lfhf = 2'b11; end - 6 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1100; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b0101; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0111; pll_res = 4'b0001; pll_lfhf = 2'b11; end - 7 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1100; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1001; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b0001; pll_lfhf = 2'b11; end - 8 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0010; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1110; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1110; pll_lfhf = 2'b11; end - 9 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0010; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1110; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b0001; pll_lfhf = 2'b11; end - 10 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b0001; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b0001; pll_lfhf = 2'b11; end - 11 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b0001; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1101; pll_res = 4'b0110; pll_lfhf = 2'b11; end - 12 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b0110; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b0110; pll_lfhf = 2'b11; end - 13 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b0110; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b0110; pll_lfhf = 2'b11; end - 14 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b0110; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b0110; pll_lfhf = 2'b11; end - 15 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b1010; pll_lfhf = 2'b11; end - else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b1010; pll_lfhf = 2'b11; end - 16 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b1010; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b1010; pll_lfhf = 2'b11; end - 17 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1010; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; pll_lfhf = 2'b11; end - 18 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1010; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; pll_lfhf = 2'b11; end - 19 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1010; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; pll_lfhf = 2'b11; end - 20 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1010; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b1100; pll_lfhf = 2'b11; end - 21 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1010; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b1100; pll_lfhf = 2'b11; end - 22 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1101; pll_res = 4'b1100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1101; pll_res = 4'b1100; pll_lfhf = 2'b11; end - 23 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1101; pll_res = 4'b1100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1101; pll_res = 4'b1100; pll_lfhf = 2'b11; end - 24 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1101; pll_res = 4'b1100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0111; pll_res = 4'b0010; pll_lfhf = 2'b11; end - 25 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b1100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b1100; pll_lfhf = 2'b11; end - 26 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b1100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b1100; pll_lfhf = 2'b11; end - 27 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1100; pll_lfhf = 2'b11; end - 28 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b1100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b0010; pll_lfhf = 2'b11; end - 29 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b1100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b0010; pll_lfhf = 2'b11; end - 30 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b1100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b0010; pll_lfhf = 2'b11; end - 31 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1100; pll_res = 4'b0010; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b0010; pll_lfhf = 2'b11; end - 32 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1100; pll_res = 4'b0010; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b0010; pll_lfhf = 2'b11; end - 33 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1010; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end - 34 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0111; pll_res = 4'b0010; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end - 35 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0111; pll_res = 4'b0010; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end - 36 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0111; pll_res = 4'b0010; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end - 37 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0110; pll_res = 4'b0010; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end - 38 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0110; pll_res = 4'b0010; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end - 39 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end - 40 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 41 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 42 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 43 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 44 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 45 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 46 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 47 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0101; pll_res = 4'b0010; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 48 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0101; pll_res = 4'b0010; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 49 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 50 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 51 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 52 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 53 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 54 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 55 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end - 56 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end - 57 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 58 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 59 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 60 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 61 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 62 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 63 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - 64 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end - endcase - - - tmp_string = "DIVCLK_DIVIDE"; - chk_ok = para_int_range_chk (DIVCLK_DIVIDE, tmp_string, D_MIN, D_MAX); - - tmp_string = "CLKFBOUT_MULT"; - chk_ok = para_int_range_chk (CLKFBOUT_MULT, tmp_string, M_MIN, M_MAX); - - tmp_string = "CLKOUT0_DUTY_CYCLE"; - chk_ok = clkout_duty_chk (CLKOUT0_DIVIDE, CLKOUT0_DUTY_CYCLE, tmp_string); - tmp_string = "CLKOUT1_DUTY_CYCLE"; - chk_ok = clkout_duty_chk (CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE, tmp_string); - tmp_string = "CLKOUT2_DUTY_CYCLE"; - chk_ok = clkout_duty_chk (CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE, tmp_string); - tmp_string = "CLKOUT3_DUTY_CYCLE"; - chk_ok = clkout_duty_chk (CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE, tmp_string); - tmp_string = "CLKOUT4_DUTY_CYCLE"; - chk_ok = clkout_duty_chk (CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE, tmp_string); - tmp_string = "CLKOUT5_DUTY_CYCLE"; - chk_ok = clkout_duty_chk (CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE, tmp_string); - - period_vco_max = 1000000 / VCOCLK_FREQ_MIN; - period_vco_min = 1000000 / VCOCLK_FREQ_MAX; - period_vco_target = 1000000 / VCOCLK_FREQ_TARGET; - period_vco_target_half = period_vco_target / 2; - fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE; - md_product = CLKFBOUT_MULT * DIVCLK_DIVIDE; - md_product_dbl = md_product * 2; - clkout_en_time = `PLL_LOCK_TIME + 2; -// locked_en_time = md_product_dbl + clkout_en_time +2; // for DCM 3 cycle reset requirement - locked_en_time = md_product + clkout_en_time + 2; // for DCM 3 cycle reset requirement - lock_cnt_max = locked_en_time + 6; - clkfb_stop_max = 3; - clkin_stop_max = DIVCLK_DIVIDE + 1; - REF_CLK_JITTER_MAX_tmp = REF_CLK_JITTER_MAX; - - clk_out_para_cal (clk0_ht, clk0_lt, clk0_nocnt, clk0_edge, CLKOUT0_DIVIDE, CLKOUT0_DUTY_CYCLE); - clk_out_para_cal (clk1_ht, clk1_lt, clk1_nocnt, clk1_edge, CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE); - clk_out_para_cal (clk2_ht, clk2_lt, clk2_nocnt, clk2_edge, CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE); - clk_out_para_cal (clk3_ht, clk3_lt, clk3_nocnt, clk3_edge, CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE); - clk_out_para_cal (clk4_ht, clk4_lt, clk4_nocnt, clk4_edge, CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE); - clk_out_para_cal (clk5_ht, clk5_lt, clk5_nocnt, clk5_edge, CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE); - clk_out_para_cal (clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge, CLKFBOUT_MULT, 0.50); - clk_out_para_cal (clkind_ht, clkind_lt, clkind_nocnt, clkind_edge, DIVCLK_DIVIDE, 0.50); - tmp_string = "CLKOUT0_PHASE"; - clkout_dly_cal (clkout0_dly, clk0pm_sel, CLKOUT0_DIVIDE, CLKOUT0_PHASE, tmp_string); - tmp_string = "CLKOUT1_PHASE"; - clkout_dly_cal (clkout1_dly, clk1pm_sel, CLKOUT1_DIVIDE, CLKOUT1_PHASE, tmp_string); - tmp_string = "CLKOUT2_PHASE"; - clkout_dly_cal (clkout2_dly, clk2pm_sel, CLKOUT2_DIVIDE, CLKOUT2_PHASE, tmp_string); - tmp_string = "CLKOUT3_PHASE"; - clkout_dly_cal (clkout3_dly, clk3pm_sel, CLKOUT3_DIVIDE, CLKOUT3_PHASE, tmp_string); - tmp_string = "CLKOUT4_PHASE"; - clkout_dly_cal (clkout4_dly, clk4pm_sel, CLKOUT4_DIVIDE, CLKOUT4_PHASE, tmp_string); - tmp_string = "CLKOUT5_PHASE"; - clkout_dly_cal (clkout5_dly, clk5pm_sel, CLKOUT5_DIVIDE, CLKOUT5_PHASE, tmp_string); - tmp_string = "CLKFBOUT_PHASE"; - clkout_dly_cal (clkfbm1_dly, clkfbm1pm_sel, CLKFBOUT_MULT, CLKFBOUT_PHASE, tmp_string); - - clkind_div = DIVCLK_DIVIDE; - - dr_sram[5'b11100] = {8'bx, clk0_edge, clk0_nocnt, clkout0_dly[5:0]}; - dr_sram[5'b11011] = {clk0pm_sel[2:0], 1'b1, clk0_ht[5:0], clk0_lt[5:0]}; - dr_sram[5'b11010] = {8'bx, clk1_edge, clk1_nocnt, clkout1_dly[5:0]}; - dr_sram[5'b11001] = {clk1pm_sel[2:0], 1'b1, clk1_ht[5:0], clk1_lt[5:0]}; - dr_sram[5'b10111] = {8'bx, clk2_edge, clk2_nocnt, clkout2_dly[5:0]}; - dr_sram[5'b10110] = {clk2pm_sel[2:0], 1'b1, clk2_ht[5:0], clk2_lt[5:0]}; - dr_sram[5'b10101] = {8'bx, clk3_edge, clk3_nocnt, clkout3_dly[5:0]}; - dr_sram[5'b10100] = {clk3pm_sel[2:0], 1'b1, clk3_ht[5:0], clk3_lt[5:0]}; - dr_sram[5'b10011] = {8'bx, clk4_edge, clk4_nocnt, clkout4_dly[5:0]}; - dr_sram[5'b10010] = {clk4pm_sel[2:0], 1'b1, clk4_ht[5:0], clk4_lt[5:0]}; - dr_sram[5'b01111] = {8'bx, clk5_edge, clk5_nocnt, clkout5_dly[5:0]}; - dr_sram[5'b01110] = {clk5pm_sel[2:0], 1'b1, clk5_ht[5:0], clk5_lt[5:0]}; - dr_sram[5'b01101] = {8'bx, clkfbm1_edge, clkfbm1_nocnt, clkfbm1_dly[5:0]}; - dr_sram[5'b01100] = {clkfbm1pm_sel[2:0], 1'b1, clkfbm1_ht[5:0], clkfbm1_lt[5:0]}; - dr_sram[5'b00110] = {2'bx, clkind_edge, clkind_nocnt, clkind_ht[5:0], clkind_lt[5:0]}; - dr_sram[5'b00001] = {8'bx, pll_lfhf, pll_cpres, pll_cp}; - dr_sram[5'b00000] = {6'bx, pll_res, 6'bx}; - - -// **** PMCD ******* - -//*** Clocks MUX - - case (RST_DEASSERT_CLK) - "CLKIN1" : rel_o_mux_sel = 1'b1; - "CLKFBIN" : rel_o_mux_sel = 1'b0; - default : begin - $display("Attribute Syntax Error : The attribute RST_DEASSERT_CLK on PLL_ADV instance %m is set to %s. Legal values for this attribute are CLKIN1 and CLKFBIN.", RST_DEASSERT_CLK); - $finish; - end - endcase - -//*** CLKDIV_RST - case (EN_REL) - "FALSE" : clkdiv_rel_rst = 1'b0; - "TRUE" : clkdiv_rel_rst = 1'b1; - default : begin - $display("Attribute Syntax Error : The attribute EN_REL on PLL_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_REL); - $finish; - end - endcase - - -end - -initial begin - rst_in1 = 0; - rst_unlock = 0; - clkin_period[0] = 0; - clkin_period[1] = 0; - clkin_period[2] = 0; - clkin_period[3] = 0; - clkin_period[4] = 0; - period_avg = 0; - period_fb = 0; - fb_delay = 0; - clkfbm1_div = 1; - clkfbm1_div1 = 0; - clkvco_delay = 0; - fbm1_comp_delay = 0; - clkfbm1pm_rl = 0; - period_vco = 0; - period_vco1 = 0; - period_vco2 = 0; - period_vco3 = 0; - period_vco4 = 0; - period_vco5 = 0; - period_vco6 = 0; - period_vco7 = 0; - period_vco_half = 0; - fb_delay_found = 0; - fb_delay_found_tmp = 0; - clkin_edge = 0; - delay_edge = 0; - clkvco_free = 0; - clkvco_lk = 0; - fbclk_tmp = 0; - clkfb_tst = 0; - clkout_cnt = 0; - clkout_en = 0; - clkout_en0 = 0; - clkout_en0_tmp = 0; - clkout_en1 = 0; - pll_locked_tmp1 = 0; - pll_locked_tmp2 = 0; - pll_locked_tm = 0; - pll_locked_delay = 0; - clkout_mux = 3'b0; - unlock_recover = 0; - clkstop_cnt_p = 0; - clkstop_cnt_n = 0; - clkpll_jitter_unlock = 0; - clkin_jit = 0; - clkin_cnt = 0; - clkin_lock_cnt = 0; - clkin_stopped_p = 0; - clkin_stopped_n = 0; - clkfb_stopped_p = 0; - clkfb_stopped_n = 0; - clkpll_dly = 0; - clkfbin_dly = 0; - clkfbstop_cnt_p = 0; - clkfbstop_cnt_n = 0; - lock_period = 0; - rst_edge = 0; - rst_ht = 0; - drdy_out = 0; - drp_lock = 0; - clkout0_out = 0; - clkout1_out = 0; - clkout2_out = 0; - clkout3_out = 0; - clkout4_out = 0; - clkout5_out = 0; - clka1_out = 1'b0; - clkb1_out = 1'b0; - clka1d2_out = 1'b0; - clka1d4_out = 1'b0; - clka1d8_out = 1'b0; - qrel_o_reg1 = 1'b0; - qrel_o_reg2 = 1'b0; - qrel_o_reg3 = 1'b0; - clk0_dly_cnt = 6'b0; - clk1_dly_cnt = 6'b0; - clk2_dly_cnt = 6'b0; - clk3_dly_cnt = 6'b0; - clk4_dly_cnt = 6'b0; - clk5_dly_cnt = 6'b0; - clkfbm1_dly_cnt = 6'b0; - clk0_cnt = 8'b0; - clk1_cnt = 8'b0; - clk2_cnt = 8'b0; - clk3_cnt = 8'b0; - clk4_cnt = 8'b0; - clk5_cnt = 8'b0; - clkfbm1_cnt = 8'b0; - clk0_out = 0; - clk1_out = 0; - clk2_out = 0; - clk3_out = 0; - clk4_out = 0; - clk5_out = 0; - clkfb_out = 0; - clkfbm1_out = 0; -end - -// PMCD function - -//*** asyn RST - always @(orig_rst_in) - if (orig_rst_in == 1'b1) begin - assign qrel_o_reg1 = 1'b1; - assign qrel_o_reg2 = 1'b1; - assign qrel_o_reg3 = 1'b1; - end - else if (orig_rst_in == 1'b0) begin - deassign qrel_o_reg1; - deassign qrel_o_reg2; - deassign qrel_o_reg3; - end - -//*** Clocks MUX - - assign rel_o_mux_clk_tmp = rel_o_mux_sel ? clkin1_in : clkfb_in; - assign rel_o_mux_clk = (pmcd_mode) ? rel_o_mux_clk_tmp : 0; - assign clka1_in = (pmcd_mode) ? clkin1_in : 0; - assign clkb1_in = (pmcd_mode) ? clkfb_in : 0; - - -//*** Rel and Rst - always @(posedge rel_o_mux_clk) - qrel_o_reg1 <= 1'b0; - - always @(negedge rel_o_mux_clk) - qrel_o_reg2 <= qrel_o_reg1; - - always @(posedge rel_in) - qrel_o_reg3 <= 1'b0; - - assign rel_rst_o = clkdiv_rel_rst ? (qrel_o_reg3 || qrel_o_reg1) : qrel_o_reg1; - -//*** CLKA - always @(clka1_in or qrel_o_reg2) - if (qrel_o_reg2 == 1'b1) - clka1_out <= 1'b0; - else if (qrel_o_reg2 == 1'b0) - clka1_out <= clka1_in; - -//*** CLKB - always @(clkb1_in or qrel_o_reg2) - if (qrel_o_reg2 == 1'b1) - clkb1_out <= 1'b0; - else if (qrel_o_reg2 == 1'b0) - clkb1_out <= clkb1_in; - - -//*** Clock divider - always @(posedge clka1_in or posedge rel_rst_o) - if (rel_rst_o == 1'b1) - clka1d2_out <= 1'b0; - else if (rel_rst_o == 1'b0) - clka1d2_out <= ~clka1d2_out; - - always @(posedge clka1d2_out or posedge rel_rst_o) - if (rel_rst_o == 1'b1) - clka1d4_out <= 1'b0; - else if (rel_rst_o == 1'b0) - clka1d4_out <= ~clka1d4_out; - - always @(posedge clka1d4_out or posedge rel_rst_o) - if (rel_rst_o == 1'b1) - clka1d8_out <= 1'b0; - else if (rel_rst_o == 1'b0) - clka1d8_out <= ~clka1d8_out; - - assign CLKOUT5 = (pmcd_mode) ? 0 : clkout5_out; - assign CLKOUT4 = (pmcd_mode) ? 0 : clkout4_out; - assign CLKOUT3 = (pmcd_mode) ? clka1_out : clkout3_out; - assign CLKOUT2 = (pmcd_mode) ? clka1d2_out : clkout2_out; - assign CLKOUT1 = (pmcd_mode) ? clka1d4_out : clkout1_out; - assign CLKOUT0 = (pmcd_mode) ? clka1d8_out : clkout0_out; - assign CLKFBOUT = (pmcd_mode) ? clkb1_out : clkfb_out; - assign CLKOUTDCM5 = (pmcd_mode) ? 0 : clkout5_out; - assign CLKOUTDCM4 = (pmcd_mode) ? 0 : clkout4_out; - assign CLKOUTDCM3 = (pmcd_mode) ? clka1_out : clkout3_out; - assign CLKOUTDCM2 = (pmcd_mode) ? clka1d2_out : clkout2_out; - assign CLKOUTDCM1 = (pmcd_mode) ? clka1d4_out : clkout1_out; - assign CLKOUTDCM0 = (pmcd_mode) ? clka1d8_out : clkout0_out; - assign CLKFBDCM = (pmcd_mode) ? clkb1_out : clkfb_out; - -// PLL function - -always @(clkinsel_in ) - if (pmcd_mode != 1) begin - if ($time >1 && rst_in != 1'b1) begin - $display("Input Error : PLL input clock can only be switched when RST=1. CLKINSEL on instance %m at time %t changed when RST low, should change at RST high.", $time); - $finish; - end - if (clkinsel_in ==1) begin - if (CLKIN1_PERIOD > (1000.0 /CLKIN_FREQ_MIN) || CLKIN1_PERIOD < (1000.0 / CLKIN_FREQ_MAX)) begin - $display (" Attribute Syntax Error : The attribute CLKIN1_PERIOD is set to %f ns and out the allowed range %f ns to %f ns.", CLKIN1_PERIOD, 1000.0/CLKIN_FREQ_MAX, 1000.0/CLKIN_FREQ_MIN); - $finish; - end - end - else if (clkinsel_in ==0) begin - if (CLKIN2_PERIOD > (1000.0 /CLKIN_FREQ_MIN) || CLKIN2_PERIOD < (1000.0 / CLKIN_FREQ_MAX)) begin - $display (" Attribute Syntax Error : The attribute CLKIN2_PERIOD is set to %f ns and out the allowed range %f ns to %f ns.", CLKIN2_PERIOD, 1000.0/CLKIN_FREQ_MAX, 1000.0/CLKIN_FREQ_MIN); - $finish; - end - end - - period_clkin = (clkinsel_in) ? CLKIN1_PERIOD : CLKIN2_PERIOD; - clkvco_freq_init_chk = 1000.0 * CLKFBOUT_MULT / (period_clkin * DIVCLK_DIVIDE); - - if (clkvco_freq_init_chk > VCOCLK_FREQ_MAX || clkvco_freq_init_chk < VCOCLK_FREQ_MIN) begin - $display (" Attribute Syntax Error : The calculation of VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT / (DIVCLK_DIVIDE * CLKIN_PERIOD). Please adjust the attributes to the permitted VCO frequency range.", clkvco_freq_init_chk, VCOCLK_FREQ_MIN, VCOCLK_FREQ_MAX); - $finish; - end -end - - assign init_trig = 1; - - - assign clkpll_tmp = (clkinsel_in) ? clkin1_in : clkin2_in; - assign clkpll = (pmcd_mode) ? 0 : clkpll_tmp; - - assign orig_rst_in = rst_input; - -always @(posedge clkpll or posedge orig_rst_in) - if (orig_rst_in) - rst_in1 <= 1; - else - rst_in1 <= orig_rst_in; - - assign rst_in = (rst_in1 || rst_unlock); - - always @(posedge pll_unlock) - if (rst_on_loss ) begin - rst_unlock <= 1'b1; - rst_unlock <= #10000 1'b0; - end - -always @(rst_input ) - if (rst_input==1) - rst_edge = $time; - else if (rst_input==0 && rst_edge > 1) begin - rst_ht = $time - rst_edge; - if (rst_ht < 10000) - $display("Input Error : RST on instance %m at time %t must be asserted at least for 10 ns.", $time); - end - -// -// DRP port read and write -// - - assign do_out = dr_sram[daddr_lat]; - -always @(posedge dclk_in or posedge gsr_in) - if (gsr_in == 1) begin - drp_lock <= 0; - end - else begin - if (den_in == 1) begin - valid_daddr = addr_is_valid(daddr_in); - if (drp_lock == 1) begin - $display(" Warning : DEN is high at PLL_ADV instance %m at time %t. Need wait for DRDY signal before next read/write operation through DRP. ", $time); - $finish; - end - else begin - drp_lock <= 1; - daddr_lat <= daddr_in; - end - - if (valid_daddr && ( daddr_in == 5'b00110 || daddr_in == 5'b00001 || daddr_in == 5'b00000 || - (daddr_in >= 5'b01100 && daddr_in <= 5'b11100 && daddr_in != 5'b10000 && - daddr_in != 5'b10001 && daddr_in != 5'b11000 ))) begin - end - else begin - $display(" Warning : Address DADDR=%b is unsupported at PLL_ADV instance %m at time %t. ", DADDR, $time); - end - - if (dwe_in == 1) begin // write process - if (rst_input == 1) begin - if (valid_daddr && ( daddr_in == 5'b00110 || daddr_in == 5'b00001 || daddr_in == 5'b00000 || - (daddr_in >= 5'b01100 && daddr_in <= 5'b11100 && daddr_in != 5'b10000 && - daddr_in != 5'b10001 && daddr_in != 5'b11000 ))) begin - dr_sram[daddr_in] <= di_in; - end - - if (daddr_in == 5'b11100) - clkout_delay_para_drp (clkout0_dly, clk0_nocnt, clk0_edge, di_in, daddr_in); - - if (daddr_in == 5'b11011) - clkout_hl_para_drp (clk0_lt, clk0_ht, clk0pm_sel, di_in, daddr_in); - - if (daddr_in == 5'b11010) - clkout_delay_para_drp (clkout1_dly, clk1_nocnt, clk1_edge, di_in, daddr_in); - - if (daddr_in == 5'b11001) - clkout_hl_para_drp (clk1_lt, clk1_ht, clk1pm_sel, di_in, daddr_in); - - if (daddr_in == 5'b10111) - clkout_delay_para_drp (clkout2_dly, clk2_nocnt, clk2_edge, di_in, daddr_in); - - if (daddr_in == 5'b10110) - clkout_hl_para_drp (clk2_lt, clk2_ht, clk2pm_sel, di_in, daddr_in); - - if (daddr_in == 5'b10101) - clkout_delay_para_drp (clkout3_dly, clk3_nocnt, clk3_edge, di_in, daddr_in); - - if (daddr_in == 5'b10100) - clkout_hl_para_drp (clk3_lt, clk3_ht, clk3pm_sel, di_in, daddr_in); - - if (daddr_in == 5'b10011) - clkout_delay_para_drp (clkout4_dly, clk4_nocnt, clk4_edge, di_in, daddr_in); - - if (daddr_in == 5'b10010) - clkout_hl_para_drp (clk4_lt, clk4_ht, clk4pm_sel, di_in, daddr_in); - - if (daddr_in == 5'b01111) - clkout_delay_para_drp (clkout5_dly, clk5_nocnt, clk5_edge, di_in, daddr_in); - - if (daddr_in == 5'b01110) - clkout_hl_para_drp (clk5_lt, clk5_ht, clk5pm_sel, di_in, daddr_in); - - if (daddr_in == 5'b01101) - clkout_delay_para_drp (clkfbm1_dly, clkfbm1_nocnt, clkfbm1_edge, di_in, daddr_in); - - if (daddr_in == 5'b01100) - clkout_hl_para_drp (clkfbm1_lt, clkfbm1_ht, clkfbm1pm_sel, di_in, daddr_in); - - if (daddr_in == 5'b00110) begin - clkind_lt <= di_in[5:0]; - clkind_ht <= di_in[11:6]; - if ( di_in[5:0] == 6'b0 && di_in[11:6] == 6'b0 ) - clkind_div <= 8'b10000000; - else if (di_in[5:0] == 6'b0 && di_in[11:6] != 6'b0 ) - clkind_div <= 64 + di_in[11:6]; - else if (di_in[5:0] == 6'b0 && di_in[11:6] != 6'b0 ) - clkind_div <= 64 + di_in[5:0]; - else - clkind_div <= di_in[5:0] + di_in[11:6]; - clkind_nocnt <= di_in[12]; - clkind_edge <= di_in[13]; - end - - end - else begin - $display(" Error : RST is low at PLL_ADV instance %m at time %t. RST need to be high when change X_PLL_ADV paramters through DRP. ", $time); - end - - end //DWE - - end //DEN - if ( drp_lock == 1) begin - drp_lock <= 0; - drp_lock1 <= 1; - end - if (drp_lock1 == 1) begin - drp_lock1 <= 0; - drdy_out <= 1; - end - if (drdy_out == 1) - drdy_out <= 0; -end - -function addr_is_valid; -input [6:0] daddr_funcin; -begin - addr_is_valid = 1; - for (i=0; i<=6; i=i+1) - if ( daddr_funcin[i] != 0 && daddr_funcin[i] != 1) - addr_is_valid = 0; -end -endfunction - - -// end process drp; - - -// -// determine clock period -// - - always @(posedge clkpll or posedge rst_in) - if (rst_in) - begin - clkin_period[0] <= period_vco_target; - clkin_period[1] <= period_vco_target; - clkin_period[2] <= period_vco_target; - clkin_period[3] <= period_vco_target; - clkin_period[4] <= period_vco_target; - clkin_jit <= 0; - clkin_lock_cnt <= 0; - pll_locked_tm <= 0; - lock_period <= 0; - pll_locked_tmp1 <= 0; - clkout_en0_tmp <= 0; - unlock_recover <= 0; - clkin_edge <= 0; - end - else begin - clkin_edge <= $time; - clkin_period[4] <= clkin_period[3]; - clkin_period[3] <= clkin_period[2]; - clkin_period[2] <= clkin_period[1]; - clkin_period[1] <= clkin_period[0]; - if (clkin_edge != 0 && clkin_stopped_p == 0 && clkin_stopped_n == 0) - clkin_period[0] <= $time - clkin_edge; - - if (pll_unlock == 0) - clkin_jit <= $time - clkin_edge - clkin_period[0]; - else - clkin_jit <= 0; - - if ( (clkin_lock_cnt < lock_cnt_max) && fb_delay_found && pll_unlock == 0) - clkin_lock_cnt <= clkin_lock_cnt + 1; - else if (pll_unlock == 1 && rst_on_loss ==0 && pll_locked_tmp1 ==1 ) begin - clkin_lock_cnt <= locked_en_time; - unlock_recover <= 1; - end - - if ( clkin_lock_cnt >= `PLL_LOCK_TIME && pll_unlock == 0) - pll_locked_tm <= 1; - - if ( clkin_lock_cnt == 6 ) - lock_period <= 1; - - if (clkin_lock_cnt >= clkout_en_time) begin - clkout_en0_tmp <= 1; - end - - if (clkin_lock_cnt >= locked_en_time) - pll_locked_tmp1 <= 1; - - if (unlock_recover ==1 && clkin_lock_cnt >= lock_cnt_max) - unlock_recover <= 0; - end - - always @(clkout_en0_tmp) - if (clkout_en0_tmp==0) - clkout_en0 = 0; - else - @(negedge clkpll) - clkout_en0 <= #(clkin_period[0]/2) clkout_en0_tmp; - - always @(clkout_en0) - clkout_en <= #(clkvco_delay) clkout_en0; - - always @(pll_locked_tmp1 ) - if (pll_locked_tmp1==0) - pll_locked_tmp2 = pll_locked_tmp1; - else begin - pll_locked_tmp2 <= #pll_locked_delay pll_locked_tmp1; - end - - - always @(rst_in) - if (rst_in) begin - assign pll_locked_tmp2 = 0; - assign clkout_en0 = 0; - assign clkout_en = 0; - end - else begin - deassign pll_locked_tmp2; - deassign clkout_en0; - deassign clkout_en; - end - - assign locked_out = (pll_locked_tm && pll_locked_tmp2 && ~pll_unlock && !unlock_recover) ? 1 : 0; - - - always @(clkin_period[0] or clkin_period[1] or clkin_period[2] or - clkin_period[3] or clkin_period[4] or period_avg) - if ( clkin_period[0] != period_avg) - period_avg = (clkin_period[0] + clkin_period[1] + clkin_period[2] - + clkin_period[3] + clkin_period[4])/5; - - always @(period_avg or clkind_div or clkfbm1_div) begin - period_fb = period_avg * clkind_div; - period_vco = period_fb / clkfbm1_div; - period_vco_half = period_vco /2; - pll_locked_delay = period_fb * clkfbm1_div; - clkin_dly_t = period_avg * (clkind_div + 1.25); - clkfb_dly_t = period_fb * 2.25 ; - period_vco1 = period_vco / 8; - period_vco2 = period_vco / 4; - period_vco3 = period_vco * 3/ 8; - period_vco4 = period_vco / 2; - period_vco5 = period_vco * 5 / 8; - period_vco6 = period_vco *3 / 4; - period_vco7 = period_vco * 7 / 8; - md_product = clkind_div * clkfbm1_div; - md_product_dbl = clkind_div * clkfbm1_div * 2; - end - - assign clkvco_lk_rst = ( rst_in == 1 || pll_unlock == 1 || pll_locked_tm == 0) ? 1 : 0; - - always @(clkvco_lk_rst) - if (clkvco_lk_rst) - assign clkvco_lk = 0; - else - deassign clkvco_lk; - - -// always @(posedge clkpll or posedge rst_in or posedge pll_unlock) -// if ( rst_in == 1 || pll_unlock == 1 || pll_locked_tm == 0) begin -// clkvco_lk <= 0; -// end -// else begin - always @(posedge clkpll) - if (pll_locked_tm ==1) begin - clkvco_lk <= 1; - for (i1=1; i1 < md_product_dbl; i1=i1+1) - #(period_vco_half) clkvco_lk <= ~clkvco_lk; - end - - - always @(fb_delay or period_vco or clkfbm1_dly or clkfbm1pm_rl) begin - val_tmp = period_vco * md_product; - fbm1_comp_delay = period_vco *(clkfbm1_dly + clkfbm1pm_rl ); - dly_tmp = fb_delay + fbm1_comp_delay; - if (fb_delay == 0) - clkvco_delay = 0; - else if ( dly_tmp < val_tmp) - clkvco_delay = val_tmp - dly_tmp; - else - clkvco_delay = val_tmp - dly_tmp % val_tmp ; - end - - always @(clkfbm1pm_sel) - case (clkfbm1pm_sel) - 3'b000 : clkfbm1pm_rl = 0.0; - 3'b001 : clkfbm1pm_rl = 0.125; - 3'b010 : clkfbm1pm_rl = 0.25; - 3'b011 : clkfbm1pm_rl = 0.375; - 3'b100 : clkfbm1pm_rl = 0.50; - 3'b101 : clkfbm1pm_rl = 0.625; - 3'b110 : clkfbm1pm_rl = 0.75; - 3'b111 : clkfbm1pm_rl = 0.875; - endcase - - always @(clkvco_free ) - if (pmcd_mode != 1 && pll_locked_tm == 0) - clkvco_free <= #period_vco_target_half ~clkvco_free; - - always @(clkvco_lk or clkvco_free or pll_locked_tm) - if ( pll_locked_tm) - clkvco <= #clkvco_delay clkvco_lk; - else - clkvco <= #clkvco_delay clkvco_free; - - always @(clk0_ht or clk0_lt or clk0_nocnt or init_trig) - clkout_pm_cal(clk0_ht1, clk0_div, clk0_div1, clk0_ht, clk0_lt, clk0_nocnt, clk0_edge); - - always @(clk1_ht or clk1_lt or clk1_nocnt or init_trig) - clkout_pm_cal(clk1_ht1, clk1_div, clk1_div1, clk1_ht, clk1_lt, clk1_nocnt, clk1_edge); - - always @(clk2_ht or clk2_lt or clk2_nocnt or init_trig) - clkout_pm_cal(clk2_ht1, clk2_div, clk2_div1, clk2_ht, clk2_lt, clk2_nocnt, clk2_edge); - - always @(clk3_ht or clk3_lt or clk3_nocnt or init_trig) - clkout_pm_cal(clk3_ht1, clk3_div, clk3_div1, clk3_ht, clk3_lt, clk3_nocnt, clk3_edge); - - always @(clk4_ht or clk4_lt or clk4_nocnt or init_trig) - clkout_pm_cal(clk4_ht1, clk4_div, clk4_div1, clk4_ht, clk4_lt, clk4_nocnt, clk4_edge); - - always @(clk5_ht or clk5_lt or clk5_nocnt or init_trig) - clkout_pm_cal(clk5_ht1, clk5_div, clk5_div1, clk5_ht, clk5_lt, clk5_nocnt, clk5_edge); - - always @(clkfbm1_ht or clkfbm1_lt or clkfbm1_nocnt or init_trig) - clkout_pm_cal(clkfbm1_ht1, clkfbm1_div, clkfbm1_div1, clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge); - - always @(rst_in) - if (rst_in) - assign clkout_mux = 8'b0; - else - deassign clkout_mux; - - always @(clkvco or clkout_en ) - if (clkout_en) begin - clkout_mux[0] <= clkvco; - clkout_mux[1] <= #(period_vco1) clkvco; - clkout_mux[2] <= #(period_vco2) clkvco; - clkout_mux[3] <= #(period_vco3) clkvco; - clkout_mux[4] <= #(period_vco4) clkvco; - clkout_mux[5] <= #(period_vco5) clkvco; - clkout_mux[6] <= #(period_vco6) clkvco; - clkout_mux[7] <= #(period_vco7) clkvco; - end - - assign clk0in = clkout_mux[clk0pm_sel]; - assign clk1in = clkout_mux[clk1pm_sel]; - assign clk2in = clkout_mux[clk2pm_sel]; - assign clk3in = clkout_mux[clk3pm_sel]; - assign clk4in = clkout_mux[clk4pm_sel]; - assign clk5in = clkout_mux[clk5pm_sel]; - assign clkfbm1in = clkout_mux[clkfbm1pm_sel]; - - assign clk0ps_en = (clk0_dly_cnt == clkout0_dly) ? clkout_en : 0; - assign clk1ps_en = (clk1_dly_cnt == clkout1_dly) ? clkout_en : 0; - assign clk2ps_en = (clk2_dly_cnt == clkout2_dly) ? clkout_en : 0; - assign clk3ps_en = (clk3_dly_cnt == clkout3_dly) ? clkout_en : 0; - assign clk4ps_en = (clk4_dly_cnt == clkout4_dly) ? clkout_en : 0; - assign clk5ps_en = (clk5_dly_cnt == clkout5_dly) ? clkout_en : 0; - assign clkfbm1ps_en = (clkfbm1_dly_cnt == clkfbm1_dly) ? clkout_en : 0; - - always @(negedge clk0in or posedge rst_in) - if (rst_in) - clk0_dly_cnt <= 6'b0; - else - if (clk0_dly_cnt < clkout0_dly && clkout_en ==1) - clk0_dly_cnt <= clk0_dly_cnt + 1; - - always @(negedge clk1in or posedge rst_in) - if (rst_in) - clk1_dly_cnt <= 6'b0; - else - if (clk1_dly_cnt < clkout1_dly && clkout_en ==1) - clk1_dly_cnt <= clk1_dly_cnt + 1; - - always @(negedge clk2in or posedge rst_in) - if (rst_in) - clk2_dly_cnt <= 6'b0; - else - if (clk2_dly_cnt < clkout2_dly && clkout_en ==1) - clk2_dly_cnt <= clk2_dly_cnt + 1; - - always @(negedge clk3in or posedge rst_in) - if (rst_in) - clk3_dly_cnt <= 6'b0; - else - if (clk3_dly_cnt < clkout3_dly && clkout_en ==1) - clk3_dly_cnt <= clk3_dly_cnt + 1; - - always @(negedge clk4in or posedge rst_in) - if (rst_in) - clk4_dly_cnt <= 6'b0; - else - if (clk4_dly_cnt < clkout4_dly && clkout_en ==1) - clk4_dly_cnt <= clk4_dly_cnt + 1; - - always @(negedge clk5in or posedge rst_in) - if (rst_in) - clk5_dly_cnt <= 6'b0; - else - if (clk5_dly_cnt < clkout5_dly && clkout_en ==1) - clk5_dly_cnt <= clk5_dly_cnt + 1; - - always @(negedge clkfbm1in or posedge rst_in) - if (rst_in) - clkfbm1_dly_cnt <= 6'b0; - else - if (clkfbm1_dly_cnt < clkfbm1_dly && clkout_en ==1) - clkfbm1_dly_cnt <= clkfbm1_dly_cnt + 1; - - always @(posedge clk0in or negedge clk0in or posedge rst_in) - if (rst_in) begin - clk0_cnt <= 8'b0; - clk0_out <= 0; - end - else if (clk0ps_en) begin - if (clk0_cnt < clk0_div1) - clk0_cnt <= clk0_cnt + 1; - else - clk0_cnt <= 8'b0; - - if (clk0_cnt < clk0_ht1) - clk0_out <= 1; - else - clk0_out <= 0; - end - else begin - clk0_cnt <= 8'b0; - clk0_out <= 0; - end - - always @(posedge clk1in or negedge clk1in or posedge rst_in) - if (rst_in) begin - clk1_cnt <= 8'b0; - clk1_out <= 0; - end - else if (clk1ps_en) begin - if (clk1_cnt < clk1_div1) - clk1_cnt <= clk1_cnt + 1; - else - clk1_cnt <= 8'b0; - - if (clk1_cnt < clk1_ht1) - clk1_out <= 1; - else - clk1_out <= 0; - end - else begin - clk1_cnt <= 8'b0; - clk1_out <= 0; - end - - always @(posedge clk2in or negedge clk2in or posedge rst_in) - if (rst_in) begin - clk2_cnt <= 8'b0; - clk2_out <= 0; - end - else if (clk2ps_en) begin - if (clk2_cnt < clk2_div1) - clk2_cnt <= clk2_cnt + 1; - else - clk2_cnt <= 8'b0; - - if (clk2_cnt < clk2_ht1) - clk2_out <= 1; - else - clk2_out <= 0; - end - else begin - clk2_cnt <= 8'b0; - clk2_out <= 0; - end - - always @(posedge clk3in or negedge clk3in or posedge rst_in) - if (rst_in) begin - clk3_cnt <= 8'b0; - clk3_out <= 0; - end - else if (clk3ps_en) begin - if (clk3_cnt < clk3_div1) - clk3_cnt <= clk3_cnt + 1; - else - clk3_cnt <= 8'b0; - - if (clk3_cnt < clk3_ht1) - clk3_out <= 1; - else - clk3_out <= 0; - end - else begin - clk3_cnt <= 8'b0; - clk3_out <= 0; - end - - - always @(posedge clk4in or negedge clk4in or posedge rst_in) - if (rst_in) begin - clk4_cnt <= 8'b0; - clk4_out <= 0; - end - else if (clk4ps_en) begin - if (clk4_cnt < clk4_div1) - clk4_cnt <= clk4_cnt + 1; - else - clk4_cnt <= 8'b0; - - if (clk4_cnt < clk4_ht1) - clk4_out <= 1; - else - clk4_out <= 0; - end - else begin - clk4_cnt <= 8'b0; - clk4_out <= 0; - end - - - always @(posedge clk5in or negedge clk5in or posedge rst_in) - if (rst_in) begin - clk5_cnt <= 8'b0; - clk5_out <= 0; - end - else if (clk5ps_en) begin - if (clk5_cnt < clk5_div1) - clk5_cnt <= clk5_cnt + 1; - else - clk5_cnt <= 8'b0; - - if (clk5_cnt < clk5_ht1) - clk5_out <= 1; - else - clk5_out <= 0; - end - else begin - clk5_cnt <= 8'b0; - clk5_out <= 0; - end - - - always @(posedge clkfbm1in or negedge clkfbm1in or posedge rst_in) - if (rst_in) begin - clkfbm1_cnt <= 8'b0; - clkfbm1_out <= 0; - end - else if (clkfbm1ps_en) begin - if (clkfbm1_cnt < clkfbm1_div1) - clkfbm1_cnt <= clkfbm1_cnt + 1; - else - clkfbm1_cnt <= 8'b0; - - if (clkfbm1_cnt < clkfbm1_ht1) - clkfbm1_out <= 1; - else - clkfbm1_out <= 0; - end - else begin - clkfbm1_cnt <= 8'b0; - clkfbm1_out <= 0; - end - - - - always @(clk0_out or clkfb_tst or fb_delay_found) - if (fb_delay_found == 1) - clkout0_out = clk0_out; - else - clkout0_out = clkfb_tst; - - always @(clk1_out or clkfb_tst or fb_delay_found) - if (fb_delay_found == 1) - clkout1_out = clk1_out; - else - clkout1_out = clkfb_tst; - - always @(clk2_out or clkfb_tst or fb_delay_found) - if (fb_delay_found == 1) - clkout2_out = clk2_out; - else - clkout2_out = clkfb_tst; - - always @(clk3_out or clkfb_tst or fb_delay_found) - if (fb_delay_found == 1) - clkout3_out = clk3_out; - else - clkout3_out = clkfb_tst; - - always @(clk4_out or clkfb_tst or fb_delay_found) - if (fb_delay_found == 1) - clkout4_out = clk4_out; - else - clkout4_out = clkfb_tst; - - always @(clk5_out or clkfb_tst or fb_delay_found) - if (fb_delay_found == 1) - clkout5_out = clk5_out; - else - clkout5_out = clkfb_tst; - - always @(clkfbm1_out or clkfb_tst or fb_delay_found) - if (fb_delay_found == 1) - clkfb_out = clkfbm1_out; - else - clkfb_out = clkfb_tst; - -// -// determine feedback delay -// - -always @(rst_in1) - if (rst_in1) - assign clkfb_tst = 0; - else - deassign clkfb_tst; - -always @(posedge clkpll ) - if (fb_delay_found_tmp == 0 && GSR == 0 && rst_in1 == 0) begin - clkfb_tst <= 1'b1; - end - else - clkfb_tst <= 1'b0; - - -always @( posedge clkfb_tst or posedge rst_in1 ) - if (rst_in1) - delay_edge <= 0; - else - delay_edge <= $time; - -always @(posedge clkfb_in or posedge rst_in1 ) - if (rst_in1) begin - fb_delay <= 0; - fb_delay_found_tmp <= 0; - end - else - if (fb_delay_found_tmp ==0 ) begin - if ( delay_edge != 0) - fb_delay <= ($time - delay_edge); - else - fb_delay <= 0; - fb_delay_found_tmp <= 1; - end - -always @(rst_in1) - if (rst_in1) - assign fb_delay_found = 0; - else - deassign fb_delay_found; - -always @(fb_delay_found_tmp or clkvco_delay ) - fb_delay_found <= #(clkvco_delay) fb_delay_found_tmp; - - -always @(fb_delay) - if (rst_in1==0 && (fb_delay/1000.0 > fb_delay_max)) begin - $display("Warning : The feedback delay on PLL_ADV instance %m at time %t is %f ns. It is over the maximun value %f ns.", $time, fb_delay / 1000.0, fb_delay_max); - end - -// -// generate unlock signal -// - -always @(clkpll) - clkpll_dly <= #clkin_dly_t clkpll; - -always @(clkfb_in) - if (pmcd_mode != 1) - clkfbin_dly <= #clkfb_dly_t clkfb_in; - else - clkfbin_dly = 0; - -always @( posedge clkpll_dly or negedge clkpll or posedge rst_in) - if (rst_in || clkpll == 0) begin - clkstop_cnt_p = 0; - clkin_stopped_p = 0; - end - else - if (fb_delay_found && pll_locked_tmp2) begin - if (clkpll && clkpll_jitter_unlock == 0) - clkstop_cnt_p <= clkstop_cnt_p +1; - else - clkstop_cnt_p = 0; - - if (clkstop_cnt_p > clkin_stop_max) - clkin_stopped_p <= 1; - else - clkin_stopped_p = 0; - end - else begin - clkstop_cnt_p = 0; - clkin_stopped_p = 0; - end - -always @( posedge clkpll_dly or posedge clkpll or posedge rst_in) - if (rst_in || clkpll == 1) begin - clkstop_cnt_n = 0; - clkin_stopped_n = 0; - end - else - if (fb_delay_found && pll_locked_tmp2) begin - if (clkpll==0 && clkpll_jitter_unlock == 0) - clkstop_cnt_n <= clkstop_cnt_n +1; - else - clkstop_cnt_n = 0; - - if (clkstop_cnt_n > clkin_stop_max) - clkin_stopped_n <= 1; - else - clkin_stopped_n = 0; - end - else begin - clkstop_cnt_n = 0; - clkin_stopped_n = 0; - end - - -always @( posedge clkfbin_dly or negedge clkfb_in or posedge rst_in) - if (rst_in || clkfb_in == 0) begin - clkfbstop_cnt_p = 0; - clkfb_stopped_p = 0; - end - else - if (fb_delay_found && pll_locked_tmp2) begin - if (clkfb_in && clkpll_jitter_unlock == 0) - clkfbstop_cnt_p <= clkfbstop_cnt_p +1; - else - clkfbstop_cnt_p = 0; - - if (clkfbstop_cnt_p > clkfb_stop_max) - clkfb_stopped_p <= 1; - else - clkfb_stopped_p = 0; - end - else begin - clkfbstop_cnt_p = 0; - clkfb_stopped_p = 0; - end - -always @( posedge clkfbin_dly or posedge clkfb_in or posedge rst_in) - if (rst_in==1 || clkfb_in == 1) begin - clkfbstop_cnt_n = 0; - clkfb_stopped_n = 0; - end - else - if (fb_delay_found && pll_locked_tmp2) begin - if (clkfb_in==0 && clkpll_jitter_unlock == 0) - clkfbstop_cnt_n <= clkfbstop_cnt_n +1; - else - clkfbstop_cnt_n = 0; - - if (clkfbstop_cnt_n > clkfb_stop_max) - clkfb_stopped_n <= 1; - else - clkfb_stopped_n = 0; - end - else begin - clkfbstop_cnt_n = 0; - clkfb_stopped_n = 0; - end - -always @(clkin_jit or rst_in ) - if (rst_in) - clkpll_jitter_unlock = 0; - else - if ( pll_locked_tmp2 && clkfb_stopped == 0 && clkin_stopped == 0) begin - if ((clkin_jit > REF_CLK_JITTER_MAX_tmp) || (clkin_jit < -REF_CLK_JITTER_MAX_tmp)) - clkpll_jitter_unlock = 1; - else - clkpll_jitter_unlock = 0; - end - else - clkpll_jitter_unlock = 0; - - assign clkin_stopped = (clkin_stopped_p || clkin_stopped_n) ? 1 : 0; - assign clkfb_stopped = (clkfb_stopped_p ||clkfb_stopped_n) ? 1 : 0; - assign pll_unlock = (clkin_stopped || clkfb_stopped || clkpll_jitter_unlock) ? 1 : 0; - -// tasks - - -task clkout_dly_cal; -output [5:0] clkout_dly; -output [2:0] clkpm_sel; -input clkdiv; -input clk_ps; -input reg [160:0] clk_ps_name; - -integer clkdiv; -real clk_ps; -real clk_ps_rl; - -real clk_dly_rl, clk_dly_rem; -integer clkout_dly_tmp; - -begin - - if (clk_ps < 0.0) - clk_dly_rl = (360.0 + clk_ps) * clkdiv / 360.0; - else - clk_dly_rl = clk_ps * clkdiv / 360.0; - - clkout_dly_tmp = $rtoi(clk_dly_rl); - - if (clkout_dly_tmp > 63) begin - $display(" Warning : Attribute %s of PLL_ADV on instance %m is set to %f. Required phase shifting can not be reached since it is over the maximum phase shifting ability of X_PLL_ADV", clk_ps_name, clk_ps); - clkout_dly = 6'b111111; - end - else - clkout_dly = clkout_dly_tmp; - - clk_dly_rem = clk_dly_rl - clkout_dly; - - if (clk_dly_rem < 0.125) - clkpm_sel = 0; - else if (clk_dly_rem >= 0.125 && clk_dly_rem < 0.25) - clkpm_sel = 1; - else if (clk_dly_rem >= 0.25 && clk_dly_rem < 0.375) - clkpm_sel = 2; - else if (clk_dly_rem >= 0.375 && clk_dly_rem < 0.5) - clkpm_sel = 3; - else if (clk_dly_rem >= 0.5 && clk_dly_rem < 0.625) - clkpm_sel = 4; - else if (clk_dly_rem >= 0.625 && clk_dly_rem < 0.75) - clkpm_sel = 5; - else if (clk_dly_rem >= 0.75 && clk_dly_rem < 0.875) - clkpm_sel = 6; - else if (clk_dly_rem >= 0.875 ) - clkpm_sel = 7; - - if (clk_ps < 0.0) - clk_ps_rl = (clkout_dly + 0.125 * clkpm_sel)* 360.0 / clkdiv - 360.0; - else - clk_ps_rl = (clkout_dly + 0.125 * clkpm_sel) * 360.0 / clkdiv; - - if (((clk_ps_rl- clk_ps) > 0.001) || ((clk_ps_rl- clk_ps) < -0.001)) - $display(" Warning : Attribute %s of PLL_ADV on instance %m is set to %f. Real phase shifting is %f. Required phase shifting can not be reached.", clk_ps_name, clk_ps, clk_ps_rl); - -end -endtask - - -task clk_out_para_cal; -output [6:0] clk_ht; -output [6:0] clk_lt; -output clk_nocnt; -output clk_edge; -input CLKOUT_DIVIDE; -input CLKOUT_DUTY_CYCLE; - -integer CLKOUT_DIVIDE; -real CLKOUT_DUTY_CYCLE; - -real tmp_value; -integer tmp_value1; -real tmp_value2; - -begin - tmp_value = CLKOUT_DIVIDE * CLKOUT_DUTY_CYCLE; - tmp_value1 = $rtoi(tmp_value * 2) % 2; - tmp_value2 = CLKOUT_DIVIDE - tmp_value; - - - if ((tmp_value) >= O_MAX_HT_LT) begin -// clk_ht = O_MAX_HT_LT; - clk_ht = 7'b1000000; - end - else begin - if (tmp_value < 1.0) - clk_ht = 1; - else - if ( tmp_value1 != 0) - clk_ht = $rtoi(tmp_value) + 1; - else - clk_ht = $rtoi(tmp_value); - end - - if ( (CLKOUT_DIVIDE - clk_ht) >= O_MAX_HT_LT) - clk_lt = 7'b1000000; - else - clk_lt = CLKOUT_DIVIDE - clk_ht; - - clk_nocnt = (CLKOUT_DIVIDE ==1) ? 1 : 0; - if ( tmp_value < 1.0) - clk_edge = 1; - else if (tmp_value1 != 0) - clk_edge = 1; - else - clk_edge = 0; -end -endtask - - -function clkout_duty_chk; - input CLKOUT_DIVIDE; - input CLKOUT_DUTY_CYCLE; - input reg [160:0] CLKOUT_DUTY_CYCLE_N; - - integer CLKOUT_DIVIDE, step_tmp; - real CLKOUT_DUTY_CYCLE; - - real CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX, CLK_DUTY_CYCLE_STEP; - real CLK_DUTY_CYCLE_MIN_rnd; - reg clk_duty_tmp_int; - -begin - - if (CLKOUT_DIVIDE > O_MAX_HT_LT) begin - CLK_DUTY_CYCLE_MIN = (CLKOUT_DIVIDE - O_MAX_HT_LT)/CLKOUT_DIVIDE; - CLK_DUTY_CYCLE_MAX = (O_MAX_HT_LT + 0.5)/CLKOUT_DIVIDE; - CLK_DUTY_CYCLE_MIN_rnd = CLK_DUTY_CYCLE_MIN; - end - else begin - if (CLKOUT_DIVIDE == 1) begin - CLK_DUTY_CYCLE_MIN = 0.0; - CLK_DUTY_CYCLE_MIN_rnd = 0.0; - end - else begin - step_tmp = 1000 / CLKOUT_DIVIDE; - CLK_DUTY_CYCLE_MIN_rnd = step_tmp / 1000.0; - CLK_DUTY_CYCLE_MIN = 1.0 /CLKOUT_DIVIDE; - end - CLK_DUTY_CYCLE_MAX = 1.0; - end - - if (CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_MAX || CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd) begin - $display(" Attribute Syntax Warning : %s is set to %f on instance %m and is not in the allowed range %f to %f.", CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE, CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX ); - end - - clk_duty_tmp_int = 0; - CLK_DUTY_CYCLE_STEP = 0.5 / CLKOUT_DIVIDE; - for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) - if (((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) > -0.001 && - ((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) < 0.001) - clk_duty_tmp_int = 1; - - if ( clk_duty_tmp_int != 1) begin - $display(" Attribute Syntax Warning : %s is set to %f on instance %m and is not an allowed value. Allowed values are:", CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE); - for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) - $display("%f", CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j); - end - - clkout_duty_chk = 1'b1; -end -endfunction - - -function para_int_pmcd_chk; - input para_in; - input reg [160:0] para_name; - input range_low; - input range_high; - input pmcd_mode; - input pmcd_value; - - integer para_in; - integer range_low; - integer range_high; - integer pmcd_value; -begin - - if (para_in < range_low || para_in > range_high) - begin - $display("Attribute Syntax Error : The Attribute %s on PLL_ADV instance %m is set to %d. Legal values for this attribute are %d to %d.", para_name, para_in, range_low, range_high); - $finish; - end - else if (pmcd_mode == 1 && para_in != pmcd_value) begin - $display("Attribute Syntax Error : The Attribute %s on PLL_ADV instance %m is set to %d when attribute PLL_PMCD_MODE is set to TRUE. Legal values for this attribute is %d when PLL in PMCD MODE.", para_name, para_in, pmcd_value); - $finish; - end - - para_int_pmcd_chk = 1'b1; -end -endfunction - -function para_real_pmcd_chk; - input para_in; - input reg [160:0] para_name; - input range_low; - input range_high; - input pmcd_mode; - input pmcd_value; - - real para_in; - real range_low; - real range_high; - real pmcd_value; -begin - - if (para_in < range_low || para_in > range_high) - begin - $display("Attribute Syntax Error : The Attribute %s on PLL_ADV instance %m is set to %f. Legal values for this attribute are %f to %f.", para_name, para_in, range_low, range_high); - $finish; - end - else if (pmcd_mode == 1 && para_in != pmcd_value) begin - $display("Attribute Syntax Error : The Attribute %s on PLL_ADV instance %m is set to %f when attribute PLL_PMCD_MODE is set to TRUE. Legal values for this attribute is %f when PLL in PMCD MODE.", para_name, para_in, pmcd_value); - $finish; - end - - para_real_pmcd_chk = 1'b0; -end -endfunction - -function para_int_range_chk; - input para_in; - input reg [160:0] para_name; - input range_low; - input range_high; - - integer para_in; - integer range_low; - integer range_high; -begin - if ( para_in < range_low || para_in > range_high) begin - $display("Attribute Syntax Error : The Attribute %s on PLL_ADV instance %m is set to %d. Legal values for this attribute are %d to %d.", para_name, para_in, range_low, range_high); - $finish; - end - para_int_range_chk = 1'b1; -end -endfunction - -function para_real_range_chk; - input para_in; - input reg [160:0] para_name; - input range_low; - input range_high; - - real para_in; - real range_low; - real range_high; -begin - if ( para_in < range_low || para_in > range_high) begin - $display("Attribute Syntax Error : The Attribute %s on PLL_ADV instance %m is set to %f. Legal values for this attribute are %f to %f.", para_name, para_in, range_low, range_high); - $finish; - end - - para_real_range_chk = 1'b0; -end -endfunction - -task clkout_pm_cal; - output [7:0] clk_ht1; - output [7:0] clk_div; - output [7:0] clk_div1; - input [6:0] clk_ht; - input [6:0] clk_lt; - input clk_nocnt; - input clk_edge; - -begin - if (clk_nocnt ==1) begin - clk_div = 8'b00000001; - clk_div1 = 8'b00000001; - clk_ht1 = 8'b00000001; - end - else begin - if ( clk_edge == 1) - clk_ht1 = 2 * clk_ht -1; - else - clk_ht1 = 2 * clk_ht; - clk_div = clk_ht + clk_lt ; - clk_div1 = 2 * clk_div -1; - end -end -endtask - -task clkout_delay_para_drp; - output [5:0] clkout_dly; - output clk_nocnt; - output clk_edge; - input [15:0] di_in; - input [4:0] daddr_in; -begin - -// if (di_in[15:8] != 8'h00) begin -// $display(" Error : PLL_ADV on instance %m input DI[15:8] is set to %h and need to be set to 00h at address DADDR=%b at time %t.", di_in[15:8], daddr_in, $time); -// $finish; -// end - clkout_dly = di_in[5:0]; - clk_nocnt = di_in[6]; - clk_edge = di_in[7]; -end -endtask - -task clkout_hl_para_drp; - output [6:0] clk_lt; - output [6:0] clk_ht; - output [2:0] clkpm_sel; - input [15:0] di_in_tmp; - input [4:0] daddr_in_tmp; -begin - if (di_in_tmp[12] != 1) begin - $display(" Error : PLL_ADV on instance %m input DI is %h at address DADDR=%b at time %t. The bit 12 need to be set to 1 .", di_in_tmp, daddr_in_tmp, $time); -// $finish; - end - if ( di_in_tmp[5:0] == 6'b0) - clk_lt = 7'b1000000; - else - clk_lt = { 1'b0, di_in[5:0]}; - if (di_in_tmp[11:6] == 6'b0) - clk_ht = 7'b1000000; - else - clk_ht = { 1'b0, di_in_tmp[11:6]}; - clkpm_sel = di_in_tmp[15:13]; -end -endtask - - - -endmodule diff --git a/fpga/usrp2/models/PLL_BASE.v b/fpga/usrp2/models/PLL_BASE.v deleted file mode 100644 index f2180a25a..000000000 --- a/fpga/usrp2/models/PLL_BASE.v +++ /dev/null @@ -1,150 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/PLL_BASE.v,v 1.5 2006/03/13 21:53:44 yanx Exp $ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2004 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 10.1 -// \ \ Description : Xilinx Timing Simulation Library Component -// / / Phase Lock Loop Clock -// /___/ /\ Filename : PLL_BASE.v -// \ \ / \ Timestamp : -// \___\/\___\ -// -// Revision: -// 12/02/05 - Initial version. -// 02/24/06 - Add real/integer to parameter. -// End Revision - - -`timescale 1 ps / 1 ps - -module PLL_BASE ( - CLKFBOUT, - CLKOUT0, - CLKOUT1, - CLKOUT2, - CLKOUT3, - CLKOUT4, - CLKOUT5, - LOCKED, - CLKFBIN, - CLKIN, - RST - -); - -parameter BANDWIDTH = "OPTIMIZED"; -parameter integer CLKFBOUT_MULT = 1; -parameter real CLKFBOUT_PHASE = 0.0; -parameter real CLKIN_PERIOD = 0.000; -parameter integer CLKOUT0_DIVIDE = 1; -parameter real CLKOUT0_DUTY_CYCLE = 0.5; -parameter real CLKOUT0_PHASE = 0.0; -parameter integer CLKOUT1_DIVIDE = 1; -parameter real CLKOUT1_DUTY_CYCLE = 0.5; -parameter real CLKOUT1_PHASE = 0.0; -parameter integer CLKOUT2_DIVIDE = 1; -parameter real CLKOUT2_DUTY_CYCLE = 0.5; -parameter real CLKOUT2_PHASE = 0.0; -parameter integer CLKOUT3_DIVIDE = 1; -parameter real CLKOUT3_DUTY_CYCLE = 0.5; -parameter real CLKOUT3_PHASE = 0.0; -parameter integer CLKOUT4_DIVIDE = 1; -parameter real CLKOUT4_DUTY_CYCLE = 0.5; -parameter real CLKOUT4_PHASE = 0.0; -parameter integer CLKOUT5_DIVIDE = 1; -parameter real CLKOUT5_DUTY_CYCLE = 0.5; -parameter real CLKOUT5_PHASE = 0.0; -parameter COMPENSATION = "SYSTEM_SYNCHRONOUS"; -parameter integer DIVCLK_DIVIDE = 1; -parameter real REF_JITTER = 0.100; -parameter RESET_ON_LOSS_OF_LOCK = "FALSE"; - - -output CLKFBOUT; -output CLKOUT0; -output CLKOUT1; -output CLKOUT2; -output CLKOUT3; -output CLKOUT4; -output CLKOUT5; -output LOCKED; - -input CLKFBIN; -input CLKIN; -input RST; - - -wire OPEN_CLKFBDCM; -wire OPEN_CLKOUTDCM0; -wire OPEN_CLKOUTDCM1; -wire OPEN_CLKOUTDCM2; -wire OPEN_CLKOUTDCM3; -wire OPEN_CLKOUTDCM4; -wire OPEN_CLKOUTDCM5; -wire OPEN_DRDY; -wire [15:0] OPEN_DO; - -PLL_ADV pll_adv_1 ( - .CLKFBDCM (OPEN_CLKFBDCM), - .CLKFBIN (CLKFBIN), - .CLKFBOUT (CLKFBOUT), - .CLKIN1 (CLKIN), - .CLKIN2 (1'b0), - .CLKOUT0 (CLKOUT0), - .CLKOUT1 (CLKOUT1), - .CLKOUT2 (CLKOUT2), - .CLKOUT3 (CLKOUT3), - .CLKOUT4 (CLKOUT4), - .CLKOUT5 (CLKOUT5), - .CLKOUTDCM0 (OPEN_CLKOUTDCM0), - .CLKOUTDCM1 (OPEN_CLKOUTDCM1), - .CLKOUTDCM2 (OPEN_CLKOUTDCM2), - .CLKOUTDCM3 (OPEN_CLKOUTDCM3), - .CLKOUTDCM4 (OPEN_CLKOUTDCM4), - .CLKOUTDCM5 (OPEN_CLKOUTDCM5), - .DADDR (5'b0), - .DCLK (1'b0), - .DEN (1'b0), - .DI (16'b0), - .DO (OPEN_DO), - .DRDY (OPEN_DRDY), - .DWE (1'b0), - .LOCKED (LOCKED), - .CLKINSEL(1'b1), - .REL (1'b0), - .RST (RST) -); - -defparam pll_adv_1.BANDWIDTH = BANDWIDTH; -defparam pll_adv_1.CLKFBOUT_MULT = CLKFBOUT_MULT; -defparam pll_adv_1.CLKFBOUT_PHASE = CLKFBOUT_PHASE; -defparam pll_adv_1.CLKIN1_PERIOD = CLKIN_PERIOD; -defparam pll_adv_1.CLKIN2_PERIOD = 10.0; -defparam pll_adv_1.CLKOUT0_DIVIDE = CLKOUT0_DIVIDE; -defparam pll_adv_1.CLKOUT0_DUTY_CYCLE = CLKOUT0_DUTY_CYCLE; -defparam pll_adv_1.CLKOUT0_PHASE = CLKOUT0_PHASE; -defparam pll_adv_1.CLKOUT1_DIVIDE = CLKOUT1_DIVIDE; -defparam pll_adv_1.CLKOUT1_DUTY_CYCLE = CLKOUT1_DUTY_CYCLE; -defparam pll_adv_1.CLKOUT1_PHASE = CLKOUT1_PHASE; -defparam pll_adv_1.CLKOUT2_DIVIDE = CLKOUT2_DIVIDE; -defparam pll_adv_1.CLKOUT2_DUTY_CYCLE = CLKOUT2_DUTY_CYCLE; -defparam pll_adv_1.CLKOUT2_PHASE = CLKOUT2_PHASE; -defparam pll_adv_1.CLKOUT3_DIVIDE = CLKOUT3_DIVIDE; -defparam pll_adv_1.CLKOUT3_DUTY_CYCLE = CLKOUT3_DUTY_CYCLE; -defparam pll_adv_1.CLKOUT3_PHASE = CLKOUT3_PHASE; -defparam pll_adv_1.CLKOUT4_DIVIDE = CLKOUT4_DIVIDE; -defparam pll_adv_1.CLKOUT4_DUTY_CYCLE = CLKOUT4_DUTY_CYCLE; -defparam pll_adv_1.CLKOUT4_PHASE = CLKOUT4_PHASE; -defparam pll_adv_1.CLKOUT5_DIVIDE = CLKOUT5_DIVIDE; -defparam pll_adv_1.CLKOUT5_DUTY_CYCLE = CLKOUT5_DUTY_CYCLE; -defparam pll_adv_1.CLKOUT5_PHASE = CLKOUT5_PHASE; -defparam pll_adv_1.COMPENSATION = COMPENSATION; -defparam pll_adv_1.DIVCLK_DIVIDE = DIVCLK_DIVIDE; -defparam pll_adv_1.REF_JITTER = REF_JITTER; -defparam pll_adv_1.RESET_ON_LOSS_OF_LOCK = RESET_ON_LOSS_OF_LOCK; - -endmodule diff --git a/fpga/usrp2/models/RAMB16_S36_S36.v b/fpga/usrp2/models/RAMB16_S36_S36.v deleted file mode 100644 index f1a92c7ce..000000000 --- a/fpga/usrp2/models/RAMB16_S36_S36.v +++ /dev/null @@ -1,2194 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2005 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 10.1 -// \ \ Description : Xilinx Functional Simulation Library Component -// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM -// /___/ /\ Filename : RAMB16_S36_S36.v -// \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005 -// \___\/\___\ -// -// Revision: -// 03/23/04 - Initial version. -// End Revision - -`ifdef legacy_model - -`timescale 1 ps / 1 ps - -module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); - - parameter INIT_A = 36'h0; - parameter INIT_B = 36'h0; - parameter SRVAL_A = 36'h0; - parameter SRVAL_B = 36'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - localparam SETUP_ALL = 1000; - localparam SETUP_READ_FIRST = 3000; - - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - - output [31:0] DOA; - output [3:0] DOPA; - reg [31:0] doa_out; - reg [3:0] dopa_out; - wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7, doa_out8, doa_out9, doa_out10, doa_out11, doa_out12, doa_out13, doa_out14, doa_out15, doa_out16, doa_out17, doa_out18, doa_out19, doa_out20, doa_out21, doa_out22, doa_out23, doa_out24, doa_out25, doa_out26, doa_out27, doa_out28, doa_out29, doa_out30, doa_out31; - wire dopa0_out, dopa1_out, dopa2_out, dopa3_out; - - input [8:0] ADDRA; - input [31:0] DIA; - input [3:0] DIPA; - input ENA, CLKA, WEA, SSRA; - - output [31:0] DOB; - output [3:0] DOPB; - reg [31:0] dob_out; - reg [3:0] dopb_out; - wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15, dob_out16, dob_out17, dob_out18, dob_out19, dob_out20, dob_out21, dob_out22, dob_out23, dob_out24, dob_out25, dob_out26, dob_out27, dob_out28, dob_out29, dob_out30, dob_out31; - wire dopb0_out, dopb1_out, dopb2_out, dopb3_out; - - input [8:0] ADDRB; - input [31:0] DIB; - input [3:0] DIPB; - input ENB, CLKB, WEB, SSRB; - - reg [18431:0] mem; - reg [8:0] count; - reg [1:0] wr_mode_a, wr_mode_b; - - reg [5:0] dmi, dbi; - reg [5:0] pmi, pbi; - - wire [8:0] addra_int; - reg [8:0] addra_reg; - wire [31:0] dia_int; - wire [3:0] dipa_int; - wire ena_int, clka_int, wea_int, ssra_int; - reg ena_reg, wea_reg, ssra_reg; - wire [8:0] addrb_int; - reg [8:0] addrb_reg; - wire [31:0] dib_int; - wire [3:0] dipb_int; - wire enb_int, clkb_int, web_int, ssrb_int; - reg display_flag; - reg enb_reg, web_reg, ssrb_reg; - - time time_clka, time_clkb; - time time_clka_clkb; - time time_clkb_clka; - - reg setup_all_a_b; - reg setup_all_b_a; - reg setup_zero; - reg setup_rf_a_b; - reg setup_rf_b_a; - reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; - reg memory_collision, memory_collision_a_b, memory_collision_b_a; - reg address_collision, address_collision_a_b, address_collision_b_a; - reg change_clka; - reg change_clkb; - - wire [14:0] data_addra_int; - wire [14:0] data_addra_reg; - wire [14:0] data_addrb_int; - wire [14:0] data_addrb_reg; - wire [15:0] parity_addra_int; - wire [15:0] parity_addra_reg; - wire [15:0] parity_addrb_int; - wire [15:0] parity_addrb_reg; - - tri0 GSR = glbl.GSR; - - always @(GSR) - if (GSR) begin - assign doa_out = INIT_A[31:0]; - assign dopa_out = INIT_A[35:32]; - assign dob_out = INIT_B[31:0]; - assign dopb_out = INIT_B[35:32]; - end - else begin - deassign doa_out; - deassign dopa_out; - deassign dob_out; - deassign dopb_out; - end - - buf b_doa_out0 (doa_out0, doa_out[0]); - buf b_doa_out1 (doa_out1, doa_out[1]); - buf b_doa_out2 (doa_out2, doa_out[2]); - buf b_doa_out3 (doa_out3, doa_out[3]); - buf b_doa_out4 (doa_out4, doa_out[4]); - buf b_doa_out5 (doa_out5, doa_out[5]); - buf b_doa_out6 (doa_out6, doa_out[6]); - buf b_doa_out7 (doa_out7, doa_out[7]); - buf b_doa_out8 (doa_out8, doa_out[8]); - buf b_doa_out9 (doa_out9, doa_out[9]); - buf b_doa_out10 (doa_out10, doa_out[10]); - buf b_doa_out11 (doa_out11, doa_out[11]); - buf b_doa_out12 (doa_out12, doa_out[12]); - buf b_doa_out13 (doa_out13, doa_out[13]); - buf b_doa_out14 (doa_out14, doa_out[14]); - buf b_doa_out15 (doa_out15, doa_out[15]); - buf b_doa_out16 (doa_out16, doa_out[16]); - buf b_doa_out17 (doa_out17, doa_out[17]); - buf b_doa_out18 (doa_out18, doa_out[18]); - buf b_doa_out19 (doa_out19, doa_out[19]); - buf b_doa_out20 (doa_out20, doa_out[20]); - buf b_doa_out21 (doa_out21, doa_out[21]); - buf b_doa_out22 (doa_out22, doa_out[22]); - buf b_doa_out23 (doa_out23, doa_out[23]); - buf b_doa_out24 (doa_out24, doa_out[24]); - buf b_doa_out25 (doa_out25, doa_out[25]); - buf b_doa_out26 (doa_out26, doa_out[26]); - buf b_doa_out27 (doa_out27, doa_out[27]); - buf b_doa_out28 (doa_out28, doa_out[28]); - buf b_doa_out29 (doa_out29, doa_out[29]); - buf b_doa_out30 (doa_out30, doa_out[30]); - buf b_doa_out31 (doa_out31, doa_out[31]); - buf b_dopa_out0 (dopa_out0, dopa_out[0]); - buf b_dopa_out1 (dopa_out1, dopa_out[1]); - buf b_dopa_out2 (dopa_out2, dopa_out[2]); - buf b_dopa_out3 (dopa_out3, dopa_out[3]); - buf b_dob_out0 (dob_out0, dob_out[0]); - buf b_dob_out1 (dob_out1, dob_out[1]); - buf b_dob_out2 (dob_out2, dob_out[2]); - buf b_dob_out3 (dob_out3, dob_out[3]); - buf b_dob_out4 (dob_out4, dob_out[4]); - buf b_dob_out5 (dob_out5, dob_out[5]); - buf b_dob_out6 (dob_out6, dob_out[6]); - buf b_dob_out7 (dob_out7, dob_out[7]); - buf b_dob_out8 (dob_out8, dob_out[8]); - buf b_dob_out9 (dob_out9, dob_out[9]); - buf b_dob_out10 (dob_out10, dob_out[10]); - buf b_dob_out11 (dob_out11, dob_out[11]); - buf b_dob_out12 (dob_out12, dob_out[12]); - buf b_dob_out13 (dob_out13, dob_out[13]); - buf b_dob_out14 (dob_out14, dob_out[14]); - buf b_dob_out15 (dob_out15, dob_out[15]); - buf b_dob_out16 (dob_out16, dob_out[16]); - buf b_dob_out17 (dob_out17, dob_out[17]); - buf b_dob_out18 (dob_out18, dob_out[18]); - buf b_dob_out19 (dob_out19, dob_out[19]); - buf b_dob_out20 (dob_out20, dob_out[20]); - buf b_dob_out21 (dob_out21, dob_out[21]); - buf b_dob_out22 (dob_out22, dob_out[22]); - buf b_dob_out23 (dob_out23, dob_out[23]); - buf b_dob_out24 (dob_out24, dob_out[24]); - buf b_dob_out25 (dob_out25, dob_out[25]); - buf b_dob_out26 (dob_out26, dob_out[26]); - buf b_dob_out27 (dob_out27, dob_out[27]); - buf b_dob_out28 (dob_out28, dob_out[28]); - buf b_dob_out29 (dob_out29, dob_out[29]); - buf b_dob_out30 (dob_out30, dob_out[30]); - buf b_dob_out31 (dob_out31, dob_out[31]); - buf b_dopb_out0 (dopb_out0, dopb_out[0]); - buf b_dopb_out1 (dopb_out1, dopb_out[1]); - buf b_dopb_out2 (dopb_out2, dopb_out[2]); - buf b_dopb_out3 (dopb_out3, dopb_out[3]); - - buf b_doa0 (DOA[0], doa_out0); - buf b_doa1 (DOA[1], doa_out1); - buf b_doa2 (DOA[2], doa_out2); - buf b_doa3 (DOA[3], doa_out3); - buf b_doa4 (DOA[4], doa_out4); - buf b_doa5 (DOA[5], doa_out5); - buf b_doa6 (DOA[6], doa_out6); - buf b_doa7 (DOA[7], doa_out7); - buf b_doa8 (DOA[8], doa_out8); - buf b_doa9 (DOA[9], doa_out9); - buf b_doa10 (DOA[10], doa_out10); - buf b_doa11 (DOA[11], doa_out11); - buf b_doa12 (DOA[12], doa_out12); - buf b_doa13 (DOA[13], doa_out13); - buf b_doa14 (DOA[14], doa_out14); - buf b_doa15 (DOA[15], doa_out15); - buf b_doa16 (DOA[16], doa_out16); - buf b_doa17 (DOA[17], doa_out17); - buf b_doa18 (DOA[18], doa_out18); - buf b_doa19 (DOA[19], doa_out19); - buf b_doa20 (DOA[20], doa_out20); - buf b_doa21 (DOA[21], doa_out21); - buf b_doa22 (DOA[22], doa_out22); - buf b_doa23 (DOA[23], doa_out23); - buf b_doa24 (DOA[24], doa_out24); - buf b_doa25 (DOA[25], doa_out25); - buf b_doa26 (DOA[26], doa_out26); - buf b_doa27 (DOA[27], doa_out27); - buf b_doa28 (DOA[28], doa_out28); - buf b_doa29 (DOA[29], doa_out29); - buf b_doa30 (DOA[30], doa_out30); - buf b_doa31 (DOA[31], doa_out31); - buf b_dopa0 (DOPA[0], dopa_out0); - buf b_dopa1 (DOPA[1], dopa_out1); - buf b_dopa2 (DOPA[2], dopa_out2); - buf b_dopa3 (DOPA[3], dopa_out3); - buf b_dob0 (DOB[0], dob_out0); - buf b_dob1 (DOB[1], dob_out1); - buf b_dob2 (DOB[2], dob_out2); - buf b_dob3 (DOB[3], dob_out3); - buf b_dob4 (DOB[4], dob_out4); - buf b_dob5 (DOB[5], dob_out5); - buf b_dob6 (DOB[6], dob_out6); - buf b_dob7 (DOB[7], dob_out7); - buf b_dob8 (DOB[8], dob_out8); - buf b_dob9 (DOB[9], dob_out9); - buf b_dob10 (DOB[10], dob_out10); - buf b_dob11 (DOB[11], dob_out11); - buf b_dob12 (DOB[12], dob_out12); - buf b_dob13 (DOB[13], dob_out13); - buf b_dob14 (DOB[14], dob_out14); - buf b_dob15 (DOB[15], dob_out15); - buf b_dob16 (DOB[16], dob_out16); - buf b_dob17 (DOB[17], dob_out17); - buf b_dob18 (DOB[18], dob_out18); - buf b_dob19 (DOB[19], dob_out19); - buf b_dob20 (DOB[20], dob_out20); - buf b_dob21 (DOB[21], dob_out21); - buf b_dob22 (DOB[22], dob_out22); - buf b_dob23 (DOB[23], dob_out23); - buf b_dob24 (DOB[24], dob_out24); - buf b_dob25 (DOB[25], dob_out25); - buf b_dob26 (DOB[26], dob_out26); - buf b_dob27 (DOB[27], dob_out27); - buf b_dob28 (DOB[28], dob_out28); - buf b_dob29 (DOB[29], dob_out29); - buf b_dob30 (DOB[30], dob_out30); - buf b_dob31 (DOB[31], dob_out31); - buf b_dopb0 (DOPB[0], dopb_out0); - buf b_dopb1 (DOPB[1], dopb_out1); - buf b_dopb2 (DOPB[2], dopb_out2); - buf b_dopb3 (DOPB[3], dopb_out3); - - buf b_addra_0 (addra_int[0], ADDRA[0]); - buf b_addra_1 (addra_int[1], ADDRA[1]); - buf b_addra_2 (addra_int[2], ADDRA[2]); - buf b_addra_3 (addra_int[3], ADDRA[3]); - buf b_addra_4 (addra_int[4], ADDRA[4]); - buf b_addra_5 (addra_int[5], ADDRA[5]); - buf b_addra_6 (addra_int[6], ADDRA[6]); - buf b_addra_7 (addra_int[7], ADDRA[7]); - buf b_addra_8 (addra_int[8], ADDRA[8]); - buf b_dia_0 (dia_int[0], DIA[0]); - buf b_dia_1 (dia_int[1], DIA[1]); - buf b_dia_2 (dia_int[2], DIA[2]); - buf b_dia_3 (dia_int[3], DIA[3]); - buf b_dia_4 (dia_int[4], DIA[4]); - buf b_dia_5 (dia_int[5], DIA[5]); - buf b_dia_6 (dia_int[6], DIA[6]); - buf b_dia_7 (dia_int[7], DIA[7]); - buf b_dia_8 (dia_int[8], DIA[8]); - buf b_dia_9 (dia_int[9], DIA[9]); - buf b_dia_10 (dia_int[10], DIA[10]); - buf b_dia_11 (dia_int[11], DIA[11]); - buf b_dia_12 (dia_int[12], DIA[12]); - buf b_dia_13 (dia_int[13], DIA[13]); - buf b_dia_14 (dia_int[14], DIA[14]); - buf b_dia_15 (dia_int[15], DIA[15]); - buf b_dia_16 (dia_int[16], DIA[16]); - buf b_dia_17 (dia_int[17], DIA[17]); - buf b_dia_18 (dia_int[18], DIA[18]); - buf b_dia_19 (dia_int[19], DIA[19]); - buf b_dia_20 (dia_int[20], DIA[20]); - buf b_dia_21 (dia_int[21], DIA[21]); - buf b_dia_22 (dia_int[22], DIA[22]); - buf b_dia_23 (dia_int[23], DIA[23]); - buf b_dia_24 (dia_int[24], DIA[24]); - buf b_dia_25 (dia_int[25], DIA[25]); - buf b_dia_26 (dia_int[26], DIA[26]); - buf b_dia_27 (dia_int[27], DIA[27]); - buf b_dia_28 (dia_int[28], DIA[28]); - buf b_dia_29 (dia_int[29], DIA[29]); - buf b_dia_30 (dia_int[30], DIA[30]); - buf b_dia_31 (dia_int[31], DIA[31]); - buf b_dipa_0 (dipa_int[0], DIPA[0]); - buf b_dipa_1 (dipa_int[1], DIPA[1]); - buf b_dipa_2 (dipa_int[2], DIPA[2]); - buf b_dipa_3 (dipa_int[3], DIPA[3]); - buf b_ena (ena_int, ENA); - buf b_clka (clka_int, CLKA); - buf b_ssra (ssra_int, SSRA); - buf b_wea (wea_int, WEA); - buf b_addrb_0 (addrb_int[0], ADDRB[0]); - buf b_addrb_1 (addrb_int[1], ADDRB[1]); - buf b_addrb_2 (addrb_int[2], ADDRB[2]); - buf b_addrb_3 (addrb_int[3], ADDRB[3]); - buf b_addrb_4 (addrb_int[4], ADDRB[4]); - buf b_addrb_5 (addrb_int[5], ADDRB[5]); - buf b_addrb_6 (addrb_int[6], ADDRB[6]); - buf b_addrb_7 (addrb_int[7], ADDRB[7]); - buf b_addrb_8 (addrb_int[8], ADDRB[8]); - buf b_dib_0 (dib_int[0], DIB[0]); - buf b_dib_1 (dib_int[1], DIB[1]); - buf b_dib_2 (dib_int[2], DIB[2]); - buf b_dib_3 (dib_int[3], DIB[3]); - buf b_dib_4 (dib_int[4], DIB[4]); - buf b_dib_5 (dib_int[5], DIB[5]); - buf b_dib_6 (dib_int[6], DIB[6]); - buf b_dib_7 (dib_int[7], DIB[7]); - buf b_dib_8 (dib_int[8], DIB[8]); - buf b_dib_9 (dib_int[9], DIB[9]); - buf b_dib_10 (dib_int[10], DIB[10]); - buf b_dib_11 (dib_int[11], DIB[11]); - buf b_dib_12 (dib_int[12], DIB[12]); - buf b_dib_13 (dib_int[13], DIB[13]); - buf b_dib_14 (dib_int[14], DIB[14]); - buf b_dib_15 (dib_int[15], DIB[15]); - buf b_dib_16 (dib_int[16], DIB[16]); - buf b_dib_17 (dib_int[17], DIB[17]); - buf b_dib_18 (dib_int[18], DIB[18]); - buf b_dib_19 (dib_int[19], DIB[19]); - buf b_dib_20 (dib_int[20], DIB[20]); - buf b_dib_21 (dib_int[21], DIB[21]); - buf b_dib_22 (dib_int[22], DIB[22]); - buf b_dib_23 (dib_int[23], DIB[23]); - buf b_dib_24 (dib_int[24], DIB[24]); - buf b_dib_25 (dib_int[25], DIB[25]); - buf b_dib_26 (dib_int[26], DIB[26]); - buf b_dib_27 (dib_int[27], DIB[27]); - buf b_dib_28 (dib_int[28], DIB[28]); - buf b_dib_29 (dib_int[29], DIB[29]); - buf b_dib_30 (dib_int[30], DIB[30]); - buf b_dib_31 (dib_int[31], DIB[31]); - buf b_dipb_0 (dipb_int[0], DIPB[0]); - buf b_dipb_1 (dipb_int[1], DIPB[1]); - buf b_dipb_2 (dipb_int[2], DIPB[2]); - buf b_dipb_3 (dipb_int[3], DIPB[3]); - buf b_enb (enb_int, ENB); - buf b_clkb (clkb_int, CLKB); - buf b_ssrb (ssrb_int, SSRB); - buf b_web (web_int, WEB); - - initial begin - for (count = 0; count < 256; count = count + 1) begin - mem[count] <= INIT_00[count]; - mem[256 * 1 + count] <= INIT_01[count]; - mem[256 * 2 + count] <= INIT_02[count]; - mem[256 * 3 + count] <= INIT_03[count]; - mem[256 * 4 + count] <= INIT_04[count]; - mem[256 * 5 + count] <= INIT_05[count]; - mem[256 * 6 + count] <= INIT_06[count]; - mem[256 * 7 + count] <= INIT_07[count]; - mem[256 * 8 + count] <= INIT_08[count]; - mem[256 * 9 + count] <= INIT_09[count]; - mem[256 * 10 + count] <= INIT_0A[count]; - mem[256 * 11 + count] <= INIT_0B[count]; - mem[256 * 12 + count] <= INIT_0C[count]; - mem[256 * 13 + count] <= INIT_0D[count]; - mem[256 * 14 + count] <= INIT_0E[count]; - mem[256 * 15 + count] <= INIT_0F[count]; - mem[256 * 16 + count] <= INIT_10[count]; - mem[256 * 17 + count] <= INIT_11[count]; - mem[256 * 18 + count] <= INIT_12[count]; - mem[256 * 19 + count] <= INIT_13[count]; - mem[256 * 20 + count] <= INIT_14[count]; - mem[256 * 21 + count] <= INIT_15[count]; - mem[256 * 22 + count] <= INIT_16[count]; - mem[256 * 23 + count] <= INIT_17[count]; - mem[256 * 24 + count] <= INIT_18[count]; - mem[256 * 25 + count] <= INIT_19[count]; - mem[256 * 26 + count] <= INIT_1A[count]; - mem[256 * 27 + count] <= INIT_1B[count]; - mem[256 * 28 + count] <= INIT_1C[count]; - mem[256 * 29 + count] <= INIT_1D[count]; - mem[256 * 30 + count] <= INIT_1E[count]; - mem[256 * 31 + count] <= INIT_1F[count]; - mem[256 * 32 + count] <= INIT_20[count]; - mem[256 * 33 + count] <= INIT_21[count]; - mem[256 * 34 + count] <= INIT_22[count]; - mem[256 * 35 + count] <= INIT_23[count]; - mem[256 * 36 + count] <= INIT_24[count]; - mem[256 * 37 + count] <= INIT_25[count]; - mem[256 * 38 + count] <= INIT_26[count]; - mem[256 * 39 + count] <= INIT_27[count]; - mem[256 * 40 + count] <= INIT_28[count]; - mem[256 * 41 + count] <= INIT_29[count]; - mem[256 * 42 + count] <= INIT_2A[count]; - mem[256 * 43 + count] <= INIT_2B[count]; - mem[256 * 44 + count] <= INIT_2C[count]; - mem[256 * 45 + count] <= INIT_2D[count]; - mem[256 * 46 + count] <= INIT_2E[count]; - mem[256 * 47 + count] <= INIT_2F[count]; - mem[256 * 48 + count] <= INIT_30[count]; - mem[256 * 49 + count] <= INIT_31[count]; - mem[256 * 50 + count] <= INIT_32[count]; - mem[256 * 51 + count] <= INIT_33[count]; - mem[256 * 52 + count] <= INIT_34[count]; - mem[256 * 53 + count] <= INIT_35[count]; - mem[256 * 54 + count] <= INIT_36[count]; - mem[256 * 55 + count] <= INIT_37[count]; - mem[256 * 56 + count] <= INIT_38[count]; - mem[256 * 57 + count] <= INIT_39[count]; - mem[256 * 58 + count] <= INIT_3A[count]; - mem[256 * 59 + count] <= INIT_3B[count]; - mem[256 * 60 + count] <= INIT_3C[count]; - mem[256 * 61 + count] <= INIT_3D[count]; - mem[256 * 62 + count] <= INIT_3E[count]; - mem[256 * 63 + count] <= INIT_3F[count]; - mem[256 * 64 + count] <= INITP_00[count]; - mem[256 * 65 + count] <= INITP_01[count]; - mem[256 * 66 + count] <= INITP_02[count]; - mem[256 * 67 + count] <= INITP_03[count]; - mem[256 * 68 + count] <= INITP_04[count]; - mem[256 * 69 + count] <= INITP_05[count]; - mem[256 * 70 + count] <= INITP_06[count]; - mem[256 * 71 + count] <= INITP_07[count]; - end - address_collision <= 0; - address_collision_a_b <= 0; - address_collision_b_a <= 0; - change_clka <= 0; - change_clkb <= 0; - data_collision <= 0; - data_collision_a_b <= 0; - data_collision_b_a <= 0; - memory_collision <= 0; - memory_collision_a_b <= 0; - memory_collision_b_a <= 0; - setup_all_a_b <= 0; - setup_all_b_a <= 0; - setup_zero <= 0; - setup_rf_a_b <= 0; - setup_rf_b_a <= 0; - end - - assign data_addra_int = addra_int * 32; - assign data_addra_reg = addra_reg * 32; - assign data_addrb_int = addrb_int * 32; - assign data_addrb_reg = addrb_reg * 32; - assign parity_addra_int = 16384 + addra_int * 4; - assign parity_addra_reg = 16384 + addra_reg * 4; - assign parity_addrb_int = 16384 + addrb_int * 4; - assign parity_addrb_reg = 16384 + addrb_reg * 4; - - - initial begin - - display_flag = 1; - - case (SIM_COLLISION_CHECK) - - "NONE" : begin - assign setup_all_a_b = 1'b0; - assign setup_all_b_a = 1'b0; - assign setup_zero = 1'b0; - assign setup_rf_a_b = 1'b0; - assign setup_rf_b_a = 1'b0; - assign display_flag = 0; - end - "WARNING_ONLY" : begin - assign data_collision = 2'b00; - assign data_collision_a_b = 2'b00; - assign data_collision_b_a = 2'b00; - assign memory_collision = 1'b0; - assign memory_collision_a_b = 1'b0; - assign memory_collision_b_a = 1'b0; - end - "GENERATE_X_ONLY" : begin - assign display_flag = 0; - end - "ALL" : ; - default : begin - $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); - $finish; - end - - endcase // case(SIM_COLLISION_CHECK) - - end // initial begin - - - always @(posedge clka_int) begin - time_clka = $time; - #0 time_clkb_clka = time_clka - time_clkb; - change_clka = ~change_clka; - end - - always @(posedge clkb_int) begin - time_clkb = $time; - #0 time_clka_clkb = time_clkb - time_clka; - change_clkb = ~change_clkb; - end - - always @(change_clkb) begin - if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) - setup_all_a_b = 1; - if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) - setup_rf_a_b = 1; - end - - always @(change_clka) begin - if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) - setup_all_b_a = 1; - if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) - setup_rf_b_a = 1; - end - - always @(change_clkb or change_clka) begin - if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) - setup_zero = 1; - end - - always @(posedge setup_zero) begin - if ((ena_int == 1) && (wea_int == 1) && - (enb_int == 1) && (web_int == 1) && - (data_addra_int[14:5] == data_addrb_int[14:5])) - memory_collision <= 1; - end - - always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin - if ((ena_reg == 1) && (wea_reg == 1) && - (enb_int == 1) && (web_int == 1) && - (data_addra_reg[14:5] == data_addrb_int[14:5])) - memory_collision_a_b <= 1; - end - - always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin - if ((ena_int == 1) && (wea_int == 1) && - (enb_reg == 1) && (web_reg == 1) && - (data_addra_int[14:5] == data_addrb_reg[14:5])) - memory_collision_b_a <= 1; - end - - always @(posedge setup_all_a_b) begin - if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin - if ((ena_reg == 1) && (enb_int == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) - 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end - 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end - 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end -// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end - 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end - 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end - 6'b101011 : begin display_wa_wb; end - 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end -// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end - 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end - 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end -// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end - 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end - 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end -// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end - 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end - 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end -// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end - 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - endcase - end - end - setup_all_a_b <= 0; - end - - - always @(posedge setup_all_b_a) begin - if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin - if ((ena_int == 1) && (enb_reg == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) - 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end -// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end - 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end -// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end - 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end - 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end - 6'b101011 : begin display_wa_wb; end - 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end -// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end - 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - endcase - end - end - setup_all_b_a <= 0; - end - - - always @(posedge setup_zero) begin - if (data_addra_int[14:5] == data_addrb_int[14:5]) begin - if ((ena_int == 1) && (enb_int == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_int, web_int}) - 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end - 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end - 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end - 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end - 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end - 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end - 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end - 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end - 6'b101011 : begin display_wa_wb; end - 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end -// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end - 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end - 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end -// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end - 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end - 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end -// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end - 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end - 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end - 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end - 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end -// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end -// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end -// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end - 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end - 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end - 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end - endcase - end - end - setup_zero <= 0; - end - - task display_ra_wb; - begin - if (display_flag) - $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); - end - endtask - - task display_wa_rb; - begin - if (display_flag) - $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); - end - endtask - - task display_wa_wb; - begin - if (display_flag) - $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); - end - endtask - - - always @(posedge setup_rf_a_b) begin - if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin - if ((ena_reg == 1) && (enb_int == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) -// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end - 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end - 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end - 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end -// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end - 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end -// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end - endcase - end - end - setup_rf_a_b <= 0; - end - - - always @(posedge setup_rf_b_a) begin - if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin - if ((ena_int == 1) && (enb_reg == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) -// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end -// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end -// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end -// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end -// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end -// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end -// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end - 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end -// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end -// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end - 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end -// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end -// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end - 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end -// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end -// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end - endcase - end - end - setup_rf_b_a <= 0; - end - - - always @(posedge clka_int) begin - addra_reg <= addra_int; - ena_reg <= ena_int; - ssra_reg <= ssra_int; - wea_reg <= wea_int; - end - - always @(posedge clkb_int) begin - addrb_reg <= addrb_int; - enb_reg <= enb_int; - ssrb_reg <= ssrb_int; - web_reg <= web_int; - end - - // Data - always @(posedge memory_collision) begin - for (dmi = 0; dmi < 32; dmi = dmi + 1) begin - mem[data_addra_int + dmi] <= 1'bX; - end - memory_collision <= 0; - end - - always @(posedge memory_collision_a_b) begin - for (dmi = 0; dmi < 32; dmi = dmi + 1) begin - mem[data_addra_reg + dmi] <= 1'bX; - end - memory_collision_a_b <= 0; - end - - always @(posedge memory_collision_b_a) begin - for (dmi = 0; dmi < 32; dmi = dmi + 1) begin - mem[data_addra_int + dmi] <= 1'bX; - end - memory_collision_b_a <= 0; - end - - always @(posedge data_collision[1]) begin - if (ssra_int == 0) begin - doa_out <= 32'bX; - end - data_collision[1] <= 0; - end - - always @(posedge data_collision[0]) begin - if (ssrb_int == 0) begin - dob_out <= 32'bX; - end - data_collision[0] <= 0; - end - - always @(posedge data_collision_a_b[1]) begin - if (ssra_reg == 0) begin - doa_out <= 32'bX; - end - data_collision_a_b[1] <= 0; - end - - always @(posedge data_collision_a_b[0]) begin - if (ssrb_int == 0) begin - dob_out <= 32'bX; - end - data_collision_a_b[0] <= 0; - end - - always @(posedge data_collision_b_a[1]) begin - if (ssra_int == 0) begin - doa_out <= 32'bX; - end - data_collision_b_a[1] <= 0; - end - - always @(posedge data_collision_b_a[0]) begin - if (ssrb_reg == 0) begin - dob_out <= 32'bX; - end - data_collision_b_a[0] <= 0; - end - - - // Parity - always @(posedge memory_collision) begin - for (pmi = 0; pmi < 4; pmi = pmi + 1) begin - mem[parity_addra_int + pmi] <= 1'bX; - end - end - - always @(posedge memory_collision_a_b) begin - for (pmi = 0; pmi < 4; pmi = pmi + 1) begin - mem[parity_addra_reg + pmi] <= 1'bX; - end - end - - always @(posedge memory_collision_b_a) begin - for (pmi = 0; pmi < 4; pmi = pmi + 1) begin - mem[parity_addra_int + pmi] <= 1'bX; - end - end - - always @(posedge data_collision[1]) begin - if (ssra_int == 0) begin - dopa_out <= 4'bX; - end - end - - always @(posedge data_collision[0]) begin - if (ssrb_int == 0) begin - dopb_out <= 4'bX; - end - end - - always @(posedge data_collision_a_b[1]) begin - if (ssra_reg == 0) begin - dopa_out <= 4'bX; - end - end - - always @(posedge data_collision_a_b[0]) begin - if (ssrb_int == 0) begin - dopb_out <= 4'bX; - end - end - - always @(posedge data_collision_b_a[1]) begin - if (ssra_int == 0) begin - dopa_out <= 4'bX; - end - end - - always @(posedge data_collision_b_a[0]) begin - if (ssrb_reg == 0) begin - dopb_out <= 4'bX; - end - end - - - initial begin - case (WRITE_MODE_A) - "WRITE_FIRST" : wr_mode_a <= 2'b00; - "READ_FIRST" : wr_mode_a <= 2'b01; - "NO_CHANGE" : wr_mode_a <= 2'b10; - default : begin - $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); - $finish; - end - endcase - end - - initial begin - case (WRITE_MODE_B) - "WRITE_FIRST" : wr_mode_b <= 2'b00; - "READ_FIRST" : wr_mode_b <= 2'b01; - "NO_CHANGE" : wr_mode_b <= 2'b10; - default : begin - $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); - $finish; - end - endcase - end - - // Port A - always @(posedge clka_int) begin - if (ena_int == 1'b1) begin - if (ssra_int == 1'b1) begin - doa_out[0] <= SRVAL_A[0]; - doa_out[1] <= SRVAL_A[1]; - doa_out[2] <= SRVAL_A[2]; - doa_out[3] <= SRVAL_A[3]; - doa_out[4] <= SRVAL_A[4]; - doa_out[5] <= SRVAL_A[5]; - doa_out[6] <= SRVAL_A[6]; - doa_out[7] <= SRVAL_A[7]; - doa_out[8] <= SRVAL_A[8]; - doa_out[9] <= SRVAL_A[9]; - doa_out[10] <= SRVAL_A[10]; - doa_out[11] <= SRVAL_A[11]; - doa_out[12] <= SRVAL_A[12]; - doa_out[13] <= SRVAL_A[13]; - doa_out[14] <= SRVAL_A[14]; - doa_out[15] <= SRVAL_A[15]; - doa_out[16] <= SRVAL_A[16]; - doa_out[17] <= SRVAL_A[17]; - doa_out[18] <= SRVAL_A[18]; - doa_out[19] <= SRVAL_A[19]; - doa_out[20] <= SRVAL_A[20]; - doa_out[21] <= SRVAL_A[21]; - doa_out[22] <= SRVAL_A[22]; - doa_out[23] <= SRVAL_A[23]; - doa_out[24] <= SRVAL_A[24]; - doa_out[25] <= SRVAL_A[25]; - doa_out[26] <= SRVAL_A[26]; - doa_out[27] <= SRVAL_A[27]; - doa_out[28] <= SRVAL_A[28]; - doa_out[29] <= SRVAL_A[29]; - doa_out[30] <= SRVAL_A[30]; - doa_out[31] <= SRVAL_A[31]; - dopa_out[0] <= SRVAL_A[32]; - dopa_out[1] <= SRVAL_A[33]; - dopa_out[2] <= SRVAL_A[34]; - dopa_out[3] <= SRVAL_A[35]; - end - else begin - if (wea_int == 1'b1) begin - if (wr_mode_a == 2'b00) begin - doa_out <= dia_int; - dopa_out <= dipa_int; - end - else if (wr_mode_a == 2'b01) begin - doa_out[0] <= mem[data_addra_int + 0]; - doa_out[1] <= mem[data_addra_int + 1]; - doa_out[2] <= mem[data_addra_int + 2]; - doa_out[3] <= mem[data_addra_int + 3]; - doa_out[4] <= mem[data_addra_int + 4]; - doa_out[5] <= mem[data_addra_int + 5]; - doa_out[6] <= mem[data_addra_int + 6]; - doa_out[7] <= mem[data_addra_int + 7]; - doa_out[8] <= mem[data_addra_int + 8]; - doa_out[9] <= mem[data_addra_int + 9]; - doa_out[10] <= mem[data_addra_int + 10]; - doa_out[11] <= mem[data_addra_int + 11]; - doa_out[12] <= mem[data_addra_int + 12]; - doa_out[13] <= mem[data_addra_int + 13]; - doa_out[14] <= mem[data_addra_int + 14]; - doa_out[15] <= mem[data_addra_int + 15]; - doa_out[16] <= mem[data_addra_int + 16]; - doa_out[17] <= mem[data_addra_int + 17]; - doa_out[18] <= mem[data_addra_int + 18]; - doa_out[19] <= mem[data_addra_int + 19]; - doa_out[20] <= mem[data_addra_int + 20]; - doa_out[21] <= mem[data_addra_int + 21]; - doa_out[22] <= mem[data_addra_int + 22]; - doa_out[23] <= mem[data_addra_int + 23]; - doa_out[24] <= mem[data_addra_int + 24]; - doa_out[25] <= mem[data_addra_int + 25]; - doa_out[26] <= mem[data_addra_int + 26]; - doa_out[27] <= mem[data_addra_int + 27]; - doa_out[28] <= mem[data_addra_int + 28]; - doa_out[29] <= mem[data_addra_int + 29]; - doa_out[30] <= mem[data_addra_int + 30]; - doa_out[31] <= mem[data_addra_int + 31]; - dopa_out[0] <= mem[parity_addra_int + 0]; - dopa_out[1] <= mem[parity_addra_int + 1]; - dopa_out[2] <= mem[parity_addra_int + 2]; - dopa_out[3] <= mem[parity_addra_int + 3]; - end - end - else begin - doa_out[0] <= mem[data_addra_int + 0]; - doa_out[1] <= mem[data_addra_int + 1]; - doa_out[2] <= mem[data_addra_int + 2]; - doa_out[3] <= mem[data_addra_int + 3]; - doa_out[4] <= mem[data_addra_int + 4]; - doa_out[5] <= mem[data_addra_int + 5]; - doa_out[6] <= mem[data_addra_int + 6]; - doa_out[7] <= mem[data_addra_int + 7]; - doa_out[8] <= mem[data_addra_int + 8]; - doa_out[9] <= mem[data_addra_int + 9]; - doa_out[10] <= mem[data_addra_int + 10]; - doa_out[11] <= mem[data_addra_int + 11]; - doa_out[12] <= mem[data_addra_int + 12]; - doa_out[13] <= mem[data_addra_int + 13]; - doa_out[14] <= mem[data_addra_int + 14]; - doa_out[15] <= mem[data_addra_int + 15]; - doa_out[16] <= mem[data_addra_int + 16]; - doa_out[17] <= mem[data_addra_int + 17]; - doa_out[18] <= mem[data_addra_int + 18]; - doa_out[19] <= mem[data_addra_int + 19]; - doa_out[20] <= mem[data_addra_int + 20]; - doa_out[21] <= mem[data_addra_int + 21]; - doa_out[22] <= mem[data_addra_int + 22]; - doa_out[23] <= mem[data_addra_int + 23]; - doa_out[24] <= mem[data_addra_int + 24]; - doa_out[25] <= mem[data_addra_int + 25]; - doa_out[26] <= mem[data_addra_int + 26]; - doa_out[27] <= mem[data_addra_int + 27]; - doa_out[28] <= mem[data_addra_int + 28]; - doa_out[29] <= mem[data_addra_int + 29]; - doa_out[30] <= mem[data_addra_int + 30]; - doa_out[31] <= mem[data_addra_int + 31]; - dopa_out[0] <= mem[parity_addra_int + 0]; - dopa_out[1] <= mem[parity_addra_int + 1]; - dopa_out[2] <= mem[parity_addra_int + 2]; - dopa_out[3] <= mem[parity_addra_int + 3]; - end - end - end - end - - always @(posedge clka_int) begin - if (ena_int == 1'b1 && wea_int == 1'b1) begin - mem[data_addra_int + 0] <= dia_int[0]; - mem[data_addra_int + 1] <= dia_int[1]; - mem[data_addra_int + 2] <= dia_int[2]; - mem[data_addra_int + 3] <= dia_int[3]; - mem[data_addra_int + 4] <= dia_int[4]; - mem[data_addra_int + 5] <= dia_int[5]; - mem[data_addra_int + 6] <= dia_int[6]; - mem[data_addra_int + 7] <= dia_int[7]; - mem[data_addra_int + 8] <= dia_int[8]; - mem[data_addra_int + 9] <= dia_int[9]; - mem[data_addra_int + 10] <= dia_int[10]; - mem[data_addra_int + 11] <= dia_int[11]; - mem[data_addra_int + 12] <= dia_int[12]; - mem[data_addra_int + 13] <= dia_int[13]; - mem[data_addra_int + 14] <= dia_int[14]; - mem[data_addra_int + 15] <= dia_int[15]; - mem[data_addra_int + 16] <= dia_int[16]; - mem[data_addra_int + 17] <= dia_int[17]; - mem[data_addra_int + 18] <= dia_int[18]; - mem[data_addra_int + 19] <= dia_int[19]; - mem[data_addra_int + 20] <= dia_int[20]; - mem[data_addra_int + 21] <= dia_int[21]; - mem[data_addra_int + 22] <= dia_int[22]; - mem[data_addra_int + 23] <= dia_int[23]; - mem[data_addra_int + 24] <= dia_int[24]; - mem[data_addra_int + 25] <= dia_int[25]; - mem[data_addra_int + 26] <= dia_int[26]; - mem[data_addra_int + 27] <= dia_int[27]; - mem[data_addra_int + 28] <= dia_int[28]; - mem[data_addra_int + 29] <= dia_int[29]; - mem[data_addra_int + 30] <= dia_int[30]; - mem[data_addra_int + 31] <= dia_int[31]; - mem[parity_addra_int + 0] <= dipa_int[0]; - mem[parity_addra_int + 1] <= dipa_int[1]; - mem[parity_addra_int + 2] <= dipa_int[2]; - mem[parity_addra_int + 3] <= dipa_int[3]; - end - end - - // Port B - always @(posedge clkb_int) begin - if (enb_int == 1'b1) begin - if (ssrb_int == 1'b1) begin - dob_out[0] <= SRVAL_B[0]; - dob_out[1] <= SRVAL_B[1]; - dob_out[2] <= SRVAL_B[2]; - dob_out[3] <= SRVAL_B[3]; - dob_out[4] <= SRVAL_B[4]; - dob_out[5] <= SRVAL_B[5]; - dob_out[6] <= SRVAL_B[6]; - dob_out[7] <= SRVAL_B[7]; - dob_out[8] <= SRVAL_B[8]; - dob_out[9] <= SRVAL_B[9]; - dob_out[10] <= SRVAL_B[10]; - dob_out[11] <= SRVAL_B[11]; - dob_out[12] <= SRVAL_B[12]; - dob_out[13] <= SRVAL_B[13]; - dob_out[14] <= SRVAL_B[14]; - dob_out[15] <= SRVAL_B[15]; - dob_out[16] <= SRVAL_B[16]; - dob_out[17] <= SRVAL_B[17]; - dob_out[18] <= SRVAL_B[18]; - dob_out[19] <= SRVAL_B[19]; - dob_out[20] <= SRVAL_B[20]; - dob_out[21] <= SRVAL_B[21]; - dob_out[22] <= SRVAL_B[22]; - dob_out[23] <= SRVAL_B[23]; - dob_out[24] <= SRVAL_B[24]; - dob_out[25] <= SRVAL_B[25]; - dob_out[26] <= SRVAL_B[26]; - dob_out[27] <= SRVAL_B[27]; - dob_out[28] <= SRVAL_B[28]; - dob_out[29] <= SRVAL_B[29]; - dob_out[30] <= SRVAL_B[30]; - dob_out[31] <= SRVAL_B[31]; - dopb_out[0] <= SRVAL_B[32]; - dopb_out[1] <= SRVAL_B[33]; - dopb_out[2] <= SRVAL_B[34]; - dopb_out[3] <= SRVAL_B[35]; - end - else begin - if (web_int == 1'b1) begin - if (wr_mode_b == 2'b00) begin - dob_out <= dib_int; - dopb_out <= dipb_int; - end - else if (wr_mode_b == 2'b01) begin - dob_out[0] <= mem[data_addrb_int + 0]; - dob_out[1] <= mem[data_addrb_int + 1]; - dob_out[2] <= mem[data_addrb_int + 2]; - dob_out[3] <= mem[data_addrb_int + 3]; - dob_out[4] <= mem[data_addrb_int + 4]; - dob_out[5] <= mem[data_addrb_int + 5]; - dob_out[6] <= mem[data_addrb_int + 6]; - dob_out[7] <= mem[data_addrb_int + 7]; - dob_out[8] <= mem[data_addrb_int + 8]; - dob_out[9] <= mem[data_addrb_int + 9]; - dob_out[10] <= mem[data_addrb_int + 10]; - dob_out[11] <= mem[data_addrb_int + 11]; - dob_out[12] <= mem[data_addrb_int + 12]; - dob_out[13] <= mem[data_addrb_int + 13]; - dob_out[14] <= mem[data_addrb_int + 14]; - dob_out[15] <= mem[data_addrb_int + 15]; - dob_out[16] <= mem[data_addrb_int + 16]; - dob_out[17] <= mem[data_addrb_int + 17]; - dob_out[18] <= mem[data_addrb_int + 18]; - dob_out[19] <= mem[data_addrb_int + 19]; - dob_out[20] <= mem[data_addrb_int + 20]; - dob_out[21] <= mem[data_addrb_int + 21]; - dob_out[22] <= mem[data_addrb_int + 22]; - dob_out[23] <= mem[data_addrb_int + 23]; - dob_out[24] <= mem[data_addrb_int + 24]; - dob_out[25] <= mem[data_addrb_int + 25]; - dob_out[26] <= mem[data_addrb_int + 26]; - dob_out[27] <= mem[data_addrb_int + 27]; - dob_out[28] <= mem[data_addrb_int + 28]; - dob_out[29] <= mem[data_addrb_int + 29]; - dob_out[30] <= mem[data_addrb_int + 30]; - dob_out[31] <= mem[data_addrb_int + 31]; - dopb_out[0] <= mem[parity_addrb_int + 0]; - dopb_out[1] <= mem[parity_addrb_int + 1]; - dopb_out[2] <= mem[parity_addrb_int + 2]; - dopb_out[3] <= mem[parity_addrb_int + 3]; - end - end - else begin - dob_out[0] <= mem[data_addrb_int + 0]; - dob_out[1] <= mem[data_addrb_int + 1]; - dob_out[2] <= mem[data_addrb_int + 2]; - dob_out[3] <= mem[data_addrb_int + 3]; - dob_out[4] <= mem[data_addrb_int + 4]; - dob_out[5] <= mem[data_addrb_int + 5]; - dob_out[6] <= mem[data_addrb_int + 6]; - dob_out[7] <= mem[data_addrb_int + 7]; - dob_out[8] <= mem[data_addrb_int + 8]; - dob_out[9] <= mem[data_addrb_int + 9]; - dob_out[10] <= mem[data_addrb_int + 10]; - dob_out[11] <= mem[data_addrb_int + 11]; - dob_out[12] <= mem[data_addrb_int + 12]; - dob_out[13] <= mem[data_addrb_int + 13]; - dob_out[14] <= mem[data_addrb_int + 14]; - dob_out[15] <= mem[data_addrb_int + 15]; - dob_out[16] <= mem[data_addrb_int + 16]; - dob_out[17] <= mem[data_addrb_int + 17]; - dob_out[18] <= mem[data_addrb_int + 18]; - dob_out[19] <= mem[data_addrb_int + 19]; - dob_out[20] <= mem[data_addrb_int + 20]; - dob_out[21] <= mem[data_addrb_int + 21]; - dob_out[22] <= mem[data_addrb_int + 22]; - dob_out[23] <= mem[data_addrb_int + 23]; - dob_out[24] <= mem[data_addrb_int + 24]; - dob_out[25] <= mem[data_addrb_int + 25]; - dob_out[26] <= mem[data_addrb_int + 26]; - dob_out[27] <= mem[data_addrb_int + 27]; - dob_out[28] <= mem[data_addrb_int + 28]; - dob_out[29] <= mem[data_addrb_int + 29]; - dob_out[30] <= mem[data_addrb_int + 30]; - dob_out[31] <= mem[data_addrb_int + 31]; - dopb_out[0] <= mem[parity_addrb_int + 0]; - dopb_out[1] <= mem[parity_addrb_int + 1]; - dopb_out[2] <= mem[parity_addrb_int + 2]; - dopb_out[3] <= mem[parity_addrb_int + 3]; - end - end - end - end - - always @(posedge clkb_int) begin - if (enb_int == 1'b1 && web_int == 1'b1) begin - mem[data_addrb_int + 0] <= dib_int[0]; - mem[data_addrb_int + 1] <= dib_int[1]; - mem[data_addrb_int + 2] <= dib_int[2]; - mem[data_addrb_int + 3] <= dib_int[3]; - mem[data_addrb_int + 4] <= dib_int[4]; - mem[data_addrb_int + 5] <= dib_int[5]; - mem[data_addrb_int + 6] <= dib_int[6]; - mem[data_addrb_int + 7] <= dib_int[7]; - mem[data_addrb_int + 8] <= dib_int[8]; - mem[data_addrb_int + 9] <= dib_int[9]; - mem[data_addrb_int + 10] <= dib_int[10]; - mem[data_addrb_int + 11] <= dib_int[11]; - mem[data_addrb_int + 12] <= dib_int[12]; - mem[data_addrb_int + 13] <= dib_int[13]; - mem[data_addrb_int + 14] <= dib_int[14]; - mem[data_addrb_int + 15] <= dib_int[15]; - mem[data_addrb_int + 16] <= dib_int[16]; - mem[data_addrb_int + 17] <= dib_int[17]; - mem[data_addrb_int + 18] <= dib_int[18]; - mem[data_addrb_int + 19] <= dib_int[19]; - mem[data_addrb_int + 20] <= dib_int[20]; - mem[data_addrb_int + 21] <= dib_int[21]; - mem[data_addrb_int + 22] <= dib_int[22]; - mem[data_addrb_int + 23] <= dib_int[23]; - mem[data_addrb_int + 24] <= dib_int[24]; - mem[data_addrb_int + 25] <= dib_int[25]; - mem[data_addrb_int + 26] <= dib_int[26]; - mem[data_addrb_int + 27] <= dib_int[27]; - mem[data_addrb_int + 28] <= dib_int[28]; - mem[data_addrb_int + 29] <= dib_int[29]; - mem[data_addrb_int + 30] <= dib_int[30]; - mem[data_addrb_int + 31] <= dib_int[31]; - mem[parity_addrb_int + 0] <= dipb_int[0]; - mem[parity_addrb_int + 1] <= dipb_int[1]; - mem[parity_addrb_int + 2] <= dipb_int[2]; - mem[parity_addrb_int + 3] <= dipb_int[3]; - end - end - - specify - (CLKA *> DOA) = (100, 100); - (CLKA *> DOPA) = (100, 100); - (CLKB *> DOB) = (100, 100); - (CLKB *> DOPB) = (100, 100); - endspecify - -endmodule - -`else - -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2005 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 10.1 -// \ \ Description : Xilinx Timing Simulation Library Component -// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM -// /___/ /\ Filename : RAMB16_S36_S36.v -// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 -// \___\/\___\ -// -// Revision: -// 03/23/04 - Initial version. -// 03/10/05 - Initialized outputs. -// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). -// End Revision - -`timescale 1 ps/1 ps - -module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); - - parameter INIT_A = 36'h0; - parameter INIT_B = 36'h0; - parameter SRVAL_A = 36'h0; - parameter SRVAL_B = 36'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - localparam SETUP_ALL = 1000; - localparam SETUP_READ_FIRST = 3000; - - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - - output [31:0] DOA; - output [3:0] DOPA; - output [31:0] DOB; - output [3:0] DOPB; - - input [8:0] ADDRA; - input [31:0] DIA; - input [3:0] DIPA; - input ENA, CLKA, WEA, SSRA; - input [8:0] ADDRB; - input [31:0] DIB; - input [3:0] DIPB; - input ENB, CLKB, WEB, SSRB; - - reg [31:0] doa_out = INIT_A[31:0]; - reg [3:0] dopa_out = INIT_A[35:32]; - reg [31:0] dob_out = INIT_B[31:0]; - reg [3:0] dopb_out = INIT_B[35:32]; - - reg [31:0] mem [511:0]; - reg [3:0] memp [511:0]; - - reg [8:0] count, countp; - reg [1:0] wr_mode_a, wr_mode_b; - - reg [5:0] dmi, dbi; - reg [5:0] pmi, pbi; - - wire [8:0] addra_int; - reg [8:0] addra_reg; - wire [31:0] dia_int; - wire [3:0] dipa_int; - wire ena_int, clka_int, wea_int, ssra_int; - reg ena_reg, wea_reg, ssra_reg; - wire [8:0] addrb_int; - reg [8:0] addrb_reg; - wire [31:0] dib_int; - wire [3:0] dipb_int; - wire enb_int, clkb_int, web_int, ssrb_int; - reg display_flag, output_flag; - reg enb_reg, web_reg, ssrb_reg; - - time time_clka, time_clkb; - time time_clka_clkb; - time time_clkb_clka; - - reg setup_all_a_b; - reg setup_all_b_a; - reg setup_zero; - reg setup_rf_a_b; - reg setup_rf_b_a; - reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; - reg memory_collision, memory_collision_a_b, memory_collision_b_a; - reg change_clka; - reg change_clkb; - - wire [14:0] data_addra_int; - wire [14:0] data_addra_reg; - wire [14:0] data_addrb_int; - wire [14:0] data_addrb_reg; - - wire dia_enable = ena_int && wea_int; - wire dib_enable = enb_int && web_int; - - tri0 GSR = glbl.GSR; - wire gsr_int; - - buf b_gsr (gsr_int, GSR); - - buf b_doa [31:0] (DOA, doa_out); - buf b_dopa [3:0] (DOPA, dopa_out); - buf b_addra [8:0] (addra_int, ADDRA); - buf b_dia [31:0] (dia_int, DIA); - buf b_dipa [3:0] (dipa_int, DIPA); - buf b_ena (ena_int, ENA); - buf b_clka (clka_int, CLKA); - buf b_ssra (ssra_int, SSRA); - buf b_wea (wea_int, WEA); - - buf b_dob [31:0] (DOB, dob_out); - buf b_dopb [3:0] (DOPB, dopb_out); - buf b_addrb [8:0] (addrb_int, ADDRB); - buf b_dib [31:0] (dib_int, DIB); - buf b_dipb [3:0] (dipb_int, DIPB); - buf b_enb (enb_int, ENB); - buf b_clkb (clkb_int, CLKB); - buf b_ssrb (ssrb_int, SSRB); - buf b_web (web_int, WEB); - - - always @(gsr_int) - if (gsr_int) begin - assign {dopa_out, doa_out} = INIT_A; - assign {dopb_out, dob_out} = INIT_B; - end - else begin - deassign doa_out; - deassign dopa_out; - deassign dob_out; - deassign dopb_out; - end - - - initial begin - - for (count = 0; count < 8; count = count + 1) begin - mem[count] = INIT_00[(count * 32) +: 32]; - mem[8 * 1 + count] = INIT_01[(count * 32) +: 32]; - mem[8 * 2 + count] = INIT_02[(count * 32) +: 32]; - mem[8 * 3 + count] = INIT_03[(count * 32) +: 32]; - mem[8 * 4 + count] = INIT_04[(count * 32) +: 32]; - mem[8 * 5 + count] = INIT_05[(count * 32) +: 32]; - mem[8 * 6 + count] = INIT_06[(count * 32) +: 32]; - mem[8 * 7 + count] = INIT_07[(count * 32) +: 32]; - mem[8 * 8 + count] = INIT_08[(count * 32) +: 32]; - mem[8 * 9 + count] = INIT_09[(count * 32) +: 32]; - mem[8 * 10 + count] = INIT_0A[(count * 32) +: 32]; - mem[8 * 11 + count] = INIT_0B[(count * 32) +: 32]; - mem[8 * 12 + count] = INIT_0C[(count * 32) +: 32]; - mem[8 * 13 + count] = INIT_0D[(count * 32) +: 32]; - mem[8 * 14 + count] = INIT_0E[(count * 32) +: 32]; - mem[8 * 15 + count] = INIT_0F[(count * 32) +: 32]; - mem[8 * 16 + count] = INIT_10[(count * 32) +: 32]; - mem[8 * 17 + count] = INIT_11[(count * 32) +: 32]; - mem[8 * 18 + count] = INIT_12[(count * 32) +: 32]; - mem[8 * 19 + count] = INIT_13[(count * 32) +: 32]; - mem[8 * 20 + count] = INIT_14[(count * 32) +: 32]; - mem[8 * 21 + count] = INIT_15[(count * 32) +: 32]; - mem[8 * 22 + count] = INIT_16[(count * 32) +: 32]; - mem[8 * 23 + count] = INIT_17[(count * 32) +: 32]; - mem[8 * 24 + count] = INIT_18[(count * 32) +: 32]; - mem[8 * 25 + count] = INIT_19[(count * 32) +: 32]; - mem[8 * 26 + count] = INIT_1A[(count * 32) +: 32]; - mem[8 * 27 + count] = INIT_1B[(count * 32) +: 32]; - mem[8 * 28 + count] = INIT_1C[(count * 32) +: 32]; - mem[8 * 29 + count] = INIT_1D[(count * 32) +: 32]; - mem[8 * 30 + count] = INIT_1E[(count * 32) +: 32]; - mem[8 * 31 + count] = INIT_1F[(count * 32) +: 32]; - mem[8 * 32 + count] = INIT_20[(count * 32) +: 32]; - mem[8 * 33 + count] = INIT_21[(count * 32) +: 32]; - mem[8 * 34 + count] = INIT_22[(count * 32) +: 32]; - mem[8 * 35 + count] = INIT_23[(count * 32) +: 32]; - mem[8 * 36 + count] = INIT_24[(count * 32) +: 32]; - mem[8 * 37 + count] = INIT_25[(count * 32) +: 32]; - mem[8 * 38 + count] = INIT_26[(count * 32) +: 32]; - mem[8 * 39 + count] = INIT_27[(count * 32) +: 32]; - mem[8 * 40 + count] = INIT_28[(count * 32) +: 32]; - mem[8 * 41 + count] = INIT_29[(count * 32) +: 32]; - mem[8 * 42 + count] = INIT_2A[(count * 32) +: 32]; - mem[8 * 43 + count] = INIT_2B[(count * 32) +: 32]; - mem[8 * 44 + count] = INIT_2C[(count * 32) +: 32]; - mem[8 * 45 + count] = INIT_2D[(count * 32) +: 32]; - mem[8 * 46 + count] = INIT_2E[(count * 32) +: 32]; - mem[8 * 47 + count] = INIT_2F[(count * 32) +: 32]; - mem[8 * 48 + count] = INIT_30[(count * 32) +: 32]; - mem[8 * 49 + count] = INIT_31[(count * 32) +: 32]; - mem[8 * 50 + count] = INIT_32[(count * 32) +: 32]; - mem[8 * 51 + count] = INIT_33[(count * 32) +: 32]; - mem[8 * 52 + count] = INIT_34[(count * 32) +: 32]; - mem[8 * 53 + count] = INIT_35[(count * 32) +: 32]; - mem[8 * 54 + count] = INIT_36[(count * 32) +: 32]; - mem[8 * 55 + count] = INIT_37[(count * 32) +: 32]; - mem[8 * 56 + count] = INIT_38[(count * 32) +: 32]; - mem[8 * 57 + count] = INIT_39[(count * 32) +: 32]; - mem[8 * 58 + count] = INIT_3A[(count * 32) +: 32]; - mem[8 * 59 + count] = INIT_3B[(count * 32) +: 32]; - mem[8 * 60 + count] = INIT_3C[(count * 32) +: 32]; - mem[8 * 61 + count] = INIT_3D[(count * 32) +: 32]; - mem[8 * 62 + count] = INIT_3E[(count * 32) +: 32]; - mem[8 * 63 + count] = INIT_3F[(count * 32) +: 32]; - end - -// initiate parity start - for (countp = 0; countp < 64; countp = countp + 1) begin - memp[countp] = INITP_00[(countp * 4) +: 4]; - memp[64 * 1 + countp] = INITP_01[(countp * 4) +: 4]; - memp[64 * 2 + countp] = INITP_02[(countp * 4) +: 4]; - memp[64 * 3 + countp] = INITP_03[(countp * 4) +: 4]; - memp[64 * 4 + countp] = INITP_04[(countp * 4) +: 4]; - memp[64 * 5 + countp] = INITP_05[(countp * 4) +: 4]; - memp[64 * 6 + countp] = INITP_06[(countp * 4) +: 4]; - memp[64 * 7 + countp] = INITP_07[(countp * 4) +: 4]; - end -// initiate parity end - - change_clka <= 0; - change_clkb <= 0; - data_collision <= 0; - data_collision_a_b <= 0; - data_collision_b_a <= 0; - memory_collision <= 0; - memory_collision_a_b <= 0; - memory_collision_b_a <= 0; - setup_all_a_b <= 0; - setup_all_b_a <= 0; - setup_zero <= 0; - setup_rf_a_b <= 0; - setup_rf_b_a <= 0; - end - - assign data_addra_int = addra_int * 32; - assign data_addra_reg = addra_reg * 32; - assign data_addrb_int = addrb_int * 32; - assign data_addrb_reg = addrb_reg * 32; - - - initial begin - - display_flag = 1; - output_flag = 1; - - case (SIM_COLLISION_CHECK) - - "NONE" : begin - output_flag = 0; - display_flag = 0; - end - "WARNING_ONLY" : output_flag = 0; - "GENERATE_X_ONLY" : display_flag = 0; - "ALL" : ; - - default : begin - $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); - $finish; - end - - endcase // case(SIM_COLLISION_CHECK) - - end // initial begin - - - always @(posedge clka_int) begin - if ((output_flag || display_flag)) begin - time_clka = $time; - #0 time_clkb_clka = time_clka - time_clkb; - change_clka = ~change_clka; - end - end - - always @(posedge clkb_int) begin - if ((output_flag || display_flag)) begin - time_clkb = $time; - #0 time_clka_clkb = time_clkb - time_clka; - change_clkb = ~change_clkb; - end - end - - always @(change_clkb) begin - if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) - setup_all_a_b = 1; - if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) - setup_rf_a_b = 1; - end - - always @(change_clka) begin - if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) - setup_all_b_a = 1; - if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) - setup_rf_b_a = 1; - end - - always @(change_clkb or change_clka) begin - if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) - setup_zero = 1; - end - - always @(posedge setup_zero) begin - if ((ena_int == 1) && (wea_int == 1) && - (enb_int == 1) && (web_int == 1) && - (data_addra_int[14:5] == data_addrb_int[14:5])) - memory_collision <= 1; - end - - always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin - if ((ena_reg == 1) && (wea_reg == 1) && - (enb_int == 1) && (web_int == 1) && - (data_addra_reg[14:5] == data_addrb_int[14:5])) - memory_collision_a_b <= 1; - end - - always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin - if ((ena_int == 1) && (wea_int == 1) && - (enb_reg == 1) && (web_reg == 1) && - (data_addra_int[14:5] == data_addrb_reg[14:5])) - memory_collision_b_a <= 1; - end - - always @(posedge setup_all_a_b) begin - if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin - if ((ena_reg == 1) && (enb_int == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) - 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end - 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end - 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end -// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end - 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end - 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end - 6'b101011 : begin display_wa_wb; end - 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end -// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end - 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end - 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end -// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end - 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end - 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end -// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end - 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end - 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end -// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end - 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - endcase - end - end - setup_all_a_b <= 0; - end - - - always @(posedge setup_all_b_a) begin - if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin - if ((ena_int == 1) && (enb_reg == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) - 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end -// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end - 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end -// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end - 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end - 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end - 6'b101011 : begin display_wa_wb; end - 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end -// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end - 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - endcase - end - end - setup_all_b_a <= 0; - end - - - always @(posedge setup_zero) begin - if (data_addra_int[14:5] == data_addrb_int[14:5]) begin - if ((ena_int == 1) && (enb_int == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_int, web_int}) - 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end - 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end - 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end - 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end - 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end - 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end - 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end - 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end - 6'b101011 : begin display_wa_wb; end - 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end -// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end - 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end - 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end -// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end - 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end - 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end -// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end - 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end - 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end - 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end - 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end -// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end -// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end -// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end - 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end - 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end - 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end - endcase - end - end - setup_zero <= 0; - end - - task display_ra_wb; - begin - if (display_flag) - $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); - end - endtask - - task display_wa_rb; - begin - if (display_flag) - $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); - end - endtask - - task display_wa_wb; - begin - if (display_flag) - $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); - end - endtask - - - always @(posedge setup_rf_a_b) begin - if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin - if ((ena_reg == 1) && (enb_int == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) -// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end - 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end - 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end - 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end -// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end - 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end -// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end - endcase - end - end - setup_rf_a_b <= 0; - end - - - always @(posedge setup_rf_b_a) begin - if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin - if ((ena_int == 1) && (enb_reg == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) -// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end -// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end -// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end -// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end -// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end -// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end -// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end - 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end -// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end -// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end - 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end -// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end -// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end - 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end -// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end -// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end - endcase - end - end - setup_rf_b_a <= 0; - end - - - always @(posedge clka_int) begin - if ((output_flag || display_flag)) begin - addra_reg <= addra_int; - ena_reg <= ena_int; - ssra_reg <= ssra_int; - wea_reg <= wea_int; - end - end - - always @(posedge clkb_int) begin - if ((output_flag || display_flag)) begin - addrb_reg <= addrb_int; - enb_reg <= enb_int; - ssrb_reg <= ssrb_int; - web_reg <= web_int; - end - end - - - // Data - always @(posedge memory_collision) begin - if ((output_flag || display_flag)) begin - mem[addra_int] <= 32'bx; - memory_collision <= 0; - end - - end - - always @(posedge memory_collision_a_b) begin - if ((output_flag || display_flag)) begin - mem[addra_reg] <= 32'bx; - memory_collision_a_b <= 0; - end - end - - always @(posedge memory_collision_b_a) begin - if ((output_flag || display_flag)) begin - mem[addra_int] <= 32'bx; - memory_collision_b_a <= 0; - end - end - - always @(posedge data_collision[1]) begin - if (ssra_int == 0 && output_flag) begin - doa_out <= #100 32'bX; - end - data_collision[1] <= 0; - end - - always @(posedge data_collision[0]) begin - if (ssrb_int == 0 && output_flag) begin - dob_out <= #100 32'bX; - end - data_collision[0] <= 0; - end - - always @(posedge data_collision_a_b[1]) begin - if (ssra_reg == 0 && output_flag) begin - doa_out <= #100 32'bX; - end - data_collision_a_b[1] <= 0; - end - - always @(posedge data_collision_a_b[0]) begin - if (ssrb_int == 0 && output_flag) begin - dob_out <= #100 32'bX; - end - data_collision_a_b[0] <= 0; - end - - always @(posedge data_collision_b_a[1]) begin - if (ssra_int == 0 && output_flag) begin - doa_out <= #100 32'bX; - end - data_collision_b_a[1] <= 0; - end - - always @(posedge data_collision_b_a[0]) begin - if (ssrb_reg == 0 && output_flag) begin - dob_out <= #100 32'bX; - end - data_collision_b_a[0] <= 0; - end - -// x parity start - always @(posedge memory_collision) begin - if ((output_flag || display_flag)) - memp[addra_int] <= 4'bx; - end - - always @(posedge memory_collision_a_b) begin - if ((output_flag || display_flag)) - memp[addra_reg] <= 4'bx; - end - - always @(posedge memory_collision_b_a) begin - if ((output_flag || display_flag)) - memp[addra_int] <= 4'bx; - end - - always @(posedge data_collision[1]) begin - if (ssra_int == 0 && output_flag) begin - dopa_out <= #100 4'bX; - end - end - - always @(posedge data_collision_a_b[1]) begin - if (ssra_reg == 0 && output_flag) begin - dopa_out <= #100 4'bX; - end - end - - - always @(posedge data_collision_b_a[1]) begin - if (ssra_int == 0 && output_flag) begin - dopa_out <= #100 4'bX; - end - end - - always @(posedge data_collision[0]) begin - if (ssrb_int == 0 && output_flag) begin - dopb_out <= #100 4'bx; - end - end - - always @(posedge data_collision_a_b[0]) begin - if (ssrb_int == 0 && output_flag) begin - dopb_out <= #100 4'bx; - end - end - - always @(posedge data_collision_b_a[0]) begin - if (ssrb_reg == 0 && output_flag) begin - dopb_out <= #100 4'bx; - end - end -// x parity end - - initial begin - case (WRITE_MODE_A) - "WRITE_FIRST" : wr_mode_a <= 2'b00; - "READ_FIRST" : wr_mode_a <= 2'b01; - "NO_CHANGE" : wr_mode_a <= 2'b10; - default : begin - $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); - $finish; - end - endcase - end - - initial begin - case (WRITE_MODE_B) - "WRITE_FIRST" : wr_mode_b <= 2'b00; - "READ_FIRST" : wr_mode_b <= 2'b01; - "NO_CHANGE" : wr_mode_b <= 2'b10; - default : begin - $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); - $finish; - end - endcase - end - - - // Port A - always @(posedge clka_int) begin - - if (ena_int == 1'b1) begin - - if (ssra_int == 1'b1) begin - {dopa_out, doa_out} <= #100 SRVAL_A; - end - else begin - if (wea_int == 1'b1) begin - if (wr_mode_a == 2'b00) begin - doa_out <= #100 dia_int; - dopa_out <= #100 dipa_int; - end - else if (wr_mode_a == 2'b01) begin - - doa_out <= #100 mem[addra_int]; - dopa_out <= #100 memp[addra_int]; - - end - end - else begin - - doa_out <= #100 mem[addra_int]; - dopa_out <= #100 memp[addra_int]; - - end - end - - // memory - if (wea_int == 1'b1) begin - mem[addra_int] <= dia_int; - memp[addra_int] <= dipa_int; - end - - end - end - - - // Port B - always @(posedge clkb_int) begin - - if (enb_int == 1'b1) begin - - if (ssrb_int == 1'b1) begin - {dopb_out, dob_out} <= #100 SRVAL_B; - end - else begin - if (web_int == 1'b1) begin - if (wr_mode_b == 2'b00) begin - dob_out <= #100 dib_int; - dopb_out <= #100 dipb_int; - end - else if (wr_mode_b == 2'b01) begin - dob_out <= #100 mem[addrb_int]; - dopb_out <= #100 memp[addrb_int]; - end - end - else begin - dob_out <= #100 mem[addrb_int]; - dopb_out <= #100 memp[addrb_int]; - end - end - - // memory - if (web_int == 1'b1) begin - mem[addrb_int] <= dib_int; - memp[addrb_int] <= dipb_int; - end - - end - end - - -endmodule - -`endif diff --git a/fpga/usrp2/models/SRL16E.v b/fpga/usrp2/models/SRL16E.v deleted file mode 100644 index e71a419ac..000000000 --- a/fpga/usrp2/models/SRL16E.v +++ /dev/null @@ -1,53 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRL16E.v,v 1.7 2005/03/14 22:32:58 yanx Exp $ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2004 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 8.1i (I.13) -// \ \ Description : Xilinx Functional Simulation Library Component -// / / 16-Bit Shift Register Look-Up-Table with Clock Enable -// /___/ /\ Filename : SRL16E.v -// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 -// \___\/\___\ -// -// Revision: -// 03/23/04 - Initial version. -// End Revision - -`timescale 1 ps / 1 ps - - -module SRL16E (Q, A0, A1, A2, A3, CE, CLK, D); - - parameter INIT = 16'h0000; - - output Q; - - input A0, A1, A2, A3, CE, CLK, D; - - reg [15:0] data; - - - assign Q = data[{A3, A2, A1, A0}]; - - initial - begin - assign data = INIT; - while (CLK === 1'b1 || CLK===1'bX) - #10; - deassign data; - end - - always @(posedge CLK) - begin - if (CE == 1'b1) begin - {data[15:0]} <= #100 {data[14:0], D}; - end - end - - -endmodule - diff --git a/fpga/usrp2/models/SRLC16E.v b/fpga/usrp2/models/SRLC16E.v deleted file mode 100644 index a68bbe9e9..000000000 --- a/fpga/usrp2/models/SRLC16E.v +++ /dev/null @@ -1,61 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRLC16E.v,v 1.6.158.1 2007/03/09 18:13:20 patrickp Exp $ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2004 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 8.1i (I.13) -// \ \ Description : Xilinx Functional Simulation Library Component -// / / 16-Bit Shift Register Look-Up-Table with Carry and Clock Enable -// /___/ /\ Filename : SRLC16E.v -// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 -// \___\/\___\ -// -// Revision: -// 03/23/04 - Initial version. -// End Revision - -`timescale 1 ps / 1 ps - - -module SRLC16E (Q, Q15, A0, A1, A2, A3, CE, CLK, D); - - parameter INIT = 16'h0000; - - output Q, Q15; - - input A0, A1, A2, A3, CE, CLK, D; - - reg [15:0] data; - wire [3:0] addr; - wire q_int; - - buf b_a3 (addr[3], A3); - buf b_a2 (addr[2], A2); - buf b_a1 (addr[1], A1); - buf b_a0 (addr[0], A0); - - buf b_q_int (q_int, data[addr]); - buf b_q (Q, q_int); - buf b_q15_int (q15_int, data[15]); - buf b_q15 (Q15, q15_int); - - initial - begin - assign data = INIT; - while (CLK === 1'b1 || CLK===1'bX) - #10; - deassign data; - end - - always @(posedge CLK) begin - if (CE == 1'b1) begin - {data[15:0]} <= #100 {data[14:0], D}; - end - end - - -endmodule - diff --git a/fpga/usrp2/models/adc_model.v b/fpga/usrp2/models/adc_model.v deleted file mode 100644 index 1d1f1c929..000000000 --- a/fpga/usrp2/models/adc_model.v +++ /dev/null @@ -1,65 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module adc_model - (input clk, input rst, - output [13:0] adc_a, - output adc_ovf_a, - input adc_on_a, - input adc_oe_a, - output [13:0] adc_b, - output adc_ovf_b, - input adc_on_b, - input adc_oe_b - ); - - math_real math ( ) ; - - reg [13:0] adc_a_int = 0; - reg [13:0] adc_b_int = 0; - - assign adc_a = adc_oe_a ? adc_a_int : 14'bz; - assign adc_ovf_a = adc_oe_a ? 1'b0 : 1'bz; - assign adc_b = adc_oe_b ? adc_b_int : 14'bz; - assign adc_ovf_b = adc_oe_b ? 1'b0 : 1'bz; - - real phase = 0; - real freq = 330000/100000000; - - real scale = 8190; // math.pow(2,13)-2; - always @(posedge clk) - if(rst) - begin - adc_a_int <= 0; - adc_b_int <= 0; - end - else - begin - if(adc_on_a) - //adc_a_int <= $rtoi(math.round(math.sin(phase*math.MATH_2_PI)*scale)) ; - adc_a_int <= adc_a_int + 3; - if(adc_on_b) - adc_b_int <= adc_b_int - 7; - //adc_b_int <= $rtoi(math.round(math.cos(phase*math.MATH_2_PI)*scale)) ; - if(phase > 1) - phase <= phase + freq - 1; - else - phase <= phase + freq; - end - -endmodule // adc_model diff --git a/fpga/usrp2/models/cpld_model.v b/fpga/usrp2/models/cpld_model.v deleted file mode 100644 index 900577852..000000000 --- a/fpga/usrp2/models/cpld_model.v +++ /dev/null @@ -1,113 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module cpld_model - (input aux_clk, input start, input mode, input done, - output dout, output reg sclk, output detached); - - reg [7:0] rom[0:65535]; - - reg [15:0] addr; - reg [7:0] data; - assign dout = data[7]; - - reg [2:0] state, bitcnt; - - localparam IDLE = 3'd0; - localparam READ = 3'd1; - localparam BIT1 = 3'd2; - localparam BIT2 = 3'd3; - localparam DONE = 3'd4; - localparam DETACHED = 3'd5; - localparam ERROR = 3'd7; - - integer i; - reg [1023:0] ROMFile; - - initial begin - for (i=0;i<65536;i=i+1) begin - rom[i] <= 32'h0; - end - if ( !$value$plusargs( "rom=%s", ROMFile ) ) - begin - $display( "Using default ROM file, 'flash.rom'" ); - ROMFile = "flash.rom"; - end - else - $display( "Using %s as ROM file.", ROMFile); - - #1 $readmemh( ROMFile,rom ); - end - - initial addr = 16'd0; - initial data = 8'd0; - initial state = IDLE; - initial bitcnt = 3'd0; - initial sclk = 1'b0; - - always @(posedge aux_clk) - case(state) - IDLE : - if(start) - if(~mode) - state <= READ; - else - state <= ERROR; - READ : - if(done) - state <= DONE; - else - begin - data <= rom[addr]; - addr <= addr + 1; - bitcnt <= 3'd0; - if(addr==16'hFFFF) - state <= ERROR; - else - state <= BIT1; - end // else: !if(start) - BIT1 : - begin - sclk <= 1'b1; - state <= BIT2; - end - BIT2 : - begin - sclk <= 1'b0; - data <= {data[6:0],1'b0}; - bitcnt <= bitcnt + 1; - if(bitcnt==7) - state <= READ; - else - state <=BIT1; - end - DONE : - begin - if(start) - state <= ERROR; - else - state <= DETACHED; - end - DETACHED : - if(start) - state <= ERROR; - endcase // case(state) - - assign detached = (state == DETACHED) || (state == IDLE); - -endmodule // cpld_model diff --git a/fpga/usrp2/models/gpmc_model_async.v b/fpga/usrp2/models/gpmc_model_async.v deleted file mode 100644 index 22b3cdf9f..000000000 --- a/fpga/usrp2/models/gpmc_model_async.v +++ /dev/null @@ -1,147 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -`timescale 1ps/1ps - -module gpmc_model_async - (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE, - output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, - output reg EM_NWE, output reg EM_NOE ); - - assign EM_CLK = 0; - reg [15:0] EM_D_int; - assign EM_D = EM_D_int; - - initial - begin - EM_A <= 10'bz; - EM_NBE <= 2'b11; - EM_NWE <= 1; - EM_NOE <= 1; - EM_NCS4 <= 1; - EM_NCS6 <= 1; - EM_D_int <= 16'bz; - EM_WAIT0 <= 0; // FIXME this is actually an input - end - - task GPMC_Write; - input ctrl; - input [10:0] addr; - input [15:0] data; - begin - #23000; - EM_A <= addr[10:1]; - EM_D_int <= data; - #20100; - if(ctrl) - EM_NCS6 <= 0; - else - EM_NCS4 <= 0; - #14000; - EM_NWE <= 0; - #77500; - EM_NCS4 <= 1; - EM_NCS6 <= 1; - //#1.5; - EM_NWE <= 1; - #60000; - EM_A <= 10'bz; - EM_D_int <= 16'bz; - end - endtask // GPMC_Write - - task GPMC_Read; - input ctrl; - input [10:0] addr; - begin - #13000; - EM_A <= addr[10:1]; - #3000; - if(ctrl) - EM_NCS6 <= 0; - else - EM_NCS4 <= 0; - #14000; - EM_NOE <= 0; - #77500; - EM_NCS4 <= 1; - EM_NCS6 <= 1; - //#1.5; - $display("Data Read from GPMC: %X",EM_D); - EM_NOE <= 1; - #254000; - EM_A <= 10'bz; - end - endtask // GPMC_Read - - initial - begin - #1000000; - GPMC_Write(1,36,16'hF00D); - #1000000; - GPMC_Read(1,36); - #1000000; - GPMC_Write(0,0,16'h1234); - GPMC_Write(0,0,16'h5678); - GPMC_Write(0,0,16'h9abc); - GPMC_Write(0,0,16'hF00D); - GPMC_Write(0,0,16'hDEAD); - GPMC_Write(0,0,16'hDEAD); - GPMC_Write(0,0,16'hDEAD); - GPMC_Write(0,0,16'hDEAD); - GPMC_Write(0,0,16'hDEAD); - GPMC_Write(0,0,16'hDEAD); - #1000000; - GPMC_Write(0,0,16'h1234); - GPMC_Write(0,0,16'h5678); - GPMC_Write(0,0,16'h9abc); - GPMC_Write(0,0,16'hF00D); - GPMC_Write(0,0,16'hDEAD); - GPMC_Write(0,0,16'hDEAD); - GPMC_Write(0,0,16'hDEAD); - GPMC_Write(0,0,16'hDEAD); - GPMC_Write(0,0,16'hDEAD); - GPMC_Write(0,0,16'h9876); - #1000000; - GPMC_Read(0,0); - GPMC_Read(0,0); - GPMC_Read(0,0); - GPMC_Read(0,0); - GPMC_Read(0,0); - GPMC_Read(0,0); - GPMC_Read(0,0); - GPMC_Read(0,0); - GPMC_Read(0,0); - GPMC_Read(0,0); - #1000000; - GPMC_Read(0,0); - GPMC_Read(0,0); - GPMC_Read(0,0); - GPMC_Read(0,0); - GPMC_Read(0,0); - GPMC_Read(0,0); - GPMC_Read(0,0); - GPMC_Read(0,0); - GPMC_Read(0,0); - GPMC_Read(0,0); - #1000000; - GPMC_Read(0,0); - #100000000; - $finish; - end - -endmodule // gpmc_model_async diff --git a/fpga/usrp2/models/gpmc_model_sync.v b/fpga/usrp2/models/gpmc_model_sync.v deleted file mode 100644 index 0f66961e7..000000000 --- a/fpga/usrp2/models/gpmc_model_sync.v +++ /dev/null @@ -1,114 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module gpmc_model_sync - (output reg EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE, - output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, - output reg EM_NWE, output reg EM_NOE ); - - reg [15:0] EM_D_int; - assign EM_D = EM_D_int; - - initial - begin - EM_CLK <= 0; - EM_A <= 10'bz; - EM_NBE <= 2'b11; - EM_NWE <= 1; - EM_NOE <= 1; - EM_NCS4 <= 1; - EM_NCS6 <= 1; - EM_D_int <= 16'bz; - EM_WAIT0 <= 0; // FIXME this is actually an input - end - - task GPMC_Write; - input ctrl; - input [10:0] addr; - input [15:0] data; - begin - EM_CLK <= 1; - #10; - EM_CLK <= 0; - EM_NWE <= 0; - if(ctrl) - EM_NCS6 <= 0; - else - EM_NCS4 <= 0; - EM_A <= addr[10:1]; - EM_D_int <= data; - #10; - EM_CLK <= 1; - #10; - EM_CLK <= 0; - EM_NWE <= 1; - EM_NCS4 <= 1; - EM_NCS6 <= 1; - EM_A <= 10'bz; - EM_D_int <= 16'bz; - #100; - end - endtask // GPMC_Write - - task GPMC_Read; - input ctrl; - input [10:0] addr; - begin - #1.3; - EM_A <= addr[10:1]; - #3; - if(ctrl) - EM_NCS6 <= 0; - else - EM_NCS4 <= 0; - #14; - EM_NOE <= 0; - #77.5; - EM_NCS4 <= 1; - EM_NCS6 <= 1; - //#1.5; - $display("Data Read from GPMC: %X",EM_D); - EM_NOE <= 1; - #254; - EM_A <= 10'bz; - end - endtask // GPMC_Read - - initial - begin - #1000; - GPMC_Write(1,36,16'hF00D); - #1000; - GPMC_Read(1,36); - #1000; - GPMC_Write(0,36,16'h1234); - GPMC_Write(0,38,16'h5678); - GPMC_Write(0,40,16'h9abc); - GPMC_Write(0,11'h2F4,16'hF00D); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - #100000; - $finish; - end - -endmodule // gpmc_model diff --git a/fpga/usrp2/models/idt71v65603s150.v b/fpga/usrp2/models/idt71v65603s150.v deleted file mode 100755 index 457dfa6dd..000000000 --- a/fpga/usrp2/models/idt71v65603s150.v +++ /dev/null @@ -1,301 +0,0 @@ -/******************************************************************************* - * - * File Name : idt71v65603s150.v - * Product : IDT71V65603 - * Function : 256K x 36 pipeline ZBT Static RAM - * Simulation Tool/Version : Verilog-XL 2.5 - * Date : 07/19/00 - * - * Copyright 1999 Integrated Device Technology, Inc. - * - * Revision Notes: 07/19/00 Rev00 - * - ******************************************************************************/ -/******************************************************************************* - * Module Name: idt71v65603s150 - * - * Notes : This model is believed to be functionally - * accurate. Please direct any inquiries to - * IDT SRAM Applications at: sramhelp@idt.com - * - *******************************************************************************/ - - /*************************************************************** - * - * Integrated Device Technology, Inc. ("IDT") hereby grants the - * user of this Verilog/VCS model a non-exclusive, nontransferable - * license to use this Verilog/VCS model under the following terms. - * The user is granted this license only to use the Verilog/VCS - * model and is not granted rights to sell, copy (except as needed - * to run the IBIS model), rent, lease or sub-license the Verilog/VCS - * model in whole or in part, or in modified form to anyone. The User - * may modify the Verilog/VCS model to suit its specific applications, - * but rights to derivative works and such modifications shall belong - * to IDT. - * - * This Verilog/VCS model is provided on an "AS IS" basis and - * IDT makes absolutely no warranty with respect to the information - * contained herein. IDT DISCLAIMS AND CUSTOMER WAIVES ALL - * WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE - * ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE - * USER ACCORDINGLY, IN NO EVENT SHALL IDT BE LIABLE - * FOR ANY DIRECT OR INDIRECT DAMAGES, WHETHER IN CONTRACT OR - * TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL, - * CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF - * THE USE OR APPLICATION OF THE VERILOG/VCS model. Further, - * IDT reserves the right to make changes without notice to any - * product herein to improve reliability, function, or design. - * IDT does not convey any license under patent rights or - * any other intellectual property rights, including those of - * third parties. IDT is not obligated to provide maintenance - * or support for the licensed Verilog/VCS model. - * - ***************************************************************/ - - `timescale 1ns/100ps - -module idt71v65603s150 (A, - adv_ld_, // advance (high) / load (low) - bw1_, bw2_, bw3_, bw4_, // byte write enables (low) - ce1_, ce2, ce2_, // chip enables - cen_, // clock enable (low) - clk, // clock - IO, IOP, // data bus - lbo_, // linear burst order (low) - oe_, // output enable (low) - r_w_); // read (high) / write (low) - -initial -begin - $write("\n********************************************************\n"); - $write(" idt71v65603s150, 256K x 36 Pipelined burst ZBT SRAM \n"); - $write(" Rev: 00 July 2000 \n"); - $write(" copyright 1997,1998,1999,2000 by IDT, Inc. \n"); - $write("********************************************************\n\n"); -end - -input [17:0] A; -inout [31:0] IO; -inout [4:1] IOP; -input adv_ld_, bw1_, bw2_, bw3_, bw4_, ce1_, ce2, ce2_, - cen_, clk, lbo_, oe_, r_w_; - - -//internal registers for data, address, etc -reg [8:0] mem1[0:262143]; //memory array -reg [8:0] mem2[0:262143]; //memory array -reg [8:0] mem3[0:262143]; //memory array -reg [8:0] mem4[0:262143]; //memory array - -reg [35:0] dout; -reg [17:0] addr_a, - addr_b; -reg wren_a, wren_b; -reg cs_a, cs_b; -reg bw_a1, bw_b1; -reg bw_a2, bw_b2; -reg bw_a3, bw_b3; -reg bw_a4, bw_b4; -reg [1:0] brst_cnt; - -wire[35:0] data_out; -wire doe; -wire cs = (~ce1_ & ce2 & ~ce2_); -wire baddr0, baddr1; - - -parameter regdelay = 0.2; -parameter outdly = 0.2; - -specify -specparam -//Clock Parameters - tCYC = 6.7, //clock cycle time - tCH = 2.0, //clock high time - tCL = 2.0, //clock low time - -//Output Parameters - tCD = 3.8, //clk to data valid - tCLZ = 1.5, //clk to output Low-Z - tCHZ = 3.0, //clk to data Hi-Z - tOE = 3.8, //OE to output valid - tOLZ = 0.0, //OE to output Hi-Z - tOHZ = 3.8, //OE to output Hi-Z - -//Set up times - tSE = 1.5, //clock enable set-up - tSA = 1.5, //address set-up - tSD = 1.5, //data set-up - tSW = 1.5, //Read/Write set-up - tSADV = 1.5, //Advance/Load set-up - tSC = 1.5, //Chip enable set-up - tSB = 1.5, //Byte write enable set-up - -//Hold times - tHE = 0.5, //clock enable hold - tHA = 0.5, //address hold - tHD = 0.5, //data hold - tHW = 0.5, //Read/Write hold - tHADV = 0.5, //Advance/Load hold - tHC = 0.5, //Chip enable hold - tHB = 0.5; //Byte write enable hold - - - (oe_ *> IO) = (tOE,tOE,tOHZ,tOLZ,tOHZ,tOLZ); //(01,10,0z,z1,1z,z0) - (clk *> IO) = (tCD,tCD,tCHZ,tCLZ,tCHZ,tCLZ); //(01,10,0z,z1,1z,z0) - - (oe_ *> IOP) = (tOE,tOE,tOHZ,tOLZ,tOHZ,tOLZ); //(01,10,0z,z1,1z,z0) - (clk *> IOP) = (tCD,tCD,tCHZ,tCLZ,tCHZ,tCLZ); //(01,10,0z,z1,1z,z0) - -//timing checks - - $period(posedge clk, tCYC ); - $width (posedge clk, tCH ); - $width (negedge clk, tCL ); - - - $setuphold(posedge clk, A, tSA, tHA); - $setuphold(posedge clk, IO, tSD, tHD); - $setuphold(posedge clk, IOP, tSD, tHD); - $setuphold(posedge clk, adv_ld_, tSADV, tHADV); - $setuphold(posedge clk, bw1_, tSB, tHB); - $setuphold(posedge clk, bw2_, tSB, tHB); - $setuphold(posedge clk, bw3_, tSB, tHB); - $setuphold(posedge clk, bw4_, tSB, tHB); - $setuphold(posedge clk, ce1_, tSC, tHC); - $setuphold(posedge clk, ce2, tSC, tHC); - $setuphold(posedge clk, ce2_, tSC, tHC); - $setuphold(posedge clk, cen_, tSE, tHE); - $setuphold(posedge clk, r_w_, tSW, tHW); - -endspecify - -initial begin - cs_a = 0; - cs_b = 0; -end - - -///////////////////////////////////////////////////////////////////////// -//input registers -//-------------------- -always @(posedge clk) -begin - if ( ~cen_ & ~adv_ld_ ) cs_a <= #regdelay cs; - if ( ~cen_ ) cs_b <= #regdelay cs_a; - - if ( ~cen_ & ~adv_ld_ ) wren_a <= #regdelay (cs & ~r_w_); - if ( ~cen_ ) wren_b <= #regdelay wren_a; - - if ( ~cen_ ) bw_a1 <= #regdelay ~bw1_; - if ( ~cen_ ) bw_a2 <= #regdelay ~bw2_; - if ( ~cen_ ) bw_a3 <= #regdelay ~bw3_; - if ( ~cen_ ) bw_a4 <= #regdelay ~bw4_; - - if ( ~cen_ ) bw_b1 <= #regdelay bw_a1; - if ( ~cen_ ) bw_b2 <= #regdelay bw_a2; - if ( ~cen_ ) bw_b3 <= #regdelay bw_a3; - if ( ~cen_ ) bw_b4 <= #regdelay bw_a4; - - if ( ~cen_ & ~adv_ld_ ) addr_a[17:0] <= #regdelay A[17:0]; - if ( ~cen_ ) addr_b[17:0] <= #regdelay {addr_a[17:2], baddr1, baddr0}; -end - - -///////////////////////////////////////////////////////////////////////// -//burst counter -//-------------------- -always @(posedge clk) -begin - if ( lbo_ & ~cen_ & ~adv_ld_) brst_cnt <= #regdelay 0; - else if (~lbo_ & ~cen_ & ~adv_ld_) brst_cnt <= #regdelay A[1:0]; - else if ( ~cen_ & adv_ld_) brst_cnt <= #regdelay brst_cnt + 1; -end - - -///////////////////////////////////////////////////////////////////////// -//address logic -//-------------------- -assign baddr1 = lbo_ ? (brst_cnt[1] ^ addr_a[1]) : brst_cnt[1]; -assign baddr0 = lbo_ ? (brst_cnt[0] ^ addr_a[0]) : brst_cnt[0]; - - -///////////////////////////////////////////////////////////////////////// -//data output register -//-------------------- -always @(posedge clk) -begin - #regdelay; - #regdelay; - dout[8:0] = mem1[addr_b]; - dout[17:9] = mem2[addr_b]; - dout[26:18] = mem3[addr_b]; - dout[35:27] = mem4[addr_b]; -end - -assign data_out = dout; - - -///////////////////////////////////////////////////////////////////////// -//Output buffers: using a bufif1 has the same effect as... -// -// assign D = doe ? data_out : 36'hz; -// -//It was coded this way to support SPECIFY delays in the specparam section. -//-------------------- -bufif1 #outdly (IO[0],data_out[0],doe); -bufif1 #outdly (IO[1],data_out[1],doe); -bufif1 #outdly (IO[2],data_out[2],doe); -bufif1 #outdly (IO[3],data_out[3],doe); -bufif1 #outdly (IO[4],data_out[4],doe); -bufif1 #outdly (IO[5],data_out[5],doe); -bufif1 #outdly (IO[6],data_out[6],doe); -bufif1 #outdly (IO[7],data_out[7],doe); -bufif1 #outdly (IOP[1],data_out[8],doe); - -bufif1 #outdly (IO[8],data_out[9],doe); -bufif1 #outdly (IO[9],data_out[10],doe); -bufif1 #outdly (IO[10],data_out[11],doe); -bufif1 #outdly (IO[11],data_out[12],doe); -bufif1 #outdly (IO[12],data_out[13],doe); -bufif1 #outdly (IO[13],data_out[14],doe); -bufif1 #outdly (IO[14],data_out[15],doe); -bufif1 #outdly (IO[15],data_out[16],doe); -bufif1 #outdly (IOP[2],data_out[17],doe); - -bufif1 #outdly (IO[16],data_out[18],doe); -bufif1 #outdly (IO[17],data_out[19],doe); -bufif1 #outdly (IO[18],data_out[20],doe); -bufif1 #outdly (IO[19],data_out[21],doe); -bufif1 #outdly (IO[20],data_out[22],doe); -bufif1 #outdly (IO[21],data_out[23],doe); -bufif1 #outdly (IO[22],data_out[24],doe); -bufif1 #outdly (IO[23],data_out[25],doe); -bufif1 #outdly (IOP[3],data_out[26],doe); - -bufif1 #outdly (IO[24],data_out[27],doe); -bufif1 #outdly (IO[25],data_out[28],doe); -bufif1 #outdly (IO[26],data_out[29],doe); -bufif1 #outdly (IO[27],data_out[30],doe); -bufif1 #outdly (IO[28],data_out[31],doe); -bufif1 #outdly (IO[29],data_out[32],doe); -bufif1 #outdly (IO[30],data_out[33],doe); -bufif1 #outdly (IO[31],data_out[34],doe); -bufif1 #outdly (IOP[4],data_out[35],doe); - -assign doe = cs_b & ~wren_b & ~oe_ ; - - -///////////////////////////////////////////////////////////////////////// -// write to ram -//------------- -always @(posedge clk) -begin - if (wren_b & bw_b1 & ~cen_) mem1[addr_b] = {IOP[1], IO[7:0]}; - if (wren_b & bw_b2 & ~cen_) mem2[addr_b] = {IOP[2], IO[15:8]}; - if (wren_b & bw_b3 & ~cen_) mem3[addr_b] = {IOP[3], IO[23:16]}; - if (wren_b & bw_b4 & ~cen_) mem4[addr_b] = {IOP[4], IO[31:24]}; -end - -endmodule diff --git a/fpga/usrp2/models/math_real.v b/fpga/usrp2/models/math_real.v deleted file mode 100644 index d88f72669..000000000 --- a/fpga/usrp2/models/math_real.v +++ /dev/null @@ -1,512 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -/* - * This is a general recreation of the VHDL ieee.math_real package. - */ - -module math_real ; - // Constants for use below and for general reference - // TODO: Bring it out to 12 (or more???) places beyond the decimal? - localparam MATH_E = 2.7182818284; - localparam MATH_1_OVER_E = 0.3678794411; - localparam MATH_PI = 3.1415926536; - localparam MATH_2_PI = 6.2831853071; - localparam MATH_1_OVER_PI = 0.3183098861; - localparam MATH_PI_OVER_2 = 1.5707963267; - localparam MATH_PI_OVER_3 = 1.0471975511; - localparam MATH_PI_OVER_4 = 0.7853981633; - localparam MATH_3_PI_OVER_2 = 4.7123889803; - localparam MATH_LOG_OF_2 = 0.6931471805; - localparam MATH_LOG_OF_10 = 2.3025850929; - localparam MATH_LOG2_OF_E = 1.4426950408; - localparam MATH_LOG10_OF_E = 0.4342944819; - localparam MATH_SQRT_2 = 1.4142135623; - localparam MATH_1_OVER_SQRT_2= 0.7071067811; - localparam MATH_SQRT_PI = 1.7724538509; - localparam MATH_DEG_TO_RAD = 0.0174532925; - localparam MATH_RAD_TO_DEG = 57.2957795130; - - // The number of iterations to do for the Taylor series approximations - localparam EXPLOG_ITERATIONS = 19; - localparam COS_ITERATIONS = 8; - - /* Conversion Routines */ - - // Return the sign of a particular number. - function real sign ; - input real x ; - begin - sign = x < 0.0 ? 1.0 : 0.0 ; - end - endfunction - - // Return the trunc function of a number - function real trunc ; - input real x ; - begin - trunc = x - mod(x,1.0) ; - end - endfunction - - // Return the ceiling function of a number. - function real ceil ; - input real x ; - real retval ; - begin - retval = mod(x,1.0) ; - if( retval != 0.0 && x > 0.0 ) retval = x+1.0 ; - else retval = x ; - ceil = trunc(retval) ; - end - endfunction - - // Return the floor function of a number - function real floor ; - input real x ; - real retval ; - begin - retval = mod(x,1.0) ; - if( retval != 0.0 && x < 0.0 ) retval = x - 1.0 ; - else retval = x ; - floor = trunc(retval) ; - end - endfunction - - // Return the round function of a number - function real round ; - input real x ; - real retval ; - begin - retval = x > 0.0 ? x + 0.5 : x - 0.5 ; - round = trunc(retval) ; - end - endfunction - - // Return the fractional remainder of (x mod m) - function real mod ; - input real x ; - input real m ; - real retval ; - begin - retval = x ; - if( retval > m ) begin - while( retval > m ) begin - retval = retval - m ; - end - end - else begin - while( retval < -m ) begin - retval = retval + m ; - end - end - mod = retval ; - end - endfunction - - // Return the max between two real numbers - function real realmax ; - input real x ; - input real y ; - begin - realmax = x > y ? x : y ; - end - endfunction - - // Return the min between two real numbers - function real realmin ; - input real x ; - input real y ; - begin - realmin = x > y ? y : x ; - end - endfunction - - /* Random Numbers */ - - // Generate Gaussian distributed variables - function real gaussian ; - input real mean ; - input real var ; - real u1, u2, v1, v2, s ; - begin - s = 1.0 ; - while( s >= 1.0 ) begin - // Two random numbers between 0 and 1 - u1 = $random/4294967296.0 + 0.5 ; - u2 = $random/4294967296.0 + 0.5 ; - // Adjust to be between -1,1 - v1 = 2*u1-1.0 ; - v2 = 2*u2-1.0 ; - // Polar mag squared - s = (v1*v1 + v2*v2) ; - end - gaussian = mean + sqrt((-2.0*log(s))/s) * v1 * sqrt(var) ; - // gaussian2 = mean + sqrt(-2*log(s)/s)*v2 * sqrt(var) ; - end - endfunction - - /* Roots and Log Functions */ - - // Return the square root of a number - function real sqrt ; - input real x ; - real retval ; - begin - sqrt = (x == 0.0) ? 0.0 : powr(x,0.5) ; - end - endfunction - - // Return the cube root of a number - function real cbrt ; - input real x ; - real retval ; - begin - cbrt = (x == 0.0) ? 0.0 : powr(x,1.0/3.0) ; - end - endfunction - - // Return the absolute value of a real value - function real abs ; - input real x ; - begin - abs = (x > 0.0) ? x : -x ; - end - endfunction - - // Return a real value raised to an integer power - function real pow ; - input real b ; - input integer x ; - integer absx ; - real retval ; - begin - retval = 1.0 ; - absx = abs(x) ; - repeat(absx) begin - retval = b*retval ; - end - pow = x < 0 ? (1.0/retval) : retval ; - end - endfunction - - // Return a real value raised to a real power - function real powr ; - input real b ; - input real x ; - begin - powr = exp(x*log(b)) ; - end - endfunction - - // Return the evaluation of e^x where e is the natural logarithm base - // NOTE: This is the Taylor series expansion of e^x - function real exp ; - input real x ; - real retval ; - integer i ; - real nm1_fact ; - real powm1 ; - begin - nm1_fact = 1.0 ; - powm1 = 1.0 ; - retval = 1.0 ; - for( i = 1 ; i < EXPLOG_ITERATIONS ; i = i + 1 ) begin - powm1 = x*powm1 ; - nm1_fact = nm1_fact * i ; - retval = retval + powm1/nm1_fact ; - end - exp = retval ; - end - endfunction - - // Return the evaluation log(x) - function real log ; - input real x ; - integer i ; - real whole ; - real xm1oxp1 ; - real retval ; - real newx ; - begin - retval = 0.0 ; - whole = 0.0 ; - newx = x ; - while( newx > MATH_E ) begin - whole = whole + 1.0 ; - newx = newx / MATH_E ; - end - xm1oxp1 = (newx-1.0)/(newx+1.0) ; - for( i = 0 ; i < EXPLOG_ITERATIONS ; i = i + 1 ) begin - retval = retval + pow(xm1oxp1,2*i+1)/(2.0*i+1.0) ; - end - log = whole+2.0*retval ; - end - endfunction - - // Return the evaluation ln(x) (same as log(x)) - function real ln ; - input real x ; - begin - ln = log(x) ; - end - endfunction - - // Return the evaluation log_2(x) - function real log2 ; - input real x ; - begin - log2 = log(x)/MATH_LOG_OF_2 ; - end - endfunction - - function real log10 ; - input real x ; - begin - log10 = log(x)/MATH_LOG_OF_10 ; - end - endfunction - - function real log_base ; - input real x ; - input real b ; - begin - log_base = log(x)/log(b) ; - end - endfunction - - /* Trigonometric Functions */ - - // Internal function to reduce a value to be between [-pi:pi] - function real reduce ; - input real x ; - real retval ; - begin - retval = x ; - while( abs(retval) > MATH_PI ) begin - retval = retval > MATH_PI ? - (retval - MATH_2_PI) : - (retval + MATH_2_PI) ; - end - reduce = retval ; - end - endfunction - - // Return the cos of a number in radians - function real cos ; - input real x ; - integer i ; - integer sign ; - real newx ; - real retval ; - real xsqnm1 ; - real twonm1fact ; - begin - newx = reduce(x) ; - xsqnm1 = 1.0 ; - twonm1fact = 1.0 ; - retval = 1.0 ; - for( i = 1 ; i < COS_ITERATIONS ; i = i + 1 ) begin - sign = -2*(i % 2)+1 ; - xsqnm1 = xsqnm1*newx*newx ; - twonm1fact = twonm1fact * (2.0*i) * (2.0*i-1.0) ; - retval = retval + sign*(xsqnm1/twonm1fact) ; - end - cos = retval ; - end - endfunction - - // Return the sin of a number in radians - function real sin ; - input real x ; - begin - sin = cos(x - MATH_PI_OVER_2) ; - end - endfunction - - // Return the tan of a number in radians - function real tan ; - input real x ; - begin - tan = sin(x) / cos(x) ; - end - endfunction - - // Return the arcsin in radians of a number - function real arcsin ; - input real x ; - begin - arcsin = 2.0*arctan(x/(1.0+sqrt(1.0-x*x))) ; - end - endfunction - - // Return the arccos in radians of a number - function real arccos ; - input real x ; - begin - arccos = MATH_PI_OVER_2-arcsin(x) ; - end - endfunction - - // Return the arctan in radians of a number - // TODO: Make sure this REALLY does work as it is supposed to! - function real arctan ; - input real x ; - real retval ; - real y ; - real newx ; - real twoiotwoip1 ; - integer i ; - integer mult ; - begin - retval = 1.0 ; - twoiotwoip1 = 1.0 ; - mult = 1 ; - newx = abs(x) ; - while( newx > 1.0 ) begin - mult = mult*2 ; - newx = newx/(1.0+sqrt(1.0+newx*newx)) ; - end - y = 1.0 ; - for( i = 1 ; i < 2*COS_ITERATIONS ; i = i + 1 ) begin - y = y*((newx*newx)/(1+newx*newx)) ; - twoiotwoip1 = twoiotwoip1 * (2.0*i)/(2.0*i+1.0) ; - retval = retval + twoiotwoip1*y ; - end - retval = retval * (newx/(1+newx*newx)) ; - retval = retval * mult ; - - arctan = (x > 0.0) ? retval : -retval ; - end - endfunction - - // Return the arctan in radians of a ratio x/y - // TODO: Test to make sure this works as it is supposed to! - function real arctan_xy ; - input real x ; - input real y ; - real retval ; - begin - retval = 0.0 ; - if( x < 0.0 ) retval = MATH_PI - arctan(-abs(y)/x) ; - else if( x > 0.0 ) retval = arctan(abs(y)/x) ; - else if( x == 0.0 ) retval = MATH_PI_OVER_2 ; - arctan_xy = (y < 0.0) ? -retval : retval ; - end - endfunction - - /* Hyperbolic Functions */ - - // Return the sinh of a number - function real sinh ; - input real x ; - begin - sinh = (exp(x) - exp(-x))/2.0 ; - end - endfunction - - // Return the cosh of a number - function real cosh ; - input real x ; - begin - cosh = (exp(x) + exp(-x))/2.0 ; - end - endfunction - - // Return the tanh of a number - function real tanh ; - input real x ; - real e2x ; - begin - e2x = exp(2.0*x) ; - tanh = (e2x+1.0)/(e2x-1.0) ; - end - endfunction - - // Return the arcsinh of a number - function real arcsinh ; - input real x ; - begin - arcsinh = log(x+sqrt(x*x+1.0)) ; - end - endfunction - - // Return the arccosh of a number - function real arccosh ; - input real x ; - begin - arccosh = ln(x+sqrt(x*x-1.0)) ; - end - endfunction - - // Return the arctanh of a number - function real arctanh ; - input real x ; - begin - arctanh = 0.5*ln((1.0+x)/(1.0-x)) ; - end - endfunction - /* - initial begin - $display( "cos(MATH_PI_OVER_3): %f", cos(MATH_PI_OVER_3) ) ; - $display( "sin(MATH_PI_OVER_3): %f", sin(MATH_PI_OVER_3) ) ; - $display( "sign(-10): %f", sign(-10) ) ; - $display( "realmax(MATH_PI,MATH_E): %f", realmax(MATH_PI,MATH_E) ) ; - $display( "realmin(MATH_PI,MATH_E): %f", realmin(MATH_PI,MATH_E) ) ; - $display( "mod(MATH_PI,MATH_E): %f", mod(MATH_PI,MATH_E) ) ; - $display( "ceil(-MATH_PI): %f", ceil(-MATH_PI) ) ; - $display( "ceil(4.0): %f", ceil(4.0) ) ; - $display( "ceil(3.99999999999999): %f", ceil(3.99999999999999) ) ; - $display( "pow(MATH_PI,2): %f", pow(MATH_PI,2) ) ; - $display( "gaussian(1.0,1.0): %f", gaussian(1.0,1.0) ) ; - $display( "round(MATH_PI): %f", round(MATH_PI) ) ; - $display( "trunc(-MATH_PI): %f", trunc(-MATH_PI) ) ; - $display( "ceil(-MATH_PI): %f", ceil(-MATH_PI) ) ; - $display( "floor(MATH_PI): %f", floor(MATH_PI) ) ; - $display( "round(e): %f", round(MATH_E)) ; - $display( "ceil(-e): %f", ceil(-MATH_E)) ; - $display( "exp(MATH_PI): %f", exp(MATH_PI) ) ; - $display( "log2(MATH_PI): %f", log2(MATH_PI) ) ; - $display( "log_base(pow(2,32),2): %f", log_base(pow(2,32),2) ) ; - $display( "ln(0.1): %f", log(0.1) ) ; - $display( "cbrt(7): %f", cbrt(7) ) ; - $display( "cos(MATH_2_PI): %f", cos(20*MATH_2_PI) ) ; - $display( "sin(-MATH_2_PI): %f", sin(-50*MATH_2_PI) ) ; - $display( "sinh(MATH_E): %f", sinh(MATH_E) ) ; - $display( "cosh(MATH_2_PI): %f", cosh(MATH_2_PI) ) ; - $display( "arctan_xy(-4,3): %f", arctan_xy(-4,3) ) ; - $display( "arctan(MATH_PI): %f", arctan(MATH_PI) ) ; - $display( "arctan(-MATH_E/2): %f", arctan(-MATH_E/2) ) ; - $display( "arctan(MATH_PI_OVER_2): %f", arctan(MATH_PI_OVER_2) ) ; - $display( "arctan(1/7) = %f", arctan(1.0/7.0) ) ; - $display( "arctan(3/79) = %f", arctan(3.0/79.0) ) ; - $display( "pi/4 ?= %f", 5*arctan(1.0/7.0)+2*arctan(3.0/79.0) ) ; - $display( "arcsin(1.0): %f", arcsin(1.0) ) ; - $display( "cos(pi/2): %f", cos(MATH_PI_OVER_2)) ; - $display( "arccos(cos(pi/2)): %f", arccos(cos(MATH_PI_OVER_2)) ) ; - $display( "cos(0): %f", cos(0) ) ; - $display( "cos(MATH_PI_OVER_4): %f", cos(MATH_PI_OVER_4) ) ; - $display( "cos(MATH_PI_OVER_2): %f", cos(MATH_PI_OVER_2) ) ; - $display( "cos(3*MATH_PI_OVER_4): %f", cos(3*MATH_PI_OVER_4) ) ; - $display( "cos(MATH_PI): %f", cos(MATH_PI) ) ; - $display( "cos(5*MATH_PI_OVER_4): %f", cos(5*MATH_PI_OVER_4) ) ; - $display( "cos(6*MATH_PI_OVER_4): %f", cos(6*MATH_PI_OVER_4) ) ; - $display( "cos(7*MATH_PI_OVER_4): %f", cos(7*MATH_PI_OVER_4) ) ; - $display( "cos(8*MATH_PI_OVER_4): %f", cos(8*MATH_PI_OVER_4) ) ; - end*/ - -endmodule diff --git a/fpga/usrp2/models/miim_model.v b/fpga/usrp2/models/miim_model.v deleted file mode 100644 index 8eb8e571d..000000000 --- a/fpga/usrp2/models/miim_model.v +++ /dev/null @@ -1,31 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// Skeleton PHY interface simulator - -module miim_model(input mdc_i, - inout mdio, - input phy_resetn_i, - input phy_clk_i, - output phy_intn_o, - output [2:0] speed_o); - - assign phy_intn_o = 1; // No interrupts - assign speed_o = 3'b100; // 1G mode - -endmodule // miim_model diff --git a/fpga/usrp2/models/phy_sim.v b/fpga/usrp2/models/phy_sim.v deleted file mode 100644 index b3de19b04..000000000 --- a/fpga/usrp2/models/phy_sim.v +++ /dev/null @@ -1,113 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Phy_sim.v //// -//// //// -//// This file is part of the Ethernet IP core project //// -//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// -//// //// -//// Author(s): //// -//// - Jon Gao (gaojon@yahoo.com) //// -//// //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: Phy_sim.v,v $ -// Revision 1.3 2006/11/17 17:53:07 maverickist -// no message -// -// Revision 1.2 2006/01/19 14:07:50 maverickist -// verification is complete. -// -// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator -// no message -// - -`timescale 1ns/100ps - -module phy_sim( - input Gtx_clk, // Used only in GMII mode - output Rx_clk, - output Tx_clk, // Used only in MII mode - input Tx_er, - input Tx_en, - input [7:0] Txd, - output Rx_er, - output Rx_dv, - output [7:0] Rxd, - output Crs, - output Col, - input [2:0] Speed, - input Done -); - -////////////////////////////////////////////////////////////////////// -// this file used to simulate Phy. -// generate clk and loop the Tx data to Rx data -// full duplex mode can be verified on loop mode. -////////////////////////////////////////////////////////////////////// -////////////////////////////////////////////////////////////////////// -// internal signals -////////////////////////////////////////////////////////////////////// -reg Clk_25m; // Used for 100 Mbps mode -reg Clk_2_5m; // Used for 10 Mbps mode - -//wire Rx_clk; -//wire Tx_clk; // Used only in MII mode - - initial - begin - #10; - while ( !Done ) - begin - #20 Clk_25m = 0; - #20 Clk_25m = 1; - end - end - - initial - begin - #10; - while ( !Done ) - begin - #200 Clk_2_5m = 0; - #200 Clk_2_5m = 1; - end - end - - assign Rx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0; - assign Tx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0; - - assign Rx_dv = Tx_en; - assign Rxd = Txd; - assign Rx_er = Tx_er; - assign Crs = Tx_en; - assign Col = 0; - -endmodule diff --git a/fpga/usrp2/models/serdes_model.v b/fpga/usrp2/models/serdes_model.v deleted file mode 100644 index 5e1602163..000000000 --- a/fpga/usrp2/models/serdes_model.v +++ /dev/null @@ -1,51 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module serdes_model - (input ser_tx_clk, - input ser_tkmsb, - input ser_tklsb, - input [15:0] ser_t, - - output ser_rx_clk, - output ser_rkmsb, - output ser_rklsb, - output [15:0] ser_r, - - input even, - input error); - - wire [15:0] ser_r_odd; - wire ser_rklsb_odd, ser_rkmsb_odd; - - reg [7:0] hold_dat; - reg hold_k; - - always @(posedge ser_tx_clk) hold_k <= ser_tklsb; - always @(posedge ser_tx_clk) hold_dat <= ser_t[15:8]; - assign ser_rklsb_odd = hold_k; - assign ser_rkmsb_odd = ser_tklsb; - assign ser_r_odd = {ser_t[7:0], hold_dat}; - - // Set outputs - assign ser_rx_clk = ser_tx_clk; - assign ser_rkmsb = even ? ser_tkmsb : ser_rkmsb_odd; - assign ser_rklsb = even ? ser_tklsb : ser_rklsb_odd; - assign ser_r = error ^ (even ? ser_t : ser_r_odd); - -endmodule // serdes_model diff --git a/fpga/usrp2/models/uart_rx.v b/fpga/usrp2/models/uart_rx.v deleted file mode 100644 index 738ffb45b..000000000 --- a/fpga/usrp2/models/uart_rx.v +++ /dev/null @@ -1,65 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -// Simple printout of characters from the UART -// Only does 8N1, requires the baud clock - -module uart_rx (input baudclk, input rxd); - reg [8:0] sr = 9'b0; - reg [3:0] baud_ctr = 4'b0; - - /* - wire byteclk = baud_ctr[3]; - reg rxd_d1 = 0; - always @(posedge baudclk) - rxd_d1 <= rxd; - - always @(posedge baudclk) - if(rxd_d1 != rxd) - baud_ctr <= 0; - else - baud_ctr <= baud_ctr + 1; -*/ - - wire byteclk = baudclk; - - always @(posedge byteclk) - sr <= { rxd, sr[8:1] }; - - reg [3:0] state = 0; - always @(posedge byteclk) - case(state) - 0 : - if(~sr[8] & sr[7]) // found start bit - state <= 1; - 1, 2, 3, 4, 5, 6, 7, 8 : - state <= state + 1; - 9 : - begin - state <= 0; - $write("%c",sr[7:0]); - if(~sr[8]) - $display("Error, no stop bit\n"); - end - default : - state <= 0; - endcase // case(state) - -endmodule // uart_rx - diff --git a/fpga/usrp2/models/xlnx_glbl.v b/fpga/usrp2/models/xlnx_glbl.v deleted file mode 100644 index 62e29fef4..000000000 --- a/fpga/usrp2/models/xlnx_glbl.v +++ /dev/null @@ -1,46 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module xlnx_glbl -( - GSR, - GTS -); - - //-------------------------------------------------------------------------- - // Parameters - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - // IO declarations - //-------------------------------------------------------------------------- - - output GSR; - output GTS; - - //-------------------------------------------------------------------------- - // Local declarations - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - // Internal declarations - //-------------------------------------------------------------------------- - - assign GSR = 0; - assign GTS = 0; - -endmodule diff --git a/fpga/usrp2/opencores/8b10b/.gitignore b/fpga/usrp2/opencores/8b10b/.gitignore deleted file mode 100644 index 548539d61..000000000 --- a/fpga/usrp2/opencores/8b10b/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/dump.vcd -/a.out diff --git a/fpga/usrp2/opencores/8b10b/8b10b_a.mem b/fpga/usrp2/opencores/8b10b/8b10b_a.mem deleted file mode 100644 index 1761d74f6..000000000 --- a/fpga/usrp2/opencores/8b10b/8b10b_a.mem +++ /dev/null @@ -1,268 +0,0 @@ -000000000100111010001100010110 -000000001011101010010001010110 -000000010101101010001001010110 -000000011110001101111000101001 -000000100110101010000101010110 -000000101101001101110100101001 -000000110011001101101100101001 -000000111111000101100011101001 -000001000111001010000011010110 -000001001100101101110010101001 -000001010010101101101010101001 -000001011110100101111010001001 -000001100001101101100110101001 -000001101101100101110110001001 -000001110011100101101110001001 -000001111010111010010100010110 -000010000011011010010010010110 -000010001100011101110001101001 -000010010010011101101001101001 -000010011110010101111001001001 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--git a/fpga/usrp2/opencores/8b10b/README b/fpga/usrp2/opencores/8b10b/README deleted file mode 100644 index 7bce294ac..000000000 --- a/fpga/usrp2/opencores/8b10b/README +++ /dev/null @@ -1,4 +0,0 @@ -These files are not actually from OpenCores. They are from -Chuck Benz. See http://asics.chuckbenz.com - - diff --git a/fpga/usrp2/opencores/8b10b/decode_8b10b.v b/fpga/usrp2/opencores/8b10b/decode_8b10b.v deleted file mode 100644 index 0b2a8ac59..000000000 --- a/fpga/usrp2/opencores/8b10b/decode_8b10b.v +++ /dev/null @@ -1,165 +0,0 @@ -// Chuck Benz, Hollis, NH Copyright (c)2002 -// -// The information and description contained herein is the -// property of Chuck Benz. -// -// Permission is granted for any reuse of this information -// and description as long as this copyright notice is -// preserved. Modifications may be made as long as this -// notice is preserved. - -// per Widmer and Franaszek - -module decode_8b10b (datain, dispin, dataout, dispout, code_err, disp_err) ; - input [9:0] datain ; - input dispin ; - output [8:0] dataout ; - output dispout ; - output code_err ; - output disp_err ; - - wire ai = datain[0] ; - wire bi = datain[1] ; - wire ci = datain[2] ; - wire di = datain[3] ; - wire ei = datain[4] ; - wire ii = datain[5] ; - wire fi = datain[6] ; - wire gi = datain[7] ; - wire hi = datain[8] ; - wire ji = datain[9] ; - - wire aeqb = (ai & bi) | (!ai & !bi) ; - wire ceqd = (ci & di) | (!ci & !di) ; - wire p22 = (ai & bi & !ci & !di) | - (ci & di & !ai & !bi) | - ( !aeqb & !ceqd) ; - wire p13 = ( !aeqb & !ci & !di) | - ( !ceqd & !ai & !bi) ; - wire p31 = ( !aeqb & ci & di) | - ( !ceqd & ai & bi) ; - - wire p40 = ai & bi & ci & di ; - wire p04 = !ai & !bi & !ci & !di ; - - wire disp6a = p31 | (p22 & dispin) ; // pos disp if p22 and was pos, or p31. - wire disp6a2 = p31 & dispin ; // disp is ++ after 4 bits - wire disp6a0 = p13 & ! dispin ; // -- disp after 4 bits - - wire disp6b = (((ei & ii & ! disp6a0) | (disp6a & (ei | ii)) | disp6a2 | - (ei & ii & di)) & (ei | ii | di)) ; - - // The 5B/6B decoding special cases where ABCDE != abcde - - wire p22bceeqi = p22 & bi & ci & (ei == ii) ; - wire p22bncneeqi = p22 & !bi & !ci & (ei == ii) ; - wire p13in = p13 & !ii ; - wire p31i = p31 & ii ; - wire p13dei = p13 & di & ei & ii ; - wire p22aceeqi = p22 & ai & ci & (ei == ii) ; - wire p22ancneeqi = p22 & !ai & !ci & (ei == ii) ; - wire p13en = p13 & !ei ; - wire anbnenin = !ai & !bi & !ei & !ii ; - wire abei = ai & bi & ei & ii ; - wire cdei = ci & di & ei & ii ; - wire cndnenin = !ci & !di & !ei & !ii ; - - // non-zero disparity cases: - wire p22enin = p22 & !ei & !ii ; - wire p22ei = p22 & ei & ii ; - //wire p13in = p12 & !ii ; - //wire p31i = p31 & ii ; - wire p31dnenin = p31 & !di & !ei & !ii ; - //wire p13dei = p13 & di & ei & ii ; - wire p31e = p31 & ei ; - - wire compa = p22bncneeqi | p31i | p13dei | p22ancneeqi | - p13en | abei | cndnenin ; - wire compb = p22bceeqi | p31i | p13dei | p22aceeqi | - p13en | abei | cndnenin ; - wire compc = p22bceeqi | p31i | p13dei | p22ancneeqi | - p13en | anbnenin | cndnenin ; - wire compd = p22bncneeqi | p31i | p13dei | p22aceeqi | - p13en | abei | cndnenin ; - wire compe = p22bncneeqi | p13in | p13dei | p22ancneeqi | - p13en | anbnenin | cndnenin ; - - wire ao = ai ^ compa ; - wire bo = bi ^ compb ; - wire co = ci ^ compc ; - wire do = di ^ compd ; - wire eo = ei ^ compe ; - - wire feqg = (fi & gi) | (!fi & !gi) ; - wire heqj = (hi & ji) | (!hi & !ji) ; - wire fghj22 = (fi & gi & !hi & !ji) | - (!fi & !gi & hi & ji) | - ( !feqg & !heqj) ; - wire fghjp13 = ( !feqg & !hi & !ji) | - ( !heqj & !fi & !gi) ; - wire fghjp31 = ( (!feqg) & hi & ji) | - ( !heqj & fi & gi) ; - - wire dispout = (fghjp31 | (disp6b & fghj22) | (hi & ji)) & (hi | ji) ; - - wire ko = ( (ci & di & ei & ii) | ( !ci & !di & !ei & !ii) | - (p13 & !ei & ii & gi & hi & ji) | - (p31 & ei & !ii & !gi & !hi & !ji)) ; - - wire alt7 = (fi & !gi & !hi & // 1000 cases, where disp6b is 1 - ((dispin & ci & di & !ei & !ii) | ko | - (dispin & !ci & di & !ei & !ii))) | - (!fi & gi & hi & // 0111 cases, where disp6b is 0 - (( !dispin & !ci & !di & ei & ii) | ko | - ( !dispin & ci & !di & ei & ii))) ; - - wire k28 = (ci & di & ei & ii) | ! (ci | di | ei | ii) ; - // k28 with positive disp into fghi - .1, .2, .5, and .6 special cases - wire k28p = ! (ci | di | ei | ii) ; - wire fo = (ji & !fi & (hi | !gi | k28p)) | - (fi & !ji & (!hi | gi | !k28p)) | - (k28p & gi & hi) | - (!k28p & !gi & !hi) ; - wire go = (ji & !fi & (hi | !gi | !k28p)) | - (fi & !ji & (!hi | gi |k28p)) | - (!k28p & gi & hi) | - (k28p & !gi & !hi) ; - wire ho = ((ji ^ hi) & ! ((!fi & gi & !hi & ji & !k28p) | (!fi & gi & hi & !ji & k28p) | - (fi & !gi & !hi & ji & !k28p) | (fi & !gi & hi & !ji & k28p))) | - (!fi & gi & hi & ji) | (fi & !gi & !hi & !ji) ; - - wire disp6p = (p31 & (ei | ii)) | (p22 & ei & ii) ; - wire disp6n = (p13 & ! (ei & ii)) | (p22 & !ei & !ii) ; - wire disp4p = fghjp31 ; - wire disp4n = fghjp13 ; - - assign code_err = p40 | p04 | (fi & gi & hi & ji) | (!fi & !gi & !hi & !ji) | - (p13 & !ei & !ii) | (p31 & ei & ii) | - (ei & ii & fi & gi & hi) | (!ei & !ii & !fi & !gi & !hi) | - (ei & !ii & gi & hi & ji) | (!ei & ii & !gi & !hi & !ji) | - (!p31 & ei & !ii & !gi & !hi & !ji) | - (!p13 & !ei & ii & gi & hi & ji) | - (((ei & ii & !gi & !hi & !ji) | - (!ei & !ii & gi & hi & ji)) & - ! ((ci & di & ei) | (!ci & !di & !ei))) | - (disp6p & disp4p) | (disp6n & disp4n) | - (ai & bi & ci & !ei & !ii & ((!fi & !gi) | fghjp13)) | - (!ai & !bi & !ci & ei & ii & ((fi & gi) | fghjp31)) | - (fi & gi & !hi & !ji & disp6p) | - (!fi & !gi & hi & ji & disp6n) | - (ci & di & ei & ii & !fi & !gi & !hi) | - (!ci & !di & !ei & !ii & fi & gi & hi) ; - - assign dataout = {ko, ho, go, fo, eo, do, co, bo, ao} ; - - // my disp err fires for any legal codes that violate disparity, may fire for illegal codes - assign disp_err = ((dispin & disp6p) | (disp6n & !dispin) | - (dispin & !disp6n & fi & gi) | - (dispin & ai & bi & ci) | - (dispin & !disp6n & disp4p) | - (!dispin & !disp6p & !fi & !gi) | - (!dispin & !ai & !bi & !ci) | - (!dispin & !disp6p & disp4n) | - (disp6p & disp4p) | (disp6n & disp4n)) ; - -endmodule diff --git a/fpga/usrp2/opencores/8b10b/encode_8b10b.v b/fpga/usrp2/opencores/8b10b/encode_8b10b.v deleted file mode 100644 index c1f09b9ce..000000000 --- a/fpga/usrp2/opencores/8b10b/encode_8b10b.v +++ /dev/null @@ -1,120 +0,0 @@ -// Chuck Benz, Hollis, NH Copyright (c)2002 -// -// The information and description contained herein is the -// property of Chuck Benz. -// -// Permission is granted for any reuse of this information -// and description as long as this copyright notice is -// preserved. Modifications may be made as long as this -// notice is preserved. - -// per Widmer and Franaszek - -module encode_8b10b (datain, dispin, dataout, dispout) ; - input [8:0] datain ; - input dispin ; // 0 = neg disp; 1 = pos disp - output [9:0] dataout ; - output dispout ; - - - wire ai = datain[0] ; - wire bi = datain[1] ; - wire ci = datain[2] ; - wire di = datain[3] ; - wire ei = datain[4] ; - wire fi = datain[5] ; - wire gi = datain[6] ; - wire hi = datain[7] ; - wire ki = datain[8] ; - - wire aeqb = (ai & bi) | (!ai & !bi) ; - wire ceqd = (ci & di) | (!ci & !di) ; - wire l22 = (ai & bi & !ci & !di) | - (ci & di & !ai & !bi) | - ( !aeqb & !ceqd) ; - wire l40 = ai & bi & ci & di ; - wire l04 = !ai & !bi & !ci & !di ; - wire l13 = ( !aeqb & !ci & !di) | - ( !ceqd & !ai & !bi) ; - wire l31 = ( !aeqb & ci & di) | - ( !ceqd & ai & bi) ; - - // The 5B/6B encoding - - wire ao = ai ; - wire bo = (bi & !l40) | l04 ; - wire co = l04 | ci | (ei & di & !ci & !bi & !ai) ; - wire do = di & ! (ai & bi & ci) ; - wire eo = (ei | l13) & ! (ei & di & !ci & !bi & !ai) ; - wire io = (l22 & !ei) | - (ei & !di & !ci & !(ai&bi)) | // D16, D17, D18 - (ei & l40) | - (ki & ei & di & ci & !bi & !ai) | // K.28 - (ei & !di & ci & !bi & !ai) ; - - // pds16 indicates cases where d-1 is assumed + to get our encoded value - wire pd1s6 = (ei & di & !ci & !bi & !ai) | (!ei & !l22 & !l31) ; - // nds16 indicates cases where d-1 is assumed - to get our encoded value - wire nd1s6 = ki | (ei & !l22 & !l13) | (!ei & !di & ci & bi & ai) ; - - // ndos6 is pds16 cases where d-1 is + yields - disp out - all of them - wire ndos6 = pd1s6 ; - // pdos6 is nds16 cases where d-1 is - yields + disp out - all but one - wire pdos6 = ki | (ei & !l22 & !l13) ; - - - // some Dx.7 and all Kx.7 cases result in run length of 5 case unless - // an alternate coding is used (referred to as Dx.A7, normal is Dx.P7) - // specifically, D11, D13, D14, D17, D18, D19. - wire alt7 = fi & gi & hi & (ki | - (dispin ? (!ei & di & l31) : (ei & !di & l13))) ; - - - wire fo = fi & ! alt7 ; - wire go = gi | (!fi & !gi & !hi) ; - wire ho = hi ; - wire jo = (!hi & (gi ^ fi)) | alt7 ; - - // nd1s4 is cases where d-1 is assumed - to get our encoded value - wire nd1s4 = fi & gi ; - // pd1s4 is cases where d-1 is assumed + to get our encoded value - wire pd1s4 = (!fi & !gi) | (ki & ((fi & !gi) | (!fi & gi))) ; - - // ndos4 is pd1s4 cases where d-1 is + yields - disp out - just some - wire ndos4 = (!fi & !gi) ; - // pdos4 is nd1s4 cases where d-1 is - yields + disp out - wire pdos4 = fi & gi & hi ; - - // only legal K codes are K28.0->.7, K23/27/29/30.7 - // K28.0->7 is ei=di=ci=1,bi=ai=0 - // K23 is 10111 - // K27 is 11011 - // K29 is 11101 - // K30 is 11110 - so K23/27/29/30 are ei & l31 - wire illegalk = ki & - (ai | bi | !ci | !di | !ei) & // not K28.0->7 - (!fi | !gi | !hi | !ei | !l31) ; // not K23/27/29/30.7 - - // now determine whether to do the complementing - // complement if prev disp is - and pd1s6 is set, or + and nd1s6 is set - wire compls6 = (pd1s6 & !dispin) | (nd1s6 & dispin) ; - - // disparity out of 5b6b is disp in with pdso6 and ndso6 - // pds16 indicates cases where d-1 is assumed + to get our encoded value - // ndos6 is cases where d-1 is + yields - disp out - // nds16 indicates cases where d-1 is assumed - to get our encoded value - // pdos6 is cases where d-1 is - yields + disp out - // disp toggles in all ndis16 cases, and all but that 1 nds16 case - - wire disp6 = dispin ^ (ndos6 | pdos6) ; - - wire compls4 = (pd1s4 & !disp6) | (nd1s4 & disp6) ; - assign dispout = disp6 ^ (ndos4 | pdos4) ; - - assign dataout = {(jo ^ compls4), (ho ^ compls4), - (go ^ compls4), (fo ^ compls4), - (io ^ compls6), (eo ^ compls6), - (do ^ compls6), (co ^ compls6), - (bo ^ compls6), (ao ^ compls6)} ; - -endmodule diff --git a/fpga/usrp2/opencores/8b10b/validate_8b10b.v b/fpga/usrp2/opencores/8b10b/validate_8b10b.v deleted file mode 100644 index 926b1081d..000000000 --- a/fpga/usrp2/opencores/8b10b/validate_8b10b.v +++ /dev/null @@ -1,168 +0,0 @@ -// Chuck Benz, Hollis, NH Copyright (c)2002 -// -// The information and description contained herein is the -// property of Chuck Benz. -// -// Permission is granted for any reuse of this information -// and description as long as this copyright notice is -// preserved. Modifications may be made as long as this -// notice is preserved. - -// 11-OCT-2002: updated with clearer messages, and checking decodeout - -`timescale 1ns / 1ns -module test_8b10b ; - reg [29:0] code8b10b [0:267] ; - reg [8:0] testin ; - reg dispin ; - reg [10:0] i ; - wire [9:0] testout ; - wire dispout, decodedisp, decodeerr, disperr ; - wire [8:0] decodeout ; - // My data file is 30 columns. Column 1 becomes [29], 2 becomes [28], etc.. - // code[0] is last Column (30) - // First column, [29] is K indication - // columns 2:9, [28:21], are data byte, aka 'm' and 'n' of Dm.n - // columns 10:19, [20:11] are 10b symbol if starting disparity was negative, 0 - // columns 20:29, [10:1] are 10b symbol if starting disparity was positive, 1 - // column 30, [0], is a 1 if symbol results in a disparity flip - // 0 for a balanced symbol (5 '1's, 5 '0's). - - wire [29:0] code = code8b10b[i] ; - wire [9:0] expect_0_disp = {code[11], code[12], code[13], code[14], code[15], - code[16], code[17], code[18], code[19], code[20]} ; - wire [9:0] expect_1_disp = {code[1], code[2], code[3], code[4], code[5], - code[6], code[7], code[8], code[9], code[10]} ; - - reg [1023:0] legal ; // mark every used 10b symbol as legal, leave rest marked as not - reg [2047:0] okdisp ; // now mark every used combination of symbol and starting disparity - reg [8:0] mapcode [1023:0] ; - reg [10:0] codedisp0, codedisp1 ; - reg [9:0] decodein ; - reg decdispin ; - integer errors ; - - encode_8b10b DUTE (testin, dispin, testout, dispout) ; - decode_8b10b DUTD (decodein, decdispin, decodeout, decodedisp, decodeerr, disperr) ; - - always @ (code) testin = code[29:21] ; - - initial begin - errors = 0 ; - $readmemb ("8b10b_a.mem", code8b10b) ; - //$vcdpluson ; - $dumpvars (0); - $display ("\n\nFirst, test by trying all 268 (256 Dx.y and 12 Kx.y)") ; - $display ("valid inputs, with both + and - starting disparity."); - $display ("We check that the encoder output and ending disparity is correct."); - $display ("We also check that the decoder matches."); - for (i = 0 ; i < 268 ; i = i + 1) begin - // testin = code[29:21] ; - dispin = 0 ; - #1 - decodein = testout ; - decdispin = dispin ; - #1 -// $display ("%b %b %b %b *%b*", dispin, testin, testout, {dispout, DUTD.disp6a, DUTD.disp6a2, DUTD.disp6a0, DUTD.disp6a2}, decodeout,, decodedisp,, DUTD.k28,, DUTD.disp6b) ; - if (testout != expect_0_disp) - $display ("bad code0 %b %b %b %b %b", dispin, testin, dispout, testout, expect_0_disp) ; - if (dispout != (dispin ^ code[0])) - $display ("bad disp0 %b %b %b %b %b", dispin, testin, dispout, testout, (dispin ^ code[0])) ; - if (0 != (9'b1_1111_1111 & (testin ^ decodeout))) - $display ("diff in abcdefghk decode, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; - if (decodedisp != dispout) - $display ("diff in decoder disp out, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; - if (decodeerr) $display ("decode error asserted improperly, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; - if ((testout != expect_0_disp) | decodeerr | - (dispout != (dispin ^ code[0])) | (decodedisp != dispout)) - errors = errors + 1 ; - - dispin = 1 ; - #1 - decodein = testout ; - decdispin = dispin ; - #1 -// $display ("%b %b %b %b *%b*", dispin, testin, testout, {dispout, DUTD.disp6a, DUTD.disp6a2, DUTD.disp6a0, DUTD.disp6a2, DUTD.fghjp31, DUTD.feqg, DUTD.heqj, DUTD.fghj22, DUTD.fi, DUTD.gi, DUTD.hi, DUTD.ji, DUTD.dispout}, decodeout,, decodedisp,, DUTD.k28,, DUTD.disp6b) ; - if (testout != expect_1_disp) - $display ("bad code1 %b %b %b %b %b", dispin, testin, dispout, testout, expect_1_disp) ; - if (dispout != (dispin ^ code[0])) - $display ("bad disp1 %b %b %b %b %b", dispin, testin, dispout, testout, (dispin ^ code[0])) ; - if (0 != (9'b1_1111_1111 & (testin ^ decodeout))) - $display ("diff in abcdefghk decode, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; - if (decodedisp != dispout) - $display ("diff in decoder disp out, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; - if (decodeerr) $display ("decode error asserted improperly, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; - if ((testout != expect_1_disp) | decodeerr | - (dispout != (dispin ^ code[0])) | (decodedisp != dispout)) - errors = errors + 1 ; - end - $display ("%d errors in that testing.\n", errors) ; - - // Now, having verified all legal codes, lets run some illegal codes - // at the decoder... how to figure illegal codes ? 2048 possible cases, - // lets mark the OK ones... - legal = 0 ; - okdisp = 0 ; - for (i = 0 ; i < 268 ; i = i + 1) begin - #1 -// $display ("i=%d: %b %b %d %d %x %x", i, expect_0_disp, expect_1_disp, expect_0_disp, expect_1_disp, expect_0_disp, expect_1_disp) ; - legal[expect_0_disp] = 1 ; - legal[expect_1_disp] = 1 ; - codedisp0 = expect_0_disp ; - codedisp1 = {1'b1, expect_1_disp} ; - okdisp[codedisp0] = 1 ; - okdisp[codedisp1] = 1 ; - mapcode[expect_0_disp] = code[29:21] ; - mapcode[expect_1_disp] = code[29:21] ; - end - - $display ("Now lets test all (legal and illegal) codes into the decoder."); - $display ("checking all possible decode inputs") ; - for (i = 0 ; i < 1024 ; i = i + 1) begin - decodein = i ; - decdispin = 0 ; - codedisp1 = 1024 | i ; - #1 - if (((legal[i] == 0) & (decodeerr != 1)) | - (legal[i] & (mapcode[i] != decodeout)) | - (legal[i] & (disperr != !okdisp[i]))) - $display ("10b:%b start disp:%b 8b:%b end disp:%b codevio:%b dispvio:%b known code:%b used disp:", - decodein, decdispin, decodeout, decodedisp, decodeerr, disperr, legal[i], okdisp[i]) ; - if ((legal[i] == 0) & (decodeerr != 1)) $display ("ERR: decoderr should be 1") ; - if (legal[i] & (mapcode[i] != decodeout)) $display ("ERR: decode output incorrect") ; - if (legal[i] & (disperr != 1) & !okdisp[i]) $display ("ERR: disp err should be asserted") ; - else if (legal[i] & (disperr != 0) & okdisp[i]) - $display ("ERR: disp err should not be asserted") ; - - if (((legal[i] == 0) & (decodeerr != 1)) | - (legal[i] & !disperr & !okdisp[i]) | - (legal[i] & (mapcode[i] != decodeout)) | - (legal[i] & disperr & okdisp[i])) - errors = errors + 1 ; - - decdispin = 1 ; - #1 - if (((legal[i] == 0) & (decodeerr != 1)) | - (legal[i] & (mapcode[i] != decodeout)) | - (legal[i] & (disperr != !okdisp[i|1024]))) - $display ("10b:%b start disp:%b 8b:%b end disp:%b codevio:%b dispvio:%b known code:%b used disp:", - decodein, decdispin, decodeout, decodedisp, decodeerr, disperr, legal[i], okdisp[i|1024]) ; - if ((legal[i] == 0) & (decodeerr != 1)) $display ("ERR: decoderr should be 1") ; - if (legal[i] & (mapcode[i] != decodeout)) $display ("ERR: decode output incorrect") ; - if (legal[i] & (disperr != 1) & !okdisp[i|1024]) $display ("ERR: disp err should be asserted") ; - else if (legal[i] & (disperr != 0) & okdisp[i|1024]) - $display ("ERR: disp err should not be asserted") ; - if (((legal[i] == 0) & (decodeerr != 1)) | - (legal[i] & !disperr & !okdisp[i|1024]) | - (legal[i] & (mapcode[i] != decodeout)) | - (legal[i] & disperr & okdisp[i|1024])) - errors = errors + 1 ; - end // for (i = 0 ; i < 1024 ; i = i + 1) - - $display ("\nDone testing decoder.\n") ; - $display ("Total error count: %d", errors); - if (errors == 0) $display ("Congratulations!\n"); - $finish ; - end // initial begin - -endmodule diff --git a/fpga/usrp2/opencores/Makefile.srcs b/fpga/usrp2/opencores/Makefile.srcs deleted file mode 100644 index 838b1b813..000000000 --- a/fpga/usrp2/opencores/Makefile.srcs +++ /dev/null @@ -1,36 +0,0 @@ -# -# Copyright 2010 Ettus Research LLC -# - -################################################## -# Open Cores Sources -################################################## -OPENCORES_SRCS = $(abspath $(addprefix $(BASE_DIR)/../opencores/, \ -8b10b/decode_8b10b.v \ -8b10b/encode_8b10b.v \ -aemb/rtl/verilog/aeMB_bpcu.v \ -aemb/rtl/verilog/aeMB_core_BE.v \ -aemb/rtl/verilog/aeMB_ctrl.v \ -aemb/rtl/verilog/aeMB_edk32.v \ -aemb/rtl/verilog/aeMB_ibuf.v \ -aemb/rtl/verilog/aeMB_regf.v \ -aemb/rtl/verilog/aeMB_xecu.v \ -i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -i2c/rtl/verilog/i2c_master_defines.v \ -i2c/rtl/verilog/i2c_master_top.v \ -i2c/rtl/verilog/timescale.v \ -spi/rtl/verilog/spi_clgen.v \ -spi/rtl/verilog/spi_defines.v \ -spi/rtl/verilog/spi_shift.v \ -spi/rtl/verilog/spi_top.v \ -spi/rtl/verilog/spi_top16.v \ -zpu/zpu_top_pkg.vhd \ -zpu/zpu_wb_top.vhd \ -zpu/wishbone/wishbone_pkg.vhd \ -zpu/wishbone/zpu_system.vhd \ -zpu/wishbone/zpu_wb_bridge.vhd \ -zpu/core/zpu_config.vhd \ -zpu/core/zpu_core.vhd \ -zpu/core/zpupkg.vhd \ -)) diff --git a/fpga/usrp2/opencores/README b/fpga/usrp2/opencores/README deleted file mode 100644 index d63b7cbdb..000000000 --- a/fpga/usrp2/opencores/README +++ /dev/null @@ -1,11 +0,0 @@ -All the subdirectories of this directory contain code from the OpenCores -project, checked out directly from the OpenCores CVS server. You can update -any directory to the latest OpenCores code by doing "cvs up" in that. -This is not recommended unless you know what you are doing. - - -Each directory contains its own copyright and licensing information. We -believe that we have the right to distribute all of these files in the form -in which we provide them. If this is not the case, please notify Matt Ettus, -matt@ettus.com. - diff --git a/fpga/usrp2/opencores/aemb/doc/aeMB_datasheet.pdf b/fpga/usrp2/opencores/aemb/doc/aeMB_datasheet.pdf deleted file mode 100644 index 5b26ac319..000000000 Binary files a/fpga/usrp2/opencores/aemb/doc/aeMB_datasheet.pdf and /dev/null differ diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/.gitignore b/fpga/usrp2/opencores/aemb/rtl/verilog/.gitignore deleted file mode 100644 index 6b09f5cc9..000000000 --- a/fpga/usrp2/opencores/aemb/rtl/verilog/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/aeMB2* diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v deleted file mode 100644 index 81587e25c..000000000 --- a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v +++ /dev/null @@ -1,185 +0,0 @@ -// $Id: aeMB_bpcu.v,v 1.4 2007/11/14 22:14:34 sybreon Exp $ -// -// AEMB BRANCH PROGRAMME COUNTER UNIT -// -// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -// -// This file is part of AEMB. -// -// AEMB is free software: you can redistribute it and/or modify it -// under the terms of the GNU Lesser General Public License as -// published by the Free Software Foundation, either version 3 of the -// License, or (at your option) any later version. -// -// AEMB is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -// Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with AEMB. If not, see . -// -// $Log: aeMB_bpcu.v,v $ -// Revision 1.4 2007/11/14 22:14:34 sybreon -// Changed interrupt handling system (reported by M. Ettus). -// -// Revision 1.3 2007/11/10 16:39:38 sybreon -// Upgraded license to LGPLv3. -// Significant performance optimisations. -// -// Revision 1.2 2007/11/02 19:20:58 sybreon -// Added better (beta) interrupt support. -// Changed MSR_IE to disabled at reset as per MB docs. -// -// Revision 1.1 2007/11/02 03:25:39 sybreon -// New EDK 3.2 compatible design with optional barrel-shifter and multiplier. -// Fixed various minor data hazard bugs. -// Code compatible with -O0/1/2/3/s generated code. -// - -module aeMB_bpcu (/*AUTOARG*/ - // Outputs - iwb_adr_o, rPC, rPCLNK, rBRA, rDLY, - // Inputs - rMXALT, rOPC, rRD, rRA, rRESULT, rDWBDI, rREGA, gclk, grst, gena - ); - parameter IW = 24; - - // INST WISHBONE - output [IW-1:2] iwb_adr_o; - - // INTERNAL - output [31:2] rPC, rPCLNK; - output rBRA; - output rDLY; - //output [1:0] rATOM; - //output [1:0] xATOM; - - input [1:0] rMXALT; - input [5:0] rOPC; - input [4:0] rRD, rRA; - input [31:0] rRESULT; // ALU - input [31:0] rDWBDI; // RAM - input [31:0] rREGA; - //input [1:0] rXCE; - - // SYSTEM - input gclk, grst, gena; - - // --- BRANCH CONTROL -------------------------------------------- - // Controls the branch and delay flags - - wire fRTD = (rOPC == 6'o55); - wire fBCC = (rOPC == 6'o47) | (rOPC == 6'o57); - wire fBRU = (rOPC == 6'o46) | (rOPC == 6'o56); - - wire [31:0] wREGA; - assign wREGA = (rMXALT == 2'o2) ? rDWBDI : - (rMXALT == 2'o1) ? rRESULT : - rREGA; - - wire wBEQ = (wREGA == 32'd0); - wire wBNE = ~wBEQ; - wire wBLT = wREGA[31]; - wire wBLE = wBLT | wBEQ; - wire wBGE = ~wBLT; - wire wBGT = ~wBLE; - - reg xXCC; - always @(/*AUTOSENSE*/rRD or wBEQ or wBGE or wBGT or wBLE or wBLT - or wBNE) - case (rRD[2:0]) - 3'o0: xXCC <= wBEQ; - 3'o1: xXCC <= wBNE; - 3'o2: xXCC <= wBLT; - 3'o3: xXCC <= wBLE; - 3'o4: xXCC <= wBGT; - 3'o5: xXCC <= wBGE; - default: xXCC <= 1'bX; - endcase // case (rRD[2:0]) - - reg rBRA, xBRA; - reg rDLY, xDLY; - wire fSKIP = rBRA & !rDLY; - - always @(/*AUTOSENSE*/fBCC or fBRU or fRTD or rBRA or rRA or rRD - or xXCC) - //if (rBRA | |rXCE) begin - if (rBRA) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - xBRA <= 1'h0; - xDLY <= 1'h0; - // End of automatics - end else begin - xDLY <= (fBRU & rRA[4]) | (fBCC & rRD[4]) | fRTD; - xBRA <= (fRTD | fBRU) ? 1'b1 : - (fBCC) ? xXCC : - 1'b0; - end - - // --- PC PIPELINE ------------------------------------------------ - // PC and related changes - - reg [31:2] rIPC, xIPC; - reg [31:2] rPC, xPC; - reg [31:2] rPCLNK, xPCLNK; - - assign iwb_adr_o = gena ? xIPC[IW-1:2] : rIPC[IW-1:2]; //IJB - - always @(/*AUTOSENSE*/rBRA or rIPC or rPC or rRESULT) begin - //xPCLNK <= (^rATOM) ? rPC : rPC; - xPCLNK <= rPC; - //xPC <= (^rATOM) ? rIPC : rRESULT[31:2]; - xPC <= rIPC; - //xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1); - /* - case (rXCE) - 2'o1: xIPC <= 30'h2; - 2'o2: xIPC <= 30'h4; - 2'o3: xIPC <= 30'h6; - default: xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1); - endcase // case (rXCE) - */ - xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1); - end - - // --- ATOMIC CONTROL --------------------------------------------- - // This is used to indicate 'safe' instruction borders. - - wire wIMM = (rOPC == 6'o54) & !fSKIP; - wire wRTD = (rOPC == 6'o55) & !fSKIP; - wire wBCC = xXCC & ((rOPC == 6'o47) | (rOPC == 6'o57)) & !fSKIP; - wire wBRU = ((rOPC == 6'o46) | (rOPC == 6'o56)) & !fSKIP; - - wire fATOM = ~(wIMM | wRTD | wBCC | wBRU | rBRA); - reg [1:0] rATOM, xATOM; - - always @(/*AUTOSENSE*/fATOM or rATOM) - xATOM <= {rATOM[0], (rATOM[0] ^ fATOM)}; - - - // --- SYNC PIPELINE ---------------------------------------------- - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rATOM <= 2'h0; - rBRA <= 1'h0; - rDLY <= 1'h0; -// rIPC <= 30'h0; - rIPC <= 30'h3fffffff; // DWORD aligned address - rPC <= 30'h0; - rPCLNK <= 30'h0; - // End of automatics - end else if (gena) begin - rIPC <= #1 xIPC; - rBRA <= #1 xBRA; - rPC <= #1 xPC; - rPCLNK <= #1 xPCLNK; - rDLY <= #1 xDLY; - rATOM <= #1 xATOM; - end - -endmodule // aeMB_bpcu diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core.v deleted file mode 100644 index 20ce9852e..000000000 --- a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core.v +++ /dev/null @@ -1,137 +0,0 @@ -// $Id: aeMB_core.v,v 1.9 2007/11/23 14:06:41 sybreon Exp $ -// -// AEMB 32'bit RISC MICROPROCESSOR CORE -// -// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -// -// This file is part of AEMB. -// -// AEMB is free software: you can redistribute it and/or modify it -// under the terms of the GNU Lesser General Public License as -// published by the Free Software Foundation, either version 3 of the -// License, or (at your option) any later version. -// -// AEMB is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -// Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with AEMB. If not, see . -// -// HISTORY -// $Log: aeMB_core.v,v $ -// Revision 1.9 2007/11/23 14:06:41 sybreon -// Old version deprecated. -// -// Revision 1.8 2007/10/22 19:12:59 sybreon -// Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. -// -// Revision 1.7 2007/05/30 18:44:30 sybreon -// Added interrupt support. -// -// Revision 1.6 2007/05/17 09:08:21 sybreon -// Removed asynchronous reset signal. -// -// Revision 1.5 2007/04/27 00:23:55 sybreon -// Added code documentation. -// Improved size & speed of rtl/verilog/aeMB_aslu.v -// -// Revision 1.4 2007/04/25 22:15:04 sybreon -// Added support for 8-bit and 16-bit data types. -// -// Revision 1.3 2007/04/11 04:30:43 sybreon -// Added pipeline stalling from incomplete bus cycles. -// Separated sync and async portions of code. -// -// Revision 1.2 2007/04/04 06:13:23 sybreon -// Removed unused signals -// -// Revision 1.1 2007/03/09 17:52:17 sybreon -// initial import -// - - -module aeMB_core (/*AUTOARG*/ - // Outputs - iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o, - fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o, - // Inputs - sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, - fsl_ack_i, dwb_dat_i, dwb_ack_i - ); - // Instruction WB address space - parameter ISIZ = 32; - // Data WB address space - parameter DSIZ = 32; - // Multiplier - parameter MUL = 1; - // Barrel Shifter - parameter BSF = 1; - - /*AUTOOUTPUT*/ - // Beginning of automatic outputs (from unused autoinst outputs) - output [DSIZ-1:2] dwb_adr_o; // From edk32 of aeMB_edk32.v - output [31:0] dwb_dat_o; // From edk32 of aeMB_edk32.v - output [3:0] dwb_sel_o; // From edk32 of aeMB_edk32.v - output dwb_stb_o; // From edk32 of aeMB_edk32.v - output dwb_wre_o; // From edk32 of aeMB_edk32.v - output [6:2] fsl_adr_o; // From edk32 of aeMB_edk32.v - output [31:0] fsl_dat_o; // From edk32 of aeMB_edk32.v - output fsl_stb_o; // From edk32 of aeMB_edk32.v - output [1:0] fsl_tag_o; // From edk32 of aeMB_edk32.v - output fsl_wre_o; // From edk32 of aeMB_edk32.v - output [ISIZ-1:2] iwb_adr_o; // From edk32 of aeMB_edk32.v - output iwb_stb_o; // From edk32 of aeMB_edk32.v - // End of automatics - /*AUTOINPUT*/ - // Beginning of automatic inputs (from unused autoinst inputs) - input dwb_ack_i; // To edk32 of aeMB_edk32.v - input [31:0] dwb_dat_i; // To edk32 of aeMB_edk32.v - input fsl_ack_i; // To edk32 of aeMB_edk32.v - input [31:0] fsl_dat_i; // To edk32 of aeMB_edk32.v - input iwb_ack_i; // To edk32 of aeMB_edk32.v - input [31:0] iwb_dat_i; // To edk32 of aeMB_edk32.v - input sys_clk_i; // To edk32 of aeMB_edk32.v - input sys_int_i; // To edk32 of aeMB_edk32.v - input sys_rst_i; // To edk32 of aeMB_edk32.v - // End of automatics - /*AUTOWIRE*/ - - // INSTANTIATIONS ///////////////////////////////////////////////////////////////// - - /* - aeMB_edk32 AUTO_TEMPLATE ( - .dwb_adr_o(dwb_adr_o[DSIZ-1:2]), - .iwb_adr_o(iwb_adr_o[ISIZ-1:2]), - ); - */ - - aeMB_edk32 #(ISIZ, DSIZ, MUL, BSF) - edk32 (/*AUTOINST*/ - // Outputs - .dwb_adr_o (dwb_adr_o[DSIZ-1:2]), // Templated - .dwb_dat_o (dwb_dat_o[31:0]), - .dwb_sel_o (dwb_sel_o[3:0]), - .dwb_stb_o (dwb_stb_o), - .dwb_wre_o (dwb_wre_o), - .fsl_adr_o (fsl_adr_o[6:2]), - .fsl_dat_o (fsl_dat_o[31:0]), - .fsl_stb_o (fsl_stb_o), - .fsl_tag_o (fsl_tag_o[1:0]), - .fsl_wre_o (fsl_wre_o), - .iwb_adr_o (iwb_adr_o[ISIZ-1:2]), // Templated - .iwb_stb_o (iwb_stb_o), - // Inputs - .dwb_ack_i (dwb_ack_i), - .dwb_dat_i (dwb_dat_i[31:0]), - .fsl_ack_i (fsl_ack_i), - .fsl_dat_i (fsl_dat_i[31:0]), - .iwb_ack_i (iwb_ack_i), - .iwb_dat_i (iwb_dat_i[31:0]), - .sys_int_i (sys_int_i), - .sys_clk_i (sys_clk_i), - .sys_rst_i (sys_rst_i)); - - -endmodule // aeMB_core diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v deleted file mode 100644 index 6c066d5d9..000000000 --- a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v +++ /dev/null @@ -1,71 +0,0 @@ - -// Wrapper for aeMB core: -// Drive wb_cyc_o (just tied to wb_stb_o for now) -// Make input reset active high (like the signal name makes it sound....) -// No longer needed -// Make it big-endian like the standard MicroBlaze - -module aeMB_core_BE - #(parameter ISIZ=32, parameter DSIZ=32, - parameter MUL=0, parameter BSF=0) - (input sys_clk_i, - input sys_rst_i, - // Instruction port - output [ISIZ-1:0] if_adr, - input [31:0] if_dat, - // Data port - output dwb_we_o, - output dwb_stb_o, - output [DSIZ-1:0] dwb_adr_o, - output [31:0] dwb_dat_o, - input [31:0] dwb_dat_i, - input dwb_ack_i, - output [3:0] dwb_sel_o, - output dwb_cyc_o, - - input sys_int_i, - input sys_exc_i); - - - wire [ISIZ-1:0] iwb_adr_o; - wire [31:0] iwb_dat_i; - wire iwb_ack_i; - wire iwb_stb_o; - - assign dwb_cyc_o = dwb_stb_o; - assign iwb_ack_i = 1'b1; - assign if_adr = iwb_adr_o[ISIZ-1:0]; - assign iwb_dat_i = if_dat; - - // Note some "wishbone" instruction fetch signals pruned on external interface - // but not propogated change deep into aeMB. - aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ),.MUL(MUL),.BSF(BSF)) - aeMB_edk32 (.sys_clk_i(sys_clk_i), - .sys_rst_i(sys_rst_i), - // Instruction Port - .iwb_stb_o(iwb_stb_o), - .iwb_adr_o(iwb_adr_o[ISIZ-1:2]), - .iwb_ack_i(iwb_ack_i), - .iwb_dat_i(iwb_dat_i), - // Data port - .dwb_wre_o(dwb_we_o), - .dwb_stb_o(dwb_stb_o), - .dwb_adr_o(dwb_adr_o[DSIZ-1:2]), - .dwb_ack_i(dwb_ack_i), - .dwb_sel_o(dwb_sel_o), - .dwb_dat_i(dwb_dat_i), - .dwb_dat_o(dwb_dat_o), - - .fsl_wre_o(), - .fsl_tag_o(), - .fsl_stb_o(), - .fsl_dat_o(), - .fsl_adr_o(), - .fsl_dat_i(32'b0), - .fsl_ack_i(1'b0), - .sys_int_i(sys_int_i) ); - - assign iwb_adr_o[1:0] = 2'b0; - assign dwb_adr_o[1:0] = 2'b0; - -endmodule // aeMB_core_BE diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v deleted file mode 100644 index 88d4e51ce..000000000 --- a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v +++ /dev/null @@ -1,336 +0,0 @@ -// $Id: aeMB_ctrl.v,v 1.10 2007/11/30 16:44:40 sybreon Exp $ -// -// AEMB CONTROL UNIT -// -// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -// -// This file is part of AEMB. -// -// AEMB is free software: you can redistribute it and/or modify it -// under the terms of the GNU Lesser General Public License as -// published by the Free Software Foundation, either version 3 of the -// License, or (at your option) any later version. -// -// AEMB is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -// Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with AEMB. If not, see . -// -// $Log: aeMB_ctrl.v,v $ -// Revision 1.10 2007/11/30 16:44:40 sybreon -// Minor code cleanup. -// -// Revision 1.9 2007/11/15 09:26:43 sybreon -// Fixed minor typo causing synthesis failure. -// -// Revision 1.8 2007/11/14 23:19:24 sybreon -// Fixed minor typo. -// -// Revision 1.7 2007/11/14 22:14:34 sybreon -// Changed interrupt handling system (reported by M. Ettus). -// -// Revision 1.6 2007/11/10 16:39:38 sybreon -// Upgraded license to LGPLv3. -// Significant performance optimisations. -// -// Revision 1.5 2007/11/09 20:51:52 sybreon -// Added GET/PUT support through a FSL bus. -// -// Revision 1.4 2007/11/08 17:48:14 sybreon -// Fixed data WISHBONE arbitration problem (reported by J Lee). -// -// Revision 1.3 2007/11/08 14:17:47 sybreon -// Parameterised optional components. -// -// Revision 1.2 2007/11/02 19:20:58 sybreon -// Added better (beta) interrupt support. -// Changed MSR_IE to disabled at reset as per MB docs. -// -// Revision 1.1 2007/11/02 03:25:40 sybreon -// New EDK 3.2 compatible design with optional barrel-shifter and multiplier. -// Fixed various minor data hazard bugs. -// Code compatible with -O0/1/2/3/s generated code. -// - -module aeMB_ctrl (/*AUTOARG*/ - // Outputs - rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, dwb_stb_o, dwb_wre_o, - fsl_stb_o, fsl_wre_o, - // Inputs - rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE, xIREG, - dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena - ); - // INTERNAL - //output [31:2] rPCLNK; - output [1:0] rMXDST; - output [1:0] rMXSRC, rMXTGT, rMXALT; - output [2:0] rMXALU; - output [4:0] rRW; - - input rDLY; - input [15:0] rIMM; - input [10:0] rALT; - input [5:0] rOPC; - input [4:0] rRD, rRA, rRB; - input [31:2] rPC; - input rBRA; - input rMSR_IE; - input [31:0] xIREG; - - // DATA WISHBONE - output dwb_stb_o; - output dwb_wre_o; - input dwb_ack_i; - - // INST WISHBONE - input iwb_ack_i; - - // FSL WISHBONE - output fsl_stb_o; - output fsl_wre_o; - input fsl_ack_i; - - // SYSTEM - input gclk, grst, gena; - - // --- DECODE INSTRUCTIONS - // TODO: Simplify - - wire [5:0] wOPC; - wire [4:0] wRD, wRA, wRB; - wire [10:0] wALT; - - assign {wOPC, wRD, wRA, wRB, wALT} = xIREG; // FIXME: Endian - - wire fSFT = (rOPC == 6'o44); - wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4); - - wire fMUL = (rOPC == 6'o20) | (rOPC == 6'o30); - wire fBSF = (rOPC == 6'o21) | (rOPC == 6'o31); - wire fDIV = (rOPC == 6'o22); - - wire fRTD = (rOPC == 6'o55); - wire fBCC = (rOPC == 6'o47) | (rOPC == 6'o57); - wire fBRU = (rOPC == 6'o46) | (rOPC == 6'o56); - wire fBRA = fBRU & rRA[3]; - - wire fIMM = (rOPC == 6'o54); - wire fMOV = (rOPC == 6'o45); - - wire fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6); - wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7); - wire fLDST = (&rOPC[5:4]); - - wire fPUT = (rOPC == 6'o33) & rRB[4]; - wire fGET = (rOPC == 6'o33) & !rRB[4]; - - - wire wSFT = (wOPC == 6'o44); - wire wLOG = ({wOPC[5:4],wOPC[2]} == 3'o4); - - wire wMUL = (wOPC == 6'o20) | (wOPC == 6'o30); - wire wBSF = (wOPC == 6'o21) | (wOPC == 6'o31); - wire wDIV = (wOPC == 6'o22); - - wire wRTD = (wOPC == 6'o55); - wire wBCC = (wOPC == 6'o47) | (wOPC == 6'o57); - wire wBRU = (wOPC == 6'o46) | (wOPC == 6'o56); - wire wBRA = wBRU & wRA[3]; - - wire wIMM = (wOPC == 6'o54); - wire wMOV = (wOPC == 6'o45); - - wire wLOD = ({wOPC[5:4],wOPC[2]} == 3'o6); - wire wSTR = ({wOPC[5:4],wOPC[2]} == 3'o7); - wire wLDST = (&wOPC[5:4]); - - wire wPUT = (wOPC == 6'o33) & wRB[4]; - wire wGET = (wOPC == 6'o33) & !wRB[4]; - - - // --- BRANCH SLOT REGISTERS --------------------------- - - reg [31:2] rPCLNK, xPCLNK; - reg [1:0] rMXDST, xMXDST; - reg [4:0] rRW, xRW; - - reg [1:0] rMXSRC, xMXSRC; - reg [1:0] rMXTGT, xMXTGT; - reg [1:0] rMXALT, xMXALT; - - - // --- OPERAND SELECTOR --------------------------------- - - wire wRDWE = |xRW; - wire wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE; - wire wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE; - wire wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE; - wire wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE; - - always @(/*AUTOSENSE*/rBRA or wAFWD_M or wAFWD_R or wBCC or wBFWD_M - or wBFWD_R or wBRU or wOPC) - //if (rBRA | |rXCE) begin - if (rBRA) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - xMXALT <= 2'h0; - xMXSRC <= 2'h0; - xMXTGT <= 2'h0; - // End of automatics - end else begin - xMXSRC <= (wBRU | wBCC) ? 2'o3 : // PC - (wAFWD_M) ? 2'o2 : // RAM - (wAFWD_R) ? 2'o1 : // FWD - 2'o0; // REG - xMXTGT <= (wOPC[3]) ? 2'o3 : // IMM - (wBFWD_M) ? 2'o2 : // RAM - (wBFWD_R) ? 2'o1 : // FWD - 2'o0; // REG - xMXALT <= (wAFWD_M) ? 2'o2 : // RAM - (wAFWD_R) ? 2'o1 : // FWD - 2'o0; // REG - end // else: !if(rBRA) - - // --- ALU CONTROL --------------------------------------- - - reg [2:0] rMXALU, xMXALU; - - always @(/*AUTOSENSE*/rBRA or wBRA or wBSF or wDIV or wLOG or wMOV - or wMUL or wSFT) - //if (rBRA | |rXCE) begin - if (rBRA) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - xMXALU <= 3'h0; - // End of automatics - end else begin - xMXALU <= (wBRA | wMOV) ? 3'o3 : - (wSFT) ? 3'o2 : - (wLOG) ? 3'o1 : - (wMUL) ? 3'o4 : - (wBSF) ? 3'o5 : - (wDIV) ? 3'o6 : - 3'o0; - end // else: !if(rBRA) - - // --- DELAY SLOT REGISTERS ------------------------------ - - wire fSKIP = (rBRA & !rDLY); - - always @(/*AUTOSENSE*/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP - or fSTR or rRD) - if (fSKIP) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - xMXDST <= 2'h0; - xRW <= 5'h0; - // End of automatics - end else begin - xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 : - (fLOD | fGET) ? 2'o2 : - (fBRU) ? 2'o1 : - 2'o0; - xRW <= rRD; - end // else: !if(fSKIP) - - - // --- DATA WISHBONE ---------------------------------- - - wire fDACK = !(dwb_stb_o ^ dwb_ack_i); - - reg rDWBSTB, xDWBSTB; - reg rDWBWRE, xDWBWRE; - - assign dwb_stb_o = rDWBSTB; - assign dwb_wre_o = rDWBWRE; - - - always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i) - //if (fSKIP | |rXCE) begin - if (fSKIP) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - xDWBSTB <= 1'h0; - xDWBWRE <= 1'h0; - // End of automatics - end else begin - xDWBSTB <= (fLOD | fSTR) & iwb_ack_i; - xDWBWRE <= fSTR & iwb_ack_i; - end - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rDWBSTB <= 1'h0; - rDWBWRE <= 1'h0; - // End of automatics - end else if (fDACK) begin - rDWBSTB <= #1 xDWBSTB; - rDWBWRE <= #1 xDWBWRE; - end - - - // --- FSL WISHBONE ----------------------------------- - - wire fFACK = !(fsl_stb_o ^ fsl_ack_i); - - reg rFSLSTB, xFSLSTB; - reg rFSLWRE, xFSLWRE; - - assign fsl_stb_o = rFSLSTB; - assign fsl_wre_o = rFSLWRE; - - always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i) - //if (fSKIP | |rXCE) begin - if (fSKIP) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - xFSLSTB <= 1'h0; - xFSLWRE <= 1'h0; - // End of automatics - end else begin - xFSLSTB <= (fPUT | fGET) & iwb_ack_i; - xFSLWRE <= fPUT & iwb_ack_i; - end - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rFSLSTB <= 1'h0; - rFSLWRE <= 1'h0; - // End of automatics - end else if (fFACK) begin - rFSLSTB <= #1 xFSLSTB; - rFSLWRE <= #1 xFSLWRE; - end - - // --- PIPELINE CONTROL DELAY ---------------------------- - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rMXALT <= 2'h0; - rMXALU <= 3'h0; - rMXDST <= 2'h0; - rMXSRC <= 2'h0; - rMXTGT <= 2'h0; - rRW <= 5'h0; - // End of automatics - end else if (gena) begin // if (grst) - //rPCLNK <= #1 xPCLNK; - rMXDST <= #1 xMXDST; - rRW <= #1 xRW; - rMXSRC <= #1 xMXSRC; - rMXTGT <= #1 xMXTGT; - rMXALT <= #1 xMXALT; - rMXALU <= #1 xMXALU; - end - - -endmodule // aeMB_ctrl diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v deleted file mode 100644 index 8bf4f7cac..000000000 --- a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v +++ /dev/null @@ -1,289 +0,0 @@ -/* $Id: aeMB_edk32.v,v 1.14 2008/01/19 16:01:22 sybreon Exp $ -** -** AEMB EDK 3.2 Compatible Core -** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -** -** This file is part of AEMB. -** -** AEMB is free software: you can redistribute it and/or modify it -** under the terms of the GNU Lesser General Public License as -** published by the Free Software Foundation, either version 3 of the -** License, or (at your option) any later version. -** -** AEMB is distributed in the hope that it will be useful, but WITHOUT -** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -** Public License for more details. -** -** You should have received a copy of the GNU Lesser General Public -** License along with AEMB. If not, see . -*/ - -module aeMB_edk32 (/*AUTOARG*/ - // Outputs - iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o, - fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o, - // Inputs - sys_int_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, fsl_ack_i, dwb_dat_i, - dwb_ack_i, sys_clk_i, sys_rst_i - ); - // Bus widths - parameter IW = 32; /// Instruction bus address width - parameter DW = 32; /// Data bus address width - - // Optional functions - parameter MUL = 0; // Multiplier - parameter BSF = 1; // Barrel Shifter - - /*AUTOOUTPUT*/ - // Beginning of automatic outputs (from unused autoinst outputs) - output [DW-1:2] dwb_adr_o; // From xecu of aeMB_xecu.v - output [31:0] dwb_dat_o; // From regf of aeMB_regf.v - output [3:0] dwb_sel_o; // From xecu of aeMB_xecu.v - output dwb_stb_o; // From ctrl of aeMB_ctrl.v - output dwb_wre_o; // From ctrl of aeMB_ctrl.v - output [6:2] fsl_adr_o; // From xecu of aeMB_xecu.v - output [31:0] fsl_dat_o; // From regf of aeMB_regf.v - output fsl_stb_o; // From ctrl of aeMB_ctrl.v - output [1:0] fsl_tag_o; // From xecu of aeMB_xecu.v - output fsl_wre_o; // From ctrl of aeMB_ctrl.v - output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v - output iwb_stb_o; // From ibuf of aeMB_ibuf.v - // End of automatics - /*AUTOINPUT*/ - // Beginning of automatic inputs (from unused autoinst inputs) - input dwb_ack_i; // To ctrl of aeMB_ctrl.v - input [31:0] dwb_dat_i; // To regf of aeMB_regf.v - input fsl_ack_i; // To ctrl of aeMB_ctrl.v - input [31:0] fsl_dat_i; // To regf of aeMB_regf.v - input iwb_ack_i; // To ibuf of aeMB_ibuf.v, ... - input [31:0] iwb_dat_i; // To ibuf of aeMB_ibuf.v - input sys_int_i; // To ibuf of aeMB_ibuf.v - // End of automatics - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [10:0] rALT; // From ibuf of aeMB_ibuf.v - wire rBRA; // From bpcu of aeMB_bpcu.v - wire rDLY; // From bpcu of aeMB_bpcu.v - wire [31:0] rDWBDI; // From regf of aeMB_regf.v - wire [3:0] rDWBSEL; // From xecu of aeMB_xecu.v - wire [15:0] rIMM; // From ibuf of aeMB_ibuf.v - wire rMSR_BIP; // From xecu of aeMB_xecu.v - wire rMSR_IE; // From xecu of aeMB_xecu.v - wire [1:0] rMXALT; // From ctrl of aeMB_ctrl.v - wire [2:0] rMXALU; // From ctrl of aeMB_ctrl.v - wire [1:0] rMXDST; // From ctrl of aeMB_ctrl.v - wire [1:0] rMXSRC; // From ctrl of aeMB_ctrl.v - wire [1:0] rMXTGT; // From ctrl of aeMB_ctrl.v - wire [5:0] rOPC; // From ibuf of aeMB_ibuf.v - wire [31:2] rPC; // From bpcu of aeMB_bpcu.v - wire [31:2] rPCLNK; // From bpcu of aeMB_bpcu.v - wire [4:0] rRA; // From ibuf of aeMB_ibuf.v - wire [4:0] rRB; // From ibuf of aeMB_ibuf.v - wire [4:0] rRD; // From ibuf of aeMB_ibuf.v - wire [31:0] rREGA; // From regf of aeMB_regf.v - wire [31:0] rREGB; // From regf of aeMB_regf.v - wire [31:0] rRESULT; // From xecu of aeMB_xecu.v - wire [4:0] rRW; // From ctrl of aeMB_ctrl.v - wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v - wire rSTALL; // From ibuf of aeMB_ibuf.v - wire [31:0] xIREG; // From ibuf of aeMB_ibuf.v - // End of automatics - - input sys_clk_i; - input sys_rst_i; - - wire grst = sys_rst_i; - wire gclk = sys_clk_i; - wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i) & !rSTALL; - wire oena = ((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i); - - // --- INSTANTIATIONS ------------------------------------- - - aeMB_ibuf - ibuf (/*AUTOINST*/ - // Outputs - .rIMM (rIMM[15:0]), - .rRA (rRA[4:0]), - .rRD (rRD[4:0]), - .rRB (rRB[4:0]), - .rALT (rALT[10:0]), - .rOPC (rOPC[5:0]), - .rSIMM (rSIMM[31:0]), - .xIREG (xIREG[31:0]), - .rSTALL (rSTALL), - .iwb_stb_o (iwb_stb_o), - // Inputs - .rBRA (rBRA), - .rMSR_IE (rMSR_IE), - .rMSR_BIP (rMSR_BIP), - .iwb_dat_i (iwb_dat_i[31:0]), - .iwb_ack_i (iwb_ack_i), - .sys_int_i (sys_int_i), - .gclk (gclk), - .grst (grst), - .gena (gena), - .oena (oena)); - - aeMB_ctrl - ctrl (/*AUTOINST*/ - // Outputs - .rMXDST (rMXDST[1:0]), - .rMXSRC (rMXSRC[1:0]), - .rMXTGT (rMXTGT[1:0]), - .rMXALT (rMXALT[1:0]), - .rMXALU (rMXALU[2:0]), - .rRW (rRW[4:0]), - .dwb_stb_o (dwb_stb_o), - .dwb_wre_o (dwb_wre_o), - .fsl_stb_o (fsl_stb_o), - .fsl_wre_o (fsl_wre_o), - // Inputs - .rDLY (rDLY), - .rIMM (rIMM[15:0]), - .rALT (rALT[10:0]), - .rOPC (rOPC[5:0]), - .rRD (rRD[4:0]), - .rRA (rRA[4:0]), - .rRB (rRB[4:0]), - .rPC (rPC[31:2]), - .rBRA (rBRA), - .rMSR_IE (rMSR_IE), - .xIREG (xIREG[31:0]), - .dwb_ack_i (dwb_ack_i), - .iwb_ack_i (iwb_ack_i), - .fsl_ack_i (fsl_ack_i), - .gclk (gclk), - .grst (grst), - .gena (gena)); - - aeMB_bpcu #(IW) - bpcu (/*AUTOINST*/ - // Outputs - .iwb_adr_o (iwb_adr_o[IW-1:2]), - .rPC (rPC[31:2]), - .rPCLNK (rPCLNK[31:2]), - .rBRA (rBRA), - .rDLY (rDLY), - // Inputs - .rMXALT (rMXALT[1:0]), - .rOPC (rOPC[5:0]), - .rRD (rRD[4:0]), - .rRA (rRA[4:0]), - .rRESULT (rRESULT[31:0]), - .rDWBDI (rDWBDI[31:0]), - .rREGA (rREGA[31:0]), - .gclk (gclk), - .grst (grst), - .gena (gena)); - - aeMB_regf - regf (/*AUTOINST*/ - // Outputs - .rREGA (rREGA[31:0]), - .rREGB (rREGB[31:0]), - .rDWBDI (rDWBDI[31:0]), - .dwb_dat_o (dwb_dat_o[31:0]), - .fsl_dat_o (fsl_dat_o[31:0]), - // Inputs - .rOPC (rOPC[5:0]), - .rRA (rRA[4:0]), - .rRB (rRB[4:0]), - .rRW (rRW[4:0]), - .rRD (rRD[4:0]), - .rMXDST (rMXDST[1:0]), - .rPCLNK (rPCLNK[31:2]), - .rRESULT (rRESULT[31:0]), - .rDWBSEL (rDWBSEL[3:0]), - .rBRA (rBRA), - .rDLY (rDLY), - .dwb_dat_i (dwb_dat_i[31:0]), - .fsl_dat_i (fsl_dat_i[31:0]), - .gclk (gclk), - .grst (grst), - .gena (gena)); - - aeMB_xecu #(DW, MUL, BSF) - xecu (/*AUTOINST*/ - // Outputs - .dwb_adr_o (dwb_adr_o[DW-1:2]), - .dwb_sel_o (dwb_sel_o[3:0]), - .fsl_adr_o (fsl_adr_o[6:2]), - .fsl_tag_o (fsl_tag_o[1:0]), - .rRESULT (rRESULT[31:0]), - .rDWBSEL (rDWBSEL[3:0]), - .rMSR_IE (rMSR_IE), - .rMSR_BIP (rMSR_BIP), - // Inputs - .rREGA (rREGA[31:0]), - .rREGB (rREGB[31:0]), - .rMXSRC (rMXSRC[1:0]), - .rMXTGT (rMXTGT[1:0]), - .rRA (rRA[4:0]), - .rRB (rRB[4:0]), - .rMXALU (rMXALU[2:0]), - .rBRA (rBRA), - .rDLY (rDLY), - .rALT (rALT[10:0]), - .rSTALL (rSTALL), - .rSIMM (rSIMM[31:0]), - .rIMM (rIMM[15:0]), - .rOPC (rOPC[5:0]), - .rRD (rRD[4:0]), - .rDWBDI (rDWBDI[31:0]), - .rPC (rPC[31:2]), - .gclk (gclk), - .grst (grst), - .gena (gena)); - - -endmodule // aeMB_edk32 - -/* - $Log: aeMB_edk32.v,v $ - Revision 1.14 2008/01/19 16:01:22 sybreon - Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus) - - Revision 1.13 2007/12/25 22:15:09 sybreon - Stalls pipeline on MUL/BSF instructions results in minor speed improvements. - - Revision 1.12 2007/12/23 20:40:44 sybreon - Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. - - Revision 1.11 2007/11/30 17:08:29 sybreon - Moved simulation kernel into code. - - Revision 1.10 2007/11/16 21:52:03 sybreon - Added fsl_tag_o to FSL bus (tag either address or data). - - Revision 1.9 2007/11/14 23:19:24 sybreon - Fixed minor typo. - - Revision 1.8 2007/11/14 22:14:34 sybreon - Changed interrupt handling system (reported by M. Ettus). - - Revision 1.7 2007/11/10 16:39:38 sybreon - Upgraded license to LGPLv3. - Significant performance optimisations. - - Revision 1.6 2007/11/09 20:51:52 sybreon - Added GET/PUT support through a FSL bus. - - Revision 1.5 2007/11/08 17:48:14 sybreon - Fixed data WISHBONE arbitration problem (reported by J Lee). - - Revision 1.4 2007/11/08 14:17:47 sybreon - Parameterised optional components. - - Revision 1.3 2007/11/03 08:34:55 sybreon - Minor code cleanup. - - Revision 1.2 2007/11/02 19:20:58 sybreon - Added better (beta) interrupt support. - Changed MSR_IE to disabled at reset as per MB docs. - - Revision 1.1 2007/11/02 03:25:40 sybreon - New EDK 3.2 compatible design with optional barrel-shifter and multiplier. - Fixed various minor data hazard bugs. - Code compatible with -O0/1/2/3/s generated code. -*/ \ No newline at end of file diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v deleted file mode 100644 index a4edf1d90..000000000 --- a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v +++ /dev/null @@ -1,192 +0,0 @@ -/* $Id: aeMB_ibuf.v,v 1.10 2008/01/21 01:02:26 sybreon Exp $ -** -** AEMB INSTRUCTION BUFFER -** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -** -** This file is part of AEMB. -** -** AEMB is free software: you can redistribute it and/or modify it -** under the terms of the GNU Lesser General Public License as -** published by the Free Software Foundation, either version 3 of the -** License, or (at your option) any later version. -** -** AEMB is distributed in the hope that it will be useful, but WITHOUT -** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -** Public License for more details. -** -** You should have received a copy of the GNU Lesser General Public -** License along with AEMB. If not, see . -*/ - -module aeMB_ibuf (/*AUTOARG*/ - // Outputs - rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, xIREG, rSTALL, iwb_stb_o, - // Inputs - rBRA, rMSR_IE, rMSR_BIP, iwb_dat_i, iwb_ack_i, sys_int_i, gclk, - grst, gena, oena - ); - // INTERNAL - output [15:0] rIMM; - output [4:0] rRA, rRD, rRB; - output [10:0] rALT; - output [5:0] rOPC; - output [31:0] rSIMM; - output [31:0] xIREG; - output rSTALL; - - input rBRA; - //input [1:0] rXCE; - input rMSR_IE; - input rMSR_BIP; - - // INST WISHBONE - output iwb_stb_o; - input [31:0] iwb_dat_i; - input iwb_ack_i; - - // SYSTEM - input sys_int_i; - - // SYSTEM - input gclk, grst, gena, oena; - - reg [15:0] rIMM; - reg [4:0] rRA, rRD; - reg [5:0] rOPC; - - // FIXME: Endian - wire [31:0] wIDAT = iwb_dat_i; - assign {rRB, rALT} = rIMM; - - // TODO: Assign to FIFO not full. - assign iwb_stb_o = 1'b1; - - reg [31:0] rSIMM, xSIMM; - reg rSTALL; - - wire [31:0] wXCEOP = 32'hBA2D0008; // Vector 0x08 - wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10 - wire [31:0] wBRKOP = 32'hBA0C0018; // Vector 0x18 - wire [31:0] wBRAOP = 32'h88000000; // NOP for branches - - wire [31:0] wIREG = {rOPC, rRD, rRA, rRB, rALT}; - reg [31:0] xIREG; - - - // --- INTERRUPT LATCH -------------------------------------- - // Debounce and latch onto the positive level. This is independent - // of the pipeline so that stalls do not affect it. - - reg rFINT; - reg [1:0] rDINT; - wire wSHOT = rDINT[0]; - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rDINT <= 2'h0; - rFINT <= 1'h0; - // End of automatics - end else begin - if (rMSR_IE) - rDINT <= #1 - {rDINT[0], sys_int_i}; - - rFINT <= #1 - //(wIREG == wINTOP) ? 1'b0 : - (rFINT | wSHOT) & rMSR_IE; - end - - wire fIMM = (rOPC == 6'o54); - wire fRTD = (rOPC == 6'o55); - wire fBRU = ((rOPC == 6'o46) | (rOPC == 6'o56)); - wire fBCC = ((rOPC == 6'o47) | (rOPC == 6'o57)); - - // --- DELAY SLOT ------------------------------------------- - - always @(/*AUTOSENSE*/fBCC or fBRU or fIMM or fRTD or rBRA or rFINT - or wBRAOP or wIDAT or wINTOP) begin - xIREG <= (rBRA) ? wBRAOP : - (!fIMM & rFINT & !fRTD & !fBRU & !fBCC) ? wINTOP : - wIDAT; - end - - always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or wIDAT or xIREG) begin - xSIMM <= (!fIMM | rBRA) ? { {(16){xIREG[15]}}, xIREG[15:0]} : - {rIMM, wIDAT[15:0]}; - end - - // --- PIPELINE -------------------------------------------- - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rIMM <= 16'h0; - rOPC <= 6'h0; - rRA <= 5'h0; - rRD <= 5'h0; - rSIMM <= 32'h0; - // End of automatics - end else if (gena) begin - {rOPC, rRD, rRA, rIMM} <= #1 xIREG; - rSIMM <= #1 xSIMM; - end - - // --- STALL FOR MUL/BSF ----------------------------------- - - wire [5:0] wOPC = xIREG[31:26]; - - wire fMUL = (wOPC == 6'o20) | (wOPC == 6'o30); - wire fBSF = (wOPC == 6'o21) | (wOPC == 6'o31); - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rSTALL <= 1'h0; - // End of automatics - end else begin - rSTALL <= #1 (gena & !rSTALL & (fMUL | fBSF)) | (oena & rSTALL); - end - -endmodule // aeMB_ibuf - -/* - $Log: aeMB_ibuf.v,v $ - Revision 1.10 2008/01/21 01:02:26 sybreon - Patch interrupt bug. - - Revision 1.9 2008/01/19 16:01:22 sybreon - Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus) - - Revision 1.8 2007/12/25 22:15:09 sybreon - Stalls pipeline on MUL/BSF instructions results in minor speed improvements. - - Revision 1.7 2007/11/22 15:11:15 sybreon - Change interrupt to positive level triggered interrupts. - - Revision 1.6 2007/11/14 23:39:51 sybreon - Fixed interrupt signal synchronisation. - - Revision 1.5 2007/11/14 22:14:34 sybreon - Changed interrupt handling system (reported by M. Ettus). - - Revision 1.4 2007/11/10 16:39:38 sybreon - Upgraded license to LGPLv3. - Significant performance optimisations. - - Revision 1.3 2007/11/03 08:34:55 sybreon - Minor code cleanup. - - Revision 1.2 2007/11/02 19:20:58 sybreon - Added better (beta) interrupt support. - Changed MSR_IE to disabled at reset as per MB docs. - - Revision 1.1 2007/11/02 03:25:40 sybreon - New EDK 3.2 compatible design with optional barrel-shifter and multiplier. - Fixed various minor data hazard bugs. - Code compatible with -O0/1/2/3/s generated code. -*/ diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v deleted file mode 100644 index 7fe108957..000000000 --- a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v +++ /dev/null @@ -1,244 +0,0 @@ -// $Id: aeMB_regf.v,v 1.3 2007/11/10 16:39:38 sybreon Exp $ -// -// AEMB REGISTER FILE -// -// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -// -// This file is part of AEMB. -// -// AEMB is free software: you can redistribute it and/or modify it -// under the terms of the GNU Lesser General Public License as -// published by the Free Software Foundation, either version 3 of the -// License, or (at your option) any later version. -// -// AEMB is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -// Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with AEMB. If not, see . -// -// $Log: aeMB_regf.v,v $ -// Revision 1.3 2007/11/10 16:39:38 sybreon -// Upgraded license to LGPLv3. -// Significant performance optimisations. -// -// Revision 1.2 2007/11/09 20:51:52 sybreon -// Added GET/PUT support through a FSL bus. -// -// Revision 1.1 2007/11/02 03:25:41 sybreon -// New EDK 3.2 compatible design with optional barrel-shifter and multiplier. -// Fixed various minor data hazard bugs. -// Code compatible with -O0/1/2/3/s generated code. -// - -module aeMB_regf (/*AUTOARG*/ - // Outputs - rREGA, rREGB, rDWBDI, dwb_dat_o, fsl_dat_o, - // Inputs - rOPC, rRA, rRB, rRW, rRD, rMXDST, rPCLNK, rRESULT, rDWBSEL, rBRA, - rDLY, dwb_dat_i, fsl_dat_i, gclk, grst, gena - ); - // INTERNAL - output [31:0] rREGA, rREGB; - output [31:0] rDWBDI; - input [5:0] rOPC; - input [4:0] rRA, rRB, rRW, rRD; - input [1:0] rMXDST; - input [31:2] rPCLNK; - input [31:0] rRESULT; - input [3:0] rDWBSEL; - input rBRA, rDLY; - - // DATA WISHBONE - output [31:0] dwb_dat_o; - input [31:0] dwb_dat_i; - - // FSL WISHBONE - output [31:0] fsl_dat_o; - input [31:0] fsl_dat_i; - - // SYSTEM - input gclk, grst, gena; - - // --- LOAD SIZER ---------------------------------------------- - // Moves the data bytes around depending on the size of the - // operation. - - wire [31:0] wDWBDI = dwb_dat_i; // FIXME: Endian - wire [31:0] wFSLDI = fsl_dat_i; // FIXME: Endian - - reg [31:0] rDWBDI; - reg [1:0] rSIZ; - - always @(/*AUTOSENSE*/rDWBSEL or wDWBDI or wFSLDI) begin - /* 51.2 - case (rSIZ) - // FSL - 2'o3: rDWBDI <= wFSLDI; - // 32'bit - 2'o2: rDWBDI <= wDWBDI; - // 16'bit - 2'o1: case (rRESULT[1]) - 1'b0: rDWBDI <= {16'd0, wDWBDI[31:16]}; - 1'b1: rDWBDI <= {16'd0, wDWBDI[15:0]}; - endcase // case (rRESULT[1]) - // 8'bit - 2'o0: case (rRESULT[1:0]) - 2'o0: rDWBDI <= {24'd0, wDWBDI[31:24]}; - 2'o1: rDWBDI <= {24'd0, wDWBDI[23:16]}; - 2'o2: rDWBDI <= {24'd0, wDWBDI[15:8]}; - 2'o3: rDWBDI <= {24'd0, wDWBDI[7:0]}; - endcase // case (rRESULT[1:0]) - endcase // case (rSIZ) - */ - - /* 50.6 - case ({rSIZ, rRESULT[1:0]}) - // FSL - 4'hC, 4'hD, 4'hE, 4'hF: rDWBDI <= wFSLDI; - // 32'bit - 4'h8: rDWBDI <= wDWBDI; - // 16'bit - 4'h4: rDWBDI <= {16'd0, wDWBDI[31:16]}; - 4'h6: rDWBDI <= {16'd0, wDWBDI[15:0]}; - // 8'bit - 4'h0: rDWBDI <= {24'd0, wDWBDI[31:24]}; - 4'h1: rDWBDI <= {24'd0, wDWBDI[23:16]}; - 4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]}; - 4'h3: rDWBDI <= {24'd0, wDWBDI[7:0]}; - default: rDWBDI <= 32'hX; - endcase // case (rSIZ) - */ - - // 52.0 - case (rDWBSEL) - // 8'bit - 4'h8: rDWBDI <= {24'd0, wDWBDI[31:24]}; - 4'h4: rDWBDI <= {24'd0, wDWBDI[23:16]}; - 4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]}; - 4'h1: rDWBDI <= {24'd0, wDWBDI[7:0]}; - // 16'bit - 4'hC: rDWBDI <= {16'd0, wDWBDI[31:16]}; - 4'h3: rDWBDI <= {16'd0, wDWBDI[15:0]}; - // 32'bit - 4'hF: rDWBDI <= wDWBDI; - // FSL - 4'h0: rDWBDI <= wFSLDI; - // Undefined - default: rDWBDI <= 32'hX; - endcase - - end - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rSIZ <= 2'h0; - // End of automatics - end else if (gena) begin - rSIZ <= rOPC[1:0]; - end - - // --- GENERAL PURPOSE REGISTERS (R0-R31) ----------------------- - // LUT RAM implementation is smaller and faster. R0 gets written - // during reset with 0x00 and doesn't change after. - - //synthesis attribute ram_style of mARAM is distributed - reg [31:0] mARAM[0:31]; - //synthesis attribute ram_style of mBRAM is distributed - reg [31:0] mBRAM[0:31]; - //synthesis attribute ram_style of mDRAM is distributed - reg [31:0] mDRAM[0:31]; - - wire [31:0] rREGW = mDRAM[rRW]; - wire [31:0] rREGD = mDRAM[rRD]; - assign rREGA = mARAM[rRA]; - assign rREGB = mBRAM[rRB]; - - wire fRDWE = |rRW; - - reg [31:0] xWDAT; - - always @(/*AUTOSENSE*/rDWBDI or rMXDST or rPCLNK or rREGW - or rRESULT) - case (rMXDST) - 2'o2: xWDAT <= rDWBDI; - 2'o1: xWDAT <= {rPCLNK, 2'o0}; - 2'o0: xWDAT <= rRESULT; - 2'o3: xWDAT <= rREGW; // No change - endcase // case (rMXDST) - - always @(posedge gclk) - if (grst | fRDWE) begin - mARAM[rRW] <= xWDAT; - mBRAM[rRW] <= xWDAT; - mDRAM[rRW] <= xWDAT; - end - - // --- STORE SIZER --------------------------------------------- - // Replicates the data bytes across depending on the size of the - // operation. - - reg [31:0] rDWBDO, xDWBDO; - - wire [31:0] xFSL; - wire fFFWD_M = (rRA == rRW) & (rMXDST == 2'o2) & fRDWE; - wire fFFWD_R = (rRA == rRW) & (rMXDST == 2'o0) & fRDWE; - - assign fsl_dat_o = rDWBDO; - assign xFSL = (fFFWD_M) ? rDWBDI : - (fFFWD_R) ? rRESULT : - rREGA; - - wire [31:0] xDST; - wire fDFWD_M = (rRW == rRD) & (rMXDST == 2'o2) & fRDWE; - wire fDFWD_R = (rRW == rRD) & (rMXDST == 2'o0) & fRDWE; - - assign dwb_dat_o = rDWBDO; - assign xDST = (fDFWD_M) ? rDWBDI : - (fDFWD_R) ? rRESULT : - rREGD; - - always @(/*AUTOSENSE*/rOPC or xDST or xFSL) - case (rOPC[1:0]) - // 8'bit - 2'h0: xDWBDO <= {(4){xDST[7:0]}}; - // 16'bit - 2'h1: xDWBDO <= {(2){xDST[15:0]}}; - // 32'bit - 2'h2: xDWBDO <= xDST; - // FSL - 2'h3: xDWBDO <= xFSL; - //default: xDWBDO <= 32'hX; - endcase // case (rOPC[1:0]) - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rDWBDO <= 32'h0; - // End of automatics - end else if (gena) begin - rDWBDO <= #1 xDWBDO; - end - - // --- SIMULATION ONLY ------------------------------------------ - // Randomise memory to simulate real-world memory - // synopsys translate_off - - integer i; - initial begin - for (i=0; i<32; i=i+1) begin - mARAM[i] <= $random; - mBRAM[i] <= $random; - mDRAM[i] <= $random; - end - end - - // synopsys translate_on - - -endmodule // aeMB_regf diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_sim.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_sim.v deleted file mode 100644 index 83248e4ba..000000000 --- a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_sim.v +++ /dev/null @@ -1,312 +0,0 @@ -/* $Id: aeMB_sim.v,v 1.2 2008/06/06 09:36:02 sybreon Exp $ -** -** AEMB EDK 3.2 Compatible Core -** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -** -** This file is part of AEMB. -** -** AEMB is free software: you can redistribute it and/or modify it -** under the terms of the GNU Lesser General Public License as -** published by the Free Software Foundation, either version 3 of the -** License, or (at your option) any later version. -** -** AEMB is distributed in the hope that it will be useful, but WITHOUT -** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -** Public License for more details. -** -** You should have received a copy of the GNU Lesser General Public -** License along with AEMB. If not, see . -*/ - -module aeMB_sim (/*AUTOARG*/ - // Outputs - iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o, - fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o, - // Inputs - sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, - fsl_ack_i, dwb_dat_i, dwb_ack_i - ); - // Bus widths - parameter IW = 32; /// Instruction bus address width - parameter DW = 32; /// Data bus address width - - // Optional functions - parameter MUL = 1; // Multiplier - parameter BSF = 1; // Barrel Shifter - - /*AUTOOUTPUT*/ - // Beginning of automatic outputs (from unused autoinst outputs) - output [DW-1:2] dwb_adr_o; // From cpu of aeMB_edk32.v - output [31:0] dwb_dat_o; // From cpu of aeMB_edk32.v - output [3:0] dwb_sel_o; // From cpu of aeMB_edk32.v - output dwb_stb_o; // From cpu of aeMB_edk32.v - output dwb_wre_o; // From cpu of aeMB_edk32.v - output [6:2] fsl_adr_o; // From cpu of aeMB_edk32.v - output [31:0] fsl_dat_o; // From cpu of aeMB_edk32.v - output fsl_stb_o; // From cpu of aeMB_edk32.v - output [1:0] fsl_tag_o; // From cpu of aeMB_edk32.v - output fsl_wre_o; // From cpu of aeMB_edk32.v - output [IW-1:2] iwb_adr_o; // From cpu of aeMB_edk32.v - output iwb_stb_o; // From cpu of aeMB_edk32.v - // End of automatics - /*AUTOINPUT*/ - // Beginning of automatic inputs (from unused autoinst inputs) - input dwb_ack_i; // To cpu of aeMB_edk32.v - input [31:0] dwb_dat_i; // To cpu of aeMB_edk32.v - input fsl_ack_i; // To cpu of aeMB_edk32.v - input [31:0] fsl_dat_i; // To cpu of aeMB_edk32.v - input iwb_ack_i; // To cpu of aeMB_edk32.v - input [31:0] iwb_dat_i; // To cpu of aeMB_edk32.v - input sys_clk_i; // To cpu of aeMB_edk32.v - input sys_int_i; // To cpu of aeMB_edk32.v - input sys_rst_i; // To cpu of aeMB_edk32.v - // End of automatics - /*AUTOWIRE*/ - - aeMB_edk32 - #(/*AUTOINSTPARAM*/ - // Parameters - .IW (IW), - .DW (DW), - .MUL (MUL), - .BSF (BSF)) - cpu - (/*AUTOINST*/ - // Outputs - .dwb_adr_o (dwb_adr_o[DW-1:2]), - .dwb_dat_o (dwb_dat_o[31:0]), - .dwb_sel_o (dwb_sel_o[3:0]), - .dwb_stb_o (dwb_stb_o), - .dwb_wre_o (dwb_wre_o), - .fsl_adr_o (fsl_adr_o[6:2]), - .fsl_dat_o (fsl_dat_o[31:0]), - .fsl_stb_o (fsl_stb_o), - .fsl_tag_o (fsl_tag_o[1:0]), - .fsl_wre_o (fsl_wre_o), - .iwb_adr_o (iwb_adr_o[IW-1:2]), - .iwb_stb_o (iwb_stb_o), - // Inputs - .dwb_ack_i (dwb_ack_i), - .dwb_dat_i (dwb_dat_i[31:0]), - .fsl_ack_i (fsl_ack_i), - .fsl_dat_i (fsl_dat_i[31:0]), - .iwb_ack_i (iwb_ack_i), - .iwb_dat_i (iwb_dat_i[31:0]), - .sys_int_i (sys_int_i), - .sys_clk_i (sys_clk_i), - .sys_rst_i (sys_rst_i)); - - // --- SIMULATION KERNEL ---------------------------------- - // synopsys translate_off - - wire [IW-1:0] iwb_adr = {iwb_adr_o, 2'd0}; - wire [DW-1:0] dwb_adr = {dwb_adr_o,2'd0}; - wire [1:0] wBRA = {cpu.rBRA, cpu.rDLY}; - wire [3:0] wMSR = {cpu.xecu.rMSR_BIP, cpu.xecu.rMSR_C, cpu.xecu.rMSR_IE, cpu.xecu.rMSR_BE}; - - - `ifdef AEMB_SIM_KERNEL - always @(posedge cpu.gclk) begin - if (cpu.gena) begin - - $write ("\n", ($stime/10)); - $writeh (" PC=", iwb_adr ); - $writeh ("\t"); - - case (wBRA) - 2'b00: $write(" "); - 2'b01: $write("."); - 2'b10: $write("-"); - 2'b11: $write("+"); - endcase // case (cpu.wBRA) - - case (cpu.rOPC) - 6'o00: if (cpu.rRD == 0) $write(" "); else $write("ADD"); - 6'o01: $write("RSUB"); - 6'o02: $write("ADDC"); - 6'o03: $write("RSUBC"); - 6'o04: $write("ADDK"); - 6'o05: case (cpu.rIMM[1:0]) - 2'o0: $write("RSUBK"); - 2'o1: $write("CMP"); - 2'o3: $write("CMPU"); - default: $write("XXX"); - endcase // case (cpu.rIMM[1:0]) - 6'o06: $write("ADDKC"); - 6'o07: $write("RSUBKC"); - - 6'o10: $write("ADDI"); - 6'o11: $write("RSUBI"); - 6'o12: $write("ADDIC"); - 6'o13: $write("RSUBIC"); - 6'o14: $write("ADDIK"); - 6'o15: $write("RSUBIK"); - 6'o16: $write("ADDIKC"); - 6'o17: $write("RSUBIKC"); - - 6'o20: $write("MUL"); - 6'o21: case (cpu.rALT[10:9]) - 2'o0: $write("BSRL"); - 2'o1: $write("BSRA"); - 2'o2: $write("BSLL"); - default: $write("XXX"); - endcase // case (cpu.rALT[10:9]) - 6'o22: $write("IDIV"); - - 6'o30: $write("MULI"); - 6'o31: case (cpu.rALT[10:9]) - 2'o0: $write("BSRLI"); - 2'o1: $write("BSRAI"); - 2'o2: $write("BSLLI"); - default: $write("XXX"); - endcase // case (cpu.rALT[10:9]) - 6'o33: case (cpu.rRB[4:2]) - 3'o0: $write("GET"); - 3'o4: $write("PUT"); - 3'o2: $write("NGET"); - 3'o6: $write("NPUT"); - 3'o1: $write("CGET"); - 3'o5: $write("CPUT"); - 3'o3: $write("NCGET"); - 3'o7: $write("NCPUT"); - endcase // case (cpu.rRB[4:2]) - - 6'o40: $write("OR"); - 6'o41: $write("AND"); - 6'o42: if (cpu.rRD == 0) $write(" "); else $write("XOR"); - 6'o43: $write("ANDN"); - 6'o44: case (cpu.rIMM[6:5]) - 2'o0: $write("SRA"); - 2'o1: $write("SRC"); - 2'o2: $write("SRL"); - 2'o3: if (cpu.rIMM[0]) $write("SEXT16"); else $write("SEXT8"); - endcase // case (cpu.rIMM[6:5]) - - 6'o45: $write("MOV"); - 6'o46: case (cpu.rRA[3:2]) - 3'o0: $write("BR"); - 3'o1: $write("BRL"); - 3'o2: $write("BRA"); - 3'o3: $write("BRAL"); - endcase // case (cpu.rRA[3:2]) - - 6'o47: case (cpu.rRD[2:0]) - 3'o0: $write("BEQ"); - 3'o1: $write("BNE"); - 3'o2: $write("BLT"); - 3'o3: $write("BLE"); - 3'o4: $write("BGT"); - 3'o5: $write("BGE"); - default: $write("XXX"); - endcase // case (cpu.rRD[2:0]) - - 6'o50: $write("ORI"); - 6'o51: $write("ANDI"); - 6'o52: $write("XORI"); - 6'o53: $write("ANDNI"); - 6'o54: $write("IMMI"); - 6'o55: case (cpu.rRD[1:0]) - 2'o0: $write("RTSD"); - 2'o1: $write("RTID"); - 2'o2: $write("RTBD"); - default: $write("XXX"); - endcase // case (cpu.rRD[1:0]) - 6'o56: case (cpu.rRA[3:2]) - 3'o0: $write("BRI"); - 3'o1: $write("BRLI"); - 3'o2: $write("BRAI"); - 3'o3: $write("BRALI"); - endcase // case (cpu.rRA[3:2]) - 6'o57: case (cpu.rRD[2:0]) - 3'o0: $write("BEQI"); - 3'o1: $write("BNEI"); - 3'o2: $write("BLTI"); - 3'o3: $write("BLEI"); - 3'o4: $write("BGTI"); - 3'o5: $write("BGEI"); - default: $write("XXX"); - endcase // case (cpu.rRD[2:0]) - - 6'o60: $write("LBU"); - 6'o61: $write("LHU"); - 6'o62: $write("LW"); - 6'o64: $write("SB"); - 6'o65: $write("SH"); - 6'o66: $write("SW"); - - 6'o70: $write("LBUI"); - 6'o71: $write("LHUI"); - 6'o72: $write("LWI"); - 6'o74: $write("SBI"); - 6'o75: $write("SHI"); - 6'o76: $write("SWI"); - - default: $write("XXX"); - endcase // case (cpu.rOPC) - - case (cpu.rOPC[3]) - 1'b1: $writeh("\tr",cpu.rRD,", r",cpu.rRA,", h",cpu.rIMM); - 1'b0: $writeh("\tr",cpu.rRD,", r",cpu.rRA,", r",cpu.rRB," "); - endcase // case (cpu.rOPC[3]) - - - // ALU - $write("\t"); - $writeh(" A=",cpu.xecu.rOPA); - $writeh(" B=",cpu.xecu.rOPB); - - case (cpu.rMXALU) - 3'o0: $write(" ADD"); - 3'o1: $write(" LOG"); - 3'o2: $write(" SFT"); - 3'o3: $write(" MOV"); - 3'o4: $write(" MUL"); - 3'o5: $write(" BSF"); - default: $write(" XXX"); - endcase // case (cpu.rMXALU) - $writeh("=h",cpu.xecu.xRESULT); - - // WRITEBACK - $writeh("\tSR=", wMSR," "); - - if (cpu.regf.fRDWE) begin - case (cpu.rMXDST) - 2'o2: begin - if (dwb_stb_o) $writeh("R",cpu.rRW,"=RAM(h",cpu.regf.xWDAT,")"); - if (fsl_stb_o) $writeh("R",cpu.rRW,"=FSL(h",cpu.regf.xWDAT,")"); - end - 2'o1: $writeh("R",cpu.rRW,"=LNK(h",cpu.regf.xWDAT,")"); - 2'o0: $writeh("R",cpu.rRW,"=ALU(h",cpu.regf.xWDAT,")"); - endcase // case (cpu.rMXDST) - end - - // STORE - if (dwb_stb_o & dwb_wre_o) begin - $writeh("RAM(", dwb_adr ,")=", dwb_dat_o); - case (dwb_sel_o) - 4'hF: $write(":L"); - 4'h3,4'hC: $write(":W"); - 4'h1,4'h2,4'h4,4'h8: $write(":B"); - endcase // case (dwb_sel_o) - - end - - end // if (cpu.gena) - - end // always @ (posedge cpu.gclk) - `endif // `ifdef AEMB_SIM_KERNEL - - // synopsys translate_on - -endmodule // aeMB_sim - -/* - $Log: aeMB_sim.v,v $ - Revision 1.2 2008/06/06 09:36:02 sybreon - single thread design - - Revision 1.1 2007/12/23 20:40:45 sybreon - Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. - - */ \ No newline at end of file diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v deleted file mode 100644 index 5de2ea619..000000000 --- a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v +++ /dev/null @@ -1,412 +0,0 @@ -/* $Id: aeMB_xecu.v,v 1.12 2008/05/11 13:48:46 sybreon Exp $ -** -** AEMB MAIN EXECUTION ALU -** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -** -** This file is part of AEMB. -** -** AEMB is free software: you can redistribute it and/or modify it -** under the terms of the GNU Lesser General Public License as -** published by the Free Software Foundation, either version 3 of the -** License, or (at your option) any later version. -** -** AEMB is distributed in the hope that it will be useful, but WITHOUT -** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -** Public License for more details. -** -** You should have received a copy of the GNU Lesser General Public -** License along with AEMB. If not, see . -*/ - -module aeMB_xecu (/*AUTOARG*/ - // Outputs - dwb_adr_o, dwb_sel_o, fsl_adr_o, fsl_tag_o, rRESULT, rDWBSEL, - rMSR_IE, rMSR_BIP, - // Inputs - rREGA, rREGB, rMXSRC, rMXTGT, rRA, rRB, rMXALU, rBRA, rDLY, rALT, - rSTALL, rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena - ); - parameter DW=32; - - parameter MUL=0; - parameter BSF=0; - - // DATA WISHBONE - output [DW-1:2] dwb_adr_o; - output [3:0] dwb_sel_o; - - // FSL WISHBONE - output [6:2] fsl_adr_o; - output [1:0] fsl_tag_o; - - // INTERNAL - output [31:0] rRESULT; - output [3:0] rDWBSEL; - output rMSR_IE; - output rMSR_BIP; - input [31:0] rREGA, rREGB; - input [1:0] rMXSRC, rMXTGT; - input [4:0] rRA, rRB; - input [2:0] rMXALU; - input rBRA, rDLY; - input [10:0] rALT; - - input rSTALL; - input [31:0] rSIMM; - input [15:0] rIMM; - input [5:0] rOPC; - input [4:0] rRD; - input [31:0] rDWBDI; - input [31:2] rPC; - - // SYSTEM - input gclk, grst, gena; - - reg rMSR_C, xMSR_C; - reg rMSR_IE, xMSR_IE; - reg rMSR_BE, xMSR_BE; - reg rMSR_BIP, xMSR_BIP; - - wire fSKIP = rBRA & !rDLY; - - // --- OPERAND SELECT - - reg [31:0] rOPA, rOPB; - always @(/*AUTOSENSE*/rDWBDI or rMXSRC or rPC or rREGA or rRESULT) - case (rMXSRC) - 2'o0: rOPA <= rREGA; - 2'o1: rOPA <= rRESULT; - 2'o2: rOPA <= rDWBDI; - 2'o3: rOPA <= {rPC, 2'o0}; - endcase // case (rMXSRC) - - always @(/*AUTOSENSE*/rDWBDI or rMXTGT or rREGB or rRESULT or rSIMM) - case (rMXTGT) - 2'o0: rOPB <= rREGB; - 2'o1: rOPB <= rRESULT; - 2'o2: rOPB <= rDWBDI; - 2'o3: rOPB <= rSIMM; - endcase // case (rMXTGT) - - // --- ADD/SUB SELECTOR ---- - - reg rRES_ADDC; - reg [31:0] rRES_ADD; - - wire [31:0] wADD; - wire wADC; - - wire fCCC = !rOPC[5] & rOPC[1]; // & !rOPC[4] - wire fSUB = !rOPC[5] & rOPC[0]; // & !rOPC[4] - wire fCMP = !rOPC[3] & rIMM[1]; // unsigned only - wire wCMP = (fCMP) ? !wADC : wADD[31]; // cmpu adjust - - wire [31:0] wOPA = (fSUB) ? ~rOPA : rOPA; - wire wOPC = (fCCC) ? rMSR_C : fSUB; - - assign {wADC, wADD} = (rOPB + wOPA) + wOPC; // add carry - - always @(/*AUTOSENSE*/wADC or wADD or wCMP) begin - {rRES_ADDC, rRES_ADD} <= #1 {wADC, wCMP, wADD[30:0]}; // add with carry - end - - // --- LOGIC SELECTOR -------------------------------------- - - reg [31:0] rRES_LOG; - always @(/*AUTOSENSE*/rOPA or rOPB or rOPC) - case (rOPC[1:0]) - 2'o0: rRES_LOG <= #1 rOPA | rOPB; - 2'o1: rRES_LOG <= #1 rOPA & rOPB; - 2'o2: rRES_LOG <= #1 rOPA ^ rOPB; - 2'o3: rRES_LOG <= #1 rOPA & ~rOPB; - endcase // case (rOPC[1:0]) - - // --- SHIFTER SELECTOR ------------------------------------ - - reg [31:0] rRES_SFT; - reg rRES_SFTC; - - always @(/*AUTOSENSE*/rIMM or rMSR_C or rOPA) - case (rIMM[6:5]) - 2'o0: {rRES_SFT, rRES_SFTC} <= #1 {rOPA[31],rOPA[31:0]}; - 2'o1: {rRES_SFT, rRES_SFTC} <= #1 {rMSR_C,rOPA[31:0]}; - 2'o2: {rRES_SFT, rRES_SFTC} <= #1 {1'b0,rOPA[31:0]}; - 2'o3: {rRES_SFT, rRES_SFTC} <= #1 (rIMM[0]) ? { {(16){rOPA[15]}}, rOPA[15:0], rMSR_C} : - { {(24){rOPA[7]}}, rOPA[7:0], rMSR_C}; - endcase // case (rIMM[6:5]) - - // --- MOVE SELECTOR --------------------------------------- - - wire [31:0] wMSR = {rMSR_C, 3'o0, - 20'h0ED32, - 4'h0, rMSR_BIP, rMSR_C, rMSR_IE, rMSR_BE}; - wire fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0]; - wire fMFPC = (rOPC == 6'o45) & !rIMM[14] & !rIMM[0]; - reg [31:0] rRES_MOV; - always @(/*AUTOSENSE*/fMFPC or fMFSR or rOPA or rOPB or rPC or rRA - or wMSR) - rRES_MOV <= (fMFSR) ? wMSR : - (fMFPC) ? rPC : - (rRA[3]) ? rOPB : - rOPA; - - // --- MULTIPLIER ------------------------------------------ - // TODO: 2 stage multiplier - - reg [31:0] rRES_MUL, rRES_MUL0, xRES_MUL; - always @(/*AUTOSENSE*/rOPA or rOPB) begin - xRES_MUL <= (rOPA * rOPB); - end - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rRES_MUL <= 32'h0; - // End of automatics - end else if (rSTALL) begin - rRES_MUL <= #1 xRES_MUL; - end - - - // --- BARREL SHIFTER -------------------------------------- - - reg [31:0] rRES_BSF; - reg [31:0] xBSRL, xBSRA, xBSLL; - - // Infer a logical left barrel shifter. - always @(/*AUTOSENSE*/rOPA or rOPB) - xBSLL <= rOPA << rOPB[4:0]; - - // Infer a logical right barrel shifter. - always @(/*AUTOSENSE*/rOPA or rOPB) - xBSRL <= rOPA >> rOPB[4:0]; - - // Infer a arithmetic right barrel shifter. - always @(/*AUTOSENSE*/rOPA or rOPB) - case (rOPB[4:0]) - 5'd00: xBSRA <= rOPA; - 5'd01: xBSRA <= {{(1){rOPA[31]}}, rOPA[31:1]}; - 5'd02: xBSRA <= {{(2){rOPA[31]}}, rOPA[31:2]}; - 5'd03: xBSRA <= {{(3){rOPA[31]}}, rOPA[31:3]}; - 5'd04: xBSRA <= {{(4){rOPA[31]}}, rOPA[31:4]}; - 5'd05: xBSRA <= {{(5){rOPA[31]}}, rOPA[31:5]}; - 5'd06: xBSRA <= {{(6){rOPA[31]}}, rOPA[31:6]}; - 5'd07: xBSRA <= {{(7){rOPA[31]}}, rOPA[31:7]}; - 5'd08: xBSRA <= {{(8){rOPA[31]}}, rOPA[31:8]}; - 5'd09: xBSRA <= {{(9){rOPA[31]}}, rOPA[31:9]}; - 5'd10: xBSRA <= {{(10){rOPA[31]}}, rOPA[31:10]}; - 5'd11: xBSRA <= {{(11){rOPA[31]}}, rOPA[31:11]}; - 5'd12: xBSRA <= {{(12){rOPA[31]}}, rOPA[31:12]}; - 5'd13: xBSRA <= {{(13){rOPA[31]}}, rOPA[31:13]}; - 5'd14: xBSRA <= {{(14){rOPA[31]}}, rOPA[31:14]}; - 5'd15: xBSRA <= {{(15){rOPA[31]}}, rOPA[31:15]}; - 5'd16: xBSRA <= {{(16){rOPA[31]}}, rOPA[31:16]}; - 5'd17: xBSRA <= {{(17){rOPA[31]}}, rOPA[31:17]}; - 5'd18: xBSRA <= {{(18){rOPA[31]}}, rOPA[31:18]}; - 5'd19: xBSRA <= {{(19){rOPA[31]}}, rOPA[31:19]}; - 5'd20: xBSRA <= {{(20){rOPA[31]}}, rOPA[31:20]}; - 5'd21: xBSRA <= {{(21){rOPA[31]}}, rOPA[31:21]}; - 5'd22: xBSRA <= {{(22){rOPA[31]}}, rOPA[31:22]}; - 5'd23: xBSRA <= {{(23){rOPA[31]}}, rOPA[31:23]}; - 5'd24: xBSRA <= {{(24){rOPA[31]}}, rOPA[31:24]}; - 5'd25: xBSRA <= {{(25){rOPA[31]}}, rOPA[31:25]}; - 5'd26: xBSRA <= {{(26){rOPA[31]}}, rOPA[31:26]}; - 5'd27: xBSRA <= {{(27){rOPA[31]}}, rOPA[31:27]}; - 5'd28: xBSRA <= {{(28){rOPA[31]}}, rOPA[31:28]}; - 5'd29: xBSRA <= {{(29){rOPA[31]}}, rOPA[31:29]}; - 5'd30: xBSRA <= {{(30){rOPA[31]}}, rOPA[31:30]}; - 5'd31: xBSRA <= {{(31){rOPA[31]}}, rOPA[31]}; - endcase // case (rOPB[4:0]) - - reg [31:0] rBSRL, rBSRA, rBSLL; - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rBSLL <= 32'h0; - rBSRA <= 32'h0; - rBSRL <= 32'h0; - // End of automatics - end else if (rSTALL) begin - rBSRL <= #1 xBSRL; - rBSRA <= #1 xBSRA; - rBSLL <= #1 xBSLL; - end - - always @(/*AUTOSENSE*/rALT or rBSLL or rBSRA or rBSRL) - case (rALT[10:9]) - 2'd0: rRES_BSF <= rBSRL; - 2'd1: rRES_BSF <= rBSRA; - 2'd2: rRES_BSF <= rBSLL; - default: rRES_BSF <= 32'hX; - endcase // case (rALT[10:9]) - - - // --- MSR REGISTER ----------------- - - // C - wire fMTS = (rOPC == 6'o45) & rIMM[14] & !fSKIP; - wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0); - - always @(/*AUTOSENSE*/fADDC or fMTS or fSKIP or rMSR_C or rMXALU - or rOPA or rRES_ADDC or rRES_SFTC) - //if (fSKIP | |rXCE) begin - if (fSKIP) begin - xMSR_C <= rMSR_C; - end else - case (rMXALU) - 3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C; - 3'o1: xMSR_C <= rMSR_C; // LOGIC - 3'o2: xMSR_C <= rRES_SFTC; // SHIFT - 3'o3: xMSR_C <= (fMTS) ? rOPA[2] : rMSR_C; - 3'o4: xMSR_C <= rMSR_C; - 3'o5: xMSR_C <= rMSR_C; - default: xMSR_C <= 1'hX; - endcase // case (rMXALU) - - // IE/BIP/BE - wire fRTID = (rOPC == 6'o55) & rRD[0] & !fSKIP; - wire fRTBD = (rOPC == 6'o55) & rRD[1] & !fSKIP; - wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC); - wire fINT = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE); - - always @(/*AUTOSENSE*/fINT or fMTS or fRTID or rMSR_IE or rOPA) - xMSR_IE <= (fINT) ? 1'b0 : - (fRTID) ? 1'b1 : - (fMTS) ? rOPA[1] : - rMSR_IE; - - always @(/*AUTOSENSE*/fBRK or fMTS or fRTBD or rMSR_BIP or rOPA) - xMSR_BIP <= (fBRK) ? 1'b1 : - (fRTBD) ? 1'b0 : - (fMTS) ? rOPA[3] : - rMSR_BIP; - - always @(/*AUTOSENSE*/fMTS or rMSR_BE or rOPA) - xMSR_BE <= (fMTS) ? rOPA[0] : rMSR_BE; - - // --- RESULT SELECTOR ------------------------------------------- - // Selects results from functional units. - reg [31:0] rRESULT, xRESULT; - - // RESULT - always @(/*AUTOSENSE*/fSKIP or rMXALU or rRES_ADD or rRES_BSF - or rRES_LOG or rRES_MOV or rRES_MUL or rRES_SFT) - if (fSKIP) - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - xRESULT <= 32'h0; - // End of automatics - else - case (rMXALU) - 3'o0: xRESULT <= rRES_ADD; - 3'o1: xRESULT <= rRES_LOG; - 3'o2: xRESULT <= rRES_SFT; - 3'o3: xRESULT <= rRES_MOV; - 3'o4: xRESULT <= (MUL) ? rRES_MUL : 32'hX; - 3'o5: xRESULT <= (BSF) ? rRES_BSF : 32'hX; - default: xRESULT <= 32'hX; - endcase // case (rMXALU) - - // --- DATA WISHBONE ----- - - reg [3:0] rDWBSEL, xDWBSEL; - assign dwb_adr_o = rRESULT[DW-1:2]; - assign dwb_sel_o = rDWBSEL; - - always @(/*AUTOSENSE*/rOPC or wADD) - case (rOPC[1:0]) - 2'o0: case (wADD[1:0]) // 8'bit - 2'o0: xDWBSEL <= 4'h8; - 2'o1: xDWBSEL <= 4'h4; - 2'o2: xDWBSEL <= 4'h2; - 2'o3: xDWBSEL <= 4'h1; - endcase // case (wADD[1:0]) - 2'o1: xDWBSEL <= (wADD[1]) ? 4'h3 : 4'hC; // 16'bit - 2'o2: xDWBSEL <= 4'hF; // 32'bit - 2'o3: xDWBSEL <= 4'h0; // FSL - endcase // case (rOPC[1:0]) - - // --- FSL WISHBONE -------------------- - - reg [14:2] rFSLADR, xFSLADR; - - assign {fsl_adr_o, fsl_tag_o} = rFSLADR[8:2]; - - always @(/*AUTOSENSE*/rALT or rRB) begin - xFSLADR <= {rALT, rRB[3:2]}; - end - - // --- SYNC --- - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rDWBSEL <= 4'h0; - rFSLADR <= 13'h0; - rMSR_BE <= 1'h0; - rMSR_BIP <= 1'h0; - rMSR_C <= 1'h0; - rMSR_IE <= 1'h0; - rRESULT <= 32'h0; - // End of automatics - end else if (gena) begin // if (grst) - rRESULT <= #1 xRESULT; - rDWBSEL <= #1 xDWBSEL; - rMSR_C <= #1 xMSR_C; - rMSR_IE <= #1 xMSR_IE; - rMSR_BE <= #1 xMSR_BE; - rMSR_BIP <= #1 xMSR_BIP; - rFSLADR <= #1 xFSLADR; - end - -endmodule // aeMB_xecu - -/* - $Log: aeMB_xecu.v,v $ - Revision 1.12 2008/05/11 13:48:46 sybreon - Backported Adder from AEMB2_EDK62. - Fixes 64-bit math problem reported by M. Ettus. - - Revision 1.11 2008/01/19 15:57:36 sybreon - Fix MTS during interrupt vectoring bug (reported by M. Ettus). - - Revision 1.10 2007/12/25 22:15:09 sybreon - Stalls pipeline on MUL/BSF instructions results in minor speed improvements. - - Revision 1.9 2007/11/30 16:42:51 sybreon - Minor code cleanup. - - Revision 1.8 2007/11/16 21:52:03 sybreon - Added fsl_tag_o to FSL bus (tag either address or data). - - Revision 1.7 2007/11/14 22:14:34 sybreon - Changed interrupt handling system (reported by M. Ettus). - - Revision 1.6 2007/11/10 16:39:38 sybreon - Upgraded license to LGPLv3. - Significant performance optimisations. - - Revision 1.5 2007/11/09 20:51:52 sybreon - Added GET/PUT support through a FSL bus. - - Revision 1.4 2007/11/08 14:17:47 sybreon - Parameterised optional components. - - Revision 1.3 2007/11/03 08:34:55 sybreon - Minor code cleanup. - - Revision 1.2 2007/11/02 19:20:58 sybreon - Added better (beta) interrupt support. - Changed MSR_IE to disabled at reset as per MB docs. - - Revision 1.1 2007/11/02 03:25:41 sybreon - New EDK 3.2 compatible design with optional barrel-shifter and multiplier. - Fixed various minor data hazard bugs. - Code compatible with -O0/1/2/3/s generated code. - -*/ \ No newline at end of file diff --git a/fpga/usrp2/opencores/aemb/sim/.gitignore b/fpga/usrp2/opencores/aemb/sim/.gitignore deleted file mode 100644 index 4ef5da542..000000000 --- a/fpga/usrp2/opencores/aemb/sim/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -/*.bin -/*.dump -/*.vcd -/*.rom diff --git a/fpga/usrp2/opencores/aemb/sim/CODE_DEBUG.sav b/fpga/usrp2/opencores/aemb/sim/CODE_DEBUG.sav deleted file mode 100644 index f777173c4..000000000 --- a/fpga/usrp2/opencores/aemb/sim/CODE_DEBUG.sav +++ /dev/null @@ -1,16 +0,0 @@ -[size] 1400 971 -[pos] -1 -1 -*-5.188574 2727 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -testbench.dut.dwb_we_o -@22 -testbench.dut.dwb_sel_o[3:0] -testbench.dut.dwb_adr_o[15:0] -@28 -testbench.dut.sys_clk_i -@22 -testbench.dut.dwb_dat_o[31:0] -@821 -testbench.dut.dwb_dat_i[31:0] -@22 -testbench.dut.dwb_dat_i[31:0] diff --git a/fpga/usrp2/opencores/aemb/sim/cversim b/fpga/usrp2/opencores/aemb/sim/cversim deleted file mode 100755 index 0dbb7aea1..000000000 --- a/fpga/usrp2/opencores/aemb/sim/cversim +++ /dev/null @@ -1,22 +0,0 @@ -#!/bin/sh -# $Id: cversim,v 1.5 2007/12/11 00:44:30 sybreon Exp $ -# $Log: cversim,v $ -# Revision 1.5 2007/12/11 00:44:30 sybreon -# Modified for AEMB2 -# -# Revision 1.4 2007/11/30 17:08:30 sybreon -# Moved simulation kernel into code. -# -# Revision 1.3 2007/11/05 10:59:31 sybreon -# Added random seed for simulation. -# -# Revision 1.2 2007/04/12 20:21:33 sybreon -# Moved testbench into /sim/verilog. -# Simulation cleanups. -# -# Revision 1.1 2007/03/09 17:41:55 sybreon -# initial import -# -RANDOM=$(date +%s) -echo "parameter randseed = $RANDOM;" > random.v -cver -q -w +define+AEMBX_SIMULATION_KERNEL $@ ../rtl/verilog/*.v diff --git a/fpga/usrp2/opencores/aemb/sim/iversim b/fpga/usrp2/opencores/aemb/sim/iversim deleted file mode 100755 index 9d2384b5a..000000000 --- a/fpga/usrp2/opencores/aemb/sim/iversim +++ /dev/null @@ -1,21 +0,0 @@ -#!/bin/sh -# $Id: iversim,v 1.5 2007/12/11 00:44:30 sybreon Exp $ -# $Log: iversim,v $ -# Revision 1.5 2007/12/11 00:44:30 sybreon -# Modified for AEMB2 -# -# Revision 1.4 2007/11/30 17:08:30 sybreon -# Moved simulation kernel into code. -# -# Revision 1.3 2007/11/09 20:50:51 sybreon -# Added log output to iverilog.log -# -# Revision 1.2 2007/11/05 10:59:31 sybreon -# Added random seed for simulation. -# -# Revision 1.1 2007/03/09 17:41:55 sybreon -# initial import -# -RANDOM=$(date +%s) -echo "parameter randseed = $RANDOM;" > random.v -iverilog $@ -DAEMBX_SIMULATION_KERNEL ../rtl/verilog/*.v && vvp -l iverilog.log a.out && rm a.out diff --git a/fpga/usrp2/opencores/aemb/sim/verilog/aemb2.v b/fpga/usrp2/opencores/aemb/sim/verilog/aemb2.v deleted file mode 100644 index bda1704e3..000000000 --- a/fpga/usrp2/opencores/aemb/sim/verilog/aemb2.v +++ /dev/null @@ -1,242 +0,0 @@ -/* $Id: aemb2.v,v 1.3 2007/12/28 21:44:50 sybreon Exp $ -** -** AEMB2 TEST BENCH -** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -** -** This file is part of AEMB. -** -** AEMB is free software: you can redistribute it and/or modify it -** under the terms of the GNU Lesser General Public License as -** published by the Free Software Foundation, either version 3 of the -** License, or (at your option) any later version. -** -** AEMB is distributed in the hope that it will be useful, but WITHOUT -** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -** Public License for more details. -** -** You should have received a copy of the GNU Lesser General Public -** License along with AEMB. If not, see . -*/ - -module aemb2 (); - parameter IWB=16; - parameter DWB=16; - - parameter TXE = 0; ///< thread execution enable - - parameter MUL = 1; ///< enable hardware multiplier - parameter BSF = 1; ///< enable barrel shifter - parameter FSL = 1; ///< enable FSL bus - parameter DIV = 0; ///< enable hardware divider - -`include "random.v" - - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [6:2] cwb_adr_o; // From dut of aeMB2_sim.v - wire [31:0] cwb_dat_o; // From dut of aeMB2_sim.v - wire [3:0] cwb_sel_o; // From dut of aeMB2_sim.v - wire cwb_stb_o; // From dut of aeMB2_sim.v - wire [1:0] cwb_tga_o; // From dut of aeMB2_sim.v - wire cwb_wre_o; // From dut of aeMB2_sim.v - wire [DWB-1:2] dwb_adr_o; // From dut of aeMB2_sim.v - wire dwb_cyc_o; // From dut of aeMB2_sim.v - wire [31:0] dwb_dat_o; // From dut of aeMB2_sim.v - wire [3:0] dwb_sel_o; // From dut of aeMB2_sim.v - wire dwb_stb_o; // From dut of aeMB2_sim.v - wire dwb_tga_o; // From dut of aeMB2_sim.v - wire dwb_wre_o; // From dut of aeMB2_sim.v - wire [IWB-1:2] iwb_adr_o; // From dut of aeMB2_sim.v - wire iwb_stb_o; // From dut of aeMB2_sim.v - wire iwb_tga_o; // From dut of aeMB2_sim.v - wire iwb_wre_o; // From dut of aeMB2_sim.v - // End of automatics - /*AUTOREGINPUT*/ - // Beginning of automatic reg inputs (for undeclared instantiated-module inputs) - reg cwb_ack_i; // To dut of aeMB2_sim.v - reg dwb_ack_i; // To dut of aeMB2_sim.v - reg iwb_ack_i; // To dut of aeMB2_sim.v - reg sys_clk_i; // To dut of aeMB2_sim.v - reg sys_int_i; // To dut of aeMB2_sim.v - reg sys_rst_i; // To dut of aeMB2_sim.v - // End of automatics - - // INITIAL SETUP ////////////////////////////////////////////////////// - - //reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i; - reg svc; - integer inttime; - integer seed; - integer theend; - - always #5 sys_clk_i = ~sys_clk_i; - - initial begin - //$dumpfile("dump.vcd"); - //$dumpvars(1,dut, dut.bpcu); - end - - initial begin - seed = randseed; - theend = 0; - svc = 0; - sys_clk_i = $random(seed); - sys_rst_i = 1; - sys_int_i = 0; - #50 sys_rst_i = 0; - #3500000 $finish; - end - - // FAKE MEMORY //////////////////////////////////////////////////////// - - reg [31:0] rom [0:65535]; - reg [31:0] ram[0:65535]; - reg [31:0] dwblat; - reg [15:2] dadr, iadr; - - wire [31:0] dwb_dat_t = ram[dwb_adr_o]; - wire [31:0] iwb_dat_i = rom[iadr]; - wire [31:0] dwb_dat_i = ram[dadr]; - wire [31:0] cwb_dat_i = cwb_adr_o; - -`ifdef POSEDGE -`else // !`ifdef POSEDGE - - always @(negedge sys_clk_i) - if (sys_rst_i) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - cwb_ack_i <= 1'h0; - dwb_ack_i <= 1'h0; - iwb_ack_i <= 1'h0; - // End of automatics - end else begin - iwb_ack_i <= #1 iwb_stb_o; - dwb_ack_i <= #1 dwb_stb_o; - cwb_ack_i <= #1 cwb_stb_o; - end // else: !if(sys_rst_i) - - always @(negedge sys_clk_i) begin - iadr <= #1 iwb_adr_o; - dadr <= #1 dwb_adr_o; - - if (dwb_wre_o & dwb_stb_o) begin - case (dwb_sel_o) - 4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]}; - 4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]}; - 4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]}; - 4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]}; - 4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]}; - 4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]}; - 4'hF: ram[dwb_adr_o] <= {dwb_dat_o}; - endcase // case (dwb_sel_o) - end // if (dwb_we_o & dwb_stb_o) - end // always @ (negedge sys_clk_i) - -`endif // !`ifdef POSEDGE - - - integer i; - initial begin - for (i=0;i<65535;i=i+1) begin - ram[i] <= $random; - end - #1 $readmemh("dump.vmem",rom); - #1 $readmemh("dump.vmem",ram); - end - - // DISPLAY OUTPUTS /////////////////////////////////////////////////// - - integer rnd; - - always @(posedge sys_clk_i) begin - - // Interrupt Monitors - if (!dut.sim.rMSR_IE) begin - rnd = $random % 30; - inttime = $stime + 1000 + (rnd*rnd * 10); - end - if ($stime > inttime) begin - sys_int_i = 1; - svc = 0; - end - if (($stime > inttime + 500) && !svc) begin - $display("\n\t*** INTERRUPT TIMEOUT ***", inttime); - $finish; - end - if (dwb_wre_o & (dwb_dat_o == "RTNI")) sys_int_i = 0; - /* - if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin - svc = 1; - //$display("\nLATENCY: ", ($stime - inttime)/10); - end - */ - - // Pass/Fail Monitors - if (dwb_wre_o & (dwb_dat_o == "FAIL")) begin - $display("\n\tFAIL"); - $finish; - end - - if (iwb_dat_i == 32'hb8000000) begin - theend = theend + 1; - end - - if (theend == 5) begin - $display("\n\t*** PASSED ALL TESTS ***"); - $finish; - end - - end // always @ (posedge sys_clk_i) - - // INTERNAL WIRING //////////////////////////////////////////////////// - - aeMB2_sim - #(/*AUTOINSTPARAM*/ - // Parameters - .IWB (IWB), - .DWB (DWB), - .TXE (TXE), - .MUL (MUL), - .BSF (BSF), - .FSL (FSL), - .DIV (DIV)) - dut (/*AUTOINST*/ - // Outputs - .cwb_adr_o (cwb_adr_o[6:2]), - .cwb_dat_o (cwb_dat_o[31:0]), - .cwb_sel_o (cwb_sel_o[3:0]), - .cwb_stb_o (cwb_stb_o), - .cwb_tga_o (cwb_tga_o[1:0]), - .cwb_wre_o (cwb_wre_o), - .dwb_adr_o (dwb_adr_o[DWB-1:2]), - .dwb_cyc_o (dwb_cyc_o), - .dwb_dat_o (dwb_dat_o[31:0]), - .dwb_sel_o (dwb_sel_o[3:0]), - .dwb_stb_o (dwb_stb_o), - .dwb_tga_o (dwb_tga_o), - .dwb_wre_o (dwb_wre_o), - .iwb_adr_o (iwb_adr_o[IWB-1:2]), - .iwb_stb_o (iwb_stb_o), - .iwb_tga_o (iwb_tga_o), - .iwb_wre_o (iwb_wre_o), - // Inputs - .cwb_ack_i (cwb_ack_i), - .cwb_dat_i (cwb_dat_i[31:0]), - .dwb_ack_i (dwb_ack_i), - .dwb_dat_i (dwb_dat_i[31:0]), - .iwb_ack_i (iwb_ack_i), - .iwb_dat_i (iwb_dat_i[31:0]), - .sys_clk_i (sys_clk_i), - .sys_int_i (sys_int_i), - .sys_rst_i (sys_rst_i)); - -endmodule // edk32 - -/* $Log $ */ - -// Local Variables: -// verilog-library-directories:("." "../../rtl/verilog/") -// verilog-library-files:("") -// End: diff --git a/fpga/usrp2/opencores/aemb/sim/verilog/edk32.v b/fpga/usrp2/opencores/aemb/sim/verilog/edk32.v deleted file mode 100644 index 68465e9e0..000000000 --- a/fpga/usrp2/opencores/aemb/sim/verilog/edk32.v +++ /dev/null @@ -1,288 +0,0 @@ -/* $Id: edk32.v,v 1.12 2007/12/23 20:40:51 sybreon Exp $ -** -** AEMB EDK 3.2 Compatible Core TEST -** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -** -** This file is part of AEMB. -** -** AEMB is free software: you can redistribute it and/or modify it -** under the terms of the GNU Lesser General Public License as -** published by the Free Software Foundation, either version 3 of the -** License, or (at your option) any later version. -** -** AEMB is distributed in the hope that it will be useful, but WITHOUT -** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -** Public License for more details. -** -** You should have received a copy of the GNU Lesser General Public -** License along with AEMB. If not, see . -*/ - -`define AEMB_SIMULATION_KERNEL - -module edk32 (); - -`include "random.v" - - // INITIAL SETUP ////////////////////////////////////////////////////// - - reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i; - reg svc; - integer inttime; - integer seed; - integer theend; - - always #5 sys_clk_i = ~sys_clk_i; - - initial begin - //$dumpfile("dump.vcd"); - //$dumpvars(1,dut); - end - - initial begin - seed = randseed; - theend = 0; - svc = 0; - sys_clk_i = $random(seed); - sys_rst_i = 1; - sys_int_i = 0; - sys_exc_i = 0; - #50 sys_rst_i = 0; - end - - initial fork - //inttime $display("FSADFASDFSDAF"); - //#10000 sys_int_i = 1; - //#1100 sys_int_i = 0; - //#100000 $displayh("\nTest Completed."); - //#4000 $finish; - join - - - // FAKE MEMORY //////////////////////////////////////////////////////// - - wire fsl_stb_o; - wire fsl_wre_o; - wire [31:0] fsl_dat_o; - wire [31:0] fsl_dat_i; - wire [6:2] fsl_adr_o; - - wire [15:2] iwb_adr_o; - wire iwb_stb_o; - wire dwb_stb_o; - reg [31:0] rom [0:65535]; - wire [31:0] iwb_dat_i; - reg iwb_ack_i, dwb_ack_i, fsl_ack_i; - - reg [31:0] ram[0:65535]; - wire [31:0] dwb_dat_i; - reg [31:0] dwblat; - wire dwb_we_o; - reg [15:2] dadr,iadr; - wire [3:0] dwb_sel_o; - wire [31:0] dwb_dat_o; - wire [15:2] dwb_adr_o; - wire [31:0] dwb_dat_t; - - initial begin - dwb_ack_i = 0; - iwb_ack_i = 0; - fsl_ack_i = 0; - end - - assign dwb_dat_t = ram[dwb_adr_o]; - assign iwb_dat_i = ram[iadr]; - assign dwb_dat_i = ram[dadr]; - assign fsl_dat_i = fsl_adr_o; - -`ifdef POSEDGE - - always @(posedge sys_clk_i) - if (sys_rst_i) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - dwb_ack_i <= 1'h0; - fsl_ack_i <= 1'h0; - iwb_ack_i <= 1'h0; - // End of automatics - end else begin - iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i; - dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i; - fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i; - end // else: !if(sys_rst_i) - - always @(posedge sys_clk_i) begin - iadr <= #1 iwb_adr_o; - dadr <= #1 dwb_adr_o; - - if (dwb_we_o & dwb_stb_o) begin - case (dwb_sel_o) - 4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]}; - 4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]}; - 4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]}; - 4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]}; - 4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]}; - 4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]}; - 4'hF: ram[dwb_adr_o] <= {dwb_dat_o}; - endcase // case (dwb_sel_o) - end // if (dwb_we_o & dwb_stb_o) - end // always @ (posedge sys_clk_i) - -`else // !`ifdef POSEDGE - - always @(negedge sys_clk_i) - if (sys_rst_i) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - dwb_ack_i <= 1'h0; - fsl_ack_i <= 1'h0; - iwb_ack_i <= 1'h0; - // End of automatics - end else begin - iwb_ack_i <= #1 iwb_stb_o; - dwb_ack_i <= #1 dwb_stb_o; - fsl_ack_i <= #1 fsl_stb_o; - end // else: !if(sys_rst_i) - - always @(negedge sys_clk_i) begin - iadr <= #1 iwb_adr_o; - dadr <= #1 dwb_adr_o; - - if (dwb_we_o & dwb_stb_o) begin - case (dwb_sel_o) - 4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]}; - 4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]}; - 4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]}; - 4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]}; - 4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]}; - 4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]}; - 4'hF: ram[dwb_adr_o] <= {dwb_dat_o}; - endcase // case (dwb_sel_o) - end // if (dwb_we_o & dwb_stb_o) - end // always @ (negedge sys_clk_i) - -`endif // !`ifdef POSEDGE - - - integer i; - initial begin - for (i=0;i<65535;i=i+1) begin - ram[i] <= $random; - end - #1 $readmemh("dump.vmem",ram); - end - - // DISPLAY OUTPUTS /////////////////////////////////////////////////// - - integer rnd; - - always @(posedge sys_clk_i) begin - - // Interrupt Monitors - if (!dut.cpu.rMSR_IE) begin - rnd = $random % 30; - inttime = $stime + 1000 + (rnd*rnd * 10); - end - if ($stime > inttime) begin - sys_int_i = 1; - svc = 0; - end - if (($stime > inttime + 500) && !svc) begin - $display("\n\t*** INTERRUPT TIMEOUT ***", inttime); - $finish; - end - if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0; - if (dut.cpu.regf.fRDWE && (dut.cpu.rRD == 5'h0e) && !svc && dut.cpu.gena) begin - svc = 1; - //$display("\nLATENCY: ", ($stime - inttime)/10); - end - - // Pass/Fail Monitors - if (dwb_we_o & (dwb_dat_o == "FAIL")) begin - $display("\n\tFAIL"); - $finish; - end - - if (iwb_dat_i == 32'hb8000000) begin - theend = theend + 1; - end - - if (theend == 5) begin - $display("\n\t*** PASSED ALL TESTS ***"); - $finish; - end - end // always @ (posedge sys_clk_i) - - // INTERNAL WIRING //////////////////////////////////////////////////// - - aeMB_sim #(16,16) - dut ( - .sys_int_i(sys_int_i), - .dwb_ack_i(dwb_ack_i), - .dwb_stb_o(dwb_stb_o), - .dwb_adr_o(dwb_adr_o), - .dwb_dat_o(dwb_dat_o), - .dwb_dat_i(dwb_dat_i), - .dwb_wre_o(dwb_we_o), - .dwb_sel_o(dwb_sel_o), - - .fsl_ack_i(fsl_ack_i), - .fsl_stb_o(fsl_stb_o), - .fsl_adr_o(fsl_adr_o), - .fsl_dat_o(fsl_dat_o), - .fsl_dat_i(fsl_dat_i), - .fsl_wre_o(fsl_we_o), - - .iwb_adr_o(iwb_adr_o), - .iwb_dat_i(iwb_dat_i), - .iwb_stb_o(iwb_stb_o), - .iwb_ack_i(iwb_ack_i), - .sys_clk_i(sys_clk_i), - .sys_rst_i(sys_rst_i) - ); - -endmodule // edk32 - -/* - $Log: edk32.v,v $ - Revision 1.12 2007/12/23 20:40:51 sybreon - Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. - - Revision 1.11 2007/12/11 00:44:31 sybreon - Modified for AEMB2 - - Revision 1.10 2007/11/30 17:08:30 sybreon - Moved simulation kernel into code. - - Revision 1.9 2007/11/20 18:36:00 sybreon - Removed unnecessary byte acrobatics with VMEM data. - - Revision 1.8 2007/11/18 19:41:45 sybreon - Minor simulation fixes. - - Revision 1.7 2007/11/14 22:11:41 sybreon - Added posedge/negedge bus interface. - Modified interrupt test system. - - Revision 1.6 2007/11/13 23:37:28 sybreon - Updated simulation to also check BRI 0x00 instruction. - - Revision 1.5 2007/11/09 20:51:53 sybreon - Added GET/PUT support through a FSL bus. - - Revision 1.4 2007/11/08 14:18:00 sybreon - Parameterised optional components. - - Revision 1.3 2007/11/05 10:59:31 sybreon - Added random seed for simulation. - - Revision 1.2 2007/11/02 19:16:10 sybreon - Added interrupt simulation. - Changed "human readable" simulation output. - - Revision 1.1 2007/11/02 03:25:45 sybreon - New EDK 3.2 compatible design with optional barrel-shifter and multiplier. - Fixed various minor data hazard bugs. - Code compatible with -O0/1/2/3/s generated code. - */ \ No newline at end of file diff --git a/fpga/usrp2/opencores/aemb/sw/c/aeMB_testbench.c b/fpga/usrp2/opencores/aemb/sw/c/aeMB_testbench.c deleted file mode 100644 index c3402e0ef..000000000 --- a/fpga/usrp2/opencores/aemb/sw/c/aeMB_testbench.c +++ /dev/null @@ -1,385 +0,0 @@ -/* $Id: aeMB_testbench.c,v 1.14 2007/12/28 21:44:04 sybreon Exp $ -** -** AEMB Function Verification C Testbench -** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -** -** This file is part of AEMB. -** -** AEMB is free software: you can redistribute it and/or modify it -** under the terms of the GNU General Public License as published by -** the Free Software Foundation, either version 3 of the License, or -** (at your option) any later version. -** -** AEMB is distributed in the hope that it will be useful, but WITHOUT -** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -** License for more details. -** -** You should have received a copy of the GNU General Public License -** along with AEMB. If not, see . -*/ - -#include -#include -#include - -#include "libaemb.h" - -/** - INTERRUPT TEST - - This tests for the following: - - Pointer addressing - - Interrupt handling - */ - -void __attribute__ ((interrupt_handler)) int_handler(); -volatile int service = 0xDEADDEAD; - -void int_service() -{ - int* pio = (int*)0xFFFFFFFC; - *pio = 0x52544E49; // "INTR" - service = 0; -} - -void int_handler() -{ - int_service(); -} - -/** - INTERRUPT TEST ROUTINE -*/ -int int_test () -{ - // Delay loop until hardware interrupt triggers - volatile int i; - for (i=0; i < 999; i++) { - if (service == 0) return 0; - }; - - return -1; -} - -/** - FIBONACCI TEST - http://en.literateprograms.org/Fibonacci_numbers_(C) - - This tests for the following: - - Recursion & Iteration - - 32/16/8-bit data handling -*/ - -unsigned int fib_slow(unsigned int n) -{ - return n < 2 ? n : fib_slow(n-1) + fib_slow(n-2); -} - -unsigned int fib_fast(unsigned int n) -{ - unsigned int a[3]; - unsigned int *p=a; - unsigned int i; - - for(i=0; i<=n; ++i) { - if(i<2) *p=i; - else { - if(p==a) *p=*(a+1)+*(a+2); - else if(p==a+1) *p=*a+*(a+2); - else *p=*a+*(a+1); - } - if(++p>a+2) p=a; - } - - return p==a?*(p+2):*(p-1); -} - -int fib_test(int max) { - unsigned int n; - unsigned int fast, slow; - // 32-bit LUT - unsigned int fib_lut32[] = { - 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233 - }; - // 16-bit LUT - unsigned short fib_lut16[] = { - 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233 - }; - // 8-bit LUT - unsigned char fib_lut8[] = { - 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233 - }; - - for (n=0;n a) goto b_larger; - while (1) { - a = a % b; - if (a == 0) return b; - b_larger: - b = b % a; - if (b == 0) return a; - } -} - -int euclid_test(int max) -{ - int n; - int euclid; - // Random Numbers - int euclid_a[] = { - 1804289383, 1681692777, 1957747793, 719885386, 596516649, - 1025202362, 783368690, 2044897763, 1365180540, 304089172, - 35005211, 294702567, 336465782, 278722862 - }; - int euclid_b[] = { - 846930886, 1714636915, 424238335, 1649760492, 1189641421, - 1350490027, 1102520059, 1967513926, 1540383426, 1303455736, - 521595368, 1726956429, 861021530, 233665123 - }; - - // GCD - int euclid_lut[] = { - 1, 1, 1, 2, 1, 1, 1, 1, 6, 4, 1, 3, 2, 1 - }; - - for (n=0;n 0.0) - { - xn = (i+(i-1))/2.0; - break; - } - } - while (!(iters++ >= 100 - || x == xn)) - { - x = xn; - xn = x - (x * x - n) / (2 * x); - } - return xn; -} - -int newton_test (int max) { - int n; - float newt; - // 32-bit LUT - float newt_lut[] = { - 0.000000000000000000000000, - 1.000000000000000000000000, - 1.414213538169860839843750, - 1.732050776481628417968750, - 2.000000000000000000000000, - 2.236068010330200195312500, - 2.449489831924438476562500, - 2.645751237869262695312500, - 2.828427076339721679687500, - 3.000000000000000000000000, - 3.162277698516845703125000, - 3.316624879837036132812500, - 3.464101552963256835937500, - 3.605551242828369140625000, - 3.741657495498657226562500 - }; - - for (n=0;n_errno; - // return &errnum; -} -*/ - -int malloc_test() -{ - void *alloc; - - alloc = (void *)malloc(256); // allocate 32 bytes - - if (alloc == NULL) - return -1; - else - return (int) alloc; -} - -/** - MAIN TEST PROGRAMME - - This is the main test procedure. It will output signals onto the - MPI port that is checked by the testbench. - */ - -int main () -{ - // Message Passing Port - int* mpi = (int*)0xFFFFFFFF; - - // Number of each test to run - int max = 10; - - // lock T0 if it's multi-threaded - /* - if ((aemb_isthreaded() == 0) && (aemb_isthread1() != 0)) { - while (1) { - asm volatile ("nop;"); - } - } - */ - - // Enable Global Interrupts - aemb_enable_interrupt(); - - // INT TEST - //if (int_test() == -1) { *mpi = 0x4641494C; } - - // TEST MALLOC - if (malloc_test() == -1) { *mpi = 0x4641494C; } - - // FSL TEST - //if (fsl_test() == -1) { *mpi = 0x4641494C; } - - // Fibonacci Test - if (fib_test(max) == -1) { *mpi = 0x4641494C; } - - // Euclid Test - if (euclid_test(max) == -1) { *mpi = 0x4641494C; } - - // Newton-Rhapson Test - if (newton_test(max) == -1) { *mpi = 0x4641494C; } - - // Disable Global Interrupts - aemb_disable_interrupt(); - - // ALL PASSED - return 0; -} - -/* - HISTORY - $Log: aeMB_testbench.c,v $ - Revision 1.14 2007/12/28 21:44:04 sybreon - Added malloc() test - - Revision 1.13 2007/12/11 00:44:31 sybreon - Modified for AEMB2 - - Revision 1.12 2007/11/18 19:41:45 sybreon - Minor simulation fixes. - - Revision 1.11 2007/11/14 23:41:06 sybreon - Fixed minor interrupt test typo. - - Revision 1.10 2007/11/14 22:12:02 sybreon - Added interrupt test routine. - - Revision 1.9 2007/11/09 20:51:53 sybreon - Added GET/PUT support through a FSL bus. - - Revision 1.8 2007/11/03 08:40:18 sybreon - Minor code cleanup. - - Revision 1.7 2007/11/02 18:32:19 sybreon - Enable MSR_IE with software. - - Revision 1.6 2007/04/30 15:57:10 sybreon - Removed byte acrobatics. - - Revision 1.5 2007/04/27 15:17:59 sybreon - Added code documentation. - Added new tests that test floating point, modulo arithmetic and multiplication/division. - - Revision 1.4 2007/04/25 22:15:05 sybreon - Added support for 8-bit and 16-bit data types. - - Revision 1.3 2007/04/04 14:09:04 sybreon - Added initial interrupt/exception support. - - Revision 1.2 2007/04/04 06:07:45 sybreon - Fixed C code bug which passes the test - - Revision 1.1 2007/03/09 17:41:57 sybreon - initial import -*/ diff --git a/fpga/usrp2/opencores/aemb/sw/c/endian-test.c b/fpga/usrp2/opencores/aemb/sw/c/endian-test.c deleted file mode 100644 index b585f7a30..000000000 --- a/fpga/usrp2/opencores/aemb/sw/c/endian-test.c +++ /dev/null @@ -1,86 +0,0 @@ - -#include "memory_map.h" - -int main() { - char *p = (char *)0x4000; - short *q = (short *)0x5000; - int *r= (int *)0x6000; - - int *output = (int *)0x7000; - - char s; - short t; - int u; - - // Write - // Bytes - *p = (char)1; - p++; - *p = (char)2; - p++; - *p = (char)3; - p++; - *p = (char)4; - p++; - *p = (char)5; - - // Words - *q = (short) 0x1112; - q++; - *q = (short) 0x1314; - q++; - *q = (short) 0x1516; - - // Double Words - *r = 0x21222324; - r++; - *r = 0x25262728; - r++; - *r = 0x292a2b2c; - - - // Read - p = (char *)0x6000; - s = *p; - if(s == 0x21) - *output = 0x53534150; // PASS - else - *output = 0x4C494146; // FAIL - - p = (char *)0x6001; - s = *p; - if(s == 0x22) - *output = 0x53534150; // PASS - else - *output = 0x4C494146; // FAIL - - p = (char *)0x6002; - s = *p; - if(s == 0x23) - *output = 0x53534150; // PASS - else - *output = 0x4C494146; // FAIL - - - p = (char *)0x6003; - s = *p; - if(s == 0x24) - *output = 0x53534150; // PASS - else - *output = 0x4C494146; // FAIL - - q = (short *)0x4000; - t = *q; - if(t == 0x0102) - *output = 0x53534150; // PASS - else - *output = 0x4C494146; // FAIL - - r = (int *)0x4000; - u = *r; - if(u == 0x01020304) - *output = 0x53534150; // PASS - else - *output = 0x4C494146; // FAIL - -} diff --git a/fpga/usrp2/opencores/aemb/sw/c/libaemb.h b/fpga/usrp2/opencores/aemb/sw/c/libaemb.h deleted file mode 100644 index 329a327a1..000000000 --- a/fpga/usrp2/opencores/aemb/sw/c/libaemb.h +++ /dev/null @@ -1,218 +0,0 @@ -/* $Id: libaemb.h,v 1.3 2007/12/16 03:26:37 sybreon Exp $ -** -** AEMB2 CUSTOM LIBRARY -** -** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -** -** This file is part of AEMB. -** -** AEMB is free software: you can redistribute it and/or modify it -** under the terms of the GNU Lesser General Public License as -** published by the Free Software Foundation, either version 3 of the -** License, or (at your option) any later version. -** -** AEMB is distributed in the hope that it will be useful, but WITHOUT -** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -** Public License for more details. -** -** You should have received a copy of the GNU Lesser General Public -** License along with AEMB. If not, see . -*/ - -#ifndef LIBAEMB_H -#define LIBAEMB_H - -#define AEMB_TXE 0x0100 -#define AEMB_TXP 0x0400 -#define AEMB_TX0 0x0300 -#define AEMB_TX1 0x0700 -#define AEMB_MSK 0x0F00 - -#define AEMB_BIP 0x0008 -#define AEMB_CCC 0x0004 -#define AEMB_ITE 0x0002 -#define AEMB_BLE 0x0001 - - -// Linker symbols -extern void* _STACK_SIZE; -extern void* _stack_end; - - -void aemb_hook_init () asm ("_program_init"); -void aemb_hook_clean () asm ("_program_clean"); - -inline void aemb_enable_interrupt (); -inline void aemb_disable_interrupt (); -inline int aemb_isthread1(); -inline int aemb_isthread0(); -inline int aemb_isthreaded(); - -/*! -* Assembly macro to enable MSR_IE -*/ -void aemb_enable_interrupt () -{ - int msr, tmp; - asm volatile ("mfs %0, rmsr;" - "ori %1, %0, 0x02;" - "mts rmsr, %1;" - : "=r"(msr) - : "r" (tmp) - ); -} - -/*! -* Assembly macro to disable MSR_IE -*/ -void aemb_disable_interrupt () -{ - int msr, tmp; - asm volatile ("mfs %0, rmsr;" - "andi %1, %0, 0xFD;" - "mts rmsr, %1;" - : "=r"(msr) - : "r" (tmp) - ); -} - -/*! -* Bootstrap Hook Override -*/ - -void aemb_hook_init () -{ - int msr, tmp; - int stk_end, stk_siz; - - /* - // Check to see if hardware threads are enabled - if (((msr & AEMB_TXE) != AEMB_TXE) || - // Check to see if second thread is started - ((msr & AEMB_TX1) == AEMB_TX1)) return; - */ - //return; - asm volatile ("mfs %0, rmsr;" - // Check for BIP - "andi %1, %0, %5;" - "xori %1, %1, %5;" - "beqi %1, 44;" - - // Check for TXE - "andi %1, %0, %2;" - "xori %1, %1, %2;" - "bnei %1, 36;" - - // Check for TX1 - "andi %1, %0, %3;" - "xori %1, %1, %3;" - "beqi %1, 20;" - - // reallocate stack pointer for T0 - "ori %1, r0, %4;" - "sra %1, %1;" - "rsubk r1, %1, r1;" - - // reboot the machine - //"brki r0, _crtinit;" - "brid 0;" - "nop;" - - // clear BIP - "andni %1, %0, %5;" - "mts rmsr, %1;" - - :"=r"(msr), "=r"(tmp) - :"i"(AEMB_TXE), "i"(AEMB_TX1), "i"(&_STACK_SIZE), "i"(AEMB_BIP) - ); - -} - -/*! - Undo the changes made by programme init -*/ - -void aemb_hook_clean () -{ - int msr, tmp; - int stk_end, stk_siz; - - /* - // Check to see if hardware threads are enabled - if (((msr & AEMB_TXE) != AEMB_TXE) || - // Check to see if second thread is started - ((msr & AEMB_TX1) == AEMB_TX1)) return; - */ - return; - asm volatile ("mfs %0, rmsr;" - "andi %1, %0, %2;" - "xori %1, %1, %2;" - "bnei %1, 28;" - "andi %1, %0, %3;" - "xori %1, %1, %3;" - "beqi %1, 16;" - - // reallocate stack pointer for T0 - "ori %1, r0, %4;" - "sra %1, %1;" - "addk r1, %1, r1;" - - :"=r"(msr), "=r"(tmp) - :"i"(AEMB_TXE), "i"(AEMB_TX1), "i"(&_STACK_SIZE) - ); - - -} - -/* Checks if it's T1, and returns 0 if true */ - -int aemb_isthread1 () -{ - int msr, tmp, res; - asm volatile ("mfs %0, rmsr;" - "andi %1, %0, %3;" - "xori %1, %1, %3;" - :"=r"(msr), "=r"(tmp) - :"i"(AEMB_TXE), "i"(AEMB_TXP) - ); - return tmp; -} - -/* Checks if it's T0, and returns 0 if true */ - -int aemb_isthread0 () -{ - int msr, tmp, res; - asm volatile ("mfs %0, rmsr;" - "andi %1, %0, %3;" - "xori %1, %1, %2;" - :"=r"(msr), "=r"(tmp) - :"i"(AEMB_TXP), "i"(AEMB_MSK) - ); - return tmp; -} - -/* Checks if TXE is available, and returns 0 if true */ - -int aemb_isthreaded () -{ - int msr, tmp, res; - asm volatile ("mfs %0, rmsr;" - "andi %1, %0, %2;" - "xori %1, %1, %2;" - :"=r"(msr), "=r"(tmp) - :"i"(AEMB_TXE), "i"(AEMB_MSK) - ); - return tmp; -} - -#endif - -/* $Log: libaemb.h,v $ -/* Revision 1.3 2007/12/16 03:26:37 sybreon -/* Made T0 loop. -/* -/* Revision 1.1 2007/12/11 00:44:04 sybreon -/* initial import -/* */ diff --git a/fpga/usrp2/opencores/aemb/sw/gccrom b/fpga/usrp2/opencores/aemb/sw/gccrom deleted file mode 100755 index f6e581f1f..000000000 --- a/fpga/usrp2/opencores/aemb/sw/gccrom +++ /dev/null @@ -1,62 +0,0 @@ -#!/bin/sh -# $Id: gccrom,v 1.13 2008/01/19 16:42:54 sybreon Exp $ - -# Compile using C++ pre-processor -mb-g++ -g -Wl,-defsym -Wl,_HEAP_SIZE=0x800 -mxl-soft-div -msoft-float -mxl-barrel-shift -mno-xl-soft-mul -mno-clearbss $@ -o rom.elf -lc_m_bs -lm_m_bs && \ - -# Create a text listing of the compiled code -mb-objdump -DSC rom.elf > rom.dump && \ - -# Convert the ELF file to an SREC file -mb-objcopy -O srec rom.elf rom.srec && \ - -# Generate a Verilog VMEM file from the SREC file -srec_cat rom.srec -o ../sim/dump.vmem -vmem 32 && \ - -# Cleanup code -rm rom.srec && \ - -# Say Cheeze! -echo "ROM generated" - -# $Log: gccrom,v $ -# Revision 1.13 2008/01/19 16:42:54 sybreon -# Uses multiplier + barrel shifter as default. -# -# Revision 1.12 2007/12/11 00:44:32 sybreon -# Modified for AEMB2 -# -# Revision 1.11 2007/11/30 17:09:27 sybreon -# Minor code cleanup. -# -# Revision 1.10 2007/11/20 18:35:34 sybreon -# Generate VMEM instead of HEX dumps of programme. -# -# Revision 1.9 2007/11/18 19:41:46 sybreon -# Minor simulation fixes. -# -# Revision 1.8 2007/11/09 20:52:37 sybreon -# Added some compilation optimisations. -# -# Revision 1.7 2007/11/04 05:16:25 sybreon -# Added -msoft-float and -mxl-soft-div compiler flags. -# -# Revision 1.6 2007/11/02 03:25:46 sybreon -# New EDK 3.2 compatible design with optional barrel-shifter and multiplier. -# Fixed various minor data hazard bugs. -# Code compatible with -O0/1/2/3/s generated code. -# -# Revision 1.5 2007/10/22 19:14:38 sybreon -# Recommended to compile code with -O2/3/s -# -# Revision 1.4 2007/04/30 15:57:31 sybreon -# Modified compilation sequence. -# -# Revision 1.3 2007/04/25 22:15:06 sybreon -# Added support for 8-bit and 16-bit data types. -# -# Revision 1.2 2007/04/04 06:14:39 sybreon -# Minor changes -# -# Revision 1.1 2007/03/09 17:41:56 sybreon -# initial import diff --git a/fpga/usrp2/opencores/i2c/bench/verilog/i2c_slave_model.v b/fpga/usrp2/opencores/i2c/bench/verilog/i2c_slave_model.v deleted file mode 100644 index 0c8ecae0d..000000000 --- a/fpga/usrp2/opencores/i2c/bench/verilog/i2c_slave_model.v +++ /dev/null @@ -1,360 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE rev.B2 compliant synthesizable I2C Slave model //// -//// //// -//// //// -//// Authors: Richard Herveille (richard@asics.ws) www.asics.ws //// -//// John Sheahan (jrsheahan@optushome.com.au) //// -//// //// -//// Downloaded from: http://www.opencores.org/projects/i2c/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001,2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: i2c_slave_model.v,v 1.7 2006/09/04 09:08:51 rherveille Exp $ -// -// $Date: 2006/09/04 09:08:51 $ -// $Revision: 1.7 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: i2c_slave_model.v,v $ -// Revision 1.7 2006/09/04 09:08:51 rherveille -// fixed (n)ack generation -// -// Revision 1.6 2005/02/28 11:33:48 rherveille -// Fixed Tsu:sta timing check. -// Added Thd:sta timing check. -// -// Revision 1.5 2003/12/05 11:05:19 rherveille -// Fixed slave address MSB='1' bug -// -// Revision 1.4 2003/09/11 08:25:37 rherveille -// Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. -// -// Revision 1.3 2002/10/30 18:11:06 rherveille -// Added timing tests to i2c_model. -// Updated testbench. -// -// Revision 1.2 2002/03/17 10:26:38 rherveille -// Fixed some race conditions in the i2c-slave model. -// Added debug information. -// Added headers. -// - -`include "timescale.v" - -module i2c_slave_model (scl, sda); - - // - // parameters - // - parameter I2C_ADR = 7'b001_0000; - - // - // input && outpus - // - input scl; - inout sda; - - // - // Variable declaration - // - wire debug = 1'b1; - - reg [7:0] mem [3:0]; // initiate memory - reg [7:0] mem_adr; // memory address - reg [7:0] mem_do; // memory data output - - reg sta, d_sta; - reg sto, d_sto; - - reg [7:0] sr; // 8bit shift register - reg rw; // read/write direction - - wire my_adr; // my address called ?? - wire i2c_reset; // i2c-statemachine reset - reg [2:0] bit_cnt; // 3bit downcounter - wire acc_done; // 8bits transfered - reg ld; // load downcounter - - reg sda_o; // sda-drive level - wire sda_dly; // delayed version of sda - - // statemachine declaration - parameter idle = 3'b000; - parameter slave_ack = 3'b001; - parameter get_mem_adr = 3'b010; - parameter gma_ack = 3'b011; - parameter data = 3'b100; - parameter data_ack = 3'b101; - - reg [2:0] state; // synopsys enum_state - - // - // module body - // - - initial - begin - sda_o = 1'b1; - state = idle; - end - - // generate shift register - always @(posedge scl) - sr <= #1 {sr[6:0],sda}; - - //detect my_address - assign my_adr = (sr[7:1] == I2C_ADR); - // FIXME: This should not be a generic assign, but rather - // qualified on address transfer phase and probably reset by stop - - //generate bit-counter - always @(posedge scl) - if(ld) - bit_cnt <= #1 3'b111; - else - bit_cnt <= #1 bit_cnt - 3'h1; - - //generate access done signal - assign acc_done = !(|bit_cnt); - - // generate delayed version of sda - // this model assumes a hold time for sda after the falling edge of scl. - // According to the Phillips i2c spec, there s/b a 0 ns hold time for sda - // with regards to scl. If the data changes coincident with the clock, the - // acknowledge is missed - // Fix by Michael Sosnoski - assign #1 sda_dly = sda; - - - //detect start condition - always @(negedge sda) - if(scl) - begin - sta <= #1 1'b1; - d_sta <= #1 1'b0; - sto <= #1 1'b0; - - if(debug) - $display("DEBUG i2c_slave; start condition detected at %t", $time); - end - else - sta <= #1 1'b0; - - always @(posedge scl) - d_sta <= #1 sta; - - // detect stop condition - always @(posedge sda) - if(scl) - begin - sta <= #1 1'b0; - sto <= #1 1'b1; - - if(debug) - $display("DEBUG i2c_slave; stop condition detected at %t", $time); - end - else - sto <= #1 1'b0; - - //generate i2c_reset signal - assign i2c_reset = sta || sto; - - // generate statemachine - always @(negedge scl or posedge sto) - if (sto || (sta && !d_sta) ) - begin - state <= #1 idle; // reset statemachine - - sda_o <= #1 1'b1; - ld <= #1 1'b1; - end - else - begin - // initial settings - sda_o <= #1 1'b1; - ld <= #1 1'b0; - - case(state) // synopsys full_case parallel_case - idle: // idle state - if (acc_done && my_adr) - begin - state <= #1 slave_ack; - rw <= #1 sr[0]; - sda_o <= #1 1'b0; // generate i2c_ack - - #2; - if(debug && rw) - $display("DEBUG i2c_slave; command byte received (read) at %t", $time); - if(debug && !rw) - $display("DEBUG i2c_slave; command byte received (write) at %t", $time); - - if(rw) - begin - mem_do <= #1 mem[mem_adr]; - - if(debug) - begin - #2 $display("DEBUG i2c_slave; data block read %x from address %x (1)", mem_do, mem_adr); - #2 $display("DEBUG i2c_slave; memcheck [0]=%x, [1]=%x, [2]=%x", mem[4'h0], mem[4'h1], mem[4'h2]); - end - end - end - - slave_ack: - begin - if(rw) - begin - state <= #1 data; - sda_o <= #1 mem_do[7]; - end - else - state <= #1 get_mem_adr; - - ld <= #1 1'b1; - end - - get_mem_adr: // wait for memory address - if(acc_done) - begin - state <= #1 gma_ack; - mem_adr <= #1 sr; // store memory address - sda_o <= #1 !(sr <= 15); // generate i2c_ack, for valid address - - if(debug) - #1 $display("DEBUG i2c_slave; address received. adr=%x, ack=%b", sr, sda_o); - end - - gma_ack: - begin - state <= #1 data; - ld <= #1 1'b1; - end - - data: // receive or drive data - begin - if(rw) - sda_o <= #1 mem_do[7]; - - if(acc_done) - begin - state <= #1 data_ack; - mem_adr <= #2 mem_adr + 8'h1; - sda_o <= #1 (rw && (mem_adr <= 15) ); // send ack on write, receive ack on read - - if(rw) - begin - #3 mem_do <= mem[mem_adr]; - - if(debug) - #5 $display("DEBUG i2c_slave; data block read %x from address %x (2)", mem_do, mem_adr); - end - - if(!rw) - begin - mem[ mem_adr[3:0] ] <= #1 sr; // store data in memory - - if(debug) - #2 $display("DEBUG i2c_slave; data block write %x to address %x", sr, mem_adr); - end - end - end - - data_ack: - begin - ld <= #1 1'b1; - - if(rw) - if(sr[0]) // read operation && master send NACK - begin - state <= #1 idle; - sda_o <= #1 1'b1; - end - else - begin - state <= #1 data; - sda_o <= #1 mem_do[7]; - end - else - begin - state <= #1 data; - sda_o <= #1 1'b1; - end - end - - endcase - end - - // read data from memory - always @(posedge scl) - if(!acc_done && rw) - mem_do <= #1 {mem_do[6:0], 1'b1}; // insert 1'b1 for host ack generation - - // generate tri-states - assign sda = sda_o ? 1'bz : 1'b0; - - - // - // Timing checks - // - - wire tst_sto = sto; - wire tst_sta = sta; - - specify - specparam normal_scl_low = 4700, - normal_scl_high = 4000, - normal_tsu_sta = 4700, - normal_thd_sta = 4000, - normal_tsu_sto = 4000, - normal_tbuf = 4700, - - fast_scl_low = 1300, - fast_scl_high = 600, - fast_tsu_sta = 1300, - fast_thd_sta = 600, - fast_tsu_sto = 600, - fast_tbuf = 1300; - - $width(negedge scl, normal_scl_low); // scl low time - $width(posedge scl, normal_scl_high); // scl high time - - $setup(posedge scl, negedge sda &&& scl, normal_tsu_sta); // setup start - $setup(negedge sda &&& scl, negedge scl, normal_thd_sta); // hold start - $setup(posedge scl, posedge sda &&& scl, normal_tsu_sto); // setup stop - - $setup(posedge tst_sta, posedge tst_sto, normal_tbuf); // stop to start time - endspecify - -endmodule - - diff --git a/fpga/usrp2/opencores/i2c/bench/verilog/spi_slave_model.v b/fpga/usrp2/opencores/i2c/bench/verilog/spi_slave_model.v deleted file mode 100644 index 7d2f436f9..000000000 --- a/fpga/usrp2/opencores/i2c/bench/verilog/spi_slave_model.v +++ /dev/null @@ -1,128 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// SPI Slave Model //// -//// //// -//// //// -//// Authors: Richard Herveille (richard@asics.ws) www.asics.ws //// -//// //// -//// http://www.opencores.org/projects/simple_spi/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2004 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: spi_slave_model.v,v 1.1 2004/02/28 15:32:54 rherveille Exp $ -// -// $Date: 2004/02/28 15:32:54 $ -// $Revision: 1.1 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: spi_slave_model.v,v $ -// Revision 1.1 2004/02/28 15:32:54 rherveille -// Added testbench -// -// -// - - -// Requires: Verilog2001 - -`include "timescale.v" - -module spi_slave_model ( - input wire csn; - input wire sck - input wire di; - output wire do -); - - // - // Variable declaration - // - wire debug = 1'b1; - - wire cpol = 1'b0; - wire cpha = 1'b0; - - reg [7:0] mem [7:0]; // initiate memory - reg [2:0] mem_adr; // memory address - reg [7:0] mem_do; // memory data output - - reg [7:0] sri, sro; // 8bit shift register - - reg [2:0] bit_cnt; - reg ld; - - wire clk; - - // - // module body - // - - assign clk = cpol ^ cpha ^ sck; - - // generate shift registers - always @(posedge clk) - sri <= #1 {sri[6:0],di}; - - always @(posedge clk) - if (&bit_cnt) - sro <= #1 mem[mem_adr]; - else - sro <= #1 {sro[6:0],1'bx}; - - assign do = sro[7]; - - //generate bit-counter - always @(posedge clk, posedge csn) - if(csn) - bit_cnt <= #1 3'b111; - else - bit_cnt <= #1 bit_cnt - 3'h1; - - //generate access done signal - always @(posedge clk) - ld <= #1 ~(|bit_cnt); - - always @(negedge clk) - if (ld) begin - mem[mem_adr] <= #1 sri; - mem_adr <= #1 mem_adr + 1'b1; - end - - initial - begin - bit_cnt=3'b111; - mem_adr = 0; - sro = mem[mem_adr]; - end -endmodule - - diff --git a/fpga/usrp2/opencores/i2c/bench/verilog/tst_bench_top.v b/fpga/usrp2/opencores/i2c/bench/verilog/tst_bench_top.v deleted file mode 100644 index 66284e4d4..000000000 --- a/fpga/usrp2/opencores/i2c/bench/verilog/tst_bench_top.v +++ /dev/null @@ -1,467 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE rev.B2 compliant I2C Master controller Testbench //// -//// //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -//// Downloaded from: http://www.opencores.org/projects/i2c/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: tst_bench_top.v,v 1.8 2006/09/04 09:08:51 rherveille Exp $ -// -// $Date: 2006/09/04 09:08:51 $ -// $Revision: 1.8 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: tst_bench_top.v,v $ -// Revision 1.8 2006/09/04 09:08:51 rherveille -// fixed (n)ack generation -// -// Revision 1.7 2005/02/27 09:24:18 rherveille -// Fixed scl, sda delay. -// -// Revision 1.6 2004/02/28 15:40:42 rherveille -// *** empty log message *** -// -// Revision 1.4 2003/12/05 11:04:38 rherveille -// Added slave address configurability -// -// Revision 1.3 2002/10/30 18:11:06 rherveille -// Added timing tests to i2c_model. -// Updated testbench. -// -// Revision 1.2 2002/03/17 10:26:38 rherveille -// Fixed some race conditions in the i2c-slave model. -// Added debug information. -// Added headers. -// - -`include "timescale.v" - -module tst_bench_top(); - - // - // wires && regs - // - reg clk; - reg rstn; - - wire [31:0] adr; - wire [ 7:0] dat_i, dat_o, dat0_i, dat1_i; - wire we; - wire stb; - wire cyc; - wire ack; - wire inta; - - reg [7:0] q, qq; - - wire scl, scl0_o, scl0_oen, scl1_o, scl1_oen; - wire sda, sda0_o, sda0_oen, sda1_o, sda1_oen; - - parameter PRER_LO = 3'b000; - parameter PRER_HI = 3'b001; - parameter CTR = 3'b010; - parameter RXR = 3'b011; - parameter TXR = 3'b011; - parameter CR = 3'b100; - parameter SR = 3'b100; - - parameter TXR_R = 3'b101; // undocumented / reserved output - parameter CR_R = 3'b110; // undocumented / reserved output - - parameter RD = 1'b1; - parameter WR = 1'b0; - parameter SADR = 7'b0010_000; - - // - // Module body - // - - // generate clock - always #5 clk = ~clk; - - // hookup wishbone master model - wb_master_model #(8, 32) u0 ( - .clk(clk), - .rst(rstn), - .adr(adr), - .din(dat_i), - .dout(dat_o), - .cyc(cyc), - .stb(stb), - .we(we), - .sel(), - .ack(ack), - .err(1'b0), - .rty(1'b0) - ); - - wire stb0 = stb & ~adr[3]; - wire stb1 = stb & adr[3]; - - assign dat_i = ({{8'd8}{stb0}} & dat0_i) | ({{8'd8}{stb1}} & dat1_i); - - // hookup wishbone_i2c_master core - i2c_master_top i2c_top ( - - // wishbone interface - .wb_clk_i(clk), - .wb_rst_i(1'b0), - .arst_i(rstn), - .wb_adr_i(adr[2:0]), - .wb_dat_i(dat_o), - .wb_dat_o(dat0_i), - .wb_we_i(we), - .wb_stb_i(stb0), - .wb_cyc_i(cyc), - .wb_ack_o(ack), - .wb_inta_o(inta), - - // i2c signals - .scl_pad_i(scl), - .scl_pad_o(scl0_o), - .scl_padoen_o(scl0_oen), - .sda_pad_i(sda), - .sda_pad_o(sda0_o), - .sda_padoen_o(sda0_oen) - ), - i2c_top2 ( - - // wishbone interface - .wb_clk_i(clk), - .wb_rst_i(1'b0), - .arst_i(rstn), - .wb_adr_i(adr[2:0]), - .wb_dat_i(dat_o), - .wb_dat_o(dat1_i), - .wb_we_i(we), - .wb_stb_i(stb1), - .wb_cyc_i(cyc), - .wb_ack_o(ack), - .wb_inta_o(inta), - - // i2c signals - .scl_pad_i(scl), - .scl_pad_o(scl1_o), - .scl_padoen_o(scl1_oen), - .sda_pad_i(sda), - .sda_pad_o(sda1_o), - .sda_padoen_o(sda1_oen) - ); - - - // hookup i2c slave model - i2c_slave_model #(SADR) i2c_slave ( - .scl(scl), - .sda(sda) - ); - - // create i2c lines - delay m0_scl (scl0_oen ? 1'bz : scl0_o, scl), - m1_scl (scl1_oen ? 1'bz : scl1_o, scl), - m0_sda (sda0_oen ? 1'bz : sda0_o, sda), - m1_sda (sda1_oen ? 1'bz : sda1_o, sda); - - pullup p1(scl); // pullup scl line - pullup p2(sda); // pullup sda line - - initial - begin - `ifdef WAVES - $shm_open("waves"); - $shm_probe("AS",tst_bench_top,"AS"); - $display("INFO: Signal dump enabled ...\n\n"); - `endif - -// force i2c_slave.debug = 1'b1; // enable i2c_slave debug information - force i2c_slave.debug = 1'b0; // disable i2c_slave debug information - - $display("\nstatus: %t Testbench started\n\n", $time); - -// $dumpfile("bench.vcd"); -// $dumpvars(1, tst_bench_top); -// $dumpvars(1, tst_bench_top.i2c_slave); - - // initially values - clk = 0; - - // reset system - rstn = 1'b1; // negate reset - #2; - rstn = 1'b0; // assert reset - repeat(1) @(posedge clk); - rstn = 1'b1; // negate reset - - $display("status: %t done reset", $time); - - @(posedge clk); - - // - // program core - // - - // program internal registers - u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte - u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte - u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte - $display("status: %t programmed registers", $time); - - u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte - u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte - $display("status: %t verified registers", $time); - - u0.wb_write(1, CTR, 8'h80); // enable core - $display("status: %t core enabled", $time); - - // - // access slave (write) - // - - // drive slave address - u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit - u0.wb_write(0, CR, 8'h90 ); // set command (start, write) - $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} ); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(0, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // send memory address - u0.wb_write(1, TXR, 8'h01); // present slave's memory address - u0.wb_write(0, CR, 8'h10); // set command (write) - $display("status: %t write slave memory address 01", $time); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(0, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // send memory contents - u0.wb_write(1, TXR, 8'ha5); // present data - u0.wb_write(0, CR, 8'h10); // set command (write) - $display("status: %t write data a5", $time); - -while (scl) #1; -force scl= 1'b0; -#100000; -release scl; - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // send memory contents for next memory address (auto_inc) - u0.wb_write(1, TXR, 8'h5a); // present data - u0.wb_write(0, CR, 8'h50); // set command (stop, write) - $display("status: %t write next data 5a, generate 'stop'", $time); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // - // delay - // -// #100000; // wait for 100us. -// $display("status: %t wait 100us", $time); - - // - // access slave (read) - // - - // drive slave address - u0.wb_write(1, TXR,{SADR,WR} ); // present slave address, set write-bit - u0.wb_write(0, CR, 8'h90 ); // set command (start, write) - $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} ); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // send memory address - u0.wb_write(1, TXR, 8'h01); // present slave's memory address - u0.wb_write(0, CR, 8'h10); // set command (write) - $display("status: %t write slave address 01", $time); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // drive slave address - u0.wb_write(1, TXR, {SADR,RD} ); // present slave's address, set read-bit - u0.wb_write(0, CR, 8'h90 ); // set command (start, write) - $display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,RD} ); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // read data from slave - u0.wb_write(1, CR, 8'h20); // set command (read, ack_read) - $display("status: %t read + ack", $time); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // check data just received - u0.wb_read(1, RXR, qq); - if(qq !== 8'ha5) - $display("\nERROR: Expected a5, received %x at time %t", qq, $time); - else - $display("status: %t received %x", $time, qq); - - // read data from slave - u0.wb_write(1, CR, 8'h20); // set command (read, ack_read) - $display("status: %t read + ack", $time); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // check data just received - u0.wb_read(1, RXR, qq); - if(qq !== 8'h5a) - $display("\nERROR: Expected 5a, received %x at time %t", qq, $time); - else - $display("status: %t received %x", $time, qq); - - // read data from slave - u0.wb_write(1, CR, 8'h20); // set command (read, ack_read) - $display("status: %t read + ack", $time); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // check data just received - u0.wb_read(1, RXR, qq); - $display("status: %t received %x from 3rd read address", $time, qq); - - // read data from slave - u0.wb_write(1, CR, 8'h28); // set command (read, nack_read) - $display("status: %t read + nack", $time); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // check data just received - u0.wb_read(1, RXR, qq); - $display("status: %t received %x from 4th read address", $time, qq); - - // - // check invalid slave memory address - // - - // drive slave address - u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit - u0.wb_write(0, CR, 8'h90 ); // set command (start, write) - $display("status: %t generate 'start', write cmd %0h (slave address+write). Check invalid address", $time, {SADR,WR} ); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // send memory address - u0.wb_write(1, TXR, 8'h10); // present slave's memory address - u0.wb_write(0, CR, 8'h10); // set command (write) - $display("status: %t write slave memory address 10", $time); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // slave should have send NACK - $display("status: %t Check for nack", $time); - if(!q[7]) - $display("\nERROR: Expected NACK, received ACK\n"); - - // read data from slave - u0.wb_write(1, CR, 8'h40); // set command (stop) - $display("status: %t generate 'stop'", $time); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - #250000; // wait 250us - $display("\n\nstatus: %t Testbench done", $time); - $finish; - end - -endmodule - -module delay (in, out); - input in; - output out; - - assign out = in; - - specify - (in => out) = (600,600); - endspecify -endmodule - - diff --git a/fpga/usrp2/opencores/i2c/bench/verilog/wb_master_model.v b/fpga/usrp2/opencores/i2c/bench/verilog/wb_master_model.v deleted file mode 100644 index 14ed6cbf5..000000000 --- a/fpga/usrp2/opencores/i2c/bench/verilog/wb_master_model.v +++ /dev/null @@ -1,205 +0,0 @@ -/////////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE rev.B2 Wishbone Master model //// -//// //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -//// Downloaded from: http://www.opencores.org/projects/mem_ctrl //// -//// //// -/////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -/////////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_master_model.v,v 1.4 2004/02/28 15:40:42 rherveille Exp $ -// -// $Date: 2004/02/28 15:40:42 $ -// $Revision: 1.4 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// -`include "timescale.v" - -module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty); - -parameter dwidth = 32; -parameter awidth = 32; - -input clk, rst; -output [awidth -1:0] adr; -input [dwidth -1:0] din; -output [dwidth -1:0] dout; -output cyc, stb; -output we; -output [dwidth/8 -1:0] sel; -input ack, err, rty; - -//////////////////////////////////////////////////////////////////// -// -// Local Wires -// - -reg [awidth -1:0] adr; -reg [dwidth -1:0] dout; -reg cyc, stb; -reg we; -reg [dwidth/8 -1:0] sel; - -reg [dwidth -1:0] q; - -//////////////////////////////////////////////////////////////////// -// -// Memory Logic -// - -initial - begin - //adr = 32'hxxxx_xxxx; - //adr = 0; - adr = {awidth{1'bx}}; - dout = {dwidth{1'bx}}; - cyc = 1'b0; - stb = 1'bx; - we = 1'hx; - sel = {dwidth/8{1'bx}}; - #1; - $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n"); - end - -//////////////////////////////////////////////////////////////////// -// -// Wishbone write cycle -// - -task wb_write; - input delay; - integer delay; - - input [awidth -1:0] a; - input [dwidth -1:0] d; - - begin - - // wait initial delay - repeat(delay) @(posedge clk); - - // assert wishbone signal - #1; - adr = a; - dout = d; - cyc = 1'b1; - stb = 1'b1; - we = 1'b1; - sel = {dwidth/8{1'b1}}; - @(posedge clk); - - // wait for acknowledge from slave - while(~ack) @(posedge clk); - - // negate wishbone signals - #1; - cyc = 1'b0; - stb = 1'bx; - adr = {awidth{1'bx}}; - dout = {dwidth{1'bx}}; - we = 1'hx; - sel = {dwidth/8{1'bx}}; - - end -endtask - -//////////////////////////////////////////////////////////////////// -// -// Wishbone read cycle -// - -task wb_read; - input delay; - integer delay; - - input [awidth -1:0] a; - output [dwidth -1:0] d; - - begin - - // wait initial delay - repeat(delay) @(posedge clk); - - // assert wishbone signals - #1; - adr = a; - dout = {dwidth{1'bx}}; - cyc = 1'b1; - stb = 1'b1; - we = 1'b0; - sel = {dwidth/8{1'b1}}; - @(posedge clk); - - // wait for acknowledge from slave - while(~ack) @(posedge clk); - - // negate wishbone signals - #1; - cyc = 1'b0; - stb = 1'bx; - adr = {awidth{1'bx}}; - dout = {dwidth{1'bx}}; - we = 1'hx; - sel = {dwidth/8{1'bx}}; - d = din; - - end -endtask - -//////////////////////////////////////////////////////////////////// -// -// Wishbone compare cycle (read data from location and compare with expected data) -// - -task wb_cmp; - input delay; - integer delay; - - input [awidth -1:0] a; - input [dwidth -1:0] d_exp; - - begin - wb_read (delay, a, q); - - if (d_exp !== q) - $display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time); - end -endtask - -endmodule - - diff --git a/fpga/usrp2/opencores/i2c/doc/i2c_specs.pdf b/fpga/usrp2/opencores/i2c/doc/i2c_specs.pdf deleted file mode 100644 index 72021df11..000000000 Binary files a/fpga/usrp2/opencores/i2c/doc/i2c_specs.pdf and /dev/null differ diff --git a/fpga/usrp2/opencores/i2c/doc/src/I2C_specs.doc b/fpga/usrp2/opencores/i2c/doc/src/I2C_specs.doc deleted file mode 100644 index 31ab2684f..000000000 Binary files a/fpga/usrp2/opencores/i2c/doc/src/I2C_specs.doc and /dev/null differ diff --git a/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v b/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v deleted file mode 100644 index edab94f61..000000000 --- a/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v +++ /dev/null @@ -1,538 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE rev.B2 compliant I2C Master bit-controller //// -//// //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -//// Downloaded from: http://www.opencores.org/projects/i2c/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: i2c_master_bit_ctrl.v,v 1.12 2006/09/04 09:08:13 rherveille Exp $ -// -// $Date: 2006/09/04 09:08:13 $ -// $Revision: 1.12 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: i2c_master_bit_ctrl.v,v $ -// Revision 1.12 2006/09/04 09:08:13 rherveille -// fixed short scl high pulse after clock stretch -// fixed slave model not returning correct '(n)ack' signal -// -// Revision 1.11 2004/05/07 11:02:26 rherveille -// Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. -// -// Revision 1.10 2003/08/09 07:01:33 rherveille -// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. -// Fixed a potential bug in the byte controller's host-acknowledge generation. -// -// Revision 1.9 2003/03/10 14:26:37 rherveille -// Fixed cmd_ack generation item (no bug). -// -// Revision 1.8 2003/02/05 00:06:10 rherveille -// Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. -// -// Revision 1.7 2002/12/26 16:05:12 rherveille -// Small code simplifications -// -// Revision 1.6 2002/12/26 15:02:32 rherveille -// Core is now a Multimaster I2C controller -// -// Revision 1.5 2002/11/30 22:24:40 rherveille -// Cleaned up code -// -// Revision 1.4 2002/10/30 18:10:07 rherveille -// Fixed some reported minor start/stop generation timing issuess. -// -// Revision 1.3 2002/06/15 07:37:03 rherveille -// Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. -// -// Revision 1.2 2001/11/05 11:59:25 rherveille -// Fixed wb_ack_o generation bug. -// Fixed bug in the byte_controller statemachine. -// Added headers. -// - -// -///////////////////////////////////// -// Bit controller section -///////////////////////////////////// -// -// Translate simple commands into SCL/SDA transitions -// Each command has 5 states, A/B/C/D/idle -// -// start: SCL ~~~~~~~~~~\____ -// SDA ~~~~~~~~\______ -// x | A | B | C | D | i -// -// repstart SCL ____/~~~~\___ -// SDA __/~~~\______ -// x | A | B | C | D | i -// -// stop SCL ____/~~~~~~~~ -// SDA ==\____/~~~~~ -// x | A | B | C | D | i -// -//- write SCL ____/~~~~\____ -// SDA ==X=========X= -// x | A | B | C | D | i -// -//- read SCL ____/~~~~\____ -// SDA XXXX=====XXXX -// x | A | B | C | D | i -// - -// Timing: Normal mode Fast mode -/////////////////////////////////////////////////////////////////////// -// Fscl 100KHz 400KHz -// Th_scl 4.0us 0.6us High period of SCL -// Tl_scl 4.7us 1.3us Low period of SCL -// Tsu:sta 4.7us 0.6us setup time for a repeated start condition -// Tsu:sto 4.0us 0.6us setup time for a stop conditon -// Tbuf 4.7us 1.3us Bus free time between a stop and start condition -// - -// synopsys translate_off -`include "timescale.v" -// synopsys translate_on - -`include "i2c_master_defines.v" - -module i2c_master_bit_ctrl( - clk, rst, nReset, - clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout, - scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen - ); - - // - // inputs & outputs - // - input clk; - input rst; - input nReset; - input ena; // core enable signal - - input [15:0] clk_cnt; // clock prescale value - - input [3:0] cmd; - output cmd_ack; // command complete acknowledge - reg cmd_ack; - output busy; // i2c bus busy - reg busy; - output al; // i2c bus arbitration lost - reg al; - - input din; - output dout; - reg dout; - - // I2C lines - input scl_i; // i2c clock line input - output scl_o; // i2c clock line output - output scl_oen; // i2c clock line output enable (active low) - reg scl_oen; - input sda_i; // i2c data line input - output sda_o; // i2c data line output - output sda_oen; // i2c data line output enable (active low) - reg sda_oen; - - - // - // variable declarations - // - - reg sSCL, sSDA; // synchronized SCL and SDA inputs - reg dscl_oen; // delayed scl_oen - reg sda_chk; // check SDA output (Multi-master arbitration) - reg clk_en; // clock generation signals - wire slave_wait; -// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation) - reg [15:0] cnt; // clock divider counter (synthesis) - - // state machine variable - reg [16:0] c_state; // synopsys enum_state - - // - // module body - // - - // whenever the slave is not ready it can delay the cycle by pulling SCL low - // delay scl_oen - always @(posedge clk) - dscl_oen <= #1 scl_oen; - - assign slave_wait = dscl_oen && !sSCL; - - - // generate clk enable signal - always @(posedge clk or negedge nReset) - if(~nReset) - begin - cnt <= #1 16'h0; - clk_en <= #1 1'b1; - end - else if (rst) - begin - cnt <= #1 16'h0; - clk_en <= #1 1'b1; - end - else if ( ~|cnt || !ena) - begin - cnt <= #1 clk_cnt; - clk_en <= #1 1'b1; - end - else if (slave_wait) - begin - cnt <= #1 cnt; - clk_en <= #1 1'b0; - end - else - begin - cnt <= #1 cnt - 16'h1; - clk_en <= #1 1'b0; - end - - - // generate bus status controller - reg dSCL, dSDA; - reg sta_condition; - reg sto_condition; - - // synchronize SCL and SDA inputs - // reduce metastability risc - always @(posedge clk or negedge nReset) - if (~nReset) - begin - sSCL <= #1 1'b1; - sSDA <= #1 1'b1; - - dSCL <= #1 1'b1; - dSDA <= #1 1'b1; - end - else if (rst) - begin - sSCL <= #1 1'b1; - sSDA <= #1 1'b1; - - dSCL <= #1 1'b1; - dSDA <= #1 1'b1; - end - else - begin - sSCL <= #1 scl_i; - sSDA <= #1 sda_i; - - dSCL <= #1 sSCL; - dSDA <= #1 sSDA; - end - - // detect start condition => detect falling edge on SDA while SCL is high - // detect stop condition => detect rising edge on SDA while SCL is high - always @(posedge clk or negedge nReset) - if (~nReset) - begin - sta_condition <= #1 1'b0; - sto_condition <= #1 1'b0; - end - else if (rst) - begin - sta_condition <= #1 1'b0; - sto_condition <= #1 1'b0; - end - else - begin - sta_condition <= #1 ~sSDA & dSDA & sSCL; - sto_condition <= #1 sSDA & ~dSDA & sSCL; - end - - // generate i2c bus busy signal - always @(posedge clk or negedge nReset) - if(!nReset) - busy <= #1 1'b0; - else if (rst) - busy <= #1 1'b0; - else - busy <= #1 (sta_condition | busy) & ~sto_condition; - - // generate arbitration lost signal - // aribitration lost when: - // 1) master drives SDA high, but the i2c bus is low - // 2) stop detected while not requested - reg cmd_stop; - always @(posedge clk or negedge nReset) - if (~nReset) - cmd_stop <= #1 1'b0; - else if (rst) - cmd_stop <= #1 1'b0; - else if (clk_en) - cmd_stop <= #1 cmd == `I2C_CMD_STOP; - - always @(posedge clk or negedge nReset) - if (~nReset) - al <= #1 1'b0; - else if (rst) - al <= #1 1'b0; - else - al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop); - - - // generate dout signal (store SDA on rising edge of SCL) - always @(posedge clk) - if(sSCL & ~dSCL) - dout <= #1 sSDA; - - // generate statemachine - - // nxt_state decoder - parameter [16:0] idle = 17'b0_0000_0000_0000_0000; - parameter [16:0] start_a = 17'b0_0000_0000_0000_0001; - parameter [16:0] start_b = 17'b0_0000_0000_0000_0010; - parameter [16:0] start_c = 17'b0_0000_0000_0000_0100; - parameter [16:0] start_d = 17'b0_0000_0000_0000_1000; - parameter [16:0] start_e = 17'b0_0000_0000_0001_0000; - parameter [16:0] stop_a = 17'b0_0000_0000_0010_0000; - parameter [16:0] stop_b = 17'b0_0000_0000_0100_0000; - parameter [16:0] stop_c = 17'b0_0000_0000_1000_0000; - parameter [16:0] stop_d = 17'b0_0000_0001_0000_0000; - parameter [16:0] rd_a = 17'b0_0000_0010_0000_0000; - parameter [16:0] rd_b = 17'b0_0000_0100_0000_0000; - parameter [16:0] rd_c = 17'b0_0000_1000_0000_0000; - parameter [16:0] rd_d = 17'b0_0001_0000_0000_0000; - parameter [16:0] wr_a = 17'b0_0010_0000_0000_0000; - parameter [16:0] wr_b = 17'b0_0100_0000_0000_0000; - parameter [16:0] wr_c = 17'b0_1000_0000_0000_0000; - parameter [16:0] wr_d = 17'b1_0000_0000_0000_0000; - - always @(posedge clk or negedge nReset) - if (!nReset) - begin - c_state <= #1 idle; - cmd_ack <= #1 1'b0; - scl_oen <= #1 1'b1; - sda_oen <= #1 1'b1; - sda_chk <= #1 1'b0; - end - else if (rst | al) - begin - c_state <= #1 idle; - cmd_ack <= #1 1'b0; - scl_oen <= #1 1'b1; - sda_oen <= #1 1'b1; - sda_chk <= #1 1'b0; - end - else - begin - cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle - - if (clk_en) - case (c_state) // synopsys full_case parallel_case - // idle state - idle: - begin - case (cmd) // synopsys full_case parallel_case - `I2C_CMD_START: - c_state <= #1 start_a; - - `I2C_CMD_STOP: - c_state <= #1 stop_a; - - `I2C_CMD_WRITE: - c_state <= #1 wr_a; - - `I2C_CMD_READ: - c_state <= #1 rd_a; - - default: - c_state <= #1 idle; - endcase - - scl_oen <= #1 scl_oen; // keep SCL in same state - sda_oen <= #1 sda_oen; // keep SDA in same state - sda_chk <= #1 1'b0; // don't check SDA output - end - - // start - start_a: - begin - c_state <= #1 start_b; - scl_oen <= #1 scl_oen; // keep SCL in same state - sda_oen <= #1 1'b1; // set SDA high - sda_chk <= #1 1'b0; // don't check SDA output - end - - start_b: - begin - c_state <= #1 start_c; - scl_oen <= #1 1'b1; // set SCL high - sda_oen <= #1 1'b1; // keep SDA high - sda_chk <= #1 1'b0; // don't check SDA output - end - - start_c: - begin - c_state <= #1 start_d; - scl_oen <= #1 1'b1; // keep SCL high - sda_oen <= #1 1'b0; // set SDA low - sda_chk <= #1 1'b0; // don't check SDA output - end - - start_d: - begin - c_state <= #1 start_e; - scl_oen <= #1 1'b1; // keep SCL high - sda_oen <= #1 1'b0; // keep SDA low - sda_chk <= #1 1'b0; // don't check SDA output - end - - start_e: - begin - c_state <= #1 idle; - cmd_ack <= #1 1'b1; - scl_oen <= #1 1'b0; // set SCL low - sda_oen <= #1 1'b0; // keep SDA low - sda_chk <= #1 1'b0; // don't check SDA output - end - - // stop - stop_a: - begin - c_state <= #1 stop_b; - scl_oen <= #1 1'b0; // keep SCL low - sda_oen <= #1 1'b0; // set SDA low - sda_chk <= #1 1'b0; // don't check SDA output - end - - stop_b: - begin - c_state <= #1 stop_c; - scl_oen <= #1 1'b1; // set SCL high - sda_oen <= #1 1'b0; // keep SDA low - sda_chk <= #1 1'b0; // don't check SDA output - end - - stop_c: - begin - c_state <= #1 stop_d; - scl_oen <= #1 1'b1; // keep SCL high - sda_oen <= #1 1'b0; // keep SDA low - sda_chk <= #1 1'b0; // don't check SDA output - end - - stop_d: - begin - c_state <= #1 idle; - cmd_ack <= #1 1'b1; - scl_oen <= #1 1'b1; // keep SCL high - sda_oen <= #1 1'b1; // set SDA high - sda_chk <= #1 1'b0; // don't check SDA output - end - - // read - rd_a: - begin - c_state <= #1 rd_b; - scl_oen <= #1 1'b0; // keep SCL low - sda_oen <= #1 1'b1; // tri-state SDA - sda_chk <= #1 1'b0; // don't check SDA output - end - - rd_b: - begin - c_state <= #1 rd_c; - scl_oen <= #1 1'b1; // set SCL high - sda_oen <= #1 1'b1; // keep SDA tri-stated - sda_chk <= #1 1'b0; // don't check SDA output - end - - rd_c: - begin - c_state <= #1 rd_d; - scl_oen <= #1 1'b1; // keep SCL high - sda_oen <= #1 1'b1; // keep SDA tri-stated - sda_chk <= #1 1'b0; // don't check SDA output - end - - rd_d: - begin - c_state <= #1 idle; - cmd_ack <= #1 1'b1; - scl_oen <= #1 1'b0; // set SCL low - sda_oen <= #1 1'b1; // keep SDA tri-stated - sda_chk <= #1 1'b0; // don't check SDA output - end - - // write - wr_a: - begin - c_state <= #1 wr_b; - scl_oen <= #1 1'b0; // keep SCL low - sda_oen <= #1 din; // set SDA - sda_chk <= #1 1'b0; // don't check SDA output (SCL low) - end - - wr_b: - begin - c_state <= #1 wr_c; - scl_oen <= #1 1'b1; // set SCL high - sda_oen <= #1 din; // keep SDA - sda_chk <= #1 1'b1; // check SDA output - end - - wr_c: - begin - c_state <= #1 wr_d; - scl_oen <= #1 1'b1; // keep SCL high - sda_oen <= #1 din; - sda_chk <= #1 1'b1; // check SDA output - end - - wr_d: - begin - c_state <= #1 idle; - cmd_ack <= #1 1'b1; - scl_oen <= #1 1'b0; // set SCL low - sda_oen <= #1 din; - sda_chk <= #1 1'b0; // don't check SDA output (SCL low) - end - - endcase - end - - - // assign scl and sda output (always gnd) - assign scl_o = 1'b0; - assign sda_o = 1'b0; - -endmodule diff --git a/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v b/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v deleted file mode 100644 index d091d1e36..000000000 --- a/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v +++ /dev/null @@ -1,344 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE rev.B2 compliant I2C Master byte-controller //// -//// //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -//// Downloaded from: http://www.opencores.org/projects/i2c/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: i2c_master_byte_ctrl.v,v 1.7 2004/02/18 11:40:46 rherveille Exp $ -// -// $Date: 2004/02/18 11:40:46 $ -// $Revision: 1.7 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: i2c_master_byte_ctrl.v,v $ -// Revision 1.7 2004/02/18 11:40:46 rherveille -// Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. -// -// Revision 1.6 2003/08/09 07:01:33 rherveille -// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. -// Fixed a potential bug in the byte controller's host-acknowledge generation. -// -// Revision 1.5 2002/12/26 15:02:32 rherveille -// Core is now a Multimaster I2C controller -// -// Revision 1.4 2002/11/30 22:24:40 rherveille -// Cleaned up code -// -// Revision 1.3 2001/11/05 11:59:25 rherveille -// Fixed wb_ack_o generation bug. -// Fixed bug in the byte_controller statemachine. -// Added headers. -// - -// synopsys translate_off -`include "timescale.v" -// synopsys translate_on - -`include "i2c_master_defines.v" - -module i2c_master_byte_ctrl ( - clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din, - cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen ); - - // - // inputs & outputs - // - input clk; // master clock - input rst; // synchronous active high reset - input nReset; // asynchronous active low reset - input ena; // core enable signal - - input [15:0] clk_cnt; // 4x SCL - - // control inputs - input start; - input stop; - input read; - input write; - input ack_in; - input [7:0] din; - - // status outputs - output cmd_ack; - reg cmd_ack; - output ack_out; - reg ack_out; - output i2c_busy; - output i2c_al; - output [7:0] dout; - - // I2C signals - input scl_i; - output scl_o; - output scl_oen; - input sda_i; - output sda_o; - output sda_oen; - - - // - // Variable declarations - // - - // statemachine - parameter [4:0] ST_IDLE = 5'b0_0000; - parameter [4:0] ST_START = 5'b0_0001; - parameter [4:0] ST_READ = 5'b0_0010; - parameter [4:0] ST_WRITE = 5'b0_0100; - parameter [4:0] ST_ACK = 5'b0_1000; - parameter [4:0] ST_STOP = 5'b1_0000; - - // signals for bit_controller - reg [3:0] core_cmd; - reg core_txd; - wire core_ack, core_rxd; - - // signals for shift register - reg [7:0] sr; //8bit shift register - reg shift, ld; - - // signals for state machine - wire go; - reg [2:0] dcnt; - wire cnt_done; - - // - // Module body - // - - // hookup bit_controller - i2c_master_bit_ctrl bit_controller ( - .clk ( clk ), - .rst ( rst ), - .nReset ( nReset ), - .ena ( ena ), - .clk_cnt ( clk_cnt ), - .cmd ( core_cmd ), - .cmd_ack ( core_ack ), - .busy ( i2c_busy ), - .al ( i2c_al ), - .din ( core_txd ), - .dout ( core_rxd ), - .scl_i ( scl_i ), - .scl_o ( scl_o ), - .scl_oen ( scl_oen ), - .sda_i ( sda_i ), - .sda_o ( sda_o ), - .sda_oen ( sda_oen ) - ); - - // generate go-signal - assign go = (read | write | stop) & ~cmd_ack; - - // assign dout output to shift-register - assign dout = sr; - - // generate shift register - always @(posedge clk or negedge nReset) - if (!nReset) - sr <= #1 8'h0; - else if (rst) - sr <= #1 8'h0; - else if (ld) - sr <= #1 din; - else if (shift) - sr <= #1 {sr[6:0], core_rxd}; - - // generate counter - always @(posedge clk or negedge nReset) - if (!nReset) - dcnt <= #1 3'h0; - else if (rst) - dcnt <= #1 3'h0; - else if (ld) - dcnt <= #1 3'h7; - else if (shift) - dcnt <= #1 dcnt - 3'h1; - - assign cnt_done = ~(|dcnt); - - // - // state machine - // - reg [4:0] c_state; // synopsis enum_state - - always @(posedge clk or negedge nReset) - if (!nReset) - begin - core_cmd <= #1 `I2C_CMD_NOP; - core_txd <= #1 1'b0; - shift <= #1 1'b0; - ld <= #1 1'b0; - cmd_ack <= #1 1'b0; - c_state <= #1 ST_IDLE; - ack_out <= #1 1'b0; - end - else if (rst | i2c_al) - begin - core_cmd <= #1 `I2C_CMD_NOP; - core_txd <= #1 1'b0; - shift <= #1 1'b0; - ld <= #1 1'b0; - cmd_ack <= #1 1'b0; - c_state <= #1 ST_IDLE; - ack_out <= #1 1'b0; - end - else - begin - // initially reset all signals - core_txd <= #1 sr[7]; - shift <= #1 1'b0; - ld <= #1 1'b0; - cmd_ack <= #1 1'b0; - - case (c_state) // synopsys full_case parallel_case - ST_IDLE: - if (go) - begin - if (start) - begin - c_state <= #1 ST_START; - core_cmd <= #1 `I2C_CMD_START; - end - else if (read) - begin - c_state <= #1 ST_READ; - core_cmd <= #1 `I2C_CMD_READ; - end - else if (write) - begin - c_state <= #1 ST_WRITE; - core_cmd <= #1 `I2C_CMD_WRITE; - end - else // stop - begin - c_state <= #1 ST_STOP; - core_cmd <= #1 `I2C_CMD_STOP; - end - - ld <= #1 1'b1; - end - - ST_START: - if (core_ack) - begin - if (read) - begin - c_state <= #1 ST_READ; - core_cmd <= #1 `I2C_CMD_READ; - end - else - begin - c_state <= #1 ST_WRITE; - core_cmd <= #1 `I2C_CMD_WRITE; - end - - ld <= #1 1'b1; - end - - ST_WRITE: - if (core_ack) - if (cnt_done) - begin - c_state <= #1 ST_ACK; - core_cmd <= #1 `I2C_CMD_READ; - end - else - begin - c_state <= #1 ST_WRITE; // stay in same state - core_cmd <= #1 `I2C_CMD_WRITE; // write next bit - shift <= #1 1'b1; - end - - ST_READ: - if (core_ack) - begin - if (cnt_done) - begin - c_state <= #1 ST_ACK; - core_cmd <= #1 `I2C_CMD_WRITE; - end - else - begin - c_state <= #1 ST_READ; // stay in same state - core_cmd <= #1 `I2C_CMD_READ; // read next bit - end - - shift <= #1 1'b1; - core_txd <= #1 ack_in; - end - - ST_ACK: - if (core_ack) - begin - if (stop) - begin - c_state <= #1 ST_STOP; - core_cmd <= #1 `I2C_CMD_STOP; - end - else - begin - c_state <= #1 ST_IDLE; - core_cmd <= #1 `I2C_CMD_NOP; - - // generate command acknowledge signal - cmd_ack <= #1 1'b1; - end - - // assign ack_out output to bit_controller_rxd (contains last received bit) - ack_out <= #1 core_rxd; - - core_txd <= #1 1'b1; - end - else - core_txd <= #1 ack_in; - - ST_STOP: - if (core_ack) - begin - c_state <= #1 ST_IDLE; - core_cmd <= #1 `I2C_CMD_NOP; - - // generate command acknowledge signal - cmd_ack <= #1 1'b1; - end - - endcase - end -endmodule diff --git a/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v b/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v deleted file mode 100644 index ee3b694fa..000000000 --- a/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v +++ /dev/null @@ -1,64 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE rev.B2 compliant I2C Master controller defines //// -//// //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -//// Downloaded from: http://www.opencores.org/projects/i2c/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: i2c_master_defines.v,v 1.3 2001/11/05 11:59:25 rherveille Exp $ -// -// $Date: 2001/11/05 11:59:25 $ -// $Revision: 1.3 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: i2c_master_defines.v,v $ -// Revision 1.3 2001/11/05 11:59:25 rherveille -// Fixed wb_ack_o generation bug. -// Fixed bug in the byte_controller statemachine. -// Added headers. -// - - -// I2C registers wishbone addresses - -// bitcontroller states -`define I2C_CMD_NOP 4'b0000 -`define I2C_CMD_START 4'b0001 -`define I2C_CMD_STOP 4'b0010 -`define I2C_CMD_WRITE 4'b0100 -`define I2C_CMD_READ 4'b1000 diff --git a/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v b/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v deleted file mode 100644 index 30689bd70..000000000 --- a/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v +++ /dev/null @@ -1,301 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE revB.2 compliant I2C Master controller Top-level //// -//// //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -//// Downloaded from: http://www.opencores.org/projects/i2c/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: i2c_master_top.v,v 1.11 2005/02/27 09:26:24 rherveille Exp $ -// -// $Date: 2005/02/27 09:26:24 $ -// $Revision: 1.11 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: i2c_master_top.v,v $ -// Revision 1.11 2005/02/27 09:26:24 rherveille -// Fixed register overwrite issue. -// Removed full_case pragma, replaced it by a default statement. -// -// Revision 1.10 2003/09/01 10:34:38 rherveille -// Fix a blocking vs. non-blocking error in the wb_dat output mux. -// -// Revision 1.9 2003/01/09 16:44:45 rherveille -// Fixed a bug in the Command Register declaration. -// -// Revision 1.8 2002/12/26 16:05:12 rherveille -// Small code simplifications -// -// Revision 1.7 2002/12/26 15:02:32 rherveille -// Core is now a Multimaster I2C controller -// -// Revision 1.6 2002/11/30 22:24:40 rherveille -// Cleaned up code -// -// Revision 1.5 2001/11/10 10:52:55 rherveille -// Changed PRER reset value from 0x0000 to 0xffff, conform specs. -// - -// synopsys translate_off -`include "timescale.v" -// synopsys translate_on - -`include "i2c_master_defines.v" - -module i2c_master_top( - wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o, - wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o, - scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o ); - - // parameters - parameter ARST_LVL = 1'b0; // asynchronous reset level - - // - // inputs & outputs - // - - // wishbone signals - input wb_clk_i; // master clock input - input wb_rst_i; // synchronous active high reset - input arst_i; // asynchronous reset - input [2:0] wb_adr_i; // lower address bits - input [7:0] wb_dat_i; // databus input - output [7:0] wb_dat_o; // databus output - input wb_we_i; // write enable input - input wb_stb_i; // stobe/core select signal - input wb_cyc_i; // valid bus cycle input - output wb_ack_o; // bus cycle acknowledge output - output wb_inta_o; // interrupt request signal output - - reg [7:0] wb_dat_o; - reg wb_ack_o; - reg wb_inta_o; - - // I2C signals - // i2c clock line - input scl_pad_i; // SCL-line input - output scl_pad_o; // SCL-line output (always 1'b0) - output scl_padoen_o; // SCL-line output enable (active low) - - // i2c data line - input sda_pad_i; // SDA-line input - output sda_pad_o; // SDA-line output (always 1'b0) - output sda_padoen_o; // SDA-line output enable (active low) - - - // - // variable declarations - // - - // registers - reg [15:0] prer; // clock prescale register - reg [ 7:0] ctr; // control register - reg [ 7:0] txr; // transmit register - wire [ 7:0] rxr; // receive register - reg [ 7:0] cr; // command register - wire [ 7:0] sr; // status register - - // done signal: command completed, clear command register - wire done; - - // core enable signal - wire core_en; - wire ien; - - // status register signals - wire irxack; - reg rxack; // received aknowledge from slave - reg tip; // transfer in progress - reg irq_flag; // interrupt pending flag - wire i2c_busy; // bus busy (start signal detected) - wire i2c_al; // i2c bus arbitration lost - reg al; // status register arbitration lost bit - - // - // module body - // - - // generate internal reset - wire rst_i = arst_i ^ ARST_LVL; - - // generate wishbone signals - wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i; - - // generate acknowledge output signal - always @(posedge wb_clk_i) - wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored - - // assign DAT_O - always @(posedge wb_clk_i) - begin - case (wb_adr_i) // synopsis parallel_case - 3'b000: wb_dat_o <= #1 prer[ 7:0]; - 3'b001: wb_dat_o <= #1 prer[15:8]; - 3'b010: wb_dat_o <= #1 ctr; - 3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr) - 3'b100: wb_dat_o <= #1 sr; // write is command register (cr) - 3'b101: wb_dat_o <= #1 txr; - 3'b110: wb_dat_o <= #1 cr; - 3'b111: wb_dat_o <= #1 0; // reserved - endcase - end - - // generate registers - always @(posedge wb_clk_i or negedge rst_i) - if (!rst_i) - begin - prer <= #1 16'hffff; - ctr <= #1 8'h0; - txr <= #1 8'h0; - end - else if (wb_rst_i) - begin - prer <= #1 16'hffff; - ctr <= #1 8'h0; - txr <= #1 8'h0; - end - else - if (wb_wacc) - case (wb_adr_i) // synopsis parallel_case - 3'b000 : prer [ 7:0] <= #1 wb_dat_i; - 3'b001 : prer [15:8] <= #1 wb_dat_i; - 3'b010 : ctr <= #1 wb_dat_i; - 3'b011 : txr <= #1 wb_dat_i; - default: ; - endcase - - // generate command register (special case) - always @(posedge wb_clk_i or negedge rst_i) - if (~rst_i) - cr <= #1 8'h0; - else if (wb_rst_i) - cr <= #1 8'h0; - else if (wb_wacc) - begin - if (core_en & (wb_adr_i == 3'b100) ) - cr <= #1 wb_dat_i; - end - else - begin - if (done | i2c_al) - cr[7:4] <= #1 4'h0; // clear command bits when done - // or when aribitration lost - cr[2:1] <= #1 2'b0; // reserved bits - cr[0] <= #1 2'b0; // clear IRQ_ACK bit - end - - - // decode command register - wire sta = cr[7]; - wire sto = cr[6]; - wire rd = cr[5]; - wire wr = cr[4]; - wire ack = cr[3]; - wire iack = cr[0]; - - // decode control register - assign core_en = ctr[7]; - assign ien = ctr[6]; - - // hookup byte controller block - i2c_master_byte_ctrl byte_controller ( - .clk ( wb_clk_i ), - .rst ( wb_rst_i ), - .nReset ( rst_i ), - .ena ( core_en ), - .clk_cnt ( prer ), - .start ( sta ), - .stop ( sto ), - .read ( rd ), - .write ( wr ), - .ack_in ( ack ), - .din ( txr ), - .cmd_ack ( done ), - .ack_out ( irxack ), - .dout ( rxr ), - .i2c_busy ( i2c_busy ), - .i2c_al ( i2c_al ), - .scl_i ( scl_pad_i ), - .scl_o ( scl_pad_o ), - .scl_oen ( scl_padoen_o ), - .sda_i ( sda_pad_i ), - .sda_o ( sda_pad_o ), - .sda_oen ( sda_padoen_o ) - ); - - // status register block + interrupt request signal - always @(posedge wb_clk_i or negedge rst_i) - if (!rst_i) - begin - al <= #1 1'b0; - rxack <= #1 1'b0; - tip <= #1 1'b0; - irq_flag <= #1 1'b0; - end - else if (wb_rst_i) - begin - al <= #1 1'b0; - rxack <= #1 1'b0; - tip <= #1 1'b0; - irq_flag <= #1 1'b0; - end - else - begin - al <= #1 i2c_al | (al & ~sta); - rxack <= #1 irxack; - tip <= #1 (rd | wr); - irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated - end - - // generate interrupt request signals - always @(posedge wb_clk_i or negedge rst_i) - if (!rst_i) - wb_inta_o <= #1 1'b0; - else if (wb_rst_i) - wb_inta_o <= #1 1'b0; - else - wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set) - - // assign status register bits - assign sr[7] = rxack; - assign sr[6] = i2c_busy; - assign sr[5] = al; - assign sr[4:2] = 3'h0; // reserved - assign sr[1] = tip; - assign sr[0] = irq_flag; - -endmodule diff --git a/fpga/usrp2/opencores/i2c/rtl/verilog/timescale.v b/fpga/usrp2/opencores/i2c/rtl/verilog/timescale.v deleted file mode 100644 index 60d4ecbd1..000000000 --- a/fpga/usrp2/opencores/i2c/rtl/verilog/timescale.v +++ /dev/null @@ -1,2 +0,0 @@ -`timescale 1ns / 10ps - diff --git a/fpga/usrp2/opencores/i2c/rtl/vhdl/I2C.VHD b/fpga/usrp2/opencores/i2c/rtl/vhdl/I2C.VHD deleted file mode 100644 index 64d1eb656..000000000 --- a/fpga/usrp2/opencores/i2c/rtl/vhdl/I2C.VHD +++ /dev/null @@ -1,620 +0,0 @@ --- --- Simple I2C controller --- --- 1) No multimaster --- 2) No slave mode --- 3) No fifo's --- --- notes: --- Every command is acknowledged. Do not set a new command before previous is acknowledged. --- Dout is available 1 clock cycle later as cmd_ack --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -package I2C is - component simple_i2c is - port ( - clk : in std_logic; - ena : in std_logic; - nReset : in std_logic; - - clk_cnt : in unsigned(7 downto 0); -- 4x SCL - - -- input signals - start, - stop, - read, - write, - ack_in : std_logic; - Din : in std_logic_vector(7 downto 0); - - -- output signals - cmd_ack : out std_logic; - ack_out : out std_logic; - Dout : out std_logic_vector(7 downto 0); - - -- i2c signals - SCL : inout std_logic; - SDA : inout std_logic - ); - end component simple_i2c; -end package I2C; - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity simple_i2c is - port ( - clk : in std_logic; - ena : in std_logic; - nReset : in std_logic; - - clk_cnt : in unsigned(7 downto 0); -- 4x SCL - - -- input signals - start, - stop, - read, - write, - ack_in : std_logic; - Din : in std_logic_vector(7 downto 0); - - -- output signals - cmd_ack : out std_logic; - ack_out : out std_logic; - Dout : out std_logic_vector(7 downto 0); - - -- i2c signals - SCL : inout std_logic; - SDA : inout std_logic - ); -end entity simple_i2c; - -architecture structural of simple_i2c is - component i2c_core is - port ( - clk : in std_logic; - nReset : in std_logic; - - clk_cnt : in unsigned(7 downto 0); - - cmd : in std_logic_vector(2 downto 0); - cmd_ack : out std_logic; - busy : out std_logic; - - Din : in std_logic; - Dout : out std_logic; - - SCL : inout std_logic; - SDA : inout std_logic - ); - end component i2c_core; - - -- commands for i2c_core - constant CMD_NOP : std_logic_vector(2 downto 0) := "000"; - constant CMD_START : std_logic_vector(2 downto 0) := "010"; - constant CMD_STOP : std_logic_vector(2 downto 0) := "011"; - constant CMD_READ : std_logic_vector(2 downto 0) := "100"; - constant CMD_WRITE : std_logic_vector(2 downto 0) := "101"; - - -- signals for i2c_core - signal core_cmd : std_logic_vector(2 downto 0); - signal core_ack, core_busy, core_txd, core_rxd : std_logic; - - -- signals for shift register - signal sr : std_logic_vector(7 downto 0); -- 8bit shift register - signal shift, ld : std_logic; - - -- signals for state machine - signal go, host_ack : std_logic; -begin - -- hookup i2c core - u1: i2c_core port map (clk, nReset, clk_cnt, core_cmd, core_ack, core_busy, core_txd, core_rxd, SCL, SDA); - - -- generate host-command-acknowledge - cmd_ack <= host_ack; - - -- generate go-signal - go <= (read or write) and not host_ack; - - -- assign Dout output to shift-register - Dout <= sr; - - -- assign ack_out output to core_rxd (contains last received bit) - ack_out <= core_rxd; - - -- generate shift register - shift_register: process(clk) - begin - if (clk'event and clk = '1') then - if (ld = '1') then - sr <= din; - elsif (shift = '1') then - sr <= (sr(6 downto 0) & core_rxd); - end if; - end if; - end process shift_register; - - -- - -- state machine - -- - statemachine : block - type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop); - signal state : states; - signal dcnt : unsigned(2 downto 0); - begin - -- - -- command interpreter, translate complex commands into simpler I2C commands - -- - nxt_state_decoder: process(clk, nReset, state) - variable nxt_state : states; - variable idcnt : unsigned(2 downto 0); - variable ihost_ack : std_logic; - variable icore_cmd : std_logic_vector(2 downto 0); - variable icore_txd : std_logic; - variable ishift, iload : std_logic; - begin - -- 8 databits (1byte) of data to shift-in/out - idcnt := dcnt; - - -- no acknowledge (until command complete) - ihost_ack := '0'; - - icore_txd := core_txd; - - -- keep current command to i2c_core - icore_cmd := core_cmd; - - -- no shifting or loading of shift-register - ishift := '0'; - iload := '0'; - - -- keep current state; - nxt_state := state; - case state is - when st_idle => - if (go = '1') then - if (start = '1') then - nxt_state := st_start; - icore_cmd := CMD_START; - elsif (read = '1') then - nxt_state := st_read; - icore_cmd := CMD_READ; - idcnt := "111"; - else - nxt_state := st_write; - icore_cmd := CMD_WRITE; - idcnt := "111"; - iload := '1'; - end if; - end if; - - when st_start => - if (core_ack = '1') then - if (read = '1') then - nxt_state := st_read; - icore_cmd := CMD_READ; - idcnt := "111"; - else - nxt_state := st_write; - icore_cmd := CMD_WRITE; - idcnt := "111"; - iload := '1'; - end if; - end if; - - when st_write => - if (core_ack = '1') then - idcnt := dcnt -1; -- count down Data_counter - icore_txd := sr(7); - if (dcnt = 0) then - nxt_state := st_ack; - icore_cmd := CMD_READ; - else - ishift := '1'; --- icore_txd := sr(7); - end if; - end if; - - when st_read => - if (core_ack = '1') then - idcnt := dcnt -1; -- count down Data_counter - ishift := '1'; - if (dcnt = 0) then - nxt_state := st_ack; - icore_cmd := CMD_WRITE; - icore_txd := ack_in; - end if; - end if; - - when st_ack => - if (core_ack = '1') then - -- generate command acknowledge signal - ihost_ack := '1'; - - -- Perform an additional shift, needed for 'read' (store last received bit in shift register) - ishift := '1'; - - -- check for stop; Should a STOP command be generated ? - if (stop = '1') then - nxt_state := st_stop; - icore_cmd := CMD_STOP; - else - nxt_state := st_idle; - icore_cmd := CMD_NOP; - end if; - end if; - - when st_stop => - if (core_ack = '1') then - nxt_state := st_idle; - icore_cmd := CMD_NOP; - end if; - - when others => -- illegal states - nxt_state := st_idle; - icore_cmd := CMD_NOP; - end case; - - -- generate registers - if (nReset = '0') then - core_cmd <= CMD_NOP; - core_txd <= '0'; - - shift <= '0'; - ld <= '0'; - - dcnt <= "111"; - host_ack <= '0'; - - state <= st_idle; - elsif (clk'event and clk = '1') then - if (ena = '1') then - state <= nxt_state; - - dcnt <= idcnt; - shift <= ishift; - ld <= iload; - - core_cmd <= icore_cmd; - core_txd <= icore_txd; - - host_ack <= ihost_ack; - end if; - end if; - end process nxt_state_decoder; - - end block statemachine; - -end architecture structural; - - --- --- --- I2C Core --- --- Translate simple commands into SCL/SDA transitions --- Each command has 5 states, A/B/C/D/idle --- --- start: SCL ~~~~~~~~~~\____ --- SDA ~~~~~~~~\______ --- x | A | B | C | D | i --- --- repstart SCL ____/~~~~\___ --- SDA __/~~~\______ --- x | A | B | C | D | i --- --- stop SCL ____/~~~~~~~~ --- SDA ==\____/~~~~~ --- x | A | B | C | D | i --- ---- write SCL ____/~~~~\____ --- SDA ==X=========X= --- x | A | B | C | D | i --- ---- read SCL ____/~~~~\____ --- SDA XXXX=====XXXX --- x | A | B | C | D | i --- - --- Timing: Normal mode Fast mode ------------------------------------------------------------------ --- Fscl 100KHz 400KHz --- Th_scl 4.0us 0.6us High period of SCL --- Tl_scl 4.7us 1.3us Low period of SCL --- Tsu:sta 4.7us 0.6us setup time for a repeated start condition --- Tsu:sto 4.0us 0.6us setup time for a stop conditon --- Tbuf 4.7us 1.3us Bus free time between a stop and start condition --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity i2c_core is - port ( - clk : in std_logic; - nReset : in std_logic; - - clk_cnt : in unsigned(7 downto 0); - - cmd : in std_logic_vector(2 downto 0); - cmd_ack : out std_logic; - busy : out std_logic; - - Din : in std_logic; - Dout : out std_logic; - - SCL : inout std_logic; - SDA : inout std_logic - ); -end entity i2c_core; - -architecture structural of i2c_core is - constant CMD_NOP : std_logic_vector(2 downto 0) := "000"; - constant CMD_START : std_logic_vector(2 downto 0) := "010"; - constant CMD_STOP : std_logic_vector(2 downto 0) := "011"; - constant CMD_READ : std_logic_vector(2 downto 0) := "100"; - constant CMD_WRITE : std_logic_vector(2 downto 0) := "101"; - - type cmds is (idle, start_a, start_b, start_c, start_d, stop_a, stop_b, stop_c, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d); - signal state : cmds; - signal SDAo, SCLo : std_logic; - signal txd : std_logic; - signal clk_en, slave_wait :std_logic; - signal cnt : unsigned(7 downto 0) := clk_cnt; -begin - -- whenever the slave is not ready it can delay the cycle by pulling SCL low - slave_wait <= '1' when ((SCLo = '1') and (SCL = '0')) else '0'; - - -- generate clk enable signal - gen_clken: process(clk, nReset) - begin - if (nReset = '0') then - cnt <= (others => '0'); - clk_en <= '1'; --'0'; - elsif (clk'event and clk = '1') then - if (cnt = 0) then - clk_en <= '1'; - cnt <= clk_cnt; - else - if (slave_wait = '0') then - cnt <= cnt -1; - end if; - clk_en <= '0'; - end if; - end if; - end process gen_clken; - - -- generate statemachine - nxt_state_decoder : process (clk, nReset, state, cmd, SDA) - variable nxt_state : cmds; - variable icmd_ack, ibusy, store_sda : std_logic; - variable itxd : std_logic; - begin - - nxt_state := state; - - icmd_ack := '0'; -- default no acknowledge - ibusy := '1'; -- default busy - - store_sda := '0'; - - itxd := txd; - - case (state) is - -- idle - when idle => - case cmd is - when CMD_START => - nxt_state := start_a; - icmd_ack := '1'; -- command completed - - when CMD_STOP => - nxt_state := stop_a; - icmd_ack := '1'; -- command completed - - when CMD_WRITE => - nxt_state := wr_a; - icmd_ack := '1'; -- command completed - itxd := Din; - - when CMD_READ => - nxt_state := rd_a; - icmd_ack := '1'; -- command completed - - when others => - nxt_state := idle; --- don't acknowledge NOP command icmd_ack := '1'; -- command completed - ibusy := '0'; - end case; - - -- start - when start_a => - nxt_state := start_b; - - when start_b => - nxt_state := start_c; - - when start_c => - nxt_state := start_d; - - when start_d => - nxt_state := idle; - ibusy := '0'; -- not busy when idle - - - -- stop - when stop_a => - nxt_state := stop_b; - - when stop_b => - nxt_state := stop_c; - - when stop_c => --- nxt_state := stop_d; - --- when stop_d => - nxt_state := idle; - ibusy := '0'; -- not busy when idle - - -- read - when rd_a => - nxt_state := rd_b; - - when rd_b => - nxt_state := rd_c; - - when rd_c => - nxt_state := rd_d; - store_sda := '1'; - - when rd_d => - nxt_state := idle; - ibusy := '0'; -- not busy when idle - - -- write - when wr_a => - nxt_state := wr_b; - - when wr_b => - nxt_state := wr_c; - - when wr_c => - nxt_state := wr_d; - - when wr_d => - nxt_state := idle; - ibusy := '0'; -- not busy when idle - - end case; - - -- generate regs - if (nReset = '0') then - state <= idle; - cmd_ack <= '0'; - busy <= '0'; - txd <= '0'; - Dout <= '0'; - elsif (clk'event and clk = '1') then - if (clk_en = '1') then - state <= nxt_state; - busy <= ibusy; - - txd <= itxd; - if (store_sda = '1') then - Dout <= SDA; - end if; - end if; - - cmd_ack <= icmd_ack and clk_en; - end if; - end process nxt_state_decoder; - - -- - -- convert states to SCL and SDA signals - -- - output_decoder: process (clk, nReset, state) - variable iscl, isda : std_logic; - begin - case (state) is - when idle => - iscl := SCLo; -- keep SCL in same state - isda := SDA; -- keep SDA in same state - - -- start - when start_a => - iscl := SCLo; -- keep SCL in same state (for repeated start) - isda := '1'; -- set SDA high - - when start_b => - iscl := '1'; -- set SCL high - isda := '1'; -- keep SDA high - - when start_c => - iscl := '1'; -- keep SCL high - isda := '0'; -- sel SDA low - - when start_d => - iscl := '0'; -- set SCL low - isda := '0'; -- keep SDA low - - -- stop - when stop_a => - iscl := '0'; -- keep SCL disabled - isda := '0'; -- set SDA low - - when stop_b => - iscl := '1'; -- set SCL high - isda := '0'; -- keep SDA low - - when stop_c => - iscl := '1'; -- keep SCL high - isda := '1'; -- set SDA high - - -- write - when wr_a => - iscl := '0'; -- keep SCL low --- isda := txd; -- set SDA - isda := Din; - - when wr_b => - iscl := '1'; -- set SCL high --- isda := txd; -- set SDA - isda := Din; - - when wr_c => - iscl := '1'; -- keep SCL high --- isda := txd; -- set SDA - isda := Din; - - when wr_d => - iscl := '0'; -- set SCL low --- isda := txd; -- set SDA - isda := Din; - - -- read - when rd_a => - iscl := '0'; -- keep SCL low - isda := '1'; -- tri-state SDA - - when rd_b => - iscl := '1'; -- set SCL high - isda := '1'; -- tri-state SDA - - when rd_c => - iscl := '1'; -- keep SCL high - isda := '1'; -- tri-state SDA - - when rd_d => - iscl := '0'; -- set SCL low - isda := '1'; -- tri-state SDA - end case; - - -- generate registers - if (nReset = '0') then - SCLo <= '1'; - SDAo <= '1'; - elsif (clk'event and clk = '1') then - if (clk_en = '1') then - SCLo <= iscl; - SDAo <= isda; - end if; - end if; - end process output_decoder; - - SCL <= '0' when (SCLo = '0') else 'Z'; -- since SCL is externally pulled-up convert a '1' to a 'Z'(tri-state) - SDA <= '0' when (SDAo = '0') else 'Z'; -- since SDA is externally pulled-up convert a '1' to a 'Z'(tri-state) --- SCL <= SCLo; --- SDA <= SDAo; - -end architecture structural; - - - - diff --git a/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd b/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd deleted file mode 100644 index 1b8eb96d2..000000000 --- a/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd +++ /dev/null @@ -1,495 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- WISHBONE revB2 I2C Master Core; bit-controller ---- ----- ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ----- Downloaded from: http://www.opencores.org/projects/i2c/ ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2000 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- CVS Log --- --- $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11 12:10:13 rherveille Exp $ --- --- $Date: 2006/10/11 12:10:13 $ --- $Revision: 1.14 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: i2c_master_bit_ctrl.vhd,v $ --- Revision 1.14 2006/10/11 12:10:13 rherveille --- Added missing semicolons ';' on endif --- --- Revision 1.13 2006/10/06 10:48:24 rherveille --- fixed short scl high pulse after clock stretch --- --- Revision 1.12 2004/05/07 11:53:31 rherveille --- Fixed previous fix :) Made a variable vs signal mistake. --- --- Revision 1.11 2004/05/07 11:04:00 rherveille --- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. --- --- Revision 1.10 2004/02/27 07:49:43 rherveille --- Fixed a bug in the arbitration-lost signal generation. VHDL version only. --- --- Revision 1.9 2003/08/12 14:48:37 rherveille --- Forgot an 'end if' :-/ --- --- Revision 1.8 2003/08/09 07:01:13 rherveille --- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. --- Fixed a potential bug in the byte controller's host-acknowledge generation. --- --- Revision 1.7 2003/02/05 00:06:02 rherveille --- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. --- --- Revision 1.6 2003/02/01 02:03:06 rherveille --- Fixed a few 'arbitration lost' bugs. VHDL version only. --- --- Revision 1.5 2002/12/26 16:05:47 rherveille --- Core is now a Multimaster I2C controller. --- --- Revision 1.4 2002/11/30 22:24:37 rherveille --- Cleaned up code --- --- Revision 1.3 2002/10/30 18:09:53 rherveille --- Fixed some reported minor start/stop generation timing issuess. --- --- Revision 1.2 2002/06/15 07:37:04 rherveille --- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. --- --- Revision 1.1 2001/11/05 12:02:33 rherveille --- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. --- Code updated, is now up-to-date to doc. rev.0.4. --- Added headers. --- - - --- -------------------------------------- --- Bit controller section ------------------------------------- --- --- Translate simple commands into SCL/SDA transitions --- Each command has 5 states, A/B/C/D/idle --- --- start: SCL ~~~~~~~~~~~~~~\____ --- SDA XX/~~~~~~~\______ --- x | A | B | C | D | i --- --- repstart SCL ______/~~~~~~~\___ --- SDA __/~~~~~~~\______ --- x | A | B | C | D | i --- --- stop SCL _______/~~~~~~~~~~~ --- SDA ==\___________/~~~~~ --- x | A | B | C | D | i --- ---- write SCL ______/~~~~~~~\____ --- SDA XXX===============XX --- x | A | B | C | D | i --- ---- read SCL ______/~~~~~~~\____ --- SDA XXXXXXX=XXXXXXXXXXX --- x | A | B | C | D | i --- - --- Timing: Normal mode Fast mode ------------------------------------------------------------------ --- Fscl 100KHz 400KHz --- Th_scl 4.0us 0.6us High period of SCL --- Tl_scl 4.7us 1.3us Low period of SCL --- Tsu:sta 4.7us 0.6us setup time for a repeated start condition --- Tsu:sto 4.0us 0.6us setup time for a stop conditon --- Tbuf 4.7us 1.3us Bus free time between a stop and start condition --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity i2c_master_bit_ctrl is - port ( - clk : in std_logic; - rst : in std_logic; - nReset : in std_logic; - ena : in std_logic; -- core enable signal - - clk_cnt : in unsigned(15 downto 0); -- clock prescale value - - cmd : in std_logic_vector(3 downto 0); - cmd_ack : out std_logic; -- command completed - busy : out std_logic; -- i2c bus busy - al : out std_logic; -- arbitration lost - - din : in std_logic; - dout : out std_logic; - - -- i2c lines - scl_i : in std_logic; -- i2c clock line input - scl_o : out std_logic; -- i2c clock line output - scl_oen : out std_logic; -- i2c clock line output enable, active low - sda_i : in std_logic; -- i2c data line input - sda_o : out std_logic; -- i2c data line output - sda_oen : out std_logic -- i2c data line output enable, active low - ); -end entity i2c_master_bit_ctrl; - -architecture structural of i2c_master_bit_ctrl is - constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000"; - constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001"; - constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010"; - constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100"; - constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000"; - - type states is (idle, start_a, start_b, start_c, start_d, start_e, - stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d); - signal c_state : states; - - signal iscl_oen, isda_oen : std_logic; -- internal I2C lines - signal sda_chk : std_logic; -- check SDA status (multi-master arbitration) - signal dscl_oen : std_logic; -- delayed scl_oen signals - signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs - signal clk_en, slave_wait : std_logic; -- clock generation signals - signal ial : std_logic; -- internal arbitration lost signal --- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation) - signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis) - -begin - -- whenever the slave is not ready it can delay the cycle by pulling SCL low - -- delay scl_oen - process (clk) - begin - if (clk'event and clk = '1') then - dscl_oen <= iscl_oen; - end if; - end process; - slave_wait <= dscl_oen and not sSCL; - - -- generate clk enable signal - gen_clken: process(clk, nReset) - begin - if (nReset = '0') then - cnt <= (others => '0'); - clk_en <= '1'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - cnt <= (others => '0'); - clk_en <= '1'; - elsif ( (cnt = 0) or (ena = '0') ) then - cnt <= clk_cnt; - clk_en <= '1'; - elsif (slave_wait = '1') then - cnt <= cnt; - clk_en <= '0'; - else - cnt <= cnt -1; - clk_en <= '0'; - end if; - end if; - end process gen_clken; - - - -- generate bus status controller - bus_status_ctrl: block - signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA - signal sta_condition : std_logic; -- start detected - signal sto_condition : std_logic; -- stop detected - signal cmd_stop : std_logic; -- STOP command - signal ibusy : std_logic; -- internal busy signal - begin - -- synchronize SCL and SDA inputs - synch_scl_sda: process(clk, nReset) - begin - if (nReset = '0') then - sSCL <= '1'; - sSDA <= '1'; - - dSCL <= '1'; - dSDA <= '1'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - sSCL <= '1'; - sSDA <= '1'; - - dSCL <= '1'; - dSDA <= '1'; - else - sSCL <= scl_i; - sSDA <= sda_i; - - dSCL <= sSCL; - dSDA <= sSDA; - end if; - end if; - end process synch_SCL_SDA; - - -- detect start condition => detect falling edge on SDA while SCL is high - -- detect stop condition => detect rising edge on SDA while SCL is high - detect_sta_sto: process(clk, nReset) - begin - if (nReset = '0') then - sta_condition <= '0'; - sto_condition <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - sta_condition <= '0'; - sto_condition <= '0'; - else - sta_condition <= (not sSDA and dSDA) and sSCL; - sto_condition <= (sSDA and not dSDA) and sSCL; - end if; - end if; - end process detect_sta_sto; - - -- generate i2c-bus busy signal - gen_busy: process(clk, nReset) - begin - if (nReset = '0') then - ibusy <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - ibusy <= '0'; - else - ibusy <= (sta_condition or ibusy) and not sto_condition; - end if; - end if; - end process gen_busy; - busy <= ibusy; - - - -- generate arbitration lost signal - -- aribitration lost when: - -- 1) master drives SDA high, but the i2c bus is low - -- 2) stop detected while not requested (detect during 'idle' state) - gen_al: process(clk, nReset) - begin - if (nReset = '0') then - cmd_stop <= '0'; - ial <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - cmd_stop <= '0'; - ial <= '0'; - else - if (clk_en = '1') then - if (cmd = I2C_CMD_STOP) then - cmd_stop <= '1'; - else - cmd_stop <= '0'; - end if; - end if; - - if (c_state = idle) then - ial <= (sda_chk and not sSDA and isda_oen); - else - ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop); - end if; - - end if; - end if; - end process gen_al; - al <= ial; - - -- generate dout signal, store dout on rising edge of SCL - gen_dout: process(clk) - begin - if (clk'event and clk = '1') then - if (sSCL = '1' and dSCL = '0') then - dout <= sSDA; - end if; - end if; - end process gen_dout; - end block bus_status_ctrl; - - - -- generate statemachine - nxt_state_decoder : process (clk, nReset, c_state, cmd) - begin - if (nReset = '0') then - c_state <= idle; - cmd_ack <= '0'; - iscl_oen <= '1'; - isda_oen <= '1'; - sda_chk <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1' or ial = '1') then - c_state <= idle; - cmd_ack <= '0'; - iscl_oen <= '1'; - isda_oen <= '1'; - sda_chk <= '0'; - else - cmd_ack <= '0'; -- default no acknowledge - - if (clk_en = '1') then - case (c_state) is - -- idle - when idle => - case cmd is - when I2C_CMD_START => c_state <= start_a; - when I2C_CMD_STOP => c_state <= stop_a; - when I2C_CMD_WRITE => c_state <= wr_a; - when I2C_CMD_READ => c_state <= rd_a; - when others => c_state <= idle; -- NOP command - end case; - - iscl_oen <= iscl_oen; -- keep SCL in same state - isda_oen <= isda_oen; -- keep SDA in same state - sda_chk <= '0'; -- don't check SDA - - -- start - when start_a => - c_state <= start_b; - iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start) - isda_oen <= '1'; -- set SDA high - sda_chk <= '0'; -- don't check SDA - - when start_b => - c_state <= start_c; - iscl_oen <= '1'; -- set SCL high - isda_oen <= '1'; -- keep SDA high - sda_chk <= '0'; -- don't check SDA - - when start_c => - c_state <= start_d; - iscl_oen <= '1'; -- keep SCL high - isda_oen <= '0'; -- set SDA low - sda_chk <= '0'; -- don't check SDA - - when start_d => - c_state <= start_e; - iscl_oen <= '1'; -- keep SCL high - isda_oen <= '0'; -- keep SDA low - sda_chk <= '0'; -- don't check SDA - - when start_e => - c_state <= idle; - cmd_ack <= '1'; -- command completed - iscl_oen <= '0'; -- set SCL low - isda_oen <= '0'; -- keep SDA low - sda_chk <= '0'; -- don't check SDA - - -- stop - when stop_a => - c_state <= stop_b; - iscl_oen <= '0'; -- keep SCL low - isda_oen <= '0'; -- set SDA low - sda_chk <= '0'; -- don't check SDA - - when stop_b => - c_state <= stop_c; - iscl_oen <= '1'; -- set SCL high - isda_oen <= '0'; -- keep SDA low - sda_chk <= '0'; -- don't check SDA - - when stop_c => - c_state <= stop_d; - iscl_oen <= '1'; -- keep SCL high - isda_oen <= '0'; -- keep SDA low - sda_chk <= '0'; -- don't check SDA - - when stop_d => - c_state <= idle; - cmd_ack <= '1'; -- command completed - iscl_oen <= '1'; -- keep SCL high - isda_oen <= '1'; -- set SDA high - sda_chk <= '0'; -- don't check SDA - - -- read - when rd_a => - c_state <= rd_b; - iscl_oen <= '0'; -- keep SCL low - isda_oen <= '1'; -- tri-state SDA - sda_chk <= '0'; -- don't check SDA - - when rd_b => - c_state <= rd_c; - iscl_oen <= '1'; -- set SCL high - isda_oen <= '1'; -- tri-state SDA - sda_chk <= '0'; -- don't check SDA - - when rd_c => - c_state <= rd_d; - iscl_oen <= '1'; -- keep SCL high - isda_oen <= '1'; -- tri-state SDA - sda_chk <= '0'; -- don't check SDA - - when rd_d => - c_state <= idle; - cmd_ack <= '1'; -- command completed - iscl_oen <= '0'; -- set SCL low - isda_oen <= '1'; -- tri-state SDA - sda_chk <= '0'; -- don't check SDA - - -- write - when wr_a => - c_state <= wr_b; - iscl_oen <= '0'; -- keep SCL low - isda_oen <= din; -- set SDA - sda_chk <= '0'; -- don't check SDA (SCL low) - - when wr_b => - c_state <= wr_c; - iscl_oen <= '1'; -- set SCL high - isda_oen <= din; -- keep SDA - sda_chk <= '1'; -- check SDA - - when wr_c => - c_state <= wr_d; - iscl_oen <= '1'; -- keep SCL high - isda_oen <= din; -- keep SDA - sda_chk <= '1'; -- check SDA - - when wr_d => - c_state <= idle; - cmd_ack <= '1'; -- command completed - iscl_oen <= '0'; -- set SCL low - isda_oen <= din; -- keep SDA - sda_chk <= '0'; -- don't check SDA (SCL low) - - when others => - - end case; - end if; - end if; - end if; - end process nxt_state_decoder; - - - -- assign outputs - scl_o <= '0'; - scl_oen <= iscl_oen; - sda_o <= '0'; - sda_oen <= isda_oen; -end architecture structural; - diff --git a/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd b/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd deleted file mode 100644 index bdb2a881e..000000000 --- a/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd +++ /dev/null @@ -1,370 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- WISHBONE revB2 compl. I2C Master Core; byte-controller ---- ----- ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ----- Downloaded from: http://www.opencores.org/projects/i2c/ ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2000 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- CVS Log --- --- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004/02/18 11:41:48 rherveille Exp $ --- --- $Date: 2004/02/18 11:41:48 $ --- $Revision: 1.5 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: i2c_master_byte_ctrl.vhd,v $ --- Revision 1.5 2004/02/18 11:41:48 rherveille --- Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. --- --- Revision 1.4 2003/08/09 07:01:13 rherveille --- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. --- Fixed a potential bug in the byte controller's host-acknowledge generation. --- --- Revision 1.3 2002/12/26 16:05:47 rherveille --- Core is now a Multimaster I2C controller. --- --- Revision 1.2 2002/11/30 22:24:37 rherveille --- Cleaned up code --- --- Revision 1.1 2001/11/05 12:02:33 rherveille --- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. --- Code updated, is now up-to-date to doc. rev.0.4. --- Added headers. --- - - - - --- ------------------------------------------- --- Byte controller section ------------------------------------------- --- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity i2c_master_byte_ctrl is - port ( - clk : in std_logic; - rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) - nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) - ena : in std_logic; -- core enable signal - - clk_cnt : in unsigned(15 downto 0); -- 4x SCL - - -- input signals - start, - stop, - read, - write, - ack_in : std_logic; - din : in std_logic_vector(7 downto 0); - - -- output signals - cmd_ack : out std_logic; -- command done - ack_out : out std_logic; - i2c_busy : out std_logic; -- arbitration lost - i2c_al : out std_logic; -- i2c bus busy - dout : out std_logic_vector(7 downto 0); - - -- i2c lines - scl_i : in std_logic; -- i2c clock line input - scl_o : out std_logic; -- i2c clock line output - scl_oen : out std_logic; -- i2c clock line output enable, active low - sda_i : in std_logic; -- i2c data line input - sda_o : out std_logic; -- i2c data line output - sda_oen : out std_logic -- i2c data line output enable, active low - ); -end entity i2c_master_byte_ctrl; - -architecture structural of i2c_master_byte_ctrl is - component i2c_master_bit_ctrl is - port ( - clk : in std_logic; - rst : in std_logic; - nReset : in std_logic; - ena : in std_logic; -- core enable signal - - clk_cnt : in unsigned(15 downto 0); -- clock prescale value - - cmd : in std_logic_vector(3 downto 0); - cmd_ack : out std_logic; -- command done - busy : out std_logic; -- i2c bus busy - al : out std_logic; -- arbitration lost - - din : in std_logic; - dout : out std_logic; - - -- i2c lines - scl_i : in std_logic; -- i2c clock line input - scl_o : out std_logic; -- i2c clock line output - scl_oen : out std_logic; -- i2c clock line output enable, active low - sda_i : in std_logic; -- i2c data line input - sda_o : out std_logic; -- i2c data line output - sda_oen : out std_logic -- i2c data line output enable, active low - ); - end component i2c_master_bit_ctrl; - - -- commands for bit_controller block - constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000"; - constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001"; - constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010"; - constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100"; - constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000"; - - -- signals for bit_controller - signal core_cmd : std_logic_vector(3 downto 0); - signal core_ack, core_txd, core_rxd : std_logic; - signal al : std_logic; - - -- signals for shift register - signal sr : std_logic_vector(7 downto 0); -- 8bit shift register - signal shift, ld : std_logic; - - -- signals for state machine - signal go, host_ack : std_logic; - signal dcnt : unsigned(2 downto 0); -- data counter - signal cnt_done : std_logic; - -begin - -- hookup bit_controller - bit_ctrl: i2c_master_bit_ctrl port map( - clk => clk, - rst => rst, - nReset => nReset, - ena => ena, - clk_cnt => clk_cnt, - cmd => core_cmd, - cmd_ack => core_ack, - busy => i2c_busy, - al => al, - din => core_txd, - dout => core_rxd, - scl_i => scl_i, - scl_o => scl_o, - scl_oen => scl_oen, - sda_i => sda_i, - sda_o => sda_o, - sda_oen => sda_oen - ); - i2c_al <= al; - - -- generate host-command-acknowledge - cmd_ack <= host_ack; - - -- generate go-signal - go <= (read or write or stop) and not host_ack; - - -- assign Dout output to shift-register - dout <= sr; - - -- generate shift register - shift_register: process(clk, nReset) - begin - if (nReset = '0') then - sr <= (others => '0'); - elsif (clk'event and clk = '1') then - if (rst = '1') then - sr <= (others => '0'); - elsif (ld = '1') then - sr <= din; - elsif (shift = '1') then - sr <= (sr(6 downto 0) & core_rxd); - end if; - end if; - end process shift_register; - - -- generate data-counter - data_cnt: process(clk, nReset) - begin - if (nReset = '0') then - dcnt <= (others => '0'); - elsif (clk'event and clk = '1') then - if (rst = '1') then - dcnt <= (others => '0'); - elsif (ld = '1') then - dcnt <= (others => '1'); -- load counter with 7 - elsif (shift = '1') then - dcnt <= dcnt -1; - end if; - end if; - end process data_cnt; - - cnt_done <= '1' when (dcnt = 0) else '0'; - - -- - -- state machine - -- - statemachine : block - type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop); - signal c_state : states; - begin - -- - -- command interpreter, translate complex commands into simpler I2C commands - -- - nxt_state_decoder: process(clk, nReset) - begin - if (nReset = '0') then - core_cmd <= I2C_CMD_NOP; - core_txd <= '0'; - shift <= '0'; - ld <= '0'; - host_ack <= '0'; - c_state <= st_idle; - ack_out <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1' or al = '1') then - core_cmd <= I2C_CMD_NOP; - core_txd <= '0'; - shift <= '0'; - ld <= '0'; - host_ack <= '0'; - c_state <= st_idle; - ack_out <= '0'; - else - -- initialy reset all signal - core_txd <= sr(7); - shift <= '0'; - ld <= '0'; - host_ack <= '0'; - - case c_state is - when st_idle => - if (go = '1') then - if (start = '1') then - c_state <= st_start; - core_cmd <= I2C_CMD_START; - elsif (read = '1') then - c_state <= st_read; - core_cmd <= I2C_CMD_READ; - elsif (write = '1') then - c_state <= st_write; - core_cmd <= I2C_CMD_WRITE; - else -- stop - c_state <= st_stop; - core_cmd <= I2C_CMD_STOP; - end if; - - ld <= '1'; - end if; - - when st_start => - if (core_ack = '1') then - if (read = '1') then - c_state <= st_read; - core_cmd <= I2C_CMD_READ; - else - c_state <= st_write; - core_cmd <= I2C_CMD_WRITE; - end if; - - ld <= '1'; - end if; - - when st_write => - if (core_ack = '1') then - if (cnt_done = '1') then - c_state <= st_ack; - core_cmd <= I2C_CMD_READ; - else - c_state <= st_write; -- stay in same state - core_cmd <= I2C_CMD_WRITE; -- write next bit - shift <= '1'; - end if; - end if; - - when st_read => - if (core_ack = '1') then - if (cnt_done = '1') then - c_state <= st_ack; - core_cmd <= I2C_CMD_WRITE; - else - c_state <= st_read; -- stay in same state - core_cmd <= I2C_CMD_READ; -- read next bit - end if; - - shift <= '1'; - core_txd <= ack_in; - end if; - - when st_ack => - if (core_ack = '1') then - -- check for stop; Should a STOP command be generated ? - if (stop = '1') then - c_state <= st_stop; - core_cmd <= I2C_CMD_STOP; - else - c_state <= st_idle; - core_cmd <= I2C_CMD_NOP; - - -- generate command acknowledge signal - host_ack <= '1'; - end if; - - -- assign ack_out output to core_rxd (contains last received bit) - ack_out <= core_rxd; - - core_txd <= '1'; - else - core_txd <= ack_in; - end if; - - when st_stop => - if (core_ack = '1') then - c_state <= st_idle; - core_cmd <= I2C_CMD_NOP; - - -- generate command acknowledge signal - host_ack <= '1'; - end if; - - when others => -- illegal states - c_state <= st_idle; - core_cmd <= I2C_CMD_NOP; - report ("Byte controller entered illegal state."); - - end case; - - end if; - end if; - end process nxt_state_decoder; - - end block statemachine; - -end architecture structural; - diff --git a/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_top.vhd b/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_top.vhd deleted file mode 100644 index a2557120f..000000000 --- a/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_top.vhd +++ /dev/null @@ -1,359 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- WISHBONE revB2 compl. I2C Master Core; top level ---- ----- ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ----- Downloaded from: http://www.opencores.org/projects/i2c/ ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2000 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- CVS Log --- --- $Id: i2c_master_top.vhd,v 1.7 2004/03/14 10:17:03 rherveille Exp $ --- --- $Date: 2004/03/14 10:17:03 $ --- $Revision: 1.7 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: i2c_master_top.vhd,v $ --- Revision 1.7 2004/03/14 10:17:03 rherveille --- Fixed simulation issue when writing to CR register --- --- Revision 1.6 2003/08/09 07:01:13 rherveille --- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. --- Fixed a potential bug in the byte controller's host-acknowledge generation. --- --- Revision 1.5 2003/02/01 02:03:06 rherveille --- Fixed a few 'arbitration lost' bugs. VHDL version only. --- --- Revision 1.4 2002/12/26 16:05:47 rherveille --- Core is now a Multimaster I2C controller. --- --- Revision 1.3 2002/11/30 22:24:37 rherveille --- Cleaned up code --- --- Revision 1.2 2001/11/10 10:52:44 rherveille --- Changed PRER reset value from 0x0000 to 0xffff, conform specs. --- - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity i2c_master_top is - generic( - ARST_LVL : std_logic := '0' -- asynchronous reset level - ); - port ( - -- wishbone signals - wb_clk_i : in std_logic; -- master clock input - wb_rst_i : in std_logic := '0'; -- synchronous active high reset - arst_i : in std_logic := not ARST_LVL; -- asynchronous reset - wb_adr_i : in unsigned(2 downto 0); -- lower address bits - wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input - wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output - wb_we_i : in std_logic; -- Write enable input - wb_stb_i : in std_logic; -- Strobe signals / core select signal - wb_cyc_i : in std_logic; -- Valid bus cycle input - wb_ack_o : out std_logic; -- Bus cycle acknowledge output - wb_inta_o : out std_logic; -- interrupt request output signal - - -- i2c lines - scl_pad_i : in std_logic; -- i2c clock line input - scl_pad_o : out std_logic; -- i2c clock line output - scl_padoen_o : out std_logic; -- i2c clock line output enable, active low - sda_pad_i : in std_logic; -- i2c data line input - sda_pad_o : out std_logic; -- i2c data line output - sda_padoen_o : out std_logic -- i2c data line output enable, active low - ); -end entity i2c_master_top; - -architecture structural of i2c_master_top is - component i2c_master_byte_ctrl is - port ( - clk : in std_logic; - rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) - nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) - ena : in std_logic; -- core enable signal - - clk_cnt : in unsigned(15 downto 0); -- 4x SCL - - -- input signals - start, - stop, - read, - write, - ack_in : std_logic; - din : in std_logic_vector(7 downto 0); - - -- output signals - cmd_ack : out std_logic; - ack_out : out std_logic; - i2c_busy : out std_logic; - i2c_al : out std_logic; - dout : out std_logic_vector(7 downto 0); - - -- i2c lines - scl_i : in std_logic; -- i2c clock line input - scl_o : out std_logic; -- i2c clock line output - scl_oen : out std_logic; -- i2c clock line output enable, active low - sda_i : in std_logic; -- i2c data line input - sda_o : out std_logic; -- i2c data line output - sda_oen : out std_logic -- i2c data line output enable, active low - ); - end component i2c_master_byte_ctrl; - - -- registers - signal prer : unsigned(15 downto 0); -- clock prescale register - signal ctr : std_logic_vector(7 downto 0); -- control register - signal txr : std_logic_vector(7 downto 0); -- transmit register - signal rxr : std_logic_vector(7 downto 0); -- receive register - signal cr : std_logic_vector(7 downto 0); -- command register - signal sr : std_logic_vector(7 downto 0); -- status register - - -- internal reset signal - signal rst_i : std_logic; - - -- wishbone write access - signal wb_wacc : std_logic; - - -- internal acknowledge signal - signal iack_o : std_logic; - - -- done signal: command completed, clear command register - signal done : std_logic; - - -- command register signals - signal sta, sto, rd, wr, ack, iack : std_logic; - - signal core_en : std_logic; -- core enable signal - signal ien : std_logic; -- interrupt enable signal - - -- status register signals - signal irxack, rxack : std_logic; -- received aknowledge from slave - signal tip : std_logic; -- transfer in progress - signal irq_flag : std_logic; -- interrupt pending flag - signal i2c_busy : std_logic; -- i2c bus busy (start signal detected) - signal i2c_al, al : std_logic; -- arbitration lost - -begin - -- generate internal reset signal - rst_i <= arst_i xor ARST_LVL; - - -- generate acknowledge output signal - gen_ack_o : process(wb_clk_i) - begin - if (wb_clk_i'event and wb_clk_i = '1') then - iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored - end if; - end process gen_ack_o; - wb_ack_o <= iack_o; - - - -- generate wishbone write access signal - wb_wacc <= wb_cyc_i and wb_stb_i and wb_we_i; - - -- assign wb_dat_o - assign_dato : process(wb_clk_i) - begin - if (wb_clk_i'event and wb_clk_i = '1') then - case wb_adr_i is - when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0)); - when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8)); - when "010" => wb_dat_o <= ctr; - when "011" => wb_dat_o <= rxr; -- write is transmit register TxR - when "100" => wb_dat_o <= sr; -- write is command register CR - - -- Debugging registers: - -- These registers are not documented. - -- Functionality could change in future releases - when "101" => wb_dat_o <= txr; - when "110" => wb_dat_o <= cr; - when "111" => wb_dat_o <= (others => '0'); - when others => wb_dat_o <= (others => 'X'); -- for simulation only - end case; - end if; - end process assign_dato; - - - -- generate registers (CR, SR see below) - gen_regs: process(rst_i, wb_clk_i) - begin - if (rst_i = '0') then - prer <= (others => '1'); - ctr <= (others => '0'); - txr <= (others => '0'); - elsif (wb_clk_i'event and wb_clk_i = '1') then - if (wb_rst_i = '1') then - prer <= (others => '1'); - ctr <= (others => '0'); - txr <= (others => '0'); - elsif (wb_wacc = '1') then - case wb_adr_i is - when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i); - when "001" => prer(15 downto 8) <= unsigned(wb_dat_i); - when "010" => ctr <= wb_dat_i; - when "011" => txr <= wb_dat_i; - when "100" => null; --write to CR, avoid executing the others clause - - -- illegal cases, for simulation only - when others => - report ("Illegal write address, setting all registers to unknown."); - prer <= (others => 'X'); - ctr <= (others => 'X'); - txr <= (others => 'X'); - end case; - end if; - end if; - end process gen_regs; - - - -- generate command register - gen_cr: process(rst_i, wb_clk_i) - begin - if (rst_i = '0') then - cr <= (others => '0'); - elsif (wb_clk_i'event and wb_clk_i = '1') then - if (wb_rst_i = '1') then - cr <= (others => '0'); - elsif (wb_wacc = '1') then - if ( (core_en = '1') and (wb_adr_i = 4) ) then - -- only take new commands when i2c core enabled - -- pending commands are finished - cr <= wb_dat_i; - end if; - else - if (done = '1' or i2c_al = '1') then - cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost - end if; - - cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0' - cr(0) <= '0'; -- clear IRQ_ACK bit - end if; - end if; - end process gen_cr; - - -- decode command register - sta <= cr(7); - sto <= cr(6); - rd <= cr(5); - wr <= cr(4); - ack <= cr(3); - iack <= cr(0); - - -- decode control register - core_en <= ctr(7); - ien <= ctr(6); - - -- hookup byte controller block - byte_ctrl: i2c_master_byte_ctrl port map ( - clk => wb_clk_i, - rst => wb_rst_i, - nReset => rst_i, - ena => core_en, - clk_cnt => prer, - start => sta, - stop => sto, - read => rd, - write => wr, - ack_in => ack, - i2c_busy => i2c_busy, - i2c_al => i2c_al, - din => txr, - cmd_ack => done, - ack_out => irxack, - dout => rxr, - scl_i => scl_pad_i, - scl_o => scl_pad_o, - scl_oen => scl_padoen_o, - sda_i => sda_pad_i, - sda_o => sda_pad_o, - sda_oen => sda_padoen_o - ); - - - -- status register block + interrupt request signal - st_irq_block : block - begin - -- generate status register bits - gen_sr_bits: process (wb_clk_i, rst_i) - begin - if (rst_i = '0') then - al <= '0'; - rxack <= '0'; - tip <= '0'; - irq_flag <= '0'; - elsif (wb_clk_i'event and wb_clk_i = '1') then - if (wb_rst_i = '1') then - al <= '0'; - rxack <= '0'; - tip <= '0'; - irq_flag <= '0'; - else - al <= i2c_al or (al and not sta); - rxack <= irxack; - tip <= (rd or wr); - - -- interrupt request flag is always generated - irq_flag <= (done or i2c_al or irq_flag) and not iack; - end if; - end if; - end process gen_sr_bits; - - -- generate interrupt request signals - gen_irq: process (wb_clk_i, rst_i) - begin - if (rst_i = '0') then - wb_inta_o <= '0'; - elsif (wb_clk_i'event and wb_clk_i = '1') then - if (wb_rst_i = '1') then - wb_inta_o <= '0'; - else - -- interrupt signal is only generated when IEN (interrupt enable bit) is set - wb_inta_o <= irq_flag and ien; - end if; - end if; - end process gen_irq; - - -- assign status register bits - sr(7) <= rxack; - sr(6) <= i2c_busy; - sr(5) <= al; - sr(4 downto 2) <= (others => '0'); -- reserved - sr(1) <= tip; - sr(0) <= irq_flag; - end block; - -end architecture structural; diff --git a/fpga/usrp2/opencores/i2c/rtl/vhdl/readme b/fpga/usrp2/opencores/i2c/rtl/vhdl/readme deleted file mode 100644 index 0d049f736..000000000 --- a/fpga/usrp2/opencores/i2c/rtl/vhdl/readme +++ /dev/null @@ -1,25 +0,0 @@ - - --- This code is provided for free and may be used and -- --- distributed without restriction provided that the -- --- copyright statement is not removed from the file and -- --- that any derivative work contains the original -- --- copyright notice and the associated disclaimer. -- - --- Comments and suggestions are always welcome -- - -The i2c_master core consists of three files: - -- i2c_master_top -- top level -- i2c_master_byte_ctrl -- byte controller -- i2c_master_bit_ctrl -- bit controller - -VHDL needs to be compiled in order. The files are listed -above in descending order. - -I2C.VHD and tst_ds1621.vhd are not supported anymore. -They remain mostly for historical purposes, altough they -might prove usefull. - -Richard Herveille -rherveille@opencores.org diff --git a/fpga/usrp2/opencores/i2c/rtl/vhdl/tst_ds1621.vhd b/fpga/usrp2/opencores/i2c/rtl/vhdl/tst_ds1621.vhd deleted file mode 100644 index ccf50460c..000000000 --- a/fpga/usrp2/opencores/i2c/rtl/vhdl/tst_ds1621.vhd +++ /dev/null @@ -1,283 +0,0 @@ --- --- --- State machine for reading data from Dallas 1621 --- --- Testsystem for i2c controller --- --- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -use work.i2c.all; - -entity DS1621_interface is - port ( - clk : in std_logic; - nReset : in std_logic; - - Dout : out std_logic_vector(7 downto 0); -- data read from ds1621 - - error : out std_logic; -- no correct ack received - - SCL : inout std_logic; - SDA : inout std_logic - ); -end entity DS1621_interface; - -architecture structural of DS1621_interface is - constant SLAVE_ADDR : std_logic_vector(6 downto 0) := "1001000"; - constant CLK_CNT : unsigned(7 downto 0) := conv_unsigned(20, 8); - - signal cmd_ack : std_logic; - signal D : std_logic_vector(7 downto 0); - signal lack, store_dout : std_logic; - - signal start, read, write, ack, stop : std_logic; - signal i2c_dout : std_logic_vector(7 downto 0); - -begin - -- hookup I2C controller - u1: simple_i2c port map (clk => clk, ena => '1', clk_cnt => clk_cnt, nReset => nReset, - read => read, write => write, start => start, stop => stop, ack_in => ack, cmd_ack => cmd_ack, - Din => D, Dout => i2c_dout, ack_out => lack, SCL => SCL, SDA => SDA); - - init_statemachine : block - type states is (i1, i2, i3, i4, i5, t1, t2, t3, t4, t5); - signal state : states; - begin - nxt_state_decoder: process(clk, nReset, state) - variable nxt_state : states; - variable iD : std_logic_vector(7 downto 0); - variable ierr : std_logic; - variable istart, iread, iwrite, iack, istop : std_logic; - variable istore_dout : std_logic; - begin - nxt_state := state; - ierr := '0'; - istore_dout := '0'; - - istart := start; - iread := read; - iwrite := write; - iack := ack; - istop := stop; - iD := D; - - case (state) is - -- init DS1621 - -- 1) send start condition - -- 2) send slave address + write - -- 3) check ack - -- 4) send "access config" command (0xAC) - -- 5) check ack - -- 6) send config register data (0x00) - -- 7) check ack - -- 8) send stop condition - -- 9) send start condition - -- 10) send slave address + write - -- 11) check ack - -- 12) send "start conversion" command (0xEE) - -- 13) check ack - -- 14) send stop condition - - when i1 => -- send start condition, sent slave address + write - nxt_state := i2; - istart := '1'; - iread := '0'; - iwrite := '1'; - iack := '0'; - istop := '0'; - iD := (slave_addr & '0'); -- write to slave (R/W = '0') - - when i2 => -- send "access config" command - if (cmd_ack = '1') then - nxt_state := i3; - -- check aknowledge bit - if (lack = '1') then - ierr := '1'; -- no acknowledge received from last command, expected ACK - end if; - - istart := '0'; - iread := '0'; - iwrite := '1'; - iack := '0'; - istop := '0'; - iD := x"AC"; - end if; - - when i3 => -- send config register data, sent stop condition - if (cmd_ack = '1') then - nxt_state := i4; - -- check aknowledge bit - if (lack = '1') then - ierr := '1'; -- no acknowledge received from last command, expected ACK - end if; - - istart := '0'; - iread := '0'; - iwrite := '1'; - iack := '0'; - istop := '1'; - iD := x"00"; - end if; - - when i4 => -- send start condition, sent slave address + write - if (cmd_ack = '1') then - nxt_state := i5; - - istart := '1'; - iread := '0'; - iwrite := '1'; - iack := '0'; - istop := '0'; - iD := (slave_addr & '0'); -- write to slave (R/W = '0') - end if; - - when i5 => -- send "start conversion" command + stop condition - if (cmd_ack = '1') then - nxt_state := t1; - -- check aknowledge bit - if (lack = '1') then - ierr := '1'; -- no acknowledge received from last command, expected ACK - end if; - - istart := '0'; - iread := '0'; - iwrite := '1'; - iack := '0'; - istop := '1'; - iD := x"EE"; - end if; - -- read temperature - -- 1) sent start condition - -- 2) sent slave address + write - -- 3) check ack - -- 4) sent "read temperature" command (0xAA) - -- 5) check ack - -- 6) sent start condition - -- 7) sent slave address + read - -- 8) check ack - -- 9) read msb - -- 10) send ack - -- 11) read lsb - -- 12) send nack - -- 13) send stop condition - - when t1 => -- send start condition, sent slave address + write - if (cmd_ack = '1') then - nxt_state := t2; - -- check aknowledge bit - if (lack = '1') then - ierr := '1'; -- no acknowledge received from last command, expected ACK - end if; - - istart := '1'; - iread := '0'; - iwrite := '1'; - iack := '0'; - istop := '0'; - iD := (slave_addr & '0'); -- write to slave (R/W = '0') - end if; - - when t2 => -- send read temperature command - if (cmd_ack = '1') then - nxt_state := t3; - -- check aknowledge bit - if (lack = '1') then - ierr := '1'; -- no acknowledge received from last command, expected ACK - end if; - - istart := '0'; - iread := '0'; - iwrite := '1'; - iack := '0'; - istop := '0'; - iD := x"AA"; - end if; - - when t3 => -- send (repeated) start condition, send slave address + read - if (cmd_ack = '1') then - nxt_state := t4; - -- check aknowledge bit - if (lack = '1') then - ierr := '1'; -- no acknowledge received, expected ACK - end if; - - istart := '1'; - iread := '0'; - iwrite := '1'; - iack := '0'; - istop := '0'; - iD := (slave_addr & '1'); -- read from slave (R/W = '1') - end if; - - when t4 => -- read MSB (hi-byte), send acknowledge - if (cmd_ack = '1') then - nxt_state := t5; - -- check aknowledge bit - if (lack = '1') then - ierr := '1'; -- no acknowledge received from last command, expected ACK - end if; - - istart := '0'; - iread := '1'; - iwrite := '0'; - iack := '0'; --ACK - istop := '0'; - end if; - - when t5 => -- read LSB (lo-byte), send acknowledge, sent stop - if (cmd_ack = '1') then - nxt_state := t1; - - istart := '0'; - iread := '1'; - iwrite := '0'; - iack := '1'; --NACK - istop := '1'; - - istore_dout := '1'; - end if; - end case; - - -- genregs - if (nReset = '0') then - state <= i1; - error <= '0'; - store_dout <= '0'; - - start <= '0'; - read <= '0'; - write <= '0'; - ack <= '0'; - stop <= '0'; - D <= (others => '0'); - elsif (clk'event and clk = '1') then - state <= nxt_state; - error <= ierr; - store_dout <= istore_dout; - - start <= istart; - read <= iread; - write <= iwrite; - ack <= iack; - stop <= istop; - D <= iD; - end if; - end process nxt_state_decoder; - end block init_statemachine; - - -- store temp - gen_dout : process(clk) - begin - if (clk'event and clk = '1') then - if (store_dout = '1') then - Dout <= i2c_dout; - end if; - end if; - end process gen_dout; - -end architecture structural; - - diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/bench.vcd b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/bench.vcd deleted file mode 100644 index 9a364415f..000000000 --- a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/bench.vcd +++ /dev/null @@ -1,1496812 +0,0 @@ -$date - Jun 15, 2002 13:36:37 -$end -$version - ncsim: v03.40.(b001) -$end -$timescale - 10 ps -$end - -$scope module tst_bench_top $end -$var reg 1 ! clk $end -$var reg 1 " rstn $end -$var wire 1 # adr [31] $end -$var wire 1 $ adr [30] $end -$var wire 1 % adr [29] $end -$var wire 1 & adr [28] $end -$var wire 1 ' adr [27] $end -$var wire 1 ( adr [26] $end -$var wire 1 ) adr [25] $end -$var wire 1 * adr [24] $end -$var wire 1 + adr [23] $end -$var wire 1 , adr [22] $end -$var wire 1 - adr [21] $end -$var wire 1 . adr [20] $end -$var wire 1 / adr [19] $end -$var wire 1 0 adr [18] $end -$var wire 1 1 adr [17] $end -$var wire 1 2 adr [16] $end -$var wire 1 3 adr [15] $end -$var wire 1 4 adr [14] $end -$var wire 1 5 adr [13] $end -$var wire 1 6 adr [12] $end -$var wire 1 7 adr [11] $end -$var wire 1 8 adr [10] $end -$var wire 1 9 adr [9] $end -$var wire 1 : adr [8] $end -$var wire 1 ; adr [7] $end -$var wire 1 < adr [6] $end -$var wire 1 = adr [5] $end -$var wire 1 > adr [4] $end -$var wire 1 ? adr [3] $end -$var wire 1 @ adr [2] $end -$var wire 1 A adr [1] $end -$var wire 1 B adr [0] $end -$var wire 8 C dat_i [7:0] $end -$var wire 8 D dat_o [7:0] $end -$var wire 1 E we $end -$var wire 1 F stb $end -$var wire 1 G cyc $end -$var wire 1 H ack $end -$var wire 1 I inta $end -$var reg 8 J q [7:0] $end -$var reg 8 K qq [7:0] $end -$var wire 1 L scl $end -$var wire 1 M scl_o $end -$var wire 1 N scl_oen $end -$var wire 1 O sda $end -$var wire 1 P sda_o $end -$var wire 1 Q sda_oen $end -$var parameter 3 R PRER_LO $end -$var parameter 3 S PRER_HI $end -$var parameter 3 T CTR $end -$var parameter 3 U RXR $end -$var parameter 3 V TXR $end -$var parameter 3 W CR $end -$var parameter 3 X SR $end -$var parameter 3 Y TXR_R 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a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/run b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/run deleted file mode 100755 index 41bcaab30..000000000 --- a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/run +++ /dev/null @@ -1,25 +0,0 @@ -#!/bin/csh - -set i2c = ../../.. -set bench = $i2c/bench -set wave_dir = $i2c/sim/rtl_sim/i2c_verilog/waves - -ncverilog \ - \ - +access+rwc \ - +define+WAVES \ - \ - +incdir+$bench/verilog \ - +incdir+$i2c/rtl/verilog \ - \ - $i2c/rtl/verilog/i2c_master_bit_ctrl.v \ - $i2c/rtl/verilog/i2c_master_byte_ctrl.v \ - $i2c/rtl/verilog/i2c_master_top.v \ - \ - $bench/verilog/i2c_slave_model.v \ - $bench/verilog/wb_master_model.v \ - $bench/verilog/tst_bench_top.v - - - - diff --git a/fpga/usrp2/opencores/i2c/software/include/oc_i2c_master.h b/fpga/usrp2/opencores/i2c/software/include/oc_i2c_master.h deleted file mode 100644 index 7f7cfc417..000000000 --- a/fpga/usrp2/opencores/i2c/software/include/oc_i2c_master.h +++ /dev/null @@ -1,102 +0,0 @@ -/* -///////////////////////////////////////////////////////////////////// -//// //// -//// Include file for OpenCores I2C Master core //// -//// //// -//// File : oc_i2c_master.h //// -//// Function: c-include file //// -//// //// -//// Authors: Richard Herveille (richard@asics.ws) //// -//// Filip Miletic //// -//// //// -//// www.opencores.org //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Richard Herveille //// -//// Filip Miletic //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// -*/ - -/* - * Definitions for the Opencores i2c master core - */ - -/* --- Definitions for i2c master's registers --- */ - -/* ----- Read-write access */ - -#define OC_I2C_PRER_LO 0x00 /* Low byte clock prescaler register */ -#define OC_I2C_PRER_HI 0x01 /* High byte clock prescaler register */ -#define OC_I2C_CTR 0x02 /* Control register */ - -/* ----- Write-only registers */ - -#define OC_I2C_TXR 0x03 /* Transmit byte register */ -#define OC_I2C_CR 0x04 /* Command register */ - -/* ----- Read-only registers */ - -#define OC_I2C_RXR 0x03 /* Receive byte register */ -#define OC_I2C_SR 0x04 /* Status register */ - -/* ----- Bits definition */ - -/* ----- Control register */ - -#define OC_I2C_EN (1<<7) /* Core enable bit: */ - /* 1 - core is enabled */ - /* 0 - core is disabled */ -#define OC_I2C_IEN (1<<6) /* Interrupt enable bit */ - /* 1 - Interrupt enabled */ - /* 0 - Interrupt disabled */ - /* Other bits in CR are reserved */ - -/* ----- Command register bits */ - -#define OC_I2C_STA (1<<7) /* Generate (repeated) start condition*/ -#define OC_I2C_STO (1<<6) /* Generate stop condition */ -#define OC_I2C_RD (1<<5) /* Read from slave */ -#define OC_I2C_WR (1<<4) /* Write to slave */ -#define OC_I2C_ACK (1<<3) /* Acknowledge from slave */ - /* 1 - ACK */ - /* 0 - NACK */ -#define OC_I2C_IACK (1<<0) /* Interrupt acknowledge */ - -/* ----- Status register bits */ - -#define OC_I2C_RXACK (1<<7) /* ACK received from slave */ - /* 1 - ACK */ - /* 0 - NACK */ -#define OC_I2C_BUSY (1<<6) /* Busy bit */ -#define OC_I2C_TIP (1<<1) /* Transfer in progress */ -#define OC_I2C_IF (1<<0) /* Interrupt flag */ - -/* bit testing and setting macros */ - -#define OC_ISSET(reg,bitmask) ((reg)&(bitmask)) -#define OC_ISCLEAR(reg,bitmask) (!(OC_ISSET(reg,bitmask))) -#define OC_BITSET(reg,bitmask) ((reg)|(bitmask)) -#define OC_BITCLEAR(reg,bitmask) ((reg)|(~(bitmask))) -#define OC_BITTOGGLE(reg,bitmask) ((reg)^(bitmask)) -#define OC_REGMOVE(reg,value) ((reg)=(value)) \ No newline at end of file diff --git a/fpga/usrp2/opencores/simple_gpio/rtl/simple_gpio.v b/fpga/usrp2/opencores/simple_gpio/rtl/simple_gpio.v deleted file mode 100644 index 0b78f9921..000000000 --- a/fpga/usrp2/opencores/simple_gpio/rtl/simple_gpio.v +++ /dev/null @@ -1,193 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// OpenCores Simple General Purpose IO core //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: simple_gpio.v,v 1.2 2002/12/22 16:10:17 rherveille Exp $ -// -// $Date: 2002/12/22 16:10:17 $ -// $Revision: 1.2 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: simple_gpio.v,v $ -// Revision 1.2 2002/12/22 16:10:17 rherveille -// Fixed some typos in the documentation section. -// -// - - - -// -// Very basic 8bit GPIO core -// -// -// Registers: -// -// 0x00: Control Register -// bits 7:0 R/W Input/Output '1' = output mode -// '0' = input mode -// 0x01: Line Register -// bits 7:0 R Status Current GPIO pin level -// W Output GPIO pin output level -// -// -// HOWTO: -// -// Use a pin as an input: -// Program the corresponding bit in the control register to 'input mode' ('0'). -// The pin's state (input level) can be checked by reading the Line Register. -// Writing to the GPIO pin's Line Register bit while in input mode has no effect. -// -// Use a pin as an output: -// Program the corresponding bit in the control register to 'output mode' ('1'). -// Program the GPIO pin's output level by writing to the corresponding bit in -// the Line Register. -// Reading the GPIO pin's Line Register bit while in output mode returns the -// current output level. -// -// Addapt the core for fewer GPIOs: -// If less than 8 GPIOs are required, than the 'io' parameter can be set to -// the amount of required interrupts. GPIOs are mapped starting at the LSBs. -// So only the 'io' LSBs per register are valid. -// All other bits (i.e. the 8-'io' MSBs) are set to zero '0'. -// Codesize is approximately linear to the amount of interrupts. I.e. using -// 4 instead of 8 GPIO sources reduces the size by approx. half. -// - - -// synopsys translate_off -`include "timescale.v" -// synopsys translate_on - -module simple_gpio( - clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o, - gpio -); - - // - // Inputs & outputs - // - parameter io = 8; // number of GPIOs - - // 8bit WISHBONE bus slave interface - input clk_i; // clock - input rst_i; // reset (asynchronous active low) - input cyc_i; // cycle - input stb_i; // strobe - input adr_i; // address adr_i[1] - input we_i; // write enable - input [ 7:0] dat_i; // data output - output [ 7:0] dat_o; // data input - output ack_o; // normal bus termination - - // GPIO pins - inout [io:1] gpio; - - // - // Module body - // - reg [io:1] ctrl, line; // ControlRegister, LineRegister - reg [io:1] lgpio, llgpio; // LatchedGPIO pins - - // - // perform parameter checks - // - // synopsys translate_off - initial - begin - if(io > 8) - $display("simple_gpio: max. 8 GPIOs supported."); - end - // synopsys translate_on - - // - // WISHBONE interface - - wire wb_acc = cyc_i & stb_i; // WISHBONE access - wire wb_wr = wb_acc & we_i; // WISHBONE write access - - always @(posedge clk_i or negedge rst_i) - if (~rst_i) - begin - ctrl <= #1 {io{1'b0}}; - line <= #1 {io{1'b0}}; - end - else if (wb_wr) - if ( adr_i ) - line <= #1 dat_i[io-1:0]; - else - ctrl <= #1 dat_i[io-1:0]; - - - reg [7:0] dat_o; - always @(posedge clk_i) - if ( adr_i ) - dat_o <= #1 { {(8-io){1'b0}}, llgpio}; - else - dat_o <= #1 { {(8-io){1'b0}}, ctrl}; - - reg ack_o; - always @(posedge clk_i or negedge rst_i) - if (~rst_i) - ack_o <= #1 1'b0; - else - ack_o <= #1 wb_acc & !ack_o; - - - // - // GPIO section - - // latch GPIO input pins - always @(posedge clk_i) - lgpio <= #1 gpio; - - // latch again (reduce meta-stability risc) - always @(posedge clk_i) - llgpio <= #1 lgpio; - - // assign GPIO outputs - integer n; - reg [io:1] igpio; // temporary internal signal - - always @(ctrl or line) - for(n=1;n<=io;n=n+1) - igpio[n] <= ctrl[n] ? line[n] : 1'bz; - - assign gpio = igpio; - -endmodule - diff --git a/fpga/usrp2/opencores/simple_pic/rtl/simple_pic.v b/fpga/usrp2/opencores/simple_pic/rtl/simple_pic.v deleted file mode 100644 index 28184cbe2..000000000 --- a/fpga/usrp2/opencores/simple_pic/rtl/simple_pic.v +++ /dev/null @@ -1,228 +0,0 @@ - -// Modified by M. Ettus, 2008 for 32 bit width - -///////////////////////////////////////////////////////////////////// -//// //// -//// OpenCores Simple Programmable Interrupt Controller //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// -// -// This is a simple Programmable Interrupt Controller. -// The number of interrupts is depending on the databus size. -// There's one interrupt input per databit (i.e. 16 interrupts for a 16 -// bit databus). -// All attached devices share the same CPU priority level. -// -// -// -// Registers: -// -// 0x00: EdgeEnable Register -// bits 7:0 R/W Edge Enable '1' = edge triggered interrupt source -// '0' = level triggered interrupt source -// 0x01: PolarityRegister -// bits 7:0 R/W Polarity '1' = high level / rising edge -// '0' = low level / falling edge -// 0x02: MaskRegister -// bits 7:0 R/W Mask '1' = interrupt masked (disabled) -// '0' = interrupt not masked (enabled) -// 0x03: PendingRegister -// bits 7:0 R/W Pending '1' = interrupt pending -// '0' = no interrupt pending -// -// A CPU interrupt is generated when an interrupt is pending and its -// MASK bit is cleared. -// -// -// -// HOWTO: -// -// Clearing pending interrupts: -// Writing a '1' to a bit in the interrupt pending register clears the -// interrupt. Make sure to clear the interrupt at the source before -// writing to the interrupt pending register. Otherwise the interrupt -// will be set again. -// -// Priority based interrupts: -// Upon reception of an interrupt, check the interrupt register and -// determine the highest priority interrupt. Mask all interrupts from the -// current level to the lowest level. This negates the interrupt line, and -// makes sure only interrupts with a higher level are triggered. After -// completion of the interrupt service routine, clear the interrupt source, -// the interrupt bit in the pending register, and restore the MASK register -// to it's previous state. -// -// Addapt the core for fewer interrupt sources: -// If less than 8 interrupt sources are required, than the 'is' parameter -// can be set to the amount of required interrupts. Interrupts are mapped -// starting at the LSBs. So only the 'is' LSBs per register are valid. All -// other bits (i.e. the 8-'is' MSBs) are set to zero '0'. -// Codesize is approximately linear to the amount of interrupts. I.e. using -// 4 instead of 8 interrupt sources reduces the size by approx. half. -// - - -module simple_pic( - clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o, int_o, - irq -); - parameter is = 8; // Number of interrupt sources - parameter dwidth = 32; - // - // Inputs & outputs - // - - // 8bit WISHBONE bus slave interface - input clk_i; // clock - input rst_i; // reset (asynchronous active low) - input cyc_i; // cycle - input stb_i; // strobe (cycle and strobe are the same signal) - input [ 2:1] adr_i; // address - input we_i; // write enable - input [ dwidth-1:0] dat_i; // data output - output [ dwidth-1:0] dat_o; // data input - output ack_o; // normal bus termination - - output int_o; // interrupt output - - // - // Interrupt sources - // - input [is:1] irq; // interrupt request inputs - - - // - // Module body - // - reg [is:1] pol, edgen, pending, mask; // register bank - reg [is:1] lirq, dirq; // latched irqs, delayed latched irqs - - - // - // perform parameter checks - // - // synopsys translate_off - initial - begin - if(is > dwidth) - $display("simple_pic: max number of interrupts = data bus width."); - end - // synopsys translate_on - - // - // latch interrupt inputs - always @(posedge clk_i) - lirq <= #1 irq; - - // - // generate delayed latched irqs - always @(posedge clk_i) - dirq <= #1 lirq; - - - // - // generate actual triggers - function trigger; - input edgen, pol, lirq, dirq; - - reg edge_irq, level_irq; - begin - edge_irq = pol ? (lirq & ~dirq) : (dirq & ~lirq); - level_irq = pol ? lirq : ~lirq; - - trigger = edgen ? edge_irq : level_irq; - end - endfunction - - reg [is:1] irq_event; - integer n; - always @(posedge clk_i) - for(n=1; n<=is; n=n+1) - irq_event[n] <= #1 trigger(edgen[n], pol[n], lirq[n], dirq[n]); - - // - // generate wishbone register bank writes - wire wb_acc = cyc_i & stb_i; // WISHBONE access - wire wb_wr = wb_acc & we_i; // WISHBONE write access - - always @(posedge clk_i) - if (rst_i) - begin - pol <= #1 {is{1'b0}}; // clear polarity register - edgen <= #1 {is{1'b0}}; // clear edge enable register - mask <= #1 {is{1'b1}}; // mask all interrupts - end - else if(wb_wr) // wishbone write cycle?? - case (adr_i) // synopsys full_case parallel_case - 2'b00: edgen <= #1 dat_i[is-1:0]; // EDGE-ENABLE register - 2'b01: pol <= #1 dat_i[is-1:0]; // POLARITY register - 2'b10: mask <= #1 dat_i[is-1:0]; // MASK register - 2'b11: ; // PENDING register is a special case (see below) - endcase - - - // pending register is a special case - always @(posedge clk_i) - if (rst_i) - pending <= #1 {is{1'b0}}; // clear all pending interrupts - else if ( wb_wr & (&adr_i) ) - pending <= #1 (pending & ~dat_i[is-1:0]) | irq_event; - else - pending <= #1 pending | irq_event; - - // - // generate dat_o - reg [dwidth-1:0] dat_o; - always @(posedge clk_i) - case (adr_i) // synopsys full_case parallel_case - 2'b00: dat_o <= #1 { {(dwidth-is){1'b0}}, edgen}; - 2'b01: dat_o <= #1 { {(dwidth-is){1'b0}}, pol}; - 2'b10: dat_o <= #1 { {(dwidth-is){1'b0}}, mask}; - 2'b11: dat_o <= #1 { {(dwidth-is){1'b0}}, pending}; - endcase - - // - // generate ack_o - reg ack_o; - always @(posedge clk_i) - ack_o <= #1 wb_acc & !ack_o; - - // - // generate CPU interrupt signal - reg int_o; - always @(posedge clk_i) - if(rst_i) - int_o <= #1 0; - else - int_o <= #1 |(pending & ~mask); - -endmodule - diff --git a/fpga/usrp2/opencores/spi/bench/verilog/spi_slave_model.v b/fpga/usrp2/opencores/spi/bench/verilog/spi_slave_model.v deleted file mode 100644 index dfdaed929..000000000 --- a/fpga/usrp2/opencores/spi/bench/verilog/spi_slave_model.v +++ /dev/null @@ -1,73 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// spi_slave_model.v //// -//// //// -//// This file is part of the SPI IP core project //// -//// http://www.opencores.org/projects/spi/ //// -//// //// -//// Author(s): //// -//// - Simon Srot (simons@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`include "timescale.v" - -module spi_slave_model (rst, ss, sclk, mosi, miso); - - input rst; // reset - input ss; // slave select - input sclk; // serial clock - input mosi; // master out slave in - output miso; // master in slave out - - reg miso; - - reg rx_negedge; // slave receiving on negedge - reg tx_negedge; // slave transmiting on negedge - reg [31:0] data; // data register - - parameter Tp = 1; - - always @(posedge(sclk && !rx_negedge) or negedge(sclk && rx_negedge) or rst) - begin - if (rst) - data <= #Tp 32'b0; - else if (!ss) - data <= #Tp {data[30:0], mosi}; - end - - always @(posedge(sclk && !tx_negedge) or negedge(sclk && tx_negedge)) - begin - miso <= #Tp data[31]; - end - -endmodule - diff --git a/fpga/usrp2/opencores/spi/bench/verilog/tb_spi_top.v b/fpga/usrp2/opencores/spi/bench/verilog/tb_spi_top.v deleted file mode 100644 index 529c0aca1..000000000 --- a/fpga/usrp2/opencores/spi/bench/verilog/tb_spi_top.v +++ /dev/null @@ -1,339 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// tb_spi_top.v //// -//// //// -//// This file is part of the SPI IP core project //// -//// http://www.opencores.org/projects/spi/ //// -//// //// -//// Author(s): //// -//// - Simon Srot (simons@opencores.org) //// -//// //// -//// Based on: //// -//// - i2c/bench/verilog/tst_bench_top.v //// -//// Copyright (C) 2001 Richard Herveille //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`include "timescale.v" - -module tb_spi_top(); - - reg clk; - reg rst; - wire [31:0] adr; - wire [31:0] dat_i, dat_o; - wire we; - wire [3:0] sel; - wire stb; - wire cyc; - wire ack; - wire err; - wire int; - - wire [7:0] ss; - wire sclk; - wire mosi; - wire miso; - - reg [31:0] q; - reg [31:0] q1; - reg [31:0] q2; - reg [31:0] q3; - reg [31:0] result; - - parameter SPI_RX_0 = 5'h0; - parameter SPI_RX_1 = 5'h4; - parameter SPI_RX_2 = 5'h8; - parameter SPI_RX_3 = 5'hc; - parameter SPI_TX_0 = 5'h0; - parameter SPI_TX_1 = 5'h4; - parameter SPI_TX_2 = 5'h8; - parameter SPI_TX_3 = 5'hc; - parameter SPI_CTRL = 5'h10; - parameter SPI_DIVIDE = 5'h14; - parameter SPI_SS = 5'h18; - - // Generate clock - always #5 clk = ~clk; - - // Wishbone master model - wb_master_model #(32, 32) i_wb_master ( - .clk(clk), .rst(rst), - .adr(adr), .din(dat_i), .dout(dat_o), - .cyc(cyc), .stb(stb), .we(we), .sel(sel), .ack(ack), .err(err), .rty(1'b0) - ); - - // SPI master core - spi_top i_spi_top ( - .wb_clk_i(clk), .wb_rst_i(rst), - .wb_adr_i(adr[4:0]), .wb_dat_i(dat_o), .wb_dat_o(dat_i), - .wb_sel_i(sel), .wb_we_i(we), .wb_stb_i(stb), - .wb_cyc_i(cyc), .wb_ack_o(ack), .wb_err_o(err), .wb_int_o(int), - .ss_pad_o(ss), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) - ); - - // SPI slave model - spi_slave_model i_spi_slave ( - .rst(rst), .ss(ss[0]), .sclk(sclk), .mosi(mosi), .miso(miso) - ); - - initial - begin - $display("\nstatus: %t Testbench started\n\n", $time); - - $dumpfile("bench.vcd"); - $dumpvars(1, tb_spi_top); - $dumpvars(1, tb_spi_top.i_spi_slave); - - // Initial values - clk = 0; - - i_spi_slave.rx_negedge = 1'b0; - i_spi_slave.tx_negedge = 1'b0; - - result = 32'h0; - - // Reset system - rst = 1'b0; // negate reset - #2; - rst = 1'b1; // assert reset - repeat(20) @(posedge clk); - rst = 1'b0; // negate reset - - $display("status: %t done reset", $time); - - @(posedge clk); - - // Program core - i_wb_master.wb_write(0, SPI_DIVIDE, 32'h00); // set devider register - i_wb_master.wb_write(0, SPI_TX_0, 32'h5a); // set tx register to 0x5a - i_wb_master.wb_write(0, SPI_CTRL, 32'h208); // set 8 bit transfer - i_wb_master.wb_write(0, SPI_SS, 32'h01); // set ss 0 - - $display("status: %t programmed registers", $time); - - i_wb_master.wb_cmp(0, SPI_DIVIDE, 32'h00); // verify devider register - i_wb_master.wb_cmp(0, SPI_TX_0, 32'h5a); // verify tx register - i_wb_master.wb_cmp(0, SPI_CTRL, 32'h208); // verify tx register - i_wb_master.wb_cmp(0, SPI_SS, 32'h01); // verify ss register - - $display("status: %t verified registers", $time); - - i_spi_slave.rx_negedge = 1'b1; - i_spi_slave.tx_negedge = 1'b0; - i_spi_slave.data[31:0] = 32'ha5967e5a; - i_wb_master.wb_write(0, SPI_CTRL, 32'h308); // set 8 bit transfer, start transfer - - $display("status: %t generate transfer: 8 bit, msb first, tx posedge, rx negedge", $time); - - // Check bsy bit - i_wb_master.wb_read(0, SPI_CTRL, q); - while (q[8]) - i_wb_master.wb_read(1, SPI_CTRL, q); - - i_wb_master.wb_read(1, SPI_RX_0, q); - result = result + q; - - if (i_spi_slave.data[7:0] == 8'h5a && q == 32'h000000a5) - $display("status: %t transfer completed: ok", $time); - else - $display("status: %t transfer completed: nok", $time); - - i_spi_slave.rx_negedge = 1'b0; - i_spi_slave.tx_negedge = 1'b1; - i_wb_master.wb_write(0, SPI_TX_0, 32'ha5); - i_wb_master.wb_write(0, SPI_CTRL, 32'h408); // set 8 bit transfer, tx negedge - i_wb_master.wb_write(0, SPI_CTRL, 32'h508); // set 8 bit transfer, tx negedge, start transfer - - $display("status: %t generate transfer: 8 bit, msb first, tx negedge, rx posedge", $time); - - // Check bsy bit - i_wb_master.wb_read(0, SPI_CTRL, q); - while (q[8]) - i_wb_master.wb_read(1, SPI_CTRL, q); - - i_wb_master.wb_read(1, SPI_RX_0, q); - result = result + q; - - if (i_spi_slave.data[7:0] == 8'ha5 && q == 32'h00000096) - $display("status: %t transfer completed: ok", $time); - else - $display("status: %t transfer completed: nok", $time); - - i_spi_slave.rx_negedge = 1'b0; - i_spi_slave.tx_negedge = 1'b1; - i_wb_master.wb_write(0, SPI_TX_0, 32'h5aa5); - i_wb_master.wb_write(0, SPI_CTRL, 32'hc10); // set 16 bit transfer, tx negedge, lsb - i_wb_master.wb_write(0, SPI_CTRL, 32'hd10); // set 16 bit transfer, tx negedge, start transfer - - $display("status: %t generate transfer: 16 bit, lsb first, tx negedge, rx posedge", $time); - - // Check bsy bit - i_wb_master.wb_read(0, SPI_CTRL, q); - while (q[8]) - i_wb_master.wb_read(1, SPI_CTRL, q); - - i_wb_master.wb_read(1, SPI_RX_0, q); - result = result + q; - - if (i_spi_slave.data[15:0] == 16'ha55a && q == 32'h00005a7e) - $display("status: %t transfer completed: ok", $time); - else - $display("status: %t transfer completed: nok", $time); - - i_spi_slave.rx_negedge = 1'b1; - i_spi_slave.tx_negedge = 1'b0; - i_wb_master.wb_write(0, SPI_TX_0, 32'h76543210); - i_wb_master.wb_write(0, SPI_TX_1, 32'hfedcba98); - i_wb_master.wb_write(0, SPI_CTRL, 32'h1a40); // set 64 bit transfer, rx negedge, lsb - i_wb_master.wb_write(0, SPI_CTRL, 32'h1b40); // set 64 bit transfer, rx negedge, start transfer - - $display("status: %t generate transfer: 64 bit, lsb first, tx posedge, rx negedge", $time); - - // Check bsy bit - i_wb_master.wb_read(0, SPI_CTRL, q); - while (q[8]) - i_wb_master.wb_read(1, SPI_CTRL, q); - - i_wb_master.wb_read(1, SPI_RX_0, q); - result = result + q; - i_wb_master.wb_read(1, SPI_RX_1, q1); - result = result + q1; - - if (i_spi_slave.data == 32'h195d3b7f && q == 32'h5aa5a55a && q1 == 32'h76543210) - $display("status: %t transfer completed: ok", $time); - else - $display("status: %t transfer completed: nok", $time); - - i_spi_slave.rx_negedge = 1'b0; - i_spi_slave.tx_negedge = 1'b1; - i_wb_master.wb_write(0, SPI_TX_0, 32'hccddeeff); - i_wb_master.wb_write(0, SPI_TX_1, 32'h8899aabb); - i_wb_master.wb_write(0, SPI_TX_2, 32'h44556677); - i_wb_master.wb_write(0, SPI_TX_3, 32'h00112233); - i_wb_master.wb_write(0, SPI_CTRL, 32'h400); - i_wb_master.wb_write(0, SPI_CTRL, 32'h500); - - $display("status: %t generate transfer: 128 bit, msb first, tx posedge, rx negedge", $time); - - // Check bsy bit - i_wb_master.wb_read(0, SPI_CTRL, q); - while (q[8]) - i_wb_master.wb_read(1, SPI_CTRL, q); - - i_wb_master.wb_read(1, SPI_RX_0, q); - result = result + q; - i_wb_master.wb_read(1, SPI_RX_1, q1); - result = result + q1; - i_wb_master.wb_read(1, SPI_RX_2, q2); - result = result + q2; - i_wb_master.wb_read(1, SPI_RX_3, q3); - result = result + q3; - - if (i_spi_slave.data == 32'hccddeeff && q == 32'h8899aabb && q1 == 32'h44556677 && q2 == 32'h00112233 && q3 == 32'h195d3b7f) - $display("status: %t transfer completed: ok", $time); - else - $display("status: %t transfer completed: nok", $time); - - i_spi_slave.rx_negedge = 1'b0; - i_spi_slave.tx_negedge = 1'b1; - i_wb_master.wb_write(0, SPI_TX_0, 32'haa55a5a5); - i_wb_master.wb_write(0, SPI_CTRL, 32'h1420); - i_wb_master.wb_write(0, SPI_CTRL, 32'h1520); - - $display("status: %t generate transfer: 32 bit, msb first, tx negedge, rx posedge, ie", $time); - - // Check interrupt signal - while (!int) - @(posedge clk); - - i_wb_master.wb_read(1, SPI_RX_0, q); - result = result + q; - - @(posedge clk); - if (!int && i_spi_slave.data == 32'haa55a5a5 && q == 32'hccddeeff) - $display("status: %t transfer completed: ok", $time); - else - $display("status: %t transfer completed: nok", $time); - - i_spi_slave.rx_negedge = 1'b1; - i_spi_slave.tx_negedge = 1'b0; - i_wb_master.wb_write(0, SPI_TX_0, 32'h01248421); - i_wb_master.wb_write(0, SPI_CTRL, 32'h3220); - i_wb_master.wb_write(0, SPI_CTRL, 32'h3320); - - $display("status: %t generate transfer: 32 bit, msb first, tx posedge, rx negedge, ie, ass", $time); - - while (!int) - @(posedge clk); - - i_wb_master.wb_read(1, SPI_RX_0, q); - result = result + q; - - @(posedge clk); - if (!int && i_spi_slave.data == 32'h01248421 && q == 32'haa55a5a5) - $display("status: %t transfer completed: ok", $time); - else - $display("status: %t transfer completed: nok", $time); - - i_spi_slave.rx_negedge = 1'b1; - i_spi_slave.tx_negedge = 1'b0; - i_wb_master.wb_write(0, SPI_TX_0, 32'h1); - i_wb_master.wb_write(0, SPI_CTRL, 32'h3201); - i_wb_master.wb_write(0, SPI_CTRL, 32'h3301); - - $display("status: %t generate transfer: 1 bit, msb first, tx posedge, rx negedge, ie, ass", $time); - - while (!int) - @(posedge clk); - - i_wb_master.wb_read(1, SPI_RX_0, q); - result = result + q; - - @(posedge clk); - if (!int && i_spi_slave.data == 32'h02490843 && q == 32'h0) - $display("status: %t transfer completed: ok", $time); - else - $display("status: %t transfer completed: nok", $time); - - $display("\n\nstatus: %t Testbench done", $time); - - #25000; // wait 25us - - $display("report (%h)", (result ^ 32'h2e8b36ab) + 32'hdeaddead); - $display("exit (%h)", result ^ 32'h2e8b36ab); - - $stop; - end - -endmodule - - diff --git a/fpga/usrp2/opencores/spi/bench/verilog/wb_master_model.v b/fpga/usrp2/opencores/spi/bench/verilog/wb_master_model.v deleted file mode 100644 index 3f8b7ee6a..000000000 --- a/fpga/usrp2/opencores/spi/bench/verilog/wb_master_model.v +++ /dev/null @@ -1,176 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// wb_master_model.v //// -//// //// -//// This file is part of the SPI IP core project //// -//// http://www.opencores.org/projects/spi/ //// -//// //// -//// Author(s): //// -//// - Simon Srot (simons@opencores.org) //// -//// //// -//// Based on: //// -//// - i2c/bench/verilog/wb_master_model.v //// -//// Copyright (C) 2001 Richard Herveille //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`include "timescale.v" - -module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty); - - parameter dwidth = 32; - parameter awidth = 32; - - input clk, rst; - output [awidth -1:0] adr; - input [dwidth -1:0] din; - output [dwidth -1:0] dout; - output cyc, stb; - output we; - output [dwidth/8 -1:0] sel; - input ack, err, rty; - - // Internal signals - reg [awidth -1:0] adr; - reg [dwidth -1:0] dout; - reg cyc, stb; - reg we; - reg [dwidth/8 -1:0] sel; - - reg [dwidth -1:0] q; - - // Memory Logic - initial - begin - adr = {awidth{1'bx}}; - dout = {dwidth{1'bx}}; - cyc = 1'b0; - stb = 1'bx; - we = 1'hx; - sel = {dwidth/8{1'bx}}; - #1; - end - - // Wishbone write cycle - task wb_write; - input delay; - integer delay; - - input [awidth -1:0] a; - input [dwidth -1:0] d; - - begin - - // wait initial delay - repeat(delay) @(posedge clk); - - // assert wishbone signal - #1; - adr = a; - dout = d; - cyc = 1'b1; - stb = 1'b1; - we = 1'b1; - sel = {dwidth/8{1'b1}}; - @(posedge clk); - - // wait for acknowledge from slave - while(~ack) @(posedge clk); - - // negate wishbone signals - #1; - cyc = 1'b0; - stb = 1'bx; - adr = {awidth{1'bx}}; - dout = {dwidth{1'bx}}; - we = 1'hx; - sel = {dwidth/8{1'bx}}; - - end - endtask - - // Wishbone read cycle - task wb_read; - input delay; - integer delay; - - input [awidth -1:0] a; - output [dwidth -1:0] d; - - begin - - // wait initial delay - repeat(delay) @(posedge clk); - - // assert wishbone signals - #1; - adr = a; - dout = {dwidth{1'bx}}; - cyc = 1'b1; - stb = 1'b1; - we = 1'b0; - sel = {dwidth/8{1'b1}}; - @(posedge clk); - - // wait for acknowledge from slave - while(~ack) @(posedge clk); - - // negate wishbone signals - #1; - cyc = 1'b0; - stb = 1'bx; - adr = {awidth{1'bx}}; - dout = {dwidth{1'bx}}; - we = 1'hx; - sel = {dwidth/8{1'bx}}; - d = din; - - end - endtask - - // Wishbone compare cycle (read data from location and compare with expected data) - task wb_cmp; - input delay; - integer delay; - - input [awidth -1:0] a; - input [dwidth -1:0] d_exp; - - begin - wb_read (delay, a, q); - - if (d_exp !== q) - $display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time); - end - endtask - -endmodule - diff --git a/fpga/usrp2/opencores/spi/doc/spi.pdf b/fpga/usrp2/opencores/spi/doc/spi.pdf deleted file mode 100644 index d88ee2807..000000000 Binary files a/fpga/usrp2/opencores/spi/doc/spi.pdf and /dev/null differ diff --git a/fpga/usrp2/opencores/spi/doc/src/spi.doc b/fpga/usrp2/opencores/spi/doc/src/spi.doc deleted file mode 100755 index b04700177..000000000 Binary files a/fpga/usrp2/opencores/spi/doc/src/spi.doc and /dev/null differ diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v deleted file mode 100644 index 2d9c34f40..000000000 --- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v +++ /dev/null @@ -1,105 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// spi_clgen.v //// -//// //// -//// This file is part of the SPI IP core project //// -//// http://www.opencores.org/projects/spi/ //// -//// //// -//// Author(s): //// -//// - Simon Srot (simons@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`include "spi_defines.v" - -module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge); - - input clk_in; // input clock (system clock) - input rst; // reset - input enable; // clock enable - input go; // start transfer - input last_clk; // last clock - input [`SPI_DIVIDER_LEN-1:0] divider; // clock divider (output clock is divided by this value) - output clk_out; // output clock - output pos_edge; // pulse marking positive edge of clk_out - output neg_edge; // pulse marking negative edge of clk_out - - reg clk_out; - reg pos_edge; - reg neg_edge; - - reg [`SPI_DIVIDER_LEN-1:0] cnt; // clock counter - wire cnt_zero; // conter is equal to zero - wire cnt_one; // conter is equal to one - - - assign cnt_zero = cnt == {`SPI_DIVIDER_LEN{1'b0}}; - assign cnt_one = cnt == {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; - - // Counter counts half period - always @(posedge clk_in) - begin - if(rst) - cnt <= {`SPI_DIVIDER_LEN{1'b1}}; - else - begin - if(!enable || cnt_zero) - cnt <= divider; - else - cnt <= cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; - end - end - - // clk_out is asserted every other half period - always @(posedge clk_in) - begin - if(rst) - clk_out <= 1'b0; - else - clk_out <= (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out; - end - - // Pos and neg edge signals - always @(posedge clk_in) - begin - if(rst) - begin - pos_edge <= 1'b0; - neg_edge <= 1'b0; - end - else - begin - pos_edge <= (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable); - neg_edge <= (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable); - end - end -endmodule - diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v deleted file mode 100644 index 3e4dd0e3c..000000000 --- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v +++ /dev/null @@ -1,159 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// spi_define.v //// -//// //// -//// This file is part of the SPI IP core project //// -//// http://www.opencores.org/projects/spi/ //// -//// //// -//// Author(s): //// -//// - Simon Srot (simons@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -// -// Number of bits used for devider register. If used in system with -// low frequency of system clock this can be reduced. -// Use SPI_DIVIDER_LEN for fine tuning theexact number. -// -`define SPI_DIVIDER_LEN_8 -//`define SPI_DIVIDER_LEN_16 -//`define SPI_DIVIDER_LEN_24 -//`define SPI_DIVIDER_LEN_32 - -`ifdef SPI_DIVIDER_LEN_8 - `define SPI_DIVIDER_LEN 8 // Can be set from 1 to 8 -`endif -`ifdef SPI_DIVIDER_LEN_16 - `define SPI_DIVIDER_LEN 16 // Can be set from 9 to 16 -`endif -`ifdef SPI_DIVIDER_LEN_24 - `define SPI_DIVIDER_LEN 24 // Can be set from 17 to 24 -`endif -`ifdef SPI_DIVIDER_LEN_32 - `define SPI_DIVIDER_LEN 32 // Can be set from 25 to 32 -`endif - -// -// Maximum nuber of bits that can be send/received at once. -// Use SPI_MAX_CHAR for fine tuning the exact number, when using -// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8. -// -`define SPI_MAX_CHAR_128 -//`define SPI_MAX_CHAR_64 -//`define SPI_MAX_CHAR_32 -//`define SPI_MAX_CHAR_24 -//`define SPI_MAX_CHAR_16 -//`define SPI_MAX_CHAR_8 - -`ifdef SPI_MAX_CHAR_128 - `define SPI_MAX_CHAR 128 // Can only be set to 128 - `define SPI_CHAR_LEN_BITS 7 -`endif -`ifdef SPI_MAX_CHAR_64 - `define SPI_MAX_CHAR 64 // Can only be set to 64 - `define SPI_CHAR_LEN_BITS 6 -`endif -`ifdef SPI_MAX_CHAR_32 - `define SPI_MAX_CHAR 32 // Can be set from 25 to 32 - `define SPI_CHAR_LEN_BITS 5 -`endif -`ifdef SPI_MAX_CHAR_24 - `define SPI_MAX_CHAR 24 // Can be set from 17 to 24 - `define SPI_CHAR_LEN_BITS 5 -`endif -`ifdef SPI_MAX_CHAR_16 - `define SPI_MAX_CHAR 16 // Can be set from 9 to 16 - `define SPI_CHAR_LEN_BITS 4 -`endif -`ifdef SPI_MAX_CHAR_8 - `define SPI_MAX_CHAR 8 // Can be set from 1 to 8 - `define SPI_CHAR_LEN_BITS 3 -`endif - -// -// Number of device select signals. Use SPI_SS_NB for fine tuning the -// exact number. -// -//`define SPI_SS_NB_8 -`define SPI_SS_NB_16 -//`define SPI_SS_NB_24 -//`define SPI_SS_NB_32 - -`ifdef SPI_SS_NB_8 - `define SPI_SS_NB 8 // Can be set from 1 to 8 -`endif -`ifdef SPI_SS_NB_16 - `define SPI_SS_NB 16 // Can be set from 9 to 16 -`endif -`ifdef SPI_SS_NB_24 - `define SPI_SS_NB 24 // Can be set from 17 to 24 -`endif -`ifdef SPI_SS_NB_32 - `define SPI_SS_NB 32 // Can be set from 25 to 32 -`endif - -// -// Bits of WISHBONE address used for partial decoding of SPI registers. -// -`define SPI_OFS_BITS 4:2 - -// -// Register offset -// -`define SPI_RX_0 0 -`define SPI_RX_1 1 -`define SPI_RX_2 2 -`define SPI_RX_3 3 -`define SPI_TX_0 0 -`define SPI_TX_1 1 -`define SPI_TX_2 2 -`define SPI_TX_3 3 -`define SPI_CTRL 4 -`define SPI_DIVIDE 5 -`define SPI_SS 6 - -// -// Number of bits in ctrl register -// -`define SPI_CTRL_BIT_NB 14 - -// -// Control register bit position -// -`define SPI_CTRL_ASS 13 -`define SPI_CTRL_IE 12 -`define SPI_CTRL_LSB 11 -`define SPI_CTRL_TX_NEGEDGE 10 -`define SPI_CTRL_RX_NEGEDGE 9 -`define SPI_CTRL_GO 8 -`define SPI_CTRL_RES_1 7 -`define SPI_CTRL_CHAR_LEN 6:0 - diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v deleted file mode 100644 index ac3bb3f48..000000000 --- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v +++ /dev/null @@ -1,235 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// spi_shift.v //// -//// //// -//// This file is part of the SPI IP core project //// -//// http://www.opencores.org/projects/spi/ //// -//// //// -//// Author(s): //// -//// - Simon Srot (simons@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`include "spi_defines.v" - -module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, - pos_edge, neg_edge, rx_negedge, tx_negedge, - tip, last, - p_in, p_out, s_clk, s_in, s_out); - - input clk; // system clock - input rst; // reset - input [3:0] latch; // latch signal for storing the data in shift register - input [3:0] byte_sel; // byte select signals for storing the data in shift register - input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one) - input lsb; // lbs first on the line - input go; // start stansfer - input pos_edge; // recognize posedge of sclk - input neg_edge; // recognize negedge of sclk - input rx_negedge; // s_in is sampled on negative edge - input tx_negedge; // s_out is driven on negative edge - output tip; // transfer in progress - output last; // last bit - input [31:0] p_in; // parallel in - output [`SPI_MAX_CHAR-1:0] p_out; // parallel out - input s_clk; // serial clock - input s_in; // serial in - output s_out; // serial out - - reg s_out; - reg tip; - - reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count - reg [`SPI_MAX_CHAR-1:0] data; // shift register - wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position - wire [`SPI_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position - wire rx_clk; // rx clock enable - wire tx_clk; // tx clock enable - - assign p_out = data; - - assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1}; - assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) : - (rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1}); - - assign last = !(|cnt); - - assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk); - assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last; - - // Character bit counter - always @(posedge clk) - begin - if(rst) - cnt <= {`SPI_CHAR_LEN_BITS+1{1'b0}}; - else - begin - if(tip) - cnt <= pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt; - else - cnt <= !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len}; - end - end - - // Transfer in progress - always @(posedge clk) - begin - if(rst) - tip <= 1'b0; - else if(go && ~tip) - tip <= 1'b1; - else if(tip && last && pos_edge) - tip <= 1'b0; - end - - // Sending bits to the line - always @(posedge clk) - begin - if (rst) - s_out <= 1'b0; - else - s_out <= (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out; - end - - // Receiving bits from the line - always @(posedge clk) - begin - if (rst) - data <= {`SPI_MAX_CHAR{1'b0}}; -`ifdef SPI_MAX_CHAR_128 - else if (latch[0] && !tip) - begin - if (byte_sel[3]) - data[31:24] <= p_in[31:24]; - if (byte_sel[2]) - data[23:16] <= p_in[23:16]; - if (byte_sel[1]) - data[15:8] <= p_in[15:8]; - if (byte_sel[0]) - data[7:0] <= p_in[7:0]; - end - else if (latch[1] && !tip) - begin - if (byte_sel[3]) - data[63:56] <= p_in[31:24]; - if (byte_sel[2]) - data[55:48] <= p_in[23:16]; - if (byte_sel[1]) - data[47:40] <= p_in[15:8]; - if (byte_sel[0]) - data[39:32] <= p_in[7:0]; - end - else if (latch[2] && !tip) - begin - if (byte_sel[3]) - data[95:88] <= p_in[31:24]; - if (byte_sel[2]) - data[87:80] <= p_in[23:16]; - if (byte_sel[1]) - data[79:72] <= p_in[15:8]; - if (byte_sel[0]) - data[71:64] <= p_in[7:0]; - end - else if (latch[3] && !tip) - begin - if (byte_sel[3]) - data[127:120] <= p_in[31:24]; - if (byte_sel[2]) - data[119:112] <= p_in[23:16]; - if (byte_sel[1]) - data[111:104] <= p_in[15:8]; - if (byte_sel[0]) - data[103:96] <= p_in[7:0]; - end -`else -`ifdef SPI_MAX_CHAR_64 - else if (latch[0] && !tip) - begin - if (byte_sel[3]) - data[31:24] <= p_in[31:24]; - if (byte_sel[2]) - data[23:16] <= p_in[23:16]; - if (byte_sel[1]) - data[15:8] <= p_in[15:8]; - if (byte_sel[0]) - data[7:0] <= p_in[7:0]; - end - else if (latch[1] && !tip) - begin - if (byte_sel[3]) - data[63:56] <= p_in[31:24]; - if (byte_sel[2]) - data[55:48] <= p_in[23:16]; - if (byte_sel[1]) - data[47:40] <= p_in[15:8]; - if (byte_sel[0]) - data[39:32] <= p_in[7:0]; - end -`else - else if (latch[0] && !tip) - begin - `ifdef SPI_MAX_CHAR_8 - if (byte_sel[0]) - data[`SPI_MAX_CHAR-1:0] <= p_in[`SPI_MAX_CHAR-1:0]; - `endif - `ifdef SPI_MAX_CHAR_16 - if (byte_sel[0]) - data[7:0] <= p_in[7:0]; - if (byte_sel[1]) - data[`SPI_MAX_CHAR-1:8] <= p_in[`SPI_MAX_CHAR-1:8]; - `endif - `ifdef SPI_MAX_CHAR_24 - if (byte_sel[0]) - data[7:0] <= p_in[7:0]; - if (byte_sel[1]) - data[15:8] <= p_in[15:8]; - if (byte_sel[2]) - data[`SPI_MAX_CHAR-1:16] <= p_in[`SPI_MAX_CHAR-1:16]; - `endif - `ifdef SPI_MAX_CHAR_32 - if (byte_sel[0]) - data[7:0] <= p_in[7:0]; - if (byte_sel[1]) - data[15:8] <= p_in[15:8]; - if (byte_sel[2]) - data[23:16] <= p_in[23:16]; - if (byte_sel[3]) - data[`SPI_MAX_CHAR-1:24] <= p_in[`SPI_MAX_CHAR-1:24]; - `endif - end -`endif -`endif - else - data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]]; - end - -endmodule - diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v deleted file mode 100644 index 8289449a9..000000000 --- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v +++ /dev/null @@ -1,287 +0,0 @@ - -// Modified 2010 by Matt Ettus to remove old verilog style - -////////////////////////////////////////////////////////////////////// -//// //// -//// spi_top.v //// -//// //// -//// This file is part of the SPI IP core project //// -//// http://www.opencores.org/projects/spi/ //// -//// //// -//// Author(s): //// -//// - Simon Srot (simons@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -`include "spi_defines.v" - -module spi_top -( - // Wishbone signals - wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, - wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, - - // SPI signals - ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i -); - - // Wishbone signals - input wb_clk_i; // master clock input - input wb_rst_i; // synchronous active high reset - input [4:0] wb_adr_i; // lower address bits - input [32-1:0] wb_dat_i; // databus input - output [32-1:0] wb_dat_o; // databus output - input [3:0] wb_sel_i; // byte select inputs - input wb_we_i; // write enable input - input wb_stb_i; // stobe/core select signal - input wb_cyc_i; // valid bus cycle input - output wb_ack_o; // bus cycle acknowledge output - output wb_err_o; // termination w/ error - output wb_int_o; // interrupt request signal output - - // SPI signals - output [`SPI_SS_NB-1:0] ss_pad_o; // slave select - output sclk_pad_o; // serial clock - output mosi_pad_o; // master out slave in - input miso_pad_i; // master in slave out - - reg [32-1:0] wb_dat_o; - reg wb_ack_o; - reg wb_int_o; - - // Internal signals - reg [`SPI_DIVIDER_LEN-1:0] divider; // Divider register - reg [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register - reg [`SPI_SS_NB-1:0] ss; // Slave select register - reg [32-1:0] wb_dat; // wb data out - wire [`SPI_MAX_CHAR-1:0] rx; // Rx register - wire rx_negedge; // miso is sampled on negative edge - wire tx_negedge; // mosi is driven on negative edge - wire [`SPI_CHAR_LEN_BITS-1:0] char_len; // char len - wire go; // go - wire lsb; // lsb first on line - wire ie; // interrupt enable - wire ass; // automatic slave select - wire spi_divider_sel; // divider register select - wire spi_ctrl_sel; // ctrl register select - wire [3:0] spi_tx_sel; // tx_l register select - wire spi_ss_sel; // ss register select - wire tip; // transfer in progress - wire pos_edge; // recognize posedge of sclk - wire neg_edge; // recognize negedge of sclk - wire last_bit; // marks last character bit - - // Address decoder - assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DIVIDE); - assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL); - assign spi_tx_sel[0] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0); - assign spi_tx_sel[1] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_1); - assign spi_tx_sel[2] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_2); - assign spi_tx_sel[3] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_3); - assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS); - - // Read from registers - always @(wb_adr_i or rx or ctrl or divider or ss) - begin - case (wb_adr_i[`SPI_OFS_BITS]) -`ifdef SPI_MAX_CHAR_128 - `SPI_RX_0: wb_dat = rx[31:0]; - `SPI_RX_1: wb_dat = rx[63:32]; - `SPI_RX_2: wb_dat = rx[95:64]; - `SPI_RX_3: wb_dat = {{128-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:96]}; -`else -`ifdef SPI_MAX_CHAR_64 - `SPI_RX_0: wb_dat = rx[31:0]; - `SPI_RX_1: wb_dat = {{64-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:32]}; - `SPI_RX_2: wb_dat = 32'b0; - `SPI_RX_3: wb_dat = 32'b0; -`else - `SPI_RX_0: wb_dat = {{32-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:0]}; - `SPI_RX_1: wb_dat = 32'b0; - `SPI_RX_2: wb_dat = 32'b0; - `SPI_RX_3: wb_dat = 32'b0; -`endif -`endif - `SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl}; - `SPI_DIVIDE: wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider}; - `SPI_SS: wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss}; - default: wb_dat = 32'bx; - endcase - end - - // Wb data out - always @(posedge wb_clk_i) - begin - if (wb_rst_i) - wb_dat_o <= 32'b0; - else - wb_dat_o <= wb_dat; - end - - // Wb acknowledge - always @(posedge wb_clk_i) - begin - if (wb_rst_i) - wb_ack_o <= 1'b0; - else - wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o; - end - - // Wb error - assign wb_err_o = 1'b0; - - // Interrupt - always @(posedge wb_clk_i) - begin - if (wb_rst_i) - wb_int_o <= 1'b0; - else if (ie && tip && last_bit && pos_edge) - wb_int_o <= 1'b1; - else if (wb_ack_o) - wb_int_o <= 1'b0; - end - - // Divider register - always @(posedge wb_clk_i) - begin - if (wb_rst_i) - divider <= {`SPI_DIVIDER_LEN{1'b0}}; - else if (spi_divider_sel && wb_we_i && !tip) - begin - `ifdef SPI_DIVIDER_LEN_8 - if (wb_sel_i[0]) - divider <= wb_dat_i[`SPI_DIVIDER_LEN-1:0]; - `endif - `ifdef SPI_DIVIDER_LEN_16 - if (wb_sel_i[0]) - divider[7:0] <= wb_dat_i[7:0]; - if (wb_sel_i[1]) - divider[`SPI_DIVIDER_LEN-1:8] <= wb_dat_i[`SPI_DIVIDER_LEN-1:8]; - `endif - `ifdef SPI_DIVIDER_LEN_24 - if (wb_sel_i[0]) - divider[7:0] <= wb_dat_i[7:0]; - if (wb_sel_i[1]) - divider[15:8] <= wb_dat_i[15:8]; - if (wb_sel_i[2]) - divider[`SPI_DIVIDER_LEN-1:16] <= wb_dat_i[`SPI_DIVIDER_LEN-1:16]; - `endif - `ifdef SPI_DIVIDER_LEN_32 - if (wb_sel_i[0]) - divider[7:0] <= wb_dat_i[7:0]; - if (wb_sel_i[1]) - divider[15:8] <= wb_dat_i[15:8]; - if (wb_sel_i[2]) - divider[23:16] <= wb_dat_i[23:16]; - if (wb_sel_i[3]) - divider[`SPI_DIVIDER_LEN-1:24] <= wb_dat_i[`SPI_DIVIDER_LEN-1:24]; - `endif - end - end - - // Ctrl register - always @(posedge wb_clk_i) - begin - if (wb_rst_i) - ctrl <= {`SPI_CTRL_BIT_NB{1'b0}}; - else if(spi_ctrl_sel && wb_we_i && !tip) - begin - if (wb_sel_i[0]) - ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]}; - if (wb_sel_i[1]) - ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8]; - end - else if(tip && last_bit && pos_edge) - ctrl[`SPI_CTRL_GO] <= 1'b0; - end - - assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE]; - assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE]; - assign go = ctrl[`SPI_CTRL_GO]; - assign char_len = ctrl[`SPI_CTRL_CHAR_LEN]; - assign lsb = ctrl[`SPI_CTRL_LSB]; - assign ie = ctrl[`SPI_CTRL_IE]; - assign ass = ctrl[`SPI_CTRL_ASS]; - - // Slave select register - always @(posedge wb_clk_i) - begin - if (wb_rst_i) - ss <= {`SPI_SS_NB{1'b0}}; - else if(spi_ss_sel && wb_we_i && !tip) - begin - `ifdef SPI_SS_NB_8 - if (wb_sel_i[0]) - ss <= wb_dat_i[`SPI_SS_NB-1:0]; - `endif - `ifdef SPI_SS_NB_16 - if (wb_sel_i[0]) - ss[7:0] <= wb_dat_i[7:0]; - if (wb_sel_i[1]) - ss[`SPI_SS_NB-1:8] <= wb_dat_i[`SPI_SS_NB-1:8]; - `endif - `ifdef SPI_SS_NB_24 - if (wb_sel_i[0]) - ss[7:0] <= wb_dat_i[7:0]; - if (wb_sel_i[1]) - ss[15:8] <= wb_dat_i[15:8]; - if (wb_sel_i[2]) - ss[`SPI_SS_NB-1:16] <= wb_dat_i[`SPI_SS_NB-1:16]; - `endif - `ifdef SPI_SS_NB_32 - if (wb_sel_i[0]) - ss[7:0] <= wb_dat_i[7:0]; - if (wb_sel_i[1]) - ss[15:8] <= wb_dat_i[15:8]; - if (wb_sel_i[2]) - ss[23:16] <= wb_dat_i[23:16]; - if (wb_sel_i[3]) - ss[`SPI_SS_NB-1:24] <= wb_dat_i[`SPI_SS_NB-1:24]; - `endif - end - end - - assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}})); - - spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit), - .divider(divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge), - .neg_edge(neg_edge)); - - spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]), - .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(wb_sel_i), .lsb(lsb), - .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), - .rx_negedge(rx_negedge), .tx_negedge(tx_negedge), - .tip(tip), .last(last_bit), - .p_in(wb_dat_i), .p_out(rx), - .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o)); -endmodule - diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v deleted file mode 100644 index ee808a8ab..000000000 --- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v +++ /dev/null @@ -1,182 +0,0 @@ - -// Modified 2010 by Matt Ettus to remove old verilog style and -// allow 16-bit operation - -////////////////////////////////////////////////////////////////////// -//// //// -//// spi_top.v //// -//// //// -//// This file is part of the SPI IP core project //// -//// http://www.opencores.org/projects/spi/ //// -//// //// -//// Author(s): //// -//// - Simon Srot (simons@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -`include "spi_defines.v" - -module spi_top16 - (input wb_clk_i, input wb_rst_i, - input [4:0] wb_adr_i, - input [15:0] wb_dat_i, - output reg [15:0] wb_dat_o, - input [1:0] wb_sel_i, - input wb_we_i, input wb_stb_i, input wb_cyc_i, - output reg wb_ack_o, output wb_err_o, output reg wb_int_o, - - // SPI signals - output [15:0] ss_pad_o, output sclk_pad_o, output mosi_pad_o, input miso_pad_i); - - // Internal signals - reg [15:0] divider; // Divider register - reg [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register - reg [15:0] ss; // Slave select register - reg [31:0] wb_dat; // wb data out - wire [31:0] rx; // Rx register - wire rx_negedge; // miso is sampled on negative edge - wire tx_negedge; // mosi is driven on negative edge - wire [`SPI_CHAR_LEN_BITS-1:0] char_len; // char len - wire go; // go - wire lsb; // lsb first on line - wire ie; // interrupt enable - wire ass; // automatic slave select - wire spi_divider_sel; // divider register select - wire spi_ctrl_sel; // ctrl register select - wire [3:0] spi_tx_sel; // tx_l register select - wire spi_ss_sel; // ss register select - wire tip; // transfer in progress - wire pos_edge; // recognize posedge of sclk - wire neg_edge; // recognize negedge of sclk - wire last_bit; // marks last character bit - - // Address decoder - assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_DIVIDE); - assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_CTRL); - assign spi_tx_sel[0] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_0); - assign spi_tx_sel[1] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_1); - assign spi_tx_sel[2] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_2); - assign spi_tx_sel[3] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_3); - assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_SS); - - always @(wb_adr_i or rx or ctrl or divider or ss) - case (wb_adr_i[4:2]) - `SPI_RX_0: wb_dat = rx[31:0]; - `SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl}; - `SPI_DIVIDE: wb_dat = {16'b0, divider}; - `SPI_SS: wb_dat = {16'b0, ss}; - default : wb_dat = 32'd0; - endcase // case (wb_adr_i[4:2]) - - always @(posedge wb_clk_i) - if (wb_rst_i) - wb_dat_o <= 32'b0; - else - wb_dat_o <= wb_adr_i[1] ? wb_dat[31:16] : wb_dat[15:0]; - - always @(posedge wb_clk_i) - if (wb_rst_i) - wb_ack_o <= 1'b0; - else - wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o; - - assign wb_err_o = 1'b0; - - // Interrupt - always @(posedge wb_clk_i) - if (wb_rst_i) - wb_int_o <= 1'b0; - else if (ie && tip && last_bit && pos_edge) - wb_int_o <= 1'b1; - else if (wb_ack_o) - wb_int_o <= 1'b0; - - // Divider register - always @(posedge wb_clk_i) - if (wb_rst_i) - divider <= 16'b0; - else if (spi_divider_sel && wb_we_i && !tip && ~wb_adr_i[1]) - divider <= wb_dat_i; - - // Ctrl register - always @(posedge wb_clk_i) - if (wb_rst_i) - ctrl <= {`SPI_CTRL_BIT_NB{1'b0}}; - else if(spi_ctrl_sel && wb_we_i && !tip && ~wb_adr_i[1]) - begin - if (wb_sel_i[0]) - ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]}; - if (wb_sel_i[1]) - ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8]; - end - else if(tip && last_bit && pos_edge) - ctrl[`SPI_CTRL_GO] <= 1'b0; - - assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE]; - assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE]; - assign go = ctrl[`SPI_CTRL_GO]; - assign char_len = ctrl[`SPI_CTRL_CHAR_LEN]; - assign lsb = ctrl[`SPI_CTRL_LSB]; - assign ie = ctrl[`SPI_CTRL_IE]; - assign ass = ctrl[`SPI_CTRL_ASS]; - - // Slave select register - always @(posedge wb_clk_i) - if (wb_rst_i) - ss <= 16'b0; - else if(spi_ss_sel && wb_we_i && !tip & ~wb_adr_i[1]) - begin - if (wb_sel_i[0]) - ss[7:0] <= wb_dat_i[7:0]; - if (wb_sel_i[1]) - ss[15:8] <= wb_dat_i[15:8]; - end - - assign ss_pad_o = ~((ss & {16{tip & ass}}) | (ss & {16{!ass}})); - - spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit), - .divider(divider[`SPI_DIVIDER_LEN-1:0]), .clk_out(sclk_pad_o), .pos_edge(pos_edge), - .neg_edge(neg_edge)); - - wire [3:0] new_sels = { (wb_adr_i[1] & wb_sel_i[1]), (wb_adr_i[1] & wb_sel_i[0]), - (~wb_adr_i[1] & wb_sel_i[1]), (~wb_adr_i[1] & wb_sel_i[0]) }; - - - spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]), - .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(new_sels), .lsb(lsb), - .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), - .rx_negedge(rx_negedge), .tx_negedge(tx_negedge), - .tip(tip), .last(last_bit), - .p_in({wb_dat_i,wb_dat_i}), .p_out(rx), - .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o)); - -endmodule // spi_top16 diff --git a/fpga/usrp2/opencores/spi/sim/rtl_sim/run/rtl.fl b/fpga/usrp2/opencores/spi/sim/rtl_sim/run/rtl.fl deleted file mode 100644 index d84a0840d..000000000 --- a/fpga/usrp2/opencores/spi/sim/rtl_sim/run/rtl.fl +++ /dev/null @@ -1,3 +0,0 @@ -spi_top.v -spi_clgen.v -spi_shift.v diff --git a/fpga/usrp2/opencores/spi/sim/rtl_sim/run/run_sim b/fpga/usrp2/opencores/spi/sim/rtl_sim/run/run_sim deleted file mode 100755 index 1b13a35b9..000000000 --- a/fpga/usrp2/opencores/spi/sim/rtl_sim/run/run_sim +++ /dev/null @@ -1,108 +0,0 @@ -#!/bin/csh -f - -set current_par = 0 -set output_waveform = 0 -while ( $current_par < $# ) - @ current_par = $current_par + 1 - case wave: - @ output_waveform = 1 - breaksw - default: - echo 'Unknown option "'$argv[$current_par]'"!' - exit - breaksw - endsw -end - -echo "TEST: spi" - -#echo "-CDSLIB ./cds.lib" > ncvlog.args -#echo "-HDLVAR ./hdl.var" >> ncvlog.args -echo "-MESSAGES" > ncvlog.args -echo "-INCDIR ../../../bench/verilog" >> ncvlog.args -echo "-INCDIR ../../../rtl/verilog" >> ncvlog.args -echo "-NOCOPYRIGHT" >> ncvlog.args -echo "-UPDATE" >> ncvlog.args -echo "-LOGFILE ncvlog.log" >> ncvlog.args - -foreach filename ( `cat ./rtl.fl` ) - echo "../../../rtl/verilog/"$filename >> ncvlog.args -end - -foreach filename ( `cat ./sim.fl` ) - echo "../../../bench/verilog/"$filename >> ncvlog.args -end - -ncvlog -f ncvlog.args -if ($status != 0) then - echo "STATUS: failed" - exit -endif - - -echo "-MESSAGES" > ncelab.args -echo "-NOCOPYRIGHT" >> ncelab.args -#echo "-CDSLIB ./cds.lib" >> ncelab.args -#echo "-HDLVAR ./hdl.var" >> ncelab.args -echo "-LOGFILE ncelab.log" >> ncelab.args -echo "-SNAPSHOT worklib.tb_spi_top:v" >> ncelab.args -echo "-NOTIMINGCHECKS" >> ncelab.args -echo "-ACCESS +RWC" >> ncelab.args -echo "tb_spi_top" >> ncelab.args - -ncelab -f ncelab.args -if ($status != 0) then - echo "STATUS: failed" - exit -endif - - -echo "-MESSAGES" > ncsim.args -echo "-NOCOPYRIGHT" >> ncsim.args -#echo "-CDSLIB ./cds.lib" >> ncsim.args -#echo "-HDLVAR ./hdl.var" >> ncsim.args -echo "-INPUT ncsim.tcl" >> ncsim.args -echo "-LOGFILE ncsim.log" >> ncsim.args -echo "worklib.tb_spi_top:v" >> ncsim.args - -if ( $output_waveform ) then - echo "database -open waves -shm -into ../out/wav" > ./ncsim.tcl - echo "probe -create -database waves -shm tb_spi_top -all -depth all" >> ./ncsim.tcl - echo "stop -create -time 25000000 -relative" >> ./ncsim.tcl - echo "run" >> ./ncsim.tcl -else - echo "stop -create -time 25000000 -relative" >> ./ncsim.tcl - echo "run" > ./ncsim.tcl -endif - -echo "exit" >> ncsim.tcl - -ncsim -LICQUEUE -f ./ncsim.args - -set exit_line_nb = `sed -n '/exit/=' < ./ncsim.log` - -set dead_line_nb = 0 - -if ( $exit_line_nb ) then - - @ dead_line_nb = $exit_line_nb - 1 - set exit_line=`sed -n $exit_line_nb's/exit/&/gp' < ./ncsim.log` - set dead_line=`sed -n $dead_line_nb's/report/&/gp' < ./ncsim.log` - - if ( "$dead_line" == "report (deaddead)" ) then - if ( "$exit_line" == "exit (00000000)" ) then - echo "STATUS: passed" #|tee -a ./run_sim.log 2>&1 - else - echo "STATUS: failed" #|tee -a ./run_sim.log 2>&1 - endif - else - echo "STATUS: failed" - endif - -endif - -exit - - - - diff --git a/fpga/usrp2/opencores/spi/sim/rtl_sim/run/sim.fl b/fpga/usrp2/opencores/spi/sim/rtl_sim/run/sim.fl deleted file mode 100644 index 283aad1f8..000000000 --- a/fpga/usrp2/opencores/spi/sim/rtl_sim/run/sim.fl +++ /dev/null @@ -1,3 +0,0 @@ -tb_spi_top.v -wb_master_model.v -spi_slave_model.v diff --git a/fpga/usrp2/opencores/spi_boot/COMPILE_LIST b/fpga/usrp2/opencores/spi_boot/COMPILE_LIST deleted file mode 100644 index fc8f7d418..000000000 --- a/fpga/usrp2/opencores/spi_boot/COMPILE_LIST +++ /dev/null @@ -1,33 +0,0 @@ - -Compile list for the spi_boot core -================================== -Version: $Date: 2005/04/14 21:26:22 $ - -bench/vhdl/tb.vhd -rtl/vhdl/spi_boot_pack-p.vhd -bench/vhdl/tb_pack-p.vhd -bench/vhdl/tb_elem.vhd -rtl/vhdl/chip-e.vhd -rtl/vhdl/chip-full-a.vhd -rtl/vhdl/spi_boot.vhd -rtl/vhdl/spi_counter.vhd -rtl/vhdl/spi_counter-c.vhd -rtl/vhdl/spi_boot-c.vhd -rtl/vhdl/chip-full-c.vhd -bench/vhdl/card.vhd -bench/vhdl/card-c.vhd -bench/vhdl/tb_elem-full-c.vhd -rtl/vhdl/chip-mmc-a.vhd -rtl/vhdl/chip-mmc-c.vhd -bench/vhdl/tb_elem-mmc-c.vhd -rtl/vhdl/chip-sd-a.vhd -rtl/vhdl/chip-sd-c.vhd -bench/vhdl/tb_elem-sd-c.vhd -rtl/vhdl/chip-minimal-a.vhd -rtl/vhdl/chip-minimal-c.vhd -bench/vhdl/tb_elem-minimal-c.vhd -bench/vhdl/tb-c.vhd -bench/vhdl/tb_rl.vhd -rtl/vhdl/sample/ram_loader.vhd -rtl/vhdl/sample/ram_loader-c.vhd -bench/vhdl/tb_rl-c.vhd diff --git a/fpga/usrp2/opencores/spi_boot/COPYING b/fpga/usrp2/opencores/spi_boot/COPYING deleted file mode 100644 index 60549be51..000000000 --- a/fpga/usrp2/opencores/spi_boot/COPYING +++ /dev/null @@ -1,340 +0,0 @@ - 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If this is what you want to do, use the GNU Library General -Public License instead of this License. diff --git a/fpga/usrp2/opencores/spi_boot/KNOWN_BUGS b/fpga/usrp2/opencores/spi_boot/KNOWN_BUGS deleted file mode 100644 index 298e4ba2e..000000000 --- a/fpga/usrp2/opencores/spi_boot/KNOWN_BUGS +++ /dev/null @@ -1,4 +0,0 @@ - -Known bugs of the spi_boot core -=============================== -Version: $Date: 2005/02/13 18:28:35 $ diff --git a/fpga/usrp2/opencores/spi_boot/README b/fpga/usrp2/opencores/spi_boot/README deleted file mode 100644 index 926b35bff..000000000 --- a/fpga/usrp2/opencores/spi_boot/README +++ /dev/null @@ -1,170 +0,0 @@ - -README for the spi_boot core -============================ -Version: $Date: 2005/04/14 21:32:58 $ - - -Description ------------ - -The SD/MMC Bootloader is a CPLD design that manages configuration and -bootstrapping of FPGAs. It is able to retrieve the required data from -SecureDigital (SD) cards or MultiMediaCards (MMC) and manages the FPGA -configuration process. SD cards as well as MMCs are operated in SPI mode which -is part of both standards thus eliminating the need for dedicated -implementations. The SD/MMC Bootloader fits both. Beyond configuration, this -core supports a bootstrapping strategy where multiple images are stored on one -single memory card. -For example consider a system completely based on SRAM. The bootloader -provides the initial configuration data from the first image to the FPGA. This -image contains a design which pulls the next image from the memory card and -transfers this data to SRAM. In the third step the final FPGA design is loaded -from the third image. -These images are clustered in sets which can be selected by external switches -for example. Several configuration sets can be stored on one memory card -allowing you to provide a number of applications which are downloaded quickly -to the FPGA. -The schematic (rev. B) shows how the core can be used with an FPGA board. I -use it to configure/boot the Xilinx Spartan IIe on BurchED's B5-X300 -board. SV2 fits the "SERIAL MODE" connector on this board but you will have to -add a separate wire from R6 to attach INIT. Please check the proper use of the -pull-up resistors for your specific board. - - -Features --------- - -* Configuration mode: configures SRAM based FPGAs via slave serial mode - (Xilinx and Altera) -* Data mode: provides stored data over a simple synchronous serial interface -* Broad compatability using SPI mode - + SecureDigital cards using dedicated initialization command - + MultiMediaCards (see below) -* Operation triggerd by power-up or card insertion -* Multiple configuration sets stored on on single memory card - - -Compatability -------------- - -These cards have been tested with the SD/MMC Bootloader: - - * Hama 64 MB SD - * SanDisk 128 MB SD - * SanDisk 64 MB MMC - * Panasonic 32 MB SD - -Some MMC might fail with this core as not all cards support CMD18 -(READ_MULTIPLE_BLOCK). Please consult the data sheet of your specific -model. In case your MMC does not implement CMD18 you might want to have a look -at the FPGA MMC-Card Config project. - - -Tools ------ - -Downloading the configuration data to the card is a straight forward -process. The images have to be written starting at dedicated locations. For -the provided toplevel designs, these locations are multiples of 256 K. I.e. 0, -0x40000, 0x80000 and so forth. - -dd (part of the GNU coreutils) serves this purpose: -$ dd if=ram_loader.bin of=/dev/sdX bs=512 -$ dd if=pongrom_6.bin of=/dev/sdX bs=512 seek=512 -$ dd if=pacman.bin of=/dev/sdX bs=512 seek=1024 - -The name of the device node depends on how the card reader is attached to the -kernel. For Linux systems this is most often something like /dev/sdX with X -ranging from a-z. Please note that it is essential to use the device without -any trailing numbers as they refer to partitions leading to wrong offsets for -data written to the card. -All this works perfectly for my Spartan IIe device as this FPGA expects the -configuration data as it is delivered from the card: Consecutive bytes each -with its most significant bit first. Altera devices like the FLEX family are -different here. They expect the bytes with least significant bit -first. Therefore, the configuration data has to be swapped bitwise before it -is written to the card. - - -Verification ------------- - -The spi_boot core comes with a simple testbench that simulates an SD/MMC -card. All four implementations of the core are verified there in parallel -while transferring the data for several sets. -You should normally not need to run the testbench. But in case you modified -the VHDL code the testbench gives some hints if the design has been broken. - - -Directory Structure -------------------- - -The core's directory structure follows the proposal of OpenCores.org. - -spi_boot - | - \--+-- doc : Documentation - | | - | \-- src : Source files of documentation - | - +-- rtl - | | - | \-- vhdl : VHDL code containing the RTL description - | of the core. - | - +-- bench - | | - | \-- vhdl : VHDL testbench code. - | - \-- sim - | - \-- rtl_sim : Directory for running simulations. - - -RAM Loader ----------- - -Directory rtl/vhdl/ram_loader contains the sample design which loads the next -image from the card and stores its contents to external asynchronous -RAM. After reading 64 KB it triggers a new configuration process for the final -FPGA design. -Refer to the code for the mechanisms involved. - - -Compiling the VHDL Code ------------------------ - -VHDL compilation and simulation tasks take place inside in sim/rtl_sim -directory. The project setup supports only the GHDL simulator (see -http://ghdl.free.fr). - -To compile the code simply type at the shell - -$ make - -This should result in a file called tb_behav_c0 which can be executed as any -other executable. - -The basic simple sequence list can be found in COMPILE_LIST. This can be -useful to quickly set up the analyze stage of any compiler or -synthesizer. Especially when synthesizing the code, you want to skip the VHDL -configurations in *-c.vhd and everything below the bench/ directory. - - -References ----------- - - * SanDisk SD Card Product Manual - http://www.sandisk.com/pdf/oem/ProdManualSDCardv1.9.pdf - - * SanDisk MMC Product Manual - http://www.sandisk.com/pdf/oem/manual-rs-mmcv1.0.pdf - - * Toshiba SD Card Specification - http://i.cmpnet.com/chipcenter/memory/images/prod055.pdf - - * BurchED - http://burched.biz/ - - * FPGA MMC-Card Config project - http://www.opencores.org/projects.cgi/web/mmcfpgaconfig/overview diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/card-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/card-c.vhd deleted file mode 100644 index 797eb1c90..000000000 --- a/fpga/usrp2/opencores/spi_boot/bench/vhdl/card-c.vhd +++ /dev/null @@ -1,14 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: card-c.vhd,v 1.1 2005/02/08 21:09:18 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration card_behav_c0 of card is - - for behav - end for; - -end card_behav_c0; diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/card.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/card.vhd deleted file mode 100644 index dcd676095..000000000 --- a/fpga/usrp2/opencores/spi_boot/bench/vhdl/card.vhd +++ /dev/null @@ -1,446 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Simple SD and MMC model --- --- $Id: card.vhd,v 1.2 2005/02/13 17:06:22 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -entity card is - - generic ( - card_type_g : string := "none"; - is_sd_card_g : integer := 1 - ); - - port ( - spi_clk_i : in std_logic; - spi_cs_n_i : in std_logic; - spi_data_i : in std_logic; - spi_data_o : out std_logic - ); - -end card; - - -library ieee; -use ieee.numeric_std.all; -library std; -use std.textio.all; - -use work.tb_pack.all; - -architecture behav of card is - - signal power_on_n_s : std_logic; - signal soft_res_n_s : std_logic; - signal res_n_s : std_logic; - - signal rx_s : std_logic_vector(47 downto 0); - - signal set_spi_mode_s, - spi_mode_q : boolean; - signal set_idle_mode_s, - poll_idle_mode_s : boolean; - signal idle_mode_q : natural; - - signal block_len_q, - block_len_s : unsigned(31 downto 0); - signal set_block_len_s : boolean; - - signal new_read_addr_s, - read_addr_q : unsigned(31 downto 0); - signal set_read_addr_s, - inc_read_addr_s : boolean; - - signal cmd_spi_data_s, - read_spi_data_s : std_logic; - signal start_read_s : boolean; - signal reading_s : boolean; - - procedure rise_clk is - begin - wait until spi_clk_i'event and to_X01(spi_clk_i) = '1'; - end rise_clk; - --- procedure rise_clk(num : natural) is --- begin --- for i in 1 to num loop --- rise_clk; --- end loop; --- end rise_clk; - - procedure fall_clk is - begin - wait until spi_clk_i'event and to_X01(spi_clk_i) = '0'; - end fall_clk; - - procedure fall_clk(num : natural) is - begin - for i in 1 to num loop - fall_clk; - end loop; - end fall_clk; - -begin - - res_n_s <= power_on_n_s and soft_res_n_s; - - ----------------------------------------------------------------------------- - -- Power on reset - ----------------------------------------------------------------------------- - por: process - begin - power_on_n_s <= '0'; - wait for 200 ns; - power_on_n_s <= '1'; - wait; - end process por; - - - ----------------------------------------------------------------------------- - -- - ctrl: process - - function check_crc(payload : in std_logic_vector(47 downto 0)) - return boolean is - - begin - - return calc_crc(payload(47 downto 8)) = payload(7 downto 1); - end check_crc; - - variable rx_v : std_logic_vector(47 downto 0); - variable cmd_v : std_logic_vector( 5 downto 0); - variable arg_v : std_logic_vector(31 downto 0); - variable crc_v : std_logic_vector( 6 downto 0); - variable wrong_v : std_logic; - variable read_data_v : boolean; - - begin - rx_s <= (others => '0'); - set_spi_mode_s <= false; - set_idle_mode_s <= false; - poll_idle_mode_s <= false; - cmd_spi_data_s <= '1'; - soft_res_n_s <= '1'; - set_block_len_s <= false; - block_len_s <= (others => '0'); - new_read_addr_s <= (others => '0'); - set_read_addr_s <= false; - start_read_s <= false; - read_data_v := false; - - loop - - rise_clk; - -- wait for startbit of command - while to_X01(spi_data_i) = '1' loop - rise_clk; - end loop; - rx_v(47) := '0'; - - -- read remaining 47 bits of command - for i in 46 downto 0 loop - rise_clk; - rx_v(i) := to_X01(spi_data_i); - end loop; - rx_s <= rx_v; - - -- dissect received data - cmd_v := rx_v(45 downto 40); - arg_v := rx_v(39 downto 8); - crc_v := rx_v( 7 downto 1); - - assert spi_mode_q or check_crc(payload => rx_v) - report "CRC mismatch" - severity error; - - wrong_v := '0'; - case cmd_v is - -- CMD0: GO_IDLE_STATE ------------------------------------------------ - when "000000" => - set_spi_mode_s <= true; - set_idle_mode_s <= true; - -- CMD1: SEND_OP_COND ------------------------------------------------- - when "000001" => - poll_idle_mode_s <= true; - -- CMD12: STOP_TRANSMISSION ------------------------------------------- - when "001100" => - start_read_s <= false; - read_data_v := false; - -- CMD16: SET_BLOCKLEN ------------------------------------------------ - when "010000" => - block_len_s <= unsigned(arg_v); - set_block_len_s <= true; - -- CMD18: READ_MULTIPLE_BLOCK ----------------------------------------- - when "010010" => - new_read_addr_s <= unsigned(arg_v); - set_read_addr_s <= true; - read_data_v := true; - -- CMD55: APPL_CMD ---------------------------------------------------- - when "110111" => - -- command only available for SD card - if is_sd_card_g /= 1 then - wrong_v := '1'; - end if; - -- ACMD41: SEND_OP_COND ----------------------------------------------- - when "101001" => - -- command only available for SD card - if is_sd_card_g /= 1 then - wrong_v := '1'; - else - poll_idle_mode_s <= true; - end if; - - when others => - wrong_v := '1'; - null; - end case; - - - -- spend some time before removing control signals - fall_clk(2); - poll_idle_mode_s <= false; - set_idle_mode_s <= false; - fall_clk(6); - set_spi_mode_s <= false; - set_block_len_s <= false; - set_read_addr_s <= false; - - if reading_s then - wait until not reading_s; - end if; - - - -- wait for a total two "bytes" before sending out response - for i in 1 to 8 loop - fall_clk; - end loop; - - for i in 7 downto 0 loop - fall_clk; - case i is - when 2 => - cmd_spi_data_s <= wrong_v; - when 0 => - if idle_mode_q = 0 then - cmd_spi_data_s <= '0'; - else - cmd_spi_data_s <= '1'; - end if; - when others => - cmd_spi_data_s <= '0'; - end case; - end loop; - fall_clk; - cmd_spi_data_s <= '1'; - - -- transmit data if requested - start_read_s <= read_data_v; - - end loop; - end process ctrl; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- - seq: process (res_n_s, - spi_clk_i, - set_spi_mode_s, - set_idle_mode_s, - poll_idle_mode_s, - set_block_len_s, - block_len_s) - - begin - if res_n_s = '0' then - spi_mode_q <= false; - idle_mode_q <= 5; - block_len_q <= (others => '0'); - read_addr_q <= (others => '0'); - - elsif spi_clk_i'event and spi_clk_i = '1' then - if set_spi_mode_s then - spi_mode_q <= true; - end if; - - if set_idle_mode_s then - idle_mode_q <= 5; - elsif poll_idle_mode_s then - if idle_mode_q > 0 then - idle_mode_q <= idle_mode_q - 1; - end if; - end if; - - if set_block_len_s then - block_len_q <= block_len_s; - end if; - - if set_read_addr_s then - read_addr_q <= new_read_addr_s; - elsif inc_read_addr_s then - read_addr_q <= read_addr_q + 1; - end if; - - end if; - end process seq; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- - read_block: process - - variable t_v : unsigned(7 downto 0); - - begin - -- default assignments - inc_read_addr_s <= false; - reading_s <= false; - read_spi_data_s <= '1'; - - loop - if not start_read_s then - wait until start_read_s; - end if; - - reading_s <= true; - - fall_clk(8); -- delay for one "byte" - - -- send data token - fall_clk(7); -- 7 ones in a data token - read_spi_data_s <= '0'; - - -- send payload - payload: for i in 0 to to_integer(block_len_q)-1 loop - t_v := read_addr_q(0) & calc_crc(read_addr_q); - for bit in 7 downto 0 loop - fall_clk; - read_spi_data_s <= t_v(bit); - - exit payload when not start_read_s; - end loop; - inc_read_addr_s <= true; - rise_clk; - inc_read_addr_s <= false; - wait for 10 ns; - end loop; - - if start_read_s then - -- send crc - for i in 0 to 15 loop - fall_clk; - t_v := to_unsigned(i, 8); - read_spi_data_s <= t_v(0); - end loop; - fall_clk; - end if; - - read_spi_data_s <= '1'; - reading_s <= false; - -- loop for one "byte" - fall_clk(8); - - end loop; - end process read_block; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- - clk_check: process (spi_clk_i) - - variable last_rising_v : time := 0 ns; - variable dump_line : line; - - begin - if spi_clk_i'event and spi_clk_i = '1' then - if is_sd_card_g = 0 and card_type_g /= "Minimal Chip" and - idle_mode_q > 0 then - if now - last_rising_v < 2.5 us and last_rising_v > 0 ns then - write(dump_line, card_type_g); - write(dump_line, string'(" @ ")); - write(dump_line, now); - write(dump_line, string'(": Last rising edge of SPI clock ")); - write(dump_line, now - last_rising_v); - write(dump_line, string'(" ago.")); - writeline(output, dump_line); - end if; - - last_rising_v := now; - end if; - end if; - end process clk_check; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output Mapping - ----------------------------------------------------------------------------- - spi_data_o <= cmd_spi_data_s and read_spi_data_s - when spi_cs_n_i = '0' else - 'Z'; - -end behav; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: card.vhd,v $ --- Revision 1.2 2005/02/13 17:06:22 arniml --- handle termination properly --- --- Revision 1.1 2005/02/08 21:09:20 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb-c.vhd deleted file mode 100644 index caa171362..000000000 --- a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb-c.vhd +++ /dev/null @@ -1,31 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: tb-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration tb_behav_c0 of tb is - - for behav - - for tb_elem_full_b : tb_elem - use configuration work.tb_elem_behav_full; - end for; - - for tb_elem_mmc_b : tb_elem - use configuration work.tb_elem_behav_mmc; - end for; - - for tb_elem_sd_b : tb_elem - use configuration work.tb_elem_behav_sd; - end for; - - for tb_elem_minimal_b : tb_elem - use configuration work.tb_elem_behav_minimal; - end for; - - end for; - -end tb_behav_c0; diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb.vhd deleted file mode 100644 index b359fa7c5..000000000 --- a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb.vhd +++ /dev/null @@ -1,201 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Testbench --- --- $Id: tb.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -entity tb is - -end tb; - - -library ieee; -use ieee.std_logic_1164.all; - -architecture behav of tb is - - component tb_elem - generic ( - chip_type_g : string := "none"; - has_sd_card_g : integer := 1 - ); - port ( - clk_i : in std_logic; - reset_i : in std_logic; - eos_o : out boolean - ); - end component; - - constant period_c : time := 100 ns; - constant reset_level_c : integer := 0; - - signal clk_s : std_logic; - signal reset_s : std_logic; - - signal eos_full_s, - eos_mmc_s, - eos_sd_s, - eos_minimal_s : boolean; - -begin - - - ----------------------------------------------------------------------------- - -- Testbench element including full featured chip - ----------------------------------------------------------------------------- - tb_elem_full_b : tb_elem - generic map ( - chip_type_g => "Full Chip", - has_sd_card_g => 1 - ) - port map ( - clk_i => clk_s, - reset_i => reset_s, - eos_o => eos_full_s - ); - - - ----------------------------------------------------------------------------- - -- Testbench element including MMC chip - ----------------------------------------------------------------------------- - tb_elem_mmc_b : tb_elem - generic map ( - chip_type_g => "MMC Chip", - has_sd_card_g => 0 - ) - port map ( - clk_i => clk_s, - reset_i => reset_s, - eos_o => eos_mmc_s - ); - - - ----------------------------------------------------------------------------- - -- Testbench element including SD chip - ----------------------------------------------------------------------------- - tb_elem_sd_b : tb_elem - generic map ( - chip_type_g => "SD Chip", - has_sd_card_g => 1 - ) - port map ( - clk_i => clk_s, - reset_i => reset_s, - eos_o => eos_sd_s - ); - - - ----------------------------------------------------------------------------- - -- Testbench element including cip with minimal features - ----------------------------------------------------------------------------- - tb_elem_minimal_b : tb_elem - generic map ( - chip_type_g => "Minimal Chip", - has_sd_card_g => 0 - ) - port map ( - clk_i => clk_s, - reset_i => reset_s, - eos_o => eos_minimal_s - ); - - - ----------------------------------------------------------------------------- - -- Clock Generator - ----------------------------------------------------------------------------- - clk: process - begin - clk_s <= '0'; - wait for period_c / 2; - clk_s <= '1'; - wait for period_c / 2; - end process clk; - - - ----------------------------------------------------------------------------- - -- Reset Generator - ----------------------------------------------------------------------------- - reset: process - begin - if reset_level_c = 0 then - reset_s <= '0'; - else - reset_s <= '1'; - end if; - - wait for period_c * 4 + 10 ns; - - reset_s <= not reset_s; - - wait; - end process reset; - - - ----------------------------------------------------------------------------- - -- End Of Simulation Detection - ----------------------------------------------------------------------------- - eos: process (eos_full_s, - eos_mmc_s, - eos_sd_s, - eos_minimal_s) - begin - - if eos_full_s and eos_mmc_s and eos_sd_s and eos_minimal_s then - assert false - report "End of Simulation." - severity failure; - end if; - - end process eos; - -end behav; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: tb.vhd,v $ --- Revision 1.1 2005/02/08 21:09:20 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd deleted file mode 100644 index 3c0fb902f..000000000 --- a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd +++ /dev/null @@ -1,23 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: tb_elem-full-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration tb_elem_behav_full of tb_elem is - - for behav - - for dut_b : chip - use configuration work.chip_full_c0; - end for; - - for card_b : card - use configuration work.card_behav_c0; - end for; - - end for; - -end tb_elem_behav_full; diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd deleted file mode 100644 index 1c33ac3d0..000000000 --- a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd +++ /dev/null @@ -1,23 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: tb_elem-minimal-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration tb_elem_behav_minimal of tb_elem is - - for behav - - for dut_b : chip - use configuration work.chip_minimal_c0; - end for; - - for card_b : card - use configuration work.card_behav_c0; - end for; - - end for; - -end tb_elem_behav_minimal; diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd deleted file mode 100644 index b5baf604e..000000000 --- a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd +++ /dev/null @@ -1,23 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: tb_elem-mmc-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration tb_elem_behav_mmc of tb_elem is - - for behav - - for dut_b : chip - use configuration work.chip_mmc_c0; - end for; - - for card_b : card - use configuration work.card_behav_c0; - end for; - - end for; - -end tb_elem_behav_mmc; diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd deleted file mode 100644 index 9cdf3eaa1..000000000 --- a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd +++ /dev/null @@ -1,23 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: tb_elem-sd-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration tb_elem_behav_sd of tb_elem is - - for behav - - for dut_b : chip - use configuration work.chip_sd_c0; - end for; - - for card_b : card - use configuration work.card_behav_c0; - end for; - - end for; - -end tb_elem_behav_sd; diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem.vhd deleted file mode 100644 index 689cec037..000000000 --- a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem.vhd +++ /dev/null @@ -1,376 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Generic testbench element for a specific feature set --- --- $Id: tb_elem.vhd,v 1.7 2005/04/07 20:43:36 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -entity tb_elem is - - generic ( - chip_type_g : string := "none"; - has_sd_card_g : integer := 1 - ); - port ( - clk_i : in std_logic; - reset_i : in std_logic; - eos_o : out boolean - ); - -end tb_elem; - - -library ieee; -use ieee.numeric_std.all; -library std; -use std.textio.all; - -use work.spi_boot_pack.all; -use work.tb_pack.all; - -architecture behav of tb_elem is - - component chip - port ( - clk_i : in std_logic; - reset_i : in std_logic; - set_sel_n_i : in std_logic_vector(3 downto 0); - spi_clk_o : out std_logic; - spi_cs_n_o : out std_logic; - spi_data_in_i : in std_logic; - spi_data_out_o : out std_logic; - start_i : in std_logic; - mode_i : in std_logic; - config_n_o : out std_logic; - detached_o : out std_logic; - cfg_init_n_i : in std_logic; - cfg_done_i : in std_logic; - dat_done_i : in std_logic; - cfg_clk_o : out std_logic; - cfg_dat_o : out std_logic - ); - end component; - - component card - generic ( - card_type_g : string := "none"; - is_sd_card_g : integer := 1 - ); - port ( - spi_clk_i : in std_logic; - spi_cs_n_i : in std_logic; - spi_data_i : in std_logic; - spi_data_o : out std_logic - ); - end component; - - signal reset_s : std_logic; - - -- SPI interface signals - signal spi_clk_s : std_logic; - signal spi_data_to_card_s : std_logic; - signal spi_data_from_card_s : std_logic; - signal spi_cs_n_s : std_logic; - - -- config related signals - signal start_s : std_logic; - signal mode_s : std_logic; - signal config_n_s : std_logic; - signal cfg_init_n_s : std_logic; - signal cfg_done_s : std_logic; - signal dat_done_s : std_logic; - signal cfg_clk_s : std_logic; - signal cfg_dat_s : std_logic; - signal data_s : unsigned(7 downto 0); - - signal set_sel_n_s : std_logic_vector(3 downto 0); - - constant verbose_c : boolean := false; - -begin - - -- weak pull-ups - spi_clk_s <= 'H'; - spi_cs_n_s <= 'H'; - spi_data_to_card_s <= 'H'; - - ----------------------------------------------------------------------------- - -- DUT - ----------------------------------------------------------------------------- - dut_b : chip - port map ( - clk_i => clk_i, - reset_i => reset_s, - set_sel_n_i => set_sel_n_s, - spi_clk_o => spi_clk_s, - spi_cs_n_o => spi_cs_n_s, - spi_data_in_i => spi_data_from_card_s, - spi_data_out_o => spi_data_to_card_s, - start_i => start_s, - mode_i => mode_s, - config_n_o => config_n_s, - detached_o => open, - cfg_init_n_i => cfg_init_n_s, - cfg_done_i => cfg_done_s, - dat_done_i => dat_done_s, - cfg_clk_o => cfg_clk_s, - cfg_dat_o => cfg_dat_s - ); - - card_b : card - generic map ( - card_type_g => chip_type_g, - is_sd_card_g => has_sd_card_g - ) - port map ( - spi_clk_i => spi_clk_s, - spi_cs_n_i => spi_cs_n_s, - spi_data_i => spi_data_to_card_s, - spi_data_o => spi_data_from_card_s - ); - - - ----------------------------------------------------------------------------- - -- DUT Stimuli - -- - stim: process - - procedure rise_cfg_clk(num : integer) is - begin - for i in 1 to num loop - wait until cfg_clk_s'event and cfg_clk_s = '1'; - end loop; - end rise_cfg_clk; - --- procedure fall_cfg_clk(num : integer) is --- begin --- for i in 1 to num loop --- wait until cfg_clk_s'event and cfg_clk_s = '0'; --- end loop; --- end fall_cfg_clk; - - procedure rise_clk(num : integer) is - begin - for i in 1 to num loop - wait until clk_i'event and clk_i = '1'; - end loop; - end rise_clk; - - procedure read_check_byte(ref : unsigned(7 downto 0)) is - variable byte_v : unsigned(7 downto 0); - variable dump_line : line; - begin - for bit in 7 downto 0 loop - rise_cfg_clk(1); - byte_v(bit) := cfg_dat_s; - end loop; - data_s <= byte_v; - - if byte_v /= ref then - write(dump_line, chip_type_g); - write(dump_line, string'(" at ")); - write(dump_line, now); - write(dump_line, string'(": read_check_byte failed ")); - write(dump_line, to_integer(byte_v)); - write(dump_line, string'(" ")); - write(dump_line, to_integer(ref)); - writeline(output, dump_line); - end if; - end read_check_byte; - - variable dump_line : line; - variable addr_v : unsigned(31 downto 0); - variable temp_v : unsigned( 7 downto 0); - variable set_sel_v : unsigned(3 downto 0); - - begin - -- default assignments - -- these defaults show the required pull resistors - -- except start_i as this must be pulled high for automatic start - start_s <= '0'; - mode_s <= '1'; - cfg_init_n_s <= '1'; - cfg_done_s <= '0'; - dat_done_s <= '1'; - data_s <= (others => '1'); - addr_v := (others => '0'); - eos_o <= false; - set_sel_n_s <= (others => '1'); - reset_s <= '0'; - - -- loop through some sets - for set in 0 to 3 loop - set_sel_v := to_unsigned(set, 4); - addr_v(23 downto 20) := set_sel_v; -- must match num_bits_per_img_g - -- plus width_img_cnt_g - set_sel_n_s <= not std_logic_vector(set_sel_v); - - assert not verbose_c - report chip_type_g & ": Processing set " & to_string(set) - severity note; - - wait for 100 us; - reset_s <= '1'; - - assert not verbose_c - report chip_type_g & ": Requesting image 0" - severity note; - - -- signal start - start_s <= '1'; - mode_s <= '1'; - cfg_done_s <= '0'; - addr_v(19 downto 0) := (others => '0'); - wait until config_n_s = '0'; - -- run through configuration sequence - rise_clk(1); - cfg_init_n_s <= '0'; - rise_clk(3); - cfg_init_n_s <= '1'; - - -- and receive 32 bytes from image 0 - for i in 1 to 32 loop - temp_v := addr_v(0) & calc_crc(addr_v); - read_check_byte(temp_v); - addr_v := addr_v + 1; - end loop; - start_s <= '0'; - cfg_done_s <= '1'; - - rise_clk(10); - - assert not verbose_c - report chip_type_g & ": Requesting image 1" - severity note; - - -- request next image - mode_s <= '0'; - start_s <= '1'; - addr_v(17 downto 0) := (others => '0'); - addr_v(19 downto 18) := "01"; -- must match num_bits_per_img_g in chip-*-a.vhd - dat_done_s <= '0'; - - -- receive another 32 bytes from image 1 - for i in 1 to 32 loop - temp_v := addr_v(0) & calc_crc(addr_v); - read_check_byte(temp_v); - addr_v := addr_v + 1; - end loop; - start_s <= '0'; - dat_done_s <= '1'; - - - rise_clk(10); - - assert not verbose_c - report chip_type_g & ": Requesting image 2" - severity note; - - -- request next image - mode_s <= '1'; - start_s <= '1'; - addr_v(17 downto 0) := (others => '0'); - addr_v(19 downto 18) := "10"; -- must match num_bits_per_img_g in chip-*-a.vhd - - wait until config_n_s = '0'; - -- run through configuration sequence - rise_clk(1); - cfg_done_s <= '0'; - cfg_init_n_s <= '0'; - rise_clk(3); - cfg_init_n_s <= '1'; - - -- receive another 32 bytes from image 2 - for i in 1 to 32 loop - temp_v := addr_v(0) & calc_crc(addr_v); - read_check_byte(temp_v); - addr_v := addr_v + 1; - end loop; - start_s <= '0'; - cfg_done_s <= '1'; - - -- give dut a chance to stop current transfer - wait until spi_cs_n_s = '1'; - rise_clk(10); - - reset_s <= '0'; - end loop; - - eos_o <= true; - wait; - end process stim; - -- - ----------------------------------------------------------------------------- - -end behav; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: tb_elem.vhd,v $ --- Revision 1.7 2005/04/07 20:43:36 arniml --- add new port detached_o --- --- Revision 1.6 2005/03/09 19:48:04 arniml --- make verbosity level switchable --- --- Revision 1.5 2005/03/08 22:06:21 arniml --- added set selection --- --- Revision 1.4 2005/02/17 18:59:23 arniml --- clarify wording for images --- --- Revision 1.3 2005/02/16 19:34:56 arniml --- add weak pull-ups for SPI lines --- --- Revision 1.2 2005/02/13 17:14:03 arniml --- change dat_done handling --- --- Revision 1.1 2005/02/08 21:09:20 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd deleted file mode 100644 index 7534aafdc..000000000 --- a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd +++ /dev/null @@ -1,93 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: tb_pack-p.vhd,v 1.2 2005/03/08 22:06:39 arniml Exp $ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package tb_pack is - - function calc_crc(payload : in std_logic_vector) return std_logic_vector; - function calc_crc(payload : in unsigned) return unsigned; - - function to_string(value : in integer) return string; - -end tb_pack; - - -package body tb_pack is - - function calc_crc(payload : in std_logic_vector) return std_logic_vector is - - variable crc_v : std_logic_vector(6 downto 0); - variable temp_v : std_logic; - - begin - - crc_v := (others => '0'); - - for i in payload'high downto payload'low loop - temp_v := payload(i) xor crc_v(6); - - crc_v(6 downto 4) := crc_v(5 downto 3); - crc_v(3) := crc_v(2) xor temp_v; - crc_v(2 downto 1) := crc_v(1 downto 0); - crc_v(0) := temp_v; - end loop; - - return crc_v; - end calc_crc; - - function calc_crc(payload : in unsigned) return unsigned is - begin - return unsigned(calc_crc(std_logic_vector(payload))); - end calc_crc; - - function to_string(value : in integer) return string is - variable str: string (11 downto 1); - variable val: integer := value; - variable digit: natural; - variable index: natural := 0; - begin - -- Taken from: - -- textio package body. This file is part of GHDL. - -- Copyright (C) 2002 Tristan Gingold. - -- Note: the absolute value of VAL cannot be directly taken, since - -- it may be greather that the maximum value of an INTEGER. - loop - -- LRM93 7.2.6 - -- (A rem B) has the sign of A and an absolute value less then - -- the absoulte value of B. - digit := abs (val rem 10); - val := val / 10; - index := index + 1; - str (index) := character'val(48 + digit); - exit when val = 0; - end loop; - if value < 0 then - index := index + 1; - str(index) := '-'; - end if; - - return str; - end to_string; - -end tb_pack; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: tb_pack-p.vhd,v $ --- Revision 1.2 2005/03/08 22:06:39 arniml --- added integer->string conversion function --- --- Revision 1.1 2005/02/08 21:09:20 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd deleted file mode 100644 index 84273abc5..000000000 --- a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd +++ /dev/null @@ -1,27 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: tb_rl-c.vhd,v 1.1 2005/04/10 18:07:26 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration tb_rl_behav_c0 of tb_rl is - - for behav - - for dut_b : chip - use configuration work.chip_full_c0; - end for; - - for card_b : card - use configuration work.card_behav_c0; - end for; - - for rl_b : ram_loader - use configuration work.ram_loader_rtl_c0; - end for; - - end for; - -end tb_rl_behav_c0; diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl.vhd deleted file mode 100644 index 9f28e62b4..000000000 --- a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl.vhd +++ /dev/null @@ -1,259 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Testbench for ram_loader --- --- $Id: tb_rl.vhd,v 1.1 2005/04/10 18:07:25 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -entity tb_rl is - -end tb_rl; - - -library ieee; -use ieee.std_logic_1164.all; - -architecture behav of tb_rl is - - component chip - port ( - clk_i : in std_logic; - reset_i : in std_logic; - set_sel_n_i : in std_logic_vector(3 downto 0); - spi_clk_o : out std_logic; - spi_cs_n_o : out std_logic; - spi_data_in_i : in std_logic; - spi_data_out_o : out std_logic; - start_i : in std_logic; - mode_i : in std_logic; - config_n_o : out std_logic; - detached_o : out std_logic; - cfg_init_n_i : in std_logic; - cfg_done_i : in std_logic; - dat_done_i : in std_logic; - cfg_clk_o : out std_logic; - cfg_dat_o : out std_logic - ); - end component; - - component card - generic ( - card_type_g : string := "none"; - is_sd_card_g : integer := 1 - ); - port ( - spi_clk_i : in std_logic; - spi_cs_n_i : in std_logic; - spi_data_i : in std_logic; - spi_data_o : out std_logic - ); - end component; - - component ram_loader - port ( - clk_i : in std_logic; - reset_i : in std_logic; - lamp_o : out std_logic; - cfg_clk_i : in std_logic; - cfg_data_i : in std_logic; - start_o : out std_logic; - mode_o : out std_logic; - done_o : out std_logic; - detached_i : in std_logic; - ram_addr_o : out std_logic_vector(15 downto 0); - ram_data_b : out std_logic_vector( 7 downto 0); - ram_ce_no : out std_logic_vector( 3 downto 0); - ram_oe_no : out std_logic; - ram_we_no : out std_logic - ); - end component; - - constant period_c : time := 100 ns; - constant rl_period_c : time := 20 ns; - constant reset_level_c : integer := 0; - - signal clk_s : std_logic; - signal rl_clk_s: std_logic; - signal reset_s : std_logic; - - -- SPI interface signals - signal spi_clk_s : std_logic; - signal spi_data_to_card_s : std_logic; - signal spi_data_from_card_s : std_logic; - signal spi_cs_n_s : std_logic; - - -- config related signals - signal start_s : std_logic; - signal mode_s : std_logic; - signal config_n_s : std_logic; - signal cfg_init_n_s : std_logic; - signal cfg_done_s : std_logic; - signal dat_done_s : std_logic; - signal cfg_clk_s : std_logic; - signal cfg_dat_s : std_logic; - signal detached_s : std_logic; - - signal set_sel_n_s : std_logic_vector(3 downto 0); - -begin - - set_sel_n_s <= (others => '1'); - cfg_init_n_s <= '1'; - cfg_done_s <= '1'; - - ----------------------------------------------------------------------------- - -- DUT - ----------------------------------------------------------------------------- - dut_b : chip - port map ( - clk_i => clk_s, - reset_i => reset_s, - set_sel_n_i => set_sel_n_s, - spi_clk_o => spi_clk_s, - spi_cs_n_o => spi_cs_n_s, - spi_data_in_i => spi_data_from_card_s, - spi_data_out_o => spi_data_to_card_s, - start_i => start_s, - mode_i => mode_s, - config_n_o => config_n_s, - detached_o => detached_s, - cfg_init_n_i => cfg_init_n_s, - cfg_done_i => cfg_done_s, - dat_done_i => dat_done_s, - cfg_clk_o => cfg_clk_s, - cfg_dat_o => cfg_dat_s - ); - - card_b : card - generic map ( - card_type_g => "Full Chip", - is_sd_card_g => 1 - ) - port map ( - spi_clk_i => spi_clk_s, - spi_cs_n_i => spi_cs_n_s, - spi_data_i => spi_data_to_card_s, - spi_data_o => spi_data_from_card_s - ); - - rl_b : ram_loader - port map ( - clk_i => rl_clk_s, - reset_i => reset_s, - lamp_o => open, - cfg_clk_i => cfg_clk_s, - cfg_data_i => cfg_dat_s, - start_o => start_s, - mode_o => mode_s, - done_o => dat_done_s, - detached_i => detached_s, - ram_addr_o => open, - ram_data_b => open, - ram_ce_no => open, - ram_oe_no => open, - ram_we_no => open - ); - - ----------------------------------------------------------------------------- - -- Clock Generator - ----------------------------------------------------------------------------- - clk: process - begin - clk_s <= '0'; - wait for period_c / 2; - clk_s <= '1'; - wait for period_c / 2; - end process clk; - - rl_clk: process - begin - rl_clk_s <= '0'; - wait for rl_period_c / 2; - rl_clk_s <= '1'; - wait for rl_period_c / 2; - end process rl_clk; - - - ----------------------------------------------------------------------------- - -- Reset Generator - ----------------------------------------------------------------------------- - reset: process - begin - if reset_level_c = 0 then - reset_s <= '0'; - else - reset_s <= '1'; - end if; - - wait for period_c * 4 + 10 ns; - - reset_s <= not reset_s; - - wait; - end process reset; - - - ----------------------------------------------------------------------------- - -- End of Simulation - ----------------------------------------------------------------------------- - eos: process - begin - wait for 4 ms; - assert false - report "No checks have been performed. Investigate waveforms." - severity note; - assert false - report "End of simulation." - severity failure; - end process eos; - -end behav; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: tb_rl.vhd,v $ --- Revision 1.1 2005/04/10 18:07:25 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/fpga/usrp2/opencores/spi_boot/doc/spi_boot.pdf b/fpga/usrp2/opencores/spi_boot/doc/spi_boot.pdf deleted file mode 100644 index a889c3f22..000000000 Binary files a/fpga/usrp2/opencores/spi_boot/doc/spi_boot.pdf and /dev/null differ diff --git a/fpga/usrp2/opencores/spi_boot/doc/spi_boot_schematic.pdf b/fpga/usrp2/opencores/spi_boot/doc/spi_boot_schematic.pdf deleted file mode 100644 index 92755d5f3..000000000 Binary files a/fpga/usrp2/opencores/spi_boot/doc/spi_boot_schematic.pdf and /dev/null differ diff --git a/fpga/usrp2/opencores/spi_boot/doc/src/architecture.eps b/fpga/usrp2/opencores/spi_boot/doc/src/architecture.eps deleted file mode 100644 index 3e70efdb1..000000000 --- a/fpga/usrp2/opencores/spi_boot/doc/src/architecture.eps +++ /dev/null @@ -1,512 +0,0 @@ -%!PS-Adobe-2.0 EPSF-2.0 -%%Title: architecture.eps -%%Creator: fig2dev Version 3.2 Patchlevel 3d -%%CreationDate: Thu Apr 14 00:29:54 2005 -%%For: arnim@lola (Arnim Laeuger) -%%BoundingBox: 0 0 452 241 -%%Magnification: 1.0000 -%%EndComments -/$F2psDict 200 dict def -$F2psDict begin -$F2psDict /mtrx matrix put -/col-1 {0 setgray} bind def -/col0 {0.000 0.000 0.000 srgb} bind def -/col1 {0.000 0.000 1.000 srgb} bind def -/col2 {0.000 1.000 0.000 srgb} bind def -/col3 {0.000 1.000 1.000 srgb} bind def -/col4 {1.000 0.000 0.000 srgb} bind def -/col5 {1.000 0.000 1.000 srgb} bind def -/col6 {1.000 1.000 0.000 srgb} bind def -/col7 {1.000 1.000 1.000 srgb} bind def -/col8 {0.000 0.000 0.560 srgb} bind def -/col9 {0.000 0.000 0.690 srgb} bind def -/col10 {0.000 0.000 0.820 srgb} bind def -/col11 {0.530 0.810 1.000 srgb} bind def -/col12 {0.000 0.560 0.000 srgb} bind def -/col13 {0.000 0.690 0.000 srgb} bind def -/col14 {0.000 0.820 0.000 srgb} bind def -/col15 {0.000 0.560 0.560 srgb} bind def -/col16 {0.000 0.690 0.690 srgb} bind def -/col17 {0.000 0.820 0.820 srgb} bind def -/col18 {0.560 0.000 0.000 srgb} bind def -/col19 {0.690 0.000 0.000 srgb} bind def -/col20 {0.820 0.000 0.000 srgb} bind def -/col21 {0.560 0.000 0.560 srgb} bind def -/col22 {0.690 0.000 0.690 srgb} bind def -/col23 {0.820 0.000 0.820 srgb} bind def -/col24 {0.500 0.190 0.000 srgb} bind def -/col25 {0.630 0.250 0.000 srgb} bind def -/col26 {0.750 0.380 0.000 srgb} bind def -/col27 {1.000 0.500 0.500 srgb} bind def -/col28 {1.000 0.630 0.630 srgb} bind def -/col29 {1.000 0.750 0.750 srgb} bind def -/col30 {1.000 0.880 0.880 srgb} bind def -/col31 {1.000 0.840 0.000 srgb} bind def - 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5940 4770 7380 4770 7380 5400 5940 5400 5940 4770 -4 1 0 50 0 16 10 0.0000 4 135 960 6660 5130 Activate config_n\001 --6 -6 5895 5715 7425 6435 -2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 - 6660 5760 7380 6030 6660 6390 5940 6030 6660 5760 -4 1 0 50 0 16 10 0.0000 4 135 855 6660 6112 cfg_init_n low?\001 --6 -6 5895 6705 7425 7425 -2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 - 5940 6750 7380 6750 7380 7380 5940 7380 5940 6750 -4 1 0 50 0 16 10 0.0000 4 135 1125 6660 7110 Deactivate config_n\001 --6 -6 5895 7695 7425 8415 -2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 - 6660 7740 7380 8010 6660 8370 5940 8010 6660 7740 -4 1 0 50 0 16 10 0.0000 4 135 915 6660 8092 cfg_init_n high?\001 --6 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 45.00 90.00 - 3780 3420 3780 3780 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 45.00 90.00 - 3780 4410 3780 4770 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 45.00 90.00 - 3780 5400 3780 5760 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 45.00 90.00 - 3780 6390 3780 6750 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 45.00 90.00 - 3780 7380 3780 7740 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 4 - 1 1 1.00 45.00 90.00 - 4545 7020 5130 7020 5130 5535 3780 5535 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 6 - 1 1 1.00 45.00 90.00 - 3780 8370 3780 8640 2520 8640 2520 2520 3780 2520 3780 2790 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 45.00 90.00 - 4680 3555 3780 3555 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 3 - 1 1 1.00 45.00 90.00 - 4500 4050 6660 4050 6660 4770 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 4 - 1 1 1.00 45.00 90.00 - 7380 6030 7920 6030 7920 4050 6660 4050 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 4 - 1 1 1.00 45.00 90.00 - 7380 8010 7920 8010 7920 6525 6660 6525 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 5 - 1 1 1.00 45.00 90.00 - 6660 8370 6660 8640 5310 8640 5310 4545 3780 4545 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 45.00 90.00 - 6660 5400 6660 5760 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 45.00 90.00 - 6660 6390 6660 6750 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 45.00 90.00 - 6660 7380 6660 7740 -4 0 0 50 0 16 10 0.0000 4 105 210 3870 7560 Yes\001 -4 0 0 50 0 16 10 0.0000 4 105 165 4590 6930 No\001 -4 0 0 50 0 16 10 0.0000 4 105 240 4770 3600 start\001 -4 2 0 50 0 16 10 0.0000 4 105 165 3690 4590 No\001 -4 0 0 50 0 16 10 0.0000 4 105 210 4590 3960 Yes\001 -4 0 0 50 0 16 10 0.0000 4 105 165 7470 5940 No\001 -4 2 0 50 0 16 10 0.0000 4 105 210 6570 6570 Yes\001 -4 0 0 50 0 16 10 0.0000 4 105 165 7470 7920 No\001 -4 0 0 50 0 16 10 0.0000 4 105 210 6750 8550 Yes\001 diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-e.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-e.vhd deleted file mode 100644 index 0bdd05aff..000000000 --- a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-e.vhd +++ /dev/null @@ -1,91 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Chip toplevel --- --- $Id: chip-e.vhd,v 1.3 2005/04/07 20:44:23 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -entity chip is - - port ( - -- System Interface ------------------------------------------------------- - clk_i : in std_logic; - reset_i : in std_logic; - set_sel_n_i : in std_logic_vector(3 downto 0); - -- SD Card Interface ------------------------------------------------------ - spi_clk_o : out std_logic; - spi_cs_n_o : out std_logic; - spi_data_in_i : in std_logic; - spi_data_out_o : out std_logic; - -- FPGA Configuration Interface ------------------------------------------- - start_i : in std_logic; - mode_i : in std_logic; - config_n_o : out std_logic; - detached_o : out std_logic; - cfg_init_n_i : in std_logic; - cfg_done_i : in std_logic; - dat_done_i : in std_logic; - cfg_clk_o : out std_logic; - cfg_dat_o : out std_logic - ); - -end chip; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: chip-e.vhd,v $ --- Revision 1.3 2005/04/07 20:44:23 arniml --- add new port detached_o --- --- Revision 1.2 2005/03/08 22:07:11 arniml --- added set selection --- --- Revision 1.1 2005/02/08 20:41:30 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd deleted file mode 100644 index e43ecb3c4..000000000 --- a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd +++ /dev/null @@ -1,164 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Chip toplevel design with full feature set --- --- $Id: chip-full-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -architecture full of chip is - - component spi_boot - generic ( - width_set_sel_g : integer := 4; - width_bit_cnt_g : integer := 6; - width_img_cnt_g : integer := 2; - num_bits_per_img_g : integer := 18; - sd_init_g : integer := 0; - mmc_compat_clk_div_g : integer := 0; - width_mmc_clk_div_g : integer := 0; - reset_level_g : integer := 0 - ); - port ( - clk_i : in std_logic; - reset_i : in std_logic; - set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); - spi_clk_o : out std_logic; - spi_cs_n_o : out std_logic; - spi_data_in_i : in std_logic; - spi_data_out_o : out std_logic; - spi_en_outs_o : out std_logic; - start_i : in std_logic; - mode_i : in std_logic; - config_n_o : out std_logic; - detached_o : out std_logic; - cfg_init_n_i : in std_logic; - cfg_done_i : in std_logic; - dat_done_i : in std_logic; - cfg_clk_o : out std_logic; - cfg_dat_o : out std_logic - ); - end component; - - signal spi_clk_s : std_logic; - signal spi_cs_n_s : std_logic; - signal spi_data_out_s : std_logic; - signal spi_en_outs_s : std_logic; - - signal set_sel_s : std_logic_vector(3 downto 0); - -begin - - set_sel_s <= not set_sel_n_i; - - spi_boot_b : spi_boot - generic map ( - width_set_sel_g => 4, -- 16 sets - width_bit_cnt_g => 12, -- 512 bytes per block - width_img_cnt_g => 2, -- 4 images - num_bits_per_img_g => 18, -- 256 kByte per image - sd_init_g => 1, -- use SD specific initialization - mmc_compat_clk_div_g => 13, -- MMC compat 400 kHz > 10 MHz / (13*2) - width_mmc_clk_div_g => 4 -- need 5 bits for MMC compat divider - ) - port map ( - clk_i => clk_i, - reset_i => reset_i, - set_sel_i => set_sel_s, - spi_clk_o => spi_clk_s, - spi_cs_n_o => spi_cs_n_s, - spi_data_in_i => spi_data_in_i, - spi_data_out_o => spi_data_out_s, - spi_en_outs_o => spi_en_outs_s, - start_i => start_i, - mode_i => mode_i, - config_n_o => config_n_o, - detached_o => detached_o, - cfg_init_n_i => cfg_init_n_i, - cfg_done_i => cfg_done_i, - dat_done_i => dat_done_i, - cfg_clk_o => cfg_clk_o, - cfg_dat_o => cfg_dat_o - ); - - ----------------------------------------------------------------------------- - -- Three state drivers for SPI outputs. - ----------------------------------------------------------------------------- - spi_clk_o <= spi_clk_s - when spi_en_outs_s = '1' else - 'Z'; - spi_cs_n_o <= spi_cs_n_s - when spi_en_outs_s = '1' else - 'Z'; - spi_data_out_o <= spi_data_out_s - when spi_en_outs_s = '1' else - 'Z'; - -end full; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: chip-full-a.vhd,v $ --- Revision 1.6 2005/04/07 20:44:23 arniml --- add new port detached_o --- --- Revision 1.5 2005/03/09 19:48:34 arniml --- invert level of set_sel input --- --- Revision 1.4 2005/03/08 22:07:12 arniml --- added set selection --- --- Revision 1.3 2005/02/18 06:42:11 arniml --- clarify wording for images --- --- Revision 1.2 2005/02/16 18:54:37 arniml --- added tri-state drivers for spi outputs --- --- Revision 1.1 2005/02/08 20:41:31 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd deleted file mode 100644 index da88552c4..000000000 --- a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd +++ /dev/null @@ -1,19 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: chip-full-c.vhd,v 1.1 2005/02/08 20:41:31 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration chip_full_c0 of chip is - - for full - - for spi_boot_b : spi_boot - use configuration work.spi_boot_rtl_c0; - end for; - - end for; - -end chip_full_c0; diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd deleted file mode 100644 index 090d0b79c..000000000 --- a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd +++ /dev/null @@ -1,164 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Chip toplevel design with minimal feature set --- --- $Id: chip-minimal-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -architecture minimal of chip is - - component spi_boot - generic ( - width_set_sel_g : integer := 4; - width_bit_cnt_g : integer := 6; - width_img_cnt_g : integer := 2; - num_bits_per_img_g : integer := 18; - sd_init_g : integer := 0; - mmc_compat_clk_div_g : integer := 0; - width_mmc_clk_div_g : integer := 0; - reset_level_g : integer := 0 - ); - port ( - clk_i : in std_logic; - reset_i : in std_logic; - set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); - spi_clk_o : out std_logic; - spi_cs_n_o : out std_logic; - spi_data_in_i : in std_logic; - spi_data_out_o : out std_logic; - spi_en_outs_o : out std_logic; - start_i : in std_logic; - mode_i : in std_logic; - config_n_o : out std_logic; - detached_o : out std_logic; - cfg_init_n_i : in std_logic; - cfg_done_i : in std_logic; - dat_done_i : in std_logic; - cfg_clk_o : out std_logic; - cfg_dat_o : out std_logic - ); - end component; - - signal spi_clk_s : std_logic; - signal spi_cs_n_s : std_logic; - signal spi_data_out_s : std_logic; - signal spi_en_outs_s : std_logic; - - signal set_sel_s : std_logic_vector(3 downto 0); - -begin - - set_sel_s <= not set_sel_n_i; - - spi_boot_b : spi_boot - generic map ( - width_set_sel_g => 4, -- 16 sets - width_bit_cnt_g => 6, -- 8 bytes per block - width_img_cnt_g => 2, -- 4 images - num_bits_per_img_g => 18, -- 256 kByte per image - sd_init_g => 0, -- no SD specific initialization - mmc_compat_clk_div_g => 0, -- no MMC compatibility - width_mmc_clk_div_g => 0 -- no MMC compatibility - ) - port map ( - clk_i => clk_i, - reset_i => reset_i, - set_sel_i => set_sel_s, - spi_clk_o => spi_clk_s, - spi_cs_n_o => spi_cs_n_s, - spi_data_in_i => spi_data_in_i, - spi_data_out_o => spi_data_out_s, - spi_en_outs_o => spi_en_outs_s, - start_i => start_i, - mode_i => mode_i, - config_n_o => config_n_o, - detached_o => detached_o, - cfg_init_n_i => cfg_init_n_i, - cfg_done_i => cfg_done_i, - dat_done_i => dat_done_i, - cfg_clk_o => cfg_clk_o, - cfg_dat_o => cfg_dat_o - ); - - ----------------------------------------------------------------------------- - -- Three state drivers for SPI outputs. - ----------------------------------------------------------------------------- - spi_clk_o <= spi_clk_s - when spi_en_outs_s = '1' else - 'Z'; - spi_cs_n_o <= spi_cs_n_s - when spi_en_outs_s = '1' else - 'Z'; - spi_data_out_o <= spi_data_out_s - when spi_en_outs_s = '1' else - 'Z'; - -end minimal; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: chip-minimal-a.vhd,v $ --- Revision 1.6 2005/04/07 20:44:23 arniml --- add new port detached_o --- --- Revision 1.5 2005/03/09 19:48:34 arniml --- invert level of set_sel input --- --- Revision 1.4 2005/03/08 22:07:12 arniml --- added set selection --- --- Revision 1.3 2005/02/18 06:42:12 arniml --- clarify wording for images --- --- Revision 1.2 2005/02/16 18:54:39 arniml --- added tri-state drivers for spi outputs --- --- Revision 1.1 2005/02/08 20:41:31 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd deleted file mode 100644 index 5547747b2..000000000 --- a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd +++ /dev/null @@ -1,19 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: chip-minimal-c.vhd,v 1.1 2005/02/08 20:41:32 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration chip_minimal_c0 of chip is - - for minimal - - for spi_boot_b : spi_boot - use configuration work.spi_boot_rtl_c0; - end for; - - end for; - -end chip_minimal_c0; diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd deleted file mode 100644 index cef42d268..000000000 --- a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd +++ /dev/null @@ -1,164 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Chip toplevel design with MMC feature set --- --- $Id: chip-mmc-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -architecture mmc of chip is - - component spi_boot - generic ( - width_set_sel_g : integer := 4; - width_bit_cnt_g : integer := 6; - width_img_cnt_g : integer := 2; - num_bits_per_img_g : integer := 18; - sd_init_g : integer := 0; - mmc_compat_clk_div_g : integer := 0; - width_mmc_clk_div_g : integer := 0; - reset_level_g : integer := 0 - ); - port ( - clk_i : in std_logic; - reset_i : in std_logic; - set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); - spi_clk_o : out std_logic; - spi_cs_n_o : out std_logic; - spi_data_in_i : in std_logic; - spi_data_out_o : out std_logic; - spi_en_outs_o : out std_logic; - start_i : in std_logic; - mode_i : in std_logic; - config_n_o : out std_logic; - detached_o : out std_logic; - cfg_init_n_i : in std_logic; - cfg_done_i : in std_logic; - dat_done_i : in std_logic; - cfg_clk_o : out std_logic; - cfg_dat_o : out std_logic - ); - end component; - - signal spi_clk_s : std_logic; - signal spi_cs_n_s : std_logic; - signal spi_data_out_s : std_logic; - signal spi_en_outs_s : std_logic; - - signal set_sel_s : std_logic_vector(3 downto 0); - -begin - - set_sel_s <= not set_sel_n_i; - - spi_boot_b : spi_boot - generic map ( - width_set_sel_g => 4, -- 16 sets - width_bit_cnt_g => 12, -- 512 bytes per block - width_img_cnt_g => 2, -- 4 images - num_bits_per_img_g => 18, -- 256 kByte per image - sd_init_g => 0, -- no SD specific initialization - mmc_compat_clk_div_g => 13, -- MMC compat 400 kHz > 10 MHz / (13*2) - width_mmc_clk_div_g => 4 -- need 5 bits for MMC compat divider - ) - port map ( - clk_i => clk_i, - reset_i => reset_i, - set_sel_i => set_sel_s, - spi_clk_o => spi_clk_s, - spi_cs_n_o => spi_cs_n_s, - spi_data_in_i => spi_data_in_i, - spi_data_out_o => spi_data_out_s, - spi_en_outs_o => spi_en_outs_s, - start_i => start_i, - mode_i => mode_i, - config_n_o => config_n_o, - detached_o => detached_o, - cfg_init_n_i => cfg_init_n_i, - cfg_done_i => cfg_done_i, - dat_done_i => dat_done_i, - cfg_clk_o => cfg_clk_o, - cfg_dat_o => cfg_dat_o - ); - - ----------------------------------------------------------------------------- - -- Three state drivers for SPI outputs. - ----------------------------------------------------------------------------- - spi_clk_o <= spi_clk_s - when spi_en_outs_s = '1' else - 'Z'; - spi_cs_n_o <= spi_cs_n_s - when spi_en_outs_s = '1' else - 'Z'; - spi_data_out_o <= spi_data_out_s - when spi_en_outs_s = '1' else - 'Z'; - -end mmc; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: chip-mmc-a.vhd,v $ --- Revision 1.6 2005/04/07 20:44:23 arniml --- add new port detached_o --- --- Revision 1.5 2005/03/09 19:48:34 arniml --- invert level of set_sel input --- --- Revision 1.4 2005/03/08 22:07:12 arniml --- added set selection --- --- Revision 1.3 2005/02/18 06:42:13 arniml --- clarify wording for images --- --- Revision 1.2 2005/02/16 18:54:39 arniml --- added tri-state drivers for spi outputs --- --- Revision 1.1 2005/02/08 20:41:32 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd deleted file mode 100644 index 6131013e4..000000000 --- a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd +++ /dev/null @@ -1,19 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: chip-mmc-c.vhd,v 1.1 2005/02/08 20:41:32 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration chip_mmc_c0 of chip is - - for mmc - - for spi_boot_b : spi_boot - use configuration work.spi_boot_rtl_c0; - end for; - - end for; - -end chip_mmc_c0; diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd deleted file mode 100644 index c955a5f3a..000000000 --- a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd +++ /dev/null @@ -1,164 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Chip toplevel design with SD feature set --- --- $Id: chip-sd-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -architecture sd of chip is - - component spi_boot - generic ( - width_set_sel_g : integer := 4; - width_bit_cnt_g : integer := 6; - width_img_cnt_g : integer := 2; - num_bits_per_img_g : integer := 18; - sd_init_g : integer := 0; - mmc_compat_clk_div_g : integer := 0; - width_mmc_clk_div_g : integer := 0; - reset_level_g : integer := 0 - ); - port ( - clk_i : in std_logic; - reset_i : in std_logic; - set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); - spi_clk_o : out std_logic; - spi_cs_n_o : out std_logic; - spi_data_in_i : in std_logic; - spi_data_out_o : out std_logic; - spi_en_outs_o : out std_logic; - start_i : in std_logic; - mode_i : in std_logic; - config_n_o : out std_logic; - detached_o : out std_logic; - cfg_init_n_i : in std_logic; - cfg_done_i : in std_logic; - dat_done_i : in std_logic; - cfg_clk_o : out std_logic; - cfg_dat_o : out std_logic - ); - end component; - - signal spi_clk_s : std_logic; - signal spi_cs_n_s : std_logic; - signal spi_data_out_s : std_logic; - signal spi_en_outs_s : std_logic; - - signal set_sel_s : std_logic_vector(3 downto 0); - -begin - - set_sel_s <= not set_sel_n_i; - - spi_boot_b : spi_boot - generic map ( - width_set_sel_g => 4, -- 16 sets - width_bit_cnt_g => 12, -- 512 bytes per block - width_img_cnt_g => 2, -- 4 images - num_bits_per_img_g => 18, -- 256 kByte per image - sd_init_g => 1, -- SD specific initialization - mmc_compat_clk_div_g => 0, -- no MMC compatibility - width_mmc_clk_div_g => 0 -- no MMC compatibility - ) - port map ( - clk_i => clk_i, - reset_i => reset_i, - set_sel_i => set_sel_s, - spi_clk_o => spi_clk_s, - spi_cs_n_o => spi_cs_n_s, - spi_data_in_i => spi_data_in_i, - spi_data_out_o => spi_data_out_s, - spi_en_outs_o => spi_en_outs_s, - start_i => start_i, - mode_i => mode_i, - config_n_o => config_n_o, - detached_o => detached_o, - cfg_init_n_i => cfg_init_n_i, - cfg_done_i => cfg_done_i, - dat_done_i => dat_done_i, - cfg_clk_o => cfg_clk_o, - cfg_dat_o => cfg_dat_o - ); - - ----------------------------------------------------------------------------- - -- Three state drivers for SPI outputs. - ----------------------------------------------------------------------------- - spi_clk_o <= spi_clk_s - when spi_en_outs_s = '1' else - 'Z'; - spi_cs_n_o <= spi_cs_n_s - when spi_en_outs_s = '1' else - 'Z'; - spi_data_out_o <= spi_data_out_s - when spi_en_outs_s = '1' else - 'Z'; - -end sd; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: chip-sd-a.vhd,v $ --- Revision 1.6 2005/04/07 20:44:23 arniml --- add new port detached_o --- --- Revision 1.5 2005/03/09 19:48:34 arniml --- invert level of set_sel input --- --- Revision 1.4 2005/03/08 22:07:12 arniml --- added set selection --- --- Revision 1.3 2005/02/18 06:42:14 arniml --- clarify wording for images --- --- Revision 1.2 2005/02/16 18:54:39 arniml --- added tri-state drivers for spi outputs --- --- Revision 1.1 2005/02/08 20:41:32 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd deleted file mode 100644 index 91e41ddfb..000000000 --- a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd +++ /dev/null @@ -1,19 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: chip-sd-c.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration chip_sd_c0 of chip is - - for sd - - for spi_boot_b : spi_boot - use configuration work.spi_boot_rtl_c0; - end for; - - end for; - -end chip_sd_c0; diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd deleted file mode 100644 index 8b26c4d57..000000000 --- a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd +++ /dev/null @@ -1,10 +0,0 @@ -------------------------------------------------------------------------------- --- $Id: ram_loader-c.vhd,v 1.1 2005/04/10 18:02:32 arniml Exp $ -------------------------------------------------------------------------------- - -configuration ram_loader_rtl_c0 of ram_loader is - - for rtl - end for; - -end ram_loader_rtl_c0; diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd deleted file mode 100644 index c604876d7..000000000 --- a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd +++ /dev/null @@ -1,355 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Sample client for loading an image to asynchronous SRAM --- --- $Id: ram_loader.vhd,v 1.2 2005/04/10 17:17:23 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -entity ram_loader is - - port ( - -- Global Interface ------------------------------------------------------- - clk_i : in std_logic; - reset_i : in std_logic; - lamp_o : out std_logic; - -- Config Interface ------------------------------------------------------- - cfg_clk_i : in std_logic; - cfg_data_i : in std_logic; - start_o : out std_logic; - mode_o : out std_logic; - done_o : out std_logic; - detached_i : in std_logic; - -- Asynchronous RAM Interface --------------------------------------------- - ram_addr_o : out std_logic_vector(15 downto 0); - ram_data_b : out std_logic_vector( 7 downto 0); - ram_ce_no : out std_logic_vector( 3 downto 0); - ram_oe_no : out std_logic; - ram_we_no : out std_logic - ); - -end ram_loader; - - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of ram_loader is - - signal addr_q : unsigned(17 downto 0); - signal inc_addr_s : boolean; - - signal shift_dat_q : std_logic_vector(7 downto 0); - signal ser_dat_q : std_logic_vector(7 downto 0); - signal bit_q : unsigned(2 downto 0); - signal bit_ovfl_q : boolean; - - type fsm_t is (IDLE, - WE_ON, - WE_OFF, - INC_ADDR1, INC_ADDR2, - FINISHED); - signal fsm_s, - fsm_q : fsm_t; - signal done_q : std_logic; - signal done_s : boolean; - signal mode_q, - mode_s : std_logic; - - signal ram_we_n_q, - ram_we_n_s : std_logic; - signal ram_ce_n_q, - ram_ce_n_s : std_logic_vector(3 downto 0); - - type start_fsm_t is (WAIT_DETACH, - CHECK_NO_DONE, - WAIT_DONE); - signal start_fsm_s, - start_fsm_q : start_fsm_t; - - signal start_s, - start_q : std_logic; - signal enable_s, - enable_q : boolean; - -begin - - ----------------------------------------------------------------------------- - -- Process seq - -- - -- Purpose: - -- Implements the sequential elements clocked with cfg_clk_i. - -- - seq: process (cfg_clk_i, reset_i) - begin - if reset_i = '0' then - addr_q <= (others => '0'); - shift_dat_q <= (others => '0'); - ser_dat_q <= (others => '0'); - bit_q <= (others => '0'); - bit_ovfl_q <= false; - fsm_q <= IDLE; - ram_we_n_q <= '1'; - ram_ce_n_q <= (others => '1'); - done_q <= '0'; - mode_q <= '0'; - - elsif cfg_clk_i'event and cfg_clk_i = '1' then - if inc_addr_s then - addr_q <= addr_q + 1; - end if; - - if enable_q then - bit_q <= bit_q + 1; - bit_ovfl_q <= bit_q = 7; - - shift_dat_q(0) <= cfg_data_i; - shift_dat_q(7 downto 1) <= shift_dat_q(6 downto 0); - end if; - - -- update register when 8 serial bits have been shifted in - if bit_ovfl_q then - ser_dat_q <= shift_dat_q; - end if; - - fsm_q <= fsm_s; - - ram_we_n_q <= ram_we_n_s; - ram_ce_n_q <= ram_ce_n_s; - - -- done only settable once - if done_s then - done_q <= '1'; - end if; - - mode_q <= mode_s; - - end if; - end process seq; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process fsm - -- - -- Purpose: - -- Implements the combinational logic of the RAM loader FSM. - -- - fsm: process (fsm_q, - bit_ovfl_q, - start_q, - addr_q) - begin - -- default assignments - inc_addr_s <= false; - ram_we_n_s <= '1'; - done_s <= false; - fsm_s <= IDLE; - lamp_o <= '1'; - mode_s <= '0'; - - case fsm_q is - when IDLE => - lamp_o <= '0'; - if start_q = '1' then - if bit_ovfl_q then - fsm_s <= WE_ON; - end if; - end if; - - when WE_ON => - ram_we_n_s <= '0'; - fsm_s <= WE_OFF; - - when WE_OFF => - fsm_s <= INC_ADDR1; - - when INC_ADDR1 => - fsm_s <= INC_ADDR2; - - when INC_ADDR2 => - if addr_q = "001111111111111111" then -- load only 64k - fsm_s <= FINISHED; - done_s <= true; - mode_s <= '1'; - else - inc_addr_s <= true; - fsm_s <= IDLE; - end if; - - when FINISHED => - fsm_s <= FINISHED; - lamp_o <= '1'; - mode_s <= '1'; - - when others => - end case; - - end process fsm; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process ce_gen - -- - -- Purpose: - -- Generates the four CE signals for the external RAM chips. - -- - ce_gen: process (addr_q) - begin - ram_ce_n_s <= (others => '1'); - ram_ce_n_s(to_integer(addr_q(17 downto 16))) <= '0'; - end process ce_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process start_seq - -- - -- Purpose: - -- Implements the sequential elements clocked with clk_i. - -- - start_seq: process (clk_i, reset_i) - begin - if reset_i = '0' then - start_fsm_q <= WAIT_DETACH; - start_q <= '0'; - enable_q <= false; - - elsif clk_i'event and clk_i = '1' then - start_fsm_q <= start_fsm_s; - - enable_q <= enable_s; - - start_q <= start_s; - - end if; - end process start_seq; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process start_comb - -- - -- Purpose: - -- Implements the combinational logic of the start FSM. - -- - start_comb: process (start_fsm_q, - detached_i, - done_q, - enable_q, - start_q) - begin - -- default assignments - start_fsm_s <= WAIT_DETACH; - enable_s <= enable_q; - start_s <= start_q; - - case start_fsm_q is - -- Wait for detached_i to become '1' - -- This state is entered/left twice: - -- 1. after reset to start the data download - -- 2. after data download to start the next configuration cycle - when WAIT_DETACH => - if detached_i = '1' then - start_fsm_s <= CHECK_NO_DONE; - enable_s <= true; - start_s <= '1'; - - else - start_fsm_s <= WAIT_DETACH; - end if; - - -- Wait until done_q is '0' - -- This ensures that the FSM stalls when it has started the configuration - -- download. There must be no further action in this case. - when CHECK_NO_DONE => - if done_q = '0' then - start_fsm_s <= WAIT_DONE; - else - start_fsm_s <= CHECK_NO_DONE; - end if; - - -- Wait until done_q is '1' - -- done_q is the signal that the main FSM has finished its work. We - -- need to start the configuration download. - when WAIT_DONE => - if done_q = '1' then - start_fsm_s <= WAIT_DETACH; - enable_s <= false; - start_s <= '0'; - else - start_fsm_s <= WAIT_DONE; - end if; - - when others => - null; - - end case; - - end process start_comb; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output Mapping - ----------------------------------------------------------------------------- - start_o <= start_q; - mode_o <= mode_q; - done_o <= done_q - when start_q = '1' else - '1'; - ram_addr_o <= std_logic_vector(addr_q(15 downto 0)); - ram_data_b <= ser_dat_q; - ram_oe_no <= '1'; - ram_ce_no <= ram_ce_n_q; - ram_we_no <= ram_we_n_q; - -end rtl; diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd deleted file mode 100644 index 6f11ed34b..000000000 --- a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd +++ /dev/null @@ -1,27 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: spi_boot-c.vhd,v 1.2 2005/02/18 06:42:11 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration spi_boot_rtl_c0 of spi_boot is - - for rtl - - for img_cnt - for img_cnt_b : spi_counter - use configuration work.spi_counter_rtl_c0; - end for; - end for; - - for mmc_cnt - for mmc_cnt_b : spi_counter - use configuration work.spi_counter_rtl_c0; - end for; - end for; - - end for; - -end spi_boot_rtl_c0; diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot.vhd deleted file mode 100644 index 3d2b81da7..000000000 --- a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot.vhd +++ /dev/null @@ -1,979 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: spi_boot.vhd,v 1.9 2007/02/25 18:24:12 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -entity spi_boot is - - generic ( - -- width of set selection - width_set_sel_g : integer := 4; - -- width of bit counter: minimum 6, maximum 12 - width_bit_cnt_g : integer := 6; - -- width of image counter: minimum 0, maximum n - width_img_cnt_g : integer := 2; - -- number of bits required to address one image - num_bits_per_img_g : integer := 18; - -- SD specific initialization - sd_init_g : integer := 0; - -- clock divider to reach 400 kHz for MMC compatibility - mmc_compat_clk_div_g : integer := 0; - width_mmc_clk_div_g : integer := 0; - -- active level of reset_i - reset_level_g : integer := 0 - ); - - port ( - -- System Interface ------------------------------------------------------- - clk_i : in std_logic; - reset_i : in std_logic; - set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); - -- Card Interface --------------------------------------------------------- - spi_clk_o : out std_logic; - spi_cs_n_o : out std_logic; - spi_data_in_i : in std_logic; - spi_data_out_o : out std_logic; - spi_en_outs_o : out std_logic; - -- FPGA Configuration Interface ------------------------------------------- - start_i : in std_logic; - mode_i : in std_logic; - config_n_o : out std_logic; - detached_o : out std_logic; - cfg_init_n_i : in std_logic; - cfg_done_i : in std_logic; - dat_done_i : in std_logic; - cfg_clk_o : out std_logic; - cfg_dat_o : out std_logic - ); - -end spi_boot; - - -library ieee; -use ieee.numeric_std.all; -use work.spi_boot_pack.all; - -architecture rtl of spi_boot is - - component spi_counter - generic ( - cnt_width_g : integer := 4; - cnt_max_g : integer := 15 - ); - port ( - clk_i : in std_logic; - reset_i : in boolean; - cnt_en_i : in boolean; - cnt_o : out std_logic_vector(cnt_width_g-1 downto 0); - cnt_ovfl_o : out boolean - ); - end component; - - - ----------------------------------------------------------------------------- - -- States of the controller FSM - -- - type ctrl_states_t is (POWER_UP1, POWER_UP2, - CMD0, - CMD1, - CMD55, ACMD41, - CMD16, - WAIT_START, - WAIT_INIT_LOW, WAIT_INIT_HIGH, - CMD18, CMD18_DATA, - CMD12, - INC_IMG_CNT); - -- - signal ctrl_fsm_q, - ctrl_fsm_s : ctrl_states_t; - -- - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - -- States of the command FSM - -- - type cmd_states_t is (CMD, START, R1, PAUSE); - -- - signal cmd_fsm_q, - cmd_fsm_s : cmd_states_t; - -- - ----------------------------------------------------------------------------- - - subtype op_r is integer range 5 downto 0; - type res_bc_t is (NONE, RES_MAX, RES_47, RES_15, RES_7); - signal bit_cnt_q : unsigned(width_bit_cnt_g-1 downto 0); - signal res_bc_s : res_bc_t; - signal upper_bitcnt_zero_s : boolean; - - signal cfg_dat_q : std_logic; - - signal spi_clk_q : std_logic; - signal spi_clk_rising_q : boolean; - signal spi_clk_falling_q : boolean; - signal spi_dat_q, - spi_dat_s : std_logic; - signal spi_cs_n_q, - spi_cs_n_s : std_logic; - - signal cfg_clk_q : std_logic; - - signal start_q : std_logic; - - signal img_cnt_s : std_logic_vector(width_img_cnt_g downto 0); - signal cnt_en_img_s : boolean; - signal mmc_cnt_ovfl_s : boolean; - signal mmc_compat_s : boolean; - - signal cmd_finished_s : boolean; - - signal r1_result_q : std_logic; - signal done_q, - send_cmd12_q : boolean; - - signal en_outs_s, - en_outs_q : boolean; - - signal reset_s : boolean; - - signal true_s : boolean; - -begin - - true_s <= true; - - reset_s <= true - when (reset_level_g = 1 and reset_i = '1') or - (reset_level_g = 0 and reset_i = '0') else - false; - - ----------------------------------------------------------------------------- - -- Process seq - -- - -- Purpose: - -- Implements several sequential elements. - -- - seq: process (clk_i, reset_s) - - variable bit_cnt_v : unsigned(1 downto 0); - - begin - if reset_s then - -- reset bit counter to 63 for power up - bit_cnt_q <= (others => '0'); - bit_cnt_q(op_r) <= "111111"; - spi_dat_q <= '1'; - spi_cs_n_q <= '1'; - cfg_dat_q <= '1'; - start_q <= '0'; - done_q <= false; - send_cmd12_q <= false; - ctrl_fsm_q <= POWER_UP1; - cmd_fsm_q <= CMD; - r1_result_q <= '0'; - en_outs_q <= false; - - elsif clk_i'event and clk_i = '1' then - -- bit counter control - if spi_clk_rising_q then - case res_bc_s is - when NONE => - bit_cnt_q <= bit_cnt_q - 1; - when RES_MAX => - bit_cnt_q <= (others => '1'); - when RES_47 => - bit_cnt_q <= (others => '0'); - bit_cnt_q(op_r) <= "101111"; - when RES_15 => - bit_cnt_q <= (others => '0'); - bit_cnt_q(op_r) <= "001111"; - when RES_7 => - bit_cnt_q <= (others => '0'); - bit_cnt_q(op_r) <= "000111"; - when others => - bit_cnt_q <= (others => '0'); - end case; - end if; - - -- Card data output register - -- spi_clk_falling_q acts as enable during MMC clock compatibility mode. - -- As soon as this mode is left, the register must start latching. - -- There is no explicit relation to spi_clk_q anymore in normal mode. - -- Instead, spi_dat_s is operated by bit_cnt_q above which changes its - -- value after the rising edge of spi_clk_q. - -- -> spi_dat_q changes upon falling edge of spi_clk_q - if spi_clk_falling_q or not mmc_compat_s then - spi_dat_q <= spi_dat_s; - end if; - - -- config data output register - -- a new value is loaded when config clock is high, - -- i.e. input data is sampled with rising spi_clk - -- while output value changes on falling edge of cfg_clk - if cfg_clk_q = '1' and spi_clk_rising_q then - cfg_dat_q <= spi_data_in_i; - end if; - - -- Controller FSM state - ctrl_fsm_q <= ctrl_fsm_s; - - -- Command FSM state - cmd_fsm_q <= cmd_fsm_s; - - -- CS signal for SPI card - if spi_clk_q = '1' then - spi_cs_n_q <= spi_cs_n_s; - end if; - - -- Extract flags from R1 response - if cmd_fsm_q = R1 then - bit_cnt_v := bit_cnt_q(1 downto 0); - case bit_cnt_v(1 downto 0) is - when "10" => - -- always save "Illegal Command" flag - r1_result_q <= to_X01(spi_data_in_i); - when "00" => - -- overwrite with "Idle State" flag when not in CMD55 - if ctrl_fsm_q /= CMD55 then - r1_result_q <= to_X01(spi_data_in_i); - end if; - when others => - null; - end case; - end if; - - -- Start trigger register for rising edge detection - -- the reset value is '0' thus a rising edge will always be detected - -- after reset even though start_i is tied to '1' - if start_i = '0' then - start_q <= '0'; - elsif ctrl_fsm_q = WAIT_START and cmd_finished_s then - start_q <= start_i; - end if; - - -- Marker for cfg_done and dat_done - if ctrl_fsm_q = CMD18_DATA then - if cfg_done_i = '1' and dat_done_i = '1' then - done_q <= true; - end if; - - if done_q and - (not upper_bitcnt_zero_s or cmd_fsm_q = START) then - -- activate sending of CMD12 when it is safe: - -- * upper bits of bit counter are not zero - -- -> transmission of CMD12 is not running - -- * cmd FSM is in START state - -- -> also no transmission running - send_cmd12_q <= true; - end if; - elsif ctrl_fsm_q = WAIT_START then - -- reset done_q when WAIT_START has been reached - -- this is necessary to let the stop transmission process come to - -- an end without interruption or generation of unwanted cfg_clk_q - done_q <= false; - send_cmd12_q <= false; - end if; - - -- output enable - if spi_clk_rising_q then - en_outs_q <= en_outs_s; - end if; - - end if; - - end process seq; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process upper_bits - -- - -- Purpose: - -- Detects that the upper bits of the bit counter are zero. - -- Upper bits = n downto 6, i.e. the optional part that is not required for - -- commands but for extension of data blocks. - -- - upper_bits: process (bit_cnt_q) - variable zero_v : boolean; - begin - - zero_v := true; - for i in bit_cnt_q'high downto 6 loop - if bit_cnt_q(i) = '1' then - zero_v := false; - end if; - end loop; - - upper_bitcnt_zero_s <= zero_v; - - end process upper_bits; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process clk_gen - -- - -- Purpose: - -- Generates clocks for card and FPGA configuration. - -- The card clock is free running with a divide by two of clk_i. - -- The clock for FPGA config has an enable and is stopped on high level. - -- There is a phase shift of half a period between spi_clk and cfg_clk. - -- - clk_gen: process (clk_i, reset_s) - begin - if reset_s then - spi_clk_q <= '0'; - cfg_clk_q <= '1'; - - elsif clk_i'event and clk_i = '1' then - - -- spi_clk_q rises according to the flag - -- it falls with overflow indication - -- the resulting duty cycle is not exactly 50:50, - -- high time is a bit longer - if mmc_compat_s then - -- MMC clock compatibility mode: - -- spi_clk_q rises when flagged by spi_clk_rising_q - if spi_clk_rising_q then - spi_clk_q <= '1'; - elsif mmc_cnt_ovfl_s then - -- upon counter overflow spi_clk_q falls in case it does not rise - spi_clk_q <= '0'; - end if; - else - -- normal mode - -- spi_clk_q follows spi_clk_rising_q - if spi_clk_rising_q then - spi_clk_q <= '1'; - else - spi_clk_q <= '0'; - end if; - end if; - - -- clock for FPGA config must be enabled and follows spi_clk - if ctrl_fsm_q = CMD18_DATA and cmd_fsm_q = CMD and - not done_q then - cfg_clk_q <= spi_clk_q; - else - cfg_clk_q <= '1'; - end if; - - end if; - - end process clk_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Indication flags for rising and falling spi_clk_q. - -- Essential for MMC clock compatibility mode. - ----------------------------------------------------------------------------- - mmc_comap: if mmc_compat_clk_div_g > 0 generate - mmc_compat_sig: process (clk_i, reset_s) - begin - if reset_s then - spi_clk_rising_q <= false; - spi_clk_falling_q <= false; - - elsif clk_i'event and clk_i = '1' then - if mmc_compat_s then - -- MMC clock compatibility mode: - -- spi_clk_rising_q is an impulse right before rising edge of spi_clk_q - -- spi_clk_falling_q is an impulse right before falling edge of spi_clk_q - if mmc_cnt_ovfl_s then - spi_clk_rising_q <= spi_clk_q = '0'; - spi_clk_falling_q <= spi_clk_q = '1'; - else - spi_clk_rising_q <= false; - spi_clk_falling_q <= false; - end if; - else - -- normal mode - spi_clk_rising_q <= not spi_clk_rising_q; - spi_clk_falling_q <= true; - end if; - - end if; - end process mmc_compat_sig; - end generate; - - no_mmc_compat: if mmc_compat_clk_div_g = 0 generate - -- SPI clock rising whenever spi_clk_q is '0' - spi_clk_rising_q <= spi_clk_q = '0'; - -- SPI clock falling whenever spi_clk_q is '1' - spi_clk_falling_q <= spi_clk_q = '1'; - end generate; - - - ----------------------------------------------------------------------------- - -- Process ctrl_fsm - -- - -- Purpose: - -- Implements the controller FSM. - -- - ctrl_fsm: process (ctrl_fsm_q, - cmd_finished_s, r1_result_q, - start_i, start_q, mode_i, - cfg_init_n_i) - - variable mmc_compat_v : boolean; - - begin - -- default assignments - ctrl_fsm_s <= POWER_UP1; - config_n_o <= '1'; - cnt_en_img_s <= false; - spi_cs_n_s <= '0'; - mmc_compat_v := false; - en_outs_s <= true; - - case ctrl_fsm_q is - -- Let card finish power up, step 1 ------------------------------------- - when POWER_UP1 => - mmc_compat_v := true; - spi_cs_n_s <= '1'; - if cmd_finished_s then - ctrl_fsm_s <= POWER_UP2; - else - ctrl_fsm_s <= POWER_UP1; - end if; - - - -- Let card finish power up, step 2 ------------------------------------- - when POWER_UP2 => - mmc_compat_v := true; - if cmd_finished_s then - ctrl_fsm_s <= CMD0; - else - spi_cs_n_s <= '1'; - ctrl_fsm_s <= POWER_UP2; - end if; - - - -- Issue CMD0: GO_IDLE_STATE -------------------------------------------- - when CMD0 => - mmc_compat_v := true; - if cmd_finished_s then - if sd_init_g = 1 then - ctrl_fsm_s <= CMD55; - else - ctrl_fsm_s <= CMD1; - end if; - else - ctrl_fsm_s <= CMD0; - end if; - - - -- Issue CMD55: APP_CMD ------------------------------------------------- - when CMD55 => - if sd_init_g = 1 then - - mmc_compat_v := true; - if cmd_finished_s then - if r1_result_q = '0' then - -- command accepted, it's an SD card - ctrl_fsm_s <= ACMD41; - else - -- command rejected, it's an MMC card - ctrl_fsm_s <= CMD1; - end if; - else - ctrl_fsm_s <= CMD55; - end if; - - end if; - - - -- Issue ACMD41: SEND_OP_COND ------------------------------------------- - when ACMD41 => - if sd_init_g = 1 then - - mmc_compat_v := true; - if cmd_finished_s then - if r1_result_q = '0' then - ctrl_fsm_s <= CMD16; - else - ctrl_fsm_s <= CMD55; - end if; - else - ctrl_fsm_s <= ACMD41; - end if; - - end if; - - - -- Issue CMD1: SEND_OP_COND --------------------------------------------- - when CMD1 => - mmc_compat_v := true; - if cmd_finished_s then - if r1_result_q = '0' then - ctrl_fsm_s <= CMD16; - else - ctrl_fsm_s <= CMD1; - end if; - else - ctrl_fsm_s <= CMD1; - end if; - - - -- Issue CMD16: SET_BLOCKLEN -------------------------------------------- - when CMD16 => - if cmd_finished_s then - ctrl_fsm_s <= WAIT_START; - else - ctrl_fsm_s <= CMD16; - end if; - - - -- Wait for configuration start request --------------------------------- - when WAIT_START => - spi_cs_n_s <= '1'; - - -- detect rising edge of start_i - if start_i = '1' and start_q = '0' then - -- decide which mode is requested - if cmd_finished_s then - if mode_i = '0' then - ctrl_fsm_s <= CMD18; - else - ctrl_fsm_s <= WAIT_INIT_LOW; - end if; - else - en_outs_s <= false; - ctrl_fsm_s <= WAIT_START; - end if; - else - en_outs_s <= false; - ctrl_fsm_s <= WAIT_START; - end if; - - - -- Wait for INIT to become low ------------------------------------------ - when WAIT_INIT_LOW => - spi_cs_n_s <= '1'; - -- activate FPGA configuration - config_n_o <= '0'; - - if cfg_init_n_i = '0' then - ctrl_fsm_s <= WAIT_INIT_HIGH; - else - ctrl_fsm_s <= WAIT_INIT_LOW; - end if; - - - -- Wait for INIT to become high ----------------------------------------- - when WAIT_INIT_HIGH => - spi_cs_n_s <= '1'; - - if cfg_init_n_i = '1' and cmd_finished_s then - ctrl_fsm_s <= CMD18; - else - ctrl_fsm_s <= WAIT_INIT_HIGH; - end if; - - - -- Issue CMD18: READ_MULTIPLE_BLOCKS ------------------------------------ - when CMD18 => - if cmd_finished_s then - ctrl_fsm_s <= CMD18_DATA; - else - ctrl_fsm_s <= CMD18; - end if; - -- - -- receive a data block - when CMD18_DATA => - if cmd_finished_s then - ctrl_fsm_s <= CMD12; - else - ctrl_fsm_s <= CMD18_DATA; - end if; - - - -- Issued CMD12: STOP_TRANSMISSION -------------------------------------- - when CMD12 => - if cmd_finished_s then - ctrl_fsm_s <= INC_IMG_CNT; - else - ctrl_fsm_s <= CMD12; - end if; - - - -- Increment Image Counter ---------------------------------------------- - when INC_IMG_CNT => - spi_cs_n_s <= '1'; - ctrl_fsm_s <= WAIT_START; - cnt_en_img_s <= true; - - - - when others => - null; - - end case; - - -- mmc_compat_s is suppressed if MMC clock compatibility is not required - if mmc_compat_clk_div_g > 0 then - mmc_compat_s <= mmc_compat_v; - else - mmc_compat_s <= false; - end if; - - end process ctrl_fsm; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process cmd_fsm - -- - -- Purpose: - -- Implements the command FSM. - -- - cmd_fsm: process (spi_clk_rising_q, - spi_data_in_i, - bit_cnt_q, - ctrl_fsm_q, - cmd_fsm_q, - send_cmd12_q) - - variable cnt_zero_v : boolean; - variable spi_data_low_v : boolean; - variable no_startbit_v : boolean; - - begin - -- default assignments - cmd_finished_s <= false; - cmd_fsm_s <= CMD; - res_bc_s <= NONE; - - cnt_zero_v := spi_clk_rising_q and bit_cnt_q = 0; - spi_data_low_v := spi_clk_rising_q and spi_data_in_i = '0'; - - -- these are no real commands thus there will be no startbit - case ctrl_fsm_q is - when POWER_UP1 | POWER_UP2 | - WAIT_START | WAIT_INIT_HIGH | WAIT_INIT_LOW => - no_startbit_v := true; - when others => - no_startbit_v := false; - end case; - - - case cmd_fsm_q is - -- Send the command ----------------------------------------------------- - when CMD => - if cnt_zero_v then - if ctrl_fsm_q /= CMD18_DATA then - -- normal commands including CMD12 require startbit of R1 response - cmd_fsm_s <= START; - else - if not send_cmd12_q then - -- CMD18_DATA needs to read CRC - cmd_fsm_s <= R1; - res_bc_s <= RES_15; - else - -- CMD18_DATA finished, scan for startbit of response - cmd_finished_s <= true; - cmd_fsm_s <= START; - end if; - end if; - else - cmd_fsm_s <= CMD; - end if; - - -- Wait for startbit of response ---------------------------------------- - when START => - -- startbit detection or skip of this check - if no_startbit_v and spi_clk_rising_q then - cmd_fsm_s <= R1; - res_bc_s <= RES_7; - elsif spi_data_low_v then - if ctrl_fsm_q /= CMD18_DATA then - cmd_fsm_s <= R1; - else - -- CMD18_DATA startbit detected, read payload - cmd_fsm_s <= CMD; - res_bc_s <= RES_MAX; - end if; - else - cmd_fsm_s <= START; - res_bc_s <= RES_7; - end if; - - -- Read R1 response ----------------------------------------------------- - when R1 => - if cnt_zero_v then - res_bc_s <= RES_7; - - if not (ctrl_fsm_q = CMD18 or ctrl_fsm_q = CMD18_DATA) then - cmd_fsm_s <= PAUSE; - else - -- CMD18 needs another startbit detection for the data token. - -- CMD18_DATA needs a startbit after having received the CRC, either - -- * next data token - -- * R1 response of CMD12 - cmd_fsm_s <= START; - - if ctrl_fsm_q = CMD18 then - -- CMD18 response received -> advance to CMD18_DATA - cmd_finished_s <= true; - end if; - end if; - else - cmd_fsm_s <= R1; - end if; - - -- PAUSE state -> required for Nrc, card response to host command ------- - when PAUSE => - if cnt_zero_v then - cmd_fsm_s <= CMD; - res_bc_s <= RES_47; - cmd_finished_s <= true; - else - cmd_fsm_s <= PAUSE; - end if; - - when others => - null; - - end case; - - end process cmd_fsm; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process transmit - -- - -- Purpose: - -- Generates the serial data output values based on the current FSM state - -- - -- The local variable cmd_v is 64 bits wide in contrast to an SPI command - -- with 48 bits. There are two reasons for this: - -- * During "overlaid" sending of CMD12 in FSM state CMD18_DATA, the bit - -- counter will start from 3F on its lowest 6 bits. Therefore, it is - -- necessary to provide all 64 positions in cmd_v. - -- * Reduces logic. - -- - transmit: process (ctrl_fsm_q, - cmd_fsm_q, - bit_cnt_q, - img_cnt_s, - send_cmd12_q, - set_sel_i, - upper_bitcnt_zero_s) - - subtype cmd_r is natural range 47 downto 0; - subtype cmd_t is std_logic_vector(cmd_r); - subtype ext_cmd_t is std_logic_vector(63 downto 0); - -- STCCCCCCAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAcccccccS - constant cmd0_c : cmd_t := "010000000000000000000000000000000000000010010101"; - constant cmd1_c : cmd_t := "0100000100000000000000000000000000000000-------1"; - constant cmd12_c : cmd_t := "0100110000000000000000000000000000000000-------1"; - constant cmd16_c : cmd_t := "0101000000000000000000000000000000000000-------1"; - constant cmd18_c : cmd_t := "0101001000000000000000000000000000000000-------1"; - constant cmd55_c : cmd_t := "0111011100000000000000000000000000000000-------1"; - constant acmd41_c : cmd_t := "0110100100000000000000000000000000000000-------1"; - - variable cmd_v : ext_cmd_t; - variable tx_v : boolean; - - begin - -- default assignments - spi_dat_s <= '1'; - cmd_v := (others => '1'); - tx_v := false; - - if cmd_fsm_q = CMD then - case ctrl_fsm_q is - when CMD0 => - cmd_v(cmd_r) := cmd0_c; - tx_v := true; - when CMD1 => - cmd_v(cmd_r) := cmd1_c; - tx_v := true; - when CMD16 => - cmd_v(cmd_r) := cmd16_c; - cmd_v(8 + width_bit_cnt_g-3) := '1'; - tx_v := true; - when CMD18 => - cmd_v(cmd_r) := cmd18_c; - -- insert image counter - cmd_v(8 + num_bits_per_img_g + width_img_cnt_g - downto 8 + num_bits_per_img_g) := img_cnt_s; - -- insert set selection - cmd_v(8 + num_bits_per_img_g + width_img_cnt_g + width_set_sel_g-1 - downto 8 + num_bits_per_img_g + width_img_cnt_g) := set_sel_i; - tx_v := true; - when CMD18_DATA => - cmd_v(cmd_r) := cmd12_c; - - if send_cmd12_q and upper_bitcnt_zero_s then - tx_v := true; - end if; - when CMD55 => - cmd_v(cmd_r) := cmd55_c; - tx_v := true; - when ACMD41 => - cmd_v(cmd_r) := acmd41_c; - tx_v := true; - - when others => - null; - end case; - end if; - - if tx_v then - spi_dat_s <= cmd_v(to_integer(bit_cnt_q(5 downto 0))); - end if; - - end process transmit; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Optional Image Counter - ----------------------------------------------------------------------------- - img_cnt: if width_img_cnt_g > 0 generate - img_cnt_b : spi_counter - generic map ( - cnt_width_g => width_img_cnt_g, - cnt_max_g => 2**width_img_cnt_g - 1 - ) - port map ( - clk_i => clk_i, - reset_i => reset_s, - cnt_en_i => cnt_en_img_s, - cnt_o => img_cnt_s(width_img_cnt_g-1 downto 0), - cnt_ovfl_o => open - ); - img_cnt_s(width_img_cnt_g) <= '0'; - end generate; - - no_img_cnt: if width_img_cnt_g = 0 generate - img_cnt_s <= (others => '0'); - end generate; - - - ----------------------------------------------------------------------------- - -- Optional MMC compatibility counter - ----------------------------------------------------------------------------- - mmc_cnt: if mmc_compat_clk_div_g > 0 generate - mmc_cnt_b : spi_counter - generic map ( - cnt_width_g => width_mmc_clk_div_g, - cnt_max_g => mmc_compat_clk_div_g - ) - port map ( - clk_i => clk_i, - reset_i => reset_s, - cnt_en_i => true_s, - cnt_o => open, - cnt_ovfl_o => mmc_cnt_ovfl_s - ); - end generate; - - no_mmc_cnt: if mmc_compat_clk_div_g = 0 generate - mmc_cnt_ovfl_s <= true; - end generate; - - - ----------------------------------------------------------------------------- - -- Output Mapping - ----------------------------------------------------------------------------- - spi_clk_o <= spi_clk_q; - spi_cs_n_o <= spi_cs_n_q; - spi_data_out_o <= spi_dat_q; - spi_en_outs_o <= '1' - when en_outs_q else - '0'; - cfg_clk_o <= cfg_clk_q; - cfg_dat_o <= cfg_dat_q; - detached_o <= '0' - when en_outs_q else - '1'; - -end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: spi_boot.vhd,v $ --- Revision 1.9 2007/02/25 18:24:12 arniml --- fix type handling of resets --- --- Revision 1.8 2006/09/11 23:03:36 arniml --- disable outputs with reset --- --- Revision 1.7 2005/04/07 20:44:23 arniml --- add new port detached_o --- --- Revision 1.6 2005/03/09 19:48:34 arniml --- invert level of set_sel input --- --- Revision 1.5 2005/03/08 22:07:12 arniml --- added set selection --- --- Revision 1.4 2005/02/18 06:42:08 arniml --- clarify wording for images --- --- Revision 1.3 2005/02/16 18:59:10 arniml --- include output enable control for SPI outputs --- --- Revision 1.2 2005/02/13 17:25:51 arniml --- major update to fix several problems --- configuration/data download of multiple sets works now --- --- Revision 1.1 2005/02/08 20:41:33 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd deleted file mode 100644 index ac8b544f9..000000000 --- a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd +++ /dev/null @@ -1,54 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: spi_boot_pack-p.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -package spi_boot_pack is - - function "=" (a : std_logic; b : integer) return boolean; - -end spi_boot_pack; - -package body spi_boot_pack is - - function "=" (a : std_logic; b : integer) return boolean is - variable result_v : boolean; - begin - result_v := false; - - case a is - when '0' => - if b = 0 then - result_v := true; - end if; - - when '1' => - if b = 1 then - result_v := true; - end if; - - when others => - null; - - end case; - - return result_v; - end; - -end spi_boot_pack; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: spi_boot_pack-p.vhd,v $ --- Revision 1.1 2005/02/08 20:41:33 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd deleted file mode 100644 index d81e20db6..000000000 --- a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd +++ /dev/null @@ -1,14 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: spi_counter-c.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration spi_counter_rtl_c0 of spi_counter is - - for rtl - end for; - -end spi_counter_rtl_c0; diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter.vhd deleted file mode 100644 index 8ec7357ea..000000000 --- a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter.vhd +++ /dev/null @@ -1,118 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Generic counter module --- --- $Id: spi_counter.vhd,v 1.2 2007/02/25 18:24:12 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -entity spi_counter is - - generic ( - cnt_width_g : integer := 4; - cnt_max_g : integer := 15 - ); - - port ( - clk_i : in std_logic; - reset_i : in boolean; - cnt_en_i : in boolean; - cnt_o : out std_logic_vector(cnt_width_g-1 downto 0); - cnt_ovfl_o : out boolean - ); - -end spi_counter; - - -library ieee; -use ieee.numeric_std.all; -use work.spi_boot_pack.all; - -architecture rtl of spi_counter is - - signal cnt_q : unsigned(cnt_width_g-1 downto 0); - signal cnt_ovfl_s : boolean; - -begin - - cnt: process (clk_i, reset_i) - begin - if reset_i then - cnt_q <= (others => '0'); - - elsif clk_i'event and clk_i = '1' then - if cnt_en_i then - if not cnt_ovfl_s then - cnt_q <= cnt_q + 1; - else - cnt_q <= (others => '0'); - end if; - end if; - end if; - end process cnt; - - cnt_ovfl_s <= cnt_q = cnt_max_g; - - - ----------------------------------------------------------------------------- - -- Output Mapping - ----------------------------------------------------------------------------- - cnt_ovfl_o <= cnt_ovfl_s; - cnt_o <= std_logic_vector(cnt_q); - -end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: spi_counter.vhd,v $ --- Revision 1.2 2007/02/25 18:24:12 arniml --- fix type handling of resets --- --- Revision 1.1 2005/02/08 20:41:33 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/Makefile b/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/Makefile deleted file mode 100644 index 46fb3c635..000000000 --- a/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/Makefile +++ /dev/null @@ -1,159 +0,0 @@ -############################################################################## -# -# Makefile for the spi_boot project. -# -# The dependencies for all VHDL source files are stored here. -# -# Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) -# -# All rights reserved -# -############################################################################## - - -PROJECT_DIR = ../.. -RTL_DIR = $(PROJECT_DIR)/rtl/vhdl -BENCH_DIR = $(PROJECT_DIR)/bench/vhdl - - - -ANALYZE=ghdl -a --std=87 --workdir=work -ELABORATE=ghdl -e --std=87 --workdir=work - -.PHONY: all -all: work elaborate - -work: - mkdir work - -work/spi_boot_pack-p.o: $(RTL_DIR)/spi_boot_pack-p.vhd - $(ANALYZE) $(RTL_DIR)/spi_boot_pack-p.vhd - -work/spi_counter.o: $(RTL_DIR)/spi_counter.vhd \ - work/spi_boot_pack-p.o - $(ANALYZE) $(RTL_DIR)/spi_counter.vhd -work/spi_counter-c.o: $(RTL_DIR)/spi_counter-c.vhd \ - work/spi_counter.o - $(ANALYZE) $(RTL_DIR)/spi_counter-c.vhd - -work/spi_boot.o: $(RTL_DIR)/spi_boot.vhd \ - work/spi_boot_pack-p.o - $(ANALYZE) $(RTL_DIR)/spi_boot.vhd -work/spi_boot-c.o: $(RTL_DIR)/spi_boot-c.vhd \ - work/spi_boot.o \ - work/spi_counter-c.o - $(ANALYZE) $(RTL_DIR)/spi_boot-c.vhd - -work/chip-e.o: $(RTL_DIR)/chip-e.vhd - $(ANALYZE) $(RTL_DIR)/chip-e.vhd - -work/chip-full-a.o: $(RTL_DIR)/chip-full-a.vhd \ - work/chip-e.o - $(ANALYZE) $(RTL_DIR)/chip-full-a.vhd -work/chip-full-c.o: $(RTL_DIR)/chip-full-c.vhd \ - work/chip-full-a.o \ - work/spi_boot-c.o - $(ANALYZE) $(RTL_DIR)/chip-full-c.vhd - -work/chip-mmc-a.o: $(RTL_DIR)/chip-mmc-a.vhd \ - work/chip-e.o - $(ANALYZE) $(RTL_DIR)/chip-mmc-a.vhd -work/chip-mmc-c.o: $(RTL_DIR)/chip-mmc-c.vhd \ - work/chip-mmc-a.o \ - work/spi_boot-c.o - $(ANALYZE) $(RTL_DIR)/chip-mmc-c.vhd - -work/chip-sd-a.o: $(RTL_DIR)/chip-sd-a.vhd \ - work/chip-e.o - $(ANALYZE) $(RTL_DIR)/chip-sd-a.vhd -work/chip-sd-c.o: $(RTL_DIR)/chip-sd-c.vhd \ - work/chip-sd-a.o \ - work/spi_boot-c.o - $(ANALYZE) $(RTL_DIR)/chip-sd-c.vhd - -work/chip-minimal-a.o: $(RTL_DIR)/chip-minimal-a.vhd \ - work/chip-e.o - $(ANALYZE) $(RTL_DIR)/chip-minimal-a.vhd -work/chip-minimal-c.o: $(RTL_DIR)/chip-minimal-c.vhd \ - work/chip-minimal-a.o \ - work/spi_boot-c.o - $(ANALYZE) $(RTL_DIR)/chip-minimal-c.vhd - -work/ram_loader.o: $(RTL_DIR)/sample/ram_loader.vhd - $(ANALYZE) $(RTL_DIR)/sample/ram_loader.vhd -work/ram_loader-c.o: $(RTL_DIR)/sample/ram_loader-c.vhd \ - work/ram_loader.o - $(ANALYZE) $(RTL_DIR)/sample/ram_loader-c.vhd - -work/tb_pack-p.o: $(BENCH_DIR)/tb_pack-p.vhd - $(ANALYZE) $(BENCH_DIR)/tb_pack-p.vhd - -work/card.o: $(BENCH_DIR)/card.vhd \ - work/tb_pack-p.o - $(ANALYZE) $(BENCH_DIR)/card.vhd -work/card-c.o: $(BENCH_DIR)/card-c.vhd \ - work/card.o - $(ANALYZE) $(BENCH_DIR)/card-c.vhd - -work/tb_elem.o: $(BENCH_DIR)/tb_elem.vhd \ - work/spi_boot_pack-p.o \ - work/tb_pack-p.o - $(ANALYZE) $(BENCH_DIR)/tb_elem.vhd -work/tb_elem-full-c.o: $(BENCH_DIR)/tb_elem-full-c.vhd \ - work/tb_elem.o \ - work/chip-full-c.o \ - work/card-c.o - $(ANALYZE) $(BENCH_DIR)/tb_elem-full-c.vhd -work/tb_elem-mmc-c.o: $(BENCH_DIR)/tb_elem-mmc-c.vhd \ - work/tb_elem.o \ - work/chip-mmc-c.o \ - work/card-c.o - $(ANALYZE) $(BENCH_DIR)/tb_elem-mmc-c.vhd -work/tb_elem-sd-c.o: $(BENCH_DIR)/tb_elem-sd-c.vhd \ - work/tb_elem.o \ - work/chip-sd-c.o \ - work/card-c.o - $(ANALYZE) $(BENCH_DIR)/tb_elem-sd-c.vhd -work/tb_elem-minimal-c.o: $(BENCH_DIR)/tb_elem-minimal-c.vhd \ - work/tb_elem.o \ - work/chip-minimal-c.o \ - work/card-c.o - $(ANALYZE) $(BENCH_DIR)/tb_elem-minimal-c.vhd - -work/tb.o: $(BENCH_DIR)/tb.vhd - $(ANALYZE) $(BENCH_DIR)/tb.vhd -work/tb-c.o: $(BENCH_DIR)/tb-c.vhd \ - work/tb.o \ - work/tb_elem-full-c.o \ - work/tb_elem-mmc-c.o \ - work/tb_elem-sd-c.o \ - work/tb_elem-minimal-c.o - $(ANALYZE) $(BENCH_DIR)/tb-c.vhd - -work/tb_rl.o: $(BENCH_DIR)/tb_rl.vhd - $(ANALYZE) $(BENCH_DIR)/tb_rl.vhd -work/tb_rl-c.o: $(BENCH_DIR)/tb_rl-c.vhd \ - work/tb_rl.o \ - work/chip-full-c.o \ - work/card-c.o \ - work/ram_loader-c.o - $(ANALYZE) $(BENCH_DIR)/tb_rl-c.vhd - - -.PHONY: elaborate -elaborate: tb_behav_c0 tb_rl_behav_c0 - -tb_behav_c0: work/tb-c.o - $(ELABORATE) tb_behav_c0; \ - strip tb_behav_c0 - -tb_rl_behav_c0: work/tb_rl-c.o - $(ELABORATE) tb_rl_behav_c0; \ - strip tb_rl_behav_c0 - -.PHONY: analyze -analyze: work/tb-c.o work/tb_rl-c.o - -.PHONY: clean -clean: - rm -rf work tb_behav_c0 tb_rl_behav_c0 *~ diff --git a/fpga/usrp2/opencores/spi_boot/sw/misc/bit_reverse.c b/fpga/usrp2/opencores/spi_boot/sw/misc/bit_reverse.c deleted file mode 100644 index 9defb106a..000000000 --- a/fpga/usrp2/opencores/spi_boot/sw/misc/bit_reverse.c +++ /dev/null @@ -1,74 +0,0 @@ -// Altera requires configuration bytes to be sent LSB first but the -// SD Card reads bytes MSB first -// This code reverses the bits of the altera bitstream so -// it will come out correct when read from the SD card -// $Log: bit_reverse.c,v $ -// Revision 1.1 2006/01/06 14:44:17 mbl -// initial version -// - - - -#include "stdio.h" -#include "string.h" - -FILE* fileOut; -FILE* fileIn; - -void outIOerror(char* pfn); -void inIOerror(char* pfn); - -int main(int argc, char* arg[]) -{ - unsigned char input, output; - unsigned char in_mask, out_mask; - int i; - - fileOut = fopen(arg[2],"wb"); - if (fileOut == NULL) - { - outIOerror(arg[2]); - exit(-1); - } - - printf("Opening input file %s\n", arg[1]); - fileIn = fopen(arg[1],"rb"); - if (fileIn == NULL) - { - inIOerror(arg[1]); - exit(-1); - } - - while (!feof(fileIn) && fgets((char*)&input, 2 ,fileIn) != NULL) - { - in_mask = 1; - out_mask = 0x80; - output = 0; - - for ( i=0; i < 8; ++i ) - { - if (input & in_mask) - { - output |= out_mask; - } - out_mask = out_mask >> 1; - in_mask = in_mask << 1; - } - fwrite((void*)&output,sizeof(char),1,fileOut); - } - - fclose(fileIn); - fclose(fileOut); - printf("\n%s has been created\n", arg[2]); - exit(0); -} - -void outIOerror(char *pfn) -{ - printf("I/O Error while writing to file=%s\n",pfn); -} - -void inIOerror(char *pfn) -{ - printf("I/O Error while reading file=%s\n",pfn); -} diff --git a/fpga/usrp2/opencores/wb_zbt/wb_zbt.v b/fpga/usrp2/opencores/wb_zbt/wb_zbt.v deleted file mode 100644 index 8f9232752..000000000 --- a/fpga/usrp2/opencores/wb_zbt/wb_zbt.v +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Multi-port ZBT SRAM WISHBONE controller - * Copyright (C) 2008 Sebastien Bourdeauducq - http://lekernel.net - * This file is part of Milkymist. - * - * Milkymist is free software; you can redistribute it and/or modify it - * under the terms of the GNU Library General Public License as published - * by the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Library General Public License for more details. - * - * You should have received a copy of the GNU Library General Public - * License along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, - * USA. - */ - -module wb_zbt( - input clk, - input rst, - // Wishbone bus A, highest priority, with prefetch - input [31:0] wbA_adr_i, - input [31:0] wbA_dat_i, - output [31:0] wbA_dat_o, - input [ 3:0] wbA_sel_i, - input wbA_cyc_i, - input wbA_stb_i, - output wbA_ack_o, - input wbA_we_i, - // Wishbone bus B, lower priority - input [31:0] wbB_adr_i, - input [31:0] wbB_dat_i, - output [31:0] wbB_dat_o, - input [ 3:0] wbB_sel_i, - input wbB_cyc_i, - input wbB_stb_i, - output wbB_ack_o, - input wbB_we_i, - // Memory connection - output sram_clk, - output [17:0] sram_a, - inout [31:0] sram_d, - output sram_we, - output [ 3:0] sram_bw, - output sram_adv, - output sram_ce, - output sram_oe, - output sram_mode, - output sram_zz -); - -assign sram_clk = clk; -assign sram_oe = 1'b0; -assign sram_ce = 1'b0; -assign sram_adv = 1'b0; -assign sram_mode = 1'b0; -assign sram_zz = 1'b0; - -/* Wishbone decoding */ - -wire busA_active; -wire busB_active; - -assign busA_active = wbA_cyc_i & wbA_stb_i; -assign busB_active = wbB_cyc_i & wbB_stb_i; - -/* Those are used to represent the state of the SRAM pipeline - * Bit 0 = Write Enable - * Bits 18..1 = Address - */ -wire [18:0] pipeline_in; -reg [18:0] pipeline_internal; -reg [18:0] pipeline_out; - -always @(posedge clk or posedge rst) begin - if(rst) begin - pipeline_internal <= 0; - pipeline_out <= 0; - end else begin - pipeline_internal <= pipeline_in; - pipeline_out <= pipeline_internal; - end -end - -/* Pipeline contents decode */ - -wire inprogressA; -wire inprogressB; - -assign inprogressA = (pipeline_internal[18:1] == wbA_adr_i[19:2]) & (pipeline_internal[0] == wbA_we_i); -assign inprogressB = (pipeline_internal[18:1] == wbB_adr_i[19:2]) & (pipeline_internal[0] == wbB_we_i); - -wire hitA; -wire hitB; - -assign hitA = (pipeline_out[18:1] == wbA_adr_i[19:2]) & (pipeline_out[0] == wbA_we_i); -assign hitB = (pipeline_out[18:1] == wbB_adr_i[19:2]) & (pipeline_out[0] == wbB_we_i); - -/* Access arbitration */ - -wire [1:0] bus_request; - -assign bus_request[0] = busA_active & ~inprogressA & ~hitA; -assign bus_request[1] = busB_active & ~inprogressB & ~hitB; - -wire prefetch_enable; -reg [17:0] prefetch_address; - -assign prefetch_enable = ~bus_request[0] & ~bus_request[1]; -always @(posedge clk) begin - if(prefetch_enable) - prefetch_address <= wbA_adr_i[19:2] + 2; - else - prefetch_address <= wbA_adr_i[19:2] + 1; -end - -wire [1:0] bus_selected; - -assign bus_selected[0] = bus_request[0]; -assign bus_selected[1] = bus_request[1] & ~bus_request[0]; - -assign pipeline_in[18:1] = ({18{bus_selected[0]}} & wbA_adr_i[19:2]) - | ({18{bus_selected[1]}} & wbB_adr_i[19:2]) - | ({18{prefetch_enable}} & prefetch_address); -assign pipeline_in[0] = (bus_selected[0] & wbA_we_i)|(bus_selected[1] & wbB_we_i); - -/* SRAM control */ - -assign sram_a = pipeline_in[18:1]; -assign sram_bw = ~(({4{bus_selected[0]}} & wbA_sel_i)|({4{bus_selected[1]}} & wbB_sel_i)); -assign sram_we = ~pipeline_in[0]; - -/* SRAM data */ - -wire [31:0] bus_wdata; - -assign wbA_ack_o = busA_active & hitA; -assign wbB_ack_o = busB_active & hitB; - -assign bus_wdata = ({32{hitA}} & wbA_dat_i)|({32{hitB}} & wbB_dat_i); -assign sram_d = pipeline_out[0] ? bus_wdata : 32'hzzzzzzzz; -assign wbA_dat_o = sram_d; -assign wbB_dat_o = sram_d; - -endmodule diff --git a/fpga/usrp2/opencores/zpu/core/zpu_config.vhd b/fpga/usrp2/opencores/zpu/core/zpu_config.vhd deleted file mode 100644 index f7743d602..000000000 --- a/fpga/usrp2/opencores/zpu/core/zpu_config.vhd +++ /dev/null @@ -1,20 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -package zpu_config is - -- generate trace output or not. - constant Generate_Trace : boolean := false; - constant wordPower : integer := 5; - -- during simulation, set this to '0' to get matching trace.txt - constant DontCareValue : std_logic := '0'; - -- Clock frequency in MHz. - constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"40"; - -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) - constant maxAddrBitIncIO : integer := 15; - - -- start byte address of stack. - -- point to top of RAM - 2*words - constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"3ff8"; - -end zpu_config; diff --git a/fpga/usrp2/opencores/zpu/core/zpu_core.vhd b/fpga/usrp2/opencores/zpu/core/zpu_core.vhd deleted file mode 100644 index 2450f14d3..000000000 --- a/fpga/usrp2/opencores/zpu/core/zpu_core.vhd +++ /dev/null @@ -1,948 +0,0 @@ - --- Company: ZPU4 generic memory interface CPU --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.STD_LOGIC_arith.ALL; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - - - - -entity zpu_core is - Port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - mem_req : out std_logic; - mem_we : out std_logic; - mem_ack : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic; - zpu_status : out std_logic_vector(63 downto 0)); -end zpu_core; - -architecture behave of zpu_core is - -type InsnType is -( -State_AddTop, -State_Dup, -State_DupStackB, -State_Pop, -State_Popdown, -State_Add, -State_Or, -State_And, -State_Store, -State_AddSP, -State_Shift, -State_Nop, -State_Im, -State_LoadSP, -State_StoreSP, -State_Emulate, -State_Load, -State_PushPC, -State_PushSP, -State_PopPC, -State_PopPCRel, -State_Not, -State_Flip, -State_PopSP, -State_Neqbranch, -State_Eq, -State_Loadb, -State_Mult, -State_Lessthan, -State_Lessthanorequal, -State_Ulessthanorequal, -State_Ulessthan, -State_Pushspadd, -State_Call, -State_Callpcrel, -State_Sub, -State_Break, -State_Storeb, -State_Interrupt, -State_InsnFetch -); - -type StateType is -( -State_Idle, -- using first state first on the list out of paranoia -State_Load2, -State_Popped, -State_LoadSP2, -State_LoadSP3, -State_AddSP2, -State_Fetch, -State_Execute, -State_Decode, -State_Decode2, -State_Resync, - -State_StoreSP2, -State_Resync2, -State_Resync3, -State_Loadb2, -State_Storeb2, -State_Mult2, -State_Mult3, -State_Mult5, -State_Mult6, -State_Mult4, -State_BinaryOpResult -); - - -signal pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal incSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal incIncSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal decSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal stackA : std_logic_vector(wordSize-1 downto 0); -signal binaryOpResult : std_logic_vector(wordSize-1 downto 0); -signal multResult2 : std_logic_vector(wordSize-1 downto 0); -signal multResult3 : std_logic_vector(wordSize-1 downto 0); -signal multResult : std_logic_vector(wordSize-1 downto 0); -signal multA : std_logic_vector(wordSize-1 downto 0); -signal multB : std_logic_vector(wordSize-1 downto 0); -signal stackB : std_logic_vector(wordSize-1 downto 0); -signal idim_flag : std_logic; -signal busy : std_logic; -signal mem_readEnable : std_logic; -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal mem_delayReadEnable : std_logic; -signal mem_busy : std_logic; -signal decodeWord : std_logic_vector(wordSize-1 downto 0); - - -signal state : StateType; -signal insn : InsnType; -type InsnArray is array(0 to wordBytes-1) of InsnType; -signal decodedOpcode : InsnArray; - -type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); - -signal opcode : OpcodeArray; - - - - -signal begin_inst : std_logic; -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - -signal out_mem_req : std_logic; - -signal inInterrupt : std_logic; - --- state machine. - -begin - - zpu_status(maxAddrBitIncIO downto 0) <= trace_pc; - zpu_status(31) <= '1'; - zpu_status(39 downto 32) <= trace_opcode; - zpu_status(40) <= '1' when (state = State_Idle) else '0'; - zpu_status(62) <= '1'; - - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - - -- the memory subsystem will tell us one cycle later whether or - -- not it is busy - out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; - out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); - mem_req <= out_mem_req; - - incSp <= sp + 1; - incIncSp <= sp + 2; - decSp <= sp - 1; - - mem_busy <= out_mem_req and not mem_ack; -- '1' when the memory is busy - - opcodeControl: - process(clk, areset) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - variable spOffset : std_logic_vector(4 downto 0); - variable tSpOffset : std_logic_vector(4 downto 0); - variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0); - variable tNextState : InsnType; - variable tDecodedOpcode : InsnArray; - variable tMultResult : std_logic_vector(wordSize*2-1 downto 0); - begin - if areset = '1' then - state <= State_Idle; - break <= '0'; - sp <= spStart(maxAddrBitIncIO downto minAddrBit); - - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - mem_we <= '0'; - multA <= (others => '0'); - multB <= (others => '0'); - mem_writeMask <= (others => '1'); - out_mem_req <= '0'; - mem_addr <= (others => DontCareValue); - mem_write <= (others => DontCareValue); - inInterrupt <= '0'; - elsif (clk'event and clk = '1') then - -- we must multiply unconditionally to get pipelined multiplication - tMultResult := multA * multB; - multResult3 <= multResult2; - multResult2 <= multResult; - multResult <= tMultResult(wordSize-1 downto 0); - - - spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4); - spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0); - nextPC := pc + 1; - - -- prepare trace snapshot - trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0))); - trace_pc <= pc; - trace_sp <= sp; - trace_topOfStack <= stackA; - trace_topOfStackB <= stackB; - begin_inst <= '0'; - - -- we terminate the requeset as soon as we get acknowledge - if mem_ack = '1' then - out_mem_req <= '0'; - mem_we <= '0'; - end if; - - if interrupt='0' then - inInterrupt <= '0'; -- no longer in an interrupt - end if; - - case state is - when State_Idle => - if enable='1' then - state <= State_Resync; - end if; - -- Initial state of ZPU, fetch top of stack + first instruction - when State_Resync => - if mem_busy='0' then - mem_addr <= sp; - out_mem_req <= '1'; - state <= State_Resync2; - end if; - when State_Resync2 => - if mem_busy='0' then - stackA <= mem_read; - mem_addr <= incSp; - out_mem_req <= '1'; - state <= State_Resync3; - end if; - when State_Resync3 => - if mem_busy='0' then - stackB <= mem_read; - mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); - out_mem_req <= '1'; - state <= State_Decode; - end if; - when State_Decode => - if mem_busy='0' then - decodeWord <= mem_read; - state <= State_Decode2; - end if; - when State_Decode2 => - -- decode 4 instructions in parallel - for i in 0 to wordBytes-1 loop - tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); - - tSpOffset(4):=not tOpcode(4); - tSpOffset(3 downto 0):=tOpcode(3 downto 0); - - opcode(i) <= tOpcode; - if (tOpcode(7 downto 7)=OpCode_Im) then - tNextState:=State_Im; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - if tSpOffset = 0 then - tNextState := State_Pop; - elsif tSpOffset=1 then - tNextState := State_PopDown; - else - tNextState :=State_StoreSP; - end if; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - if tSpOffset = 0 then - tNextState :=State_Dup; - elsif tSpOffset = 1 then - tNextState :=State_DupStackB; - else - tNextState :=State_LoadSP; - end if; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - tNextState :=State_Emulate; - if tOpcode(5 downto 0)=OpCode_Neqbranch then - tNextState :=State_Neqbranch; - elsif tOpcode(5 downto 0)=OpCode_Eq then - tNextState :=State_Eq; - elsif tOpcode(5 downto 0)=OpCode_Lessthan then - tNextState :=State_Lessthan; - elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then - --tNextState :=State_Lessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Ulessthan then - tNextState :=State_Ulessthan; - elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then - --tNextState :=State_Ulessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Loadb then - tNextState :=State_Loadb; - elsif tOpcode(5 downto 0)=OpCode_Mult then - tNextState :=State_Mult; - elsif tOpcode(5 downto 0)=OpCode_Storeb then - tNextState :=State_Storeb; - elsif tOpcode(5 downto 0)=OpCode_Pushspadd then - tNextState :=State_Pushspadd; - elsif tOpcode(5 downto 0)=OpCode_Callpcrel then - tNextState :=State_Callpcrel; - elsif tOpcode(5 downto 0)=OpCode_Call then - --tNextState :=State_Call; - elsif tOpcode(5 downto 0)=OpCode_Sub then - tNextState :=State_Sub; - elsif tOpcode(5 downto 0)=OpCode_PopPCRel then - --tNextState :=State_PopPCRel; - end if; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - if tSpOffset = 0 then - tNextState := State_Shift; - elsif tSpOffset = 1 then - tNextState := State_AddTop; - else - tNextState :=State_AddSP; - end if; - else - case tOpcode(3 downto 0) is - when OpCode_Nop => - tNextState :=State_Nop; - when OpCode_PushSP => - tNextState :=State_PushSP; - when OpCode_PopPC => - tNextState :=State_PopPC; - when OpCode_Add => - tNextState :=State_Add; - when OpCode_Or => - tNextState :=State_Or; - when OpCode_And => - tNextState :=State_And; - when OpCode_Load => - tNextState :=State_Load; - when OpCode_Not => - tNextState :=State_Not; - when OpCode_Flip => - tNextState :=State_Flip; - when OpCode_Store => - tNextState :=State_Store; - when OpCode_PopSP => - tNextState :=State_PopSP; - when others => - tNextState := State_Break; - - end case; - end if; - tDecodedOpcode(i) := tNextState; - - end loop; - - insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0))); - - -- once we wrap, we need to fetch - tDecodedOpcode(0) := State_InsnFetch; - - decodedOpcode <= tDecodedOpcode; - state <= State_Execute; - - - - -- Each instruction must: - -- - -- 1. set idim_flag - -- 2. increase pc if applicable - -- 3. set next state if appliable - -- 4. do it's operation - - when State_Execute => - insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0))); - - case insn is - when State_InsnFetch => - state <= State_Fetch; - when State_Im => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '1'; - pc <= pc + 1; - - if idim_flag='1' then - stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); - stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); - else - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - stackB <= stackA; - sp <= decSp; - for i in wordSize-1 downto 7 loop - stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6); - end loop; - stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); - end if; - else - insn <= insn; - end if; - when State_StoreSP => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_StoreSP2; - - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= sp+spOffset; - mem_write <= stackA; - stackA <= stackB; - sp <= incSp; - else - insn <= insn; - end if; - - - when State_LoadSP => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_LoadSP2; - - sp <= decSp; - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - else - insn <= insn; - end if; - when State_Emulate => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - sp <= decSp; - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - stackB <= stackA; - - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0); - state <= State_Fetch; - else - insn <= insn; - end if; - when State_Callpcrel => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - - pc <= pc + stackA(maxAddrBitIncIO downto 0); - state <= State_Fetch; - else - insn <= insn; - end if; - when State_Call => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - pc <= stackA(maxAddrBitIncIO downto 0); - state <= State_Fetch; - else - insn <= insn; - end if; - when State_AddSP => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_AddSP2; - - out_mem_req <= '1'; - mem_addr <= sp+spOffset; - else - insn <= insn; - end if; - when State_PushSP => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackA <= (others => '0'); - stackA(maxAddrBitIncIO downto minAddrBit) <= sp; - stackB <= stackA; - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - else - insn <= insn; - end if; - when State_PopPC => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= stackA(maxAddrBitIncIO downto 0); - sp <= incSp; - - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - state <= State_Resync; - else - insn <= insn; - end if; - when State_PopPCRel => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= stackA(maxAddrBitIncIO downto 0) + pc; - sp <= incSp; - - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - state <= State_Resync; - else - insn <= insn; - end if; - when State_Add => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= stackA + stackB; - - out_mem_req <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - else - insn <= insn; - end if; - when State_Sub => - begin_inst <= '1'; - idim_flag <= '0'; - binaryOpResult <= stackB - stackA; - state <= State_BinaryOpResult; - when State_Pop => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - mem_addr <= incIncSp; - out_mem_req <= '1'; - sp <= incSp; - stackA <= stackB; - state <= State_Popped; - else - insn <= insn; - end if; - when State_PopDown => - if mem_busy='0' then - -- PopDown leaves top of stack unchanged - begin_inst <= '1'; - idim_flag <= '0'; - mem_addr <= incIncSp; - out_mem_req <= '1'; - sp <= incSp; - state <= State_Popped; - else - insn <= insn; - end if; - when State_Or => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= stackA or stackB; - out_mem_req <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - else - insn <= insn; - end if; - when State_And => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - stackA <= stackA and stackB; - out_mem_req <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - else - insn <= insn; - end if; - when State_Eq => - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA=stackB) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - when State_Ulessthan => - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA<=stackB) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - when State_Lessthan => - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (signed(stackA) - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (signed(stackA)<=signed(stackB)) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - when State_Load => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Load2; - - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - out_mem_req <= '1'; - else - insn <= insn; - end if; - - when State_Dup => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackB <= stackA; - mem_write <= stackB; - mem_addr <= incSp; - out_mem_req <= '1'; - mem_we <= '1'; - else - insn <= insn; - end if; - when State_DupStackB => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackA <= stackB; - stackB <= stackA; - mem_write <= stackB; - mem_addr <= incSp; - out_mem_req <= '1'; - mem_we <= '1'; - else - insn <= insn; - end if; - when State_Store => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - mem_write <= stackB; - out_mem_req <= '1'; - mem_we <= '1'; - sp <= incIncSp; - state <= State_Resync; - else - insn <= insn; - end if; - when State_PopSP => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - mem_write <= stackB; - mem_addr <= incSp; - out_mem_req <= '1'; - mem_we <= '1'; - sp <= stackA(maxAddrBitIncIO downto minAddrBit); - state <= State_Resync; - else - insn <= insn; - end if; - when State_Nop => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - when State_Not => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= not stackA; - when State_Flip => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - for i in 0 to wordSize-1 loop - stackA(i) <= stackA(wordSize-1-i); - end loop; - when State_AddTop => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= stackA + stackB; - when State_Shift => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); - stackA(0) <= '0'; - when State_Pushspadd => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= (others => '0'); - stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; - when State_Neqbranch => - -- branches are almost always taken as they form loops - begin_inst <= '1'; - idim_flag <= '0'; - sp <= incIncSp; - if (stackB/=0) then - pc <= stackA(maxAddrBitIncIO downto 0) + pc; - else - pc <= pc + 1; - end if; - -- need to fetch stack again. - state <= State_Resync; - when State_Mult => - begin_inst <= '1'; - idim_flag <= '0'; - - multA <= stackA; - multB <= stackB; - state <= State_Mult2; - when State_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - - when State_Loadb => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Loadb2; - - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - out_mem_req <= '1'; - else - insn <= insn; - end if; - when State_Storeb => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Storeb2; - - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - out_mem_req <= '1'; - else - insn <= insn; - end if; - - when others => --- sp <= (others => DontCareValue); - report "Illegal instruction" severity failure; - break <= '1'; - end case; - - - when State_StoreSP2 => - if mem_busy='0' then - mem_addr <= incSp; - out_mem_req <= '1'; - state <= State_Popped; - end if; - when State_LoadSP2 => - if mem_busy='0' then - state <= State_LoadSP3; - out_mem_req <= '1'; - mem_addr <= sp+spOffset+1; - end if; - when State_LoadSP3 => - if mem_busy='0' then - pc <= pc + 1; - state <= State_Execute; - stackB <= stackA; - stackA <= mem_read; - end if; - when State_AddSP2 => - if mem_busy='0' then - pc <= pc + 1; - state <= State_Execute; - stackA <= stackA + mem_read; - end if; - when State_Load2 => - if mem_busy='0' then - stackA <= mem_read; - pc <= pc + 1; - state <= State_Execute; - end if; - when State_Loadb2 => - if mem_busy='0' then - stackA <= (others => '0'); - stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8); - pc <= pc + 1; - state <= State_Execute; - end if; - when State_Storeb2 => - if mem_busy='0' then - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - mem_write <= mem_read; - mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ; - out_mem_req <= '1'; - mem_we <= '1'; - pc <= pc + 1; - sp <= incIncSp; - state <= State_Resync; - end if; - when State_Fetch => - if mem_busy='0' then - if interrupt='1' and inInterrupt='0' and idim_flag='0' then - -- We got an interrupt - inInterrupt <= '1'; - - sp <= decSp; - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc; - stackB <= stackA; - - pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address - - report "ZPU jumped to interrupt!" severity note; - else - mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); - out_mem_req <= '1'; - state <= State_Decode; - end if; - end if; - when State_Mult2 => - state <= State_Mult3; - when State_Mult3 => - state <= State_Mult4; - when State_Mult4 => - state <= State_Mult5; - when State_Mult5 => - stackA <= multResult3; - state <= State_Mult6; - when State_Mult6 => - if mem_busy='0' then - out_mem_req <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - end if; - when State_BinaryOpResult => - if mem_busy='0' then - -- NB!!!! we know that the memory isn't busy at this point!!!! - out_mem_req <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - stackA <= binaryOpResult; - state <= State_Popped; - end if; - when State_Popped => - if mem_busy='0' then - pc <= pc + 1; - stackB <= mem_read; - state <= State_Execute; - end if; - when others => --- sp <= (others => DontCareValue); - report "Illegal state" severity failure; - break <= '1'; - end case; - end if; - end process; - - - -end behave; diff --git a/fpga/usrp2/opencores/zpu/core/zpupkg.vhd b/fpga/usrp2/opencores/zpu/core/zpupkg.vhd deleted file mode 100644 index 1a01563b8..000000000 --- a/fpga/usrp2/opencores/zpu/core/zpupkg.vhd +++ /dev/null @@ -1,168 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_ARITH.all; - -library work; -use work.zpu_config.all; - -package zpupkg is - - -- This bit is set for read/writes to IO - -- FIX!!! eventually this should be set to wordSize-1 so as to - -- to make the address of IO independent of amount of memory - -- reserved for CPU. Requires trivial tweaks in toolchain/runtime - -- libraries. - - constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes - constant maxAddrBit : integer := maxAddrBitIncIO-1; - constant ioBit : integer := maxAddrBit+1; - constant wordSize : integer := 2**wordPower; - constant wordBytes : integer := wordSize/8; - constant minAddrBit : integer := byteBits; - -- configurable internal stack size. Probably going to be 16 after toolchain is done - constant stack_bits : integer := 5; - constant stack_size : integer := 2**stack_bits; - - component dualport_ram is - port (clk : in std_logic; - memAWriteEnable : in std_logic; - memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); - memAWrite : in std_logic_vector(wordSize-1 downto 0); - memARead : out std_logic_vector(wordSize-1 downto 0); - memBWriteEnable : in std_logic; - memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); - memBWrite : in std_logic_vector(wordSize-1 downto 0); - memBRead : out std_logic_vector(wordSize-1 downto 0)); - end component; - - component dram is - port (clk : in std_logic; - areset : in std_logic; - mem_writeEnable : in std_logic; - mem_readEnable : in std_logic; - mem_addr : in std_logic_vector(maxAddrBit downto 0); - mem_write : in std_logic_vector(wordSize-1 downto 0); - mem_read : out std_logic_vector(wordSize-1 downto 0); - mem_busy : out std_logic; - mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); - end component; - - - component trace is - port( - clk : in std_logic; - begin_inst : in std_logic; - pc : in std_logic_vector(maxAddrBitIncIO downto 0); - opcode : in std_logic_vector(7 downto 0); - sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit); - memA : in std_logic_vector(wordSize-1 downto 0); - memB : in std_logic_vector(wordSize-1 downto 0); - busy : in std_logic; - intSp : in std_logic_vector(stack_bits-1 downto 0) - ); - end component; - - component zpu_core is - port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - mem_req : out std_logic; - mem_we : out std_logic; - mem_ack : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic; - zpu_status : out std_logic_vector(63 downto 0)); - end component; - - - - component timer is - port( - clk : in std_logic; - areset : in std_logic; - sample : in std_logic; - reset : in std_logic; - counter : out std_logic_vector(63 downto 0)); - end component; - - component zpuio is - port ( areset : in std_logic; - cpu_clk : in std_logic; - clk_status : in std_logic_vector(2 downto 0); - cpu_din : in std_logic_vector(15 downto 0); - cpu_a : in std_logic_vector(20 downto 0); - cpu_we : in std_logic_vector(1 downto 0); - cpu_re : in std_logic; - cpu_dout : inout std_logic_vector(15 downto 0)); - end component; - - - - - -- opcode decode constants - constant OpCode_Im : std_logic_vector(7 downto 7) := "1"; - constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010"; - constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011"; - constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001"; - constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001"; - constant OpCode_Short : std_logic_vector(7 downto 4) := "0000"; - - constant OpCode_Break : std_logic_vector(3 downto 0) := "0000"; - constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001"; - constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010"; - constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011"; - - constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100"; - constant OpCode_Add : std_logic_vector(3 downto 0) := "0101"; - constant OpCode_And : std_logic_vector(3 downto 0) := "0110"; - constant OpCode_Or : std_logic_vector(3 downto 0) := "0111"; - - constant OpCode_Load : std_logic_vector(3 downto 0) := "1000"; - constant OpCode_Not : std_logic_vector(3 downto 0) := "1001"; - constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010"; - constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011"; - - constant OpCode_Store : std_logic_vector(3 downto 0) := "1100"; - constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101"; - constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110"; - constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111"; - - constant OpCode_Lessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6); - constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6); - constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6); - constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6); - - constant OpCode_Swap : std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6); - constant OpCode_Mult : std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6); - - constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6); - constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6); - constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6); - constant OpCode_Call : std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6); - - constant OpCode_Eq : std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6); - constant OpCode_Neq : std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6); - - constant OpCode_Sub : std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6); - constant OpCode_Loadb : std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6); - constant OpCode_Storeb : std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6); - - constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6); - constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6); - constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6); - - constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6); - constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6); - constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6); - - - - constant OpCode_Size : integer := 8; - - - -end zpupkg; diff --git a/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd b/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd deleted file mode 100644 index 375c9ac7e..000000000 --- a/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd +++ /dev/null @@ -1,86 +0,0 @@ --- ZPU --- --- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com --- --- The FreeBSD license --- --- Redistribution and use in source and binary forms, with or without --- modification, are permitted provided that the following conditions --- are met: --- --- 1. Redistributions of source code must retain the above copyright --- notice, this list of conditions and the following disclaimer. --- 2. Redistributions in binary form must reproduce the above --- copyright notice, this list of conditions and the following --- disclaimer in the documentation and/or other materials --- provided with the distribution. --- --- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY --- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE --- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, --- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS --- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) --- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, --- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF --- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --- --- The views and conclusions contained in the software and documentation --- are those of the authors and should not be interpreted as representing --- official policies, either expressed or implied, of the ZPU Project. - -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -package wishbone_pkg is - - type wishbone_bus_in is record - adr : std_logic_vector(15 downto 0); - sel : std_logic_vector(3 downto 0); - we : std_logic; - dat : std_logic_vector(31 downto 0); -- Note! Data written with 'we' - cyc : std_logic; - stb : std_logic; - end record; - - type wishbone_bus_out is record - dat : std_logic_vector(31 downto 0); - ack : std_logic; - end record; - - type wishbone_bus is record - insig : wishbone_bus_in; - outsig : wishbone_bus_out; - end record; - - component atomic32_access is - port ( cpu_clk : in std_logic; - areset : in std_logic; - - -- Wishbone from CPU interface - wb_16_i : in wishbone_bus_in; - wb_16_o : out wishbone_bus_out; - -- Wishbone to FPGA registers and ethernet core - wb_32_i : in wishbone_bus_out; - wb_32_o : out wishbone_bus_in); - end component; - - component eth_access_corr is - port ( cpu_clk : in std_logic; - areset : in std_logic; - - -- Wishbone from Wishbone MUX - eth_raw_o : out wishbone_bus_out; - eth_raw_i : in wishbone_bus_in; - - -- Wishbone ethernet core - eth_slave_i : in wishbone_bus_out; - eth_slave_o : out wishbone_bus_in); - end component; - - -end wishbone_pkg; diff --git a/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd b/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd deleted file mode 100644 index 294651fe2..000000000 --- a/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- ZPU --- --- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com --- --- The FreeBSD license --- --- Redistribution and use in source and binary forms, with or without --- modification, are permitted provided that the following conditions --- are met: --- --- 1. Redistributions of source code must retain the above copyright --- notice, this list of conditions and the following disclaimer. --- 2. Redistributions in binary form must reproduce the above --- copyright notice, this list of conditions and the following --- disclaimer in the documentation and/or other materials --- provided with the distribution. --- --- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY --- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE --- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, --- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS --- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) --- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, --- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF --- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --- --- The views and conclusions contained in the software and documentation --- are those of the authors and should not be interpreted as representing --- official policies, either expressed or implied, of the ZPU Project. - -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.all; - -library work; -use work.zpu_top_pkg.all; -use work.wishbone_pkg.all; -use work.zpupkg.all; -use work.zpu_config.all; - -entity zpu_system is - generic( - simulate : boolean := false); - port ( areset : in std_logic; - cpu_clk : in std_logic; - - -- ZPU Control signals - enable : in std_logic; - interrupt : in std_logic; - - zpu_status : out std_logic_vector(63 downto 0); - - -- wishbone interfaces - zpu_wb_i : in wishbone_bus_out; - zpu_wb_o : out wishbone_bus_in); -end zpu_system; - -architecture behave of zpu_system is - -signal mem_req : std_logic; -signal mem_we : std_logic; -signal mem_ack : std_logic; -signal mem_read : std_logic_vector(wordSize-1 downto 0); -signal mem_write : std_logic_vector(wordSize-1 downto 0); -signal out_mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); -signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0); - - -begin - - my_zpu_core: - zpu_core port map ( - clk => cpu_clk, - areset => areset, - enable => enable, - mem_req => mem_req, - mem_we => mem_we, - mem_ack => mem_ack, - mem_read => mem_read, - mem_write => mem_write, - out_mem_addr => out_mem_addr, - mem_writeMask => mem_writeMask, - interrupt => interrupt, - zpu_status => zpu_status, - break => open); - - my_zpu_wb_bridge: - zpu_wb_bridge port map ( - clk => cpu_clk, - areset => areset, - mem_req => mem_req, - mem_we => mem_we, - mem_ack => mem_ack, - mem_read => mem_read, - mem_write => mem_write, - out_mem_addr => out_mem_addr, - mem_writeMask => mem_writeMask, - zpu_wb_i => zpu_wb_i, - zpu_wb_o => zpu_wb_o); - -end behave; diff --git a/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd b/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd deleted file mode 100644 index 104ee10b8..000000000 --- a/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd +++ /dev/null @@ -1,83 +0,0 @@ --- ZPU --- --- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com --- --- The FreeBSD license --- --- Redistribution and use in source and binary forms, with or without --- modification, are permitted provided that the following conditions --- are met: --- --- 1. Redistributions of source code must retain the above copyright --- notice, this list of conditions and the following disclaimer. --- 2. Redistributions in binary form must reproduce the above --- copyright notice, this list of conditions and the following --- disclaimer in the documentation and/or other materials --- provided with the distribution. --- --- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY --- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE --- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, --- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS --- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) --- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, --- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF --- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --- --- The views and conclusions contained in the software and documentation --- are those of the authors and should not be interpreted as representing --- official policies, either expressed or implied, of the ZPU Project. - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.zpu_top_pkg.all; -use work.wishbone_pkg.all; -use work.zpupkg.all; -use work.zpu_config.all; - -entity zpu_wb_bridge is - port ( -- Native ZPU interface - clk : in std_logic; - areset : in std_logic; - - mem_req : in std_logic; - mem_we : in std_logic; - mem_ack : out std_logic; - mem_read : out std_logic_vector(wordSize-1 downto 0); - mem_write : in std_logic_vector(wordSize-1 downto 0); - out_mem_addr : in std_logic_vector(maxAddrBitIncIO downto 0); - mem_writeMask : in std_logic_vector(wordBytes-1 downto 0); - - -- Wishbone from ZPU - zpu_wb_i : in wishbone_bus_out; - zpu_wb_o : out wishbone_bus_in); - -end zpu_wb_bridge; - -architecture behave of zpu_wb_bridge is - -begin - - mem_read <= zpu_wb_i.dat; - mem_ack <= zpu_wb_i.ack; - - zpu_wb_o.adr <= out_mem_addr; - zpu_wb_o.dat <= mem_write; - zpu_wb_o.sel <= mem_writeMask; - zpu_wb_o.stb <= mem_req; - zpu_wb_o.cyc <= mem_req; - zpu_wb_o.we <= mem_we; - -end behave; - - - - - diff --git a/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd b/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd deleted file mode 100644 index 23ff48c39..000000000 --- a/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd +++ /dev/null @@ -1,46 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.zpupkg.all; -use work.zpu_config.all; -use work.wishbone_pkg.all; - -package zpu_top_pkg is - component zpu_wb_bridge is - port ( -- Native ZPU interface - clk : in std_logic; - areset : in std_logic; - - mem_req : in std_logic; - mem_we : in std_logic; - mem_ack : out std_logic; - mem_read : out std_logic_vector(wordSize-1 downto 0); - mem_write : in std_logic_vector(wordSize-1 downto 0); - out_mem_addr : in std_logic_vector(maxAddrBitIncIO downto 0); - mem_writeMask : in std_logic_vector(wordBytes-1 downto 0); - - -- Wishbone from ZPU - zpu_wb_i : in wishbone_bus_out; - zpu_wb_o : out wishbone_bus_in); - end component; - - component zpu_system is - generic( - simulate : boolean := false); - port ( areset : in std_logic; - cpu_clk : in std_logic; - - -- ZPU Control signals - enable : in std_logic; - interrupt : in std_logic; - - zpu_status : out std_logic_vector(63 downto 0); - - -- wishbone interfaces - zpu_wb_i : in wishbone_bus_out; - zpu_wb_o : out wishbone_bus_in); - end component; - -end zpu_top_pkg; diff --git a/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd b/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd deleted file mode 100644 index 48e5ee31d..000000000 --- a/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd +++ /dev/null @@ -1,74 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.zpu_top_pkg.all; -use work.wishbone_pkg.all; -use work.zpupkg.all; -use work.zpu_config.all; - ------------------------------------------------------------------------- --- Top level ZPU + wishbone componenent to use in a verilog design: --- zpu_wb_top wraps around the zpu_system component. --- All IO lines are exposed as std_logic for verilog. ------------------------------------------------------------------------- -entity zpu_wb_top is - generic ( - dat_w: integer := 32; - adr_w: integer := 16; - sel_w: integer := 4 - ); - port ( - clk: in std_logic; - rst: in std_logic; - enb: in std_logic; - - -- wishbone interface - dat_i: in std_logic_vector(dat_w-1 downto 0); - ack_i: in std_logic; - adr_o: out std_logic_vector(adr_w-1 downto 0); - sel_o: out std_logic_vector(sel_w-1 downto 0); - we_o: out std_logic; - dat_o: out std_logic_vector(dat_w-1 downto 0); - cyc_o: out std_logic; - stb_o: out std_logic; - - -- misc zpu signals - interrupt: in std_logic; - zpu_status: out std_logic_vector(63 downto 0) - ); - -end zpu_wb_top; - -architecture syn of zpu_wb_top is - ---wishbone interface (records) -signal zpu_wb_i: wishbone_bus_out; -signal zpu_wb_o: wishbone_bus_in; - -begin - ---assign wishbone signals to records -zpu_wb_i.dat <= dat_i; -zpu_wb_i.ack <= ack_i; - -adr_o <= zpu_wb_o.adr; -sel_o <= zpu_wb_o.sel; -we_o <= zpu_wb_o.we; -dat_o <= zpu_wb_o.dat; -cyc_o <= zpu_wb_o.cyc; -stb_o <= zpu_wb_o.stb; - ---instantiate the zpu system -zpu_system0: zpu_system port map( - cpu_clk => clk, - areset => rst, - enable => enb, - interrupt => interrupt, - zpu_status => zpu_status, - zpu_wb_i => zpu_wb_i, - zpu_wb_o => zpu_wb_o -); - -end architecture syn; diff --git a/fpga/usrp2/sdr_lib/.gitignore b/fpga/usrp2/sdr_lib/.gitignore deleted file mode 100644 index 3c782d589..000000000 --- a/fpga/usrp2/sdr_lib/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -/a.out -/db -/*.vcd diff --git a/fpga/usrp2/sdr_lib/HB.sav b/fpga/usrp2/sdr_lib/HB.sav deleted file mode 100644 index c5087e8a6..000000000 --- a/fpga/usrp2/sdr_lib/HB.sav +++ /dev/null @@ -1,56 +0,0 @@ -[size] 1400 967 -[pos] -1 -1 -*-46.395245 2565000000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] hb_dec_tb. -@420 -hb_dec_tb.data_in[17:0] -@28 -hb_dec_tb.strobe_in -hb_dec_tb.strobe_out -hb_dec_tb.uut.write_even -@22 -hb_dec_tb.uut.addr_even[3:0] -@420 -hb_dec_tb.uut.data_even[17:0] -hb_dec_tb.uut.data_odd_a[17:0] -hb_dec_tb.uut.data_odd_b[17:0] -hb_dec_tb.uut.data_odd_c[17:0] -hb_dec_tb.uut.data_odd_d[17:0] -@28 -hb_dec_tb.uut.write_odd -@420 -hb_dec_tb.uut.prod1[35:0] -hb_dec_tb.uut.prod2[35:0] -@24 -hb_dec_tb.uut.phase[2:0] -@28 -hb_dec_tb.uut.stb_in -hb_dec_tb.uut.stb_out -@420 -hb_dec_tb.uut.sum2[17:0] -hb_dec_tb.uut.stb_out_pre[15:0] -@28 -hb_dec_tb.uut.do_acc -hb_dec_tb.uut.clear -@420 -hb_dec_tb.uut.sum1[17:0] -hb_dec_tb.uut.coeff1[17:0] -hb_dec_tb.uut.prod1[35:0] -hb_dec_tb.uut.prod2[35:0] -hb_dec_tb.uut.final_sum[17:0] -hb_dec_tb.uut.coeff2[17:0] -hb_dec_tb.uut.sum_of_prod[21:0] -hb_dec_tb.data_out[17:0] -@28 -hb_dec_tb.uut.do_acc -hb_dec_tb.uut.clear -@24 -hb_dec_tb.uut.addr_odd_a[3:0] -hb_dec_tb.uut.addr_odd_b[3:0] -hb_dec_tb.uut.addr_odd_c[3:0] -hb_dec_tb.uut.addr_odd_d[3:0] -@28 -hb_dec_tb.uut.write_odd -hb_dec_tb.uut.write_even -@22 -hb_dec_tb.uut.data_even[17:0] diff --git a/fpga/usrp2/sdr_lib/Makefile.srcs b/fpga/usrp2/sdr_lib/Makefile.srcs deleted file mode 100644 index e6c4c5343..000000000 --- a/fpga/usrp2/sdr_lib/Makefile.srcs +++ /dev/null @@ -1,45 +0,0 @@ -# -# Copyright 2010-2012 Ettus Research LLC -# - -################################################## -# FIFO Sources -################################################## -SDR_LIB_SRCS = $(abspath $(addprefix $(BASE_DIR)/../sdr_lib/, \ -acc.v \ -add2.v \ -add2_and_clip.v \ -add2_and_clip_reg.v \ -add2_and_round.v \ -add2_and_round_reg.v \ -add2_reg.v \ -cic_dec_shifter.v \ -cic_decim.v \ -cic_int_shifter.v \ -cic_interp.v \ -cic_strober.v \ -clip.v \ -clip_reg.v \ -cordic.v \ -cordic_z24.v \ -cordic_stage.v \ -ddc_chain.v \ -duc_chain.v \ -dspengine_16to8.v \ -dspengine_8to16.v \ -hb_dec.v \ -hb_interp.v \ -pipectrl.v \ -pipestage.v \ -round.v \ -round_reg.v \ -round_sd.v \ -rx_dcoffset.v \ -rx_frontend.v \ -sign_extend.v \ -small_hb_dec.v \ -small_hb_int.v \ -tx_frontend.v \ -dsp_tx_glue.v \ -dsp_rx_glue.v \ -)) diff --git a/fpga/usrp2/sdr_lib/SMALL_HB.sav b/fpga/usrp2/sdr_lib/SMALL_HB.sav deleted file mode 100644 index 96ba00636..000000000 --- a/fpga/usrp2/sdr_lib/SMALL_HB.sav +++ /dev/null @@ -1,40 +0,0 @@ -[size] 1400 967 -[pos] -1 -1 -*-11.608687 1834 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] small_hb_dec_tb. -[treeopen] small_hb_dec_tb.uut. -@28 -small_hb_dec_tb.uut.clk -small_hb_dec_tb.uut.phase -@10421 -small_hb_dec_tb.uut.data_in[17:0] -@420 -small_hb_dec_tb.uut.d1[17:0] -small_hb_dec_tb.uut.d2[17:0] -small_hb_dec_tb.uut.d3[17:0] -small_hb_dec_tb.uut.d4[17:0] -small_hb_dec_tb.uut.d5[17:0] -small_hb_dec_tb.uut.d6[17:0] -small_hb_dec_tb.uut.coeff[17:0] -small_hb_dec_tb.uut.sum[17:0] -small_hb_dec_tb.uut.prod[35:0] -small_hb_dec_tb.uut.accum_rnd[17:0] -@28 -small_hb_dec_tb.uut.stb_in -@420 -small_hb_dec_tb.uut.final_sum[17:0] -@28 -small_hb_dec_tb.uut.go -small_hb_dec_tb.uut.go_d1 -small_hb_dec_tb.uut.go_d2 -small_hb_dec_tb.uut.go_d3 -small_hb_dec_tb.uut.go_d4 -small_hb_dec_tb.uut.stb_out -@420 -small_hb_dec_tb.uut.data_out[17:0] -small_hb_dec_tb.uut.prod[35:0] -small_hb_dec_tb.uut.accum_rnd[17:0] -small_hb_dec_tb.uut.final_sum[17:0] -@10421 -small_hb_dec_tb.uut.round_acc.out[17:0] -small_hb_dec_tb.uut.data_out[17:0] diff --git a/fpga/usrp2/sdr_lib/acc.v b/fpga/usrp2/sdr_lib/acc.v deleted file mode 100644 index d5fc4b910..000000000 --- a/fpga/usrp2/sdr_lib/acc.v +++ /dev/null @@ -1,45 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module acc - #(parameter IWIDTH=16, OWIDTH=30) - (input clk, - input clear, - input acc, - input [IWIDTH-1:0] in, - output reg [OWIDTH-1:0] out); - - wire [OWIDTH-1:0] in_signext; - sign_extend #(.bits_in(IWIDTH),.bits_out(OWIDTH)) - acc_signext (.in(in),.out(in_signext)); - - // CLEAR & ~ACC --> clears the accumulator - // CLEAR & ACC --> loads the accumulator - // ~CLEAR & ACC --> accumulates - // ~CLEAR & ~ACC --> hold - - wire [OWIDTH-1:0] addend1 = clear ? 0 : out; - wire [OWIDTH-1:0] addend2 = ~acc ? 0 : in_signext; - wire [OWIDTH-1:0] sum_int = addend1 + addend2; - - always @(posedge clk) - out <= sum_int; - -endmodule // acc - - diff --git a/fpga/usrp2/sdr_lib/add2.v b/fpga/usrp2/sdr_lib/add2.v deleted file mode 100644 index dcca84fd3..000000000 --- a/fpga/usrp2/sdr_lib/add2.v +++ /dev/null @@ -1,28 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module add2 - #(parameter WIDTH=16) - (input [WIDTH-1:0] in1, - input [WIDTH-1:0] in2, - output [WIDTH-1:0] sum); - - wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2}; - assign sum = sum_int[WIDTH:1]; // Note -- will have some bias - -endmodule // add2 diff --git a/fpga/usrp2/sdr_lib/add2_and_clip.v b/fpga/usrp2/sdr_lib/add2_and_clip.v deleted file mode 100644 index 663f5d004..000000000 --- a/fpga/usrp2/sdr_lib/add2_and_clip.v +++ /dev/null @@ -1,12 +0,0 @@ - -module add2_and_clip - #(parameter WIDTH=16) - (input [WIDTH-1:0] in1, - input [WIDTH-1:0] in2, - output [WIDTH-1:0] sum); - - wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2}; - clip #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip - (.in(sum_int),.out(sum)); - -endmodule // add2_and_clip diff --git a/fpga/usrp2/sdr_lib/add2_and_clip_reg.v b/fpga/usrp2/sdr_lib/add2_and_clip_reg.v deleted file mode 100644 index 8073b3b54..000000000 --- a/fpga/usrp2/sdr_lib/add2_and_clip_reg.v +++ /dev/null @@ -1,25 +0,0 @@ - -module add2_and_clip_reg - #(parameter WIDTH=16) - (input clk, - input rst, - input [WIDTH-1:0] in1, - input [WIDTH-1:0] in2, - input strobe_in, - output reg [WIDTH-1:0] sum, - output reg strobe_out); - - wire [WIDTH-1:0] sum_int; - - add2_and_clip #(.WIDTH(WIDTH)) add2_and_clip (.in1(in1),.in2(in2),.sum(sum_int)); - - always @(posedge clk) - if(rst) - sum <= 0; - else if(strobe_in) - sum <= sum_int; - - always @(posedge clk) - strobe_out <= strobe_in; - -endmodule // add2_and_clip_reg diff --git a/fpga/usrp2/sdr_lib/add2_and_round.v b/fpga/usrp2/sdr_lib/add2_and_round.v deleted file mode 100644 index 7c347527c..000000000 --- a/fpga/usrp2/sdr_lib/add2_and_round.v +++ /dev/null @@ -1,28 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module add2_and_round - #(parameter WIDTH=16) - (input [WIDTH-1:0] in1, - input [WIDTH-1:0] in2, - output [WIDTH-1:0] sum); - - wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2}; - assign sum = sum_int[WIDTH:1] + (sum_int[WIDTH] & sum_int[0]); - -endmodule // add2_and_round diff --git a/fpga/usrp2/sdr_lib/add2_and_round_reg.v b/fpga/usrp2/sdr_lib/add2_and_round_reg.v deleted file mode 100644 index 5c783bda3..000000000 --- a/fpga/usrp2/sdr_lib/add2_and_round_reg.v +++ /dev/null @@ -1,33 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module add2_and_round_reg - #(parameter WIDTH=16) - (input clk, - input [WIDTH-1:0] in1, - input [WIDTH-1:0] in2, - output reg [WIDTH-1:0] sum); - - wire [WIDTH-1:0] sum_int; - - add2_and_round #(.WIDTH(WIDTH)) add2_n_rnd (.in1(in1),.in2(in2),.sum(sum_int)); - - always @(posedge clk) - sum <= sum_int; - -endmodule // add2_and_round_reg diff --git a/fpga/usrp2/sdr_lib/add2_reg.v b/fpga/usrp2/sdr_lib/add2_reg.v deleted file mode 100644 index 58d822a61..000000000 --- a/fpga/usrp2/sdr_lib/add2_reg.v +++ /dev/null @@ -1,34 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module add2_reg - #(parameter WIDTH=16) - (input clk, - input [WIDTH-1:0] in1, - input [WIDTH-1:0] in2, - output reg [WIDTH-1:0] sum); - - wire [WIDTH-1:0] sum_int; - - add2 #(.WIDTH(WIDTH)) add2 (.in1(in1),.in2(in2),.sum(sum_int)); - - always @(posedge clk) - sum <= sum_int; - -endmodule // add2_reg - diff --git a/fpga/usrp2/sdr_lib/cic_dec_shifter.v b/fpga/usrp2/sdr_lib/cic_dec_shifter.v deleted file mode 100644 index aa5ac895b..000000000 --- a/fpga/usrp2/sdr_lib/cic_dec_shifter.v +++ /dev/null @@ -1,106 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - - -// NOTE This only works for N=4, max decim rate of 128 -// NOTE signal "rate" is EQUAL TO the actual rate, no more -1 BS - -module cic_dec_shifter(rate,signal_in,signal_out); - parameter bw = 16; - parameter maxbitgain = 28; - - input [7:0] rate; - input wire [bw+maxbitgain-1:0] signal_in; - output reg [bw-1:0] signal_out; - - function [4:0] bitgain; - input [7:0] rate; - case(rate) - // Exact Cases -- N*log2(rate) - 8'd1 : bitgain = 0; - 8'd2 : bitgain = 4; - 8'd4 : bitgain = 8; - 8'd8 : bitgain = 12; - 8'd16 : bitgain = 16; - 8'd32 : bitgain = 20; - 8'd64 : bitgain = 24; - 8'd128 : bitgain = 28; - - // Nearest without overflow -- ceil(N*log2(rate)) - 8'd3 : bitgain = 7; - 8'd5 : bitgain = 10; - 8'd6 : bitgain = 11; - 8'd7 : bitgain = 12; - 8'd9 : bitgain = 13; - 8'd10,8'd11 : bitgain = 14; - 8'd12,8'd13 : bitgain = 15; - 8'd14,8'd15 : bitgain = 16; - 8'd17,8'd18,8'd19 : bitgain = 17; - 8'd20,8'd21,8'd22 : bitgain = 18; - 8'd23,8'd24,8'd25,8'd26 : bitgain = 19; - 8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20; - 8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21; - 8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22; - 8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23; - 8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24; - 8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25; - 8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26; - 8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27; - default : bitgain = 28; - endcase // case(rate) - endfunction // bitgain - - wire [4:0] shift = bitgain(rate); - - // We should be able to do this, but can't .... - // assign signal_out = signal_in[shift+bw-1:shift]; - - always @* - case(shift) - 5'd0 : signal_out = signal_in[0+bw-1:0]; - 5'd4 : signal_out = signal_in[4+bw-1:4]; - 5'd7 : signal_out = signal_in[7+bw-1:7]; - 5'd8 : signal_out = signal_in[8+bw-1:8]; - 5'd10 : signal_out = signal_in[10+bw-1:10]; - 5'd11 : signal_out = signal_in[11+bw-1:11]; - 5'd12 : signal_out = signal_in[12+bw-1:12]; - 5'd13 : signal_out = signal_in[13+bw-1:13]; - 5'd14 : signal_out = signal_in[14+bw-1:14]; - 5'd15 : signal_out = signal_in[15+bw-1:15]; - 5'd16 : signal_out = signal_in[16+bw-1:16]; - 5'd17 : signal_out = signal_in[17+bw-1:17]; - 5'd18 : signal_out = signal_in[18+bw-1:18]; - 5'd19 : signal_out = signal_in[19+bw-1:19]; - 5'd20 : signal_out = signal_in[20+bw-1:20]; - 5'd21 : signal_out = signal_in[21+bw-1:21]; - 5'd22 : signal_out = signal_in[22+bw-1:22]; - 5'd23 : signal_out = signal_in[23+bw-1:23]; - 5'd24 : signal_out = signal_in[24+bw-1:24]; - 5'd25 : signal_out = signal_in[25+bw-1:25]; - 5'd26 : signal_out = signal_in[26+bw-1:26]; - 5'd27 : signal_out = signal_in[27+bw-1:27]; - 5'd28 : signal_out = signal_in[28+bw-1:28]; - - default : signal_out = signal_in[28+bw-1:28]; - endcase // case(shift) - -endmodule // cic_dec_shifter - diff --git a/fpga/usrp2/sdr_lib/cic_decim.v b/fpga/usrp2/sdr_lib/cic_decim.v deleted file mode 100755 index e6b6e9590..000000000 --- a/fpga/usrp2/sdr_lib/cic_decim.v +++ /dev/null @@ -1,88 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - - -module cic_decim - #(parameter bw = 16, parameter N = 4, parameter log2_of_max_rate = 7) - (input clock, - input reset, - input enable, - input [7:0] rate, - input strobe_in, - input strobe_out, - input [bw-1:0] signal_in, - output reg [bw-1:0] signal_out); - - localparam maxbitgain = N * log2_of_max_rate; - - wire [bw+maxbitgain-1:0] signal_in_ext; - reg [bw+maxbitgain-1:0] integrator [0:N-1]; - reg [bw+maxbitgain-1:0] differentiator [0:N-1]; - reg [bw+maxbitgain-1:0] pipeline [0:N-1]; - reg [bw+maxbitgain-1:0] sampler; - - integer i; - - sign_extend #(bw,bw+maxbitgain) - ext_input (.in(signal_in),.out(signal_in_ext)); - - always @(posedge clock) - if(~enable) - for(i=0;i. -// - -//! The USRP digital down-conversion chain - -module ddc_chain - #( - parameter BASE = 0, - parameter DSPNO = 0, - parameter WIDTH = 24 - ) - (input clk, input rst, input clr, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user, - - // From RX frontend - input [WIDTH-1:0] rx_fe_i, - input [WIDTH-1:0] rx_fe_q, - - // To RX control - output [31:0] sample, - input run, - output strobe, - output [31:0] debug - ); - - localparam cwidth = 25; - localparam zwidth = 24; - - wire ddc_enb; - wire [31:0] phase_inc; - reg [31:0] phase; - - wire [17:0] scale_factor; - wire [cwidth-1:0] i_cordic, q_cordic; - wire [WIDTH-1:0] i_cordic_clip, q_cordic_clip; - wire [WIDTH-1:0] i_cic, q_cic; - wire [WIDTH-1:0] i_hb1, q_hb1; - wire [WIDTH-1:0] i_hb2, q_hb2; - - wire strobe_cic, strobe_hb1, strobe_hb2; - wire enable_hb1, enable_hb2; - wire [7:0] cic_decim_rate; - - reg [WIDTH-1:0] rx_fe_i_mux, rx_fe_q_mux; - wire realmode; - wire swap_iq; - - setting_reg #(.my_addr(BASE+0)) sr_0 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phase_inc),.changed()); - - setting_reg #(.my_addr(BASE+1), .width(18)) sr_1 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(scale_factor),.changed()); - - setting_reg #(.my_addr(BASE+2), .width(10)) sr_2 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed()); - - setting_reg #(.my_addr(BASE+3), .width(2)) sr_3 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({realmode,swap_iq}),.changed()); - - // MUX so we can do realmode signals on either input - - always @(posedge clk) - if(swap_iq) - begin - rx_fe_i_mux <= rx_fe_q; - rx_fe_q_mux <= realmode ? 0 : rx_fe_i; - end - else - begin - rx_fe_i_mux <= rx_fe_i; - rx_fe_q_mux <= realmode ? 0 : rx_fe_q; - end - - // NCO - always @(posedge clk) - if(rst) - phase <= 0; - else if(~ddc_enb) - phase <= 0; - else - phase <= phase + phase_inc; - - //sign extension of cordic input - wire [WIDTH-1:0] to_ddc_chain_i, to_ddc_chain_q; - wire [cwidth-1:0] to_cordic_i, to_cordic_q; - sign_extend #(.bits_in(WIDTH), .bits_out(cwidth)) sign_extend_cordic_i (.in(to_ddc_chain_i), .out(to_cordic_i)); - sign_extend #(.bits_in(WIDTH), .bits_out(cwidth)) sign_extend_cordic_q (.in(to_ddc_chain_q), .out(to_cordic_q)); - - // CORDIC 24-bit I/O - cordic_z24 #(.bitwidth(cwidth)) - cordic(.clock(clk), .reset(rst), .enable(ddc_enb), - .xi(to_cordic_i),. yi(to_cordic_q), .zi(phase[31:32-zwidth]), - .xo(i_cordic),.yo(q_cordic),.zo() ); - - clip_reg #(.bits_in(cwidth), .bits_out(WIDTH)) clip_i - (.clk(clk), .in(i_cordic), .strobe_in(1'b1), .out(i_cordic_clip)); - clip_reg #(.bits_in(cwidth), .bits_out(WIDTH)) clip_q - (.clk(clk), .in(q_cordic), .strobe_in(1'b1), .out(q_cordic_clip)); - - // CIC decimator 24 bit I/O - cic_strober cic_strober(.clock(clk),.reset(rst),.enable(ddc_enb),.rate(cic_decim_rate), - .strobe_fast(1),.strobe_slow(strobe_cic) ); - - cic_decim #(.bw(WIDTH)) - decim_i (.clock(clk),.reset(rst),.enable(ddc_enb), - .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic), - .signal_in(i_cordic_clip),.signal_out(i_cic)); - - cic_decim #(.bw(WIDTH)) - decim_q (.clock(clk),.reset(rst),.enable(ddc_enb), - .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic), - .signal_in(q_cordic_clip),.signal_out(q_cic)); - - // First (small) halfband 24 bit I/O - small_hb_dec #(.WIDTH(WIDTH)) small_hb_i - (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(ddc_enb), - .stb_in(strobe_cic),.data_in(i_cic),.stb_out(strobe_hb1),.data_out(i_hb1)); - - small_hb_dec #(.WIDTH(WIDTH)) small_hb_q - (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(ddc_enb), - .stb_in(strobe_cic),.data_in(q_cic),.stb_out(),.data_out(q_hb1)); - - // Second (large) halfband 24 bit I/O - wire [8:0] cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate}; - hb_dec #(.WIDTH(WIDTH)) hb_i - (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(ddc_enb),.cpi(cpi_hb), - .stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2)); - - hb_dec #(.WIDTH(WIDTH)) hb_q - (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(ddc_enb),.cpi(cpi_hb), - .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2)); - - //scalar operation (gain of 6 bits) - wire [35:0] prod_i, prod_q; - - MULT18X18S mult_i - (.P(prod_i), .A(i_hb2[WIDTH-1:WIDTH-18]), .B(scale_factor), .C(clk), .CE(strobe_hb2), .R(rst) ); - MULT18X18S mult_q - (.P(prod_q), .A(q_hb2[WIDTH-1:WIDTH-18]), .B(scale_factor), .C(clk), .CE(strobe_hb2), .R(rst) ); - - //pipeline for the multiplier (gain of 10 bits) - reg [WIDTH-1:0] prod_reg_i, prod_reg_q; - reg strobe_mult; - - always @(posedge clk) begin - strobe_mult <= strobe_hb2; - prod_reg_i <= prod_i[33:34-WIDTH]; - prod_reg_q <= prod_q[33:34-WIDTH]; - end - - // Round final answer to 16 bits - wire [31:0] ddc_chain_out; - wire ddc_chain_stb; - - round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(16)) round_i - (.clk(clk),.reset(rst), .in(prod_reg_i),.strobe_in(strobe_mult), .out(ddc_chain_out[31:16]), .strobe_out(ddc_chain_stb)); - - round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(16)) round_q - (.clk(clk),.reset(rst), .in(prod_reg_q),.strobe_in(strobe_mult), .out(ddc_chain_out[15:0]), .strobe_out()); - - dsp_rx_glue #(.DSPNO(DSPNO), .WIDTH(WIDTH)) custom( - .clock(clk), .reset(rst), .clear(clr), .enable(run), - .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), - .frontend_i(rx_fe_i_mux), .frontend_q(rx_fe_q_mux), - .ddc_in_i(to_ddc_chain_i), .ddc_in_q(to_ddc_chain_q), - .ddc_out_sample(ddc_chain_out), .ddc_out_strobe(ddc_chain_stb), .ddc_out_enable(ddc_enb), - .bb_sample(sample), .bb_strobe(strobe)); - - assign debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_hb1, strobe_hb2}; - -endmodule // ddc_chain diff --git a/fpga/usrp2/sdr_lib/dsp_core_rx_tb.v b/fpga/usrp2/sdr_lib/dsp_core_rx_tb.v deleted file mode 100644 index a221bed44..000000000 --- a/fpga/usrp2/sdr_lib/dsp_core_rx_tb.v +++ /dev/null @@ -1,73 +0,0 @@ - -`timescale 1ns/1ns -module ddc_chain_tb(); - - reg clk, rst; - - initial rst = 1; - initial #1000 rst = 0; - initial clk = 0; - always #5 clk = ~clk; - - initial $dumpfile("ddc_chain_tb.vcd"); - initial $dumpvars(0,ddc_chain_tb); - - reg signed [23:0] adc_in; - wire signed [15:0] adc_out_i, adc_out_q; - - always @(posedge clk) - begin - $display(adc_in); - $display(adc_out_i); - $display(adc_out_q); - end - - reg run; - reg set_stb; - reg [7:0] set_addr; - reg [31:0] set_data; - - ddc_chain #(.BASE(0)) ddc_chain - (.clk(clk),.rst(rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_i(adc_in), .adc_ovf_i(0), - .adc_q(0), .adc_ovf_q(0), - .sample({adc_out_i,adc_out_q}), - .run(run), .strobe(), .debug()); - - initial - begin - run <= 0; - @(negedge rst); - @(posedge clk); - set_addr <= 1; - set_data <= {16'd64,16'd64}; // set gains - set_stb <= 1; - @(posedge clk); - set_addr <= 2; - set_data <= {16'd0,8'd3,8'd1}; // set decim - set_stb <= 1; - @(posedge clk); - set_addr <= 0; - //set_data <= {32'h0000_0000}; - set_data <= {32'h01CA_C083}; // 700 kHz - set_stb <= 1; - @(posedge clk); - set_stb <= 0; - @(posedge clk); - run <= 1; - end - - always @(posedge clk) - //adc_in <= 24'd1000000; - adc_in <= 24'h80_0000; - - /* - always @(posedge clk) - if(rst) - adc_in <= 0; - else - adc_in <= adc_in + 4; - //adc_in <= (($random % 473) + 23)/4; -*/ -endmodule // ddc_chain_tb diff --git a/fpga/usrp2/sdr_lib/dsp_rx_glue.v b/fpga/usrp2/sdr_lib/dsp_rx_glue.v deleted file mode 100644 index 038a67a29..000000000 --- a/fpga/usrp2/sdr_lib/dsp_rx_glue.v +++ /dev/null @@ -1,98 +0,0 @@ -// -// Copyright 2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -//The following module effects the IO of the DDC chain. -//By default, this entire module is a simple pass-through. - -module dsp_rx_glue -#( - //the dsp unit number: 0, 1, 2... - parameter DSPNO = 0, - - //frontend bus width - parameter WIDTH = 24 -) -( - //control signals - input clock, input reset, input clear, input enable, - - //user settings bus, controlled through user setting regs API - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - //full rate inputs directly from the RX frontend - input [WIDTH-1:0] frontend_i, - input [WIDTH-1:0] frontend_q, - - //full rate outputs directly to the DDC chain - output [WIDTH-1:0] ddc_in_i, - output [WIDTH-1:0] ddc_in_q, - - //strobed samples {I16,Q16} from the RX DDC chain - input [31:0] ddc_out_sample, - input ddc_out_strobe, //high on valid sample - output ddc_out_enable, //enables DDC module - - //strobbed baseband samples {I16,Q16} from this module - output [31:0] bb_sample, - output bb_strobe, //high on valid sample - - //debug output (optional) - output [31:0] debug -); - - generate - if (DSPNO==0) begin - `ifndef RX_DSP0_MODULE - assign ddc_in_i = frontend_i; - assign ddc_in_q = frontend_q; - assign bb_sample = ddc_out_sample; - assign bb_strobe = ddc_out_strobe; - assign ddc_out_enable = enable; - `else - `RX_DSP0_MODULE #(.WIDTH(WIDTH)) rx_dsp0_custom - ( - .clock(clock), .reset(reset), .clear(clear), .enable(enable), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .frontend_i(frontend_i), .frontend_q(frontend_q), - .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q), - .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe), .ddc_out_enable(ddc_out_enable), - .bb_sample(bb_sample), .bb_strobe(bb_strobe) - ); - `endif - end - else begin - `ifndef RX_DSP1_MODULE - assign ddc_in_i = frontend_i; - assign ddc_in_q = frontend_q; - assign bb_sample = ddc_out_sample; - assign bb_strobe = ddc_out_strobe; - assign ddc_out_enable = enable; - `else - `RX_DSP1_MODULE #(.WIDTH(WIDTH)) rx_dsp1_custom - ( - .clock(clock), .reset(reset), .clear(clear), .enable(enable), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .frontend_i(frontend_i), .frontend_q(frontend_q), - .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q), - .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe), .ddc_out_enable(ddc_out_enable), - .bb_sample(bb_sample), .bb_strobe(bb_strobe) - ); - `endif - end - endgenerate - -endmodule //dsp_rx_glue diff --git a/fpga/usrp2/sdr_lib/dsp_tx_glue.v b/fpga/usrp2/sdr_lib/dsp_tx_glue.v deleted file mode 100644 index 46f6789ee..000000000 --- a/fpga/usrp2/sdr_lib/dsp_tx_glue.v +++ /dev/null @@ -1,98 +0,0 @@ -// -// Copyright 2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -//The following module effects the IO of the DUC chain. -//By default, this entire module is a simple pass-through. - -module dsp_tx_glue -#( - //the dsp unit number: 0, 1, 2... - parameter DSPNO = 0, - - //frontend bus width - parameter WIDTH = 24 -) -( - //control signals - input clock, input reset, input clear, input enable, - - //user settings bus, controlled through user setting regs API - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - //full rate outputs directly to the TX frontend - output [WIDTH-1:0] frontend_i, - output [WIDTH-1:0] frontend_q, - - //full rate outputs directly from the DUC chain - input [WIDTH-1:0] duc_out_i, - input [WIDTH-1:0] duc_out_q, - - //strobed samples {I16,Q16} to the TX DUC chain - output [31:0] duc_in_sample, - input duc_in_strobe, //this is a backpressure signal - output duc_in_enable, //enables DUC module - - //strobbed baseband samples {I16,Q16} to this module - input [31:0] bb_sample, - output bb_strobe, //this is a backpressure signal - - //debug output (optional) - output [31:0] debug -); - - generate - if (DSPNO==0) begin - `ifndef TX_DSP0_MODULE - assign frontend_i = duc_out_i; - assign frontend_q = duc_out_q; - assign duc_in_sample = bb_sample; - assign bb_strobe = duc_in_strobe; - assign duc_in_enable = enable; - `else - `TX_DSP0_MODULE #(.WIDTH(WIDTH)) tx_dsp0_custom - ( - .clock(clock), .reset(reset), .clear(clear), .enable(enable), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .frontend_i(frontend_i), .frontend_q(frontend_q), - .duc_out_i(duc_out_i), .duc_out_q(duc_out_q), - .duc_in_sample(duc_in_sample), .duc_in_strobe(duc_in_strobe), .duc_in_enable(duc_in_enable), - .bb_sample(bb_sample), .bb_strobe(bb_strobe) - ); - `endif - end - else begin - `ifndef TX_DSP1_MODULE - assign frontend_i = duc_out_i; - assign frontend_q = duc_out_q; - assign duc_in_sample = bb_sample; - assign bb_strobe = duc_in_strobe; - assign duc_in_enable = enable; - `else - `TX_DSP1_MODULE #(.WIDTH(WIDTH)) tx_dsp1_custom - ( - .clock(clock), .reset(reset), .clear(clear), .enable(enable), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .frontend_i(frontend_i), .frontend_q(frontend_q), - .duc_out_i(duc_out_i), .duc_out_q(duc_out_q), - .duc_in_sample(duc_in_sample), .duc_in_strobe(duc_in_strobe), .duc_in_enable(duc_in_enable), - .bb_sample(bb_sample), .bb_strobe(bb_strobe) - ); - `endif - end - endgenerate - -endmodule //dsp_tx_glue diff --git a/fpga/usrp2/sdr_lib/dspengine_16to8.v b/fpga/usrp2/sdr_lib/dspengine_16to8.v deleted file mode 100644 index 1d6746dd1..000000000 --- a/fpga/usrp2/sdr_lib/dspengine_16to8.v +++ /dev/null @@ -1,211 +0,0 @@ - -// Copyright 2011-2013 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module dspengine_16to8 - #(parameter BASE = 0, - parameter BUF_SIZE = 9) - (input clk, input reset, input clear, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - output access_we, - output access_stb, - input access_ok, - output access_done, - output access_skip_read, - output [BUF_SIZE-1:0] access_adr, - input [BUF_SIZE-1:0] access_len, - output [35:0] access_dat_o, - input [35:0] access_dat_i - ); - - wire convert; - setting_reg #(.my_addr(BASE),.width(1)) sr_16to8 - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(convert),.changed()); - - reg [2:0] dsp_state; - localparam DSP_IDLE = 0; - localparam DSP_PARSE_HEADER = 1; - localparam DSP_CONVERT = 2; - localparam DSP_CONVERT_DRAIN_PIPE = 3; - localparam DSP_READ_TRAILER = 4; - localparam DSP_WRITE_TRAILER = 5; - localparam DSP_WRITE_HEADER = 6; - localparam DSP_DONE = 7; - - // Parse VITA header - wire is_if_data = (access_dat_i[31:29] == 3'b000); - wire has_streamid = access_dat_i[28]; - wire has_classid = access_dat_i[27]; - wire has_trailer = access_dat_i[26]; - // 25:24 reserved, aka SOB/EOB - wire has_secs = |access_dat_i[23:22]; - wire has_tics = |access_dat_i[21:20]; - wire [3:0] hdr_length = 1 + has_streamid + has_classid + has_classid + has_secs + has_tics + has_tics; - - wire [35:0] prod_i, prod_q; - wire [15:0] scaled_i, scaled_q; - wire [7:0] i8, q8; - reg [7:0] i8_reg, q8_reg; - wire stb_read, stb_clip, val_read, val_clip; - wire stb_out, stb_reg; - reg even; - - reg [BUF_SIZE-1:0] read_adr, write_adr; - reg has_trailer_reg; - - wire last = (read_adr + 1) == (access_len - has_trailer_reg); - wire last_o, even_o; - - wire stb_write = stb_out & (even_o | last_o); - wire send_to_pipe = ~stb_write & (dsp_state == DSP_CONVERT); - reg [31:0] new_header, new_trailer, trailer_mask; - reg [15:0] length; - reg wait_for_trailer; - - always @(posedge clk) - if(reset | clear) - dsp_state <= DSP_IDLE; - else - case(dsp_state) - DSP_IDLE : - begin - read_adr <= 0; - write_adr <= 0; - even <= 0; - if(access_ok) - dsp_state <= DSP_PARSE_HEADER; - end - - DSP_PARSE_HEADER : - begin - has_trailer_reg <= has_trailer; - new_header[31:16] <= access_dat_i[31:16]; - new_header[15:0] <= access_len; - length <= access_len; - if(is_if_data & convert) - begin - read_adr <= hdr_length; - write_adr <= hdr_length; - dsp_state <= DSP_CONVERT; - end - else - dsp_state <= DSP_WRITE_HEADER; - end - - DSP_CONVERT: - begin - new_header[26] <= 1'b1; // all converted packets have a trailer - if(stb_write) - write_adr <= write_adr + 1; - else if(stb_read) // should always be 1 if we are here - begin - read_adr <= read_adr + 1; - even <= ~even; - if(last) - begin - dsp_state <= DSP_CONVERT_DRAIN_PIPE; - if(~even) - trailer_mask <= 32'h00400400; - else - trailer_mask <= 32'h00400000; - end - end - end - - DSP_CONVERT_DRAIN_PIPE : - if(stb_write) - begin - write_adr <= write_adr + 1; - if(last_o) - if(has_trailer_reg) - begin - dsp_state <= DSP_READ_TRAILER; - wait_for_trailer <= 0; - end - else - begin - dsp_state <= DSP_WRITE_TRAILER; - new_trailer <= trailer_mask; - end - end - - DSP_READ_TRAILER : - begin - wait_for_trailer <= 1; - if(wait_for_trailer) - dsp_state <= DSP_WRITE_TRAILER; - new_trailer <= access_dat_i[31:0] | trailer_mask; - end - - DSP_WRITE_TRAILER : - begin - dsp_state <= DSP_WRITE_HEADER; - write_adr <= 0; - new_header[15:0] <= write_adr + 1; - end - - DSP_WRITE_HEADER : - dsp_state <= DSP_DONE; - - DSP_DONE : - begin - read_adr <= 0; - write_adr <= 0; - dsp_state <= DSP_IDLE; - end - endcase // case (dsp_state) - - assign access_skip_read = 0; - assign access_done = (dsp_state == DSP_DONE); - - assign access_stb = 1; - - assign access_we = (dsp_state == DSP_WRITE_HEADER) | - (dsp_state == DSP_WRITE_TRAILER) | - stb_write; - - assign access_dat_o = (dsp_state == DSP_WRITE_HEADER) ? { 4'h1, new_header } : - (dsp_state == DSP_WRITE_TRAILER) ? { 4'h2, new_trailer } : - (last_o&~even_o) ? {4'h0, i8, q8, 16'd0 } : - {4'h0, i8_reg, q8_reg, i8, q8 }; - - assign access_adr = (stb_write|(dsp_state == DSP_WRITE_HEADER)|(dsp_state == DSP_WRITE_TRAILER)) ? write_adr : read_adr; - - // DSP Pipeline - - wire [15:0] i16 = access_dat_i[31:16]; - wire [15:0] q16 = access_dat_i[15:0]; - - pipectrl #(.STAGES(2), .TAGWIDTH(2)) pipectrl - (.clk(clk), .reset(reset), - .src_rdy_i(send_to_pipe), .dst_rdy_o(), // dst_rdy_o will always be 1 since dst_rdy_i is 1, below - .src_rdy_o(stb_out), .dst_rdy_i(1), // always accept output of chain - .strobes({stb_clip,stb_read}), .valids({val_clip,val_read}), - .tag_i({last,even}), .tag_o({last_o,even_o})); - - always @(posedge clk) - if(stb_out & ~even_o) - {i8_reg,q8_reg} <= {i8,q8}; - - clip_reg #(.bits_in(16),.bits_out(8),.STROBED(1)) clip_i - (.clk(clk), .in(i16), .out(i8), .strobe_in(stb_clip), .strobe_out()); - - clip_reg #(.bits_in(16),.bits_out(8),.STROBED(1)) clip_q - (.clk(clk), .in(q16), .out(q8), .strobe_in(stb_clip), .strobe_out()); - -endmodule // dspengine_16to8 diff --git a/fpga/usrp2/sdr_lib/dspengine_8to16.v b/fpga/usrp2/sdr_lib/dspengine_8to16.v deleted file mode 100644 index 64246ac13..000000000 --- a/fpga/usrp2/sdr_lib/dspengine_8to16.v +++ /dev/null @@ -1,203 +0,0 @@ - -// Copyright 2012-2013 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module dspengine_8to16 - #(parameter BASE = 0, - parameter BUF_SIZE = 9, - parameter HEADER_OFFSET = 0) - (input clk, input reset, input clear, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - output access_we, - output access_stb, - input access_ok, - output access_done, - output access_skip_read, - output [BUF_SIZE-1:0] access_adr, - input [BUF_SIZE-1:0] access_len, - output [35:0] access_dat_o, - input [35:0] access_dat_i - ); - - wire convert; - - setting_reg #(.my_addr(BASE),.width(1)) sr_8to16 - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(convert),.changed()); - - reg [3:0] dsp_state; - localparam DSP_IDLE = 0; - localparam DSP_IDLE_RD = 1; - localparam DSP_PARSE_HEADER = 2; - localparam DSP_READ = 3; - localparam DSP_READ_WAIT = 4; - localparam DSP_WRITE_1 = 5; - localparam DSP_WRITE_0 = 6; - localparam DSP_READ_TRAILER = 7; - localparam DSP_WRITE_TRAILER = 8; - localparam DSP_WRITE_HEADER = 9; - localparam DSP_DONE = 10; - - // Parse VITA header - wire is_if_data = (access_dat_i[31:29] == 3'b000); - wire has_streamid = access_dat_i[28]; - wire has_classid = access_dat_i[27]; - wire has_trailer = access_dat_i[26]; - // 25:24 reserved, aka SOB/EOB - wire has_secs = |access_dat_i[23:22]; - wire has_tics = |access_dat_i[21:20]; - wire [3:0] hdr_length = 1 + has_streamid + has_classid + has_classid + has_secs + has_tics + has_tics; - reg [15:0] hdr_length_reg; - - reg odd; - - reg [BUF_SIZE-1:0] read_adr, write_adr; - reg has_trailer_reg; - - reg [31:0] new_header, new_trailer, trailer_mask; - reg wait_for_trailer; - reg [15:0] data_in_len; - wire is_odd = access_dat_i[22] & access_dat_i[10]; - wire [15:0] data_in_lenx2 = {data_in_len[14:0], 1'b0} - is_odd; - - reg [7:0] i8_0, q8_0; - wire [7:0] i8_1 = access_dat_i[15:8]; - wire [7:0] q8_1 = access_dat_i[7:0]; - reg skip; - - - always @(posedge clk) - { i8_0, q8_0 } <= access_dat_i[31:16]; - - always @(posedge clk) - if(reset | clear) - dsp_state <= DSP_IDLE; - else - case(dsp_state) - DSP_IDLE : - begin - read_adr <= HEADER_OFFSET; - write_adr <= HEADER_OFFSET; - if(access_ok) - dsp_state <= DSP_IDLE_RD; - end - - DSP_IDLE_RD: //extra idle state for read to become valid - dsp_state <= DSP_PARSE_HEADER; - - DSP_PARSE_HEADER : - begin - has_trailer_reg <= has_trailer; - new_header[31:0] <= access_dat_i[31:0]; - hdr_length_reg <= hdr_length; - if(~is_if_data | ~convert | ~has_trailer) - // ~convert is valid (16 bit mode) but both ~trailer and ~is_if_data are both - // really error conditions on the TX side. We shouldn't ever see them in the TX chain - dsp_state <= DSP_WRITE_HEADER; - else - begin - read_adr <= access_dat_i[15:0] + HEADER_OFFSET - 1; // point to trailer - dsp_state <= DSP_READ_TRAILER; - wait_for_trailer <= 0; - data_in_len <= access_dat_i[15:0] - hdr_length - 1 /*trailer*/; - end - end - - DSP_READ_TRAILER : - begin - wait_for_trailer <= 1; - if(wait_for_trailer) - dsp_state <= DSP_WRITE_TRAILER; - new_trailer <= access_dat_i[31:0]; // Leave trailer unchanged - odd <= is_odd; - write_adr <= hdr_length_reg + data_in_lenx2 + HEADER_OFFSET; - end - - DSP_WRITE_TRAILER : - begin - dsp_state <= DSP_READ; - write_adr <= write_adr - 1; - read_adr <= read_adr - 1; - new_header[15:0] <= write_adr + (1 - HEADER_OFFSET); // length = addr of trailer + 1 - end - - DSP_READ : - begin - read_adr <= read_adr - 1; - if(odd) - dsp_state <= DSP_READ_WAIT; - else - dsp_state <= DSP_WRITE_1; - odd <= 0; - end - - DSP_READ_WAIT : - dsp_state <= DSP_WRITE_0; - - DSP_WRITE_1 : - begin - write_adr <= write_adr - 1; - if(write_adr == (hdr_length_reg+HEADER_OFFSET)) - begin - write_adr <= HEADER_OFFSET; - dsp_state <= DSP_WRITE_HEADER; - end - dsp_state <= DSP_WRITE_0; - end - - DSP_WRITE_0 : - begin - write_adr <= write_adr - 1; - if(write_adr == (hdr_length_reg+HEADER_OFFSET)) - begin - write_adr <= HEADER_OFFSET; - dsp_state <= DSP_WRITE_HEADER; - end - else - dsp_state <= DSP_READ; - end - - DSP_WRITE_HEADER : - dsp_state <= DSP_DONE; - - DSP_DONE : - begin - read_adr <= HEADER_OFFSET; - write_adr <= HEADER_OFFSET; - dsp_state <= DSP_IDLE; - end - endcase // case (dsp_state) - - assign access_skip_read = 0; - assign access_done = (dsp_state == DSP_DONE); - - assign access_stb = 1; - - assign access_we = (dsp_state == DSP_WRITE_HEADER) | - (dsp_state == DSP_WRITE_TRAILER) | - (dsp_state == DSP_WRITE_0) | - (dsp_state == DSP_WRITE_1); - - assign access_dat_o = (dsp_state == DSP_WRITE_HEADER) ? { 4'h0, new_header } : - (dsp_state == DSP_WRITE_TRAILER) ? { 4'h2, new_trailer } : - (dsp_state == DSP_WRITE_0) ? { 4'h0, i8_0, 8'd0, q8_0, 8'd0 } : - (dsp_state == DSP_WRITE_1) ? { 4'h0, i8_1, 8'd0, q8_1, 8'd0 } : - 34'h0DEADBEEF; - - assign access_adr = access_we ? write_adr : read_adr; - -endmodule // dspengine_16to8 diff --git a/fpga/usrp2/sdr_lib/duc.v b/fpga/usrp2/sdr_lib/duc.v deleted file mode 100755 index 6dac95b49..000000000 --- a/fpga/usrp2/sdr_lib/duc.v +++ /dev/null @@ -1,95 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// DUC block - -module duc(input clock, - input reset, - input enable, - input [3:0] rate1, - input [3:0] rate2, - output strobe, - input [31:0] freq, - input [15:0] i_in, - input [15:0] q_in, - output [15:0] i_out, - output [15:0] q_out - ); - parameter bw = 16; - parameter zw = 16; - - wire [15:0] i_interp_out, q_interp_out; - wire [31:0] phase; - - wire strobe1, strobe2; - reg [3:0] strobe_ctr1,strobe_ctr2; - - always @(posedge clock) - if(reset | ~enable) - strobe_ctr2 <= #1 4'd0; - else if(strobe2) - strobe_ctr2 <= #1 4'd0; - else - strobe_ctr2 <= #1 strobe_ctr2 + 4'd1; - - always @(posedge clock) - if(reset | ~enable) - strobe_ctr1 <= #1 4'd0; - else if(strobe1) - strobe_ctr1 <= #1 4'd0; - else if(strobe2) - strobe_ctr1 <= #1 strobe_ctr1 + 4'd1; - - - assign strobe2 = enable & ( strobe_ctr2 == rate2 ); - assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 ); - - assign strobe = strobe1; - - function [2:0] log_ceil; - input [3:0] val; - - log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1; - endfunction - - wire [2:0] shift1 = log_ceil(rate1); - wire [2:0] shift2 = log_ceil(rate2); - - cordic #(.bitwidth(bw),.zwidth(zw),.stages(16)) - cordic(.clock(clock), .reset(reset), .enable(enable), - .xi(i_interp_out), .yi(q_interp_out), .zi(phase[31:32-zw]), - .xo(i_out), .yo(q_out), .zo() ); - - cic_interp_2stage #(.bw(bw),.N(4)) - interp_i(.clock(clock),.reset(reset),.enable(enable), - .strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2), - .signal_in(i_in),.signal_out(i_interp_out)); - - cic_interp_2stage #(.bw(bw),.N(4)) - interp_q(.clock(clock),.reset(reset),.enable(enable), - .strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2), - .signal_in(q_in),.signal_out(q_interp_out)); - - phase_acc #(.resolution(32)) - nco (.clk(clock),.reset(reset),.enable(enable), - .freq(freq),.phase(phase)); - -endmodule diff --git a/fpga/usrp2/sdr_lib/duc_chain.v b/fpga/usrp2/sdr_lib/duc_chain.v deleted file mode 100644 index bd3402a1f..000000000 --- a/fpga/usrp2/sdr_lib/duc_chain.v +++ /dev/null @@ -1,165 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -//! The USRP digital up-conversion chain - -module duc_chain - #( - parameter BASE = 0, - parameter DSPNO = 0, - parameter WIDTH = 24 - ) - (input clk, input rst, input clr, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user, - - // To TX frontend - output [WIDTH-1:0] tx_fe_i, - output [WIDTH-1:0] tx_fe_q, - - // From TX control - input [31:0] sample, - input run, - output strobe, - output [31:0] debug - ); - - wire duc_enb; - wire [17:0] scale_factor; - wire [31:0] phase_inc; - reg [31:0] phase; - wire [7:0] interp_rate; - wire [3:0] tx_femux_a, tx_femux_b; - wire enable_hb1, enable_hb2; - wire rate_change; - - setting_reg #(.my_addr(BASE+0)) sr_0 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phase_inc),.changed()); - - setting_reg #(.my_addr(BASE+1), .width(18)) sr_1 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(scale_factor),.changed()); - - setting_reg #(.my_addr(BASE+2), .width(10)) sr_2 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed(rate_change)); - - // Strobes are all now delayed by 1 cycle for timing reasons - wire strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre; - reg strobe_cic = 1; - reg strobe_hb1 = 1; - reg strobe_hb2 = 1; - - cic_strober #(.WIDTH(8)) - cic_strober(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(interp_rate), - .strobe_fast(1),.strobe_slow(strobe_cic_pre) ); - cic_strober #(.WIDTH(2)) - hb2_strober(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(enable_hb2 ? 2 : 1), - .strobe_fast(strobe_cic_pre),.strobe_slow(strobe_hb2_pre) ); - cic_strober #(.WIDTH(2)) - hb1_strober(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(enable_hb1 ? 2 : 1), - .strobe_fast(strobe_hb2_pre),.strobe_slow(strobe_hb1_pre) ); - - always @(posedge clk) strobe_hb1 <= strobe_hb1_pre; - always @(posedge clk) strobe_hb2 <= strobe_hb2_pre; - always @(posedge clk) strobe_cic <= strobe_cic_pre; - - // NCO - always @(posedge clk) - if(rst) - phase <= 0; - else if(~duc_enb) - phase <= 0; - else - phase <= phase + phase_inc; - - wire signed [17:0] da, db; - wire signed [35:0] prod_i, prod_q; - - wire [15:0] bb_i; - wire [15:0] bb_q; - wire [17:0] i_interp, q_interp; - - wire [17:0] hb1_i, hb1_q, hb2_i, hb2_q; - - wire [7:0] cpo = enable_hb2 ? ({interp_rate,1'b0}) : interp_rate; - // Note that max CIC rate is 128, which would give an overflow on cpo if enable_hb2 is true, - // but the default case inside hb_interp handles this - - hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(WIDTH)) hb_interp_i - (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in({bb_i, 2'b0}),.stb_out(strobe_hb2),.data_out(hb1_i)); - hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(WIDTH)) hb_interp_q - (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in({bb_q, 2'b0}),.stb_out(strobe_hb2),.data_out(hb1_q)); - - small_hb_int #(.WIDTH(18)) small_hb_interp_i - (.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_i), - .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_i)); - small_hb_int #(.WIDTH(18)) small_hb_interp_q - (.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_q), - .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_q)); - - cic_interp #(.bw(18),.N(4),.log2_of_max_rate(7)) - cic_interp_i(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(interp_rate), - .strobe_in(strobe_cic),.strobe_out(1), - .signal_in(hb2_i),.signal_out(i_interp)); - - cic_interp #(.bw(18),.N(4),.log2_of_max_rate(7)) - cic_interp_q(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(interp_rate), - .strobe_in(strobe_cic),.strobe_out(1), - .signal_in(hb2_q),.signal_out(q_interp)); - - localparam cwidth = WIDTH; // was 18 - localparam zwidth = 24; // was 16 - - wire [cwidth-1:0] da_c, db_c; - - cordic_z24 #(.bitwidth(cwidth)) - cordic(.clock(clk), .reset(rst), .enable(duc_enb), - .xi({i_interp,{(cwidth-18){1'b0}}}),.yi({q_interp,{(cwidth-18){1'b0}}}), - .zi(phase[31:32-zwidth]), - .xo(da_c),.yo(db_c),.zo() ); - - MULT18X18S MULT18X18S_inst - (.P(prod_i), // 36-bit multiplier output - .A(da_c[cwidth-1:cwidth-18]), // 18-bit multiplier input - .B(scale_factor), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - MULT18X18S MULT18X18S_inst_2 - (.P(prod_q), // 36-bit multiplier output - .A(db_c[cwidth-1:cwidth-18]), // 18-bit multiplier input - .B(scale_factor), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - dsp_tx_glue #(.DSPNO(DSPNO), .WIDTH(WIDTH)) dsp_tx_glue( - .clock(clk), .reset(rst), .clear(clr), .enable(run), - .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), - .frontend_i(tx_fe_i), .frontend_q(tx_fe_q), - .duc_out_i(prod_i[33:34-WIDTH]), .duc_out_q(prod_q[33:34-WIDTH]), - .duc_in_sample({bb_i, bb_q}), .duc_in_strobe(strobe_hb1), .duc_in_enable(duc_enb), - .bb_sample(sample), .bb_strobe(strobe)); - - assign debug = {strobe_cic, strobe_hb1, strobe_hb2,run}; - -endmodule // dsp_core diff --git a/fpga/usrp2/sdr_lib/dummy_rx.v b/fpga/usrp2/sdr_lib/dummy_rx.v deleted file mode 100644 index 42bbe36b2..000000000 --- a/fpga/usrp2/sdr_lib/dummy_rx.v +++ /dev/null @@ -1,79 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -`define DSP_CORE_RX_BASE 160 -module dummy_rx - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - input [13:0] adc_a, input adc_ovf_a, - input [13:0] adc_b, input adc_ovf_b, - - output [31:0] sample, - input run, - output strobe - ); - - wire [15:0] scale_i, scale_q; - wire [31:0] phase_inc; - reg [31:0] phase; - - wire [23:0] i_decim, q_decim; - wire [7:0] decim_rate; - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phase_inc),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({scale_i,scale_q}),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(decim_rate),.changed()); - - strobe_gen strobe_gen(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate), - .strobe_in(1),.strobe(strobe) ); - - reg [15:0] i_out, q_out; - assign sample = {i_out,q_out}; - - always @(posedge clk) - if(rst) - i_out <= 0; - else if(~run) - i_out <= 0; - else if(strobe) - i_out <= i_out + 1; - - reg run_d1; - always @(posedge clk) - if(rst) - run_d1 <= 0; - else - run_d1 <= run; - - always @(posedge clk) - if(rst) - q_out <= 0; - else if (run & ~run_d1) - q_out <= q_out + 1; - - -endmodule // ddc_chain diff --git a/fpga/usrp2/sdr_lib/gen_cordic_consts.py b/fpga/usrp2/sdr_lib/gen_cordic_consts.py deleted file mode 100755 index 261e8c223..000000000 --- a/fpga/usrp2/sdr_lib/gen_cordic_consts.py +++ /dev/null @@ -1,10 +0,0 @@ -#!/usr/bin/env python - -import math - -zwidth = 24 - -for i in range(24): - c = math.atan (1.0/(2**i)) / (2 * math.pi) * (1 << zwidth) - print "localparam c%02d = %d'd%d;" % (i, zwidth, round (c)) - diff --git a/fpga/usrp2/sdr_lib/halfband_ideal.v b/fpga/usrp2/sdr_lib/halfband_ideal.v deleted file mode 100644 index e0b04cf86..000000000 --- a/fpga/usrp2/sdr_lib/halfband_ideal.v +++ /dev/null @@ -1,101 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module halfband_ideal ( - input clock, - input reset, - input enable, - input strobe_in, - input wire signed [17:0] data_in, - output reg strobe_out, - output reg signed [17:0] data_out -) ; - - parameter decim = 1 ; - parameter rate = 2 ; - - reg signed [40:0] temp ; - reg signed [17:0] delay[30:0] ; - reg signed [17:0] coeffs[30:0] ; - reg [7:0] count ; - integer i ; - - initial begin - for( i = 0 ; i < 31 ; i = i + 1 ) begin - coeffs[i] = 18'd0 ; - end - coeffs[0] = -1390 ; - coeffs[2] = 1604 ; - coeffs[4] = -1896 ; - coeffs[6] = 2317 ; - coeffs[8] = -2979 ; - coeffs[10] = 4172 ; - coeffs[12] = -6953 ; - coeffs[14] = 20860 ; - coeffs[15] = 32768 ; - coeffs[16] = 20860 ; - coeffs[18] = -6953 ; - coeffs[20] = 4172 ; - coeffs[22] = -2979 ; - coeffs[24] = 2317 ; - coeffs[26] = -1896 ; - coeffs[28] = 1604 ; - coeffs[30] = -1390 ; - end - - always @(posedge clock) begin - if( reset ) begin - count <= 0 ; - for( i = 0 ; i < 31 ; i = i + 1 ) begin - delay[i] <= 18'd0 ; - end - temp <= 41'd0 ; - data_out <= 18'd0 ; - strobe_out <= 1'b0 ; - end else if( enable ) begin - - if( (decim && (count == rate-1)) || !decim ) - strobe_out <= strobe_in ; - else - strobe_out <= 1'b0 ; - - - if( strobe_in ) begin - // Increment decimation count - count <= count + 1 ; - - // Shift the input - for( i = 30 ; i > 0 ; i = i - 1 ) begin - delay[i] = delay[i-1] ; - end - delay[0] = data_in ; - - // clear the temp reg - temp = 18'd0 ; - if( (decim && (count == rate-1)) || !decim ) begin - count <= 0 ; - for( i = 0 ; i < 31 ; i = i + 1 ) begin - // Multiply Accumulate - temp = temp + delay[i]*coeffs[i] ; - end - // Assign data output - data_out <= temp >>> 15 ; - end - end - end - end -endmodule diff --git a/fpga/usrp2/sdr_lib/halfband_tb.v b/fpga/usrp2/sdr_lib/halfband_tb.v deleted file mode 100644 index 80f46fe36..000000000 --- a/fpga/usrp2/sdr_lib/halfband_tb.v +++ /dev/null @@ -1,137 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module halfband_tb( ) ; - - // Parameters for instantiation - parameter clocks = 2 ; // Number of clocks per input - parameter decim = 0 ; // Sets the filter to decimate - parameter rate = 2 ; // Sets the decimation rate - - reg clock ; - reg reset ; - reg enable ; - reg strobe_in ; - reg signed [17:0] data_in ; - wire strobe_out ; - wire signed [17:0] data_out ; - - // Setup the clock - initial clock = 1'b0 ; - always #5 clock <= ~clock ; - - // Come out of reset after a while - initial reset = 1'b1 ; - initial #100 reset = 1'b0 ; - - // Enable the entire system - initial enable = 1'b1 ; - - // Instantiate UUT - halfband_ideal - #( - .decim ( decim ), - .rate ( rate ) - ) uut( - .clock ( clock ), - .reset ( reset ), - .enable ( enable ), - .strobe_in ( strobe_in ), - .data_in ( data_in ), - .strobe_out ( strobe_out ), - .data_out ( data_out ) - ) ; - - integer i, ri, ro, infile, outfile ; - - // Setup file IO - initial begin - infile = $fopen("input.dat","r") ; - outfile = $fopen("output.dat","r") ; - $timeformat(-9, 2, " ns", 10) ; - end - - reg endofsim ; - reg signed [17:0] compare ; - integer noe ; - initial noe = 0 ; - - initial begin - // Initialize inputs - strobe_in <= 1'd0 ; - data_in <= 18'd0 ; - - // Wait for reset to go away - @(negedge reset) #0 ; - - // While we're still simulating ... - while( !endofsim ) begin - - // Write the input from the file or 0 if EOF... - @( posedge clock ) begin - #1 ; - strobe_in <= 1'b1 ; - if( !$feof(infile) ) - ri = $fscanf( infile, "%d", data_in ) ; - else - data_in <= 18'd0 ; - end - - // Clocked in - set the strobe to 0 if the number of - // clocks per sample is greater than 1 - if( clocks > 1 ) begin - @(posedge clock) begin - strobe_in <= 1'b0 ; - end - - // Wait for the specified number of cycles - for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin - @(posedge clock) #1 ; - end - end - end - - // Print out the number of errors that occured - if( noe ) - $display( "FAILED: %d errors during simulation", noe ) ; - else - $display( "PASSED: Simulation successful" ) ; - - $stop ; - end - - // Output comparison of simulated values versus known good values - always @ (posedge clock) begin - if( reset ) - endofsim <= 1'b0 ; - else begin - if( !$feof(outfile) ) begin - if( strobe_out ) begin - ro = $fscanf( outfile, "%d\n", compare ) ; - if( compare != data_out ) begin - $display( "%t: %d != %d", $realtime, data_out, compare ) ; - noe = noe + 1 ; - end - end - end else begin - // Signal end of simulation when no more outputs - endofsim <= 1'b1 ; - end - end - end - -endmodule diff --git a/fpga/usrp2/sdr_lib/hb/acc.v b/fpga/usrp2/sdr_lib/hb/acc.v deleted file mode 100644 index d7be895c6..000000000 --- a/fpga/usrp2/sdr_lib/hb/acc.v +++ /dev/null @@ -1,39 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module acc (input clock, input reset, input clear, input enable_in, output reg enable_out, - input signed [30:0] addend, output reg signed [33:0] sum ); - - always @(posedge clock) - if(reset) - sum <= #1 34'd0; - //else if(clear & enable_in) - // sum <= #1 addend; - //else if(clear) - // sum <= #1 34'd0; - else if(clear) - sum <= #1 addend; - else if(enable_in) - sum <= #1 sum + addend; - - always @(posedge clock) - enable_out <= #1 enable_in; - -endmodule // acc - diff --git a/fpga/usrp2/sdr_lib/hb/coeff_ram.v b/fpga/usrp2/sdr_lib/hb/coeff_ram.v deleted file mode 100644 index 525c22abc..000000000 --- a/fpga/usrp2/sdr_lib/hb/coeff_ram.v +++ /dev/null @@ -1,43 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module coeff_ram (input clock, input [3:0] rd_addr, output reg [15:0] rd_data); - - always @(posedge clock) - case (rd_addr) - 4'd0 : rd_data <= #1 -16'd16; - 4'd1 : rd_data <= #1 16'd74; - 4'd2 : rd_data <= #1 -16'd254; - 4'd3 : rd_data <= #1 16'd669; - 4'd4 : rd_data <= #1 -16'd1468; - 4'd5 : rd_data <= #1 16'd2950; - 4'd6 : rd_data <= #1 -16'd6158; - 4'd7 : rd_data <= #1 16'd20585; - 4'd8 : rd_data <= #1 16'd20585; - 4'd9 : rd_data <= #1 -16'd6158; - 4'd10 : rd_data <= #1 16'd2950; - 4'd11 : rd_data <= #1 -16'd1468; - 4'd12 : rd_data <= #1 16'd669; - 4'd13 : rd_data <= #1 -16'd254; - 4'd14 : rd_data <= #1 16'd74; - 4'd15 : rd_data <= #1 -16'd16; - default : rd_data <= #1 16'd0; - endcase // case(rd_addr) - -endmodule // ram diff --git a/fpga/usrp2/sdr_lib/hb/coeff_rom.v b/fpga/usrp2/sdr_lib/hb/coeff_rom.v deleted file mode 100644 index a43c8391a..000000000 --- a/fpga/usrp2/sdr_lib/hb/coeff_rom.v +++ /dev/null @@ -1,36 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data); - - always @(posedge clock) - case (addr) - 3'd0 : data <= #1 -16'd49; - 3'd1 : data <= #1 16'd165; - 3'd2 : data <= #1 -16'd412; - 3'd3 : data <= #1 16'd873; - 3'd4 : data <= #1 -16'd1681; - 3'd5 : data <= #1 16'd3135; - 3'd6 : data <= #1 -16'd6282; - 3'd7 : data <= #1 16'd20628; - endcase // case(addr) - -endmodule // coeff_rom - - diff --git a/fpga/usrp2/sdr_lib/hb/halfband_decim.v b/fpga/usrp2/sdr_lib/hb/halfband_decim.v deleted file mode 100644 index dff4d902c..000000000 --- a/fpga/usrp2/sdr_lib/hb/halfband_decim.v +++ /dev/null @@ -1,163 +0,0 @@ -/* -*- verilog -*- - * - * USRP - Universal Software Radio Peripheral - * - * Copyright (C) 2005 Matt Ettus - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA - */ - -/* - * This implements a 31-tap halfband filter that decimates by two. - * The coefficients are symmetric, and with the exception of the middle tap, - * every other coefficient is zero. The middle section of taps looks like this: - * - * ..., -1468, 0, 2950, 0, -6158, 0, 20585, 32768, 20585, 0, -6158, 0, 2950, 0, -1468, ... - * | - * middle tap -------+ - * - * See coeff_rom.v for the full set. The taps are scaled relative to 32768, - * thus the middle tap equals 1.0. Not counting the middle tap, there are 8 - * non-zero taps on each side, and they are symmetric. A naive implementation - * requires a mulitply for each non-zero tap. Because of symmetry, we can - * replace 2 multiplies with 1 add and 1 multiply. Thus, to compute each output - * sample, we need to perform 8 multiplications. Since the middle tap is 1.0, - * we just add the corresponding delay line value. - * - * About timing: We implement this with a single multiplier, so it takes - * 8 cycles to compute a single output. However, since we're decimating by two - * we can accept a new input value every 4 cycles. strobe_in is asserted when - * there's a new input sample available. Depending on the overall decimation - * rate, strobe_in may be asserted less frequently than once every 4 clocks. - * On the output side, we assert strobe_out when output contains a new sample. - * - * Implementation: Every time strobe_in is asserted we store the new data into - * the delay line. We split the delay line into two components, one for the - * even samples, and one for the odd samples. ram16_odd is the delay line for - * the odd samples. This ram is written on each odd assertion of strobe_in, and - * is read on each clock when we're computing the dot product. ram16_even is - * similar, although because it holds the even samples we must be able to read - * two samples from different addresses at the same time, while writing the incoming - * even samples. Thus it's "triple-ported". - */ - -module halfband_decim - (input clock, input reset, input enable, input strobe_in, output wire strobe_out, - input wire [15:0] data_in, output reg [15:0] data_out,output wire [15:0] debugctrl); - - reg [3:0] rd_addr1; - reg [3:0] rd_addr2; - reg [3:0] phase; - reg [3:0] base_addr; - - wire signed [15:0] mac_out,middle_data, sum, coeff; - wire signed [30:0] product; - wire signed [33:0] sum_even; - wire clear; - reg store_odd; - - always @(posedge clock) - if(reset) - store_odd <= #1 1'b0; - else - if(strobe_in) - store_odd <= #1 ~store_odd; - - wire start = strobe_in & store_odd; - always @(posedge clock) - if(reset) - base_addr <= #1 4'd0; - else if(start) - base_addr <= #1 base_addr + 4'd1; - - always @(posedge clock) - if(reset) - phase <= #1 4'd8; - else if (start) - phase <= #1 4'd0; - else if(phase != 4'd8) - phase <= #1 phase + 4'd1; - - reg start_d1,start_d2,start_d3,start_d4,start_d5,start_d6,start_d7,start_d8,start_d9,start_dA,start_dB,start_dC,start_dD; - always @(posedge clock) - begin - start_d1 <= #1 start; - start_d2 <= #1 start_d1; - start_d3 <= #1 start_d2; - start_d4 <= #1 start_d3; - start_d5 <= #1 start_d4; - start_d6 <= #1 start_d5; - start_d7 <= #1 start_d6; - start_d8 <= #1 start_d7; - start_d9 <= #1 start_d8; - start_dA <= #1 start_d9; - start_dB <= #1 start_dA; - start_dC <= #1 start_dB; - start_dD <= #1 start_dC; - end // always @ (posedge clock) - - reg mult_en, mult_en_pre; - always @(posedge clock) - begin - mult_en_pre <= #1 phase!=8; - mult_en <= #1 mult_en_pre; - end - - assign clear = start_d4; // was dC - wire latch_result = start_d4; // was dC - assign strobe_out = start_d5; // was dD - wire acc_en; - - always @* - case(phase[2:0]) - 3'd0 : begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end - 3'd1 : begin rd_addr1 = base_addr + 4'd1; rd_addr2 = base_addr + 4'd14; end - 3'd2 : begin rd_addr1 = base_addr + 4'd2; rd_addr2 = base_addr + 4'd13; end - 3'd3 : begin rd_addr1 = base_addr + 4'd3; rd_addr2 = base_addr + 4'd12; end - 3'd4 : begin rd_addr1 = base_addr + 4'd4; rd_addr2 = base_addr + 4'd11; end - 3'd5 : begin rd_addr1 = base_addr + 4'd5; rd_addr2 = base_addr + 4'd10; end - 3'd6 : begin rd_addr1 = base_addr + 4'd6; rd_addr2 = base_addr + 4'd9; end - 3'd7 : begin rd_addr1 = base_addr + 4'd7; rd_addr2 = base_addr + 4'd8; end - default: begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end - endcase // case(phase) - - coeff_rom coeff_rom (.clock(clock),.addr(phase[2:0]-3'd1),.data(coeff)); - - ram16_2sum ram16_even (.clock(clock),.write(strobe_in & ~store_odd), - .wr_addr(base_addr),.wr_data(data_in), - .rd_addr1(rd_addr1),.rd_addr2(rd_addr2), - .sum(sum)); - - ram16 ram16_odd (.clock(clock),.write(strobe_in & store_odd), // Holds middle items - .wr_addr(base_addr),.wr_data(data_in), - //.rd_addr(base_addr+4'd7),.rd_data(middle_data)); - .rd_addr(base_addr+4'd6),.rd_data(middle_data)); - - mult mult(.clock(clock),.x(coeff),.y(sum),.product(product),.enable_in(mult_en),.enable_out(acc_en)); - - acc acc(.clock(clock),.reset(reset),.enable_in(acc_en),.enable_out(), - .clear(clear),.addend(product),.sum(sum_even)); - - wire signed [33:0] dout = sum_even + {{4{middle_data[15]}},middle_data,14'b0}; // We already divided product by 2!!!! - - always @(posedge clock) - if(reset) - data_out <= #1 16'd0; - else if(latch_result) - data_out <= #1 dout[30:15] + (dout[33]& |dout[14:0]); - - assign debugctrl = { clock,reset,acc_en,mult_en,clear,latch_result,store_odd,strobe_in,strobe_out,phase}; - -endmodule // halfband_decim diff --git a/fpga/usrp2/sdr_lib/hb/halfband_interp.v b/fpga/usrp2/sdr_lib/hb/halfband_interp.v deleted file mode 100644 index 83bdc9fad..000000000 --- a/fpga/usrp2/sdr_lib/hb/halfband_interp.v +++ /dev/null @@ -1,138 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module halfband_interp - (input clock, input reset, input enable, - input strobe_in, input strobe_out, - input [15:0] signal_in_i, input [15:0] signal_in_q, - output reg [15:0] signal_out_i, output reg [15:0] signal_out_q, - output wire [12:0] debug); - - wire [15:0] coeff_ram_out; - wire [15:0] data_ram_out_i; - wire [15:0] data_ram_out_q; - - wire [3:0] data_rd_addr; - reg [3:0] data_wr_addr; - reg [2:0] coeff_rd_addr; - - wire filt_done; - - wire [15:0] mac_out_i; - wire [15:0] mac_out_q; - reg [15:0] delayed_middle_i, delayed_middle_q; - wire [7:0] shift = 8'd9; - - reg stb_out_happened; - - wire [15:0] data_ram_out_i_b; - - always @(posedge clock) - if(strobe_in) - stb_out_happened <= #1 1'b0; - else if(strobe_out) - stb_out_happened <= #1 1'b1; - -assign debug = {filt_done,data_rd_addr,data_wr_addr,coeff_rd_addr}; - - wire [15:0] signal_out_i = stb_out_happened ? mac_out_i : delayed_middle_i; - wire [15:0] signal_out_q = stb_out_happened ? mac_out_q : delayed_middle_q; - -/* always @(posedge clock) - if(reset) - begin - signal_out_i <= #1 16'd0; - signal_out_q <= #1 16'd0; - end - else if(strobe_in) - begin - signal_out_i <= #1 delayed_middle_i; // Multiply by 1 for middle coeff - signal_out_q <= #1 delayed_middle_q; - end - //else if(filt_done&stb_out_happened) - else if(stb_out_happened) - begin - signal_out_i <= #1 mac_out_i; - signal_out_q <= #1 mac_out_q; - end -*/ - - always @(posedge clock) - if(reset) - coeff_rd_addr <= #1 3'd0; - else if(coeff_rd_addr != 3'd0) - coeff_rd_addr <= #1 coeff_rd_addr + 3'd1; - else if(strobe_in) - coeff_rd_addr <= #1 3'd1; - - reg filt_done_d1; - always@(posedge clock) - filt_done_d1 <= #1 filt_done; - - always @(posedge clock) - if(reset) - data_wr_addr <= #1 4'd0; - //else if(strobe_in) - else if(filt_done & ~filt_done_d1) - data_wr_addr <= #1 data_wr_addr + 4'd1; - - always @(posedge clock) - if(coeff_rd_addr == 3'd7) - begin - delayed_middle_i <= #1 data_ram_out_i_b; - // delayed_middle_q <= #1 data_ram_out_q_b; - end - -// always @(posedge clock) -// if(reset) -// data_rd_addr <= #1 4'd0; -// else if(strobe_in) -// data_rd_addr <= #1 data_wr_addr + 4'd1; -// else if(!filt_done) -// data_rd_addr <= #1 data_rd_addr + 4'd1; -// else -// data_rd_addr <= #1 data_wr_addr; - - wire [3:0] data_rd_addr1 = data_wr_addr + {1'b0,coeff_rd_addr}; - wire [3:0] data_rd_addr2 = data_wr_addr + 15 - {1'b0,coeff_rd_addr}; -// always @(posedge clock) -// if(reset) -// filt_done <= #1 1'b1; -// else if(strobe_in) - // filt_done <= #1 1'b0; -// else if(coeff_rd_addr == 4'd0) -// filt_done <= #1 1'b1; - - assign filt_done = (coeff_rd_addr == 3'd0); - - coeff_ram coeff_ram ( .clock(clock),.rd_addr({1'b0,coeff_rd_addr}),.rd_data(coeff_ram_out) ); - - ram16_2sum data_ram_i ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_i), - .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_i_b),.sum(data_ram_out_i)); - - ram16_2sum data_ram_q ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_q), - .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_q)); - - mac mac_i (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in), - .x(data_ram_out_i),.y(coeff_ram_out),.shift(shift),.z(mac_out_i) ); - - mac mac_q (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in), - .x(data_ram_out_q),.y(coeff_ram_out),.shift(shift),.z(mac_out_q) ); - -endmodule // halfband_interp diff --git a/fpga/usrp2/sdr_lib/hb/hbd_tb/HBD b/fpga/usrp2/sdr_lib/hb/hbd_tb/HBD deleted file mode 100644 index 574fbba91..000000000 --- a/fpga/usrp2/sdr_lib/hb/hbd_tb/HBD +++ /dev/null @@ -1,80 +0,0 @@ -*-6.432683 5736 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -test_hbd.clock -test_hbd.reset -@420 -test_hbd.halfband_decim.middle_data[15:0] -@22 -test_hbd.halfband_decim.sum_even[33:0] -test_hbd.halfband_decim.base_addr[3:0] -@420 -test_hbd.i_in[15:0] -@24 -test_hbd.halfband_decim.phase[3:0] -test_hbd.halfband_decim.ram16_even.rd_addr1[3:0] -test_hbd.halfband_decim.ram16_even.rd_addr2[3:0] -test_hbd.halfband_decim.ram16_even.wr_addr[3:0] -test_hbd.halfband_decim.ram16_even.wr_data[15:0] -@28 -test_hbd.halfband_decim.ram16_even.write -@420 -test_hbd.halfband_decim.sum[15:0] -test_hbd.halfband_decim.product[30:0] -test_hbd.halfband_decim.dout[33:0] -test_hbd.halfband_decim.sum_even[33:0] -@22 -test_hbd.halfband_decim.acc.addend[30:0] -@28 -test_hbd.halfband_decim.acc.reset -@420 -test_hbd.halfband_decim.acc.sum[33:0] -test_hbd.halfband_decim.mult.x[15:0] -test_hbd.halfband_decim.mult.y[15:0] -@28 -test_hbd.halfband_decim.acc.clear -test_hbd.strobe_in -test_hbd.strobe_out -test_hbd.halfband_decim.acc_en -@420 -test_hbd.i_out[15:0] -@28 -test_hbd.halfband_decim.mult_en -test_hbd.halfband_decim.latch_result -@420 -test_hbd.halfband_decim.sum[15:0] -test_hbd.halfband_decim.sum_even[33:0] -test_hbd.halfband_decim.dout[33:0] -test_hbd.halfband_decim.data_out[15:0] -@22 -test_hbd.halfband_decim.data_out[15:0] -@28 -test_hbd.halfband_decim.dout[33:0] -@29 -test_hbd.halfband_decim.acc_en -@22 -test_hbd.halfband_decim.base_addr[3:0] -@28 -test_hbd.halfband_decim.clear -test_hbd.halfband_decim.latch_result -test_hbd.halfband_decim.mult_en -test_hbd.halfband_decim.mult_en_pre -@22 -test_hbd.halfband_decim.phase[3:0] -@28 -test_hbd.halfband_decim.start -test_hbd.halfband_decim.start_d1 -test_hbd.halfband_decim.start_d2 -test_hbd.halfband_decim.start_d3 -test_hbd.halfband_decim.start_d4 -test_hbd.halfband_decim.start_d5 -test_hbd.halfband_decim.start_d6 -test_hbd.halfband_decim.start_d7 -test_hbd.halfband_decim.start_d8 -test_hbd.halfband_decim.start_d9 -test_hbd.halfband_decim.start_dA -test_hbd.halfband_decim.start_dB -test_hbd.halfband_decim.start_dC -test_hbd.halfband_decim.start_dD -test_hbd.halfband_decim.store_odd -test_hbd.halfband_decim.strobe_in -test_hbd.halfband_decim.strobe_out diff --git a/fpga/usrp2/sdr_lib/hb/hbd_tb/really_golden b/fpga/usrp2/sdr_lib/hb/hbd_tb/really_golden deleted file mode 100644 index 2d24a9e14..000000000 --- a/fpga/usrp2/sdr_lib/hb/hbd_tb/really_golden +++ /dev/null @@ -1,142 +0,0 @@ -VCD info: dumpfile test_hbd.vcd opened for output. - x - x - x - x - x - x - x - x - x - x - x - x - x - x - x - x - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 8192 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 -- 4 - 18 -- 63 - 167 -- 367 - 737 -- 1539 - 5146 - 5146 -- 1539 - 737 -- 367 - 167 -- 63 - 18 -- 4 - 0 - 0 - 0 - 0 - 0 -- 4 - 14 -- 49 - 118 -- 249 - 488 - 7141 -12287 -17433 -15894 -16631 -16264 -16432 -16368 -16387 -16383 -16383 -16383 -16383 -16383 -16387 -16368 -16432 -16264 -16631 -15894 - 9241 - 4095 -- 1051 - 488 -- 249 - 118 -- 49 - 14 -- 4 - 0 - 0 - 0 - 0 - 0 -- 4 - 14 -- 49 - 118 -- 249 - 488 -- 1051 -12287 -17433 -15894 -16631 -16264 -16432 -16368 -16387 -16383 -16383 -16383 -16383 -16383 -16387 -16368 -16432 -16264 -16631 -15894 -17433 - 4095 -- 1051 - 488 -- 249 - 118 -- 49 - 14 -- 4 - 0 - 0 - 0 - 0 diff --git a/fpga/usrp2/sdr_lib/hb/hbd_tb/regression b/fpga/usrp2/sdr_lib/hb/hbd_tb/regression deleted file mode 100644 index fc279c2f2..000000000 --- a/fpga/usrp2/sdr_lib/hb/hbd_tb/regression +++ /dev/null @@ -1,95 +0,0 @@ -echo "Baseline 1000" -iverilog -y .. -o test_hbd -DRATE=1000 test_hbd.v ; ./test_hbd >golden -diff golden really_golden - -echo -echo "Test 100" -iverilog -y .. -o test_hbd -DRATE=100 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 50" -iverilog -y .. -o test_hbd -DRATE=50 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 40" -iverilog -y .. -o test_hbd -DRATE=40 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 30" -iverilog -y .. -o test_hbd -DRATE=30 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 25" -iverilog -y .. -o test_hbd -DRATE=25 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 20" -iverilog -y .. -o test_hbd -DRATE=20 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 19" -iverilog -y .. -o test_hbd -DRATE=19 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 18" -iverilog -y .. -o test_hbd -DRATE=18 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 17" -iverilog -y .. -o test_hbd -DRATE=17 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 16" -iverilog -y .. -o test_hbd -DRATE=16 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 15" -iverilog -y .. -o test_hbd -DRATE=15 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 14" -iverilog -y .. -o test_hbd -DRATE=14 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 13" -iverilog -y .. -o test_hbd -DRATE=13 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 12" -iverilog -y .. -o test_hbd -DRATE=12 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 11" -iverilog -y .. -o test_hbd -DRATE=11 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 10" -iverilog -y .. -o test_hbd -DRATE=10 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 9" -iverilog -y .. -o test_hbd -DRATE=9 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 8" -iverilog -y .. -o test_hbd -DRATE=8 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 7" -iverilog -y .. -o test_hbd -DRATE=7 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 6" -iverilog -y .. -o test_hbd -DRATE=6 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 5" -iverilog -y .. -o test_hbd -DRATE=5 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 4" -iverilog -y .. -o test_hbd -DRATE=4 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 3" -iverilog -y .. -o test_hbd -DRATE=3 test_hbd.v ; ./test_hbd >output ; diff output golden diff --git a/fpga/usrp2/sdr_lib/hb/hbd_tb/run_hbd b/fpga/usrp2/sdr_lib/hb/hbd_tb/run_hbd deleted file mode 100755 index b8aec7574..000000000 --- a/fpga/usrp2/sdr_lib/hb/hbd_tb/run_hbd +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/sh - -iverilog -y .. -o test_hbd test_hbd.v -./test_hbd diff --git a/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v b/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v deleted file mode 100644 index 450f90e66..000000000 --- a/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v +++ /dev/null @@ -1,92 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module test_hbd(); - - reg clock; - initial clock = 1'b0; - always #5 clock <= ~clock; - - reg reset; - initial reset = 1'b1; - initial #1000 reset = 1'b0; - - initial $dumpfile("test_hbd.vcd"); - initial $dumpvars(0,test_hbd); - - reg [15:0] i_in, q_in; - wire [15:0] i_out, q_out; - - reg strobe_in; - wire strobe_out; - reg coeff_write; - reg [15:0] coeff_data; - reg [4:0] coeff_addr; - - halfband_decim halfband_decim - ( .clock(clock),.reset(reset),.enable(),.strobe_in(strobe_in),.strobe_out(strobe_out), - .data_in(i_in),.data_out(i_out) ); - - always @(posedge strobe_out) - if(i_out[15]) - $display("-%d",65536-i_out); - else - $display("%d",i_out); - - initial - begin - strobe_in = 1'b0; - @(negedge reset); - @(posedge clock); - while(1) - begin - strobe_in <= #1 1'b1; - @(posedge clock); - strobe_in <= #1 1'b0; - repeat (`RATE) - @(posedge clock); - end - end - - initial #10000000 $finish; // Just in case... - - initial - begin - i_in <= #1 16'd0; - repeat (40) @(posedge strobe_in); - i_in <= #1 16'd16384; - @(posedge strobe_in); - i_in <= #1 16'd0; - repeat (40) @(posedge strobe_in); - i_in <= #1 16'd16384; - @(posedge strobe_in); - i_in <= #1 16'd0; - repeat (40) @(posedge strobe_in); - i_in <= #1 16'd16384; - repeat (40) @(posedge strobe_in); - i_in <= #1 16'd0; - repeat (41) @(posedge strobe_in); - i_in <= #1 16'd16384; - repeat (40) @(posedge strobe_in); - i_in <= #1 16'd0; - repeat (40) @(posedge strobe_in); - repeat (7) @(posedge clock); - $finish; - end // initial begin -endmodule // test_hb diff --git a/fpga/usrp2/sdr_lib/hb/mac.v b/fpga/usrp2/sdr_lib/hb/mac.v deleted file mode 100644 index 8058a6db4..000000000 --- a/fpga/usrp2/sdr_lib/hb/mac.v +++ /dev/null @@ -1,75 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module mac (input clock, input reset, input enable, input clear, - input signed [15:0] x, input signed [15:0] y, - input [7:0] shift, output [15:0] z ); - - reg signed [30:0] product; - reg signed [39:0] z_int; - reg signed [15:0] z_shift; - - reg enable_d1; - always @(posedge clock) - enable_d1 <= #1 enable; - - always @(posedge clock) - if(reset | clear) - z_int <= #1 40'd0; - else if(enable_d1) - z_int <= #1 z_int + {{9{product[30]}},product}; - - always @(posedge clock) - product <= #1 x*y; - - always @* // FIXME full case? parallel case? - case(shift) - //8'd0 : z_shift <= z_int[39:24]; - //8'd1 : z_shift <= z_int[38:23]; - //8'd2 : z_shift <= z_int[37:22]; - //8'd3 : z_shift <= z_int[36:21]; - //8'd4 : z_shift <= z_int[35:20]; - //8'd5 : z_shift <= z_int[34:19]; - 8'd6 : z_shift <= z_int[33:18]; - 8'd7 : z_shift <= z_int[32:17]; - 8'd8 : z_shift <= z_int[31:16]; - 8'd9 : z_shift <= z_int[30:15]; - 8'd10 : z_shift <= z_int[29:14]; - 8'd11 : z_shift <= z_int[28:13]; - //8'd12 : z_shift <= z_int[27:12]; - //8'd13 : z_shift <= z_int[26:11]; - //8'd14 : z_shift <= z_int[25:10]; - //8'd15 : z_shift <= z_int[24:9]; - //8'd16 : z_shift <= z_int[23:8]; - //8'd17 : z_shift <= z_int[22:7]; - //8'd18 : z_shift <= z_int[21:6]; - //8'd19 : z_shift <= z_int[20:5]; - //8'd20 : z_shift <= z_int[19:4]; - //8'd21 : z_shift <= z_int[18:3]; - //8'd22 : z_shift <= z_int[17:2]; - //8'd23 : z_shift <= z_int[16:1]; - //8'd24 : z_shift <= z_int[15:0]; - default : z_shift <= z_int[15:0]; - endcase // case(shift) - - // FIXME do we need to saturate? - //assign z = z_shift; - assign z = z_int[15:0]; - -endmodule // mac diff --git a/fpga/usrp2/sdr_lib/hb/mult.v b/fpga/usrp2/sdr_lib/hb/mult.v deleted file mode 100644 index a50ae69e2..000000000 --- a/fpga/usrp2/sdr_lib/hb/mult.v +++ /dev/null @@ -1,33 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module mult (input clock, input signed [15:0] x, input signed [15:0] y, output reg signed [30:0] product, - input enable_in, output reg enable_out ); - - always @(posedge clock) - if(enable_in) - product <= #1 x*y; - else - product <= #1 31'd0; - - always @(posedge clock) - enable_out <= #1 enable_in; - -endmodule // mult - diff --git a/fpga/usrp2/sdr_lib/hb/ram16_2port.v b/fpga/usrp2/sdr_lib/hb/ram16_2port.v deleted file mode 100644 index 631cf5a41..000000000 --- a/fpga/usrp2/sdr_lib/hb/ram16_2port.v +++ /dev/null @@ -1,39 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module ram16_2port (input clock, input write, - input [3:0] wr_addr, input [15:0] wr_data, - input [3:0] rd_addr1, output reg [15:0] rd_data1, - input [3:0] rd_addr2, output reg [15:0] rd_data2); - - reg [15:0] ram_array [0:31]; - - always @(posedge clock) - rd_data1 <= #1 ram_array[rd_addr1]; - - always @(posedge clock) - rd_data2 <= #1 ram_array[rd_addr2]; - - always @(posedge clock) - if(write) - ram_array[wr_addr] <= #1 wr_data; - -endmodule // ram16_2port - - diff --git a/fpga/usrp2/sdr_lib/hb/ram16_2sum.v b/fpga/usrp2/sdr_lib/hb/ram16_2sum.v deleted file mode 100644 index f9ec1837e..000000000 --- a/fpga/usrp2/sdr_lib/hb/ram16_2sum.v +++ /dev/null @@ -1,44 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module ram16_2sum (input clock, input write, - input [3:0] wr_addr, input [15:0] wr_data, - input [3:0] rd_addr1, input [3:0] rd_addr2, - output reg [15:0] sum); - - reg signed [15:0] ram_array [0:15]; - reg signed [15:0] a,b; - wire signed [16:0] sum_int; - - always @(posedge clock) - if(write) - ram_array[wr_addr] <= #1 wr_data; - - always @(posedge clock) - begin - a <= #1 ram_array[rd_addr1]; - b <= #1 ram_array[rd_addr2]; - end - - assign sum_int = {a[15],a} + {b[15],b}; - - always @(posedge clock) - sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]); - -endmodule // ram16_2sum diff --git a/fpga/usrp2/sdr_lib/hb/ram32_2sum.v b/fpga/usrp2/sdr_lib/hb/ram32_2sum.v deleted file mode 100644 index f7032835e..000000000 --- a/fpga/usrp2/sdr_lib/hb/ram32_2sum.v +++ /dev/null @@ -1,39 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module ram32_2sum (input clock, input write, - input [4:0] wr_addr, input [15:0] wr_data, - input [4:0] rd_addr1, input [4:0] rd_addr2, - output reg [15:0] sum); - - reg [15:0] ram_array [0:31]; - wire [16:0] sum_int; - - always @(posedge clock) - if(write) - ram_array[wr_addr] <= #1 wr_data; - - assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2]; - - always @(posedge clock) - sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]); - - -endmodule // ram32_2sum - diff --git a/fpga/usrp2/sdr_lib/hb_dec.v b/fpga/usrp2/sdr_lib/hb_dec.v deleted file mode 100644 index 8d21c21c0..000000000 --- a/fpga/usrp2/sdr_lib/hb_dec.v +++ /dev/null @@ -1,189 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// Final halfband decimator -// Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A] -// Strobe in cannot come faster than every 2nd clock cycle -// These taps designed by halfgen4 from ldoolittle -// myfilt = round(2^18 * halfgen4(.7/4,8)) - -module hb_dec - #(parameter WIDTH=24) - (input clk, - input rst, - input bypass, - input run, - input [8:0] cpi, // Clocks per input -- equal to the decimation ratio ahead of this block - input stb_in, - input [WIDTH-1:0] data_in, - output reg stb_out, - output reg [WIDTH-1:0] data_out); - - localparam INTWIDTH = 17; - localparam ACCWIDTH = WIDTH + 3; - - // Round off inputs to 17 bits because of 18 bit multipliers - wire [INTWIDTH-1:0] data_rnd; - wire stb_rnd; - - round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(INTWIDTH)) round_in - (.clk(clk),.reset(rst),.in(data_in),.strobe_in(stb_in),.out(data_rnd),.strobe_out(stb_rnd)); - - // Control - reg [3:0] addr_odd_a, addr_odd_b, addr_odd_c, addr_odd_d; - wire write_odd, write_even, do_mult; - reg odd; - reg [2:0] phase, phase_d1; - reg stb_out_int; - wire clear, do_acc; - assign do_mult = 1; - - always @(posedge clk) - if(rst | ~run) - odd <= 0; - else if(stb_rnd) - odd <= ~odd; - - assign write_odd = stb_rnd & odd; - assign write_even = stb_rnd & ~odd; - - always @(posedge clk) - if(rst | ~run) - phase <= 0; - else if(stb_rnd & odd) - phase <= 1; - else if(phase == 4) - phase <= 0; - else if(phase != 0) - phase <= phase + 1; - - always @(posedge clk) - phase_d1 <= phase; - - reg [15:0] stb_out_pre; - always @(posedge clk) - if(rst) - stb_out_pre <= 0; - else - stb_out_pre <= {stb_out_pre[14:0],(stb_rnd & odd)}; - - always @* - case(phase) - 1 : begin addr_odd_a = 0; addr_odd_b = 15; end - 2 : begin addr_odd_a = 1; addr_odd_b = 14; end - 3 : begin addr_odd_a = 2; addr_odd_b = 13; end - 4 : begin addr_odd_a = 3; addr_odd_b = 12; end - default : begin addr_odd_a = 0; addr_odd_b = 15; end - endcase // case(phase) - - always @* - case(phase) - 1 : begin addr_odd_c = 4; addr_odd_d = 11; end - 2 : begin addr_odd_c = 5; addr_odd_d = 10; end - 3 : begin addr_odd_c = 6; addr_odd_d = 9; end - 4 : begin addr_odd_c = 7; addr_odd_d = 8; end - default : begin addr_odd_c = 4; addr_odd_d = 11; end - endcase // case(phase) - - assign do_acc = |stb_out_pre[6:3]; - assign clear = stb_out_pre[3]; - - // Data - wire [INTWIDTH-1:0] data_odd_a, data_odd_b, data_odd_c, data_odd_d; - reg [INTWIDTH:0] sum1, sum2; // these are 18-bit inputs to mult - reg [WIDTH:0] final_sum; - wire [WIDTH-1:0] final_sum_clip; - reg [17:0] coeff1, coeff2; - wire [35:0] prod1, prod2; - - always @* // Outer coeffs - case(phase_d1) - 1 : coeff1 = -107; - 2 : coeff1 = 445; - 3 : coeff1 = -1271; - 4 : coeff1 = 2959; - default : coeff1 = -107; - endcase // case(phase) - - always @* // Inner coeffs - case(phase_d1) - 1 : coeff2 = -6107; - 2 : coeff2 = 11953; - 3 : coeff2 = -24706; - 4 : coeff2 = 82359; - default : coeff2 = -6107; - endcase // case(phase) - - srl #(.WIDTH(INTWIDTH)) srl_odd_a - (.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_a),.out(data_odd_a)); - srl #(.WIDTH(INTWIDTH)) srl_odd_b - (.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_b),.out(data_odd_b)); - srl #(.WIDTH(INTWIDTH)) srl_odd_c - (.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_c),.out(data_odd_c)); - srl #(.WIDTH(INTWIDTH)) srl_odd_d - (.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_d),.out(data_odd_d)); - - always @(posedge clk) sum1 <= {data_odd_a[INTWIDTH-1],data_odd_a} + {data_odd_b[INTWIDTH-1],data_odd_b}; - always @(posedge clk) sum2 <= {data_odd_c[INTWIDTH-1],data_odd_c} + {data_odd_d[INTWIDTH-1],data_odd_d}; - - wire [INTWIDTH-1:0] data_even; - reg [3:0] addr_even; - - always @(posedge clk) - case(cpi) - // 1 is an error - 2 : addr_even <= 9; // Maximum speed (overall decim by 4) - 3, 4, 5, 6, 7 : addr_even <= 8; - default : addr_even <= 7; - endcase // case(cpi) - - srl #(.WIDTH(INTWIDTH)) srl_even - (.clk(clk),.write(write_even),.in(data_rnd),.addr(addr_even),.out(data_even)); - - MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1), .B(sum1) ); - MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2), .B(sum2) ); - - reg [35:0] sum_of_prod; - always @(posedge clk) sum_of_prod <= prod1 + prod2; // Can't overflow - - wire [ACCWIDTH-1:0] acc_out; - acc #(.IWIDTH(ACCWIDTH-2),.OWIDTH(ACCWIDTH)) - acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod[35:38-ACCWIDTH]),.out(acc_out)); - - wire [ACCWIDTH-1:0] data_even_signext; - - localparam SHIFT_FACTOR = 6; - - sign_extend #(.bits_in(INTWIDTH),.bits_out(ACCWIDTH-SHIFT_FACTOR)) signext_data_even - (.in(data_even),.out(data_even_signext[ACCWIDTH-1:SHIFT_FACTOR])); - assign data_even_signext[SHIFT_FACTOR-1:0] = 0; - - always @(posedge clk) final_sum <= acc_out + data_even_signext; - - clip #(.bits_in(WIDTH+1), .bits_out(WIDTH)) clip (.in(final_sum), .out(final_sum_clip)); - - // Output MUX to allow for bypass - wire selected_stb = bypass ? stb_in : stb_out_pre[8]; - - always @(posedge clk) - begin - stb_out <= selected_stb; - if(selected_stb) - data_out <= bypass ? data_in : final_sum_clip; - end - -endmodule // hb_dec diff --git a/fpga/usrp2/sdr_lib/hb_dec_tb.v b/fpga/usrp2/sdr_lib/hb_dec_tb.v deleted file mode 100644 index 153cfba76..000000000 --- a/fpga/usrp2/sdr_lib/hb_dec_tb.v +++ /dev/null @@ -1,157 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module hb_dec_tb( ) ; - - // Parameters for instantiation - parameter clocks = 9'd12 ; // Number of clocks per input - parameter decim = 1 ; // Sets the filter to decimate - parameter rate = 2 ; // Sets the decimation rate - - reg clock ; - reg reset ; - reg enable ; - reg strobe_in ; - reg signed [23:0] data_in ; - wire strobe_out ; - wire signed [23:0] data_out ; - - initial - begin - $dumpfile("hb_dec_tb.vcd"); - $dumpvars(0,hb_dec_tb); - end - - // Setup the clock - initial clock = 1'b0 ; - always #5 clock <= ~clock ; - - // Come out of reset after a while - initial reset = 1'b1 ; - initial #1000 reset = 1'b0 ; - - // Enable the entire system - initial enable = 1'b1 ; - - // Instantiate UUT - /* - halfband_ideal - #( - .decim ( decim ), - .rate ( rate ) - ) uut( - .clock ( clock ), - .reset ( reset ), - .enable ( enable ), - .strobe_in ( strobe_in ), - .data_in ( data_in ), - .strobe_out ( strobe_out ), - .data_out ( data_out ) - ) ; - */ - - - hb_dec #(.WIDTH(24)) uut - (.clk(clock),.rst(reset),.bypass(0),.run(1),.cpi(clocks),.stb_in(strobe_in),.data_in(data_in), - .stb_out(strobe_out),.data_out(data_out) ); - - integer i, ri, ro, infile, outfile ; - - always @(posedge clock) - begin - if(strobe_out) - $display(data_out); - end - - // Setup file IO - initial begin - infile = $fopen("input.dat","r") ; - outfile = $fopen("output.dat","r") ; - $timeformat(-9, 2, " ns", 10) ; - end - - reg endofsim ; - reg signed [17:0] compare ; - integer noe ; - initial noe = 0 ; - - initial begin - // Initialize inputs - strobe_in <= 1'd0 ; - data_in <= 18'd0 ; - - // Wait for reset to go away - @(negedge reset) #0 ; - - // While we're still simulating ... - while( !endofsim ) begin - - // Write the input from the file or 0 if EOF... - @( posedge clock ) begin - //#1 ; - strobe_in <= 1'b1 ; - if( !$feof(infile) ) - ri = $fscanf( infile, "%d", data_in ) ; - else - data_in <= 18'd0 ; - end - - // Clocked in - set the strobe to 0 if the number of - // clocks per sample is greater than 1 - if( clocks > 1 ) begin - @(posedge clock) begin - strobe_in <= 1'b0 ; - end - - // Wait for the specified number of cycles - for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin - @(posedge clock) #1 ; - end - end - end - - // Print out the number of errors that occured - if( noe ) - $display( "FAILED: %d errors during simulation", noe ) ; - else - $display( "PASSED: Simulation successful" ) ; - - $finish ; - end - - // Output comparison of simulated values versus known good values - always @ (posedge clock) begin - if( reset ) - endofsim <= 1'b0 ; - else begin - if( !$feof(outfile) ) begin - if( strobe_out ) begin - ro = $fscanf( outfile, "%d\n", compare ) ; - if( compare != data_out ) begin - //$display( "%t: %d != %d", $realtime, data_out, compare ) ; - noe = noe + 1 ; - end - end - end else begin - // Signal end of simulation when no more outputs - endofsim <= 1'b1 ; - end - end - end - -endmodule // hb_dec_tb - diff --git a/fpga/usrp2/sdr_lib/hb_interp.v b/fpga/usrp2/sdr_lib/hb_interp.v deleted file mode 100644 index deb4fe056..000000000 --- a/fpga/usrp2/sdr_lib/hb_interp.v +++ /dev/null @@ -1,174 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// First halfband iterpolator -// Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A] -// Strobe in cannot come faster than every 4th clock cycle, -// Strobe out cannot come faster than every 2nd clock cycle - -// These taps designed by halfgen4 from ldoolittle -// myfilt = round(2^18 * halfgen4(.7/4,8)) - -module hb_interp - #(parameter IWIDTH=18, OWIDTH=18, ACCWIDTH=24) - (input clk, - input rst, - input bypass, - input [7:0] cpo, // Clocks per output, must be at least 2 - input stb_in, - input [IWIDTH-1:0] data_in, - input stb_out, - output reg [OWIDTH-1:0] data_out); - - localparam MWIDTH = ACCWIDTH-2; - localparam CWIDTH = 18; - - reg [CWIDTH-1:0] coeff1, coeff2; - reg [3:0] addr_a, addr_b, addr_c, addr_d, addr_e; - wire [IWIDTH-1:0] data_a, data_b, data_c, data_d, data_e, sum1, sum2; - wire [35:0] prod1, prod2; - - reg [2:0] phase, phase_d1, phase_d2, phase_d3, phase_d4, phase_d5; - - always @(posedge clk) - if(rst) - phase <= 0; - else - if(stb_in) - phase <= 1; - else if(phase==4) - phase <= 0; - else if(phase!=0) - phase <= phase + 1; - always @(posedge clk) phase_d1 <= phase; - always @(posedge clk) phase_d2 <= phase_d1; - always @(posedge clk) phase_d3 <= phase_d2; - always @(posedge clk) phase_d4 <= phase_d3; - always @(posedge clk) phase_d5 <= phase_d4; - - srl #(.WIDTH(IWIDTH)) srl_a - (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_a),.out(data_a)); - srl #(.WIDTH(IWIDTH)) srl_b - (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_b),.out(data_b)); - srl #(.WIDTH(IWIDTH)) srl_c - (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_c),.out(data_c)); - srl #(.WIDTH(IWIDTH)) srl_d - (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_d),.out(data_d)); - srl #(.WIDTH(IWIDTH)) srl_e - (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_e),.out(data_e)); - - always @* - case(phase) - 1 : begin addr_a = 0; addr_b = 15; end - 2 : begin addr_a = 1; addr_b = 14; end - 3 : begin addr_a = 2; addr_b = 13; end - 4 : begin addr_a = 3; addr_b = 12; end - default : begin addr_a = 0; addr_b = 15; end - endcase // case(phase) - - always @* - case(phase) - 1 : begin addr_c = 4; addr_d = 11; end - 2 : begin addr_c = 5; addr_d = 10; end - 3 : begin addr_c = 6; addr_d = 9; end - 4 : begin addr_c = 7; addr_d = 8; end - default : begin addr_c = 4; addr_d = 11; end - endcase // case(phase) - - always @* - case(cpo) - 2 : addr_e <= 9; - 3,4,5,6,7,8 : addr_e <= 8; - default : addr_e <= 7; // This case works for 256, which = 0 due to overflow outside this block - endcase // case(cpo) - - always @* // Outer coeffs - case(phase_d1) - 1 : coeff1 = -107; - 2 : coeff1 = 445; - 3 : coeff1 = -1271; - 4 : coeff1 = 2959; - default : coeff1 = -107; - endcase // case(phase) - - always @* // Inner coeffs - case(phase_d1) - 1 : coeff2 = -6107; - 2 : coeff2 = 11953; - 3 : coeff2 = -24706; - 4 : coeff2 = 82359; - default : coeff2 = -6107; - endcase // case(phase) - - add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add1 (.clk(clk),.in1(data_a),.in2(data_b),.sum(sum1)); - add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add2 (.clk(clk),.in1(data_c),.in2(data_d),.sum(sum2)); - // sum1, sum2 available on phase_d1 - - wire do_mult = 1; - MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1), .B(sum1) ); - MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2), .B(sum2) ); - // prod1, prod2 available on phase_d2 - - wire [MWIDTH-1:0] sum_of_prod; - - add2_and_round_reg #(.WIDTH(MWIDTH)) - add3 (.clk(clk),.in1(prod1[35:36-MWIDTH]),.in2(prod2[35:36-MWIDTH]),.sum(sum_of_prod)); - // sum_of_prod available on phase_d3 - - wire [ACCWIDTH-1:0] acc_out; - wire [OWIDTH-1:0] acc_round; - - wire clear = (phase_d3 == 1); - wire do_acc = (phase_d3 != 0); - - acc #(.IWIDTH(MWIDTH),.OWIDTH(ACCWIDTH)) - acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod),.out(acc_out)); - // acc_out available on phase_d4 - - wire [ACCWIDTH-6:0] clipped_acc; - clip #(.bits_in(ACCWIDTH),.bits_out(ACCWIDTH-5)) final_clip(.in(acc_out),.out(clipped_acc)); - - reg [ACCWIDTH-6:0] clipped_reg; - always @(posedge clk) - if(phase_d4 == 4) - clipped_reg <= clipped_acc; - // clipped_reg available on phase_d5 - - wire [OWIDTH-1:0] data_out_round; - round #(.bits_in(ACCWIDTH-5),.bits_out(OWIDTH)) final_round (.in(clipped_reg),.out(data_out_round)); - - reg odd; - always @(posedge clk) - if(rst) - odd <= 0; - else if(stb_in) - odd <= 0; - else if(stb_out) - odd <= 1; - - always @(posedge clk) - if(bypass) - data_out <= data_in; - else if(stb_out) - if(odd) - data_out <= data_e; - else - data_out <= data_out_round; - - // data_out available on phase_d6 - -endmodule // hb_interp diff --git a/fpga/usrp2/sdr_lib/hb_interp_tb.v b/fpga/usrp2/sdr_lib/hb_interp_tb.v deleted file mode 100644 index 239412155..000000000 --- a/fpga/usrp2/sdr_lib/hb_interp_tb.v +++ /dev/null @@ -1,149 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module hb_interp_tb( ) ; - - // Parameters for instantiation - parameter clocks = 8'd2 ; // Number of clocks per output - parameter decim = 1 ; // Sets the filter to decimate - parameter rate = 2 ; // Sets the decimation rate - - reg clock ; - reg reset ; - reg enable ; - wire strobe_in ; - reg signed [17:0] data_in ; - wire strobe_out ; - wire signed [17:0] data_out ; - - initial - begin - $dumpfile("hb_interp_tb.vcd"); - $dumpvars(0,hb_interp_tb); - end - - // Setup the clock - initial clock = 1'b0 ; - always #5 clock <= ~clock ; - - // Come out of reset after a while - initial reset = 1'b1 ; - initial #1000 reset = 1'b0 ; - - always @(posedge clock) - enable <= ~reset; - - // Instantiate UUT - /* - halfband_ideal - #( - .decim ( decim ), - .rate ( rate ) - ) uut( - .clock ( clock ), - .reset ( reset ), - .enable ( enable ), - .strobe_in ( strobe_in ), - .data_in ( data_in ), - .strobe_out ( strobe_out ), - .data_out ( data_out ) - ) ; - */ - - cic_strober #(.WIDTH(8)) - out_strober(.clock(clock),.reset(reset),.enable(enable),.rate(clocks), - .strobe_fast(1),.strobe_slow(strobe_out) ); - - cic_strober #(.WIDTH(8)) - in_strober(.clock(clock),.reset(reset),.enable(enable),.rate(2), - .strobe_fast(strobe_out),.strobe_slow(strobe_in) ); - - hb_interp #() uut - (.clk(clock),.rst(reset),.bypass(0),.cpo(clocks),.stb_in(strobe_in),.data_in(data_in), - .stb_out(strobe_out),/* .output_rate(clocks), */ .data_out(data_out) ); - - integer i, ri, ro, infile, outfile ; - - always @(posedge clock) - begin - if(strobe_out) - $display(data_out); - end - - // Setup file IO - initial begin - infile = $fopen("input.dat","r") ; - outfile = $fopen("output.dat","r") ; - $timeformat(-9, 2, " ns", 10) ; - end - - reg endofsim ; - reg signed [17:0] compare ; - integer noe ; - initial noe = 0 ; - - initial begin - // Initialize inputs - data_in <= 18'd0 ; - - // Wait for reset to go away - @(negedge reset) #0 ; - - // While we're still simulating ... - while( !endofsim ) begin - - // Write the input from the file or 0 if EOF... - @( negedge clock ) begin - if(strobe_in) - if( !$feof(infile) ) - ri <= #1 $fscanf( infile, "%d", data_in ) ; - else - data_in <= 18'd0 ; - end - end - - // Print out the number of errors that occured - if( noe ) - $display( "FAILED: %d errors during simulation", noe ) ; - else - $display( "PASSED: Simulation successful" ) ; - - $finish ; - end - - // Output comparison of simulated values versus known good values - always @ (posedge clock) begin - if( reset ) - endofsim <= 1'b0 ; - else begin - if( !$feof(outfile) ) begin - if( strobe_out ) begin - ro = $fscanf( outfile, "%d\n", compare ) ; - if( compare != data_out ) begin - //$display( "%t: %d != %d", $realtime, data_out, compare ) ; - noe = noe + 1 ; - end - end - end else begin - // Signal end of simulation when no more outputs - if($feof(infile)) - endofsim <= 1'b1 ; - end - end - end - -endmodule // small_hb_int_tb diff --git a/fpga/usrp2/sdr_lib/hb_tb.v b/fpga/usrp2/sdr_lib/hb_tb.v deleted file mode 100644 index 3260ac738..000000000 --- a/fpga/usrp2/sdr_lib/hb_tb.v +++ /dev/null @@ -1,172 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module hb_tb(); - - localparam SWIDTH = 17; - localparam CWIDTH = 18; - localparam TWIDTH = 20; - localparam ACC_WIDTH = 40; - - reg clk = 0, rst = 1; - wire strobe_in, strobe_out; - reg [SWIDTH-1:0] sample_in; - wire signed [SWIDTH:0] sample_out; - - reg set_stb; - reg [7:0] set_addr; - reg [31:0] set_data; - - localparam DECIM = 3; - - initial $dumpfile("hb_tb.vcd"); - initial $dumpvars(0,hb_tb); - - always #5 clk <= ~clk; - initial - begin - @(posedge clk); - @(negedge clk); - rst <= 0; - end - - reg [7:0] stb_counter; - always @(posedge clk) - if(rst) - stb_counter <= 0; - else - if(stb_counter == 0) - stb_counter <= DECIM; - else - stb_counter <= stb_counter - 1; - assign strobe_in = (stb_counter == 0); - - hb_decim #(.SWIDTH(SWIDTH),.CWIDTH(CWIDTH), - .TWIDTH(TWIDTH),.ACC_WIDTH(ACC_WIDTH)) hb_decim - (.clk(clk), .rst(rst), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .sample_in(sample_in), - .strobe_in(strobe_in), - .sample_out(sample_out), - .strobe_out(strobe_out) - ); - - initial - begin : load_coeffs - @(negedge rst); - @(posedge clk); - set_addr <= 124; // load coeffs - set_stb <= 1; - set_data <= -18'd49; - @(posedge clk); - set_data <= 18'd165; - @(posedge clk); - set_data <= -18'd412; - @(posedge clk); - set_data <= 18'd873; - @(posedge clk); - set_data <= -18'd1681; - @(posedge clk); - set_data <= 18'd3135; - @(posedge clk); - set_data <= -18'd6282; - @(posedge clk); - set_data <= 18'd20628; - @(posedge clk); - set_addr <=125; // load table - // { stb_out, accum, load_accum, done, even_addr, odd_addr_a, odd_addr_b, coeff_addr } - set_data <= {1'b1,1'b1,1'b0,1'b1,4'd15,4'd15,4'd0,4'd0}; // Phase 8 - @(posedge clk); - set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd14,4'd1,4'd1}; // Phase 7 - @(posedge clk); - set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd13,4'd2,4'd2}; // Phase 6 - @(posedge clk); - set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd12,4'd3,4'd3}; // Phase 5 - @(posedge clk); - set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd11,4'd4,4'd4}; // Phase 4 - @(posedge clk); - set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd10,4'd5,4'd5}; // Phase 3 - @(posedge clk); - set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd9,4'd6,4'd6}; // Phase 2 - @(posedge clk); - set_data <= {1'b0,1'b0,1'b1,1'b0,4'd15,4'd8,4'd7,4'd7}; // Phase 1 - @(posedge clk); - set_data <= {1'b0,1'b0,1'b0,1'b0,4'd15,4'd8,4'd7,4'd7}; // Phase 0 - @(posedge clk); - set_stb <= 0; - end // block: load_coeffs - - initial - begin - sample_in <= 0; - repeat(40) - @(posedge strobe_in); - $display("EVEN"); - sample_in <= 0; - repeat(10) - @(posedge strobe_in); - sample_in <= 1; - @(posedge strobe_in); - sample_in <= 0; - repeat(40) - @(posedge strobe_in); - sample_in <= 1; - repeat(40) - @(posedge strobe_in); - sample_in <= 0; - repeat(60) - @(posedge strobe_in); - sample_in <= 1; - repeat(2) - @(posedge strobe_in); - sample_in <= 0; - repeat(60) - @(posedge strobe_in); - $display("ODD"); - sample_in <= 0; - repeat(10) - @(posedge strobe_in); - sample_in <= 1; - @(posedge strobe_in); - sample_in <= 0; - repeat(40) - @(posedge strobe_in); - sample_in <= 1; - repeat(40) - @(posedge strobe_in); - sample_in <= 0; - repeat(60) - @(posedge strobe_in); - sample_in <= 1; - repeat(2) - @(posedge strobe_in); - sample_in <= 0; - repeat(60) - @(posedge strobe_in); - $finish; - end - - always @(posedge clk) - if(strobe_in) - $display(sample_in); - - always @(posedge clk) - if(strobe_out) - $display("\t",sample_out); - -endmodule // hb_tb diff --git a/fpga/usrp2/sdr_lib/input.dat b/fpga/usrp2/sdr_lib/input.dat deleted file mode 100644 index 85b5887e8..000000000 --- a/fpga/usrp2/sdr_lib/input.dat +++ /dev/null @@ -1,171 +0,0 @@ -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -8388607 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -8388607 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -8388607 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 - diff --git a/fpga/usrp2/sdr_lib/integrate.v b/fpga/usrp2/sdr_lib/integrate.v deleted file mode 100644 index ce674d470..000000000 --- a/fpga/usrp2/sdr_lib/integrate.v +++ /dev/null @@ -1,55 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module integrate - #(parameter INPUTW = 16, - parameter ACCUMW = 32, - parameter OUTPUTW = 16) - - (input clk_i, - input rst_i, - input ena_i, - - input dump_i, - input [INPUTW-1:0] data_i, - - output reg stb_o, - output reg [OUTPUTW-1:0] integ_o - ); - - wire [ACCUMW-1:0] data_ext = {{ACCUMW-INPUTW{data_i[INPUTW-1]}},data_i}; - reg [ACCUMW-1:0] accum; - - always @(posedge clk_i) - if (rst_i | ~ena_i) - begin - accum <= 0; - integ_o <= 0; - end - else - if (dump_i) - begin - integ_o <= accum[ACCUMW-1:ACCUMW-OUTPUTW]; - accum <= data_ext; - end - else - accum <= accum + data_ext; - - always @(posedge clk_i) - stb_o <= dump_i; - -endmodule // integrate diff --git a/fpga/usrp2/sdr_lib/med_hb_int.v b/fpga/usrp2/sdr_lib/med_hb_int.v deleted file mode 100644 index f619dc81b..000000000 --- a/fpga/usrp2/sdr_lib/med_hb_int.v +++ /dev/null @@ -1,112 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// Medium halfband decimator (intended to be followed by another stage) -// Implements impulse responses of the form [A 0 B 0 C 0 D 0.5 D 0 C 0 B 0 A] -// -// These taps designed by halfgen_test: -// 2 * 131072 * halfgen_test(.8/8,4,1) -// -597, 0, 4283, 0, -17516, 0, 79365, 131072, 79365, 0, -17516, 0, 4283, 0, -597 - - -module med_hb_int - #(parameter WIDTH=18) - (input clk, - input rst, - input bypass, - input stb_in, - input [WIDTH-1:0] data_in, - input [7:0] output_rate, - input stb_out, - output reg [WIDTH-1:0] data_out); - - localparam coeff_a = -597; - localparam coeff_b = 4283; - localparam coeff_c = -17516; - localparam coeff_d = 79365; - - reg phase; - reg [WIDTH-1:0] d1, d2, d3, d4, d5, d6, d7, d8; - - localparam MWIDTH = 36; - wire [MWIDTH-1:0] prod; - - reg [6:0] stbin_d; - - always @(posedge clk) - stbin_d <= {stbin_d[5:0],stb_in}; - - always @(posedge clk) - if(stb_in) - begin - d1 <= data_in; - d2 <= d1; - d3 <= d2; - d4 <= d3; - d5 <= d4; - d6 <= d5; - d7 <= d6; - d8 <= d7; - end - - wire [WIDTH-1:0] sum_a, sum_b, sum_c, sum_d; - add2_and_round_reg #(.WIDTH(WIDTH)) add_a (.clk(clk),.in1(d1),.in2(d8),.sum(sum_a)); - add2_and_round_reg #(.WIDTH(WIDTH)) add_b (.clk(clk),.in1(d2),.in2(d7),.sum(sum_b)); - add2_and_round_reg #(.WIDTH(WIDTH)) add_c (.clk(clk),.in1(d3),.in2(d6),.sum(sum_c)); - add2_and_round_reg #(.WIDTH(WIDTH)) add_d (.clk(clk),.in1(d4),.in2(d5),.sum(sum_d)); - - MULT18X18S mult1(.C(clk), .CE(1), .R(rst), .P(prod1), .A(stbin_d[1] ? coeff_a : coeff_b), - .B(stbin_d[1] ? sum_a : sum_b) ); - MULT18X18S mult2(.C(clk), .CE(1), .R(rst), .P(prod2), .A(stbin_d[1] ? coeff_c : coeff_d), - .B(stbin_d[1] ? sum_c : sum_d) ); - - wire [MWIDTH:0] accum; - acc #(.IWIDTH(MWIDTH),.OWIDTH(MWIDTH+1)) - acc (.clk(clk),.clear(stbin_d[2]),.acc(|stbin_d[3:2]),.in(prod),.out(accum)); - - wire [WIDTH+2:0] accum_rnd; - round_reg #(.bits_in(MWIDTH+1),.bits_out(WIDTH+3)) - final_round (.clk(clk),.in(accum),.out(accum_rnd)); - - wire [WIDTH-1:0] clipped; - clip_reg #(.bits_in(WIDTH+3),.bits_out(WIDTH)) - final_clip (.clk(clk),.in(accum_rnd),.out(clipped)); - - reg [WIDTH-1:0] saved, saved_d3; - always @(posedge clk) - if(stbin_d[6]) - saved <= clipped; - - always @(posedge clk) - if(stbin_d[3]) - saved_d3 <= d3; - - always @(posedge clk) - if(bypass) - data_out <= data_in; - else if(stb_in & stb_out) - case(output_rate) - 1 : data_out <= d6; - 2 : data_out <= d4; - 3, 4, 5, 6, 7 : data_out <= d3; - default : data_out <= d2; - endcase // case(output_rate) - else if(stb_out) - data_out <= saved; - -endmodule // small_hb_int - diff --git a/fpga/usrp2/sdr_lib/output.dat b/fpga/usrp2/sdr_lib/output.dat deleted file mode 100644 index 15db3ced4..000000000 --- a/fpga/usrp2/sdr_lib/output.dat +++ /dev/null @@ -1,130 +0,0 @@ --1390 -0 -1604 -0 --1896 -0 -2317 -0 --2979 -0 -4172 -0 --6953 -0 -20860 -32768 -20860 -0 --6953 -0 -4172 -0 --2979 -0 -2317 -0 --1896 -0 -1604 -0 --1390 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 - diff --git a/fpga/usrp2/sdr_lib/pipectrl.v b/fpga/usrp2/sdr_lib/pipectrl.v deleted file mode 100644 index 85d0ce04f..000000000 --- a/fpga/usrp2/sdr_lib/pipectrl.v +++ /dev/null @@ -1,66 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// Control DSP pipeline with 1 cycle per stage. Minimum 2 stages or this won't work -module pipectrl - #(parameter STAGES = 2, - parameter TAGWIDTH = 1) - (input clk, - input reset, - input src_rdy_i, - output dst_rdy_o, - output src_rdy_o, - input dst_rdy_i, - output [STAGES-1:0] strobes, - output [STAGES-1:0] valids, - input [TAGWIDTH-1:0] tag_i, - output [TAGWIDTH-1:0] tag_o); - - wire new_input = src_rdy_i & dst_rdy_o; - wire new_output = src_rdy_o & dst_rdy_i; - wire [TAGWIDTH-1:0] tags [STAGES-1:0]; - - assign dst_rdy_o = ~valids[0] | strobes[1]; - - pipestage #(.TAGWIDTH(TAGWIDTH)) head - (.clk(clk),.reset(reset), .stb_in(strobes[0]), .stb_out(strobes[1]),.valid(valids[0]), - .tag_in(tag_i), .tag_out(tags[0])); - assign strobes[0] = src_rdy_i & (~valids[0] | strobes[1]); - - genvar i; - generate - for(i = 1; i < STAGES - 1; i = i + 1) - begin : gen_stages - pipestage #(.TAGWIDTH(TAGWIDTH)) pipestage - (.clk(clk),.reset(reset), .stb_in(strobes[i]),.stb_out(strobes[i+1]),.valid(valids[i]), - .tag_in(tags[i-1]),.tag_out(tags[i])); - assign strobes[i] = valids[i-1] & (~valids[i] | strobes[i+1]); - end - endgenerate - - pipestage #(.TAGWIDTH(TAGWIDTH)) tail - (.clk(clk),.reset(reset), .stb_in(strobes[STAGES-1]), .stb_out(dst_rdy_i),.valid(valids[STAGES-1]), - .tag_in(tags[STAGES-2]), .tag_out(tags[STAGES-1])); - assign strobes[STAGES-1] = valids[STAGES-2] & (~valids[STAGES-1] | new_output); - - assign src_rdy_o = valids[STAGES-1]; - - assign tag_o = tags[STAGES-1]; - -endmodule // pipectrl - - diff --git a/fpga/usrp2/sdr_lib/pipestage.v b/fpga/usrp2/sdr_lib/pipestage.v deleted file mode 100644 index 011afb1ba..000000000 --- a/fpga/usrp2/sdr_lib/pipestage.v +++ /dev/null @@ -1,45 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module pipestage - #(parameter TAGWIDTH = 1) - (input clk, - input reset, - input stb_in, - input stb_out, - output reg valid, - input [TAGWIDTH-1:0] tag_in, - output reg [TAGWIDTH-1:0] tag_out); - - always @(posedge clk) - if(reset) - begin - valid <= 0; - tag_out <= 0; - end - else if(stb_in) - begin - valid <= 1; - tag_out <= tag_in; - end - else if(stb_out) - begin - valid <= 0; - tag_out <= 0; - end - -endmodule // pipestage diff --git a/fpga/usrp2/sdr_lib/round.v b/fpga/usrp2/sdr_lib/round.v deleted file mode 100644 index 26d5a4cf4..000000000 --- a/fpga/usrp2/sdr_lib/round.v +++ /dev/null @@ -1,59 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2011 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Rounding "macro" -// Keeps the topmost bits, does proper 2s comp round to zero (unbiased truncation) - -module round - #(parameter bits_in=0, - parameter bits_out=0, - parameter round_to_zero=0, // original behavior - parameter round_to_nearest=1, // lowest noise - parameter trunc=0) // round to negative infinity - (input [bits_in-1:0] in, - output [bits_out-1:0] out, - output [bits_in-bits_out:0] err); - - wire round_corr,round_corr_trunc,round_corr_rtz,round_corr_nearest,round_corr_nearest_safe; - - assign round_corr_trunc = 0; - assign round_corr_rtz = (in[bits_in-1] & |in[bits_in-bits_out-1:0]); - assign round_corr_nearest = in[bits_in-bits_out-1]; - - generate - if(bits_in-bits_out > 1) - assign round_corr_nearest_safe = (~in[bits_in-1] & (&in[bits_in-2:bits_out])) ? 0 : - round_corr_nearest; - else - assign round_corr_nearest_safe = round_corr_nearest; - endgenerate - - - assign round_corr = round_to_nearest ? round_corr_nearest_safe : - trunc ? round_corr_trunc : - round_to_zero ? round_corr_rtz : - 0; // default to trunc - - assign out = in[bits_in-1:bits_in-bits_out] + round_corr; - - assign err = in - {out,{(bits_in-bits_out){1'b0}}}; - -endmodule // round diff --git a/fpga/usrp2/sdr_lib/round_reg.v b/fpga/usrp2/sdr_lib/round_reg.v deleted file mode 100644 index 6f2e974d7..000000000 --- a/fpga/usrp2/sdr_lib/round_reg.v +++ /dev/null @@ -1,44 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2008 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Rounding "macro" -// Keeps the topmost bits, does proper 2s comp rounding (round-to-zero) - -module round_reg - #(parameter bits_in=0, - parameter bits_out=0) - (input clk, - input [bits_in-1:0] in, - output reg [bits_out-1:0] out, - output reg [bits_in-bits_out:0] err); - - wire [bits_out-1:0] temp; - wire [bits_in-bits_out:0] err_temp; - - round #(.bits_in(bits_in),.bits_out(bits_out)) round (.in(in),.out(temp), .err(err_temp)); - - always @(posedge clk) - out <= temp; - - always @(posedge clk) - err <= err_temp; - -endmodule // round_reg diff --git a/fpga/usrp2/sdr_lib/round_sd.v b/fpga/usrp2/sdr_lib/round_sd.v deleted file mode 100644 index 94584f6ef..000000000 --- a/fpga/usrp2/sdr_lib/round_sd.v +++ /dev/null @@ -1,23 +0,0 @@ - - -module round_sd - #(parameter WIDTH_IN=18, - parameter WIDTH_OUT=16, - parameter DISABLE_SD=0) - (input clk, input reset, - input [WIDTH_IN-1:0] in, input strobe_in, - output [WIDTH_OUT-1:0] out, output strobe_out); - - localparam ERR_WIDTH = WIDTH_IN - WIDTH_OUT + 1; - - wire [ERR_WIDTH-1:0] err; - wire [WIDTH_IN-1:0] err_ext, sum; - - sign_extend #(.bits_in(ERR_WIDTH),.bits_out(WIDTH_IN)) ext_err (.in(err), .out(err_ext)); - - add2_and_clip_reg #(.WIDTH(WIDTH_IN)) add2_and_clip_reg - (.clk(clk), .rst(reset), .in1(in), .in2((DISABLE_SD == 0) ? err_ext : 0), .strobe_in(strobe_in), .sum(sum), .strobe_out(strobe_out)); - - round #(.bits_in(WIDTH_IN),.bits_out(WIDTH_OUT)) round_sum (.in(sum), .out(out), .err(err)); - -endmodule // round_sd diff --git a/fpga/usrp2/sdr_lib/round_sd_tb.v b/fpga/usrp2/sdr_lib/round_sd_tb.v deleted file mode 100644 index 1e8e9a323..000000000 --- a/fpga/usrp2/sdr_lib/round_sd_tb.v +++ /dev/null @@ -1,58 +0,0 @@ - -module round_sd_tb(); - - reg clk, rst; - - initial rst = 1; - initial #1000 rst = 0; - initial clk = 0; - always #5 clk = ~clk; - - initial $dumpfile("round_sd_tb.vcd"); - initial $dumpvars(0,round_sd_tb); - - localparam WIDTH_IN = 8; - localparam WIDTH_OUT = 5; - - reg [WIDTH_IN-1:0] adc_in, adc_in_del; - wire [WIDTH_OUT-1:0] adc_out; - - integer factor = 1<<(WIDTH_IN-WIDTH_OUT); - - always @(posedge clk) - if(~rst) - begin - if(adc_in_del[WIDTH_IN-1]) - $write("-%d\t",-adc_in_del); - else - $write("%d\t",adc_in_del); - if(adc_out[WIDTH_OUT-1]) - $write("-%d\t",-adc_out); - else - $write("%d\t",adc_out); - $write("\n"); - - //$write("%f\t",adc_in_del/factor); - //$write("%f\n",adc_in_del/factor-adc_out); - end - - round_sd #(.WIDTH_IN(WIDTH_IN),.WIDTH_OUT(WIDTH_OUT)) - round_sd(.clk(clk),.reset(rst), .in(adc_in), .strobe_in(1'b1), .out(adc_out), .strobe_out()); - - reg [5:0] counter = 0; - - always @(posedge clk) - counter <= counter+1; - - always @(posedge clk) - adc_in_del <= adc_in; - - always @(posedge clk) - if(rst) - adc_in <= 0; - else if(counter == 63) - adc_in <= adc_in + 1; - - initial #300000 $finish; - -endmodule // longfifo_tb diff --git a/fpga/usrp2/sdr_lib/round_tb.v b/fpga/usrp2/sdr_lib/round_tb.v deleted file mode 100644 index ddc464f4a..000000000 --- a/fpga/usrp2/sdr_lib/round_tb.v +++ /dev/null @@ -1,61 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2011 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Rounding "macro" -// Keeps the topmost bits, does proper 2s comp round to zero (unbiased truncation) - -module round_tb(); - - localparam IW=8; - localparam OW=4; - localparam EW=IW-OW+1; - - reg signed [IW-1:0] in; - wire signed [OW-1:0] out; - wire signed [EW-1:0] err; - - round #(.bits_in(IW), - .bits_out(OW), - .round_to_zero(0), // original behavior - .round_to_nearest(1), // lowest noise - .trunc(0)) // round to negative infinity - round (.in(in),.out(out),.err(err)); - - initial $dumpfile("round_tb.vcd"); - initial $dumpvars(0,round_tb); - - wire signed [IW-1:0] out_round = {out,{IW-OW{1'b0}}}; - - initial - begin - in <= -129; - #1; - repeat (260) - begin - in <= in + 1; - #1; - $display("In %d, out %d, out_rnd %d, err %d, real err %d",in,out,out_round,-err,out_round-in); - #1; - end - $finish; - end - -endmodule // round diff --git a/fpga/usrp2/sdr_lib/rssi.v b/fpga/usrp2/sdr_lib/rssi.v deleted file mode 100644 index e931ff865..000000000 --- a/fpga/usrp2/sdr_lib/rssi.v +++ /dev/null @@ -1,47 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module rssi (input clock, input reset, input enable, - input [11:0] adc, output [15:0] rssi, output [15:0] over_count); - - wire over_hi = (adc == 12'h7FF); - wire over_lo = (adc == 12'h800); - wire over = over_hi | over_lo; - - reg [25:0] over_count_int; - always @(posedge clock) - if(reset | ~enable) - over_count_int <= #1 26'd0; - else - over_count_int <= #1 over_count_int + (over ? 26'd65535 : 26'd0) - over_count_int[25:10]; - - assign over_count = over_count_int[25:10]; - - wire [11:0] abs_adc = adc[11] ? ~adc : adc; - - reg [25:0] rssi_int; - always @(posedge clock) - if(reset | ~enable) - rssi_int <= #1 26'd0; - else - rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10]; - - assign rssi = rssi_int[25:10]; - -endmodule // rssi diff --git a/fpga/usrp2/sdr_lib/rx_control.v b/fpga/usrp2/sdr_lib/rx_control.v deleted file mode 100644 index 12f411ffe..000000000 --- a/fpga/usrp2/sdr_lib/rx_control.v +++ /dev/null @@ -1,197 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -`define DSP_CORE_RX_BASE 160 - -module rx_control - #(parameter FIFOSIZE = 10) - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - input [31:0] master_time, - output overrun, - - // To FIFO interface of Buffer Pool - output [31:0] wr_dat_o, - output [3:0] wr_flags_o, - input wr_ready_i, - output wr_ready_o, - - // From DSP Core - input [31:0] sample, - output run, - input strobe, - - // FIFO Levels - output [15:0] fifo_occupied, - output fifo_full, - output fifo_empty, - - // Debug - output [31:0] debug_rx - ); - - wire [31:0] new_time, new_command; - wire sc_pre1, clear_overrun; - wire [31:0] rcvtime_pre; - reg [31:0] rcvtime; - wire [8:0] lines_per_frame; - wire [20:0] numlines; - wire send_imm_pre, chain_pre; - reg send_imm, chain; - wire full_ctrl, read_ctrl, empty_ctrl, write_ctrl; - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+3)) sr_3 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(new_time),.changed(sc_pre1)); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+4)) sr_4 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(new_command),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+5)) sr_5 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_overrun)); - - reg sc_pre2; - always @(posedge clk) - sc_pre2 <= sc_pre1; - assign write_ctrl = sc_pre1 & ~sc_pre2; - - shortfifo #(.WIDTH(64)) commandfifo - (.clk(clk),.rst(rst),.clear(clear_overrun), - .datain({new_command,new_time}), .write(write_ctrl), .full(full_ctrl), - .dataout({send_imm_pre,chain_pre,numlines,lines_per_frame,rcvtime_pre}), - .read(read_ctrl), .empty(empty_ctrl) ); - - // Buffer interface to internal FIFO - wire have_space, write; - wire [35:0] fifo_line; - - // Internal FIFO, size 9 is 2K, size 10 is 4K - fifo_cascade #(.WIDTH(36),.SIZE(FIFOSIZE)) rxfifo - (.clk(clk),.reset(rst),.clear(clear_overrun), - .datain(fifo_line), .src_rdy_i(write), .dst_rdy_o(have_space), - .dataout({wr_flags_o,wr_dat_o}), .src_rdy_o(wr_ready_o), .dst_rdy_i(wr_ready_i), - .space(),.occupied(fifo_occupied) ); - assign fifo_full = ~have_space; - assign fifo_empty = ~wr_ready_o; - - // Internal FIFO to DSP interface - reg [22:0] lines_left; - reg [8:0] lines_left_frame; - localparam IBS_IDLE = 0; - localparam IBS_WAITING = 1; - localparam IBS_FIRSTLINE = 2; - localparam IBS_RUNNING = 3; - localparam IBS_OVERRUN = 4; - - reg [2:0] ibs_state; - - wire [32:0] delta_time = {1'b0,rcvtime}-{1'b0,master_time}; - wire too_late = (delta_time[32:31] == 2'b11) & ~send_imm; - wire go_now = send_imm | ( master_time == rcvtime ); - - always @(posedge clk) - if(rst) - begin - ibs_state <= IBS_IDLE; - lines_left <= 0; - lines_left_frame <= 0; - rcvtime <= 0; - send_imm <= 0; - chain <= 0; - end - else - if(clear_overrun) - begin - ibs_state <= IBS_IDLE; - lines_left <= 0; - lines_left_frame <= 0; - rcvtime <= 0; - send_imm <= 0; - chain <= 0; - end - else - case(ibs_state) - IBS_IDLE : - if(~empty_ctrl) - begin - lines_left <= numlines; - lines_left_frame <= lines_per_frame; - rcvtime <= rcvtime_pre; - ibs_state <= IBS_WAITING; - send_imm <= send_imm_pre; - chain <= chain_pre; - end - IBS_WAITING : - if(go_now) - ibs_state <= IBS_FIRSTLINE; - else if(too_late) - ibs_state <= IBS_OVERRUN; - IBS_FIRSTLINE : - if(~have_space | strobe) - ibs_state <= IBS_OVERRUN; - else - ibs_state <= IBS_RUNNING; - IBS_RUNNING : - if(strobe) - if(~have_space) - ibs_state <= IBS_OVERRUN; - else - begin - lines_left <= lines_left - 1; - if(lines_left == 1) - if(~chain) - ibs_state <= IBS_IDLE; - else if(empty_ctrl) - ibs_state <= IBS_OVERRUN; - else - begin - lines_left <= numlines; - lines_left_frame <= lines_per_frame; - rcvtime <= rcvtime_pre; - ibs_state <= IBS_FIRSTLINE; - send_imm <= send_imm_pre; - chain <= chain_pre; - end - else if(lines_left_frame == 1) - begin - lines_left_frame <= lines_per_frame; - ibs_state <= IBS_FIRSTLINE; - end - else - lines_left_frame <= lines_left_frame - 1; - end // else: !if(~have_space) - endcase // case(ibs_state) - - assign fifo_line = (ibs_state == IBS_FIRSTLINE) ? {2'b0,1'b0,1'b1,master_time} : - {2'b0,((lines_left==1)|(lines_left_frame==1)),1'b0,sample}; - - assign write = ((ibs_state == IBS_FIRSTLINE) | strobe) & have_space; // & (ibs_state == IBS_RUNNING) should strobe only when running - assign overrun = (ibs_state == IBS_OVERRUN); - assign run = (ibs_state == IBS_RUNNING) | (ibs_state == IBS_FIRSTLINE); - assign read_ctrl = ( (ibs_state == IBS_IDLE) | - ((ibs_state == IBS_RUNNING) & strobe & have_space & (lines_left==1) & chain) ) - & ~empty_ctrl; - - assign debug_rx = { 8'd0, - 1'd0, send_imm, chain, wr_ready_i,wr_ready_o, 2'b0, run, - write,have_space,wr_flags_o[1:0],write_ctrl,full_ctrl,read_ctrl,empty_ctrl, - sc_pre1, clear_overrun, go_now, too_late, overrun, ibs_state[2:0] }; -endmodule // rx_control diff --git a/fpga/usrp2/sdr_lib/rx_dcoffset.v b/fpga/usrp2/sdr_lib/rx_dcoffset.v deleted file mode 100644 index 04d7795c0..000000000 --- a/fpga/usrp2/sdr_lib/rx_dcoffset.v +++ /dev/null @@ -1,58 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module rx_dcoffset - #(parameter WIDTH=16, - parameter ADDR=8'd0, - parameter alpha_shift=20) - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - input [WIDTH-1:0] in, output [WIDTH-1:0] out); - - wire set_now = set_stb & (ADDR == set_addr); - - reg fixed; // uses fixed offset - wire [WIDTH-1:0] fixed_dco; - - localparam int_width = WIDTH + alpha_shift; - reg [int_width-1:0] integrator; - wire [WIDTH-1:0] quantized; - - always @(posedge clk) - if(rst) - begin - fixed <= 0; - integrator <= {int_width{1'b0}}; - end - else if(set_now) - begin - fixed <= set_data[31]; - if(set_data[30]) - integrator <= {set_data[29:0],{(int_width-30){1'b0}}}; - end - else if(~fixed) - integrator <= integrator + {{(alpha_shift){out[WIDTH-1]}},out}; - - round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd - (.clk(clk), .reset(rst), .in(integrator), .strobe_in(1'b1), .out(quantized), .strobe_out()); - - add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg - (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .strobe_in(1'b1), .sum(out), .strobe_out()); - -endmodule // rx_dcoffset diff --git a/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v b/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v deleted file mode 100644 index b4fb66ad7..000000000 --- a/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v +++ /dev/null @@ -1,54 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -`timescale 1ns/1ns -module rx_dcoffset_tb(); - - reg clk, rst; - - initial rst = 1; - initial #1000 rst = 0; - initial clk = 0; - always #5 clk = ~clk; - - initial $dumpfile("rx_dcoffset_tb.vcd"); - initial $dumpvars(0,rx_dcoffset_tb); - - reg [13:0] adc_in; - wire [13:0] adc_out; - - always @(posedge clk) - begin - if(adc_in[13]) - $write("-%d,",-adc_in); - else - $write("%d,",adc_in); - if(adc_out[13]) - $write("-%d\n",-adc_out); - else - $write("%d\n",adc_out); - end - - rx_dcoffset #(.WIDTH(14),.ADDR(0), .alpha_shift(8)) - rx_dcoffset(.clk(clk),.rst(rst),.set_stb(0),.set_addr(0),.set_data(0), - .in(adc_in),.out(adc_out)); - - always @(posedge clk) - adc_in <= (($random % 473) + 23)/4; - -endmodule // longfifo_tb diff --git a/fpga/usrp2/sdr_lib/rx_frontend.v b/fpga/usrp2/sdr_lib/rx_frontend.v deleted file mode 100644 index ebe19240c..000000000 --- a/fpga/usrp2/sdr_lib/rx_frontend.v +++ /dev/null @@ -1,78 +0,0 @@ - -module rx_frontend - #(parameter BASE = 0, - parameter IQCOMP_EN = 1) - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - input [15:0] adc_a, input adc_ovf_a, - input [15:0] adc_b, input adc_ovf_b, - - output [23:0] i_out, output [23:0] q_out, - input run, - output [31:0] debug - ); - - reg [15:0] adc_i, adc_q; - wire [17:0] adc_i_ofs, adc_q_ofs; - wire [35:0] corr_i, corr_q; wire [17:0] mag_corr,phase_corr; - wire swap_iq; - - setting_reg #(.my_addr(BASE), .width(1)) sr_8 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(swap_iq),.changed()); - - always @(posedge clk) - if(swap_iq) // Swap - {adc_i,adc_q} <= {adc_b,adc_a}; - else - {adc_i,adc_q} <= {adc_a,adc_b}; - - setting_reg #(.my_addr(BASE+1),.width(18)) sr_1 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(mag_corr),.changed()); - - setting_reg #(.my_addr(BASE+2),.width(18)) sr_2 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phase_corr),.changed()); - - generate - if(IQCOMP_EN == 1) - begin - rx_dcoffset #(.WIDTH(18),.ADDR(BASE+3)) rx_dcoffset_i - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .in({adc_i,2'b00}),.out(adc_i_ofs)); - - rx_dcoffset #(.WIDTH(18),.ADDR(BASE+4)) rx_dcoffset_q - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .in({adc_q,2'b00}),.out(adc_q_ofs)); - - MULT18X18S mult_mag_corr - (.P(corr_i), .A(adc_i_ofs), .B(mag_corr), .C(clk), .CE(1), .R(rst) ); - - MULT18X18S mult_phase_corr - (.P(corr_q), .A(adc_i_ofs), .B(phase_corr), .C(clk), .CE(1), .R(rst) ); - - add2_and_clip_reg #(.WIDTH(24)) add_clip_i - (.clk(clk), .rst(rst), - .in1({adc_i_ofs,6'd0}), .in2(corr_i[35:12]), .strobe_in(1'b1), - .sum(i_out), .strobe_out()); - - add2_and_clip_reg #(.WIDTH(24)) add_clip_q - (.clk(clk), .rst(rst), - .in1({adc_q_ofs,6'd0}), .in2(corr_q[35:12]), .strobe_in(1'b1), - .sum(q_out), .strobe_out()); - end // if (IQCOMP_EN == 1) - else - begin - rx_dcoffset #(.WIDTH(24),.ADDR(BASE+3)) rx_dcoffset_i - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .in({adc_i,8'b00}),.out(i_out)); - - rx_dcoffset #(.WIDTH(24),.ADDR(BASE+4)) rx_dcoffset_q - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .in({adc_q,8'b00}),.out(q_out)); - end // else: !if(IQCOMP_EN == 1) - endgenerate - -endmodule // rx_frontend diff --git a/fpga/usrp2/sdr_lib/rx_frontend_tb.v b/fpga/usrp2/sdr_lib/rx_frontend_tb.v deleted file mode 100644 index 487b72687..000000000 --- a/fpga/usrp2/sdr_lib/rx_frontend_tb.v +++ /dev/null @@ -1,45 +0,0 @@ - -`timescale 1ns/1ns -module rx_frontend_tb(); - - reg clk, rst; - - initial rst = 1; - initial #1000 rst = 0; - initial clk = 0; - always #5 clk = ~clk; - - initial $dumpfile("rx_frontend_tb.vcd"); - initial $dumpvars(0,rx_frontend_tb); - - reg [15:0] adc_in; - wire [17:0] adc_out; - - always @(posedge clk) - begin - if(adc_in[13]) - $write("-%d,",-adc_in); - else - $write("%d,",adc_in); - if(adc_out[13]) - $write("-%d\n",-adc_out); - else - $write("%d\n",adc_out); - end - - rx_frontend #(.BASE(0)) rx_frontend - (.clk(clk),.rst(rst), - .set_stb(0),.set_addr(0),.set_data(0), - .adc_a(adc_in), .adc_ovf_a(0), - .adc_b(0), .adc_ovf_b(0), - .i_out(adc_out),.q_out(), - .run(), .debug()); - - always @(posedge clk) - if(rst) - adc_in <= 0; - else - adc_in <= adc_in + 4; - //adc_in <= (($random % 473) + 23)/4; - -endmodule // rx_frontend_tb diff --git a/fpga/usrp2/sdr_lib/sign_extend.v b/fpga/usrp2/sdr_lib/sign_extend.v deleted file mode 100644 index eae67faf2..000000000 --- a/fpga/usrp2/sdr_lib/sign_extend.v +++ /dev/null @@ -1,35 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - - -// Sign extension "macro" -// bits_out should be greater than bits_in - -module sign_extend (in,out); - parameter bits_in=0; // FIXME Quartus insists on a default - parameter bits_out=0; - - input [bits_in-1:0] in; - output [bits_out-1:0] out; - - assign out = {{(bits_out-bits_in){in[bits_in-1]}},in}; - -endmodule diff --git a/fpga/usrp2/sdr_lib/small_hb_dec.v b/fpga/usrp2/sdr_lib/small_hb_dec.v deleted file mode 100644 index c05a48b81..000000000 --- a/fpga/usrp2/sdr_lib/small_hb_dec.v +++ /dev/null @@ -1,136 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// Short halfband decimator (intended to be followed by another stage) -// Implements impulse responses of the form [A 0 B 0.5 B 0 A] -// -// These taps designed by halfgen4 from ldoolittle: -// 2 * 131072 * halfgen4(.75/8,2) -module small_hb_dec - #(parameter WIDTH=18) - (input clk, - input rst, - input bypass, - input run, - input stb_in, - input [WIDTH-1:0] data_in, - output reg stb_out, - output reg [WIDTH-1:0] data_out); - - // Round off inputs to 17 bits because of 18 bit multipliers - localparam INTWIDTH = 17; - wire [INTWIDTH-1:0] data_rnd; - wire stb_rnd; - - round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(INTWIDTH)) round_in - (.clk(clk),.reset(rst),.in(data_in),.strobe_in(stb_in),.out(data_rnd),.strobe_out(stb_rnd)); - - - reg stb_rnd_d1; - reg [INTWIDTH-1:0] data_rnd_d1; - always @(posedge clk) stb_rnd_d1 <= stb_rnd; - always @(posedge clk) data_rnd_d1 <= data_rnd; - - wire go; - reg phase, go_d1, go_d2, go_d3, go_d4; - always @(posedge clk) - if(rst | ~run) - phase <= 0; - else if(stb_rnd_d1) - phase <= ~phase; - assign go = stb_rnd_d1 & phase; - always @(posedge clk) - if(rst | ~run) - begin - go_d1 <= 0; - go_d2 <= 0; - go_d3 <= 0; - go_d4 <= 0; - end - else - begin - go_d1 <= go; - go_d2 <= go_d1; - go_d3 <= go_d2; - go_d4 <= go_d3; - end - - wire [17:0] coeff_a = -10690; - wire [17:0] coeff_b = 75809; - - reg [INTWIDTH-1:0] d1, d2, d3, d4 , d5, d6; - always @(posedge clk) - if(stb_rnd_d1 | rst) - begin - d1 <= data_rnd_d1; - d2 <= d1; - d3 <= d2; - d4 <= d3; - d5 <= d4; - d6 <= d5; - end - - reg [17:0] sum_a, sum_b, middle, middle_d1; - - always @(posedge clk) - if(go) - begin - sum_a <= {data_rnd_d1[INTWIDTH-1],data_rnd_d1} + {d6[INTWIDTH-1],d6}; - sum_b <= {d2[INTWIDTH-1],d2} + {d4[INTWIDTH-1],d4}; - //middle <= {d3[INTWIDTH-1],d3}; - middle <= {d3,1'b0}; - end - - always @(posedge clk) - if(go_d1) - middle_d1 <= middle; - - wire [17:0] sum = go_d1 ? sum_b : sum_a; - wire [17:0] coeff = go_d1 ? coeff_b : coeff_a; - wire [35:0] prod; - MULT18X18S mult(.C(clk), .CE(go_d1 | go_d2), .R(rst), .P(prod), .A(coeff), .B(sum) ); - - localparam ACCWIDTH = 30; - reg [ACCWIDTH-1:0] accum; - - always @(posedge clk) - if(rst) - accum <= 0; - else if(go_d2) - accum <= {middle_d1[17],middle_d1[17],middle_d1,{(16+ACCWIDTH-36){1'b0}}} + {prod[35:36-ACCWIDTH]}; - else if(go_d3) - accum <= accum + {prod[35:36-ACCWIDTH]}; - - wire [WIDTH:0] accum_rnd; - wire [WIDTH-1:0] accum_rnd_clip; - - wire stb_round; - - round_sd #(.WIDTH_IN(ACCWIDTH),.WIDTH_OUT(WIDTH+1)) round_acc - (.clk(clk), .reset(rst), .in(accum), .strobe_in(go_d4), .out(accum_rnd), .strobe_out(stb_round)); - - clip #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip (.in(accum_rnd), .out(accum_rnd_clip)); - - // Output - always @(posedge clk) - begin - stb_out <= bypass ? stb_in : stb_round; - data_out <= bypass ? data_in : accum_rnd_clip; - end - - -endmodule // small_hb_dec diff --git a/fpga/usrp2/sdr_lib/small_hb_dec_tb.v b/fpga/usrp2/sdr_lib/small_hb_dec_tb.v deleted file mode 100644 index 1e713321a..000000000 --- a/fpga/usrp2/sdr_lib/small_hb_dec_tb.v +++ /dev/null @@ -1,157 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module hb_dec_tb( ) ; - - // Parameters for instantiation - parameter clocks = 9'd2 ; // Number of clocks per input - parameter decim = 1 ; // Sets the filter to decimate - parameter rate = 2 ; // Sets the decimation rate - - reg clock ; - reg reset ; - reg enable ; - reg strobe_in ; - reg signed [17:0] data_in ; - wire strobe_out ; - wire signed [17:0] data_out ; - - initial - begin - $dumpfile("hb_dec_tb.vcd"); - $dumpvars(0,hb_dec_tb); - end - - // Setup the clock - initial clock = 1'b0 ; - always #5 clock <= ~clock ; - - // Come out of reset after a while - initial reset = 1'b1 ; - initial #1000 reset = 1'b0 ; - - // Enable the entire system - initial enable = 1'b1 ; - - // Instantiate UUT - /* - halfband_ideal - #( - .decim ( decim ), - .rate ( rate ) - ) uut( - .clock ( clock ), - .reset ( reset ), - .enable ( enable ), - .strobe_in ( strobe_in ), - .data_in ( data_in ), - .strobe_out ( strobe_out ), - .data_out ( data_out ) - ) ; - */ - - - small_hb_dec #(.WIDTH(18)) uut - (.clk(clock),.rst(reset),.bypass(0),.stb_in(strobe_in),.data_in(data_in), - .stb_out(strobe_out),.data_out(data_out) ); - - integer i, ri, ro, infile, outfile ; - - always @(posedge clock) - begin - if(strobe_out) - $display(data_out); - end - - // Setup file IO - initial begin - infile = $fopen("input.dat","r") ; - outfile = $fopen("output.dat","r") ; - $timeformat(-9, 2, " ns", 10) ; - end - - reg endofsim ; - reg signed [17:0] compare ; - integer noe ; - initial noe = 0 ; - - initial begin - // Initialize inputs - strobe_in <= 1'd0 ; - data_in <= 18'd0 ; - - // Wait for reset to go away - @(negedge reset) #0 ; - - // While we're still simulating ... - while( !endofsim ) begin - - // Write the input from the file or 0 if EOF... - @( posedge clock ) begin - //#1 ; - strobe_in <= 1'b1 ; - if( !$feof(infile) ) - ri = $fscanf( infile, "%d", data_in ) ; - else - data_in <= 18'd0 ; - end - - // Clocked in - set the strobe to 0 if the number of - // clocks per sample is greater than 1 - if( clocks > 1 ) begin - @(posedge clock) begin - strobe_in <= 1'b0 ; - end - - // Wait for the specified number of cycles - for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin - @(posedge clock) #1 ; - end - end - end - - // Print out the number of errors that occured - if( noe ) - $display( "FAILED: %d errors during simulation", noe ) ; - else - $display( "PASSED: Simulation successful" ) ; - - $finish ; - end - - // Output comparison of simulated values versus known good values - always @ (posedge clock) begin - if( reset ) - endofsim <= 1'b0 ; - else begin - if( !$feof(outfile) ) begin - if( strobe_out ) begin - ro = $fscanf( outfile, "%d\n", compare ) ; - if( compare != data_out ) begin - //$display( "%t: %d != %d", $realtime, data_out, compare ) ; - noe = noe + 1 ; - end - end - end else begin - // Signal end of simulation when no more outputs - endofsim <= 1'b1 ; - end - end - end - -endmodule // hb_dec_tb - diff --git a/fpga/usrp2/sdr_lib/small_hb_int.v b/fpga/usrp2/sdr_lib/small_hb_int.v deleted file mode 100644 index b69c45413..000000000 --- a/fpga/usrp2/sdr_lib/small_hb_int.v +++ /dev/null @@ -1,102 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// Short halfband decimator (intended to be followed by another stage) -// Implements impulse responses of the form [A 0 B 0.5 B 0 A] -// -// These taps designed by halfgen4 from ldoolittle: -// 2 * 131072 * halfgen4(.75/8,2) - -module small_hb_int - #(parameter WIDTH=18) - (input clk, - input rst, - input bypass, - input stb_in, - input [WIDTH-1:0] data_in, - input [7:0] output_rate, - input stb_out, - output reg [WIDTH-1:0] data_out); - - reg phase; - reg [WIDTH-1:0] d1, d2, d3, d4, d5, d6; - - localparam MWIDTH = 36; - wire [MWIDTH-1:0] prod; - - reg [6:0] stbin_d; - - always @(posedge clk) - stbin_d <= {stbin_d[5:0],stb_in}; - - always @(posedge clk) - if(stb_in) - begin - d1 <= data_in; - d2 <= d1; - d3 <= d2; - d4 <= d3; - d5 <= d4; - d6 <= d5; - end - - wire [WIDTH-1:0] sum_outer, sum_inner; - add2_and_round_reg #(.WIDTH(WIDTH)) add_outer (.clk(clk),.in1(d1),.in2(d4),.sum(sum_outer)); - add2_and_round_reg #(.WIDTH(WIDTH)) add_inner (.clk(clk),.in1(d2),.in2(d3),.sum(sum_inner)); - - wire [17:0] coeff_outer = -10690; - wire [17:0] coeff_inner = 75809; - - MULT18X18S mult(.C(clk), .CE(1), .R(rst), .P(prod), .A(stbin_d[1] ? coeff_outer : coeff_inner), - .B(stbin_d[1] ? sum_outer : sum_inner) ); - - wire [MWIDTH:0] accum; - acc #(.IWIDTH(MWIDTH),.OWIDTH(MWIDTH+1)) - acc (.clk(clk),.clear(stbin_d[2]),.acc(|stbin_d[3:2]),.in(prod),.out(accum)); - - wire [WIDTH+2:0] accum_rnd; - round_reg #(.bits_in(MWIDTH+1),.bits_out(WIDTH+3)) - final_round (.clk(clk),.in(accum),.out(accum_rnd)); - - wire [WIDTH-1:0] clipped; - clip_reg #(.bits_in(WIDTH+3),.bits_out(WIDTH)) final_clip - (.clk(clk),.in(accum_rnd),.strobe_in(1'b1), .out(clipped)); - - reg [WIDTH-1:0] saved, saved_d3; - always @(posedge clk) - if(stbin_d[6]) - saved <= clipped; - - always @(posedge clk) - if(stbin_d[3]) - saved_d3 <= d3; - - always @(posedge clk) - if(bypass) - data_out <= data_in; - else if(stb_in & stb_out) - case(output_rate) - 1 : data_out <= d6; - 2 : data_out <= d4; - 3, 4, 5, 6, 7 : data_out <= d3; - default : data_out <= d2; - endcase // case(output_rate) - else if(stb_out) - data_out <= saved; - -endmodule // small_hb_int - diff --git a/fpga/usrp2/sdr_lib/small_hb_int_tb.v b/fpga/usrp2/sdr_lib/small_hb_int_tb.v deleted file mode 100644 index fe1e1a7dd..000000000 --- a/fpga/usrp2/sdr_lib/small_hb_int_tb.v +++ /dev/null @@ -1,149 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module small_hb_int_tb( ) ; - - // Parameters for instantiation - parameter clocks = 8'd1 ; // Number of clocks per output - parameter decim = 1 ; // Sets the filter to decimate - parameter rate = 2 ; // Sets the decimation rate - - reg clock ; - reg reset ; - reg enable ; - wire strobe_in ; - reg signed [17:0] data_in ; - wire strobe_out ; - wire signed [17:0] data_out ; - - initial - begin - $dumpfile("small_hb_int_tb.vcd"); - $dumpvars(0,small_hb_int_tb); - end - - // Setup the clock - initial clock = 1'b0 ; - always #5 clock <= ~clock ; - - // Come out of reset after a while - initial reset = 1'b1 ; - initial #1000 reset = 1'b0 ; - - always @(posedge clock) - enable <= ~reset; - - // Instantiate UUT - /* - halfband_ideal - #( - .decim ( decim ), - .rate ( rate ) - ) uut( - .clock ( clock ), - .reset ( reset ), - .enable ( enable ), - .strobe_in ( strobe_in ), - .data_in ( data_in ), - .strobe_out ( strobe_out ), - .data_out ( data_out ) - ) ; - */ - - cic_strober #(.WIDTH(8)) - out_strober(.clock(clock),.reset(reset),.enable(enable),.rate(clocks), - .strobe_fast(1),.strobe_slow(strobe_out) ); - - cic_strober #(.WIDTH(8)) - in_strober(.clock(clock),.reset(reset),.enable(enable),.rate(2), - .strobe_fast(strobe_out),.strobe_slow(strobe_in) ); - - small_hb_int #(.WIDTH(18)) uut - (.clk(clock),.rst(reset),.bypass(0),.stb_in(strobe_in),.data_in(data_in), - .stb_out(strobe_out),.output_rate(clocks),.data_out(data_out) ); - - integer i, ri, ro, infile, outfile ; - - always @(posedge clock) - begin - if(strobe_out) - $display(data_out); - end - - // Setup file IO - initial begin - infile = $fopen("input.dat","r") ; - outfile = $fopen("output.dat","r") ; - $timeformat(-9, 2, " ns", 10) ; - end - - reg endofsim ; - reg signed [17:0] compare ; - integer noe ; - initial noe = 0 ; - - initial begin - // Initialize inputs - data_in <= 18'd0 ; - - // Wait for reset to go away - @(negedge reset) #0 ; - - // While we're still simulating ... - while( !endofsim ) begin - - // Write the input from the file or 0 if EOF... - @( negedge clock ) begin - if(strobe_in) - if( !$feof(infile) ) - ri <= #1 $fscanf( infile, "%d", data_in ) ; - else - data_in <= 18'd0 ; - end - end - - // Print out the number of errors that occured - if( noe ) - $display( "FAILED: %d errors during simulation", noe ) ; - else - $display( "PASSED: Simulation successful" ) ; - - $finish ; - end - - // Output comparison of simulated values versus known good values - always @ (posedge clock) begin - if( reset ) - endofsim <= 1'b0 ; - else begin - if( !$feof(outfile) ) begin - if( strobe_out ) begin - ro = $fscanf( outfile, "%d\n", compare ) ; - if( compare != data_out ) begin - //$display( "%t: %d != %d", $realtime, data_out, compare ) ; - noe = noe + 1 ; - end - end - end else begin - // Signal end of simulation when no more outputs - if($feof(infile)) - endofsim <= 1'b1 ; - end - end - end - -endmodule // small_hb_int_tb diff --git a/fpga/usrp2/sdr_lib/tx_control.v b/fpga/usrp2/sdr_lib/tx_control.v deleted file mode 100644 index e6866a40c..000000000 --- a/fpga/usrp2/sdr_lib/tx_control.v +++ /dev/null @@ -1,185 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -`define DSP_CORE_TX_BASE 128 - -module tx_control - #(parameter FIFOSIZE = 10) - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - input [31:0] master_time, - output underrun, - - // To FIFO interface from Buffer Pool - input [31:0] rd_dat_i, - input [3:0] rd_flags_i, - input rd_ready_i, - output rd_ready_o, - - // To DSP Core - output [31:0] sample, - output run, - input strobe, - - // FIFO Levels - output [15:0] fifo_occupied, - output fifo_full, - output fifo_empty, - - // Debug - output [31:0] debug - ); - - wire rd_sop_i = rd_flags_i[0]; // Unused - wire rd_eop_i = rd_flags_i[1]; - wire rd_occ_i = rd_flags_i[3:2]; // Unused, should always be 0 - - // Buffer interface to internal FIFO - wire write_data, write_ctrl, full_data, full_ctrl; - wire read_data, read_ctrl, empty_data, empty_ctrl; - wire clear_state; - reg [1:0] xfer_state; - reg [2:0] held_flags; - - localparam XFER_IDLE = 0; - localparam XFER_CTRL = 1; - localparam XFER_PKT = 2; - // Add underrun state? - - always @(posedge clk) - if(rst) - xfer_state <= XFER_IDLE; - else if(clear_state) - xfer_state <= XFER_IDLE; - else - if(rd_ready_i & rd_ready_o) - case(xfer_state) - XFER_IDLE : - begin - xfer_state <= XFER_CTRL; - held_flags <= rd_dat_i[2:0]; - end - XFER_CTRL : - xfer_state <= XFER_PKT; - XFER_PKT : - if(rd_eop_i) - xfer_state <= XFER_IDLE; - endcase // case(xfer_state) - - wire have_data_space; - assign full_data = ~have_data_space; - - assign write_data = (xfer_state == XFER_PKT) & rd_ready_i & rd_ready_o; - assign write_ctrl = (xfer_state == XFER_CTRL) & rd_ready_i & rd_ready_o; - - assign rd_ready_o = ~full_data & ~full_ctrl; - - wire [31:0] data_o; - wire eop_o, eob, sob, send_imm; - wire [31:0] sendtime; - wire [4:0] occ_ctrl; -/* - cascadefifo2 #(.WIDTH(33),.SIZE(FIFOSIZE)) txctrlfifo - (.clk(clk),.rst(rst),.clear(clear_state), - .datain({rd_eop_i,rd_dat_i[31:0]}), .write(write_data), .full(full_data), - .dataout({eop_o,data_o}), .read(read_data), .empty(empty_data), - .space(), .occupied(fifo_occupied) ); -*/ - wire have_data; - assign empty_data = ~have_data; - - fifo_cascade #(.WIDTH(33),.SIZE(FIFOSIZE)) txctrlfifo - (.clk(clk),.reset(rst),.clear(clear_state), - .datain({rd_eop_i,rd_dat_i[31:0]}), .src_rdy_i(write_data), .dst_rdy_o(have_data_space), - .dataout({eop_o,data_o}), .src_rdy_o(have_data), .dst_rdy_i(read_data), - .space(), .occupied(fifo_occupied) ); - assign fifo_full = full_data; - assign fifo_empty = empty_data; - - shortfifo #(.WIDTH(35)) ctrlfifo - (.clk(clk),.rst(rst),.clear(clear_state), - .datain({held_flags[2:0],rd_dat_i[31:0]}), .write(write_ctrl), .full(full_ctrl), - .dataout({send_imm,sob,eob,sendtime}), .read(read_ctrl), .empty(empty_ctrl), - .space(), .occupied(occ_ctrl) ); - - // Internal FIFO to DSP interface - reg [2:0] ibs_state; - - localparam IBS_IDLE = 0; - localparam IBS_WAIT = 1; - localparam IBS_RUNNING = 2; - localparam IBS_CONT_BURST = 3; - localparam IBS_UNDERRUN = 7; - - wire [32:0] delta_time = {1'b0,sendtime}-{1'b0,master_time}; - - wire too_late = (delta_time[32:31] == 2'b11); - wire go_now = ( master_time == sendtime ); - - always @(posedge clk) - if(rst) - ibs_state <= IBS_IDLE; - else - case(ibs_state) - IBS_IDLE : - if(~empty_ctrl & ~empty_data) - ibs_state <= IBS_WAIT; - IBS_WAIT : - if(send_imm) - ibs_state <= IBS_RUNNING; - else if(too_late) - ibs_state <= IBS_UNDERRUN; - else if(go_now) - ibs_state <= IBS_RUNNING; - IBS_RUNNING : - if(strobe) - if(empty_data) - ibs_state <= IBS_UNDERRUN; - else if(eop_o) - if(eob) - ibs_state <= IBS_IDLE; - else - ibs_state <= IBS_CONT_BURST; - IBS_CONT_BURST : - if(~empty_ctrl) // & ~empty_data) - ibs_state <= IBS_RUNNING; - else if(strobe) - ibs_state <= IBS_UNDERRUN; - IBS_UNDERRUN : // FIXME Should probably clean everything out - if(clear_state) - ibs_state <= IBS_IDLE; - endcase // case(ibs_state) - - assign read_ctrl = (ibs_state == IBS_RUNNING) & strobe & eop_o; // & ~empty_ctrl; - assign read_data = (ibs_state == IBS_RUNNING) & strobe & ~empty_data; - assign run = (ibs_state == IBS_RUNNING) | (ibs_state == IBS_CONT_BURST); - assign underrun = (ibs_state == IBS_UNDERRUN); - - wire [7:0] interp_rate; - setting_reg #(.my_addr(`DSP_CORE_TX_BASE+3)) sr_3 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_state)); - - assign sample = data_o; - - assign debug = { {16'b0}, - { read_data, write_data, read_ctrl, write_ctrl, xfer_state[1:0],full_ctrl,empty_ctrl }, - { occ_ctrl, eop_o, clear_state, underrun} }; - -endmodule // tx_control diff --git a/fpga/usrp2/sdr_lib/tx_frontend.v b/fpga/usrp2/sdr_lib/tx_frontend.v deleted file mode 100644 index dea8e010a..000000000 --- a/fpga/usrp2/sdr_lib/tx_frontend.v +++ /dev/null @@ -1,101 +0,0 @@ - -module tx_frontend - #(parameter BASE=0, - parameter WIDTH_OUT=16, - parameter IQCOMP_EN=1) - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - input [23:0] tx_i, input [23:0] tx_q, input run, - output reg [WIDTH_OUT-1:0] dac_a, output reg [WIDTH_OUT-1:0] dac_b - ); - - // IQ balance --> DC offset --> rounding --> mux - - wire [23:0] i_dco, q_dco, i_ofs, q_ofs; - wire [WIDTH_OUT-1:0] i_final, q_final; - wire [7:0] mux_ctrl; - wire [35:0] corr_i, corr_q; - wire [23:0] i_bal, q_bal; - wire [17:0] mag_corr, phase_corr; - - setting_reg #(.my_addr(BASE+0), .width(24)) sr_0 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(i_dco),.changed()); - - setting_reg #(.my_addr(BASE+1), .width(24)) sr_1 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(q_dco),.changed()); - - setting_reg #(.my_addr(BASE+2),.width(18)) sr_2 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(mag_corr),.changed()); - - setting_reg #(.my_addr(BASE+3),.width(18)) sr_3 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phase_corr),.changed()); - - setting_reg #(.my_addr(BASE+4), .width(8)) sr_4 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(mux_ctrl),.changed()); - - generate - if(IQCOMP_EN==1) - begin - // IQ Balance - MULT18X18S mult_mag_corr - (.P(corr_i), .A(tx_i[23:6]), .B(mag_corr), .C(clk), .CE(1), .R(rst) ); - - MULT18X18S mult_phase_corr - (.P(corr_q), .A(tx_i[23:6]), .B(phase_corr), .C(clk), .CE(1), .R(rst) ); - - add2_and_clip_reg #(.WIDTH(24)) add_clip_i - (.clk(clk), .rst(rst), - .in1(tx_i), .in2(corr_i[35:12]), .strobe_in(1'b1), - .sum(i_bal), .strobe_out()); - - add2_and_clip_reg #(.WIDTH(24)) add_clip_q - (.clk(clk), .rst(rst), - .in1(tx_q), .in2(corr_q[35:12]), .strobe_in(1'b1), - .sum(q_bal), .strobe_out()); - - // DC Offset - add2_and_clip_reg #(.WIDTH(24)) add_dco_i - (.clk(clk), .rst(rst), .in1(i_dco), .in2(i_bal), .strobe_in(1'b1), .sum(i_ofs), .strobe_out()); - - add2_and_clip_reg #(.WIDTH(24)) add_dco_q - (.clk(clk), .rst(rst), .in1(q_dco), .in2(q_bal), .strobe_in(1'b1), .sum(q_ofs), .strobe_out()); - end // if (IQCOMP_EN==1) - else - begin - // DC Offset - add2_and_clip_reg #(.WIDTH(24)) add_dco_i - (.clk(clk), .rst(rst), .in1(i_dco), .in2(tx_i), .strobe_in(1'b1), .sum(i_ofs), .strobe_out()); - - add2_and_clip_reg #(.WIDTH(24)) add_dco_q - (.clk(clk), .rst(rst), .in1(q_dco), .in2(tx_q), .strobe_in(1'b1), .sum(q_ofs), .strobe_out()); - end // else: !if(IQCOMP_EN==1) - endgenerate - - // Rounding - round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_i - (.clk(clk), .reset(rst), .in(i_ofs),.strobe_in(1'b1), .out(i_final), .strobe_out()); - - round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_q - (.clk(clk), .reset(rst), .in(q_ofs),.strobe_in(1'b1), .out(q_final), .strobe_out()); - - // Mux - always @(posedge clk) - case(mux_ctrl[3:0]) - 0 : dac_a <= i_final; - 1 : dac_a <= q_final; - default : dac_a <= 0; - endcase // case (mux_ctrl[3:0]) - - always @(posedge clk) - case(mux_ctrl[7:4]) - 0 : dac_b <= i_final; - 1 : dac_b <= q_final; - default : dac_b <= 0; - endcase // case (mux_ctrl[7:4]) - -endmodule // tx_frontend diff --git a/fpga/usrp2/serdes/Makefile.srcs b/fpga/usrp2/serdes/Makefile.srcs deleted file mode 100644 index bade46ad1..000000000 --- a/fpga/usrp2/serdes/Makefile.srcs +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright 2010 Ettus Research LLC -# - -################################################## -# SERDES Sources -################################################## -SERDES_SRCS = $(abspath $(addprefix $(BASE_DIR)/../serdes/, \ -serdes.v \ -serdes_fc_rx.v \ -serdes_fc_tx.v \ -serdes_rx.v \ -serdes_tx.v \ -)) diff --git a/fpga/usrp2/serdes/serdes.v b/fpga/usrp2/serdes/serdes.v deleted file mode 100644 index edbc46419..000000000 --- a/fpga/usrp2/serdes/serdes.v +++ /dev/null @@ -1,80 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// SERDES TX and RX along with all flow control logic - -module serdes - #(parameter TXFIFOSIZE = 9, - parameter RXFIFOSIZE = 9) - (input clk, input rst, - // TX side - output ser_tx_clk, output [15:0] ser_t, output ser_tklsb, output ser_tkmsb, - input [31:0] rd_dat_i, input [3:0] rd_flags_i, output rd_ready_o, input rd_ready_i, - // RX side - input ser_rx_clk, input [15:0] ser_r, input ser_rklsb, input ser_rkmsb, - output [31:0] wr_dat_o, output [3:0] wr_flags_o, output wr_ready_o, input wr_ready_i, - - output [15:0] tx_occupied, output tx_full, output tx_empty, - output [15:0] rx_occupied, output rx_full, output rx_empty, - - output serdes_link_up, - - output [31:0] debug0, - output [31:0] debug1); - - wire [15:0] fifo_space; - wire xon_rcvd, xoff_rcvd, inhibit_tx, send_xon, send_xoff, sent; - wire [31:0] debug_rx, debug_tx; - - serdes_tx #(.FIFOSIZE(TXFIFOSIZE)) serdes_tx - (.clk(clk),.rst(rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd_dat_i),.rd_flags_i(rd_flags_i),.rd_ready_o(rd_ready_o),.rd_ready_i(rd_ready_i), - .inhibit_tx(inhibit_tx), .send_xon(send_xon), .send_xoff(send_xoff), .sent(sent), - .fifo_occupied(tx_occupied),.fifo_full(tx_full),.fifo_empty(tx_empty), - .debug(debug_tx) ); - - serdes_rx #(.FIFOSIZE(RXFIFOSIZE)) serdes_rx - (.clk(clk),.rst(rst), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr_dat_o),.wr_flags_o(wr_flags_o),.wr_ready_o(wr_ready_o),.wr_ready_i(wr_ready_i), - .fifo_space(fifo_space), .xon_rcvd(xon_rcvd), .xoff_rcvd(xoff_rcvd), - .fifo_occupied(rx_occupied),.fifo_full(rx_full),.fifo_empty(rx_empty), - .serdes_link_up(serdes_link_up), .debug(debug_rx) ); - - serdes_fc_tx serdes_fc_tx - (.clk(clk),.rst(rst), - .xon_rcvd(xon_rcvd),.xoff_rcvd(xoff_rcvd),.inhibit_tx(inhibit_tx) ); - - serdes_fc_rx #(.LWMARK(32),.HWMARK(128)) serdes_fc_rx - (.clk(clk),.rst(rst), - .fifo_space(fifo_space),.send_xon(send_xon),.send_xoff(send_xoff),.sent(sent) ); - - //assign debug = { fifo_space, send_xon, send_xoff, debug_rx[13:0] }; - //assign debug = debug_rx; - - assign debug0 = { { 2'b00, rd_ready_o, rd_ready_i, rd_flags_i[3:0]}, - { debug_tx[5:4] /* full,empty */ , inhibit_tx, send_xon, send_xoff, sent, ser_tkmsb, ser_tklsb}, - { ser_t[15:8] }, - { ser_t[7:0] } }; - - assign debug1 = { { debug_rx[7:0] }, /* odd,xfer_active,sop_i,eop_i,error_i,state[2:0] */ - { wr_flags_o[1:0], wr_ready_i, wr_ready_o, xon_rcvd, xoff_rcvd, ser_rkmsb, ser_rklsb }, - { ser_r[15:8] }, - { ser_r[7:0] } }; -endmodule // serdes diff --git a/fpga/usrp2/serdes/serdes_fc_rx.v b/fpga/usrp2/serdes/serdes_fc_rx.v deleted file mode 100644 index 9ea32cf8d..000000000 --- a/fpga/usrp2/serdes/serdes_fc_rx.v +++ /dev/null @@ -1,79 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module serdes_fc_rx - #(parameter LWMARK = 64, - parameter HWMARK = 320) - (input clk, input rst, - input [15:0] fifo_space, - output reg send_xon, - output reg send_xoff, - input sent); - - reg [15:0] countdown; - reg send_xon_int, send_xoff_int; - - always @(posedge clk) - if(rst) - begin - send_xon_int <= 0; - send_xoff_int <= 0; - countdown <= 0; - end - else - begin - send_xon_int <= 0; - send_xoff_int <= 0; - if(countdown == 0) - if(fifo_space < LWMARK) - begin - send_xoff_int <= 1; - countdown <= 240; - end - else - ; - else - if(fifo_space > HWMARK) - begin - send_xon_int <= 1; - countdown <= 0; - end - else - countdown <= countdown - 1; - end // else: !if(rst) - - // If we are between the high and low water marks, we let the countdown expire - - always @(posedge clk) - if(rst) - send_xon <= 0; - else if(send_xon_int) - send_xon <= 1; - else if(sent) - send_xon <= 0; - - always @(posedge clk) - if(rst) - send_xoff <= 0; - else if(send_xoff_int) - send_xoff <= 1; - else if(sent) - send_xoff <= 0; - -endmodule // serdes_fc_rx diff --git a/fpga/usrp2/serdes/serdes_fc_tx.v b/fpga/usrp2/serdes/serdes_fc_tx.v deleted file mode 100644 index 0a62ae2e5..000000000 --- a/fpga/usrp2/serdes/serdes_fc_tx.v +++ /dev/null @@ -1,41 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module serdes_fc_tx - (input clk, input rst, - input xon_rcvd, input xoff_rcvd, output reg inhibit_tx); - - // XOFF means stop sending, XON means start sending - // clock domain stuff happens elsewhere, everything here is on main clk - - reg [15:0] state; - always @(posedge clk) - if(rst) - state <= 0; - else if(xoff_rcvd) - state <= 255; - else if(xon_rcvd) - state <= 0; - else if(state !=0) - state <= state - 1; - - always @(posedge clk) - inhibit_tx <= (state != 0); - -endmodule // serdes_fc_tx diff --git a/fpga/usrp2/serdes/serdes_rx.v b/fpga/usrp2/serdes/serdes_rx.v deleted file mode 100644 index 1950d4e2a..000000000 --- a/fpga/usrp2/serdes/serdes_rx.v +++ /dev/null @@ -1,310 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// SERDES Interface - -// LS-Byte is sent first, MS-Byte is second -// Invalid K Codes -// K0.0 000-00000 Error detected -// K31.7 111-11111 Loss of input signal - -// Valid K Codes -// K28.0 000-11100 -// K28.1 001-11100 Alternate COMMA? -// K28.2 010-11100 -// K28.3 011-11100 -// K28.4 100-11100 -// K28.5 101-11100 Standard COMMA? -// K28.6 110-11100 -// K28.7 111-11100 Bad COMMA? -// K23.7 111-10111 -// K27.7 111-11011 -// K29.7 111-11101 -// K30.7 111-11110 - -module serdes_rx - #(parameter FIFOSIZE = 9) - (input clk, - input rst, - - // RX HW Interface - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - output [31:0] wr_dat_o, - output [3:0] wr_flags_o, - input wr_ready_i, - output wr_ready_o, - - output [15:0] fifo_space, - output xon_rcvd, output xoff_rcvd, - - output [15:0] fifo_occupied, output fifo_full, output fifo_empty, - output reg serdes_link_up, - output [31:0] debug - ); - - localparam K_COMMA = 8'b101_11100; // 0xBC K28.5 - localparam K_IDLE = 8'b001_11100; // 0x3C K28.1 - localparam K_PKT_START = 8'b110_11100; // 0xDC K28.6 - localparam K_PKT_END = 8'b100_11100; // 0x9C K28.4 - localparam K_XON = 8'b010_11100; // 0x5C K28.2 - localparam K_XOFF = 8'b011_11100; // 0x7C K28.3 - localparam K_LOS = 8'b111_11111; // 0xFF K31.7 - localparam K_ERROR = 8'b000_00000; // 0x00 K00.0 - localparam D_56 = 8'b110_00101; // 0xC5 D05.6 - - localparam IDLE = 3'd0; - localparam FIRSTLINE1 = 3'd1; - localparam FIRSTLINE2 = 3'd2; - localparam PKT1 = 3'd3; - localparam PKT2 = 3'd4; - localparam CRC_CHECK = 3'd5; - localparam ERROR = 3'd6; - localparam DONE = 3'd7; - - wire [17:0] even_data; - reg [17:0] odd_data; - wire [17:0] chosen_data; - reg odd; - - reg [31:0] line_i; - reg sop_i, eop_i, error_i; - wire error_o, sop_o, eop_o, write; - reg [15:0] halfline; - reg [8:0] holder; - wire [31:0] line_o; - - reg [2:0] state; - - reg [15:0] CRC; - wire [15:0] nextCRC; - reg write_d; - - wire rst_rxclk; - wire have_space; - - oneshot_2clk rst_1s(.clk_in(clk),.in(rst),.clk_out(ser_rx_clk),.out(rst_rxclk)); - - assign even_data = {ser_rkmsb,ser_rklsb,ser_r}; - - always @(posedge ser_rx_clk) - if(rst_rxclk) - holder <= 9'd0; - else - holder <= {even_data[17],even_data[15:8]}; - - always @(posedge ser_rx_clk) - if(rst_rxclk) - odd_data <= 18'd0; - else - odd_data <= {even_data[16],holder[8],even_data[7:0],holder[7:0]}; - - assign chosen_data = odd ? odd_data : even_data; - - // Transfer xon and xoff info to the main system clock for flow control purposes - reg xon_rcvd_rxclk, xoff_rcvd_rxclk; - always @(posedge ser_rx_clk) - xon_rcvd_rxclk = ({1'b1,K_XON} == {ser_rkmsb,ser_r[15:8]}) | ({1'b1,K_XON} == {ser_rklsb,ser_r[7:0]} ); - always @(posedge ser_rx_clk) - xoff_rcvd_rxclk = ({1'b1,K_XOFF} == {ser_rkmsb,ser_r[15:8]}) | ({1'b1,K_XOFF} == {ser_rklsb,ser_r[7:0]} ); - - oneshot_2clk xon_1s(.clk_in(ser_rx_clk),.in(xon_rcvd_rxclk),.clk_out(clk),.out(xon_rcvd)); - oneshot_2clk xoff_1s(.clk_in(ser_rx_clk),.in(xoff_rcvd_rxclk),.clk_out(clk),.out(xoff_rcvd)); - - // If the other side is sending xon or xoff, or is flow controlled (b/c we told them to be), don't fill the fifos - wire wait_here = ((chosen_data == {2'b10,K_COMMA,D_56})|| - (chosen_data == {2'b11,K_XON,K_XON})|| - (chosen_data == {2'b11,K_XOFF,K_XOFF}) ); - - always @(posedge ser_rx_clk) - if(rst_rxclk) sop_i <= 0; - else if(state == FIRSTLINE1) sop_i <= 1; - else if(write_d) sop_i <= 0; - - reg write_pre; - always @(posedge ser_rx_clk) - if(rst_rxclk) - begin - state <= IDLE; - odd <= 0; - halfline <= 0; - line_i <= 0; - eop_i <= 0; - error_i <= 0; - write_pre <= 0; - end - else - case(state) - IDLE : - begin - error_i <= 0; - write_pre <= 0; - if(even_data == {2'b11,K_PKT_START,K_PKT_START}) - begin - state <= FIRSTLINE1; - odd <= 0; - end - else if(odd_data == {2'b11,K_PKT_START,K_PKT_START}) - begin - state <= FIRSTLINE1; - odd <= 1; - end - end - - FIRSTLINE1 : - if(chosen_data[17:16] == 0) - begin - halfline <= chosen_data[15:0]; - state <= FIRSTLINE2; - end - else if(wait_here) - ; // Flow Controlled, so wait here and do nothing - else - state <= ERROR; - - FIRSTLINE2 : - if(chosen_data[17:16] == 0) - begin - line_i <= {chosen_data[15:0],halfline}; - if(~have_space) // No space to write to! Should have been avoided by flow control - state <= ERROR; - else - begin - state <= PKT1; - write_pre <= 1; - end - end // if (chosen_data[17:16] == 0) - else if(wait_here) - ; // Flow Controlled, so wait here and do nothing - else - state <= ERROR; - - PKT1 : - begin - write_pre <= 0; - if(chosen_data[17:16] == 0) - begin - halfline <= chosen_data[15:0]; - state <= PKT2; - end - else if(wait_here) - ; // Flow Controlled - else if(chosen_data == {2'b11,K_PKT_END,K_PKT_END}) - state <= CRC_CHECK; - else - state <= ERROR; - end // case: PKT1 - - PKT2 : - if(chosen_data[17:16] == 0) - begin - line_i <= {1'b0,1'b0,1'b0,chosen_data[15:0],halfline}; - if(~have_space) // No space to write to! - state <= ERROR; - else - begin - state <= PKT1; - write_pre <= 1; - end - end // if (chosen_data[17:16] == 0) - else if(wait_here) - ; // Flow Controlled - else - state <= ERROR; - - CRC_CHECK : - if(chosen_data[17:0] == {2'b00,CRC}) - begin - if(~have_space) - state <= ERROR; - else - begin - eop_i <= 1; - state <= DONE; - end - end - else if(wait_here) - ; - else - state <= ERROR; - - ERROR : - begin - error_i <= 1; - if(have_space) - state <= IDLE; - end - DONE : - begin - state <= IDLE; - eop_i <= 0; - end - - endcase // case(state) - - - always @(posedge ser_rx_clk) - if(rst_rxclk) - CRC <= 16'hFFFF; - else if(state == IDLE) - CRC <= 16'hFFFF; - else if(chosen_data[17:16] == 2'b00) - CRC <= nextCRC; - - CRC16_D16 crc_blk(chosen_data[15:0],CRC,nextCRC); - - always @(posedge ser_rx_clk) - if(rst_rxclk) write_d <= 0; - else write_d <= write_pre; - - // Internal FIFO, size 9 is 2K, size 10 is 4K Bytes - assign write = eop_i | (error_i & have_space) | (write_d & (state != CRC_CHECK)); - wire dummy; // avoid warning on unconnected pin - - fifo_2clock_cascade #(.WIDTH(36),.SIZE(FIFOSIZE)) serdes_rx_fifo - (.arst(rst), - .wclk(ser_rx_clk),.datain({1'b0,error_i,sop_i,eop_i,line_i}), - .src_rdy_i(write), .dst_rdy_o(have_space), .space(fifo_space), - .rclk(clk),.dataout({dummy,error_o,sop_o,eop_o,line_o}), - .src_rdy_o(wr_ready_o), .dst_rdy_i(wr_ready_i), .occupied(fifo_occupied) ); - - assign fifo_full = ~have_space; // Note -- in the wrong clock domain - assign fifo_empty = ~wr_ready_o; - - // Internal FIFO to Buffer interface - assign wr_dat_o = line_o; - assign wr_flags_o = { 2'b00, eop_o | error_o, sop_o | error_o }; - - wire slu = ~(({2'b11,K_ERROR,K_ERROR}=={ser_rkmsb,ser_rklsb,ser_r}) || - ({2'b11,K_LOS,K_LOS}=={ser_rkmsb,ser_rklsb,ser_r})); - - reg [3:0] slu_reg; - - always @(posedge clk) - if(rst) slu_reg <= 0; - else slu_reg <= {slu_reg[2:0],slu}; - - always @(posedge clk) - serdes_link_up <= &slu_reg[3:1]; - - assign debug = { have_space, wr_ready_o, odd, sop_i, eop_i, error_i, state[2:0] }; - -endmodule // serdes_rx diff --git a/fpga/usrp2/serdes/serdes_tb.v b/fpga/usrp2/serdes/serdes_tb.v deleted file mode 100644 index 685a8580d..000000000 --- a/fpga/usrp2/serdes/serdes_tb.v +++ /dev/null @@ -1,345 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// FIXME need to add flow control - -module serdes_tb(); - - reg clk, rst; - wire ser_rx_clk, ser_tx_clk; - wire ser_rklsb, ser_rkmsb, ser_tklsb, ser_tkmsb; - wire [15:0] ser_r, ser_t; - - initial clk = 0; - initial rst = 1; - initial #1000 rst = 0; - always #100 clk = ~clk; - - // Wishbone - reg [31:0] wb_dat_i; - wire [31:0] wb_dat_o_rx, wb_dat_o_tx; - reg wb_we, wb_en_rx, wb_en_tx; - reg [8:0] wb_adr; - - // Buffer Control - reg go, clear, read, write; - reg [3:0] buf_num; - wire [31:0] ctrl_word = {buf_num,3'b0,clear,write,read,step,lastline,firstline}; - reg [8:0] firstline = 0, lastline = 0; - reg [3:0] step = 1; - reg first_tx = 1, first_rx = 1; // for verif - - // TX Side - reg wb_we_tx; - wire en_tx, we_tx; - wire [8:0] addr_tx; - wire [31:0] f2r_tx, r2f_tx; - wire [31:0] data_tx; - wire read_tx, done_tx, error_tx, sop_tx, eop_tx; - - wire fdone_tx, ferror_tx; - - reg even; - reg channel_error = 0; - - serdes_tx serdes_tx - (.clk(clk),.rst(rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(data_tx),.rd_read_o(read_tx),.rd_done_o(done_tx), - .rd_error_o(error_tx),.rd_sop_i(sop_tx),.rd_eop_i(eop_tx) ); - - ram_2port #(.DWIDTH(32),.AWIDTH(9)) - ram_tx(.clka(clk),.ena(wb_en_tx),.wea(wb_we_tx),.addra(wb_adr),.dia(wb_dat_i),.doa(wb_dat_o_tx), - .clkb(clk),.enb(en_tx),.web(we_tx),.addrb(addr_tx),.dib(f2r_tx),.dob(r2f_tx)); - - buffer_int #(.BUFF_NUM(1)) buffer_int_tx - (.clk(clk),.rst(rst), - .ctrl_word(ctrl_word),.go(go), - .done(fdone_tx),.error(ferror_tx), - - .en_o(en_tx),.we_o(we_tx),.addr_o(addr_tx),.dat_to_buf(f2r_tx),.dat_from_buf(r2f_tx), - - .wr_dat_i(0),.wr_write_i(0),.wr_done_i(0), - .wr_error_i(0),.wr_ready_o(),.wr_full_o(), - - .rd_dat_o(data_tx),.rd_read_i(read_tx),.rd_done_i(done_tx), - .rd_error_i(error_tx),.rd_sop_o(sop_tx),.rd_eop_o(eop_tx) ); - - - // RX Side - reg wb_we_rx; - wire en_rx, we_rx; - wire [8:0] addr_rx; - wire [31:0] f2r_rx, r2f_rx; - wire [31:0] data_rx; - wire write_rx, done_rx, error_rx, ready_rx, empty_rx; - - wire fdone_rx, ferror_rx; - - serdes_rx serdes_rx - (.clk(clk),.rst(rst), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(data_rx),.wr_write_o(write_rx),.wr_done_o(done_rx), - .wr_error_o(error_rx),.wr_ready_i(ready_rx),.wr_full_i(full_rx) ); - - ram_2port #(.DWIDTH(32),.AWIDTH(9)) - ram_rx(.clka(clk),.ena(wb_en_rx),.wea(wb_we_rx),.addra(wb_adr),.dia(wb_dat_i),.doa(wb_dat_o_rx), - .clkb(clk),.enb(en_rx),.web(we_rx),.addrb(addr_rx),.dib(f2r_rx),.dob(r2f_rx) ); - - buffer_int #(.BUFF_NUM(0)) buffer_int_rx - (.clk(clk),.rst(rst), - .ctrl_word(ctrl_word),.go(go), - .done(fdone_rx),.error(ferror_rx), - - .en_o(en_rx),.we_o(we_rx),.addr_o(addr_rx),.dat_to_buf(f2r_rx),.dat_from_buf(r2f_rx), - - .wr_dat_i(data_rx),.wr_write_i(write_rx),.wr_done_i(done_rx), - .wr_error_i(error_rx),.wr_ready_o(ready_rx),.wr_full_o(full_rx), - - .rd_dat_o(),.rd_read_i(0),.rd_done_i(0), - .rd_error_i(0),.rd_sop_o(),.rd_eop_o() ); - - // Simulate the connection - serdes_model serdes_model - (.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), .ser_t(ser_t), - .ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), .ser_r(ser_r), - .even(even), .error(channel_error) ); - - initial begin - wb_en_rx <= 0; - wb_en_tx <=0; - wb_we_tx <= 0; - wb_we_rx <= 0; - wb_adr <= 0; - wb_dat_i <= 0; - go <= 0; - even <= 0; - @(negedge rst); - @(posedge clk); - FillTXRAM; - ClearRXRAM; - ResetBuffer(0); - ResetBuffer(1); - - // receive a full buffer - ReceiveSERDES(0,10); - SendSERDES(0,10); - - // Receive a partial buffer - SendSERDES(11,20); - ReceiveSERDES(11,50); - - // Receive too many for buffer - SendSERDES(21,100); - ReceiveSERDES(21,30); - - // Send 3 packets, then wait to receive them, so they stack up in the rx fifo - SendSERDES(31,40); - SendSERDES(41,50); - SendSERDES(51,60); - repeat (10) - @(posedge clk); - ReceiveSERDES(31,40); - ReceiveSERDES(41,50); - repeat (1000) - @(posedge clk); - ReceiveSERDES(51,60); - - // Overfill the FIFO, should get an error on 3rd packet - SendSERDES(1,400); - SendSERDES(1,400); - - - WaitForTX; - //WaitForRX; - - - repeat(1000) - @(posedge clk); - ReceiveSERDES(101,500); - ReceiveSERDES(101,500); - ReadRAM(80); - $finish; - end // initial begin - - always @(posedge clk) - if(write_rx) - $display("SERDES RX, FIFO WRITE %x, FIFO RDY %d, FIFO FULL %d",data_rx, ready_rx, full_rx); - - always @(posedge clk) - if(read_tx) - $display("SERDES TX, FIFO READ %x, SOP %d, EOP %d",data_tx, sop_tx, eop_tx); - - initial begin - $dumpfile("serdes_tb.vcd"); - $dumpvars(0,serdes_tb); - end - - initial #10000000 $finish; - - initial #259300 channel_error <= 1; - initial #259500 channel_error <= 0; - - task FillTXRAM; - begin - wb_adr <= 0; - wb_dat_i <= 32'h10802000; - wb_we_tx <= 1; - wb_en_tx <= 1; - @(posedge clk); - repeat(511) begin - wb_dat_i <= wb_dat_i + 32'h00010001; - wb_adr <= wb_adr + 1; - @(posedge clk); - end // repeat (511) - wb_we_tx <= 0; - wb_en_tx <= 0; - @(posedge clk); - $display("Done entering Data into TX RAM\n"); - end - endtask // FillTXRAM - - task ClearRXRAM; - begin - wb_adr <= 0; - wb_dat_i <= 0; - wb_we_rx <= 1; - wb_en_rx <= 1; - wb_dat_i <= 0; - @(posedge clk); - repeat(511) begin - wb_adr <= wb_adr + 1; - @(posedge clk); - end // repeat (511) - wb_we_rx <= 0; - wb_en_rx <= 0; - @(posedge clk); - $display("Done clearing RX RAM\n"); - end - endtask // FillRAM - - task ReadRAM; - input [8:0] lastline; - begin - wb_en_rx <= 1; - wb_adr <= 0; - @(posedge clk); - @(posedge clk); - repeat(lastline) begin - $display("ADDR: %h DATA %h", wb_adr, wb_dat_o_rx); - wb_adr <= wb_adr + 1; - @(posedge clk); - @(posedge clk); - end // repeat (511) - $display("ADDR: %h DATA %h", wb_adr, wb_dat_o_rx); - wb_en_rx <= 0; - @(posedge clk); - $display("Done reading out RX RAM\n"); - end - endtask // FillRAM - - task ResetBuffer; - input [3:0] buffer_num; - begin - buf_num <= buffer_num; - clear <= 1; read <= 0; write <= 0; - go <= 1; - @(posedge clk); - go <= 0; - @(posedge clk); - $display("Buffer Reset"); - end - endtask // ClearBuffer - - task SetBufferWrite; - input [3:0] buffer_num; - input [8:0] start; - input [8:0] stop; - begin - buf_num <= buffer_num; - clear <= 0; read <= 0; write <= 1; - firstline <= start; - lastline <= stop; - go <= 1; - @(posedge clk); - go <= 0; - @(posedge clk); - $display("Buffer Set for Write"); - end - endtask // SetBufferWrite - - task SetBufferRead; - input [3:0] buffer_num; - input [8:0] start; - input [8:0] stop; - begin - buf_num <= buffer_num; - clear <= 0; read <= 1; write <= 0; - firstline <= start; - lastline <= stop; - go <= 1; - @(posedge clk); - go <= 0; - @(posedge clk); - $display("Buffer Set for Read"); - end - endtask // SetBufferRead - - task WaitForTX; - begin - while (!(fdone_tx | ferror_tx)) - @(posedge clk); - end - endtask // WaitForTX - - task WaitForRX; - begin - while (!(fdone_rx | ferror_rx)) - @(posedge clk); - end - endtask // WaitForRX - - task SendSERDES; - input [8:0] start; - input [8:0] stop; - begin - if(~first_tx) - WaitForTX; - else - first_tx <= 0; - ResetBuffer(1); - SetBufferRead(1,start,stop); - $display("Here"); - end - endtask // SendSERDES - - task ReceiveSERDES; - input [8:0] start; - input [8:0] stop; - begin - if(~first_rx) - WaitForRX; - else - first_rx <= 0; - ResetBuffer(0); - SetBufferWrite(0,start,stop); - $display("Here2"); - end - endtask // ReceiveSERDES - -endmodule // serdes_tb diff --git a/fpga/usrp2/serdes/serdes_tx.v b/fpga/usrp2/serdes/serdes_tx.v deleted file mode 100644 index 0cd077e5c..000000000 --- a/fpga/usrp2/serdes/serdes_tx.v +++ /dev/null @@ -1,203 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// SERDES Interface - -// LS-Byte is sent first, MS-Byte is second -// Invalid K Codes -// K0.0 000-00000 Error detected -// K31.7 111-11111 Loss of input signal - -// Valid K Codes -// K28.0 000-11100 -// K28.1 001-11100 Alternate COMMA? -// K28.2 010-11100 -// K28.3 011-11100 -// K28.4 100-11100 -// K28.5 101-11100 Standard COMMA? -// K28.6 110-11100 -// K28.7 111-11100 Bad COMMA? -// K23.7 111-10111 -// K27.7 111-11011 -// K29.7 111-11101 -// K30.7 111-11110 - -module serdes_tx - #(parameter FIFOSIZE = 9) - (input clk, - input rst, - - // TX HW Interface - output ser_tx_clk, - output reg [15:0] ser_t, - output reg ser_tklsb, - output reg ser_tkmsb, - - // TX Stream Interface - input [31:0] rd_dat_i, - input [3:0] rd_flags_i, - output rd_ready_o, - input rd_ready_i, - - // Flow control interface - input inhibit_tx, - input send_xon, - input send_xoff, - output sent, - - // FIFO Levels - output [15:0] fifo_occupied, - output fifo_full, - output fifo_empty, - - // DEBUG - output [31:0] debug - ); - - localparam K_COMMA = 8'b101_11100; // 0xBC K28.5 - localparam K_IDLE = 8'b001_11100; // 0x3C K28.1 - localparam K_PKT_START = 8'b110_11100; // 0xDC K28.6 - localparam K_PKT_END = 8'b100_11100; // 0x9C K28.4 - localparam K_XON = 8'b010_11100; // 0x5C K28.2 - localparam K_XOFF = 8'b011_11100; // 0x7C K28.3 - localparam K_LOS = 8'b111_11111; // 0xFF K31.7 - localparam K_ERROR = 8'b000_00000; // 0x00 K00.0 - localparam D_56 = 8'b110_00101; // 0xC5 D05.6 - assign ser_tx_clk = clk; - - localparam IDLE = 3'd0; - localparam RUN1 = 3'd1; - localparam RUN2 = 3'd2; - localparam DONE = 3'd3; - localparam SENDCRC = 3'd4; - localparam WAIT = 3'd5; - - reg [2:0] state; - - reg [15:0] CRC; - wire [15:0] nextCRC; - reg [3:0] wait_count; - - // Internal FIFO, size 9 is 2K, size 10 is 4K bytes - wire sop_o, eop_o; - wire [31:0] data_o; - - wire rd_sop_i = rd_flags_i[0]; - wire rd_eop_i = rd_flags_i[1]; - wire [1:0] rd_occ_i = rd_flags_i[3:2]; // Unused - - wire have_data, empty, read; - fifo_cascade #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo - (.clk(clk),.reset(rst),.clear(0), - .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .src_rdy_i(rd_ready_i), .dst_rdy_o(rd_ready_o), - .dataout({sop_o,eop_o,data_o}), .dst_rdy_i(read), .src_rdy_o(have_data), - .space(), .occupied(fifo_occupied) ); - - assign fifo_full = ~rd_ready_o; - assign empty = ~have_data; - assign fifo_empty = empty; - - // FIXME Implement flow control - reg [15:0] second_word; - reg [33:0] pipeline; - - assign read = (~send_xon & ~send_xoff & (state==RUN2)) | ((state==IDLE) & ~empty & ~sop_o); - assign sent = send_xon | send_xoff; - // 2nd half of above probably not necessary. Just in case we get junk between packets - - always @(posedge clk) - if(rst) - begin - state <= IDLE; - wait_count <= 0; - {ser_tkmsb,ser_tklsb,ser_t} <= 18'd0; - //{2'b10,K_COMMA,K_COMMA}; - // make tkmsb and tklsb different so they can go in IOFFs - end - else - if(send_xon) - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_XON,K_XON}; - else if(send_xoff) - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_XOFF,K_XOFF}; - else - case(state) - IDLE : - begin - if(sop_o & ~empty & ~inhibit_tx) - begin - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_PKT_START,K_PKT_START}; - state <= RUN1; - end - else - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56}; - end - RUN1 : - begin - if(empty | inhibit_tx) - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56}; - else - begin - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,data_o[15:0]}; - state <= RUN2; - end - end - RUN2 : - begin - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,data_o[31:16]}; - if(eop_o) - state <= DONE; - else - state <= RUN1; - end - DONE : - begin - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_PKT_END,K_PKT_END}; - state <= SENDCRC; - end - SENDCRC : - begin - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,CRC}; - state <= WAIT; - wait_count <= 4'd15; - end - WAIT : - begin - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56}; - if(wait_count == 0) - state <= IDLE; - else - wait_count <= wait_count - 1; - end - default - state <= IDLE; - endcase // case(state) - - always @(posedge clk) - if(rst) - CRC <= 16'hFFFF; - else if(state == IDLE) - CRC <= 16'hFFFF; - else if( (~empty & ~inhibit_tx & (state==RUN1)) || (state==RUN2) ) - CRC <= nextCRC; - - CRC16_D16 crc_blk( (state==RUN1) ? data_o[15:0] : data_o[31:16], CRC, nextCRC); - - assign debug = { 28'd0, state[2:0] }; - -endmodule // serdes_tx - diff --git a/fpga/usrp2/simple_gemac/.gitignore b/fpga/usrp2/simple_gemac/.gitignore deleted file mode 100644 index 17f35e962..000000000 --- a/fpga/usrp2/simple_gemac/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -/a.out -/*.vcd -simple_gemac_wrapper_tb - diff --git a/fpga/usrp2/simple_gemac/Makefile.srcs b/fpga/usrp2/simple_gemac/Makefile.srcs deleted file mode 100644 index 4ba3852b0..000000000 --- a/fpga/usrp2/simple_gemac/Makefile.srcs +++ /dev/null @@ -1,28 +0,0 @@ -# -# Copyright 2010 Ettus Research LLC -# - -################################################## -# Simple GEMAC Sources -################################################## -SIMPLE_GEMAC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../simple_gemac/, \ -simple_gemac_wrapper.v \ -simple_gemac.v \ -simple_gemac_wb.v \ -simple_gemac_tx.v \ -simple_gemac_rx.v \ -crc.v \ -delay_line.v \ -flow_ctrl_tx.v \ -flow_ctrl_rx.v \ -address_filter.v \ -address_filter_promisc.v \ -ll8_to_txmac.v \ -rxmac_to_ll8.v \ -miim/eth_miim.v \ -miim/eth_clockgen.v \ -miim/eth_outputcontrol.v \ -miim/eth_shiftreg.v \ -ethtx_realign.v \ -ethrx_realign.v \ -)) diff --git a/fpga/usrp2/simple_gemac/address_filter.v b/fpga/usrp2/simple_gemac/address_filter.v deleted file mode 100644 index bf6194600..000000000 --- a/fpga/usrp2/simple_gemac/address_filter.v +++ /dev/null @@ -1,52 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module address_filter - (input clk, - input reset, - input go, - input [7:0] data, - input [47:0] address, - output match, - output done); - - reg [2:0] af_state; - - always @(posedge clk) - if(reset) - af_state <= 0; - else - if(go) - af_state <= (data == address[47:40]) ? 1 : 7; - else - case(af_state) - 1 : af_state <= (data == address[39:32]) ? 2 : 7; - 2 : af_state <= (data == address[31:24]) ? 3 : 7; - 3 : af_state <= (data == address[23:16]) ? 4 : 7; - 4 : af_state <= (data == address[15:8]) ? 5 : 7; - 5 : af_state <= (data == address[7:0]) ? 6 : 7; - 6, 7 : af_state <= 0; - endcase // case (af_state) - - assign match = (af_state==6); - assign done = (af_state==6)|(af_state==7); - -endmodule // address_filter - - diff --git a/fpga/usrp2/simple_gemac/address_filter_promisc.v b/fpga/usrp2/simple_gemac/address_filter_promisc.v deleted file mode 100644 index 3ff05fbe1..000000000 --- a/fpga/usrp2/simple_gemac/address_filter_promisc.v +++ /dev/null @@ -1,49 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module address_filter_promisc - (input clk, - input reset, - input go, - input [7:0] data, - output match, - output done); - - reg [2:0] af_state; - - always @(posedge clk) - if(reset) - af_state <= 0; - else - if(go) - af_state <= (data[0] == 1'b0) ? 1 : 7; - else - case(af_state) - 1 : af_state <= 2; - 2 : af_state <= 3; - 3 : af_state <= 4; - 4 : af_state <= 5; - 5 : af_state <= 6; - 6, 7 : af_state <= 0; - endcase // case (af_state) - - assign match = (af_state==6); - assign done = (af_state==6)|(af_state==7); - -endmodule // address_filter_promisc diff --git a/fpga/usrp2/simple_gemac/crc.v b/fpga/usrp2/simple_gemac/crc.v deleted file mode 100644 index ef62f8ff8..000000000 --- a/fpga/usrp2/simple_gemac/crc.v +++ /dev/null @@ -1,83 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module crc - (input clk, - input reset, - input clear, - input [7:0] data, - input calc, - output [31:0] crc_out, - output match); - - function[31:0] NextCRC; - input[7:0] D; - input[31:0] C; - reg[31:0] NewCRC; - begin - NewCRC[0] = C[24]^C[30]^D[1]^D[7]; - NewCRC[1] = C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; - NewCRC[2] = C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; - NewCRC[3] = C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; - NewCRC[4] = C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7]; - NewCRC[5] = C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; - NewCRC[6] = C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; - NewCRC[7] = C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; - NewCRC[8] = C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; - NewCRC[9] = C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]; - NewCRC[10] = C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; - NewCRC[11] = C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; - NewCRC[12] = C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; - NewCRC[13] = C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; - NewCRC[14] = C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5]; - NewCRC[15] = C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4]; - NewCRC[16] = C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7]; - NewCRC[17] = C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6]; - NewCRC[18] = C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5]; - NewCRC[19] = C[11]^C[31]^D[0]^C[27]^D[4]; - NewCRC[20] = C[12]^C[28]^D[3]; - NewCRC[21] = C[13]^C[29]^D[2]; - NewCRC[22] = C[14]^C[24]^D[7]; - NewCRC[23] = C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; - NewCRC[24] = C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; - NewCRC[25] = C[17]^C[27]^D[4]^C[26]^D[5]; - NewCRC[26] = C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7]; - NewCRC[27] = C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6]; - NewCRC[28] = C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5]; - NewCRC[29] = C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4]; - NewCRC[30] = C[22]^C[31]^D[0]^C[28]^D[3]; - NewCRC[31] = C[23]^C[29]^D[2]; - NextCRC = NewCRC; - end - endfunction - - reg [31:0] crc_reg; - always @ (posedge clk) - if (reset | clear) - crc_reg <= 32'hffffffff; - else if (calc) - crc_reg <= NextCRC(data,crc_reg); - - assign crc_out = ~{crc_reg[24],crc_reg[25],crc_reg[26],crc_reg[27],crc_reg[28],crc_reg[29],crc_reg[30],crc_reg[31], - crc_reg[16],crc_reg[17],crc_reg[18],crc_reg[19],crc_reg[20],crc_reg[21],crc_reg[22],crc_reg[23], - crc_reg[8],crc_reg[9],crc_reg[10],crc_reg[11],crc_reg[12],crc_reg[13],crc_reg[14],crc_reg[15], - crc_reg[0],crc_reg[1],crc_reg[2],crc_reg[3],crc_reg[4],crc_reg[5],crc_reg[6],crc_reg[7] }; - - assign match = (crc_reg == 32'hc704_dd7b); - -endmodule // crc diff --git a/fpga/usrp2/simple_gemac/delay_line.v b/fpga/usrp2/simple_gemac/delay_line.v deleted file mode 100644 index 5a559a504..000000000 --- a/fpga/usrp2/simple_gemac/delay_line.v +++ /dev/null @@ -1,38 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module delay_line - #(parameter WIDTH=32) - (input clk, - input [3:0] delay, - input [WIDTH-1:0] din, - output [WIDTH-1:0] dout); - - genvar i; - generate - for (i=0;i. -// - - - -task SendFlowCtrl; - input [15:0] fc_len; - begin - $display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time); - pause_time <= fc_len; - @(posedge clk); - pause_req <= 1; - @(posedge clk); - pause_req <= 0; - $display("Sent Flow Control"); - end -endtask // SendFlowCtrl - -task SendPacket2MAC; - input tx_clk; - input [7:0] data_start; - input [31:0] data_len; - output [7:0] tx_data; - output tx_valid; - output tx_error; - input tx_ack; - reg [15:0] count; - begin - $display("Sending Packet Len=%d, %d", data_len, $time); - count <= 1; - tx_data <= data_start; - tx_error <= 0; - tx_valid <= 1; - while(~tx_ack) - @(posedge tx_clk); - $display("Packet Accepted, %d", $time); - while(count < data_len) - begin - tx_data <= tx_data + 1; - count <= count + 1; - @(posedge clk); - end - tx_valid <= 0; - @(posedge tx_clk); - end -endtask // SendPacket2MAC - -task SendPacket_to_ll8; - input [7:0] data_start; - input [15:0] data_len; -// output [7:0] tx_data; -// output tx_sof; -// output tx_eof; -// output tx_src_rdy; -// input tx_dst_rdy; - reg [15:0] count; - begin - $display("Sending Packet Len=%d, %d", data_len, $time); - count <= 2; - tx_ll_data2 <= data_start; - tx_ll_src_rdy2 <= 1; - tx_ll_sof2 <= 1; - tx_ll_eof2 <= 0; - #1; - while(count < data_len) - begin - while(~tx_ll_dst_rdy2) - @(posedge clk); - @(posedge clk); - tx_ll_data2 = tx_ll_data2 + 1; - count = count + 1; - tx_ll_sof2 <= 0; - end - tx_ll_eof2 <= 1; - while(~tx_ll_dst_rdy2) - @(posedge clk); - @(posedge clk); - tx_ll_src_rdy2 <= 0; - end -endtask // SendPacket_to_ll8 - - -task SendPacketFromFile; - input clk; - input [31:0] data_len; - output [7:0] tx_data; - output tx_valid; - output tx_error; - input tx_ack; - reg [15:0] count; - begin - $display("Sending Packet From File Len=%d, %d",data_len,$time); - $readmemh("test_packet.mem",pkt_rom ); - count = 0; - tx_data = pkt_rom[count]; - tx_error = 0; - tx_valid = 1; - while(~tx_ack) - @(posedge clk); - $display("Packet Accepted, %d",$time); - count = 1; - while(count < data_len) - begin - tx_data = pkt_rom[count]; - count = count + 1; - @(posedge clk); - end - tx_valid <= 0; - @(posedge clk); - end -endtask // SendPacketFromFile - -task Waiter; - input [31:0] wait_length; - begin - tx_ll_src_rdy2 <= 0; - repeat(wait_length) - @(posedge clk); - tx_ll_src_rdy2 <= 1; - end -endtask // Waiter - -task SendPacketFromFile_ll8; - input [31:0] data_len; - input [31:0] wait_length; - input [31:0] wait_time; - - integer count; - begin - $display("Sending Packet From File to LL8 Len=%d, %d",data_len,$time); - $readmemh("test_packet.mem",pkt_rom ); - - while(~tx_ll_dst_rdy2) - @(posedge clk); - tx_ll_data2 <= pkt_rom[0]; - tx_ll_src_rdy2 <= 1; - tx_ll_sof2 <= 1; - tx_ll_eof2 <= 0; - @(posedge clk); - - for(i=1;i. -// - - - -task SendFlowCtrl; - input [15:0] fc_len; - begin - $display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time); - pause_time <= fc_len; - @(posedge eth_clk); - pause_req <= 1; - @(posedge eth_clk); - pause_req <= 0; - $display("Sent Flow Control"); - end -endtask // SendFlowCtrl - -task SendPacket_to_fifo19; - input [31:0] data_start; - input [15:0] data_len; - reg [15:0] count; - begin - $display("Sending Packet Len=%d, %d", data_len, $time); - count <= 2; - tx_f19_data <= {2'b0, 1'b0, 1'b1, data_start}; - tx_f19_src_rdy <= 1; - #1; - while(count < data_len) - begin - while(~tx_f19_dst_rdy) - @(posedge sys_clk); - @(posedge sys_clk); - //tx_f19_data[31:0] = tx_f19_data[31:0] + 32'h0101_0101; - count = count + 4; - //tx_f19_data[32] <= 0; - end - //tx_f19_data[33] <= 1; - while(~tx_f19_dst_rdy) - @(posedge sys_clk); - @(posedge sys_clk); - tx_f19_src_rdy <= 0; - end -endtask // SendPacket_to_fifo19 - -/* -task Waiter; - input [31:0] wait_length; - begin - tx_ll_src_rdy2 <= 0; - repeat(wait_length) - @(posedge clk); - tx_ll_src_rdy2 <= 1; - end -endtask // Waiter -*/ - -/* -task SendPacketFromFile_f19; - input [31:0] data_len; - input [31:0] wait_length; - input [31:0] wait_time; - - integer count; - begin - $display("Sending Packet From File to LL8 Len=%d, %d",data_len,$time); - $readmemh("test_packet.mem",pkt_rom ); - - while(~tx_f19_dst_rdy) - @(posedge clk); - tx_f19_data <= pkt_rom[0]; - tx_f19_src_rdy <= 1; - tx_f19_eof <= 0; - @(posedge clk); - - for(i=1;i. -// - - - -task SendFlowCtrl; - input [15:0] fc_len; - begin - $display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time); - //pause_time <= fc_len; - @(posedge eth_clk); - //pause_req <= 1; - @(posedge eth_clk); - //pause_req <= 0; - $display("Sent Flow Control"); - end -endtask // SendFlowCtrl - -task SendPacket_to_fifo36; - input [31:0] data_start; - input [15:0] data_len; - reg [15:0] count; - begin - $display("Sending Packet Len=%d, %d", data_len, $time); - count <= 2; - tx_f36_data <= {2'b0, 1'b0, 1'b1, data_start}; - tx_f36_src_rdy <= 1; - #1; - while(count < data_len) - begin - while(~tx_f36_dst_rdy) - @(posedge sys_clk); - @(posedge sys_clk); - tx_f36_data[31:0] = tx_f36_data[31:0] + 32'h0101_0101; - count = count + 4; - tx_f36_data[32] <= 0; - end - tx_f36_data[33] <= 1; - while(~tx_f36_dst_rdy) - @(posedge sys_clk); - @(posedge sys_clk); - tx_f36_src_rdy <= 0; - end -endtask // SendPacket_to_fifo36 - -/* -task Waiter; - input [31:0] wait_length; - begin - tx_ll_src_rdy2 <= 0; - repeat(wait_length) - @(posedge clk); - tx_ll_src_rdy2 <= 1; - end -endtask // Waiter -*/ - -/* -task SendPacketFromFile_f36; - input [31:0] data_len; - input [31:0] wait_length; - input [31:0] wait_time; - - integer count; - begin - $display("Sending Packet From File to LL8 Len=%d, %d",data_len,$time); - $readmemh("test_packet.mem",pkt_rom ); - - while(~tx_f36_dst_rdy) - @(posedge clk); - tx_f36_data <= pkt_rom[0]; - tx_f36_src_rdy <= 1; - tx_f36_eof <= 0; - @(posedge clk); - - for(i=1;i. -// - - -// NOTE: Will not work with single-line frames - -module ethrx_realign - (input clk, input reset, input clear, - input [35:0] datain, input src_rdy_i, output dst_rdy_o, - output [35:0] dataout, output src_rdy_o, input dst_rdy_i); - - reg [1:0] state; - reg [15:0] held; - reg [1:0] held_occ; - - wire xfer_in = src_rdy_i & dst_rdy_o; - wire xfer_out = src_rdy_o & dst_rdy_i; - - wire sof_in = datain[32]; - wire eof_in = datain[33]; - wire [1:0] occ_in = datain[35:34]; - wire sof_out, eof_out; - wire [1:0] occ_out; - - always @(posedge clk) - if(reset | clear) - begin - held <= 0; - held_occ <= 0; - end - else if(xfer_in) - begin - held <= datain[15:0]; - held_occ <= datain[35:34]; - end - - localparam RE_IDLE = 0; - localparam RE_HELD = 1; - localparam RE_DONE = 2; - - always @(posedge clk) - if(reset | clear) - state <= RE_IDLE; - else - case(state) - RE_IDLE : - if(src_rdy_i & dst_rdy_i) - if(eof_in) - state <= RE_DONE; - else - state <= RE_HELD; - - RE_HELD : - if(src_rdy_i & dst_rdy_i & eof_in) - if((occ_in==0)|(occ_in==3)) - state <= RE_DONE; - else - state <= RE_IDLE; - - RE_DONE : - if(dst_rdy_i) - state <= RE_IDLE; - - endcase // case (state) - - - assign sof_out = (state == RE_IDLE); - assign eof_out = (state == RE_DONE) | (occ_in == 1) | (occ_in == 2); - assign occ_out = (state == RE_DONE) ? ((held_occ == 3) ? 1 : 2) : - (occ_in == 1) ? 3 : 0; - - assign dataout = {occ_out,eof_out,sof_out,held,datain[31:16]}; - assign src_rdy_o = (state == RE_DONE) | src_rdy_i; - assign dst_rdy_o = dst_rdy_i & ((state == RE_IDLE)|(state == RE_HELD)); -endmodule // ethrx_realign diff --git a/fpga/usrp2/simple_gemac/ethtx_realign.v b/fpga/usrp2/simple_gemac/ethtx_realign.v deleted file mode 100644 index 236b2d4e1..000000000 --- a/fpga/usrp2/simple_gemac/ethtx_realign.v +++ /dev/null @@ -1,94 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -//////////////////////////////////////////////////////////////////////// -// Ethernet TX - Realign -// -// - removes a 2-byte pad from the front a fifo36 stream -// - occupancy is preserved -// - -module ethtx_realign - (input clk, input reset, input clear, - input [35:0] datain, input src_rdy_i, output dst_rdy_o, - output [35:0] dataout, output src_rdy_o, input dst_rdy_i); - - reg [1:0] state; - reg [15:0] held; - reg [1:0] held_occ; - reg held_sof; - - wire xfer_in = src_rdy_i & dst_rdy_o; - wire xfer_out = src_rdy_o & dst_rdy_i; - - wire sof_in = datain[32]; - wire eof_in = datain[33]; - wire [1:0] occ_in = datain[35:34]; - wire occ_low = occ_in[1] ^ occ_in[0]; //occ is 1 or 2 - - always @(posedge clk) - if(reset | clear) - begin - held <= 0; - held_occ <= 0; - held_sof <= 0; - end - else if(xfer_in) - begin - held <= datain[15:0]; - held_occ <= occ_in; - held_sof <= sof_in; - end - - localparam RE_IDLE = 0; - localparam RE_HELD = 1; - localparam RE_DONE = 2; - - always @(posedge clk) - if(reset | clear) - state <= RE_IDLE; - else - case(state) - RE_IDLE : - if(xfer_in & eof_in) - state <= RE_DONE; - else if(xfer_in & sof_in) - state <= RE_HELD; - - RE_HELD : - if(xfer_in & xfer_out & eof_in) - if(occ_low) - state <= RE_IDLE; - else - state <= RE_DONE; - - RE_DONE : - if(xfer_out) - state <= RE_IDLE; - - endcase // case (state) - - wire sof_out = held_sof; - wire eof_out = (state == RE_HELD)? (eof_in & occ_low) : (state == RE_DONE); - wire [1:0] occ_out = ((state == RE_DONE)? held_occ : occ_in) ^ 2'b10; //(occ + 2)%4 - - assign dataout = {occ_out,eof_out,sof_out,held,datain[31:16]}; - assign src_rdy_o = (state == RE_HELD)? src_rdy_i : (state == RE_DONE); - assign dst_rdy_o = (state == RE_HELD)? dst_rdy_i : (state == RE_IDLE); - -endmodule // ethtx_realign diff --git a/fpga/usrp2/simple_gemac/flow_ctrl_rx.v b/fpga/usrp2/simple_gemac/flow_ctrl_rx.v deleted file mode 100644 index aa12875f2..000000000 --- a/fpga/usrp2/simple_gemac/flow_ctrl_rx.v +++ /dev/null @@ -1,78 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// RX side of flow control -- when we are running out of RX space, send a PAUSE - -module flow_ctrl_rx - (input pause_request_en, input [15:0] pause_time, input [15:0] pause_thresh, - input rx_clk, input rx_reset, input [15:0] rx_fifo_space, - input tx_clk, input tx_reset, output reg pause_req, output reg [15:0] pause_time_req - ); - - // ****************************************************************************** - // Force our TX to send a PAUSE frame because our RX is nearly full - // ****************************************************************************** - - // RX Clock Domain - reg xon, xoff; - reg [21:0] countdown; - - wire [15:0] pause_low_thresh = pause_thresh; - wire [15:0] pause_hi_thresh = 16'hFFFF; - wire [21:0] pq_reduced = {pause_time,6'd0} - 1700; - - always @(posedge rx_clk) - if(rx_reset) - xoff <= 0; - else - xoff <= (pause_request_en & (countdown==0) & (rx_fifo_space < pause_low_thresh)); - - always @(posedge rx_clk) - if(rx_reset) - xon <= 0; - else - xon <= ((countdown!=0) & (rx_fifo_space > pause_hi_thresh)); - - always @(posedge rx_clk) - if(rx_reset) - countdown <= 0; - else if(xoff) - countdown <= pq_reduced; - else if(xon) - countdown <= 0; - else if(countdown != 0) - countdown <= countdown - 1; - - // Cross clock domains - wire xon_tx, xoff_tx; - oneshot_2clk send_xon (.clk_in(rx_clk), .in(xon), .clk_out(tx_clk), .out(xon_tx)); - oneshot_2clk send_xoff (.clk_in(rx_clk), .in(xoff), .clk_out(tx_clk), .out(xoff_tx)); - - always @(posedge tx_clk) - if(xoff_tx) - pause_time_req <= pause_time; - else if(xon_tx) - pause_time_req <= 0; - - always @(posedge tx_clk) - if(tx_reset) - pause_req <= 0; - else - pause_req <= xon_tx | xoff_tx; - -endmodule // flow_ctrl_rx diff --git a/fpga/usrp2/simple_gemac/flow_ctrl_tx.v b/fpga/usrp2/simple_gemac/flow_ctrl_tx.v deleted file mode 100644 index bdc1e4701..000000000 --- a/fpga/usrp2/simple_gemac/flow_ctrl_tx.v +++ /dev/null @@ -1,56 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// TX side of flow control -- when other side sends PAUSE, we wait - -module flow_ctrl_tx - (input rst, - input tx_clk, - //host processor - input tx_pause_en, - // From MAC_rx_ctrl - input [15:0] pause_quanta, - input pause_quanta_val, - // MAC_tx_ctrl - output pause_apply, - input paused); - - // ****************************************************************************** - // Inhibit our TX from transmitting because they sent us a PAUSE frame - // ****************************************************************************** - - // Pauses are in units of 512 bit times, or 64 bytes/clock cycles, and can be - // as big as 16 bits, so 22 bits are needed for the counter - - reg [15+6:0] pause_quanta_counter; - reg pqval_d1, pqval_d2; - - always @(posedge tx_clk) pqval_d1 <= pause_quanta_val; - always @(posedge tx_clk) pqval_d2 <= pqval_d1; - - always @ (posedge tx_clk or posedge rst) - if (rst) - pause_quanta_counter <= 0; - else if (pqval_d1 & ~pqval_d2) - pause_quanta_counter <= {pause_quanta, 6'b0}; - else if((pause_quanta_counter!=0) & paused) - pause_quanta_counter <= pause_quanta_counter - 1; - - assign pause_apply = tx_pause_en & (pause_quanta_counter != 0); - -endmodule // flow_ctrl diff --git a/fpga/usrp2/simple_gemac/ll8_to_txmac.v b/fpga/usrp2/simple_gemac/ll8_to_txmac.v deleted file mode 100644 index ac81afa63..000000000 --- a/fpga/usrp2/simple_gemac/ll8_to_txmac.v +++ /dev/null @@ -1,60 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module ll8_to_txmac - (input clk, input reset, input clear, - input [7:0] ll_data, input ll_sof, input ll_eof, input ll_src_rdy, output ll_dst_rdy, - output [7:0] tx_data, output tx_valid, output tx_error, input tx_ack ); - - reg [2:0] xfer_state; - - localparam XFER_IDLE = 0; - localparam XFER_ACTIVE = 1; - localparam XFER_WAIT1 = 2; - localparam XFER_UNDERRUN = 3; - localparam XFER_DROP = 4; - - always @(posedge clk) - if(reset | clear) - xfer_state <= XFER_IDLE; - else - case(xfer_state) - XFER_IDLE : - if(tx_ack) - xfer_state <= XFER_ACTIVE; - XFER_ACTIVE : - if(~ll_src_rdy) - xfer_state <= XFER_UNDERRUN; - else if(ll_eof) - xfer_state <= XFER_WAIT1; - XFER_WAIT1 : - xfer_state <= XFER_IDLE; - XFER_UNDERRUN : - xfer_state <= XFER_DROP; - XFER_DROP : - if(ll_eof) - xfer_state <= XFER_IDLE; - endcase // case (xfer_state) - - assign ll_dst_rdy = (xfer_state == XFER_ACTIVE) | tx_ack | (xfer_state == XFER_DROP); - assign tx_valid = (ll_src_rdy & (xfer_state == XFER_IDLE))|(xfer_state == XFER_ACTIVE); - assign tx_data = ll_data; - assign tx_error = (xfer_state == XFER_UNDERRUN); - -endmodule // ll8_to_txmac - diff --git a/fpga/usrp2/simple_gemac/miim/eth_clockgen.v b/fpga/usrp2/simple_gemac/miim/eth_clockgen.v deleted file mode 100644 index 9da732f7f..000000000 --- a/fpga/usrp2/simple_gemac/miim/eth_clockgen.v +++ /dev/null @@ -1,141 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// eth_clockgen.v //// -//// //// -//// This file is part of the Ethernet IP core project //// -//// http://www.opencores.org/projects/ethmac/ //// -//// //// -//// Author(s): //// -//// - Igor Mohor (igorM@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: eth_clockgen.v,v $ -// Revision 1.2 2005/12/13 12:54:49 maverickist -// first simulation passed -// -// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator -// no message -// -// Revision 1.2 2005/04/27 15:58:45 Administrator -// no message -// -// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator -// no message -// -// Revision 1.3 2002/01/23 10:28:16 mohor -// Link in the header changed. -// -// Revision 1.2 2001/10/19 08:43:51 mohor -// eth_timescale.v changed to timescale.v This is done because of the -// simulation of the few cores in a one joined project. -// -// Revision 1.1 2001/08/06 14:44:29 mohor -// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). -// Include files fixed to contain no path. -// File names and module names changed ta have a eth_ prologue in the name. -// File eth_timescale.v is used to define timescale -// All pin names on the top module are changed to contain _I, _O or _OE at the end. -// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O -// and Mdo_OE. The bidirectional signal must be created on the top level. This -// is done due to the ASIC tools. -// -// Revision 1.1 2001/07/30 21:23:42 mohor -// Directory structure changed. Files checked and joind together. -// -// Revision 1.3 2001/06/01 22:28:55 mohor -// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. -// -// - -module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc); - -//parameter Tp=1; - -input Clk; // Input clock (Host clock) -input Reset; // Reset signal -input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0]) - -output Mdc; // Output clock -output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises. -output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. - -reg Mdc; -reg [7:0] Counter; - -wire CountEq0; -wire [7:0] CounterPreset; -wire [7:0] TempDivider; - - -assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2 -assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; // We are counting half of period - - -// Counter counts half period -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - Counter[7:0] <= 8'h1; - else - begin - if(CountEq0) - begin - Counter[7:0] <= CounterPreset[7:0]; - end - else - Counter[7:0] <= Counter - 8'h1; - end -end - - -// Mdc is asserted every other half period -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - Mdc <= 1'b0; - else - begin - if(CountEq0) - Mdc <= ~Mdc; - end -end - - -assign CountEq0 = Counter == 8'h0; -assign MdcEn = CountEq0 & ~Mdc; -assign MdcEn_n = CountEq0 & Mdc; - -endmodule - - diff --git a/fpga/usrp2/simple_gemac/miim/eth_miim.v b/fpga/usrp2/simple_gemac/miim/eth_miim.v deleted file mode 100644 index a15c94205..000000000 --- a/fpga/usrp2/simple_gemac/miim/eth_miim.v +++ /dev/null @@ -1,470 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// eth_miim.v //// -//// //// -//// This file is part of the Ethernet IP core project //// -//// http://www.opencores.org/projects/ethmac/ //// -//// //// -//// Author(s): //// -//// - Igor Mohor (igorM@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: eth_miim.v,v $ -// Revision 1.3 2006/01/19 14:07:53 maverickist -// verification is complete. -// -// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator -// no message -// -// Revision 1.4 2005/08/16 12:07:57 Administrator -// no message -// -// Revision 1.3 2005/05/19 07:04:29 Administrator -// no message -// -// Revision 1.2 2005/04/27 15:58:46 Administrator -// no message -// -// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator -// no message -// -// Revision 1.5 2003/05/16 10:08:27 mohor -// Busy was set 2 cycles too late. Reported by Dennis Scott. -// -// Revision 1.4 2002/08/14 18:32:10 mohor -// - Busy signal was not set on time when scan status operation was performed -// and clock was divided with more than 2. -// - Nvalid remains valid two more clocks (was previously cleared too soon). -// -// Revision 1.3 2002/01/23 10:28:16 mohor -// Link in the header changed. -// -// Revision 1.2 2001/10/19 08:43:51 mohor -// eth_timescale.v changed to timescale.v This is done because of the -// simulation of the few cores in a one joined project. -// -// Revision 1.1 2001/08/06 14:44:29 mohor -// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). -// Include files fixed to contain no path. -// File names and module names changed ta have a eth_ prologue in the name. -// File eth_timescale.v is used to define timescale -// All pin names on the top module are changed to contain _I, _O or _OE at the end. -// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O -// and Mdo_OE. The bidirectional signal must be created on the top level. This -// is done due to the ASIC tools. -// -// Revision 1.2 2001/08/02 09:25:31 mohor -// Unconnected signals are now connected. -// -// Revision 1.1 2001/07/30 21:23:42 mohor -// Directory structure changed. Files checked and joind together. -// -// Revision 1.3 2001/06/01 22:28:56 mohor -// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. -// -// - -module eth_miim -( - Clk, - Reset, - Divider, - NoPre, - CtrlData, - Rgad, - Fiad, - WCtrlData, - RStat, - ScanStat, - Mdio, - Mdc, - Busy, - Prsd, - LinkFail, - Nvalid, - WCtrlDataStart, - RStatStart, - UpdateMIIRX_DATAReg -); - -input Clk; // Host Clock -input Reset; // General Reset -input [7:0] Divider; // Divider for the host clock -input [15:0] CtrlData; // Control Data (to be written to the PHY reg.) -input [4:0] Rgad; // Register Address (within the PHY) -input [4:0] Fiad; // PHY Address -input NoPre; // No Preamble (no 32-bit preamble) -input WCtrlData; // Write Control Data operation -input RStat; // Read Status operation -input ScanStat; // Scan Status operation -inout Mdio; // MII Management Data In - -output Mdc; // MII Management Data Clock - -output Busy; // Busy Signal -output LinkFail; // Link Integrity Signal -output Nvalid; // Invalid Status (qualifier for the valid scan result) - -output [15:0] Prsd; // Read Status Data (data read from the PHY) - -output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register -output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register -output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data - -//parameter Tp = 1; - - -reg Nvalid; -reg EndBusy_d; // Pre-end Busy signal -reg EndBusy; // End Busy signal (stops the operation in progress) - -reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle -reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles -reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles -reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected) -reg WCtrlDataStart_q; -reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle -reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles - -reg RStat_q1; // Read Status operation delayed 1 Clk cycle -reg RStat_q2; // Read Status operation delayed 2 Clk cycles -reg RStat_q3; // Read Status operation delayed 3 Clk cycles -reg RStatStart; // Start Read Status Command (positive edge detected) -reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle -reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles - -reg ScanStat_q1; // Scan Status operation delayed 1 cycle -reg ScanStat_q2; // Scan Status operation delayed 2 cycles -reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn - -wire WriteDataOp; // Write Data Operation (positive edge detected) -wire ReadStatusOp; // Read Status Operation (positive edge detected) -wire ScanStatusOp; // Scan Status Operation (positive edge detected) -wire StartOp; // Start Operation (start of any of the preceding operations) -wire EndOp; // End of Operation - -reg InProgress; // Operation in progress -reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle -reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles -reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles - -reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress) -reg [6:0] BitCounter; // Bit Counter - - -wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register. -wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises. -wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal - - -wire LatchByte1_d2; -wire LatchByte0_d2; -reg LatchByte1_d; -reg LatchByte0_d; -reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register - -reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data - -wire Mdo; // MII Management Data Output -wire MdoEn; // MII Management Data Output Enable -wire Mdi; - -assign Mdi=Mdio; -assign Mdio=MdoEn?Mdo:1'bz; - - - -// Generation of the EndBusy signal. It is used for ending the MII Management operation. -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - begin - EndBusy_d <= 1'b0; - EndBusy <= 1'b0; - end - else - begin - EndBusy_d <= ~InProgress_q2 & InProgress_q3; - EndBusy <= EndBusy_d; - end -end - - -// Update MII RX_DATA register -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - UpdateMIIRX_DATAReg <= 0; - else - if(EndBusy & ~WCtrlDataStart_q) - UpdateMIIRX_DATAReg <= 1; - else - UpdateMIIRX_DATAReg <= 0; -end - - - -// Generation of the delayed signals used for positive edge triggering. -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - begin - WCtrlData_q1 <= 1'b0; - WCtrlData_q2 <= 1'b0; - WCtrlData_q3 <= 1'b0; - - RStat_q1 <= 1'b0; - RStat_q2 <= 1'b0; - RStat_q3 <= 1'b0; - - ScanStat_q1 <= 1'b0; - ScanStat_q2 <= 1'b0; - SyncStatMdcEn <= 1'b0; - end - else - begin - WCtrlData_q1 <= WCtrlData; - WCtrlData_q2 <= WCtrlData_q1; - WCtrlData_q3 <= WCtrlData_q2; - - RStat_q1 <= RStat; - RStat_q2 <= RStat_q1; - RStat_q3 <= RStat_q2; - - ScanStat_q1 <= ScanStat; - ScanStat_q2 <= ScanStat_q1; - if(MdcEn) - SyncStatMdcEn <= ScanStat_q2; - end -end - - -// Generation of the Start Commands (Write Control Data or Read Status) -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - begin - WCtrlDataStart <= 1'b0; - WCtrlDataStart_q <= 1'b0; - RStatStart <= 1'b0; - end - else - begin - if(EndBusy) - begin - WCtrlDataStart <= 1'b0; - RStatStart <= 1'b0; - end - else - begin - if(WCtrlData_q2 & ~WCtrlData_q3) - WCtrlDataStart <= 1'b1; - if(RStat_q2 & ~RStat_q3) - RStatStart <= 1'b1; - WCtrlDataStart_q <= WCtrlDataStart; - end - end -end - - -// Generation of the Nvalid signal (indicates when the status is invalid) -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - Nvalid <= 1'b0; - else - begin - if(~InProgress_q2 & InProgress_q3) - begin - Nvalid <= 1'b0; - end - else - begin - if(ScanStat_q2 & ~SyncStatMdcEn) - Nvalid <= 1'b1; - end - end -end - -// Signals used for the generation of the Operation signals (positive edge) -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - begin - WCtrlDataStart_q1 <= 1'b0; - WCtrlDataStart_q2 <= 1'b0; - - RStatStart_q1 <= 1'b0; - RStatStart_q2 <= 1'b0; - - InProgress_q1 <= 1'b0; - InProgress_q2 <= 1'b0; - InProgress_q3 <= 1'b0; - - LatchByte0_d <= 1'b0; - LatchByte1_d <= 1'b0; - - LatchByte <= 2'b00; - end - else - begin - if(MdcEn) - begin - WCtrlDataStart_q1 <= WCtrlDataStart; - WCtrlDataStart_q2 <= WCtrlDataStart_q1; - - RStatStart_q1 <= RStatStart; - RStatStart_q2 <= RStatStart_q1; - - LatchByte[0] <= LatchByte0_d; - LatchByte[1] <= LatchByte1_d; - - LatchByte0_d <= LatchByte0_d2; - LatchByte1_d <= LatchByte1_d2; - - InProgress_q1 <= InProgress; - InProgress_q2 <= InProgress_q1; - InProgress_q3 <= InProgress_q2; - end - end -end - - -// Generation of the Operation signals -assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2; -assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2; -assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2; -assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp; - -// Busy -reg Busy; -always @ (posedge Clk or posedge Reset) - if (Reset) - Busy <=0; - else if(WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid) - Busy <=1; - else - Busy <=0; - -//assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid; - - -// Generation of the InProgress signal (indicates when an operation is in progress) -// Generation of the WriteOp signal (indicates when a write is in progress) -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - begin - InProgress <= 1'b0; - WriteOp <= 1'b0; - end - else - begin - if(MdcEn) - begin - if(StartOp) - begin - if(~InProgress) - WriteOp <= WriteDataOp; - InProgress <= 1'b1; - end - else - begin - if(EndOp) - begin - InProgress <= 1'b0; - WriteOp <= 1'b0; - end - end - end - end -end - - - -// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted) -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - BitCounter[6:0] <= 7'h0; - else - begin - if(MdcEn) - begin - if(InProgress) - begin - if(NoPre & ( BitCounter == 7'h0 )) - BitCounter[6:0] <= 7'h21; - else - BitCounter[6:0] <= BitCounter[6:0] + 1'b1; - end - else - BitCounter[6:0] <= 7'h0; - end - end -end - - -// Operation ends when the Bit Counter reaches 63 -assign EndOp = BitCounter==63; - -assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20))); -assign ByteSelect[1] = InProgress & (BitCounter == 7'h28); -assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30); -assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38); - - -// Latch Byte selects which part of Read Status Data is updated from the shift register -assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37; -assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F; - -wire MdcEn_n; - -// Connecting the Clock Generator Module -eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc) - ); - -// Connecting the Shift Register Module -eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad), - .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte), - .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail) - ); - -// Connecting the Output Control Module -eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress), - .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre), - .Mdo(Mdo), .MdoEn(MdoEn) - ); - -endmodule diff --git a/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v b/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v deleted file mode 100644 index 3df6c560a..000000000 --- a/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v +++ /dev/null @@ -1,158 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// eth_outputcontrol.v //// -//// //// -//// This file is part of the Ethernet IP core project //// -//// http://www.opencores.org/projects/ethmac/ //// -//// //// -//// Author(s): //// -//// - Igor Mohor (igorM@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: eth_outputcontrol.v,v $ -// Revision 1.2 2005/12/13 12:54:49 maverickist -// first simulation passed -// -// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator -// no message -// -// Revision 1.2 2005/04/27 15:58:46 Administrator -// no message -// -// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator -// no message -// -// Revision 1.4 2002/07/09 20:11:59 mohor -// Comment removed. -// -// Revision 1.3 2002/01/23 10:28:16 mohor -// Link in the header changed. -// -// Revision 1.2 2001/10/19 08:43:51 mohor -// eth_timescale.v changed to timescale.v This is done because of the -// simulation of the few cores in a one joined project. -// -// Revision 1.1 2001/08/06 14:44:29 mohor -// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). -// Include files fixed to contain no path. -// File names and module names changed ta have a eth_ prologue in the name. -// File eth_timescale.v is used to define timescale -// All pin names on the top module are changed to contain _I, _O or _OE at the end. -// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O -// and Mdo_OE. The bidirectional signal must be created on the top level. This -// is done due to the ASIC tools. -// -// Revision 1.1 2001/07/30 21:23:42 mohor -// Directory structure changed. Files checked and joind together. -// -// Revision 1.3 2001/06/01 22:28:56 mohor -// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. -// -// - -module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn); - -input Clk; // Host Clock -input Reset; // General Reset -input WriteOp; // Write Operation Latch (When asserted, write operation is in progress) -input NoPre; // No Preamble (no 32-bit preamble) -input InProgress; // Operation in progress -input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal -input [6:0] BitCounter; // Bit Counter -input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls. - -output Mdo; // MII Management Data Output -output MdoEn; // MII Management Data Output Enable - -wire SerialEn; - -reg MdoEn_2d; -reg MdoEn_d; -reg MdoEn; - -reg Mdo_2d; -reg Mdo_d; -reg Mdo; // MII Management Data Output - - - -// Generation of the Serial Enable signal (enables the serialization of the data) -assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) ) - | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre )); - - -// Generation of the MdoEn signal -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - begin - MdoEn_2d <= 1'b0; - MdoEn_d <= 1'b0; - MdoEn <= 1'b0; - end - else - begin - if(MdcEn_n) - begin - MdoEn_2d <= SerialEn | InProgress & BitCounter<32; - MdoEn_d <= MdoEn_2d; - MdoEn <= MdoEn_d; - end - end -end - - -// Generation of the Mdo signal. -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - begin - Mdo_2d <= 1'b0; - Mdo_d <= 1'b0; - Mdo <= 1'b0; - end - else - begin - if(MdcEn_n) - begin - Mdo_2d <= ~SerialEn & BitCounter<32; - Mdo_d <= ShiftedBit | Mdo_2d; - Mdo <= Mdo_d; - end - end -end - - - -endmodule diff --git a/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v b/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v deleted file mode 100644 index 0b97bb7bc..000000000 --- a/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v +++ /dev/null @@ -1,159 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// eth_shiftreg.v //// -//// //// -//// This file is part of the Ethernet IP core project //// -//// http://www.opencores.org/projects/ethmac/ //// -//// //// -//// Author(s): //// -//// - Igor Mohor (igorM@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: eth_shiftreg.v,v $ -// Revision 1.2 2005/12/13 12:54:49 maverickist -// first simulation passed -// -// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator -// no message -// -// Revision 1.2 2005/04/27 15:58:47 Administrator -// no message -// -// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator -// no message -// -// Revision 1.5 2002/08/14 18:16:59 mohor -// LinkFail signal was not latching appropriate bit. -// -// Revision 1.4 2002/03/02 21:06:01 mohor -// LinkFail signal was not latching appropriate bit. -// -// Revision 1.3 2002/01/23 10:28:16 mohor -// Link in the header changed. -// -// Revision 1.2 2001/10/19 08:43:51 mohor -// eth_timescale.v changed to timescale.v This is done because of the -// simulation of the few cores in a one joined project. -// -// Revision 1.1 2001/08/06 14:44:29 mohor -// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). -// Include files fixed to contain no path. -// File names and module names changed ta have a eth_ prologue in the name. -// File eth_timescale.v is used to define timescale -// All pin names on the top module are changed to contain _I, _O or _OE at the end. -// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O -// and Mdo_OE. The bidirectional signal must be created on the top level. This -// is done due to the ASIC tools. -// -// Revision 1.1 2001/07/30 21:23:42 mohor -// Directory structure changed. Files checked and joind together. -// -// Revision 1.3 2001/06/01 22:28:56 mohor -// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. -// -// - -module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect, - LatchByte, ShiftedBit, Prsd, LinkFail); - - -input Clk; // Input clock (Host clock) -input Reset; // Reset signal -input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. -input Mdi; // MII input data -input [4:0] Fiad; // PHY address -input [4:0] Rgad; // Register address (within the selected PHY) -input [15:0]CtrlData; // Control data (data to be written to the PHY) -input WriteOp; // The current operation is a PHY register write operation -input [3:0] ByteSelect; // Byte select -input [1:0] LatchByte; // Byte select for latching (read operation) - -output ShiftedBit; // Bit shifted out of the shift register -output[15:0]Prsd; // Read Status Data (data read from the PHY) -output LinkFail; // Link Integrity Signal - -reg [7:0] ShiftReg; // Shift register for shifting the data in and out -reg [15:0]Prsd; -reg LinkFail; - - - - -// ShiftReg[7:0] :: Shift Register Data -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - begin - ShiftReg[7:0] <= 8'h0; - Prsd[15:0] <= 16'h0; - LinkFail <= 1'b0; - end - else - begin - if(MdcEn_n) - begin - if(|ByteSelect) - begin - case (ByteSelect[3:0]) - 4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]}; - 4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10}; - 4'h4 : ShiftReg[7:0] <= CtrlData[15:8]; - 4'h8 : ShiftReg[7:0] <= CtrlData[7:0]; - default : ShiftReg[7:0] <= 8'h0; - endcase - end - else - begin - ShiftReg[7:0] <= {ShiftReg[6:0], Mdi}; - if(LatchByte[0]) - begin - Prsd[7:0] <= {ShiftReg[6:0], Mdi}; - if(Rgad == 5'h01) - LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet - end - else - begin - if(LatchByte[1]) - Prsd[15:8] <= {ShiftReg[6:0], Mdi}; - end - end - end - end -end - - -assign ShiftedBit = ShiftReg[7]; - - -endmodule diff --git a/fpga/usrp2/simple_gemac/rxmac_to_ll8.v b/fpga/usrp2/simple_gemac/rxmac_to_ll8.v deleted file mode 100644 index 5acb08bb7..000000000 --- a/fpga/usrp2/simple_gemac/rxmac_to_ll8.v +++ /dev/null @@ -1,71 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module rxmac_to_ll8 - (input clk, input reset, input clear, - input [7:0] rx_data, input rx_valid, input rx_error, input rx_ack, - output [7:0] ll_data, output ll_sof, output ll_eof, output ll_error, output ll_src_rdy, input ll_dst_rdy ); - - reg [2:0] xfer_state; - - localparam XFER_IDLE = 0; - localparam XFER_ACTIVE = 1; - localparam XFER_ERROR = 2; - localparam XFER_ERROR2 = 3; - localparam XFER_OVERRUN = 4; - localparam XFER_OVERRUN2 = 5; - - assign ll_data = rx_data; - assign ll_src_rdy = ((rx_valid & (xfer_state != XFER_OVERRUN2) ) - | (xfer_state == XFER_ERROR) - | (xfer_state == XFER_OVERRUN)); - assign ll_sof = ((xfer_state==XFER_IDLE)|(xfer_state==XFER_ERROR)|(xfer_state==XFER_OVERRUN)); - assign ll_eof = (rx_ack | (xfer_state==XFER_ERROR) | (xfer_state==XFER_OVERRUN)); - assign ll_error = (xfer_state == XFER_ERROR)|(xfer_state==XFER_OVERRUN); - - always @(posedge clk) - if(reset | clear) - xfer_state <= XFER_IDLE; - else - case(xfer_state) - XFER_IDLE : - if(rx_valid) - xfer_state <= XFER_ACTIVE; - XFER_ACTIVE : - if(rx_error) - xfer_state <= XFER_ERROR; - else if(~rx_valid) - xfer_state <= XFER_IDLE; - else if(~ll_dst_rdy) - xfer_state <= XFER_OVERRUN; - XFER_ERROR : - if(ll_dst_rdy) - xfer_state <= XFER_ERROR2; - XFER_ERROR2 : - if(~rx_error) - xfer_state <= XFER_IDLE; - XFER_OVERRUN : - if(ll_dst_rdy) - xfer_state <= XFER_OVERRUN2; - XFER_OVERRUN2 : - if(~rx_valid) - xfer_state <= XFER_IDLE; - endcase // case (xfer_state) - - -endmodule // rxmac_to_ll8 diff --git a/fpga/usrp2/simple_gemac/simple_gemac.v b/fpga/usrp2/simple_gemac/simple_gemac.v deleted file mode 100644 index ec13d3c96..000000000 --- a/fpga/usrp2/simple_gemac/simple_gemac.v +++ /dev/null @@ -1,81 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module simple_gemac - (input clk125, input reset, - // GMII - output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD, - input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD, - - // Flow Control Interface - input pause_req, input [15:0] pause_time_req, input pause_respect_en, - - // Settings - input [47:0] ucast_addr, input [47:0] mcast_addr, - input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause, input pass_all, - - // RX Client Interface - output rx_clk, output [7:0] rx_data, output rx_valid, output rx_error, output rx_ack, - - // TX Client Interface - output tx_clk, input [7:0] tx_data, input tx_valid, input tx_error, output tx_ack, - - output [31:0] debug - ); - - localparam SGE_IFG = 8'd12; // 12 should be the absolute minimum - - wire rst_rxclk, rst_txclk; - reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(rst_txclk)); - reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rst_rxclk)); - - wire [15:0] pause_quanta_rcvd; - wire pause_rcvd, pause_apply, paused; - - simple_gemac_tx simple_gemac_tx - (.clk125(clk125),.reset(rst_txclk), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .tx_clk(tx_clk), .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack), - .ifg(SGE_IFG), .mac_addr(ucast_addr), - .pause_req(pause_req), .pause_time(pause_time_req), // We request flow control - .pause_apply(pause_apply), .paused(paused) // We respect flow control - ); - - simple_gemac_rx simple_gemac_rx - (.reset(rst_rxclk), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .rx_clk(rx_clk), .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), - .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), - .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), - .pass_pause(pass_pause), .pass_all(pass_all), - .pause_quanta_rcvd(pause_quanta_rcvd), .pause_rcvd(pause_rcvd), - .debug(debug) - ); - - flow_ctrl_tx flow_ctrl_tx - (.rst(rst_txclk), .tx_clk(tx_clk), - .tx_pause_en(pause_respect_en), - .pause_quanta(pause_quanta_rcvd), // 16 bit value - .pause_quanta_val(pause_rcvd), - .pause_apply(pause_apply), - .paused(paused) - ); - -endmodule // simple_gemac diff --git a/fpga/usrp2/simple_gemac/simple_gemac_rx.v b/fpga/usrp2/simple_gemac/simple_gemac_rx.v deleted file mode 100644 index e6c0424bd..000000000 --- a/fpga/usrp2/simple_gemac/simple_gemac_rx.v +++ /dev/null @@ -1,196 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module simple_gemac_rx - (input reset, - input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD, - output rx_clk, output [7:0] rx_data, output reg rx_valid, output rx_error, output reg rx_ack, - input [47:0] ucast_addr, input [47:0] mcast_addr, - input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause, input pass_all, - output reg [15:0] pause_quanta_rcvd, output pause_rcvd, - output [31:0] debug ); - - localparam RX_IDLE = 0; - localparam RX_PREAMBLE = 1; - localparam RX_FRAME = 2; - localparam RX_GOODFRAME = 3; - localparam RX_DO_PAUSE = 4; - localparam RX_ERROR = 5; - localparam RX_DROP = 6; - - localparam RX_PAUSE = 16; - localparam RX_PAUSE_CHK88 = RX_PAUSE + 5; - localparam RX_PAUSE_CHK08 = RX_PAUSE_CHK88 + 1; - localparam RX_PAUSE_CHK00 = RX_PAUSE_CHK08 + 1; - localparam RX_PAUSE_CHK01 = RX_PAUSE_CHK00 + 1; - localparam RX_PAUSE_STORE_MSB = RX_PAUSE_CHK01 + 1; - localparam RX_PAUSE_STORE_LSB = RX_PAUSE_STORE_MSB + 1; - localparam RX_PAUSE_WAIT_CRC = RX_PAUSE_STORE_LSB + 1; - - reg [7:0] rxd_d1; - reg rx_dv_d1, rx_er_d1; - assign rx_clk = GMII_RX_CLK; - - always @(posedge rx_clk) - begin - rx_dv_d1 <= GMII_RX_DV; - rx_er_d1 <= GMII_RX_ER; - rxd_d1 <= GMII_RXD; - end - - reg [7:0] rx_state; - wire [7:0] rxd_del; - wire rx_dv_del, rx_er_del; - reg go_filt; - - wire match_crc; - wire clear_crc = rx_state == RX_IDLE; - wire calc_crc = (rx_state == RX_FRAME) | rx_state[7:4]==4'h1; - - localparam DELAY = 6; - delay_line #(.WIDTH(10)) rx_delay - (.clk(rx_clk), .delay(DELAY), .din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_del,rxd_del})); - - always @(posedge rx_clk) - if(reset) - rx_ack <= 0; - else - rx_ack <= (rx_state == RX_GOODFRAME); - - wire is_ucast, is_bcast, is_mcast, is_pause, is_any_ucast; - wire keep_packet = (pass_all & is_any_ucast) | (pass_ucast & is_ucast) | (pass_mcast & is_mcast) | - (pass_bcast & is_bcast) | (pass_pause & is_pause); - - assign rx_data = rxd_del; - assign rx_error = (rx_state == RX_ERROR); - - always @(posedge rx_clk) - if(reset) - rx_valid <= 0; - else if(keep_packet) - rx_valid <= 1; - else if((rx_state == RX_IDLE)|(rx_state == RX_ERROR)) - rx_valid <= 0; - - address_filter af_ucast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1), - .address(ucast_addr), .match(is_ucast), .done()); - address_filter af_mcast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1), - .address(mcast_addr), .match(is_mcast), .done()); - address_filter af_bcast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1), - .address(48'hFFFF_FFFF_FFFF), .match(is_bcast), .done()); - address_filter af_pause (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1), - .address(48'h0180_c200_0001), .match(is_pause), .done()); - address_filter_promisc af_promisc (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1), - .match(is_any_ucast), .done()); - - always @(posedge rx_clk) - go_filt <= (rx_state==RX_PREAMBLE) & (rxd_d1 == 8'hD5); - - reg [15:0] pkt_len_ctr; - always @(posedge rx_clk) - if(reset |(rx_state == RX_IDLE)) - pkt_len_ctr <= 0; - else - pkt_len_ctr <= pkt_len_ctr + 1; - - localparam MIN_PAUSE_LEN = 71; // 6 - wire pkt_long_enough = (pkt_len_ctr >= MIN_PAUSE_LEN); - always @(posedge rx_clk) - if(reset) - rx_state <= RX_IDLE; - else - if(rx_er_d1) // | (~pkt_long_enough & ~rx_dv_d1) & (rx_state != RX_IDLE)) - rx_state <= RX_ERROR; - else - case(rx_state) - RX_IDLE : - if(rx_dv_d1) - if(rxd_d1 == 8'h55) - rx_state <= RX_PREAMBLE; - else - rx_state <= RX_ERROR; - RX_PREAMBLE : - if(~rx_dv_d1) - rx_state <= RX_ERROR; - else if(rxd_d1 == 8'hD5) - rx_state <= RX_FRAME; - else if(rxd_d1 != 8'h55) - rx_state <= RX_ERROR; - RX_FRAME : - if(is_pause) - rx_state <= RX_PAUSE; - else if(~rx_dv_d1) - if(match_crc) - rx_state <= RX_GOODFRAME; - else - rx_state <= RX_ERROR; - RX_PAUSE_CHK88 : - if(rxd_d1 != 8'h88) - rx_state <= RX_DROP; - else - rx_state <= RX_PAUSE_CHK08; - RX_PAUSE_CHK08 : - if(rxd_d1 != 8'h08) - rx_state <= RX_DROP; - else - rx_state <= RX_PAUSE_CHK00; - RX_PAUSE_CHK00 : - if(rxd_d1 != 8'h00) - rx_state <= RX_DROP; - else - rx_state <= RX_PAUSE_CHK01; - RX_PAUSE_CHK01 : - if(rxd_d1 != 8'h01) - rx_state <= RX_DROP; - else - rx_state <= RX_PAUSE_STORE_MSB; - RX_PAUSE_WAIT_CRC : - if(pkt_long_enough) - if(match_crc) - rx_state <= RX_DO_PAUSE; - else - rx_state <= RX_DROP; - RX_DO_PAUSE : - rx_state <= RX_IDLE; - RX_GOODFRAME : - rx_state <= RX_IDLE; - RX_DROP, RX_ERROR : - if(~rx_dv_d1) - rx_state <= RX_IDLE; - default - rx_state <= rx_state + 1; - endcase // case (rx_state) - - assign pause_rcvd = (rx_state == RX_DO_PAUSE); - crc crc_check(.clk(rx_clk),.reset(reset),.clear(clear_crc), - .data(rxd_d1),.calc(calc_crc),.crc_out(),.match(match_crc)); - - always @(posedge rx_clk) - if(reset) - pause_quanta_rcvd <= 0; - else if(rx_state == RX_PAUSE_STORE_MSB) - pause_quanta_rcvd[15:8] <= rxd_d1; - else if(rx_state == RX_PAUSE_STORE_LSB) - pause_quanta_rcvd[7:0] <= rxd_d1; - - assign rx_clk = GMII_RX_CLK; - - assign debug = rx_state; - -endmodule // simple_gemac_rx diff --git a/fpga/usrp2/simple_gemac/simple_gemac_tb.v b/fpga/usrp2/simple_gemac/simple_gemac_tb.v deleted file mode 100644 index ed7d796dc..000000000 --- a/fpga/usrp2/simple_gemac/simple_gemac_tb.v +++ /dev/null @@ -1,217 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module simple_gemac_tb; -`include "eth_tasks.v" - - reg clk = 0; - reg reset = 1; - - initial #1000 reset = 0; - always #50 clk = ~clk; - - wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK; - wire [7:0] GMII_RXD, GMII_TXD; - - wire rx_valid, rx_error, rx_ack; - wire tx_ack, tx_valid, tx_error; - - wire [7:0] rx_data, tx_data; - - reg [15:0] pause_time; - reg pause_req = 0; - - wire GMII_RX_CLK = GMII_GTX_CLK; - - reg [7:0] FORCE_DAT_ERR = 0; - reg FORCE_ERR = 0; - - // Loopback - assign GMII_RX_DV = GMII_TX_EN; - assign GMII_RX_ER = GMII_TX_ER | FORCE_ERR; - assign GMII_RXD = GMII_TXD ^ FORCE_DAT_ERR; - - wire [47:0] ucast_addr = 48'hF1F2_F3F4_F5F6; - wire [47:0] mcast_addr = 0; - wire pass_ucast =1, pass_mcast=0, pass_bcast=1, pass_pause=0, pass_all=0; - - simple_gemac simple_gemac - (.clk125(clk), .reset(reset), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .pause_req(pause_req), .pause_time(pause_time), .pause_en(1), - .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), - .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), - .pass_pause(pass_pause), .pass_all(pass_all), - .rx_clk(rx_clk), .rx_data(rx_data), - .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), - .tx_clk(tx_clk), .tx_data(tx_data), - .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack) - ); - - wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; - wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2; - reg rx_ll_dst_rdy2 = 1; - wire [7:0] rx_ll_data, rx_ll_data2; - wire rx_ll_error, rx_ll_error2; - - rxmac_to_ll8 rx_adapt - (.clk(clk), .reset(reset), .clear(0), - .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), - .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error), - .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy)); - - ll8_shortfifo rx_sfifo - (.clk(clk), .reset(reset), .clear(0), - .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof), - .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy), - .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2), - .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2)); - - wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; - reg tx_ll_sof2=0, tx_ll_eof2=0; - reg tx_ll_src_rdy2 = 0; - wire tx_ll_dst_rdy2; - wire [7:0] tx_ll_data; - reg [7:0] tx_ll_data2 = 0; - wire tx_ll_error; - wire tx_ll_error2 = 0; - - ll8_shortfifo tx_sfifo - (.clk(clk), .reset(reset), .clear(clear), - .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2), - .error_i(tx_ll_error2), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2), - .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof), - .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy)); - - ll8_to_txmac ll8_to_txmac - (.clk(clk), .reset(reset), .clear(clear), - .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof), - .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy), - .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)); - - initial $dumpfile("simple_gemac_tb.vcd"); - initial $dumpvars(0,simple_gemac_tb); - - integer i; - reg [7:0] pkt_rom[0:65535]; - reg [1023:0] ROMFile; - - initial - for (i=0;i<65536;i=i+1) - pkt_rom[i] <= 8'h0; - - initial - begin - @(negedge reset); - repeat (10) - @(posedge clk); - SendFlowCtrl(16'h0007); // Send flow control - @(posedge clk); - #30000; - @(posedge clk); - SendFlowCtrl(16'h0009); // Increas flow control before it expires - #10000; - @(posedge clk); - SendFlowCtrl(16'h0000); // Cancel flow control before it expires - @(posedge clk); - - SendPacket_to_ll8(8'hAA,10); // This packet gets dropped by the filters - repeat (10) - @(posedge clk); - - SendPacketFromFile_ll8(60,0,0); // The rest are valid packets - repeat (10) - @(posedge clk); - - SendPacketFromFile_ll8(61,0,0); - repeat (10) - @(posedge clk); - SendPacketFromFile_ll8(62,0,0); - repeat (10) - @(posedge clk); - SendPacketFromFile_ll8(63,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_ll8(64,0,0); - repeat (10) - @(posedge clk); - SendPacketFromFile_ll8(59,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_ll8(58,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_ll8(100,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_ll8(200,150,30); // waiting 14 empties the fifo, 15 underruns - repeat (1) - @(posedge clk); - SendPacketFromFile_ll8(100,0,30); - #10000 $finish; - end - - // Force a CRC error - initial - begin - #90000; - @(posedge clk); - FORCE_DAT_ERR <= 8'h10; - @(posedge clk); - FORCE_DAT_ERR <= 8'h00; - end - - // Force an RX_ER error (i.e. link loss) - initial - begin - #116000; - @(posedge clk); - FORCE_ERR <= 1; - @(posedge clk); - FORCE_ERR <= 0; - end - - // Cause receive fifo to fill, causing an RX overrun - initial - begin - #126000; - @(posedge clk); - rx_ll_dst_rdy2 <= 0; - repeat (30) // Repeat of 14 fills the shortfifo, but works. 15 overflows - @(posedge clk); - rx_ll_dst_rdy2 <= 1; - end - - // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun - // Still need to test: CRC errors on Pause Frames - - always @(posedge clk) - if(rx_ll_src_rdy2 & rx_ll_dst_rdy2) - begin - if(rx_ll_sof2 & ~rx_ll_eof2) - $display("RX-PKT-START %d",$time); - $display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2); - if(rx_ll_eof2 & ~rx_ll_sof2) - $display("RX-PKT-END %d",$time); - end - -endmodule // simple_gemac_tb diff --git a/fpga/usrp2/simple_gemac/simple_gemac_tx.v b/fpga/usrp2/simple_gemac/simple_gemac_tx.v deleted file mode 100644 index ecabc3dad..000000000 --- a/fpga/usrp2/simple_gemac/simple_gemac_tx.v +++ /dev/null @@ -1,271 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module simple_gemac_tx - (input clk125, input reset, - output GMII_GTX_CLK, output reg GMII_TX_EN, output reg GMII_TX_ER, output reg [7:0] GMII_TXD, - output tx_clk, input [7:0] tx_data, input tx_valid, input tx_error, output tx_ack, - input [7:0] ifg, input [47:0] mac_addr, - input pause_req, input [15:0] pause_time, - input pause_apply, output reg paused - ); - - reg tx_en_pre, tx_er_pre; - reg [7:0] txd_pre; - - assign GMII_GTX_CLK = clk125; - assign tx_clk = clk125; - - reg [7:0] tx_state; - reg [7:0] ifg_ctr; - reg [15:0] frame_len_ctr; - reg [7:0] pause_ctr, pause_dat; - - wire in_ifg = (ifg_ctr != 0); - - wire [31:0] crc_out; - - localparam TX_IDLE = 0; - localparam TX_PREAMBLE = 1; - localparam TX_SOF_DEL = TX_PREAMBLE + 7; - localparam TX_FIRSTBYTE = TX_SOF_DEL + 1; - localparam TX_IN_FRAME = TX_FIRSTBYTE + 1; - localparam TX_IN_FRAME_2 = TX_IN_FRAME + 1; - localparam TX_PAD = TX_IN_FRAME_2 + 1; - localparam TX_CRC_0 = 16; - localparam TX_CRC_1 = TX_CRC_0 + 1; - localparam TX_CRC_2 = TX_CRC_0 + 2; - localparam TX_CRC_3 = TX_CRC_0 + 3; - localparam TX_ERROR = 32; - localparam TX_PAUSE = 55; - localparam TX_PAUSE_SOF = TX_PAUSE + 7; - localparam TX_PAUSE_FIRST = TX_PAUSE_SOF + 1; - localparam TX_PAUSE_END = TX_PAUSE_SOF + 18; - - localparam MIN_FRAME_LEN = 64 + 8 - 4; // Min frame length includes preamble but not CRC - localparam MAX_FRAME_LEN = 8192; // How big are the jumbo frames we want to handle? - always @(posedge tx_clk) - if(reset |(tx_state == TX_IDLE)) - frame_len_ctr <= 0; - else - frame_len_ctr <= frame_len_ctr + 1; - - reg send_pause; - reg [15:0] pause_time_held; - - always @(posedge tx_clk) - if(reset) - send_pause <= 0; - else if(pause_req) - send_pause <= 1; - else if(tx_state == TX_PAUSE) - send_pause <= 0; - - always @(posedge tx_clk) - if(pause_req) - pause_time_held <= pause_time; - - always @(posedge tx_clk) - if(reset) - tx_state <= TX_IDLE; - else - case(tx_state) - TX_IDLE : - if(~in_ifg) - if(send_pause) - tx_state <= TX_PAUSE; - else if(tx_valid & ~pause_apply) - tx_state <= TX_PREAMBLE; - TX_FIRSTBYTE : - if(tx_error) - tx_state <= TX_ERROR; // underrun - else if(~tx_valid) - tx_state <= TX_PAD; - else - tx_state <= TX_IN_FRAME; - TX_IN_FRAME : - if(tx_error) - tx_state <= TX_ERROR; // underrun - else if(~tx_valid) - tx_state <= TX_PAD; - else if(frame_len_ctr == MIN_FRAME_LEN - 1) - tx_state <= TX_IN_FRAME_2; - TX_IN_FRAME_2 : - if(tx_error) - tx_state <= TX_ERROR; // underrun - else if(~tx_valid) - tx_state <= TX_CRC_0; - TX_PAD : - if(frame_len_ctr == MIN_FRAME_LEN) - tx_state <= TX_CRC_0; - TX_CRC_3 : - tx_state <= TX_IDLE; - TX_ERROR : - tx_state <= TX_IDLE; - TX_PAUSE_END : - tx_state <= TX_PAD; - default : - tx_state <= tx_state + 1; - endcase // case (tx_state) - - always @(posedge tx_clk) - if(reset) - begin - tx_en_pre <= 0; - tx_er_pre <= 0; - txd_pre <= 0; - end - else - casex(tx_state) - TX_IDLE : - begin - tx_en_pre <= 0; - tx_er_pre <= 0; - txd_pre <= 0; - end - TX_PREAMBLE, TX_PAUSE : - begin - txd_pre <= 8'h55; - tx_en_pre <= 1; - end - TX_SOF_DEL, TX_PAUSE_SOF : - txd_pre <= 8'hD5; - TX_FIRSTBYTE, TX_IN_FRAME, TX_IN_FRAME_2 : - txd_pre <= tx_valid ? tx_data : 0; - TX_ERROR : - begin - tx_er_pre <= 1; - txd_pre <= 0; - end - TX_CRC_3 : - tx_en_pre <= 0; - TX_PAD : - txd_pre <= 0; - TX_PAUSE_FIRST, 8'b01xx_xxxx : // In Pause Frame - txd_pre <= pause_dat; - endcase // case (tx_state) - - localparam SGE_FLOW_CTRL_ADDR = 48'h01_80_C2_00_00_01; - always @(posedge tx_clk) - case(tx_state) - TX_PAUSE_SOF : - pause_dat <= SGE_FLOW_CTRL_ADDR[47:40]; // Note everything must be 1 cycle early - TX_PAUSE_SOF + 1: - pause_dat <= SGE_FLOW_CTRL_ADDR[39:32]; - TX_PAUSE_SOF + 2: - pause_dat <= SGE_FLOW_CTRL_ADDR[31:24]; - TX_PAUSE_SOF + 3: - pause_dat <= SGE_FLOW_CTRL_ADDR[23:16]; - TX_PAUSE_SOF + 4: - pause_dat <= SGE_FLOW_CTRL_ADDR[15:8]; - TX_PAUSE_SOF + 5: - pause_dat <= SGE_FLOW_CTRL_ADDR[7:0]; - TX_PAUSE_SOF + 6: - pause_dat <= mac_addr[47:40]; - TX_PAUSE_SOF + 7: - pause_dat <= mac_addr[39:32]; - TX_PAUSE_SOF + 8: - pause_dat <= mac_addr[31:24]; - TX_PAUSE_SOF + 9: - pause_dat <= mac_addr[23:16]; - TX_PAUSE_SOF + 10: - pause_dat <= mac_addr[15:8]; - TX_PAUSE_SOF + 11: - pause_dat <= mac_addr[7:0]; - TX_PAUSE_SOF + 12: - pause_dat <= 8'h88; // Type = 8808 = MAC ctrl frame - TX_PAUSE_SOF + 13: - pause_dat <= 8'h08; - TX_PAUSE_SOF + 14: - pause_dat <= 8'h00; // Opcode = 0001 = PAUSE - TX_PAUSE_SOF + 15: - pause_dat <= 8'h01; - TX_PAUSE_SOF + 16: - pause_dat <= pause_time_held[15:8]; - TX_PAUSE_SOF + 17: - pause_dat <= pause_time_held[7:0]; - endcase // case (tx_state) - - wire start_ifg = (tx_state == TX_CRC_3); - always @(posedge tx_clk) - if(reset) - ifg_ctr <= 100; - else if(start_ifg) - ifg_ctr <= ifg; - else if(ifg_ctr != 0) - ifg_ctr <= ifg_ctr - 1; - - wire clear_crc = (tx_state == TX_IDLE); - - wire calc_crc = - (tx_state==TX_IN_FRAME) | - (tx_state==TX_IN_FRAME_2) | - (tx_state==TX_PAD) | - (tx_state[6]); - - crc crc(.clk(tx_clk), .reset(reset), .clear(clear_crc), - .data(txd_pre), .calc(calc_crc), .crc_out(crc_out)); - - assign tx_ack = (tx_state == TX_FIRSTBYTE); - - always @(posedge tx_clk) - begin - GMII_TX_EN <= tx_en_pre; - GMII_TX_ER <= tx_er_pre; - case(tx_state) - TX_CRC_0 : - GMII_TXD <= crc_out[31:24]; - TX_CRC_1 : - GMII_TXD <= crc_out[23:16]; - TX_CRC_2 : - GMII_TXD <= crc_out[15:8]; - TX_CRC_3 : - GMII_TXD <= crc_out[7:0]; - default : - GMII_TXD <= txd_pre; - endcase // case (tx_state) - end - - // report that we are paused only when we get back to IDLE - always @(posedge tx_clk) - if(reset) - paused <= 0; - else if(~pause_apply) - paused <= 0; - else if(tx_state == TX_IDLE) - paused <= 1; - -endmodule // simple_gemac_tx - -// Testing code -/* - reg [7:0] crc_ctr; - reg calc_crc_d1; - always @(posedge tx_clk) - calc_crc_d1 <= calc_crc; - - always @(posedge tx_clk) - if(reset) - crc_ctr <= 0; - else if(calc_crc) - crc_ctr <= crc_ctr+1; - else if(calc_crc_d1) - $display("CRC COUNT = %d",crc_ctr); - else - crc_ctr <= 0; -*/ diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wb.v b/fpga/usrp2/simple_gemac/simple_gemac_wb.v deleted file mode 100644 index 0ddb8398a..000000000 --- a/fpga/usrp2/simple_gemac/simple_gemac_wb.v +++ /dev/null @@ -1,179 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module wb_reg - #(parameter ADDR=0, - parameter DEFAULT=0, - parameter WIDTH=32) - (input clk, input rst, - input [5:0] adr, input wr_acc, - input [31:0] dat_i, output reg [WIDTH-1:0] dat_o); - - always @(posedge clk) - if(rst) - dat_o <= DEFAULT; - else if(wr_acc & (adr == ADDR)) - dat_o <= dat_i[WIDTH-1:0]; - -endmodule // wb_reg - - - -module simple_gemac_wb - (input wb_clk, input wb_rst, - input wb_cyc, input wb_stb, output reg wb_ack, input wb_we, - input [7:0] wb_adr, input [31:0] wb_dat_i, output reg [31:0] wb_dat_o, - - inout mdio, output mdc, - output [47:0] ucast_addr, output [47:0] mcast_addr, - output pass_ucast, output pass_mcast, output pass_bcast, - output pass_pause, output pass_all, - output pause_respect_en, output pause_request_en, - output [15:0] pause_time, output [15:0] pause_thresh ); - - wire acc = wb_cyc & wb_stb; - wire wr_acc = wb_cyc & wb_stb & wb_we; - wire rd_acc = wb_cyc & wb_stb & ~wb_we; - - always @(posedge wb_clk) - if(wb_rst) - wb_ack <= 0; - else - wb_ack <= acc & ~wb_ack; - - wire [6:0] misc_settings; - assign {pause_request_en, pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_respect_en} = misc_settings; - - wb_reg #(.ADDR(0),.DEFAULT(7'b0111011),.WIDTH(7)) - wb_reg_settings (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o(misc_settings) ); - wb_reg #(.ADDR(1),.DEFAULT(0),.WIDTH(16)) - wb_reg_ucast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o(ucast_addr[47:32]) ); - wb_reg #(.ADDR(2),.DEFAULT(0),.WIDTH(32)) - wb_reg_ucast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o(ucast_addr[31:0]) ); - wb_reg #(.ADDR(3),.DEFAULT(0),.WIDTH(16)) - wb_reg_mcast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o(mcast_addr[47:32]) ); - wb_reg #(.ADDR(4),.DEFAULT(0),.WIDTH(32)) - wb_reg_mcast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o(mcast_addr[31:0]) ); - - //MII to CPU - wire [7:0] Divider; // Divider for the host clock - wire [15:0] CtrlData; // Control Data (to be written to the PHY reg.) - wire [4:0] Rgad; // Register Address (within the PHY) - wire [4:0] Fiad; // PHY Address - wire NoPre; // No Preamble (no 32-bit preamble) - wire WCtrlData; // Write Control Data operation - wire RStat; // Read Status operation - wire ScanStat; // Scan Status operation - wire Busy; // Busy Signal - wire LinkFail; // Link Integrity Signal - wire Nvalid; // Invalid Status (qualifier for the valid scan result) - wire [15:0] Prsd; // Read Status Data (data read from the PHY) - wire WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register - wire RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register - wire UpdateMIIRX_DATAReg; // Updates MII RX_DATA register with read data - - // registers for controlling the MII interface - reg [2:0] MIICOMMAND; - wire [12:0] MIIADDRESS; - reg [15:0] MIIRX_DATA; - wire [2:0] MIISTATUS; - - wb_reg #(.ADDR(5),.DEFAULT(0),.WIDTH(9)) - wb_reg_miimoder (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o({NoPre,Divider}) ); - - wb_reg #(.ADDR(6),.DEFAULT(0),.WIDTH(13)) - wb_reg_miiaddr (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o(MIIADDRESS) ); - - wb_reg #(.ADDR(7),.DEFAULT(0),.WIDTH(16)) - wb_reg_miidata (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o(CtrlData) ); - - // MIICOMMAND register - needs special treatment because of auto-resetting bits - always @ (posedge wb_clk) - if (wb_rst) - MIICOMMAND <= 0; - else - if (wr_acc & (wb_adr[7:2] == 6'd8)) - MIICOMMAND <= wb_dat_i; - else - begin - if ( WCtrlDataStart ) - MIICOMMAND[2] <= 0; - if ( RStatStart ) - MIICOMMAND[1] <= 0; - end - - // MIIRX_DATA register - always @(posedge wb_clk) - if (wb_rst) - MIIRX_DATA <= 0; - else - if (UpdateMIIRX_DATAReg ) - MIIRX_DATA <= Prsd; - - // MIICOMMAND - assign WCtrlData = MIICOMMAND[2]; - assign RStat = MIICOMMAND[1]; - assign ScanStat = MIICOMMAND[0]; - // MIIADDRESS - assign Rgad = MIIADDRESS[12:8]; - assign Fiad = MIIADDRESS[4:0]; - // MIISTATUS - assign MIISTATUS[2:0] = { Nvalid, Busy, LinkFail }; - - eth_miim eth_miim - (.Clk(wb_clk), .Reset(wb_rst), - .Divider(Divider), .NoPre(NoPre), .CtrlData(CtrlData), .Rgad(Rgad), .Fiad(Fiad), - .WCtrlData(WCtrlData), .RStat(RStat), .ScanStat(ScanStat), .Mdio(mdio), .Mdc(mdc), - .Busy(Busy), .Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(Nvalid), - .WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), - .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) ); - - wb_reg #(.ADDR(11),.DEFAULT(0),.WIDTH(16)) - wb_reg_pausetime (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o(pause_time) ); - - wb_reg #(.ADDR(12),.DEFAULT(0),.WIDTH(16)) - wb_reg_pausethresh (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o(pause_thresh) ); - - always @(posedge wb_clk) - case(wb_adr[7:2]) - //0 : wb_dat_o <= misc_settings; - //1 : wb_dat_o <= ucast_addr[47:32]; - //2 : wb_dat_o <= ucast_addr[31:0]; - //3 : wb_dat_o <= mcast_addr[47:32]; - //4 : wb_dat_o <= mcast_addr[31:0]; - //5 : wb_dat_o <= {NoPre,Divider}; - //6 : wb_dat_o <= MIIADDRESS; - //7 : wb_dat_o <= CtrlData; - 8 : wb_dat_o <= MIICOMMAND; - 9 : wb_dat_o <= MIISTATUS; - 10: wb_dat_o <= MIIRX_DATA; - //11: wb_dat_o <= pause_time; - //12: wb_dat_o <= pause_thresh; - endcase // case (wb_adr[7:2]) - -endmodule // simple_gemac_wb diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.build b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.build deleted file mode 100755 index 9293deca6..000000000 --- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.build +++ /dev/null @@ -1 +0,0 @@ -iverilog -Wimplict -Wportbind -y ../fifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v deleted file mode 100644 index ec09379ed..000000000 --- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v +++ /dev/null @@ -1,175 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module simple_gemac_wrapper - #(parameter RXFIFOSIZE=9, - parameter TXFIFOSIZE=9, - parameter RX_FLOW_CTRL=0) - (input clk125, input reset, - // GMII - output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD, - input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD, - - // Client FIFO Interfaces - input sys_clk, - output [35:0] rx_f36_data, output rx_f36_src_rdy, input rx_f36_dst_rdy, - input [35:0] tx_f36_data, input tx_f36_src_rdy, output tx_f36_dst_rdy, - - // Wishbone Interface - input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we, - input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o, - - // MIIM - inout mdio, output mdc, - output [31:0] debug); - - wire clear = 0; - wire [7:0] rx_data, tx_data; - wire tx_clk, tx_valid, tx_error, tx_ack; - wire rx_clk, rx_valid, rx_error, rx_ack; - - wire [47:0] ucast_addr, mcast_addr; - wire pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all; - wire pause_req; - wire pause_request_en, pause_respect_en; - wire [15:0] pause_time, pause_thresh, pause_time_req, rx_fifo_space; - - wire [31:0] debug_state; - - wire tx_reset, rx_reset; - reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset)); - reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset)); - - simple_gemac simple_gemac - (.clk125(clk125), .reset(reset), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .pause_req(RX_FLOW_CTRL ? pause_req : 1'b0), .pause_time_req(RX_FLOW_CTRL ? pause_time_req : 16'd0), - .pause_respect_en(pause_respect_en), - .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), - .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), - .pass_pause(pass_pause), .pass_all(pass_all), - .rx_clk(rx_clk), .rx_data(rx_data), - .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), - .tx_clk(tx_clk), .tx_data(tx_data), - .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack), - .debug(debug_state) - ); - - simple_gemac_wb simple_gemac_wb - (.wb_clk(wb_clk), .wb_rst(wb_rst), - .wb_cyc(wb_cyc), .wb_stb(wb_stb), .wb_ack(wb_ack), .wb_we(wb_we), - .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o), - .mdio(mdio), .mdc(mdc), - .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), - .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), - .pass_pause(pass_pause), .pass_all(pass_all), - .pause_respect_en(pause_respect_en), .pause_request_en(pause_request_en), - .pause_time(pause_time), .pause_thresh(pause_thresh) ); - - // RX FIFO Chain - wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; - wire [7:0] rx_ll_data; - - wire [18:0] rx_f19_data_int1, rx_f19_data_int2; - wire rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1, rx_f19_src_rdy_int2, rx_f19_dst_rdy_int2; - wire [35:0] rx_f36_data_int; - wire rx_f36_src_rdy_int, rx_f36_dst_rdy_int; - - rxmac_to_ll8 rx_adapt - (.clk(rx_clk), .reset(rx_reset), .clear(0), - .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), - .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(), // error also encoded in sof/eof - .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy)); - - ll8_to_fifo19 ll8_to_fifo19 - (.clk(rx_clk), .reset(rx_reset), .clear(0), - .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), - .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy), - .f19_data(rx_f19_data_int1), .f19_src_rdy_o(rx_f19_src_rdy_int1), .f19_dst_rdy_i(rx_f19_dst_rdy_int1)); - - fifo19_rxrealign fifo19_rxrealign - (.clk(rx_clk), .reset(rx_reset), .clear(0), - .datain(rx_f19_data_int1), .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1), - .dataout(rx_f19_data_int2), .src_rdy_o(rx_f19_src_rdy_int2), .dst_rdy_i(rx_f19_dst_rdy_int2) ); - - fifo19_to_fifo36 rx_fifo19_to_fifo36 - (.clk(rx_clk), .reset(rx_reset), .clear(0), - .f19_datain(rx_f19_data_int2), .f19_src_rdy_i(rx_f19_src_rdy_int2), .f19_dst_rdy_o(rx_f19_dst_rdy_int2), - .f36_dataout(rx_f36_data_int), .f36_src_rdy_o(rx_f36_src_rdy_int), .f36_dst_rdy_i(rx_f36_dst_rdy_int) ); - - fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo - (.wclk(rx_clk), .datain(rx_f36_data_int), - .src_rdy_i(rx_f36_src_rdy_int), .dst_rdy_o(rx_f36_dst_rdy_int), .space(rx_fifo_space), - .rclk(sys_clk), .dataout(rx_f36_data), - .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .occupied(), .arst(reset)); - - // TX FIFO Chain - wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; - wire [7:0] tx_ll_data; - wire [35:0] tx_f36_data_int1, tx_f36_data_int2; - wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_src_rdy_int2, tx_f36_dst_rdy_int2; - - fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo - (.wclk(sys_clk), .datain(tx_f36_data), .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(), - .rclk(tx_clk), .dataout(tx_f36_data_int1), .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), - .arst(reset)); - - ethtx_realign ethtx_realign - (.clk(tx_clk), .reset(tx_reset), .clear(clear), - .datain(tx_f36_data_int1), .src_rdy_i(tx_f36_src_rdy_int1), .dst_rdy_o(tx_f36_dst_rdy_int1), - .dataout(tx_f36_data_int2), .src_rdy_o(tx_f36_src_rdy_int2), .dst_rdy_i(tx_f36_dst_rdy_int2) ); - - fifo36_to_ll8 fifo36_to_ll8 - (.clk(tx_clk), .reset(tx_reset), .clear(clear), - .f36_data(tx_f36_data_int2), .f36_src_rdy_i(tx_f36_src_rdy_int2), .f36_dst_rdy_o(tx_f36_dst_rdy_int2), - .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof), - .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy)); - - ll8_to_txmac ll8_to_txmac - (.clk(tx_clk), .reset(tx_reset), .clear(clear), - .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof), - .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy), - .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)); - - // Flow Control - generate - if(RX_FLOW_CTRL==1) - flow_ctrl_rx flow_ctrl_rx - (.pause_request_en(pause_request_en), .pause_time(pause_time), .pause_thresh(pause_thresh), - .rx_clk(rx_clk), .rx_reset(rx_reset), .rx_fifo_space(rx_fifo_space), - .tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), .pause_time_req(pause_time_req)); - endgenerate - - wire [31:0] debug_tx, debug_rx; - - assign debug_tx = { { tx_ll_data }, - { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, 4'b0 }, - { tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]}, - { tx_data} }; - assign debug_rx = { { rx_ll_data }, - { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 4'b0 }, - { rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int, rx_f36_dst_rdy_int, rx_f36_data_int[34:32]}, - { rx_data} }; - - assign debug = debug_rx; - -endmodule // simple_gemac_wrapper - diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v deleted file mode 100644 index 2904e38d4..000000000 --- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v +++ /dev/null @@ -1,260 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module simple_gemac_wrapper_f36_tb; -`include "eth_tasks_f36.v" - - reg clk = 0; - reg reset = 1; - - initial #1000 reset = 0; - always #50 clk = ~clk; - - reg wb_clk = 0; - wire wb_rst = reset; - always #173 wb_clk = ~wb_clk; - - wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK; - wire [7:0] GMII_RXD, GMII_TXD; - - wire rx_valid, rx_error, rx_ack; - wire tx_ack, tx_valid, tx_error; - - wire [7:0] rx_data, tx_data; - - reg [15:0] pause_time; - reg pause_req = 0; - - wire GMII_RX_CLK = GMII_GTX_CLK; - - reg [7:0] FORCE_DAT_ERR = 0; - reg FORCE_ERR = 0; - - // Loopback - assign GMII_RX_DV = GMII_TX_EN; - assign GMII_RX_ER = GMII_TX_ER | FORCE_ERR; - assign GMII_RXD = GMII_TXD ^ FORCE_DAT_ERR; - - - wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; - wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2; - wire rx_ll_dst_rdy2; - wire [7:0] rx_ll_data, rx_ll_data2; - wire rx_ll_error, rx_ll_error2; - - wire [31:0] wb_dat_o; - reg [31:0] wb_dat_i; - reg [7:0] wb_adr; - reg wb_stb=0, wb_cyc=0, wb_we=0; - wire wb_ack; - - reg [35:0] tx_f36_dat; - reg tx_f36_src_rdy; - wire tx_f36_dst_rdy; - - wire [35:0] rx_f36_dat; - wire rx_f36_src_rdy; - reg rx_f36_dst_rdy = 1; - - simple_gemac_wrapper simple_gemac_wrapper - (.clk125(clk), .reset(reset), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .pause_req(pause_req), .pause_time(pause_time), - .rx_clk(rx_clk), .rx_ll_data(rx_ll_data), .rx_ll_sof(rx_ll_sof), - .rx_ll_eof(rx_ll_eof), .rx_ll_src_rdy(rx_ll_src_rdy), .rx_ll_dst_rdy(rx_ll_dst_rdy), - .tx_clk(tx_clk), .tx_ll_data(tx_ll_data), .tx_ll_sof(tx_ll_sof), - .tx_ll_eof(tx_ll_eof), .tx_ll_src_rdy(tx_ll_src_rdy), .tx_ll_dst_rdy(tx_ll_dst_rdy), - .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), - .wb_we(wb_we), .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o), - .mdio(mdio), .mdc(mdc) ); - - wire rx_ll_dst_rdy2_n; - assign rx_ll_dst_rdy2 = ~rx_ll_dst_rdy2_n; - - ll8_shortfifo rx_sfifo - (.clk(clk), .reset(reset), .clear(0), - .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof), - .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy), - .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2), - .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2)); - - ll8_to_fifo36 ll8_to_fifo36 - (.clk(clk), .reset(reset), .clear(0), - .ll_data(rx_ll_data2), .ll_sof_n(~rx_ll_sof2), .ll_eof_n(~rx_ll_eof2), - .ll_src_rdy_n(~rx_ll_src_rdy2), .ll_dst_rdy_n(rx_ll_dst_rdy2_n), - .f36_data(rx_f36_dat), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy)); - - wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; - wire tx_ll_sof2_n, tx_ll_eof2_n; - wire tx_ll_src_rdy2_n, tx_ll_dst_rdy2; - wire [7:0] tx_ll_data, tx_ll_data2; - wire tx_ll_error; - wire tx_ll_error2 = 0; - - fifo36_to_ll8 fifo36_to_ll8 - (.clk(clk), .reset(reset), .clear(clear), - .f36_data(tx_f36_dat), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy), - .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n), - .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(~tx_ll_dst_rdy2)); - - ll8_shortfifo tx_sfifo - (.clk(clk), .reset(reset), .clear(clear), - .datain(tx_ll_data2), .sof_i(~tx_ll_sof2_n), .eof_i(~tx_ll_eof2_n), - .error_i(tx_ll_error2), .src_rdy_i(~tx_ll_src_rdy2_n), .dst_rdy_o(tx_ll_dst_rdy2), - .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof), - .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy)); - - initial $dumpfile("simple_gemac_wrapper_f36_tb.vcd"); - initial $dumpvars(0,simple_gemac_wrapper_f36_tb); - - integer i; - reg [7:0] pkt_rom[0:65535]; - reg [1023:0] ROMFile; - - initial - for (i=0;i<65536;i=i+1) - pkt_rom[i] <= 8'h0; - - initial - begin - @(negedge reset); - repeat (10) - @(posedge clk); - WishboneWR(0,6'b111001); - WishboneWR(4,16'hF1F2); - WishboneWR(8,32'hF3F4_F5F6); - WishboneWR(12,16'h0000); - WishboneWR(16,32'h0000_0000); - - @(posedge clk); - SendFlowCtrl(16'h0007); // Send flow control - @(posedge clk); - #30000; - @(posedge clk); - SendFlowCtrl(16'h0009); // Increase flow control before it expires - #10000; - @(posedge clk); - SendFlowCtrl(16'h0000); // Cancel flow control before it expires - @(posedge clk); - - SendPacket_to_fifo36(8'hAA,10); // This packet gets dropped by the filters - repeat (10) - @(posedge clk); - - SendPacketFromFile_fifo36(60,0,0); // The rest are valid packets - repeat (10) - @(posedge clk); - - SendPacketFromFile_fifo36(61,0,0); - repeat (10) - @(posedge clk); - SendPacketFromFile_fifo36(62,0,0); - repeat (10) - @(posedge clk); - SendPacketFromFile_fifo36(63,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_fifo36(64,0,0); - repeat (10) - @(posedge clk); - SendPacketFromFile_fifo36(59,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_fifo36(58,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_fifo36(100,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_fifo36(200,150,30); // waiting 14 empties the fifo, 15 underruns - repeat (1) - @(posedge clk); - SendPacketFromFile_fifo36(100,0,30); - #10000 $finish; - end -/* - // Force a CRC error - initial - begin - #90000; - @(posedge clk); - FORCE_DAT_ERR <= 8'h10; - @(posedge clk); - FORCE_DAT_ERR <= 8'h00; - end - - // Force an RX_ER error (i.e. link loss) - initial - begin - #116000; - @(posedge clk); - FORCE_ERR <= 1; - @(posedge clk); - FORCE_ERR <= 0; - end - - // Cause receive fifo to fill, causing an RX overrun - initial - begin - #126000; - @(posedge clk); - rx_f36_dst_rdy <= 0; - repeat (30) // Repeat of 14 fills the shortfifo, but works. 15 overflows - @(posedge clk); - rx_f36_dst_rdy <= 1; - end - */ - // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun - // Still need to test: CRC errors on Pause Frames, MDIO, wishbone - - task WishboneWR; - input [7:0] adr; - input [31:0] value; - begin - wb_adr <= adr; - wb_dat_i <= value; - wb_stb <= 1; - wb_cyc <= 1; - wb_we <= 1; - while (~wb_ack) - @(posedge wb_clk); - @(posedge wb_clk); - wb_stb <= 0; - wb_cyc <= 0; - wb_we <= 0; - end - endtask // WishboneWR - - always @(posedge clk) - if(rx_f36_src_rdy & rx_f36_dst_rdy) - begin - if(rx_f36_dat[32] & ~rx_f36_dat[33]) - $display("RX-PKT-START %d",$time); - $display("RX-PKT SOF %d EOF %d ERR %d OCC %d DAT %x",rx_f36_dat[32],rx_f36_dat[33], - &rx_f36_dat[33:32],rx_f36_dat[35:34],rx_f36_dat[31:0]); - if(rx_f36_dat[33] & ~rx_f36_dat[32]) - $display("RX-PKT-END %d",$time); - if(rx_f36_dat[33] & rx_f36_dat[32]) - $display("RX-PKT-ERROR %d",$time); - end - -endmodule // simple_gemac_wrapper_tb diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v deleted file mode 100644 index 5a3f3f832..000000000 --- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v +++ /dev/null @@ -1,222 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module simple_gemac_wrapper_tb; -`include "eth_tasks_f36.v" - - reg reset = 1; - initial #1000 reset = 0; - wire wb_rst = reset; - - reg eth_clk = 0; - always #50 eth_clk = ~eth_clk; - - reg wb_clk = 0; - always #173 wb_clk = ~wb_clk; - - reg sys_clk = 0; - always #77 sys_clk = ~ sys_clk; - - wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK; - wire [7:0] GMII_RXD, GMII_TXD; - - wire rx_valid, rx_error, rx_ack; - wire tx_ack, tx_valid, tx_error; - - wire [7:0] rx_data, tx_data; - - wire GMII_RX_CLK = GMII_GTX_CLK; - - reg [7:0] FORCE_DAT_ERR = 0; - reg FORCE_ERR = 0; - - // Loopback - assign GMII_RX_DV = GMII_TX_EN; - assign GMII_RX_ER = GMII_TX_ER | FORCE_ERR; - assign GMII_RXD = GMII_TXD ^ FORCE_DAT_ERR; - - - wire [31:0] wb_dat_o; - reg [31:0] wb_dat_i; - reg [7:0] wb_adr; - reg wb_stb=0, wb_cyc=0, wb_we=0; - wire wb_ack; - - reg [35:0] tx_f36_data=0; - reg tx_f36_src_rdy = 0; - wire tx_f36_dst_rdy; - wire [35:0] rx_f36_data; - wire rx_f36_src_rdy; - wire rx_f36_dst_rdy = 1; - - simple_gemac_wrapper simple_gemac_wrapper - (.clk125(eth_clk), .reset(reset), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - - .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy), - .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy), - - .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we), - .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o), - - .mdio(), .mdc(), - .debug() ); - - initial $dumpfile("simple_gemac_wrapper_tb.vcd"); - initial $dumpvars(0,simple_gemac_wrapper_tb); - - integer i; - reg [7:0] pkt_rom[0:65535]; - reg [1023:0] ROMFile; - - initial - for (i=0;i<65536;i=i+1) - pkt_rom[i] <= 8'h0; - - initial - begin - @(negedge reset); - repeat (10) - @(posedge wb_clk); - WishboneWR(0,6'b111101); - WishboneWR(4,16'hA0B0); - WishboneWR(8,32'hC0D0_A1B1); - WishboneWR(12,16'h0000); - WishboneWR(16,32'h0000_0000); - - @(posedge eth_clk); - SendFlowCtrl(16'h0007); // Send flow control - @(posedge eth_clk); - #30000; - @(posedge eth_clk); - SendFlowCtrl(16'h0009); // Increase flow control before it expires - #10000; - @(posedge eth_clk); - SendFlowCtrl(16'h0000); // Cancel flow control before it expires - @(posedge eth_clk); - - repeat (1000) - @(posedge sys_clk); - SendPacket_to_fifo36(32'hA0B0C0D0,10); // This packet gets dropped by the filters - repeat (1000) - @(posedge sys_clk); - - SendPacket_to_fifo36(32'hAABBCCDD,100); // This packet gets dropped by the filters - repeat (10) - @(posedge sys_clk); -/* - SendPacketFromFile_f36(60,0,0); // The rest are valid packets - repeat (10) - @(posedge clk); - - SendPacketFromFile_f36(61,0,0); - repeat (10) - @(posedge clk); - SendPacketFromFile_f36(62,0,0); - repeat (10) - @(posedge clk); - SendPacketFromFile_f36(63,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_f36(64,0,0); - repeat (10) - @(posedge clk); - SendPacketFromFile_f36(59,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_f36(58,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_f36(100,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_f36(200,150,30); // waiting 14 empties the fifo, 15 underruns - repeat (1) - @(posedge clk); - SendPacketFromFile_f36(100,0,30); - */ - #100000 $finish; - end - - // Force a CRC error - initial - begin - #90000; - @(posedge eth_clk); - FORCE_DAT_ERR <= 8'h10; - @(posedge eth_clk); - FORCE_DAT_ERR <= 8'h00; - end - - // Force an RX_ER error (i.e. link loss) - initial - begin - #116000; - @(posedge eth_clk); - FORCE_ERR <= 1; - @(posedge eth_clk); - FORCE_ERR <= 0; - end -/* - // Cause receive fifo to fill, causing an RX overrun - initial - begin - #126000; - @(posedge clk); - rx_ll_dst_rdy2 <= 0; - repeat (30) // Repeat of 14 fills the shortfifo, but works. 15 overflows - @(posedge clk); - rx_ll_dst_rdy2 <= 1; - end - */ - // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun - // Still need to test: CRC errors on Pause Frames, MDIO, wishbone - - task WishboneWR; - input [7:0] adr; - input [31:0] value; - begin - wb_adr <= adr; - wb_dat_i <= value; - wb_stb <= 1; - wb_cyc <= 1; - wb_we <= 1; - while (~wb_ack) - @(posedge wb_clk); - @(posedge wb_clk); - wb_stb <= 0; - wb_cyc <= 0; - wb_we <= 0; - end - endtask // WishboneWR - /* - always @(posedge clk) - if(rx_ll_src_rdy2 & rx_ll_dst_rdy2) - begin - if(rx_ll_sof2 & ~rx_ll_eof2) - $display("RX-PKT-START %d",$time); - $display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2); - if(rx_ll_eof2 & ~rx_ll_sof2) - $display("RX-PKT-END %d",$time); - end - */ -endmodule // simple_gemac_wrapper_tb diff --git a/fpga/usrp2/simple_gemac/test_packet.mem b/fpga/usrp2/simple_gemac/test_packet.mem deleted file mode 100644 index 7f41d3e42..000000000 --- a/fpga/usrp2/simple_gemac/test_packet.mem +++ /dev/null @@ -1,66 +0,0 @@ -ff -ff -ff -ff -ff -ff -08 -00 -07 -5c -2e -e4 -08 -06 -00 -01 -08 -04 -06 -02 -00 -01 -08 -00 -07 -5c -2e -e4 -03 -64 -00 -00 -00 -00 -00 -00 -02 -64 -00 -3a -f3 -5c -4f -12 -01 -10 -00 -01 -00 -00 -00 -00 -00 -00 -20 -41 -42 -41 -08 -00 -AA -BB -CC -DD -EE -FF diff --git a/fpga/usrp2/testbench/.gitignore b/fpga/usrp2/testbench/.gitignore deleted file mode 100644 index eedcf9652..000000000 --- a/fpga/usrp2/testbench/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -/single_u2_sim -/dual_u2_sim -/*.lxt -/*.vcd -/*.sav diff --git a/fpga/usrp2/testbench/Makefile b/fpga/usrp2/testbench/Makefile deleted file mode 100644 index 6032a0123..000000000 --- a/fpga/usrp2/testbench/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -all: single dual - -single: - iverilog -Wimplicit -Wportbind -c cmdfile ../top/single_u2_sim/single_u2_sim.v -o single_u2_sim - -dual: - iverilog -Wimplicit -Wportbind -c cmdfile ../top/dual_u2_sim/dual_u2_sim.v -o dual_u2_sim - -clean: - rm -f single_u2_sim dual_u2_sim *.vcd *.lxt diff --git a/fpga/usrp2/testbench/README b/fpga/usrp2/testbench/README deleted file mode 100644 index 14bbb68bb..000000000 --- a/fpga/usrp2/testbench/README +++ /dev/null @@ -1,5 +0,0 @@ -The path to happiness: - -make clean -make -./u2_sim +rom=../../firmware/eth_test.rom -lxt2 diff --git a/fpga/usrp2/testbench/cmdfile b/fpga/usrp2/testbench/cmdfile deleted file mode 100644 index 8083eb92a..000000000 --- a/fpga/usrp2/testbench/cmdfile +++ /dev/null @@ -1,27 +0,0 @@ - -# My stuff --y . --y ../top/u2_core --y ../control_lib --y ../control_lib/newfifo --y ../serdes --y ../sdr_lib --y ../timing --y ../coregen --y ../extram --y ../simple_gemac --y ../simple_gemac/miim - -# Models --y ../models --y ../models/CY7C1356C - -# Open Cores --y ../opencores/8b10b --y ../opencores/spi/rtl/verilog -+incdir+../opencores/spi/rtl/verilog --y ../opencores/i2c/rtl/verilog -+incdir+../opencores/i2c/rtl/verilog --y ../opencores/aemb/rtl/verilog --y ../opencores/simple_pic/rtl - diff --git a/fpga/usrp2/testbench/single_u2_sim.v b/fpga/usrp2/testbench/single_u2_sim.v deleted file mode 100644 index f25374613..000000000 --- a/fpga/usrp2/testbench/single_u2_sim.v +++ /dev/null @@ -1,341 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module single_u2_sim(); - // Misc, debug - wire [7:0] leds; - wire [31:0] debug; - wire [1:0] debug_clk; - - // Expansion - wire exp_pps_in; - wire exp_pps_out; - - // GMII - // GMII-CTRL - wire GMII_COL; - wire GMII_CRS; - - // GMII-TX - wire [7:0] GMII_TXD; - wire GMII_TX_EN; - wire GMII_TX_ER; - wire GMII_GTX_CLK; - wire GMII_TX_CLK; // 100mbps clk - - // GMII-RX - wire [7:0] GMII_RXD; - wire GMII_RX_CLK; - wire GMII_RX_DV; - wire GMII_RX_ER; - - // GMII-Management - wire MDIO; - wire MDC; - wire PHY_INTn; // open drain - wire PHY_RESETn; - wire PHY_CLK; // possibly use on-board osc - - // RAM - wire [17:0] RAM_D; - wire [18:0] RAM_A; - wire RAM_CE1n; - wire RAM_CENn; - wire RAM_CLK; - wire RAM_WEn; - wire RAM_OEn; - wire RAM_LDn; - - // SERDES - wire ser_enable; - wire ser_prbsen; - wire ser_loopen; - wire ser_rx_en; - - wire ser_tx_clk; - wire [15:0] ser_t; - wire ser_tklsb; - wire ser_tkmsb; - - wire ser_rx_clk; - wire [15:0] ser_r; - wire ser_rklsb; - wire ser_rkmsb; - - // CPLD interface - wire cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done; - - // ADC - wire [13:0] adc_a; - wire adc_ovf_a; - wire adc_on_a, adc_oe_a; - - wire [13:0] adc_b; - wire adc_ovf_b; - wire adc_on_b, adc_oe_b; - - // DAC - wire [15:0] dac_a; - wire [15:0] dac_b; - - // I2C - wire SCL; - wire SDA; - - // Clock Gen Control - wire [1:0] clk_en; - wire [1:0] clk_sel; - wire clk_func; // FIXME is an input to control the 9510 - wire clk_status; - - // Clocks - reg clk_fpga; - reg clk_to_mac; - wire pps_in; - - // Generic SPI - wire sclk, mosi, miso; - wire sen_clk; - wire sen_dac; - wire sen_tx_db; - wire sen_tx_adc; - wire sen_tx_dac; - wire sen_rx_db; - wire sen_rx_adc; - wire sen_rx_dac; - - // GPIO to DBoards - wire [15:0] io_tx; - wire [15:0] io_rx; - - wire wb_clk; - wire start, clock_ready; - - reg aux_clk; - - initial aux_clk= 1'b0; - always #6 aux_clk = ~aux_clk; - - initial clk_fpga = 1'bx; - initial #3007 clk_fpga = 1'b0; - always #5 clk_fpga = ~clk_fpga; - - initial clk_to_mac = 0; - always #4 clk_to_mac = ~clk_to_mac; - - wire div_clk, dsp_clk; - reg [7:0] div_ctr = 0; - - assign dsp_clk = clock_ready ? clk_fpga : aux_clk; - assign wb_clk = div_clk; - -`define CLK_DIV_2 1 -//`define CLK_DIV_3 - -`ifdef CLK_DIV_2 - localparam clock_divider = 4'd2; - always @(posedge dsp_clk) - div_ctr <= div_ctr + 1; - assign div_clk = div_ctr[0]; -`endif - -`ifdef CLK_DIV_3 - localparam clock_divider = 2; - always @(posedge dsp_clk or negedge dsp_clk) - if(div_ctr == 5) - div_ctr <= 0; - else - div_ctr <= div_ctr + 1; - assign div_clk = ((div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2)); -`endif - - initial - $monitor($time, ,clock_ready); - - always #1000000 $monitor("Time in ns ",$time); - - initial begin - @(negedge cpld_done); - @(posedge cpld_done); - $dumpfile("single_u2_sim.lxt"); - $dumpvars(0,single_u2_sim); - end - - initial #10000000 $finish; - - cpld_model - cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done), - .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached)); - - serdes_model serdes_model - (.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), .ser_t(ser_t), - .ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), .ser_r(ser_r), - .even(0),.error(0) ); - - adc_model adc_model - (.clk(dsp_clk),.rst(0), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_on_a(adc_on_a),.adc_oe_a(adc_oe_a), - .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),.adc_on_b(adc_on_b),.adc_oe_b(adc_oe_b) ); - - wire [2:0] speed; - phy_sim phy_model - (.Gtx_clk(GMII_GTX_CLK), . Rx_clk(GMII_RX_CLK), .Tx_clk(GMII_TX_CLK), - .Tx_er(GMII_TX_ER), .Tx_en(GMII_TX_EN), .Txd(GMII_TXD), - .Rx_er(GMII_RX_ER), .Rx_dv(GMII_RX_DV), .Rxd(GMII_RXD), - .Crs(GMII_CRS), .Col(GMII_COL), - .Speed(speed), .Done(0) ); - pullup p3(MDIO); - - miim_model miim_model - (.mdc_i(MDC),.mdio(MDIO),.phy_resetn_i(PHY_RESETn),.phy_clk_i(PHY_CLK), - .phy_intn_o(PHY_INTn),.speed_o(speed) ); - - xlnx_glbl glbl (.GSR(),.GTS()); - - wire RAM_MODE = 1'b0; - cy1356 ram_model(.d(RAM_D),.clk(RAM_CLK),.a(RAM_A), - .bws(2'b00),.we_b(RAM_WEn),.adv_lb(RAM_LDn), - .ce1b(RAM_CE1n),.ce2(1'b1),.ce3b(1'b0), - .oeb(RAM_OEn),.cenb(RAM_CENn),.mode(RAM_MODE) ); - - M24LC024B eeprom_model(.A0(0),.A1(0),.A2(0),.WP(0), - .SDA(SDA),.SCL(SCL),.RESET(0)); - - wire scl_pad_i, scl_pad_o, scl_pad_oen_o; - wire sda_pad_i, sda_pad_o, sda_pad_oen_o; - - pullup p1(SCL); - pullup p2(SDA); - - assign scl_pad_i = SCL; - assign sda_pad_i = SDA; - - assign SCL = scl_pad_oen_o ? 1'bz : scl_pad_o; - assign SDA = sda_pad_oen_o ? 1'bz : sda_pad_o; - - // printf output - wire uart_baud_o, uart_tx_o, uart_rx_i; - assign uart_rx_i = 1'b1; - - uart_rx uart_rx(.baudclk(uart_baud_o),.rxd(uart_tx_o)); - - // End the simulation - always @(posedge wb_clk) - if((u2_core.m0_we == 1'd1)&&(u2_core.m0_adr == 16'hC2F0)) - begin - $display($time, "Finish called.",); - $finish; - end - - u2_core #(.RAM_SIZE(32768)) - u2_core(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .leds (leds), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_pps_in), - .exp_pps_out (exp_pps_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD[7:0]), - .GMII_TX_EN (GMII_TX_EN), - .GMII_TX_ER (GMII_TX_ER), - .GMII_GTX_CLK (GMII_GTX_CLK), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk), - .ser_t (ser_t[15:0]), - .ser_tklsb (ser_tklsb), - .ser_tkmsb (ser_tkmsb), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r[15:0]), - .ser_rklsb (ser_rklsb), - .ser_rkmsb (ser_rkmsb), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .cpld_init_b (1), - .por (0), - .adc_a (adc_a[13:0]), - .adc_ovf_a (adc_ovf_a), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b[13:0]), - .adc_ovf_b (adc_ovf_b), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (dac_a[15:0]), - .dac_b (dac_b[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - .uart_rx_i (uart_rx_i), - .uart_baud_o (uart_baud_o), - .sim_mode (1'b1), - .clock_divider (clock_divider) - ); - -endmodule // single_u2_sim diff --git a/fpga/usrp2/timing/.gitignore b/fpga/usrp2/timing/.gitignore deleted file mode 100644 index 515552fdb..000000000 --- a/fpga/usrp2/timing/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/a.out -/*.vcd diff --git a/fpga/usrp2/timing/Makefile.srcs b/fpga/usrp2/timing/Makefile.srcs deleted file mode 100644 index 0cf9372d3..000000000 --- a/fpga/usrp2/timing/Makefile.srcs +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright 2010 Ettus Research LLC -# - -################################################## -# Timing Sources -################################################## -TIMING_SRCS = $(abspath $(addprefix $(BASE_DIR)/../timing/, \ -time_64bit.v \ -time_compare.v \ -time_receiver.v \ -time_sender.v \ -time_sync.v \ -timer.v \ -simple_timer.v \ -)) diff --git a/fpga/usrp2/timing/simple_timer.v b/fpga/usrp2/timing/simple_timer.v deleted file mode 100644 index 56ba8ffe8..000000000 --- a/fpga/usrp2/timing/simple_timer.v +++ /dev/null @@ -1,77 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module simple_timer - #(parameter BASE=0) - (input clk, input reset, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - output reg onetime_int, output reg periodic_int); - - reg [31:0] onetime_ctr; - always @(posedge clk) - if(reset) - begin - onetime_int <= 0; - onetime_ctr <= 0; - end - else - if(set_stb & (set_addr == BASE)) - begin - onetime_int <= 0; - onetime_ctr <= set_data; - end - else - begin - if(onetime_ctr == 1) - onetime_int <= 1; - if(onetime_ctr != 0) - onetime_ctr <= onetime_ctr - 1; - else - onetime_int <= 0; - end // else: !if(set_stb & (set_addr == BASE)) - - reg [31:0] periodic_ctr, period; - always @(posedge clk) - if(reset) - begin - periodic_int <= 0; - periodic_ctr <= 0; - period <= 0; - end - else - if(set_stb & (set_addr == (BASE+1))) - begin - periodic_int <= 0; - periodic_ctr <= set_data; - period <= set_data; - end - else - if(periodic_ctr == 1) - begin - periodic_int <= 1; - periodic_ctr <= period; - end - else - if(periodic_ctr != 0) - begin - periodic_int <= 0; - periodic_ctr <= periodic_ctr - 1; - end - -endmodule // simple_timer diff --git a/fpga/usrp2/timing/time_64bit.v b/fpga/usrp2/timing/time_64bit.v deleted file mode 100644 index 6f335890e..000000000 --- a/fpga/usrp2/timing/time_64bit.v +++ /dev/null @@ -1,162 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module time_64bit - #( - parameter BASE = 0) - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - input pps, - output reg [63:0] vita_time, - output reg [63:0] vita_time_pps, - output pps_int, - input exp_time_in, output exp_time_out, - output reg good_sync, - output [31:0] debug - ); - - localparam NEXT_TICKS_HI = 0; - localparam NEXT_TICKS_LO = 1; - localparam PPS_POLSRC = 2; - localparam PPS_IMM = 3; - localparam MIMO_SYNC = 5; - - reg [63:0] ticks; - - always @(posedge clk) - vita_time <= ticks; - - wire [63:0] vita_time_rcvd; - - wire [63:0] next_ticks_preset; - wire set_on_pps_trig; - reg set_on_next_pps; - wire pps_polarity, pps_source, set_imm; - reg [1:0] pps_del; - reg pps_reg_p, pps_reg_n, pps_reg; - wire pps_edge; - - reg [15:0] sync_counter; - wire sync_rcvd; - wire [63:0] mimo_ticks; - wire mimo_sync_now; - wire mimo_sync; - wire [7:0] sync_delay; - - setting_reg #(.my_addr(BASE+NEXT_TICKS_LO)) sr_next_ticks_lo - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(next_ticks_preset[31:0]),.changed()); - - setting_reg #(.my_addr(BASE+NEXT_TICKS_HI)) sr_next_ticks_hi - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(next_ticks_preset[63:32]),.changed(set_on_pps_trig)); - - setting_reg #(.my_addr(BASE+PPS_POLSRC), .width(2)) sr_pps_polsrc - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({pps_source,pps_polarity}),.changed()); - - setting_reg #(.my_addr(BASE+PPS_IMM), .width(1)) sr_pps_imm - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(set_imm),.changed()); - - setting_reg #(.my_addr(BASE+MIMO_SYNC), .at_reset(0), .width(9)) sr_mimosync - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({mimo_sync,sync_delay}),.changed()); - - always @(posedge clk) pps_reg_p <= pps; - always @(negedge clk) pps_reg_n <= pps; - always @* pps_reg <= pps_polarity ? pps_reg_p : pps_reg_n; - - always @(posedge clk) - if(rst) - pps_del <= 2'b00; - else - pps_del <= {pps_del[0],pps_reg}; - - assign pps_edge = pps_del[0] & ~pps_del[1]; - - always @(posedge clk) - if(pps_edge) - vita_time_pps <= vita_time; - - always @(posedge clk) - if(rst) - set_on_next_pps <= 0; - else if(set_on_pps_trig) - set_on_next_pps <= 1; - else if(set_imm | pps_edge) - set_on_next_pps <= 0; - - wire [63:0] ticks_plus_one = ticks + 1; - - always @(posedge clk) - if(rst) - begin - ticks <= 64'd0; - end - else if((set_imm | pps_edge) & set_on_next_pps) - begin - ticks <= next_ticks_preset; - end - else if(mimo_sync_now) - begin - ticks <= mimo_ticks; - end - else - ticks <= ticks_plus_one; - - assign pps_int = pps_edge; - - // MIMO Connector Time Sync - wire send_sync = (sync_counter == 59999); // X % 10 = 9 - - always @(posedge clk) - if(rst) - sync_counter <= 0; - else - if(send_sync) - sync_counter <= 0; - else - sync_counter <= sync_counter + 1; - - time_sender time_sender - (.clk(clk),.rst(rst), - .vita_time(vita_time), - .send_sync(send_sync), - .exp_time_out(exp_time_out) ); - - time_receiver time_receiver - (.clk(clk),.rst(rst), - .vita_time(vita_time_rcvd), - .sync_rcvd(sync_rcvd), - .exp_time_in(exp_time_in) ); - - assign mimo_ticks = vita_time_rcvd[63:0] + {48'd0,sync_delay}; - assign mimo_sync_now = mimo_sync & sync_rcvd; - - assign debug = { { 24'b0} , - { 2'b0, exp_time_in, exp_time_out, mimo_sync, mimo_sync_now, sync_rcvd, send_sync} }; - - always @(posedge clk) - if(rst) - good_sync <= 0; - else if(sync_rcvd) - good_sync <= 1; - -endmodule // time_64bit diff --git a/fpga/usrp2/timing/time_compare.v b/fpga/usrp2/timing/time_compare.v deleted file mode 100644 index 21607f51c..000000000 --- a/fpga/usrp2/timing/time_compare.v +++ /dev/null @@ -1,34 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -// 64 bits worth of ticks - -module time_compare - (input [63:0] time_now, - input [63:0] trigger_time, - output now, - output early, - output late, - output too_early); - - assign now = time_now == trigger_time; - assign late = time_now > trigger_time; - assign early = ~now & ~late; - assign too_early = 0; //not implemented - -endmodule // time_compare diff --git a/fpga/usrp2/timing/time_receiver.v b/fpga/usrp2/timing/time_receiver.v deleted file mode 100644 index a03337552..000000000 --- a/fpga/usrp2/timing/time_receiver.v +++ /dev/null @@ -1,157 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module time_receiver - (input clk, input rst, - output reg [63:0] vita_time, - output reg sync_rcvd, - input exp_time_in); - - wire code_err, disp_err, dispout, complete_word; - reg disp_reg; - reg [9:0] shiftreg; - reg [3:0] bit_count; - wire [8:0] dataout; - reg [8:0] dataout_reg; - - reg exp_time_in_reg, exp_time_in_reg2; - - always @(posedge clk) exp_time_in_reg <= exp_time_in; - always @(posedge clk) exp_time_in_reg2 <= exp_time_in_reg; - - always @(posedge clk) - shiftreg <= {exp_time_in_reg2, shiftreg[9:1]}; - - localparam COMMA_0 = 10'h283; - localparam COMMA_1 = 10'h17c; - - wire found_comma = (shiftreg == COMMA_0) | (shiftreg == COMMA_1); - wire set_disp = (shiftreg == COMMA_1); - - always @(posedge clk) - if(rst) - bit_count <= 0; - else if(found_comma | complete_word) - bit_count <= 0; - else - bit_count <= bit_count + 1; - assign complete_word = (bit_count == 9); - - always @(posedge clk) - if(set_disp) - disp_reg <= 1; - else if(complete_word) - disp_reg <= dispout; - - always @(posedge clk) - if(complete_word) - dataout_reg <= dataout; - - decode_8b10b decode_8b10b - (.datain(shiftreg),.dispin(disp_reg), - .dataout(dataout),.dispout(dispout), - .code_err(code_err),.disp_err(disp_err) ); - - reg error; - always @(posedge clk) - if(complete_word) - error <= code_err | disp_err; - - localparam STATE_IDLE = 0; - localparam STATE_T0 = 1; - localparam STATE_T1 = 2; - localparam STATE_T2 = 3; - localparam STATE_T3 = 4; - localparam STATE_T4 = 5; - localparam STATE_T5 = 6; - localparam STATE_T6 = 7; - localparam STATE_T7 = 8; - localparam STATE_TAIL = 9; - - localparam HEAD = 9'h13c; - localparam TAIL = 9'h1F7; - - reg [3:0] state; - reg [63:0] vita_time_pre; - reg sync_rcvd_pre; - - always @(posedge clk) - if(rst) - state <= STATE_IDLE; - else if(complete_word) - if(code_err | disp_err) - state <= STATE_IDLE; - else - case(state) - STATE_IDLE : - if(dataout_reg == HEAD) - state <= STATE_T0; - STATE_T0 : - begin - vita_time_pre[63:56] <= dataout_reg[7:0]; - state <= STATE_T1; - end - STATE_T1 : - begin - vita_time_pre[55:48] <= dataout_reg[7:0]; - state <= STATE_T2; - end - STATE_T2 : - begin - vita_time_pre[47:40] <= dataout_reg[7:0]; - state <= STATE_T3; - end - STATE_T3 : - begin - vita_time_pre[39:32] <= dataout_reg[7:0]; - state <= STATE_T4; - end - STATE_T4 : - begin - vita_time_pre[31:24] <= dataout_reg[7:0]; - state <= STATE_T5; - end - STATE_T5 : - begin - vita_time_pre[23:16] <= dataout_reg[7:0]; - state <= STATE_T6; - end - STATE_T6 : - begin - vita_time_pre[15:8] <= dataout_reg[7:0]; - state <= STATE_T7; - end - STATE_T7 : - begin - vita_time_pre[7:0] <= dataout_reg[7:0]; - state <= STATE_TAIL; - end - STATE_TAIL : - state <= STATE_IDLE; - endcase // case(state) - - always @(posedge clk) - if(rst) - sync_rcvd_pre <= 0; - else - sync_rcvd_pre <= (complete_word & (state == STATE_TAIL) & (dataout_reg[8:0] == TAIL)); - - always @(posedge clk) sync_rcvd <= sync_rcvd_pre; - always @(posedge clk) vita_time <= vita_time_pre; - -endmodule // time_sender diff --git a/fpga/usrp2/timing/time_sender.v b/fpga/usrp2/timing/time_sender.v deleted file mode 100644 index fdf6b1240..000000000 --- a/fpga/usrp2/timing/time_sender.v +++ /dev/null @@ -1,157 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module time_sender - (input clk, input rst, - input [63:0] vita_time, - input send_sync, - output reg exp_time_out); - - reg [7:0] datain; - reg k; - wire [9:0] dataout; - reg [9:0] dataout_reg; - reg disp_reg; - wire disp, new_word; - reg [4:0] state; - reg [3:0] bit_count; - - encode_8b10b encode_8b10b - (.datain({k,datain}),.dispin(disp_reg), - .dataout(dataout),.dispout(disp)); - - always @(posedge clk) - if(rst) - disp_reg <= 0; - else if(new_word) - disp_reg <= disp; - - always @(posedge clk) - if(rst) - dataout_reg <= 0; - else if(new_word) - dataout_reg <= dataout; - else - dataout_reg <= {1'b0,dataout_reg[9:1]}; - - always @(posedge clk) - exp_time_out <= dataout_reg[0]; - - assign new_word = (bit_count == 9); - - always @(posedge clk) - if(rst) - bit_count <= 0; - else if(new_word | send_sync) - bit_count <= 0; - else - bit_count <= bit_count + 1; - - localparam SEND_IDLE = 0; - localparam SEND_HEAD = 1; - localparam SEND_T0 = 2; - localparam SEND_T1 = 3; - localparam SEND_T2 = 4; - localparam SEND_T3 = 5; - localparam SEND_T4 = 6; - localparam SEND_T5 = 7; - localparam SEND_T6 = 8; - localparam SEND_T7 = 9; - localparam SEND_TAIL = 10; - - localparam COMMA = 8'hBC; - localparam HEAD = 8'h3C; - localparam TAIL = 8'hF7; - - reg [63:0] vita_time_reg; - - always @(posedge clk) - if(rst) - vita_time_reg <= 0; - else if(send_sync) - vita_time_reg <= vita_time; - - always @(posedge clk) - if(rst) - begin - {k,datain} <= 0; - state <= SEND_IDLE; - end - else - if(send_sync) - state <= SEND_HEAD; - else if(new_word) - case(state) - SEND_IDLE : - {k,datain} <= {1'b1,COMMA}; - SEND_HEAD : - begin - {k,datain} <= {1'b1, HEAD}; - state <= SEND_T0; - end - SEND_T0 : - begin - {k,datain} <= {1'b0, vita_time_reg[63:56] }; - state <= SEND_T1; - end - SEND_T1 : - begin - {k,datain} <= {1'b0, vita_time_reg[55:48]}; - state <= SEND_T2; - end - SEND_T2 : - begin - {k,datain} <= {1'b0, vita_time_reg[47:40]}; - state <= SEND_T3; - end - SEND_T3 : - begin - {k,datain} <= {1'b0, vita_time_reg[39:32]}; - state <= SEND_T4; - end - SEND_T4 : - begin - {k,datain} <= {1'b0, vita_time_reg[31:24]}; - state <= SEND_T5; - end - SEND_T5 : - begin - {k,datain} <= {1'b0, vita_time_reg[23:16]}; - state <= SEND_T6; - end - SEND_T6 : - begin - {k,datain} <= {1'b0, vita_time_reg[15:8]}; - state <= SEND_T7; - end - SEND_T7 : - begin - {k,datain} <= {1'b0, vita_time_reg[7:0]}; - state <= SEND_TAIL; - end - SEND_TAIL : - begin - {k,datain} <= {1'b1, TAIL}; - state <= SEND_IDLE; - end - default : - state <= SEND_IDLE; - endcase // case(state) - -endmodule // time_sender diff --git a/fpga/usrp2/timing/time_sync.v b/fpga/usrp2/timing/time_sync.v deleted file mode 100644 index a823e9e1b..000000000 --- a/fpga/usrp2/timing/time_sync.v +++ /dev/null @@ -1,163 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module time_sync - (input wb_clk_i, input rst_i, - input cyc_i, input stb_i, input [2:0] adr_i, - input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o, - input sys_clk_i, output [31:0] master_time_o, - input pps_posedge, input pps_negedge, - input exp_pps_in, output exp_pps_out, - output reg int_o, - output reg epoch_o, - output reg pps_o ); - - wire [31:0] master_time_rcvd; - reg [31:0] master_time; - reg [31:0] delta_time; - - reg internal_tick; - wire sync_rcvd, pps_ext; - reg [31:0] tick_time, tick_time_wb; - wire tick_free_run; - reg tick_int_enable, tick_source, external_sync; - reg [31:0] tick_interval; - reg sync_on_next_pps; - reg sync_every_pps; - reg pps_edge; - - // Generate master time - always @(posedge sys_clk_i) - if(rst_i) - master_time <= 0; - else if(external_sync & sync_rcvd) - master_time <= master_time_rcvd + delta_time; - else if(pps_ext & (sync_on_next_pps|sync_every_pps)) - master_time <= 0; - else - master_time <= master_time + 1; - assign master_time_o = master_time; - - time_sender time_sender - (.clk(sys_clk_i),.rst(rst_i), - .master_time(master_time), - .send_sync(internal_tick), - .exp_pps_out(exp_pps_out) ); - - time_receiver time_receiver - (.clk(sys_clk_i),.rst(rst_i), - .master_time(master_time_rcvd), - .sync_rcvd(sync_rcvd), - .exp_pps_in(exp_pps_in) ); - - assign ack_o = stb_i; - wire wb_write = cyc_i & stb_i & we_i; - wire wb_read = cyc_i & stb_i & ~we_i; - wire wb_acc = cyc_i & stb_i; - - always @(posedge wb_clk_i) - if(rst_i) - begin - tick_source <= 0; - tick_int_enable <= 0; - external_sync <= 0; - tick_interval <= 100000-1; // default to 1K times per second - delta_time <= 0; - pps_edge <= 0; - sync_every_pps <= 0; - end - else if(wb_write) - case(adr_i[2:0]) - 3'd0 : - begin - tick_source <= dat_i[0]; - tick_int_enable <= dat_i[1]; - external_sync <= dat_i[2]; - pps_edge <= dat_i[3]; - sync_every_pps <= dat_i[4]; - end - 3'd1 : - tick_interval <= dat_i; - 3'd2 : - delta_time <= dat_i; - 3'd3 : - ; - // Do nothing here, this is to arm the sync_on_next - endcase // case(adr_i[2:0]) - - always @(posedge sys_clk_i) - if(rst_i) - sync_on_next_pps <= 0; - else if(pps_ext) - sync_on_next_pps <= 0; - else if(wb_write & (adr_i[2:0] == 3)) - sync_on_next_pps <= 1; - - always @(posedge sys_clk_i) - if(internal_tick) - tick_time <= master_time; - - always @(posedge wb_clk_i) - tick_time_wb <= tick_time; - - assign dat_o = tick_time_wb; - - always @(posedge sys_clk_i) - internal_tick <= (tick_source == 0) ? tick_free_run : pps_ext; - - reg [31:0] counter; - always @(posedge sys_clk_i) - if(rst_i) - counter <= 0; - else if(tick_free_run) - counter <= 0; - else - counter <= counter + 1; - assign tick_free_run = (counter >= tick_interval); - - // Properly Latch and edge detect External PPS input - reg pps_in_d1, pps_in_d2; - always @(posedge sys_clk_i) - begin - pps_in_d1 <= pps_edge ? pps_posedge : pps_negedge; - pps_in_d2 <= pps_in_d1; - end - assign pps_ext = pps_in_d1 & ~pps_in_d2; - - always @(posedge sys_clk_i) - pps_o <= pps_ext; - - // Need to register this? - reg internal_tick_d1; - always @(posedge sys_clk_i) internal_tick_d1 <= internal_tick; - - always @(posedge wb_clk_i) - if(rst_i) - int_o <= 0; - else if(tick_int_enable & (internal_tick | internal_tick_d1)) - int_o <= 1; - else - int_o <= 0; - - always @(posedge sys_clk_i) - if(rst_i) - epoch_o <= 0; - else - epoch_o <= (master_time_o[27:0] == 0); -endmodule // time_sync diff --git a/fpga/usrp2/timing/time_transfer_tb.v b/fpga/usrp2/timing/time_transfer_tb.v deleted file mode 100644 index 288540702..000000000 --- a/fpga/usrp2/timing/time_transfer_tb.v +++ /dev/null @@ -1,67 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -`timescale 1ns / 1ps - -module time_transfer_tb(); - - reg clk = 0, rst = 1; - always #5 clk = ~clk; - - initial - begin - @(negedge clk); - @(negedge clk); - rst <= 0; - end - - initial $dumpfile("time_transfer_tb.vcd"); - initial $dumpvars(0,time_transfer_tb); - - initial #100000000 $finish; - - wire exp_time, pps, pps_rcv; - wire [63:0] vita_time_rcv; - reg [63:0] vita_time = 0; - reg [63:0] counter = 0; - - localparam PPS_PERIOD = 439; // PPS_PERIOD % 10 must = 9 - always @(posedge clk) - if(counter == PPS_PERIOD) - counter <= 0; - else - counter <= counter + 1; - assign pps = (counter == (PPS_PERIOD-1)); - - always @(posedge clk) - vita_time <= vita_time + 1; - - time_sender time_sender - (.clk(clk),.rst(rst), - .vita_time(vita_time), - .send_sync(pps), - .exp_time_out(exp_time) ); - - time_receiver time_receiver - (.clk(clk),.rst(rst), - .vita_time(vita_time_rcv), - .sync_rcvd(pps_rcv), - .exp_time_in(exp_time) ); - - wire [31:0] delta = vita_time - vita_time_rcv; -endmodule // time_transfer_tb diff --git a/fpga/usrp2/timing/timer.v b/fpga/usrp2/timing/timer.v deleted file mode 100644 index 216a9294c..000000000 --- a/fpga/usrp2/timing/timer.v +++ /dev/null @@ -1,57 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module timer - (input wb_clk_i, input rst_i, - input cyc_i, input stb_i, input [2:0] adr_i, - input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o, - input sys_clk_i, input [31:0] master_time_i, - output int_o ); - - reg [31:0] time_wb; - always @(posedge wb_clk_i) - time_wb <= master_time_i; - - assign ack_o = stb_i; - - reg [31:0] int_time; - reg int_reg; - - always @(posedge sys_clk_i) - if(rst_i) - begin - int_time <= 0; - int_reg <= 0; - end - else if(|int_time && (master_time_i == int_time)) - begin - int_time <= 0; - int_reg <= 1; - end - else if(stb_i & we_i) - begin - int_time <= dat_i; - int_reg <= 0; - end - - assign dat_o = time_wb; - assign int_o = int_reg; - -endmodule // timer - diff --git a/fpga/usrp2/top/.gitignore b/fpga/usrp2/top/.gitignore deleted file mode 100644 index 0d90f1698..000000000 --- a/fpga/usrp2/top/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/*.sav -build* diff --git a/fpga/usrp2/top/B100/.gitignore b/fpga/usrp2/top/B100/.gitignore deleted file mode 100644 index 1b2211df0..000000000 --- a/fpga/usrp2/top/B100/.gitignore +++ /dev/null @@ -1 +0,0 @@ -build* diff --git a/fpga/usrp2/top/B100/B100.ucf b/fpga/usrp2/top/B100/B100.ucf deleted file mode 100644 index 1c04c5d8d..000000000 --- a/fpga/usrp2/top/B100/B100.ucf +++ /dev/null @@ -1,204 +0,0 @@ -## Main Clock -NET "CLK_FPGA_P" LOC = "R7" ; -NET "CLK_FPGA_N" LOC = "T7" ; - -## I2C -NET "SDA_FPGA" LOC = "T13" ; -NET "SCL_FPGA" LOC = "R13" ; - -## CGEN -NET "cgen_st_ld" LOC = "M13" ; -NET "cgen_st_refmon" LOC = "J14" ; -NET "cgen_st_status" LOC = "P6" ; -NET "cgen_ref_sel" LOC = "T2" ; -NET "cgen_sync_b" LOC = "H15" ; - -## FPGA Config -#NET "fpga_cfg_din" LOC = "T14" ; -#NET "fpga_cfg_cclk" LOC = "R14" ; -#NET "fpga_cfg_init_b" LOC = "T12" ; - -## MISC -#NET "mystery_bus<1>" LOC = "C4" ; -#NET "mystery_bus<0>" LOC = "E7" ; -NET "reset_n" LOC = "D5" ; -NET "PPS_IN" LOC = "M14" ; -NET "reset_codec" LOC = "B14" ; - -## recycles fpga_cfg_cclk for reset from fw -NET "ext_reset" LOC = "R14" ; - -## GPIF -NET "GPIF_D<15>" LOC = "P7" ; -NET "GPIF_D<14>" LOC = "N8" ; -NET "GPIF_D<13>" LOC = "T5" ; -NET "GPIF_D<12>" LOC = "T6" ; -NET "GPIF_D<11>" LOC = "N6" ; -NET "GPIF_D<10>" LOC = "P5" ; -NET "GPIF_D<9>" LOC = "R3" ; -NET "GPIF_D<8>" LOC = "T3" ; -NET "GPIF_D<7>" LOC = "N12" ; -NET "GPIF_D<6>" LOC = "P13" ; -NET "GPIF_D<5>" LOC = "P11" ; -NET "GPIF_D<4>" LOC = "R9" ; -NET "GPIF_D<3>" LOC = "T9" ; -NET "GPIF_D<2>" LOC = "N9" ; -NET "GPIF_D<1>" LOC = "P9" ; -NET "GPIF_D<0>" LOC = "P8" ; - -##NET "GPIF_CTL<3>" LOC = "N5" ; -NET "GPIF_CTL<3>" LOC = "P12" ; -NET "GPIF_CTL<2>" LOC = "M11" ; -NET "GPIF_CTL<1>" LOC = "M9" ; -NET "GPIF_CTL<0>" LOC = "M7" ; - -##NET "GPIF_RDY<3>" LOC = "N11" ; -##NET "GPIF_RDY<2>" LOC = "T10" ; -NET "GPIF_SLWR" LOC = "T4" ; -NET "GPIF_SLRD" LOC = "R5" ; - -##NET "GPIF_CS" LOC = "P12" ; -NET "GPIF_SLOE" LOC = "R11" ; -NET "GPIF_PKTEND" LOC = "P10" ; -NET "GPIF_ADR<0>" LOC = "T11" ; -NET "GPIF_ADR<1>" LOC = "H16" ; - -NET "IFCLK" LOC = "T8" ; - -## LEDs -NET "debug_led<2>" LOC = "R2" ; -NET "debug_led<1>" LOC = "N4" ; -NET "debug_led<0>" LOC = "P4" ; - -## Debug bus -NET "debug_clk<0>" LOC = "K15" ; -NET "debug_clk<1>" LOC = "K14" ; -NET "debug<0>" LOC = "K16" ; -NET "debug<1>" LOC = "J16" ; -NET "debug<2>" LOC = "C16" ; -NET "debug<3>" LOC = "C15" ; -NET "debug<4>" LOC = "E13" ; -NET "debug<5>" LOC = "D14" ; -NET "debug<6>" LOC = "D16" ; -NET "debug<7>" LOC = "D15" ; -NET "debug<8>" LOC = "E14" ; -NET "debug<9>" LOC = "F13" ; -NET "debug<10>" LOC = "G13" ; -NET "debug<11>" LOC = "F14" ; -NET "debug<12>" LOC = "E16" ; -NET "debug<13>" LOC = "F15" ; -NET "debug<14>" LOC = "H13" ; -NET "debug<15>" LOC = "G14" ; -NET "debug<16>" LOC = "G16" ; -NET "debug<17>" LOC = "F16" ; -NET "debug<18>" LOC = "J12" ; -NET "debug<19>" LOC = "J13" ; -NET "debug<20>" LOC = "L14" ; -NET "debug<21>" LOC = "L16" ; -NET "debug<22>" LOC = "M15" ; -NET "debug<23>" LOC = "M16" ; -NET "debug<24>" LOC = "L13" ; -NET "debug<25>" LOC = "K13" ; -NET "debug<26>" LOC = "P16" ; -NET "debug<27>" LOC = "N16" ; -NET "debug<28>" LOC = "R15" ; -NET "debug<29>" LOC = "P15" ; -NET "debug<30>" LOC = "N13" ; -NET "debug<31>" LOC = "N14" ; - -## ADC -NET "adc<11>" LOC = "B15" ; -NET "adc<10>" LOC = "A8" ; -NET "adc<9>" LOC = "B8" ; -NET "adc<8>" LOC = "C8" ; -NET "adc<7>" LOC = "D8" ; -NET "adc<6>" LOC = "C9" ; -NET "adc<5>" LOC = "A9" ; -NET "adc<4>" LOC = "C10" ; -NET "adc<3>" LOC = "D9" ; -NET "adc<2>" LOC = "A3" ; -NET "adc<1>" LOC = "B3" ; -NET "adc<0>" LOC = "A4" ; -NET "RXSYNC" LOC = "D10" ; - -## DAC -NET "TXBLANK" LOC = "K1" ; -NET "TXSYNC" LOC = "J2" ; -NET "dac<0>" LOC = "J1" ; -NET "dac<1>" LOC = "H3" ; -NET "dac<2>" LOC = "J3" ; -NET "dac<3>" LOC = "G2" ; -NET "dac<4>" LOC = "H1" ; -NET "dac<5>" LOC = "N3" ; -NET "dac<6>" LOC = "M4" ; -NET "dac<7>" LOC = "R1" ; -NET "dac<8>" LOC = "P2" ; -NET "dac<9>" LOC = "P1" ; -NET "dac<10>" LOC = "M1" ; -NET "dac<11>" LOC = "N1" ; -NET "dac<12>" LOC = "M3" ; -NET "dac<13>" LOC = "L4" ; - -## TX DB -NET "io_tx<0>" LOC = "K4" ; -NET "io_tx<1>" LOC = "L3" ; -NET "io_tx<2>" LOC = "L2" ; -NET "io_tx<3>" LOC = "F1" ; -NET "io_tx<4>" LOC = "F3" ; -NET "io_tx<5>" LOC = "G3" ; -NET "io_tx<6>" LOC = "E3" ; -NET "io_tx<7>" LOC = "E2" ; -NET "io_tx<8>" LOC = "E4" ; -NET "io_tx<9>" LOC = "F4" ; -NET "io_tx<10>" LOC = "D1" ; -NET "io_tx<11>" LOC = "E1" ; -NET "io_tx<12>" LOC = "D4" ; -NET "io_tx<13>" LOC = "D3" ; -NET "io_tx<14>" LOC = "C2" ; -NET "io_tx<15>" LOC = "C1" ; - -## RX DB -NET "io_rx<0>" LOC = "D7" ; -NET "io_rx<1>" LOC = "C6" ; -NET "io_rx<2>" LOC = "A6" ; -NET "io_rx<3>" LOC = "B6" ; -NET "io_rx<4>" LOC = "E9" ; -NET "io_rx<5>" LOC = "A7" ; -NET "io_rx<6>" LOC = "C7" ; -NET "io_rx<7>" LOC = "B10" ; -NET "io_rx<8>" LOC = "A10" ; -NET "io_rx<9>" LOC = "C11" ; -NET "io_rx<10>" LOC = "A11" ; -NET "io_rx<11>" LOC = "D11" ; -NET "io_rx<12>" LOC = "B12" ; -NET "io_rx<13>" LOC = "A12" ; -NET "io_rx<14>" LOC = "A14" ; -NET "io_rx<15>" LOC = "A13" ; - -## SPI -#NET "SEN_AUX" LOC = "C12" ; -#NET "SCLK_AUX" LOC = "D12" ; -#NET "MISO_AUX" LOC = "J5" ; -NET "SCLK_CODEC" LOC = "K3" ; -NET "SEN_CODEC" LOC = "D13" ; -NET "MOSI_CODEC" LOC = "C13" ; -NET "MISO_CODEC" LOC = "G4" ; - -NET "MISO_RX_DB" LOC = "E6" ; -NET "SEN_RX_DB" LOC = "B4" ; -NET "MOSI_RX_DB" LOC = "A5" ; -NET "SCLK_RX_DB" LOC = "C5" ; - -NET "MISO_TX_DB" LOC = "J4" ; -NET "SEN_TX_DB" LOC = "N2" ; -NET "MOSI_TX_DB" LOC = "L1" ; -NET "SCLK_TX_DB" LOC = "G1" ; - -## Dedicated pins -#NET "TMS" LOC = "B2" ; -#NET "TDO" LOC = "B16" ; -#NET "TDI" LOC = "B1" ; -#NET "TCK" LOC = "A15" ; - -#NET "fpga_cfg_prog_b" LOC = "A2" ; -#NET "fpga_cfg_done" LOC = "T15" ; diff --git a/fpga/usrp2/top/B100/B100.v b/fpga/usrp2/top/B100/B100.v deleted file mode 100644 index d26d0a0d0..000000000 --- a/fpga/usrp2/top/B100/B100.v +++ /dev/null @@ -1,218 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module B100 - (input CLK_FPGA_P, input CLK_FPGA_N, // Diff - output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - - // GPIF - inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output GPIF_SLOE, - output [1:0] GPIF_ADR, output GPIF_SLWR, output GPIF_SLRD, output GPIF_PKTEND, - input IFCLK, - - inout SDA_FPGA, inout SCL_FPGA, // I2C - - output SCLK_TX_DB, output SEN_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, // DB TX SPI - output SCLK_RX_DB, output SEN_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, // DB TX SPI - output SCLK_CODEC, output SEN_CODEC, output MOSI_CODEC, input MISO_CODEC, // AD9862 main SPI - - input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, - - inout [15:0] io_tx, inout [15:0] io_rx, - - output [13:0] dac, output TXSYNC, output TXBLANK, - input [11:0] adc, input RXSYNC, - - input PPS_IN, - input reset_n, output reset_codec, - input ext_reset - ); - - assign reset_codec = 1; // Believed to be active low - - // ///////////////////////////////////////////////////////////////////////// - // Clocking - wire clk_fpga, clk_fpga_in, reset; - wire gpif_clk = IFCLK; - wire gpif_rst; - - IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) - clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - - BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga)); - - reset_sync reset_sync(.clk(clk_fpga), .reset_in((~reset_n) | (~ext_reset)), .reset_out(reset)); - reset_sync reset_sync_gpif(.clk(gpif_clk), .reset_in((~reset_n) | (~ext_reset)), .reset_out(gpif_rst)); - - // ///////////////////////////////////////////////////////////////////////// - // SPI - wire mosi, sclk, miso; - assign { SCLK_TX_DB, MOSI_TX_DB } = ~SEN_TX_DB ? {sclk,mosi} : 2'b0; - assign { SCLK_RX_DB, MOSI_RX_DB } = ~SEN_RX_DB ? {sclk,mosi} : 2'b0; - assign { SCLK_CODEC, MOSI_CODEC } = ~SEN_CODEC ? {sclk,mosi} : 2'b0; - assign miso = (~SEN_TX_DB & MISO_TX_DB) | (~SEN_RX_DB & MISO_RX_DB) | - (~SEN_CODEC & MISO_CODEC); - - // ///////////////////////////////////////////////////////////////////////// - // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL - - assign TXBLANK = 0; - wire [13:0] tx_i, tx_q; - - genvar i; - generate - for(i=0;i<14;i=i+1) - begin : gen_dacout - ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" - .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 - .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset - ODDR2_inst (.Q(dac[i]), // 1-bit DDR output data - .C0(clk_fpga), // 1-bit clock input - .C1(~clk_fpga), // 1-bit clock input - .CE(1'b1), // 1-bit clock enable input - .D0(tx_i[i]), // 1-bit data input (associated with C0) - .D1(tx_q[i]), // 1-bit data input (associated with C1) - .R(1'b0), // 1-bit reset input - .S(1'b0)); // 1-bit set input - end // block: gen_dacout - endgenerate - ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" - .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 - .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset - ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data - .C0(clk_fpga), // 1-bit clock input - .C1(~clk_fpga), // 1-bit clock input - .CE(1'b1), // 1-bit clock enable input - .D0(1'b0), // 1-bit data input (associated with C0) - .D1(1'b1), // 1-bit data input (associated with C1) - .R(1'b0), // 1-bit reset input - .S(1'b0)); // 1-bit set input - - // ///////////////////////////////////////////////////////////////////////// - // RX ADC -- handles deinterleaving - - wire rxsync_0, rxsync_1; - reg [11:0] rx_i, rx_q; - wire [11:0] rx_a, rx_b; - - genvar j; - generate - for(j=0;j<12;j=j+1) - begin : gen_adcin - IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" - .INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1 - .INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1 - .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset - IDDR2_inst (.Q0(rx_a[j]), // 1-bit output captured with C0 clock - .Q1(rx_b[j]), // 1-bit output captured with C1 clock - .C0(clk_fpga), // 1-bit clock input - .C1(~clk_fpga), // 1-bit clock input - .CE(1'b1), // 1-bit clock enable input - .D(adc[j]), // 1-bit DDR data input - .R(1'b0), // 1-bit reset input - .S(1'b0)); // 1-bit set input - end // block: gen_adcin - endgenerate - - IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" - .INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1 - .INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1 - .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset - IDDR2_sync (.Q0(rxsync_0), // 1-bit output captured with C0 clock - .Q1(rxsync_1), // 1-bit output captured with C1 clock - .C0(clk_fpga), // 1-bit clock input - .C1(~clk_fpga), // 1-bit clock input - .CE(1'b1), // 1-bit clock enable input - .D(RXSYNC), // 1-bit DDR data input - .R(1'b0), // 1-bit reset input - .S(1'b0)); // 1-bit set input - - always @(posedge clk_fpga) - if(rxsync_0) - begin - rx_i <= ~rx_b; - rx_q <= ~rx_a; - end - else - begin - rx_i <= ~rx_a; - rx_q <= ~rx_b; - end - - // ///////////////////////////////////////////////////////////////////////// - // Main Core - wire [35:0] rx_data, tx_data, ctrl_data, resp_data; - wire rx_src_rdy, rx_dst_rdy, tx_src_rdy, tx_dst_rdy, resp_src_rdy, resp_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy; - wire dsp_rx_run, dsp_tx_run; - wire [7:0] sen8; - assign {SEN_CODEC,SEN_TX_DB,SEN_RX_DB} = sen8[2:0]; - wire [31:0] core_debug; - - assign debug_led = {dsp_tx_run, dsp_rx_run, cgen_st_ld}; - wire cgen_sync; - assign { cgen_sync_b, cgen_ref_sel } = {~cgen_sync, 1'b1}; - - u1plus_core #( -`ifdef NUM_RX_DSP - .NUM_RX_DSPS(`NUM_RX_DSP), -`else - .NUM_RX_DSPS(1), -`endif - .DSP_RX_XTRA_FIFOSIZE(11), - .DSP_TX_XTRA_FIFOSIZE(12), - .USE_PACKET_PADDER(1) - ) core( - .clk(clk_fpga), .reset(reset), - .debug(core_debug), .debug_clk(debug_clk), - - .rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy), - .tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy), - .ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy), - .resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy), - - .dsp_rx_run(dsp_rx_run), .dsp_tx_run(dsp_tx_run), - .clock_sync(cgen_sync), - - .db_sda(SDA_FPGA), .db_scl(SCL_FPGA), - .sclk(sclk), .sen(sen8), .mosi(mosi), .miso(miso), - .io_tx(io_tx), .io_rx(io_rx), - .tx_i(tx_i), .tx_q(tx_q), - .rx_i(rx_i), .rx_q(rx_q), - .pps_in(PPS_IN) ); - - // ///////////////////////////////////////////////////////////////////////// - // Interface from host to/from GPIF - wire [31:0] gpif_debug; - slave_fifo slave_fifo (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_d(GPIF_D), - .gpif_ctl(GPIF_CTL), .sloe(GPIF_SLOE), .slwr(GPIF_SLWR), .slrd(GPIF_SLRD), - .pktend(GPIF_PKTEND), .fifoadr(GPIF_ADR), - - .fifo_clk(clk_fpga), .fifo_rst(reset), - .rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy), - .tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy), - .ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy), - .resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy), - - .debug(gpif_debug)); - - //assign debug = gpif_debug; - assign debug = core_debug; - -endmodule // B100 diff --git a/fpga/usrp2/top/B100/Makefile b/fpga/usrp2/top/B100/Makefile deleted file mode 100644 index fdd507394..000000000 --- a/fpga/usrp2/top/B100/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright 2011 Ettus Research LLC -# - -all: B100 B100_2RX - find -name "*.twr" | xargs grep constraint | grep met - -clean: - rm -rf build* - -B100: - make -f Makefile.$@ bin - -B100_2RX: - make -f Makefile.$@ bin - -.PHONY: all clean diff --git a/fpga/usrp2/top/B100/Makefile.B100 b/fpga/usrp2/top/B100/Makefile.B100 deleted file mode 100644 index 4687f2169..000000000 --- a/fpga/usrp2/top/B100/Makefile.B100 +++ /dev/null @@ -1,106 +0,0 @@ -# -# Copyright 2008-2012 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE := B100 -BUILD_DIR := build-B100/ - -# set me in a custom makefile -CUSTOM_SRCS = -CUSTOM_DEFS = - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../gpif/Makefile.srcs - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan3A" \ -device XC3S1400A \ -package ft256 \ -speed -4 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -B100.v \ -u1plus_core.v \ -B100.ucf \ -timing.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ -$(GPIF_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto \ -"Verilog Macros" "$(CUSTOM_DEFS)" - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Generate Detailed MAP Report" TRUE \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 \ -"Unused IOB Pins" "Pull Up" - -SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/B100/Makefile.B100_2RX b/fpga/usrp2/top/B100/Makefile.B100_2RX deleted file mode 100644 index ba535dfb0..000000000 --- a/fpga/usrp2/top/B100/Makefile.B100_2RX +++ /dev/null @@ -1,106 +0,0 @@ -# -# Copyright 2008-2012 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE := B100 -BUILD_DIR := build-B100_2RX/ - -# set me in a custom makefile -CUSTOM_SRCS = -CUSTOM_DEFS = - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../gpif/Makefile.srcs - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan3A" \ -device XC3S1400A \ -package ft256 \ -speed -4 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -B100.v \ -u1plus_core.v \ -B100.ucf \ -timing.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ -$(GPIF_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto \ -"Verilog Macros" "NUM_RX_DSP=2 DISABLE_TX_DSP=1 $(CUSTOM_DEFS)" - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Generate Detailed MAP Report" TRUE \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 \ -"Unused IOB Pins" "Pull Up" - -SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/B100/core_compile b/fpga/usrp2/top/B100/core_compile deleted file mode 100755 index 2192bfa94..000000000 --- a/fpga/usrp2/top/B100/core_compile +++ /dev/null @@ -1 +0,0 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac B100.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models diff --git a/fpga/usrp2/top/B100/timing.ucf b/fpga/usrp2/top/B100/timing.ucf deleted file mode 100644 index 7b212a9a6..000000000 --- a/fpga/usrp2/top/B100/timing.ucf +++ /dev/null @@ -1,24 +0,0 @@ -NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; -TIMESPEC "TS_CLK_FPGA_P" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; - -NET "IFCLK" TNM_NET = "IFCLK"; -TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20833 ps HIGH 50 %; - -#constrain FX2 IO -INST "GPIF_D<*>" TNM = gpif_net_in; -INST "GPIF_CTL<*>" TNM = gpif_net_in; - -INST "GPIF_D<*>" TNM = gpif_net_out; -INST "GPIF_ADR<*>" TNM = gpif_net_out; -INST "GPIF_SLWR" TNM = gpif_net_out; -INST "GPIF_SLOE" TNM = gpif_net_out; -INST "GPIF_SLRD" TNM = gpif_net_out; -INST "GPIF_PKTEND" TNM = gpif_net_out; - -TIMEGRP "gpif_net_in" OFFSET = IN 5 ns VALID 10 ns BEFORE "IFCLK" RISING; -TIMEGRP "gpif_net_out" OFFSET = OUT 7 ns AFTER "IFCLK" RISING; - -TIMESPEC TS_Pad2Pad = FROM PADS TO PADS 7 ns; - -NET PPS_IN TIG; -NET debug_led* TIG; diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v deleted file mode 100644 index 7f137f0d1..000000000 --- a/fpga/usrp2/top/B100/u1plus_core.v +++ /dev/null @@ -1,362 +0,0 @@ -// -// Copyright 2011-2013 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module u1plus_core -#( - parameter NUM_RX_DSPS = 2, - parameter CTRL_ACK_SID = 20, //needed for reply - - parameter DSP_TX_FIFOSIZE = 10, //4K MTU - parameter DSP_RX_FIFOSIZE = 10, //4K MTU - - parameter DSP_RX_XTRA_FIFOSIZE = 11, - parameter DSP_TX_XTRA_FIFOSIZE = 11, - - parameter USE_PACKET_PADDER = 0 -) - (input clk, input reset, - output [31:0] debug, output [1:0] debug_clk, - - // Host Interface - input [35:0] tx_data, input tx_src_rdy, output tx_dst_rdy, - output [35:0] rx_data, output rx_src_rdy, input rx_dst_rdy, - input [35:0] ctrl_data, input ctrl_src_rdy, output ctrl_dst_rdy, - output [35:0] resp_data, output resp_src_rdy, input resp_dst_rdy, - - output dsp_rx_run, output dsp_tx_run, output clock_sync, - - inout db_sda, inout db_scl, - output sclk, output [7:0] sen, output mosi, input miso, - - inout [15:0] io_tx, inout [15:0] io_rx, - output [13:0] tx_i, output [13:0] tx_q, - input [11:0] rx_i, input [11:0] rx_q, - input pps_in - ); - - localparam SR_MISC = 0; // 5 - localparam SR_USER_REGS = 5; // 2 - localparam SR_PADDER = 10; // 2 - - localparam SR_TX_CTRL = 32; // 6 - localparam SR_TX_DSP = 40; // 5 - localparam SR_TX_FE = 48; // 5 - - localparam SR_RX_CTRL0 = 96; // 9 - localparam SR_RX_DSP0 = 106; // 7 - localparam SR_RX_FE = 114; // 5 - - localparam SR_RX_CTRL1 = 128; // 9 - localparam SR_RX_DSP1 = 138; // 7 - - localparam SR_TIME64 = 192; // 6 - localparam SR_SPI = 208; // 3 - localparam SR_I2C = 216; // 1 - localparam SR_GPIO = 224; // 5 - - //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd11, 16'd4}; //major, minor - - //assign run signals used for ATR logic - wire [NUM_RX_DSPS-1:0] run_rx_n; - wire run_tx; - wire run_rx = |(run_rx_n); - assign dsp_rx_run = run_rx; - assign dsp_tx_run = run_tx; - - //shared time core signals - wire [63:0] vita_time, vita_time_pps; - - //shared settings bus signals - wire set_stb, set_stb_user; - wire [31:0] set_data, set_data_user; - wire [7:0] set_addr, set_addr_user; - - //shared SPI core signals - wire [31:0] spi_readback; - wire spi_ready; - - //shared I2C core signals - wire [31:0] i2c_readback; - wire i2c_ready; - - //shared GPIO core signals - wire [31:0] gpio_readback; - - /////////////////////////////////////////////////////////////////////////// - // Misc Registers - persistent across resets - /////////////////////////////////////////////////////////////////////////// - wire [31:0] config_word0; - setting_reg #(.my_addr(SR_MISC+0), .width(32)) sr_misc_config0 - (.clk(clk), .rst(1'b0/*reset*/), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(config_word0)); - - wire [31:0] config_word1; - setting_reg #(.my_addr(SR_MISC+1), .width(32)) sr_misc_config1 - (.clk(clk), .rst(1'b0/*reset*/), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(config_word1)); - - wire clock_sync_inv, clock_sync_enb; - setting_reg #(.my_addr(SR_MISC+2), .width(2)) sr_misc_clock_sync - (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), - .out({clock_sync_inv, clock_sync_enb})); - - /////////////////////////////////////////////////////////////////////////// - // Settings Bus and Readback - /////////////////////////////////////////////////////////////////////////// - user_settings #(.BASE(SR_USER_REGS)) user_settings - (.clk(clk),.rst(reset), - .set_stb(set_stb), .set_addr(set_addr),.set_data(set_data), - .set_addr_user(set_addr_user),.set_data_user(set_data_user), .set_stb_user(set_stb_user) ); - - wire [35:0] ctrl_out_data, ctrl_int_data; - wire ctrl_out_src_rdy, ctrl_out_dst_rdy; - wire ctrl_int_src_rdy, ctrl_int_dst_rdy; - - fifo_cascade #(.WIDTH(36), .SIZE(9)) ctrl_fifo - (.clk(clk), .reset(reset), .clear(1'b0), - .datain(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy), .space(), - .dataout(ctrl_int_data), .src_rdy_o(ctrl_int_src_rdy), .dst_rdy_i(ctrl_int_dst_rdy), .occupied()); - - wire [31:0] num_rx_dsps_rb = NUM_RX_DSPS; - - wire [31:0] sfc_debug; - settings_fifo_ctrl #(.PROT_HDR(0), .ACK_SID(CTRL_ACK_SID), .XPORT_HDR(0)) sfc - ( - .clock(clk), .reset(reset), .clear(1'b0), - .vita_time(vita_time), .perfs_ready(spi_ready & i2c_ready), - .in_data(ctrl_int_data), .in_valid(ctrl_int_src_rdy), .in_ready(ctrl_int_dst_rdy), - .out_data(ctrl_out_data), .out_valid(ctrl_out_src_rdy), .out_ready(ctrl_out_dst_rdy), - .strobe(set_stb), .addr(set_addr), .data(set_data), - .word00(spi_readback),.word01(compat_num),.word02(i2c_readback),.word03(gpio_readback), - .word04(config_word0),.word05(config_word1),.word06(num_rx_dsps_rb),.word07(32'hffff_ffff), - .word08(32'hffff_ffff),.word09(32'hffff_ffff),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(32'hffff_ffff),.word13(32'hffff_ffff), - .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]), - .debug(sfc_debug) - ); - - /////////////////////////////////////////////////////////////////////////// - // Time Core - /////////////////////////////////////////////////////////////////////////// - time_64bit #(.BASE(SR_TIME64)) time_64bit - (.clk(clk), .rst(reset), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), - .exp_time_in(0)); - - assign clock_sync = (clock_sync_enb)? (pps_in ^ clock_sync_inv) : 1'b0; - - /////////////////////////////////////////////////////////////////////////// - // SPI Core - /////////////////////////////////////////////////////////////////////////// - simple_spi_core #(.BASE(SR_SPI), .WIDTH(8), .CLK_IDLE(0), .SEN_IDLE(8'hff)) - simple_spi_core (.clock(clk), .reset(reset), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .readback(spi_readback), .ready(spi_ready), - .sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso)); - - /////////////////////////////////////////////////////////////////////////// - // I2C Core - /////////////////////////////////////////////////////////////////////////// - wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o; - simple_i2c_core #(.BASE(SR_I2C)) i2c_core - (.clock(clk),.reset(reset), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .readback(i2c_readback), .ready(i2c_ready), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - // I2C -- Don't use external transistors for open drain, the FPGA implements this - IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o)); - - /////////////////////////////////////////////////////////////////////////// - // GPIO Core - /////////////////////////////////////////////////////////////////////////// - gpio_atr #(.BASE(SR_GPIO), .WIDTH(32)) - gpio_atr(.clk(clk),.reset(reset), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .rx(run_rx), .tx(run_tx), .gpio({io_tx, io_rx}), .gpio_readback(gpio_readback) ); - - // ///////////////////////////////////////////////////////////////////////// - // RX ADC Frontend, does IQ Balance, DC Offset, muxing - - wire [23:0] rx_fe_i, rx_fe_q; // 24 bits is total overkill here, but it matches u2/u2p - - rx_frontend #(.BASE(SR_RX_FE)) rx_frontend - (.clk(clk),.rst(reset), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a({rx_i,4'b00}),.adc_ovf_a(0), - .adc_b({rx_q,4'b00}),.adc_ovf_b(0), - .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx), .debug()); - - // ///////////////////////////////////////////////////////////////////////// - // DSP RX * - - wire [35:0] rx_int2_data [NUM_RX_DSPS-1:0]; - wire rx_int2_src_rdy [NUM_RX_DSPS-1:0]; - wire rx_int2_dst_rdy [NUM_RX_DSPS-1:0]; - - genvar dspno; - generate - for(dspno = 0; dspno < NUM_RX_DSPS; dspno = dspno + 1) begin:gen_rx_dsps - - wire [31:0] sample_rx; - wire strobe_rx, clear_rx; - wire [35:0] vita_rx_data; - wire vita_rx_src_rdy, vita_rx_dst_rdy; - wire [35:0] int_rx_data; - wire int_rx_src_rdy, int_rx_dst_rdy; - - ddc_chain #(.BASE(SR_RX_DSP0+dspno*32), .DSPNO(dspno)) ddc_chain - (.clk(clk), .rst(reset), .clr(clear_rx), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), - .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), - .sample(sample_rx), .run(run_rx_n[dspno]), .strobe(strobe_rx), - .debug() ); - - vita_rx_chain #(.BASE(SR_RX_CTRL0+dspno*32), .UNIT(dspno), .FIFOSIZE(DSP_RX_FIFOSIZE), .PROT_ENG_FLAGS(0), .DSP_NUMBER(dspno)) vita_rx_chain - (.clk(clk),.reset(reset), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), - .vita_time(vita_time), .overrun(), - .sample(sample_rx), .run(run_rx_n[dspno]), .strobe(strobe_rx), .clear_o(clear_rx), - .rx_data_o(vita_rx_data), .rx_dst_rdy_i(vita_rx_dst_rdy), .rx_src_rdy_o(vita_rx_src_rdy), - .debug() ); - - fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE+1)) rx_data_fifo - (.clk(clk), .reset(reset), .clear(1'b0), - .datain(vita_rx_data), .src_rdy_i(vita_rx_src_rdy), .dst_rdy_o(vita_rx_dst_rdy), .space(), - .dataout(int_rx_data), .src_rdy_o(int_rx_src_rdy), .dst_rdy_i(int_rx_dst_rdy), .occupied()); - - if (dspno == 0) begin - assign rx_int2_data[dspno] = int_rx_data; - assign rx_int2_src_rdy[dspno] = int_rx_src_rdy; - assign int_rx_dst_rdy = rx_int2_dst_rdy[dspno]; - end - else begin - fifo36_mux #(.prio(0)) // No priority, fair sharing - combine_rx_dsps ( - .clk(clk), .reset(reset), .clear(1'b0/*noclear*/), - .data0_i(rx_int2_data[dspno-1]), .src0_rdy_i(rx_int2_src_rdy[dspno-1]), .dst0_rdy_o(rx_int2_dst_rdy[dspno-1]), - .data1_i(int_rx_data), .src1_rdy_i(int_rx_src_rdy), .dst1_rdy_o(int_rx_dst_rdy), - .data_o(rx_int2_data[dspno]), .src_rdy_o(rx_int2_src_rdy[dspno]), .dst_rdy_i(rx_int2_dst_rdy[dspno]) - ); - end - - end - endgenerate - - // ///////////////////////////////////////////////////////////////////////// - // RX Stream muxing - - wire [35:0] rx_int3_data; - wire rx_int3_src_rdy, rx_int3_dst_rdy; - - fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_XTRA_FIFOSIZE)) rx_data_fifo_combined - (.clk(clk), .reset(reset), .clear(1'b0), - .datain(rx_int2_data[NUM_RX_DSPS-1]), .src_rdy_i(rx_int2_src_rdy[NUM_RX_DSPS-1]), .dst_rdy_o(rx_int2_dst_rdy[NUM_RX_DSPS-1]), .space(), - .dataout(rx_int3_data), .src_rdy_o(rx_int3_src_rdy), .dst_rdy_i(rx_int3_dst_rdy), .occupied()); - - generate - if (USE_PACKET_PADDER) begin - packet_padder36 #(.BASE(SR_PADDER)) packet_padder_rx_data36( - .clk(clk), .reset(reset), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .data_i(rx_int3_data), .src_rdy_i(rx_int3_src_rdy), .dst_rdy_o(rx_int3_dst_rdy), - .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy), - .always_flush(~dsp_rx_run)); - end - else begin - assign rx_data = rx_int3_data; - assign rx_src_rdy = rx_int3_src_rdy; - assign rx_int3_dst_rdy = rx_dst_rdy; - end - endgenerate - - /////////////////////////////////////////////////////////////////////////// - // MUX for TX async and resp data - /////////////////////////////////////////////////////////////////////////// - wire [35:0] tx_err_data, resp_data_int; - wire tx_err_src_rdy, resp_src_rdy_int; - wire tx_err_dst_rdy, resp_dst_rdy_int; - - fifo36_mux #(.prio(0)) // No priority, fair sharing - combine_async_and_resp ( - .clk(clk), .reset(reset), .clear(1'b0/*noclear*/), - .data0_i(ctrl_out_data), .src0_rdy_i(ctrl_out_src_rdy), .dst0_rdy_o(ctrl_out_dst_rdy), - .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), - .data_o(resp_data_int), .src_rdy_o(resp_src_rdy_int), .dst_rdy_i(resp_dst_rdy_int) - ); - - fifo_cascade #(.WIDTH(36), .SIZE(9)) resp_fifo - (.clk(clk), .reset(reset), .clear(1'b0), - .datain(resp_data_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int), .space(), - .dataout(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy), .occupied()); - - // /////////////////////////////////////////////////////////////////////////////////// - // DSP TX - - wire [23:0] tx_fe_i, tx_fe_q; - wire [31:0] sample_tx; - wire strobe_tx, clear_tx; - -`ifdef DISABLE_TX_DSP - assign tx_dst_rdy = 1; //null sink - assign run_tx = 0; - assign tx_i = 0; - assign tx_q = 0; -`else - vita_tx_chain #(.BASE(SR_TX_CTRL), - .FIFOSIZE(DSP_TX_FIFOSIZE), - .POST_ENGINE_FIFOSIZE(DSP_TX_XTRA_FIFOSIZE), - .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), - .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), - .DSP_NUMBER(0)) - vita_tx_chain - (.clk(clk), .reset(reset), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), - .vita_time(vita_time), - .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), - .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), - .sample(sample_tx), .strobe(strobe_tx), - .underrun(), .run(run_tx), .clear_o(clear_tx), - .debug()); - - duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain - (.clk(clk), .rst(reset), .clr(clear_tx), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), - .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .debug() ); - - tx_frontend #(.BASE(SR_TX_FE), .WIDTH_OUT(14)) tx_frontend - (.clk(clk), .rst(reset), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1), - .dac_a(tx_i), .dac_b(tx_q)); -`endif - // ///////////////////////////////////////////////////////////////////////////////////// - // Debug circuitry - - assign debug_clk = 2'b11; - assign debug = 32'hffffffff; - -endmodule // u1plus_core diff --git a/fpga/usrp2/top/E1x0/.gitignore b/fpga/usrp2/top/E1x0/.gitignore deleted file mode 100644 index 8d872713e..000000000 --- a/fpga/usrp2/top/E1x0/.gitignore +++ /dev/null @@ -1,6 +0,0 @@ -*~ -build -*.log -*.cmd -tb_u1e -*.lxt diff --git a/fpga/usrp2/top/E1x0/E1x0.ucf b/fpga/usrp2/top/E1x0/E1x0.ucf deleted file mode 100644 index 278fc289a..000000000 --- a/fpga/usrp2/top/E1x0/E1x0.ucf +++ /dev/null @@ -1,261 +0,0 @@ - -NET "CLK_FPGA_P" LOC = "Y11" ; -NET "CLK_FPGA_N" LOC = "Y10" ; - -## GPMC -NET "EM_D<15>" LOC = "D13" ; -NET "EM_D<14>" LOC = "D15" ; -NET "EM_D<13>" LOC = "C16" ; -NET "EM_D<12>" LOC = "B20" ; -NET "EM_D<11>" LOC = "A19" ; -NET "EM_D<10>" LOC = "A17" ; -NET "EM_D<9>" LOC = "E15" ; -NET "EM_D<8>" LOC = "F15" ; -NET "EM_D<7>" LOC = "E16" ; -NET "EM_D<6>" LOC = "F16" ; -NET "EM_D<5>" LOC = "B17" ; -NET "EM_D<4>" LOC = "C17" ; -NET "EM_D<3>" LOC = "B19" ; -NET "EM_D<2>" LOC = "D19" ; -NET "EM_D<1>" LOC = "C19" ; -NET "EM_D<0>" LOC = "A20" ; - -NET "EM_A<10>" LOC = "C14" ; -NET "EM_A<9>" LOC = "C10" ; -NET "EM_A<8>" LOC = "C5" ; -NET "EM_A<7>" LOC = "A18" ; -NET "EM_A<6>" LOC = "A15" ; -NET "EM_A<5>" LOC = "A12" ; -NET "EM_A<4>" LOC = "A10" ; -NET "EM_A<3>" LOC = "E7" ; -NET "EM_A<2>" LOC = "A7" ; -NET "EM_A<1>" LOC = "C15" ; - -NET "EM_NCS6" LOC = "E17" ; -NET "EM_NCS5" LOC = "E10" ; -NET "EM_NCS4" LOC = "E6" ; -#NET "EM_NCS1" LOC = "D18" ; -#NET "EM_NCS0" LOC = "D17" ; - -NET "EM_CLK" LOC = "F11" ; -NET "EM_WAIT0" LOC = "F14" ; -NET "EM_NBE<1>" LOC = "D14" ; -NET "EM_NBE<0>" LOC = "A13" ; -NET "EM_NWE" LOC = "B13" ; -NET "EM_NOE" LOC = "A14" ; -#NET "EM_NADV_ALE" LOC = "B15" ; -#NET "EM_NWP" LOC = "F13" ; - -## Overo GPIO -NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug -NET "overo_gpio14" LOC = "C4" ; # MISC GPIO for debug -NET "overo_gpio21" LOC = "D5" ; # MISC GPIO for debug -NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug -NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug -NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug -NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug - -NET "overo_gpio127" LOC = "C8" ; # Changed name to gpio10 -NET "overo_gpio128" LOC = "G8" ; # Changed name to gpio186 - -NET "overo_gpio144" LOC = "A5" ; # tx_have_space -NET "overo_gpio145" LOC = "C7" ; # tx_underrun -NET "overo_gpio146" LOC = "A6" ; # rx_have_data -NET "overo_gpio147" LOC = "B6" ; # rx_overrun -NET "overo_gpio163" LOC = "D7" ; # MISC GPIO for debug -NET "overo_gpio170" LOC = "E8" ; # MISC GPIO for debug -NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug - -## Overo UART -NET "overo_txd1" LOC = "C6" ; -NET "overo_rxd1" LOC = "D6" ; -NET "fpga_txd1" LOC = "AB9" ; -NET "fpga_rxd1" LOC = "AB8" ; - -## FTDI UART to USB converter -NET "FPGA_TXD" LOC = "G19" ; -NET "FPGA_RXD" LOC = "F20" ; - -#NET "SYSEN" LOC = "C11" ; - -## I2C -NET "db_scl" LOC = "F19" ; -NET "db_sda" LOC = "F18" ; - -## SPI -### DBoard SPI -NET "db_sclk_rx" LOC = "D21" ; -NET "db_miso_rx" LOC = "D22" ; -NET "db_mosi_rx" LOC = "D20" ; -NET "db_sen_rx" LOC = "E19" ; -NET "db_sclk_tx" LOC = "F21" ; -NET "db_miso_tx" LOC = "E20" ; -NET "db_mosi_tx" LOC = "G17" ; -NET "db_sen_tx" LOC = "G18" ; - -### AD9862 SPI and aux SPI Interfaces -#NET "aux_sdi_codec" LOC = "G3" ; -#NET "aux_sdo_codec" LOC = "F3" ; -#NET "aux_sclk_codec" LOC = "C1" ; -NET "sen_codec" LOC = "F5" |IOSTANDARD = LVCMOS33; -NET "mosi_codec" LOC = "F4" |IOSTANDARD = LVCMOS33; -NET "miso_codec" LOC = "H4" ; -NET "sclk_codec" LOC = "H3" |IOSTANDARD = LVCMOS33; - -### Clock Gen SPI -NET "cgen_miso" LOC = "F22" ; -NET "cgen_mosi" LOC = "E22" ; -NET "cgen_sclk" LOC = "J19" ; -NET "cgen_sen_b" LOC = "H20" ; - -## Clock gen control -NET "cgen_st_status" LOC = "P20" ; -NET "cgen_st_ld" LOC = "R17" ; -NET "cgen_st_refmon" LOC = "P17" ; -NET "cgen_sync_b" LOC = "U18" ; -NET "cgen_ref_sel" LOC = "U19" ; - -## Debug pins -NET "debug_led<3>" LOC = "Y15" ; -NET "debug_led<2>" LOC = "K16" ; -NET "debug_led<1>" LOC = "J17" ; -NET "debug_led<0>" LOC = "H22" ; -NET "debug<0>" LOC = "G22" ; -NET "debug<1>" LOC = "H17" ; -NET "debug<2>" LOC = "H18" ; -NET "debug<3>" LOC = "K20" ; -NET "debug<4>" LOC = "J20" ; -NET "debug<5>" LOC = "K19" ; -NET "debug<6>" LOC = "K18" ; -NET "debug<7>" LOC = "L22" ; -NET "debug<8>" LOC = "K22" ; -NET "debug<9>" LOC = "N22" ; -NET "debug<10>" LOC = "M22" ; -NET "debug<11>" LOC = "N20" ; -NET "debug<12>" LOC = "N19" ; -NET "debug<13>" LOC = "R22" ; -NET "debug<14>" LOC = "P22" ; -NET "debug<15>" LOC = "N17" ; -NET "debug<16>" LOC = "P16" ; -NET "debug<17>" LOC = "U22" ; -NET "debug<18>" LOC = "P19" ; -NET "debug<19>" LOC = "R18" ; -NET "debug<20>" LOC = "U20" ; -NET "debug<21>" LOC = "T20" ; -NET "debug<22>" LOC = "R19" ; -NET "debug<23>" LOC = "R20" ; -NET "debug<24>" LOC = "W22" ; -NET "debug<25>" LOC = "Y22" ; -NET "debug<26>" LOC = "T18" ; -NET "debug<27>" LOC = "T17" ; -NET "debug<28>" LOC = "W19" ; -NET "debug<29>" LOC = "V20" ; -NET "debug<30>" LOC = "Y21" ; -NET "debug<31>" LOC = "AA22" ; -NET "debug_clk<0>" LOC = "N18" ; -NET "debug_clk<1>" LOC = "M17" ; - -NET "debug_pb" LOC = "C22" ; - -#NET "reset_codec" LOC = "C2" ; - -NET "RXSYNC" LOC = "F2" ; -NET "DB<11>" LOC = "G6" ; -NET "DB<10>" LOC = "G5" ; -NET "DB<9>" LOC = "E4" ; -NET "DB<8>" LOC = "E3" ; -NET "DB<7>" LOC = "H6" ; -NET "DB<6>" LOC = "H5" ; -NET "DB<5>" LOC = "H1" ; -NET "DB<4>" LOC = "G1" ; -NET "DB<3>" LOC = "K5" ; -NET "DB<2>" LOC = "K4" ; -NET "DB<1>" LOC = "H2" ; -NET "DB<0>" LOC = "L5" ; - -NET "DA<11>" LOC = "K6" ; -NET "DA<10>" LOC = "K3" ; -NET "DA<9>" LOC = "K2" ; -NET "DA<8>" LOC = "N1" ; -NET "DA<7>" LOC = "N5" ; -NET "DA<6>" LOC = "N6" ; -NET "DA<5>" LOC = "P2" ; -NET "DA<4>" LOC = "P1" ; -NET "DA<3>" LOC = "R6" ; -NET "DA<2>" LOC = "P6" ; -NET "DA<1>" LOC = "R1" ; -NET "DA<0>" LOC = "R2" ; - -NET "TX<13>" LOC = "T6" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<12>" LOC = "U1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<11>" LOC = "T1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<10>" LOC = "R5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<9>" LOC = "V1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<8>" LOC = "U2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<7>" LOC = "T4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<6>" LOC = "R3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<5>" LOC = "W1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<4>" LOC = "Y1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<3>" LOC = "V3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<2>" LOC = "V4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<1>" LOC = "W2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<0>" LOC = "W3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TXSYNC" LOC = "U5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TXBLANK" LOC = "U4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; - -NET "PPS_IN" LOC = "M5" ; - -NET "io_tx<0>" LOC = "AB20" ; -NET "io_tx<1>" LOC = "Y17" ; -NET "io_tx<2>" LOC = "Y16" ; -NET "io_tx<3>" LOC = "U16" ; -NET "io_tx<4>" LOC = "V16" ; -NET "io_tx<5>" LOC = "AB19" ; -NET "io_tx<6>" LOC = "AA19" ; -NET "io_tx<7>" LOC = "U14" ; -NET "io_tx<8>" LOC = "U15" ; -NET "io_tx<9>" LOC = "AB17" ; -NET "io_tx<10>" LOC = "AB18" ; -NET "io_tx<11>" LOC = "Y13" ; -NET "io_tx<12>" LOC = "W14" ; -NET "io_tx<13>" LOC = "U13" ; -NET "io_tx<14>" LOC = "AA15" ; -NET "io_tx<15>" LOC = "AB14" ; - -NET "io_rx<0>" LOC = "Y8" ; -NET "io_rx<1>" LOC = "Y9" ; -NET "io_rx<2>" LOC = "V7" ; -NET "io_rx<3>" LOC = "U8" ; -NET "io_rx<4>" LOC = "V10" ; -NET "io_rx<5>" LOC = "U9" ; -NET "io_rx<6>" LOC = "AB7" ; -NET "io_rx<7>" LOC = "AA8" ; -NET "io_rx<8>" LOC = "W8" ; -NET "io_rx<9>" LOC = "V8" ; -NET "io_rx<10>" LOC = "AB5" ; -NET "io_rx<11>" LOC = "AB6" ; -NET "io_rx<12>" LOC = "AB4" ; -NET "io_rx<13>" LOC = "AA4" ; -NET "io_rx<14>" LOC = "W5" ; -NET "io_rx<15>" LOC = "Y4" ; - -#NET "CLKOUT2_CODEC" LOC = "U12" ; -#NET "CLKOUT1_CODEC" LOC = "V12" ; - -## FPGA Config Pins -#NET "fpga_cfg_prog_b" LOC = "A2" ; -#NET "fpga_cfg_done" LOC = "AB21" ; -#NET "fpga_cfg_din" LOC = "W17" ; -#NET "fpga_cfg_cclk" LOC = "V17" ; -#NET "fpga_cfg_init_b" LOC = "W15" ; - -## Unused -#NET "unnamed_net53" LOC = "B1" ; # TMS -#NET "unnamed_net52" LOC = "B22" ; # TDO -#NET "unnamed_net51" LOC = "D2" ; # TDI -#NET "unnamed_net50" LOC = "A21" ; # TCK -#NET "unnamed_net59" LOC = "F7" ; # PUDC_B -#NET "unnamed_net58" LOC = "V6" ; # M2 -#NET "unnamed_net57" LOC = "AA3" ; # M1 -#NET "unnamed_net56" LOC = "AB3" ; # M0 -#NET "GND" LOC = "V19" ; # Suspend, unused diff --git a/fpga/usrp2/top/E1x0/E1x0.v b/fpga/usrp2/top/E1x0/E1x0.v deleted file mode 100644 index 44129ce92..000000000 --- a/fpga/usrp2/top/E1x0/E1x0.v +++ /dev/null @@ -1,215 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module E1x0 - (input CLK_FPGA_P, input CLK_FPGA_N, // Diff - output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - input debug_pb, output FPGA_TXD, input FPGA_RXD, - output fpga_txd1, input fpga_rxd1, input overo_txd1, output overo_rxd1, - - // GPMC - input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, - input EM_NWE, input EM_NOE, - - inout db_sda, inout db_scl, // I2C - - output db_sclk_tx, output db_sen_tx, output db_mosi_tx, input db_miso_tx, // DB TX SPI - output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx, // DB TX SPI - output sclk_codec, output sen_codec, output mosi_codec, input miso_codec, // AD9862 main SPI - output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso, // Clock gen SPI - - input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, - input overo_gpio65, input overo_gpio128, input overo_gpio145, output overo_gpio147, //aux SPI - - output overo_gpio144, output overo_gpio146, // Fifo controls - input overo_gpio0, input overo_gpio14, input overo_gpio21, input overo_gpio22, // Misc GPIO - input overo_gpio23, input overo_gpio64, input overo_gpio127, // Misc GPIO - input overo_gpio176, input overo_gpio163, input overo_gpio170, // Misc GPIO - - inout [15:0] io_tx, inout [15:0] io_rx, - - output [13:0] TX, output TXSYNC, output TXBLANK, - input [11:0] DA, input [11:0] DB, input RXSYNC, - - input PPS_IN - ); - - assign FPGA_TXD = 0; //dont care - - // ///////////////////////////////////////////////////////////////////////// - // Clocking - wire clk_fpga; - wire reset; - - reg por_rst; - reg [7:0] por_counter = 8'h0; - - always @(posedge clk_fpga) - if (por_counter != 8'h55) - begin - por_counter <= por_counter + 8'h1; - por_rst <= 1'b1; - end - else por_rst <= 1'b0; - - wire async_reset; - cross_clock_reader #(.WIDTH(1)) read_gpio_reset - (.clk(clk_fpga), .rst(por_rst), .in(cgen_sen_b & ~cgen_sclk), .out(async_reset)); - - IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) - clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - - reset_sync reset_sync(.clk(clk_fpga), .reset_in(async_reset), .reset_out(reset)); - - // ///////////////////////////////////////////////////////////////////////// - // UART level conversion - assign fpga_txd1 = overo_txd1; - assign overo_rxd1 = fpga_rxd1; - - // SPI - wire mosi, sclk, miso; - assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0; - assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0; - assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0; - //assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; //replaced by aux spi - assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) | - (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso); - - //assign the aux spi to the cgen (bypasses control fifo) - assign cgen_sclk = overo_gpio65; - assign cgen_sen_b = overo_gpio128; - assign cgen_mosi = overo_gpio145; - wire has_resp; //re-purpose gpio for interrupt when we are not using aux spi - assign overo_gpio147 = (cgen_sen_b == 1'b0)? cgen_miso : has_resp; - - wire _cgen_sen_b; - //assign cgen_sen_b = _cgen_sen_b; //replaced by aux spi - - // ///////////////////////////////////////////////////////////////////////// - // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL - - assign TXBLANK = 0; - wire [13:0] tx_i, tx_q; - - reg[13:0] delay_q; - always @(posedge clk_fpga) - delay_q <= tx_q; - - genvar i; - generate - for(i=0;i<14;i=i+1) - begin : gen_dacout - ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" - .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 - .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset - ODDR2_inst (.Q(TX[i]), // 1-bit DDR output data - .C0(clk_fpga), // 1-bit clock input - .C1(~clk_fpga), // 1-bit clock input - .CE(1'b1), // 1-bit clock enable input - .D0(tx_i[i]), // 1-bit data input (associated with C0) - .D1(delay_q[i]), // 1-bit data input (associated with C1) - .R(1'b0), // 1-bit reset input - .S(1'b0)); // 1-bit set input - end // block: gen_dacout - endgenerate - ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" - .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 - .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset - ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data - .C0(clk_fpga), // 1-bit clock input - .C1(~clk_fpga), // 1-bit clock input - .CE(1'b1), // 1-bit clock enable input - .D0(1'b0), // 1-bit data input (associated with C0) - .D1(1'b1), // 1-bit data input (associated with C1) - .R(1'b0), // 1-bit reset input - .S(1'b0)); // 1-bit set input - - // ///////////////////////////////////////////////////////////////////////// - // RX ADC -- handles inversion - - reg [11:0] rx_i, rx_q; - always @(posedge clk_fpga) begin - rx_i <= ~DA; - rx_q <= ~DB; - end - - // ///////////////////////////////////////////////////////////////////////// - // Main Core - wire [35:0] rx_data, tx_data, ctrl_data, resp_data; - wire rx_src_rdy, rx_dst_rdy, tx_src_rdy, tx_dst_rdy, resp_src_rdy, resp_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy; - wire dsp_rx_run, dsp_tx_run; - wire [7:0] sen8; - assign {_cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx} = sen8[3:0]; - wire [31:0] core_debug; - - assign debug_led = ~{PPS_IN, dsp_tx_run, dsp_rx_run, cgen_st_ld}; - wire cgen_sync; - assign { cgen_sync_b, cgen_ref_sel } = {~cgen_sync, 1'b1}; - - u1plus_core #( - .NUM_RX_DSPS(2), - .DSP_RX_XTRA_FIFOSIZE(10), - .DSP_TX_XTRA_FIFOSIZE(10), - .USE_PACKET_PADDER(0) - ) core( - .clk(clk_fpga), .reset(reset), - .debug(core_debug), .debug_clk(debug_clk), - - .rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy), - .tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy), - .ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy), - .resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy), - - .dsp_rx_run(dsp_rx_run), .dsp_tx_run(dsp_tx_run), - .clock_sync(cgen_sync), - - .db_sda(db_sda), .db_scl(db_scl), - .sclk(sclk), .sen(sen8), .mosi(mosi), .miso(miso), - .io_tx(io_tx), .io_rx(io_rx), - .tx_i(tx_i), .tx_q(tx_q), - .rx_i(rx_i), .rx_q(rx_q), - .pps_in(PPS_IN) ); - - // ///////////////////////////////////////////////////////////////////////// - // Interface between GPMC/host - wire [31:0] gpmc_debug; - - gpmc #(.TXFIFOSIZE(13), .RXFIFOSIZE(13)) - gpmc (.arst(async_reset), - .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), - .EM_NOE(EM_NOE), - - .rx_have_data(overo_gpio146), .tx_have_space(overo_gpio144), - .resp_have_data(has_resp), - - .fifo_clk(clk_fpga), .fifo_rst(reset), - .rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy), - .tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy), - .ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy), - .resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy), - - .debug(gpmc_debug)); - - //assign debug = gpmc_debug; - assign debug = core_debug; - -endmodule // E1x0 diff --git a/fpga/usrp2/top/E1x0/Makefile b/fpga/usrp2/top/E1x0/Makefile deleted file mode 100644 index 0ca8ed2dd..000000000 --- a/fpga/usrp2/top/E1x0/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright 2011 Ettus Research LLC -# - -all: E100 E110 - find -name "*.twr" | xargs grep constraint | grep met - -clean: - rm -rf build* - -E100: - make -f Makefile.$@ bin - -E110: - make -f Makefile.$@ bin - -.PHONY: all clean diff --git a/fpga/usrp2/top/E1x0/Makefile.E100 b/fpga/usrp2/top/E1x0/Makefile.E100 deleted file mode 100644 index 92334d987..000000000 --- a/fpga/usrp2/top/E1x0/Makefile.E100 +++ /dev/null @@ -1,106 +0,0 @@ -# -# Copyright 2008-2012 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = E1x0 -BUILD_DIR = $(abspath build$(ISE)-E100) - -# set me in a custom makefile -CUSTOM_SRCS = -CUSTOM_DEFS = - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../gpmc/Makefile.srcs - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd1800a \ -package cs484 \ -speed -4 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -../B100/u1plus_core.v \ -E1x0.v \ -E1x0.ucf \ -timing.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ -$(GPMC_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto \ -"Verilog Macros" "$(CUSTOM_DEFS)" - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Generate Detailed MAP Report" TRUE \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 \ -"Unused IOB Pins" "Pull Up" - -SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/E1x0/Makefile.E110 b/fpga/usrp2/top/E1x0/Makefile.E110 deleted file mode 100644 index e5be8d2fa..000000000 --- a/fpga/usrp2/top/E1x0/Makefile.E110 +++ /dev/null @@ -1,106 +0,0 @@ -# -# Copyright 2008-2012 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = E1x0 -BUILD_DIR = $(abspath build$(ISE)-E110) - -# set me in a custom makefile -CUSTOM_SRCS = -CUSTOM_DEFS = - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../gpmc/Makefile.srcs - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd3400a \ -package cs484 \ -speed -4 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -../B100/u1plus_core.v \ -E1x0.v \ -E1x0.ucf \ -timing.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ -$(GPMC_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto \ -"Verilog Macros" "$(CUSTOM_DEFS)" - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Generate Detailed MAP Report" TRUE \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 \ -"Unused IOB Pins" "Pull Up" - -SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/E1x0/README b/fpga/usrp2/top/E1x0/README deleted file mode 100644 index 14c7a4955..000000000 --- a/fpga/usrp2/top/E1x0/README +++ /dev/null @@ -1,4 +0,0 @@ - -make clean -make sim -./tb_u1e -lxt2 diff --git a/fpga/usrp2/top/E1x0/cmdfile b/fpga/usrp2/top/E1x0/cmdfile deleted file mode 100644 index 291c723b8..000000000 --- a/fpga/usrp2/top/E1x0/cmdfile +++ /dev/null @@ -1,20 +0,0 @@ - -# My stuff --y . --y ../../control_lib --y ../../control_lib/newfifo --y ../../sdr_lib --y ../../timing --y ../../coregen --y ../../gpmc - -# Models --y ../../models --y /opt/Xilinx/10.1/ISE/verilog/src/unisims - -# Open Cores --y ../../opencores/spi/rtl/verilog -+incdir+../../opencores/spi/rtl/verilog --y ../../opencores/i2c/rtl/verilog -+incdir+../../opencores/i2c/rtl/verilog - diff --git a/fpga/usrp2/top/E1x0/core_compile b/fpga/usrp2/top/E1x0/core_compile deleted file mode 100755 index ab992f29d..000000000 --- a/fpga/usrp2/top/E1x0/core_compile +++ /dev/null @@ -1,3 +0,0 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../B100 -y $XILINX/verilog/src/unisims E1x0.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models - - diff --git a/fpga/usrp2/top/E1x0/make.sim b/fpga/usrp2/top/E1x0/make.sim deleted file mode 100644 index 1c163884c..000000000 --- a/fpga/usrp2/top/E1x0/make.sim +++ /dev/null @@ -1,7 +0,0 @@ -all: sim - -sim: - iverilog -Wimplicit -Wportbind -c cmdfile tb_u1e.v -o tb_u1e - -clean: - rm -f tb_u1e *.vcd *.lxt a.out diff --git a/fpga/usrp2/top/E1x0/tb_u1e.v b/fpga/usrp2/top/E1x0/tb_u1e.v deleted file mode 100644 index 188190f04..000000000 --- a/fpga/usrp2/top/E1x0/tb_u1e.v +++ /dev/null @@ -1,58 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -`timescale 1ps / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module tb_u1e(); - - wire [2:0] debug_led; - wire [31:0] debug; - wire [1:0] debug_clk; - - xlnx_glbl glbl (.GSR(),.GTS()); - - initial begin - $dumpfile("tb_u1e.lxt"); - $dumpvars(0,tb_u1e); - end - - // GPMC - wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE; - wire [15:0] EM_D; - wire [10:1] EM_A; - wire [1:0] EM_NBE; - - reg clk_fpga = 0, rst_fpga = 1; - always #15625 clk_fpga = ~clk_fpga; - - initial #200000 - @(posedge clk_fpga) - rst_fpga <= 0; - - u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(rst_fpga), - .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), - .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), - .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); - - gpmc_model_async gpmc_model_async - (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), - .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); - -endmodule // tb_u1e diff --git a/fpga/usrp2/top/E1x0/timing.ucf b/fpga/usrp2/top/E1x0/timing.ucf deleted file mode 100644 index 1483c2a05..000000000 --- a/fpga/usrp2/top/E1x0/timing.ucf +++ /dev/null @@ -1,23 +0,0 @@ - -NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; -TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; - -NET "EM_CLK" TNM_NET = "EM_CLK"; -TIMESPEC "TS_em_clk" = PERIOD "EM_CLK" 18867 ps HIGH 50 %; - -#constrain GPMC IO -INST "EM_D<*>" TNM = gpmc_net_out; -INST "EM_D<*>" TNM = gpmc_net; -INST "EM_A<*>" TNM = gpmc_net; -INST "EM_NCS4" TNM = gpmc_net; -INST "EM_NCS6" TNM = gpmc_net; -INST "EM_NWE" TNM = gpmc_net; -INST "EM_NOE" TNM = gpmc_net; - -TIMEGRP "gpmc_net" OFFSET = IN 6 ns VALID 10 ns BEFORE "EM_CLK" FALLING; -#TIMEGRP "gpmc_net_out" OFFSET = OUT 13 ns AFTER "EM_CLK" RISING; //2 clock cyc per read - -#constrain interrupt lines -NET "overo_gpio144" MAXDELAY = 5.5 ns; #have space -NET "overo_gpio146" MAXDELAY = 5.5 ns; #have data -NET "overo_gpio147" MAXDELAY = 5.5 ns; #have msg/aux spi miso diff --git a/fpga/usrp2/top/Makefile.common b/fpga/usrp2/top/Makefile.common deleted file mode 100644 index bd999f007..000000000 --- a/fpga/usrp2/top/Makefile.common +++ /dev/null @@ -1,64 +0,0 @@ -# -# Copyright 2008-2011 Ettus Research LLC -# - -################################################## -# Constants -################################################## -ISE_VER = $(shell xtclsh -h | head -n1 | cut -f2 -d" " | cut -f1 -d.) -ifeq ($(ISE_VER),10) - ISE_EXT = ise -else - ISE_EXT = xise -endif -BASE_DIR = $(abspath ..) -ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl -SANITY_CHECKER = python $(BASE_DIR)/python/check_inout.py -TIMING_CHECKER = python $(BASE_DIR)/python/check_timing.py -ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).$(ISE_EXT) -BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin -BIT_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit -MCS_FILE = $(BUILD_DIR)/$(TOP_MODULE).mcs -TWR_FILE = $(BUILD_DIR)/$(TOP_MODULE).twr - -################################################## -# Global Targets -################################################## -all: bin - -proj: $(ISE_FILE) - -check: $(ISE_FILE) - $(SANITY_CHECKER) $(TOP_MODULE).v $(TOP_MODULE).ucf - $(ISE_HELPER) "Check Syntax" - -synth: $(ISE_FILE) - $(ISE_HELPER) "Synthesize - XST" - -bin: check $(BIN_FILE) - $(TIMING_CHECKER) $(TWR_FILE) - -mcs: $(MCS_FILE) - -clean: - $(RM) -r $(BUILD_DIR) - -.PHONY: all proj check synth bin mcs clean - -################################################## -# Dependency Targets -################################################## -.SECONDEXPANSION: -$(ISE_FILE): $$(SOURCES) $$(MAKEFILE_LIST) - @echo $@ - $(ISE_HELPER) "" - -$(BIN_FILE): $(ISE_FILE) $$(SOURCES) $$(MAKEFILE_LIST) - @echo $@ - $(ISE_HELPER) "Generate Programming File" 2>&1 | tee $(BUILD_DIR)/build.log - touch $@ - -$(MCS_FILE): $(BIN_FILE) - promgen -w -spi -p mcs -o $(MCS_FILE) -s 4096 -u 0 $(BIT_FILE) - -.EXPORT_ALL_VARIABLES: diff --git a/fpga/usrp2/top/N2x0/.gitignore b/fpga/usrp2/top/N2x0/.gitignore deleted file mode 100644 index 1b2211df0..000000000 --- a/fpga/usrp2/top/N2x0/.gitignore +++ /dev/null @@ -1 +0,0 @@ -build* diff --git a/fpga/usrp2/top/N2x0/Makefile b/fpga/usrp2/top/N2x0/Makefile deleted file mode 100644 index b6a3d9624..000000000 --- a/fpga/usrp2/top/N2x0/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright 2011 Ettus Research LLC -# - -all: N200R3 N210R3 N200R4 N210R4 - find -name "*.twr" | xargs grep constraint | grep met - -clean: - rm -rf build* - -N200R3: - make -f Makefile.$@ bin - -N210R3: - make -f Makefile.$@ bin - -N200R4: - make -f Makefile.$@ bin - -N210R4: - make -f Makefile.$@ bin - -.PHONY: all clean diff --git a/fpga/usrp2/top/N2x0/Makefile.N200R3 b/fpga/usrp2/top/N2x0/Makefile.N200R3 deleted file mode 100644 index 07b955d13..000000000 --- a/fpga/usrp2/top/N2x0/Makefile.N200R3 +++ /dev/null @@ -1,104 +0,0 @@ -# -# Copyright 2008-2012 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u2plus -BUILD_DIR = $(abspath build$(ISE)-N200R3) - -# set me in a custom makefile -CUSTOM_SRCS = -CUSTOM_DEFS = - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../extramfifo/Makefile.srcs - - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd1800a \ -package fg676 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -u2plus_core.v \ -u2plus.v \ -u2plus.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto \ -"Verilog Macros" "$(CUSTOM_DEFS)" - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Generate Detailed MAP Report" TRUE \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/N2x0/Makefile.N200R4 b/fpga/usrp2/top/N2x0/Makefile.N200R4 deleted file mode 100644 index 8b1090308..000000000 --- a/fpga/usrp2/top/N2x0/Makefile.N200R4 +++ /dev/null @@ -1,105 +0,0 @@ -# -# Copyright 2008-2012 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u2plus -BUILD_DIR = $(abspath build$(ISE)-N200R4) - -# set me in a custom makefile -CUSTOM_SRCS = -CUSTOM_DEFS = - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../extramfifo/Makefile.srcs - - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd1800a \ -package fg676 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -capture_ddrlvds.v \ -u2plus_core.v \ -u2plus.v \ -u2plus.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto \ -"Verilog Macros" "LVDS=1 $(CUSTOM_DEFS)" - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Generate Detailed MAP Report" TRUE \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/N2x0/Makefile.N210R3 b/fpga/usrp2/top/N2x0/Makefile.N210R3 deleted file mode 100644 index 411aa20f1..000000000 --- a/fpga/usrp2/top/N2x0/Makefile.N210R3 +++ /dev/null @@ -1,104 +0,0 @@ -# -# Copyright 2008-2012 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u2plus -BUILD_DIR = $(abspath build$(ISE)-N210R3) - -# set me in a custom makefile -CUSTOM_SRCS = -CUSTOM_DEFS = - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../extramfifo/Makefile.srcs - - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd3400a \ -package fg676 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -u2plus_core.v \ -u2plus.v \ -u2plus.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto \ -"Verilog Macros" "$(CUSTOM_DEFS)" - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Generate Detailed MAP Report" TRUE \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/N2x0/Makefile.N210R4 b/fpga/usrp2/top/N2x0/Makefile.N210R4 deleted file mode 100644 index 44ce17b3f..000000000 --- a/fpga/usrp2/top/N2x0/Makefile.N210R4 +++ /dev/null @@ -1,105 +0,0 @@ -# -# Copyright 2008-2012 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u2plus -BUILD_DIR = $(abspath build$(ISE)-N210R4) - -# set me in a custom makefile -CUSTOM_SRCS = -CUSTOM_DEFS = - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../extramfifo/Makefile.srcs - - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd3400a \ -package fg676 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -capture_ddrlvds.v \ -u2plus_core.v \ -u2plus.v \ -u2plus.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto \ -"Verilog Macros" "LVDS=1 $(CUSTOM_DEFS)" - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Generate Detailed MAP Report" TRUE \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/N2x0/bootloader.rmi b/fpga/usrp2/top/N2x0/bootloader.rmi deleted file mode 100644 index cf51f52b4..000000000 --- a/fpga/usrp2/top/N2x0/bootloader.rmi +++ /dev/null @@ -1,512 +0,0 @@ -defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_dbaa0400_3a0b0b80_80e7e80c_82700b0b_0b0b0b0b; -defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_80dbf42d_88080b0b_80088408; -defparam bootram.RAM0.INIT_02=256'h00000000_00000000_04000000_ffff0652_832b2a83_81058205_72830609_71fd0608; -defparam bootram.RAM0.INIT_03=256'h83a70400_0b0b0b0b_7383ffff_2b2b0906_05820583_83060981_83ffff73_71fd0608; -defparam bootram.RAM0.INIT_04=256'h00000000_00000000_53510400_070a8106_73097306_09060906_72057373_72098105; -defparam bootram.RAM0.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722473; -defparam bootram.RAM0.INIT_06=256'h00000000_53510400_81065151_0a31050a_0a720a10_30720a10_71068106_71737109; -defparam bootram.RAM0.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722673; -defparam bootram.RAM0.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM0.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_c4040000_0b0b0b88; -defparam bootram.RAM0.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_0a535104_720a722b; -defparam bootram.RAM0.INIT_0B=256'h00000000_00000000_00000000_00000000_05040000_0b0b88a7_0981050b_72729f06; -defparam bootram.RAM0.INIT_0C=256'h00000000_00000000_04000000_06075351_8106ff05_0974090a_739f062a_72722aff; -defparam bootram.RAM0.INIT_0D=256'h00000000_0c515104_0772fc06_832b0b2b_81058205_73830609_020d0406_71715351; -defparam bootram.RAM0.INIT_0E=256'h00000000_00000000_00000000_51040000_0a810653_81050906_72050970_72098105; -defparam bootram.RAM0.INIT_0F=256'h00000000_00000000_00000000_53510400_0a098106_81050906_72050970_72098105; -defparam bootram.RAM0.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_52040000_71098105; -defparam bootram.RAM0.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_04000000_05055351_72720981; -defparam bootram.RAM0.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_07535104_73730906_72097206; -defparam bootram.RAM0.INIT_13=256'h00000000_00000000_04000000_81ff0652_1010102a_81058305_72830609_71fc0608; -defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88aa0400_060b0b0b_10100508_d4738306_0b0b80e7_71fc0608; -defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_cb2d5050_0b0b80d2_88087575_80088408; -defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_fd2d5050_0b0b80d3_88087575_80088408; -defparam bootram.RAM0.INIT_17=256'h04000000_07515151_05ff0506_73097274_70547106_8106ff05_0509060a_72097081; -defparam bootram.RAM0.INIT_18=256'h51040000_06075151_7405ff05_06730972_05705471_098106ff_0509060a_72097081; -defparam bootram.RAM0.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_05ff0504; -defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_80e7e40c_810b0b0b; -defparam bootram.RAM0.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_04000000_71810552; -defparam bootram.RAM0.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM0.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_04000000_10100552_02840572; -defparam bootram.RAM0.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_020d0400_05715351_717105ff; -defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_d3f13f04_82813f80; -defparam bootram.RAM0.INIT_21=256'hfc060c51_102b0772_83051010_06098105_ff067383_51047381_10101053_10101010; -defparam bootram.RAM0.INIT_22=256'h51535104_72ed3851_0a100a53_71105272_09720605_8106ff05_72728072_51043c04; -defparam bootram.RAM0.INIT_23=256'h800b80e8_b40c82a0_0b0b80e8_8380800b_822ebd38_80e7e808_802ea438_80e7e408; -defparam bootram.RAM0.INIT_24=256'h0b80e8b8_80808280_e8b40cf8_0b0b0b80_808080a4_bc0c04f8_800b80e8_b80c8290; -defparam bootram.RAM0.INIT_25=256'h940b80e8_80c0a880_80e8b40c_8c0b0b0b_80c0a880_e8bc0c04_84800b80_0cf88080; -defparam bootram.RAM0.INIT_26=256'h70085252_80e7f008_5170a738_80e8c033_04ff3d0d_80e8bc0c_80dca40b_b80c0b0b; -defparam bootram.RAM0.INIT_27=256'hc034833d_810b80e8_5270ee38_08700852_2d80e7f0_e7f00c70_38841280_70802e94; -defparam bootram.RAM0.INIT_28=256'h38823d0d_09810685_800b802e_0b0b0b0b_802e8e38_80e8b008_3d0d0b0b_0d040480; -defparam bootram.RAM0.INIT_29=256'h389d3d22_5b7a80c4_0da13d08_0404e63d_3f823d0d_0b0bf5d4_e8b0510b_040b0b80; -defparam bootram.RAM0.INIT_2A=256'h862e8c38_39798380_8e3882fb_8380842e_248b3879_79838085_852eac38_5a798380; -defparam bootram.RAM0.INIT_2B=256'h0c82d439_7a80e8c4_81e4d00c_0c86397a_0b81e2cc_0c8e3981_0b81e18c_82f13981; -defparam bootram.RAM0.INIT_2C=256'h82b53979_842e9f38_38798380_8085248b_a7387983_8380852e_225b4079_800ba03d; -defparam bootram.RAM0.INIT_2D=256'h4288539d_83409a3d_81408339_82408739_3882a439_80872e8c_8b387983_8380862e; -defparam bootram.RAM0.INIT_2E=256'h9d3df405_963d7053_80cbe43f_3d526251_4388539d_f23f983d_615180cb_3d880552; -defparam bootram.RAM0.INIT_2F=256'h3f800808_68458cde_22993d23_08498e1b_fb38881b_3d082780_3f8f0ba3_5241acb8; -defparam bootram.RAM0.INIT_30=256'h9c3de405_08456052_cf3f8008_2e88388c_5b5b7a7a_06657b06_8008087a_5a8ccd3f; -defparam bootram.RAM0.INIT_31=256'hff5b7a44_51a0da3f_9c3de405_81068b38_797b2e09_065a805b_800881ff_51abf93f; -defparam bootram.RAM0.INIT_32=256'h887c26ed_34811c5c_5b79337b_3d7d055b_5c7b1d9e_0b833d5e_e0055480_84559c3d; -defparam bootram.RAM0.INIT_33=256'h621d5b5b_5e5c7b1d_800b883d_615b5f5f_08028405_8bdc3f80_519ff53f_389f3d22; -defparam bootram.RAM0.INIT_34=256'h811c5c88_79337b34_631d5b5b_5e5c7b1d_800b901f_7c26ef38_811c5c88_79337b34; -defparam bootram.RAM0.INIT_35=256'h805c7b1e_7c26ef38_811c5c86_79337b34_7f1d5b5b_5e5c7b1d_800b881f_7c26ef38; -defparam bootram.RAM0.INIT_36=256'h84120859_3d0d686a_3d0d04ee_9af13f9c_7c26ef38_811c5c86_79337b34_611d5b5b; -defparam bootram.RAM0.INIT_37=256'h95e93f80_80dca851_75538c52_802e8c38_2e943875_0856758c_279c3877_5a588379; -defparam bootram.RAM0.INIT_38=256'hff9f1756_8818085d_8c5ba05c_d63fa057_dcf85195_53a45280_268e3878_e15778a3; -defparam bootram.RAM0.INIT_39=256'heb399518_08085e81_8a9a3f80_0480c15c_05567508_2980dee8_81387584_75922682; -defparam bootram.RAM0.INIT_3A=256'h97193357_0852800b_08538c18_33549018_76559618_83388457_7580f22e_33568257; -defparam bootram.RAM0.INIT_3B=256'h3dea0553_33705495_b3398d18_80d35c81_3f80085f_76519791_83388157_5775772e; -defparam bootram.RAM0.INIT_3C=256'h3f80c85c_52568ecc_538c1933_70548e19_398d1833_80c95c94_568dbf3f_8c193352; -defparam bootram.RAM0.INIT_3D=256'h058c1908_2980dfb4_c2387584_75852680_33ff0556_ff399418_b5053480_75028405; -defparam bootram.RAM0.INIT_3E=256'h39768429_2277239b_a2399218_1808770c_5fa93990_ae397622_0476085f_58567508; -defparam bootram.RAM0.INIT_3F=256'h785e80cc_d25cad39_710c5680_05901908_2980e8c4_8e397684_70084056_80e8c405; -defparam bootram.RAM1.INIT_00=256'h81185888_75337734_79055757_7719963d_833d5a58_0554800b_55943ddc_5c8c1808; -defparam bootram.RAM1.INIT_01=256'h57753377_3d790557_58771996_0b833d5a_dc055480_a455943d_a439a05c_7826ed38; -defparam bootram.RAM1.INIT_02=256'hc4525393_705380dd_fe3d0d74_943d0d04_519c8d3f_38838080_887826ed_34811858; -defparam bootram.RAM1.INIT_03=256'h88b33f72_a0527251_a33f8d39_90b83f9d_c43f8151_52a05188_2e9238a0_863f7280; -defparam bootram.RAM1.INIT_04=256'h805192c7_8a5280de_5189a43f_3f80dde4_973fa5de_fa3d0d82_843d0d04_5190a73f; -defparam bootram.RAM1.INIT_05=256'h90fc3f88_3f800851_e23f878e_abe53f87_80e8e00c_be3f820b_dea05192_3f8c5280; -defparam bootram.RAM1.INIT_06=256'h95b83f86_52800851_86f03f73_3f800854_b53f8780_91963f88_3f800851_c13f878c; -defparam bootram.RAM1.INIT_07=256'h83808451_3f8ab252_805195fe_d7528380_95c23f8d_518f873f_85528008_ef3f8380; -defparam bootram.RAM1.INIT_08=256'h875195d6_b2528380_95e03f8a_83808551_3f8ab252_865195ea_b2528380_95f43f8a; -defparam bootram.RAM1.INIT_09=256'h8e3faea0_90d451ac_518ef33f_a7bb3f80_83809251_5195cb3f_52838082_3f80c3cf; -defparam bootram.RAM1.INIT_0A=256'h82fdee2e_22555573_80088e05_80c93876_8008802e_3f800856_05518eea_3f883dfc; -defparam bootram.RAM1.INIT_0B=256'h90e93f94_80decc51_80089a38_80c6f03f_08900551_dec45280_38845380_098106ad; -defparam bootram.RAM1.INIT_0C=256'h8e3f8ce1_8def3fa7_519c863f_39745275_85e03f88_f93f7351_8fda3f86_16705254; -defparam bootram.RAM1.INIT_0D=256'h51868f3f_3f9f5280_963f88e6_87ea3f8c_3f82b73f_c23f92b1_fe3d0d86_3fff9e39; -defparam bootram.RAM1.INIT_0E=256'h885185d1_c83f8852_82ac518b_5185de3f_3f845284_ac518bd5_85eb3f82_9f528051; -defparam bootram.RAM1.INIT_0F=256'h3f80e451_805185b5_82539f52_518bae3f_c43f82ac_52905185_8bbb3f90_3f82ac51; -defparam bootram.RAM1.INIT_10=256'h85b03f9f_9f529e51_8025df38_ff135372_518b923f_a83f80e4_529c5185_8b9f3f9f; -defparam bootram.RAM1.INIT_11=256'h8b2a8106_808c0870_803d0d82_843d0d04_810b800c_81e0840c_8c3f890b_52815185; -defparam bootram.RAM1.INIT_12=256'h57585957_82055a57_30708025_a7053370_7f028c05_3d0d7a7d_3d0d04f9_800c5182; -defparam bootram.RAM1.INIT_13=256'h51538054_30709f2a_388a5573_88557383_832e8838_88055575_38728025_75822e93; -defparam bootram.RAM1.INIT_14=256'h54548054_842b0751_fe057072_05777131_76812cff_802e9738_38725472_8177259e; -defparam bootram.RAM1.INIT_15=256'h51b0b43f_73528118_51b0bc3f_ff065277_c63f7281_527b51b0_81805474_86397353; -defparam bootram.RAM1.INIT_16=256'h527551fe_54bd5378_815580ca_9f053356_fb3d0d02_893d0d04_51b0ac3f_815280da; -defparam bootram.RAM1.INIT_17=256'h81ff0653_bb3f8008_51d63ffe_3f815281_c551b083_0d815280_0d04fe3d_e63f873d; -defparam bootram.RAM1.INIT_18=256'h81705654_787a5757_04fa3d0d_53843d0d_81e0800c_08709007_3881e080_72802ef3; -defparam bootram.RAM1.INIT_19=256'h38805581_81ff2e83_71335271_83388054_5270802e_17703352_279e3872_80537276; -defparam bootram.RAM1.INIT_1A=256'h33557481_0d80e8e4_0d04fc3d_800c883d_38815170_70802e83_74740751_1353df39; -defparam bootram.RAM1.INIT_1B=256'h74802e95_81ff0655_9e3f8008_80d051b0_e8538252_865480e8_80e8e434_e138810b; -defparam bootram.RAM1.INIT_1C=256'he8e85180_dfcc5280_38865380_74802e8f_81ff0655_8c3f8008_e8e851ff_38865280; -defparam bootram.RAM1.INIT_1D=256'h845280e8_802e9538_ff065574_3f800881_d051afe3_538c5280_5480e8f0_c0993f84; -defparam bootram.RAM1.INIT_1E=256'hf453b852_845480e8_80e8f00c_80dfd408_802e8938_ff065574_3f800881_f051fed1; -defparam bootram.RAM1.INIT_1F=256'h81ff0655_9c3f8008_e8f451fe_38845280_74802e95_81ff0655_ae3f8008_80d051af; -defparam bootram.RAM1.INIT_20=256'h0881ff06_aef93f80_5280d051_e8f85388_0c845480_0880e8f4_3880dfd8_74802e89; -defparam bootram.RAM1.INIT_21=256'hdc0880e8_893880df_5574802e_0881ff06_fde73f80_80e8f851_95388452_5574802e; -defparam bootram.RAM1.INIT_22=256'h3f80e8f8_0c04fdfa_e8f00b80_fe843f80_0b800c04_3f80e8e8_0d04fe8e_f80c863d; -defparam bootram.RAM1.INIT_23=256'had993f80_5280d051_5475538c_0d775684_0c04fb3d_e8f40b80_fdf03f80_0b800c04; -defparam bootram.RAM1.INIT_24=256'h80e8e434_3d0d810b_3d0d04fe_74800c87_80e8f00c_87387508_5574802e_0881ff06; -defparam bootram.RAM1.INIT_25=256'hfc080607_067180e8_73097375_04803d0d_3f843d0d_e851be8f_cc5280e8_945380df; -defparam bootram.RAM1.INIT_26=256'h077080e9_e9800806_75067180_0d730973_0d04803d_0c51823d_0c81e08c_7080e8fc; -defparam bootram.RAM1.INIT_27=256'h800c843d_81c73f72_53538051_3d0d7470_af3f04fe_3d0d0481_980c5182_800c81e0; -defparam bootram.RAM1.INIT_28=256'h06545472_337081ff_79565674_fb3d0d77_833d0d04_5181b63f_0d8a5280_0d04ff3d; -defparam bootram.RAM1.INIT_29=256'h3d0d7352_3d0d04ff_0b800c87_3fe53980_52558191_ff065376_81157481_802e9038; -defparam bootram.RAM1.INIT_2A=256'h0b800c84_80e73f80_8a527251_53ffbd3f_76537052_fe3d0d74_833d0d04_8051cd3f; -defparam bootram.RAM1.INIT_2B=256'h1234823d_3380e7f4_51028f05_803d0d72_833d0d04_8051dd3f_3d0d7352_3d0d04ff; -defparam bootram.RAM1.INIT_2C=256'hfe3d0d80_833d0d04_720c5351_e0057022_751080df_82908005_0d73a029_0d04ff3d; -defparam bootram.RAM1.INIT_2D=256'h38843d0d_827325e5_3f811353_527251ce_e7f81333_51c63f80_13335272_5380e7f4; -defparam bootram.RAM1.INIT_2E=256'h87388d52_2e098106_33537281_80e7f414_81069538_748a2e09_76785654_04fc3d0d; -defparam bootram.RAM1.INIT_2F=256'h04fe3d0d_0c863d0d_38748c15_72802ef8_84140853_90800554_73a02982_7351de3f; -defparam bootram.RAM1.INIT_30=256'h0d04ff3d_800c843d_12085372_2e853890_ff537080_11085252_90800588_74a02982; -defparam bootram.RAM1.INIT_31=256'h800b81a8_840c5181_882a81a8_a8800c70_81ff0681_e8802270_a8880c80_0d800b81; -defparam bootram.RAM1.INIT_32=256'h81a89008_2e818638_81517180_33555354_88059705_0d767802_0d04fd3d_880c833d; -defparam bootram.RAM1.INIT_33=256'ha8900870_a8900c81_81900b81_81a88c0c_72108107_5170f138_81065151_70862a70; -defparam bootram.RAM1.INIT_34=256'h70802eba_51515151_06708132_872a7081_a8900870_70f13881_06515151_812a7081; -defparam bootram.RAM1.INIT_35=256'h70810651_0870812a_0c81a890_7081a890_8338a051_5171812e_b13880e8_3871802e; -defparam bootram.RAM1.INIT_36=256'h0b81a890_883980c0_cc398151_34ff1252_70810556_08517074_3881a88c_515170f1; -defparam bootram.RAM1.INIT_37=256'h2a708106_90087086_535481a8_97053355_78028805_fd3d0d76_853d0d04_0c70800c; -defparam bootram.RAM1.INIT_38=256'h81a89008_81a8900c_81905170_802e8438_81d05171_81a88c0c_f1387210_51515170; -defparam bootram.RAM1.INIT_39=256'h5170802e_32515151_81067081_70872a70_81a89008_5170f138_81065151_70812a70; -defparam bootram.RAM1.INIT_3A=256'h900c81a8_517081a8_2e833890_d0517181_a88c0c80_38733381_802e80c5_80cf3871; -defparam bootram.RAM1.INIT_3B=256'h51515170_70813251_2a708106_90087087_f13881a8_51515170_2a708106_90087081; -defparam bootram.RAM1.INIT_3C=256'h0c853d0d_80517080_81a8900c_3980c00b_3981518a_5354ffb7_8114ff13_802e8e38; -defparam bootram.RAM1.INIT_3D=256'h8d9f7127_31515186_ac087073_085281b8_3881b8ac_7274259b_75548053_04fd3d0d; -defparam bootram.RAM1.INIT_3E=256'h0b828084_80800cef_81e20b82_8280880c_3d0dff0b_3d0d04ff_53e23985_f1388113; -defparam bootram.RAM1.INIT_3F=256'h38833d0d_708025f1_0cff1151_70840554_51a0f172_f3a85287_808c0c80_0cff0b82; -defparam bootram.RAM2.INIT_00=256'h74760652_f3a85555_53810b80_58515280_8c087106_70098280_82808808_04fb3d0d; -defparam bootram.RAM2.INIT_01=256'h877325dc_10575553_13841576_0c8f3981_7482808c_0852712d_38725173_71802e8f; -defparam bootram.RAM2.INIT_02=256'h2b700982_0c518172_a8057571_842980f3_269f3871_73527187_04ff3d0d_38873d0d; -defparam bootram.RAM2.INIT_03=256'h81e0c40c_22747008_0d029205_0404ff3d_52833d0d_880c5351_72068280_80880870; -defparam bootram.RAM2.INIT_04=256'h802ef338_06515170_a0087084_cc0c81b8_810b81e0_04803d0d_0c833d0d_5281e0c8; -defparam bootram.RAM2.INIT_05=256'h54527280_08708106_0d81b8a0_0c04fe3d_7181e0c0_0d04de3f_cc0c823d_820b81e0; -defparam bootram.RAM2.INIT_06=256'h5271802e_70810651_3971812a_8080529a_0c535381_71902a71_b8a00875_2e933881; -defparam bootram.RAM2.INIT_07=256'h7080c006_81b8a008_04803d0d_0c843d0d_72527180_3fff9e3f_ec51f8d3_8b3880df; -defparam bootram.RAM2.INIT_08=256'h0781e0cc_70902b88_028e0522_04ff3d0d_0c823d0d_80800b80_2ef23881_51517080; -defparam bootram.RAM2.INIT_09=256'h0d755480_0d04fd3d_cc0c833d_840b81e0_802ef338_06515170_a0087090_0c5281b8; -defparam bootram.RAM2.INIT_0A=256'h853d0d04_7327e638_81135385_52a6ff3f_14703352_f7a53f72_8638ba51_5372802e; -defparam bootram.RAM2.INIT_0B=256'h3d0d04f6_80ed3f87_80dff051_70335356_81113354_82113355_83113356_fb3d0d77; -defparam bootram.RAM2.INIT_0C=256'h3875802e_7680258f_5d5b5957_2a515b5f_7030709f_05bb0533_61630290_3d0d7c7e; -defparam bootram.RAM2.INIT_0D=256'h3f800851_7651aec5_80537752_79557854_77269438_76305777_ad51782d_8a387952; -defparam bootram.RAM2.INIT_0E=256'h8b053351_803d0d02_8c3d0d04_3351782d_80dffc05_dd3f8008_527651ae_ffbd3f77; -defparam bootram.RAM2.INIT_0F=256'h06575775_337081ff_5c5a5878_5208a3d8_70708405_3d0d8c3d_3d0d04f7_f68d3f82; -defparam bootram.RAM2.INIT_10=256'h2e80fb38_597580f0_19703357_80db3881_2e098106_065675a5_387681ff_802e81d1; -defparam bootram.RAM2.INIT_11=256'h80e42e80_81953975_2e819e38_8a387580_7580e324_e32eb938_a0387580_7580f024; -defparam bootram.RAM2.INIT_12=256'h80f82eba_80f53975_2e80db38_387580f3_80f5248b_2eac3875_397580f5_c638818b; -defparam bootram.RAM2.INIT_13=256'h59568055_19710852_da397784_51792d80_56805275_12335259_77841983_3880ec39; -defparam bootram.RAM2.INIT_14=256'h19710852_92397784_81538a52_55a3d854_52595680_84197108_53903977_a3d85480; -defparam bootram.RAM2.INIT_15=256'h5675802e_59567633_19710859_9e397784_51fdd03f_53905275_a3d85480_59568055; -defparam bootram.RAM2.INIT_16=256'h048a0b81_0c8b3d0d_39800b80_1959fea3_2dec3981_58335179_76708105_8e388052; -defparam bootram.RAM2.INIT_17=256'h04fc3d0d_38823d0d_515170ef_70810651_8c2a8132_b8b40870_803d0d81_e0d00c04; -defparam bootram.RAM2.INIT_18=256'h0a075272_86387181_5570802e_55555654_07728106_72982b7b_059b0533_797b0288; -defparam bootram.RAM2.INIT_19=256'h7181e0d4_51ffa93f_79712b51_52a07531_71820a07_802e8638_06515170_822a7081; -defparam bootram.RAM2.INIT_1A=256'hfc3d0d76_863d0d04_5170800c_81b88008_38ff953f_73802e89_d80c7351_0c7081e0; -defparam bootram.RAM2.INIT_1B=256'h2a517080_ee397190_15555351_22730581_72101570_74278f38_55805372_787a5455; -defparam bootram.RAM2.INIT_1C=256'h5280e988_0d865375_0d04fd3d_800c863d_52ec3971_72902a05_83ffff06_2e8d3871; -defparam bootram.RAM2.INIT_1D=256'h8812ff12_5180720c_e9985289_ff3d0d80_853d0d04_e9900c54_76700880_51b0983f; -defparam bootram.RAM2.INIT_1E=256'h5472742e_52527022_0b80e994_05225380_3d0d0296_3d0d04fd_25f33883_52527080; -defparam bootram.RAM2.INIT_1F=256'h83ffff06_0d787a71_0d04fa3d_800c853d_38805170_897225ee_88125252_8e388112; -defparam bootram.RAM2.INIT_20=256'h55555573_0b80e994_0880e998_0cad3980_80088405_2e893876_3f800880_535856c7; -defparam bootram.RAM2.INIT_21=256'h84140c88_75732376_389dad3f_897525eb_88145455_8f388115_5271802e_08881555; -defparam bootram.RAM2.INIT_22=256'h913ddc05_3d880552_3f735392_5254aee7_923dd605_54933d53_3d0d8670_3d0d04f1; -defparam bootram.RAM2.INIT_23=256'h8c3d2381_0523800b_028405a6_8b3d2380_818a800b_05a20523_90800284_51aed83f; -defparam bootram.RAM2.INIT_24=256'h8a52913d_665e8053_0523685d_028405ae_8d3d2380_80c0910b_05aa0523_80800284; -defparam bootram.RAM2.INIT_25=256'h23800b91_8405ba05_963d2202_22903d23_0523983d_028405ae_b73f8008_e40551fd; -defparam bootram.RAM2.INIT_26=256'h913d0d04_519fb03f_81e68405_6980c029_3dd40552_23ac5391_8405be05_3d238002; -defparam bootram.RAM2.INIT_27=256'h529a3df8_5380e988_adc53f86_3df20551_9b3d529a_3d238653_5b800b97_e83d0d80; -defparam bootram.RAM2.INIT_28=256'h9b3dc411_585a800b_80088008_23f7e23f_0580e205_05220284_3f0280f2_0551adb7; -defparam bootram.RAM2.INIT_29=256'h8305fc06_5fa33d08_5ea13d08_5c905d6e_08465984_0845a33d_6e44a13d_43f00543; -defparam bootram.RAM2.INIT_2A=256'h0c750854_84387376_55737527_3151565a_31908071_701a787c_84587508_408c3d56; -defparam bootram.RAM2.INIT_2B=256'he63f7508_e09851ef_2e883880_06547380_94160883_54738c38_38738306_73802e9a; -defparam bootram.RAM2.INIT_2C=256'hbf268438_ffac3878_57778025_17ff1959_84055708_823f7570_5276519e_53941608; -defparam bootram.RAM2.INIT_2D=256'h7f1f9405_0b943d23_40818a80_0d6b6e40_0d04ea3d_e83f9a3d_822a51f6_80c05978; -defparam bootram.RAM2.INIT_2E=256'h075a7996_6980c080_80ce0523_80028405_3d238180_23800b95_0580ca05_5a790284; -defparam bootram.RAM2.INIT_2F=256'h3f800809_525cfae0_52933d70_4780538a_90084668_052380e9_840580d2_3d238002; -defparam bootram.RAM2.INIT_30=256'h79923880_81ff065a_873f8008_535c5e8c_53983d70_23913d70_0580d205_5a790284; -defparam bootram.RAM2.INIT_31=256'h7b549080_575d9455_5960586b_027f5a6d_d53fa939_f6b63fed_c23f7a51_e0c451f7; -defparam bootram.RAM2.INIT_32=256'hf73d0d7f_983d0d04_38fd893f_867c26ef_34811c5c_5b79337b_1d7c1f5b_53805c7b; -defparam bootram.RAM2.INIT_33=256'ha6052377_80028405_768b3d23_23881857_8405a205_8d3d2202_228a3d23_5802ae05; -defparam bootram.RAM2.INIT_34=256'h23908002_810b8e3d_04ee3d0d_3f8b3d0d_7d51fe9e_05539152_548b3df8_567e5588; -defparam bootram.RAM2.INIT_35=256'h53800852_eb8c3f86_05b60523_34810284_8405b505_3d348402_23860b8f_8405b205; -defparam bootram.RAM2.INIT_36=256'h943df605_86538052_51a9e43f_943df205_53800852_eb863f84_51a9f43f_943dec05; -defparam bootram.RAM2.INIT_37=256'h53805b7a_05549086_55943de4_5780569c_59805880_5a025c80_64700844_51aaf13f; -defparam bootram.RAM2.INIT_38=256'h0b8e3d23_ee3d0d81_943d0d04_38fbcd3f_867b26ef_34811b5b_901b337a_1c5a80e0; -defparam bootram.RAM2.INIT_39=256'h893f8653_b60523ea_81028405_05b50534_34840284_860b8f3d_05b20523_90800284; -defparam bootram.RAM2.INIT_3A=256'h53805294_a8e13f86_3df20551_80085294_833f8453_a8f13fea_3dec0551_80085294; -defparam bootram.RAM2.INIT_3B=256'he4055490_9c55943d_80578056_80598058_0843025c_e73f8008_a9ee3fe9_3df60551; -defparam bootram.RAM2.INIT_3C=256'h04d83d0d_3f943d0d_ef38fac8_5b867b26_7a34811b_e0901b33_7a1c5a80_8653805b; -defparam bootram.RAM2.INIT_3D=256'h5c799b26_29f2055b_ad3d0884_cc38901d_09810682_7e90862e_1122405d_ab3d088e; -defparam bootram.RAM2.INIT_3E=256'h225a7990_9138821c_09810687_5a79812e_9d397b22_f49d3f87_80e0f451_8d387952; -defparam bootram.RAM2.INIT_3F=256'h2e098106_225a7982_f538861c_09810686_798c842e_841c225a_06878338_802e0981; -defparam bootram.RAM3.INIT_00=256'h79527a51_51a7a03f_981d5279_3d5a8653_a7ad3fa8_1d527a51_5b84539e_a238943d; -defparam bootram.RAM3.INIT_01=256'h5b888c3f_a81d7052_4088943f_9e1d7052_0686bb38_812e0981_1c225a79_87953f86; -defparam bootram.RAM3.INIT_02=256'h5a865380_9138a83d_5e800886_f63f8008_a40551a5_52aa3dff_5380e990_80084384; -defparam bootram.RAM3.INIT_03=256'h34851c33_1c33a33d_82052384_02840581_23821c22_7b22a23d_51a6d43f_e9885279; -defparam bootram.RAM3.INIT_04=256'h70547b53_a6a13f84_3de40551_537952aa_86052386_02840581_85053482_02840581; -defparam bootram.RAM3.INIT_05=256'haa3df405_79537f52_51a6843f_981d527a_055b8653_3f028192_525aa693_ab3dea05; -defparam bootram.RAM3.INIT_06=256'haa3ddc05_575d9c55_597e587e_027e5a7e_51a5ec3f_537a527f_9f3d4086_51a5f83f; -defparam bootram.RAM3.INIT_07=256'h397e9080_e73f84ee_26ef38f7_1c5c867c_337b3481_1d5b5b79_5c7b1d60_547e537d; -defparam bootram.RAM3.INIT_08=256'h2a708f06_d1387988_09810684_5b60842e_8c2a435b_1d702270_84e43890_2e098106; -defparam bootram.RAM3.INIT_09=256'he0905282_5e865380_84b4387e_ff065f7e_1b2280ff_84c03886_2e098106_515a7985; -defparam bootram.RAM3.INIT_0A=256'h08833881_a3ed3f80_70535b5c_80e99054_901c6255_38815e7e_3f800883_1d51a483; -defparam bootram.RAM3.INIT_0B=256'h5d407f81_22ec1140_1b33821c_84c53f89_529c1d51_8138881d_7b802e84_5c7d8738; -defparam bootram.RAM3.INIT_0C=256'h7a2e8f38_5d42407d_8411225d_7a08a41f_388c1b08_810683de_7f912e09_2e81bb38; -defparam bootram.RAM3.INIT_0D=256'h08428008_f4913f80_22535d5d_e41d821d_bd39ac1d_f0bd3f83_80e19451_79537d52; -defparam bootram.RAM3.INIT_0E=256'h3d408853_a3e13f9d_7d527951_5f5a8853_9b3d9a3d_3d237f4a_387a229a_802e83a6; -defparam bootram.RAM3.INIT_0F=256'h88537952_51a3c03f_b4055279_53aa3dff_23604888_1b22983d_a3d53f82_79527f51; -defparam bootram.RAM3.INIT_10=256'h7c26ef38_811c5c88_79337b34_7c1f5b5b_5e5c7b1d_557e843d_3f7b567c_7d51a3b7; -defparam bootram.RAM3.INIT_11=256'had398c1b_5a792d82_61840508_7b26ef38_811b5b88_84051c34_5a793302_805b7f1b; -defparam bootram.RAM3.INIT_12=256'h2e098106_335a7983_9539811a_81bb3882_387d882e_7d832e8a_33405b42_08a41e70; -defparam bootram.RAM3.INIT_13=256'h3f800841_2251f2cf_81f4387c_2e098106_5e5c7991_8912335c_1d80c01e_81a238ac; -defparam bootram.RAM3.INIT_14=256'h7d51a29b_88537a52_9c3d5c5e_794c993d_229c3d23_1c085a7c_80fe388c_8008802e; -defparam bootram.RAM3.INIT_15=256'h3dcc0552_4e8853aa_9e3d2379_5a821d22_3f901c08_7f51a28f_88537d52_3f973d40; -defparam bootram.RAM3.INIT_16=256'h5b79337b_1d7c1f5b_3d5e5c7b_7e557e84_ee3f7e56_527d51a1_3f88537a_7a51a1f7; -defparam bootram.RAM3.INIT_17=256'h38608405_887b26ef_34811b5b_0284051c_1b5a7933_38805b7f_887c26ef_34811c5c; -defparam bootram.RAM3.INIT_18=256'hd105347e_02840580_963d347e_1d5d5d7e_39ac1de4_e63f80de_80e951e3_085a792d; -defparam bootram.RAM3.INIT_19=256'h3d70525b_53605295_d605237e_02840580_23861a22_1a22973d_d2052384_02840580; -defparam bootram.RAM3.INIT_1A=256'h567c557d_d205237b_02840580_08095a79_f08e3f80_2a527c51_08537b81_f09a3f80; -defparam bootram.RAM3.INIT_1B=256'h3d0d800b_e80c04fc_800b80e9_80e9e40c_0d04800b_c53faa3d_526151f4_547a537f; -defparam bootram.RAM3.INIT_1C=256'h2e098106_53517075_71088c13_ec545651_700880e9_27a43876_55537274_80e9e408; -defparam bootram.RAM3.INIT_1D=256'h71535755_3d0d7779_3d0d04fb_70800c86_e738ff51_53737326_8b398113_85387251; -defparam bootram.RAM3.INIT_1E=256'he9e80881_0c8e3980_1480e9e4_26893881_08547387_3880e9e4_088025ba_ffb93f80; -defparam bootram.RAM3.INIT_1F=256'he9f01451_53755280_0c515486_80e9ec12_822b7608_73101470_e9e80c54_11870680; -defparam bootram.RAM3.INIT_20=256'hfd3d0d75_873d0d04_519fa43f_80e9f005_52738429_54865375_10800805_94398008; -defparam bootram.RAM3.INIT_21=256'h5276519e_80e9f005_53738429_08055486_80081080_08249938_80547380_51fed83f; -defparam bootram.RAM3.INIT_22=256'h14337088_902b0782_71982b71_33811233_3d0d7570_3d0d04fd_73800c85_fa3f8154; -defparam bootram.RAM3.INIT_23=256'h22565957_7f80eacc_f93d0d7d_853d0d04_54565452_800c5253_16337107_2b720783; -defparam bootram.RAM3.INIT_24=256'h902980ea_90291470_80d33873_54738326_72315256_8b3d2270_83ffff06_76a83873; -defparam bootram.RAM3.INIT_25=256'h38749029_748326ad_31575754_3d227072_ffff068d_c0397383_76742380_d0055154; -defparam bootram.RAM3.INIT_26=256'h33535474_38751770_75782791_ea3f8056_d005519d_902980ea_8a3d5273_15548853; -defparam bootram.RAM3.INIT_27=256'hd0545480_800b80ea_80eacc23_029a0522_04fc3d0d_39893d0d_811656ec_51e1de3f; -defparam bootram.RAM3.INIT_28=256'h14829014_eddc3f81_22740551_5280eacc_140cb8f4_800b828c_8288140c_7323800b; -defparam bootram.RAM3.INIT_29=256'h06515675_81327081_5c847c2c_80ead05a_3d0d800b_3d0d04f4_27d93886_54548374; -defparam bootram.RAM3.INIT_2A=256'h08ff2e80_e1a33f80_055b7b51_38781a88_ff2680d6_5b5d7981_82881a08_81be3875; -defparam bootram.RAM3.INIT_2B=256'h58587680_53515951_71802507_30728025_728d3270_8a327030_81ff0670_c5388008; -defparam bootram.RAM3.INIT_2C=256'h811a5a81_828c1a0c_1a0c800b_81058288_82881908_81055d34_5d777b70_2e833881; -defparam bootram.RAM3.INIT_2D=256'h568b7627_828c1b0c_19088111_9138828c_80d2387c_1908802e_b1388288_ff7a27ff; -defparam bootram.RAM3.INIT_2E=256'h57577533_771a781a_833d5b58_1954800b_19085588_ab388288_5675802e_bf387822; -defparam bootram.RAM3.INIT_2F=256'h828c1a0c_1a0c800b_800b8288_51f0e93f_cc227c05_ef3880ea_58887826_77348118; -defparam bootram.RAM3.INIT_30=256'h685194ba_5780c052_883d7054_04ea3d0d_388e3d0d_7c27fea9_1a5a5c83_811c8290; -defparam bootram.RAM3.INIT_31=256'h94387416_2e098106_387381aa_81ff2e9d_33515473_55741770_059d0557_3f800284; -defparam bootram.RAM3.INIT_32=256'h800c983d_38805473_be7527d1_39811555_3881548b_09810685_7381992e_70335154; -defparam bootram.RAM3.INIT_33=256'hca3f8008_52735199_5380e1b8_3f805584_795193ea_54548452_0d863d70_0d04f93d; -defparam bootram.RAM3.INIT_34=256'h3f8ac23f_3d0d8dd7_940c04fc_810b81e0_893d0d04_5574800c_06833881_752e0981; -defparam bootram.RAM3.INIT_35=256'he1bc5181_73883880_06515154_8d2a7081_b8b40870_89c13f81_06558051_800881ff; -defparam bootram.RAM3.INIT_36=256'h51dd843f_3880e2a0_08802e9a_febf3f80_b0800a51_51dd983f_3880e1f4_833974b5; -defparam bootram.RAM3.INIT_37=256'h51fee33f_3998800a_d85180cc_b53f80e2_800a5184_e1b73fb0_3f82ac51_81518987; -defparam bootram.RAM3.INIT_38=256'h80e3d051_5192bf3f_5298800a_5380ffff_3f838080_a451dcd7_bb3880e3_8008802e; -defparam bootram.RAM3.INIT_39=256'he93f8839_3f805183_ac51e0e9_dcb13f82_80e3f451_3ffee53f_ac51e0f9_dcc13f82; -defparam bootram.RAM3.INIT_3A=256'he5893fa0_e4fc5254_75705380_04fd3d0d_80f3900c_3d0d0471_dc9d3f86_80e4b051; -defparam bootram.RAM3.INIT_3B=256'h528051da_fe3d0da0_853d0d04_7351722d_802e8538_90085372_cc3f80f3_52a051da; -defparam bootram.RAM3.INIT_3C=256'hff0b8008_51898d3f_fc3d0d9a_843d0d04_8051722d_802e8538_90085372_b03f80f3; -defparam bootram.RAM3.INIT_3D=256'h7182802e_5580e454_86800653_820b8008_2e80ec38_81557180_06515354_862a7081; -defparam bootram.RAM3.INIT_3E=256'h845188c8_8338ff54_7184802e_3987e854_2e8e388a_8a547180_80248a38_9b387182; -defparam bootram.RAM3.INIT_3F=256'h7080f39c_e5f41133_06720780_8a2c7083_8c068008_3f71882a_855188c0_3f800852; -defparam bootram.RAM4.INIT_00=256'h80f39408_dac93f74_11085252_0680e888_71822b8c_52dab03f_55535154_0c80e5b4; -defparam bootram.RAM4.INIT_01=256'h2e098106_9e397482_38fec13f_098106a3_3874812e_74822ea6_80f3940c_2e983874; -defparam bootram.RAM4.INIT_02=256'h863d0d04_5187cd3f_fdfb3f99_a73f7351_f3980cfe_8e387380_f398082e_96387380; -defparam bootram.RAM4.INIT_03=256'h3f8d5298_995187ac_80f3980c_940cff0b_800b80f3_5187a23f_e13f8008_fd3d0dd7; -defparam bootram.RAM4.INIT_04=256'h908007f4_8f3f8008_3f845187_8451dfb1_3fbf9452_9c5187cd_81ae8052_5187d63f; -defparam bootram.RAM4.INIT_05=256'hcc51e2a7_735280e5_38800853_80082e8d_86fa3f73_b03f8451_54845187_9f067053; -defparam bootram.RAM4.INIT_06=256'h70852a82_02970533_04fd3d0d_3f853d0d_80518789_84800752_e33f8008_3f805186; -defparam bootram.RAM4.INIT_07=256'h71730707_832ba006_10900674_73070773_2a880671_84067281_0771832a_0671872a; -defparam bootram.RAM4.INIT_08=256'h51555255_0c515253_0682c080_077081ff_0778872b_c0067072_76852b80_7081ff06; -defparam bootram.RAM4.INIT_09=256'h983f81aa_81ff51ff_51ff9e3f_075381ff_0681d00a_0d74d00a_0d04fe3d_5552853d; -defparam bootram.RAM4.INIT_0A=256'h5252fef5_7081ff06_3f72882a_e151ff81_ff873f80_8c3fb251_819951ff_51ff923f; -defparam bootram.RAM4.INIT_0B=256'h902a7081_fedb3f72_72982a51_51fee23f_e83f8181_3fb251fe_0651feed_3f7281ff; -defparam bootram.RAM4.INIT_0C=256'ha051feb5_51feba3f_febf3f8e_c43f8051_81a151fe_51feca3f_fecf3fb0_ff065253; -defparam bootram.RAM4.INIT_0D=256'h05538052_54873dfc_fb3d0d82_843d0d04_51fea63f_feab3f80_b03fa051_3f8051fe; -defparam bootram.RAM4.INIT_0E=256'h12085859_d73d0884_d53d0880_b23d0d80_3d0d04ff_22800c87_ce3f863d_80d05183; -defparam bootram.RAM4.INIT_0F=256'h2681b238_16567596_bc39ff9f_dff53f81_80e68451_53829452_26903877_57778293; -defparam bootram.RAM4.INIT_10=256'h0b81e2cc_e18c0c81_5e810b81_3f800808_c15cd4c0_75080480_e6d00556_75842980; -defparam bootram.RAM4.INIT_11=256'hfef63f80_5c80f839_085f80c6_8c9d3f80_3f80085e_8a398c99_e4d00c81_0c800b81; -defparam bootram.RAM4.INIT_12=256'hc55c80d3_89f53f80_80f3c851_8c170852_90170853_5c80e839_065e80d6_0883ffff; -defparam bootram.RAM4.INIT_13=256'h39941753_80c25cb7_c45cbc39_2e863880_06567580_800881ff_518aba3f_3980f3c8; -defparam bootram.RAM4.INIT_14=256'h1708518b_1708528c_80055390_80d03dfe_d75ca439_88dc3f80_8c170851_90170852; -defparam bootram.RAM4.INIT_15=256'h54800b83_3dfdec05_945580d0_39a05c82_fcf83f83_d35c8051_5c8d3980_b93f80d2; -defparam bootram.RAM4.INIT_16=256'he6fe3f80_83808251_7826ec38_81185888_75337734_79055757_1980d23d_3d5a5877; -defparam bootram.RAM4.INIT_17=256'h05ab0533_05330284_3d0d02a7_83973ff9_ce3fff51_e7ac51d4_803d0d80_d03d0d04; -defparam bootram.RAM4.INIT_18=256'h7f7f5a57_3d0d7a7c_3d0d04f8_dfeb3f89_81528051_98547553_57578255_71882b07; -defparam bootram.RAM4.INIT_19=256'h8405a105_05583302_34767081_54738a3d_75811757_7425b738_16565480_575874ff; -defparam bootram.RAM4.INIT_1A=256'h802e8538_d8c73f73_06548a51_800881ff_51d7993f_7781ff06_3dfc0552_3482538a; -defparam bootram.RAM4.INIT_1B=256'h883d3481_38dc5675_de567483_05335580_3d0d02a3_3d0d04fa_73800c8a_c1398154; -defparam bootram.RAM4.INIT_1C=256'h893d3481_02ab0533_3d0d7c57_3d0d04f9_ff893f88_5280d051_055381f7_54883dfc; -defparam bootram.RAM4.INIT_1D=256'h38807725_73802e9e_06705654_800881ff_56d6b93f_05337052_055202a7_53893dfc; -defparam bootram.RAM4.INIT_1E=256'h0c893d0d_81557480_802e8338_70565473_0881ff06_d4fc3f80_7b527551_97387653; -defparam bootram.RAM4.INIT_1F=256'h80de2e09_33565674_800b883d_51ffa03f_f75280d0_fc055381_8154883d_04fa3d0d; -defparam bootram.RAM4.INIT_20=256'h81c0ac0c_800ca60b_eb0b81c0_c0940c80_04990b81_0c883d0d_81567580_81068338; -defparam bootram.RAM4.INIT_21=256'hc0a00c81_51820b81_81c0980c_06708107_882bbe80_803d0d72_c0b00c04_89b00b81; -defparam bootram.RAM4.INIT_22=256'h72882bbe_04803d0d_0c823d0d_c0a80880_70f13881_06515151_812a7081_c0a40870; -defparam bootram.RAM4.INIT_23=256'h70810651_0870812a_0c81c0a4_0b81c0a0_c09c0c84_0c517381_0781c098_80067081; -defparam bootram.RAM4.INIT_24=256'h83065271_71913875_55555757_7c728306_3d0d787a_04ff39fa_38823d0d_515170f1; -defparam bootram.RAM4.INIT_25=256'h822b7711_27943873_55557375_72822a72_5188ca3f_2e863881_06527180_8a387283; -defparam bootram.RAM4.INIT_26=256'h80e7b811_2a708f06_0d747084_0d04fe3d_e939883d_52811454_720c5254_77127008; -defparam bootram.RAM4.INIT_27=256'h82e09008_04803d0d_3f843d0d_5253cffb_e7b81133_728f0680_53d0883f_33545153; -defparam bootram.RAM4.INIT_28=256'h8c800607_80ff067a_93053378_fe3d0d02_823d0d04_5170f138_81065151_70882a70; -defparam bootram.RAM4.INIT_29=256'h82e0900c_e0800c71_f1387682_51515170_2a708106_90087088_535382e0_80c08007; -defparam bootram.RAM4.INIT_2A=256'h882a7081_e0900870_2e963882_72517280_82e0900c_71828007_82e0980c_7581ff06; -defparam bootram.RAM4.INIT_2B=256'h88805588_82e0940c_3d0d810b_3d0d04fc_70800c84_e0800851_70f13882_06515151; -defparam bootram.RAM4.INIT_2C=256'h51fef13f_53815281_90548a80_0d888055_0d04fc3d_873f863d_528051ff_54805380; -defparam bootram.RAM4.INIT_2D=256'h863d0d04_51fed53f_53815280_55885486_3d0d8880_3d0d04fc_06800c86_800881ff; -defparam bootram.RAM4.INIT_2E=256'h70802ef4_81ff0651_eb3f8008_04803d0d_0c823d0d_32810680_3f800881_803d0dca; -defparam bootram.RAM4.INIT_2F=256'h5475fe9b_888055a0_3fffb43f_269b38dd_3f758008_775684e3_04fb3d0d_38823d0d; -defparam bootram.RAM4.INIT_30=256'h08ff1156_0880cb3d_0d80c93d_04ffba3d_3f873d0d_8051fe84_07538152_0a069b0a; -defparam bootram.RAM4.INIT_31=256'hff52883d_82805381_2681a738_3f738008_1754849f_81b43875_7381ff26_57578055; -defparam bootram.RAM4.INIT_32=256'h82e0980c_fd9f3f74_3ffed43f_ea3ffefd_5273518a_80cb3d08_8f3f7553_7052548c; -defparam bootram.RAM4.INIT_33=256'h0b82e090_980c88a0_810b82e0_82e0800c_80c00a07_fec00a06_e0900c76_88800b82; -defparam bootram.RAM4.INIT_34=256'h84157008_8c0c54fe_700882e0_56fe8015_c83d558f_fcef3f80_82e0900c_0c8aa00b; -defparam bootram.RAM4.INIT_35=256'h82e0900c_5488800b_82e0800c_8c157008_840c54fe_700882e0_54fe8815_82e0880c; -defparam bootram.RAM4.INIT_36=256'h81557480_82e0980c_bc38800b_758025ff_90165656_b03fff16_e0900cfc_8a800b82; -defparam bootram.RAM4.INIT_37=256'hcb388157_80082680_3f805773_565682db_7212575a_0d797b7d_0d04f93d_0c80c83d; -defparam bootram.RAM4.INIT_38=256'h76547753_75278338_75555776_82807431_802ea238_ff065473_c3387581_74802e80; -defparam bootram.RAM4.INIT_39=256'he1388280_82807527_8e387454_5674802e_76315759_16741976_fdeb3f73_73527551; -defparam bootram.RAM4.INIT_3A=256'h38731354_73802e8d_7a565455_3d0d7678_3d0d04fc_76800c89_8c3f8157_54dc39fd; -defparam bootram.RAM4.INIT_3B=256'h08307074_81cb3f80_750ca639_84160c80_160c800b_38800b88_08742790_81ed3f80; -defparam bootram.RAM4.INIT_3C=256'h3f863d0d_7151fcc9_7188160c_0684160c_72760c74_3f800830_515281bd_06ff1656; -defparam bootram.RAM4.INIT_3D=256'h15082e94_88140884_9f388153_5271802e_ff067054_3f800881_7554fc98_04fd3d0d; -defparam bootram.RAM4.INIT_3E=256'h3d0d8880_3d0d04fc_72800c85_943f8053_160c51fc_08057088_88140880_3881823f; -defparam bootram.RAM4.INIT_3F=256'h0d80f3a0_0d04ff3d_800c863d_fe800a06_a33f8008_528151fa_f90a5381_55a05481; -defparam bootram.RAM5.INIT_00=256'h387180f3_09810693_5170a02e_ff065451_06800881_2a7081ff_3f800888_08a038d7; -defparam bootram.RAM5.INIT_01=256'h0880e882_04c03f80_0c833d0d_b33f7180_278438f5_52528271_a008ea11_a00c80f3; -defparam bootram.RAM5.INIT_02=256'h0d7d56f9_0c04f63d_80082b80_a93f810b_800c04ff_0b80082b_04f33f81_0533800c; -defparam bootram.RAM5.INIT_03=256'h810b82e0_82e0800c_0c7c882b_0b82e084_e0900c8b_88800b82_82e0980c_983f800b; -defparam bootram.RAM5.INIT_04=256'h3888800b_762780d3_55805473_f8e73f7e_82e0900c_0c8aa80b_0b82e090_980c88a8; -defparam bootram.RAM5.INIT_05=256'h5a82e080_82e08408_e0880859_8c085882_cc3f82e0_e0900cf8_8a800b82_82e0900c; -defparam bootram.RAM5.INIT_06=256'h70337570_38711751_71732791_70538052_73278338_57905370_76753152_085b883d; -defparam bootram.RAM5.INIT_07=256'h7251f789_04803d0d_0c8c3d0d_0b82e098_ffa93980_39721454_811252ec_81055734; -defparam bootram.RAM5.INIT_08=256'h70800c54_de3f8008_05085182_528c0888_088c0508_0d80538c_8c0cfd3d_3f8c0802; -defparam bootram.RAM5.INIT_09=256'h82b93f80_88050851_08528c08_8c088c05_3d0d8153_028c0cfd_0c048c08_853d0d8c; -defparam bootram.RAM5.INIT_0A=256'h88050880_050c8c08_0b8c08fc_f93d0d80_08028c0c_8c0c048c_54853d0d_0870800c; -defparam bootram.RAM5.INIT_0B=256'h810b8c08_05088838_0c8c08fc_8c08f405_050c800b_308c0888_08880508_25ab388c; -defparam bootram.RAM5.INIT_0C=256'h8c088c05_8c050830_ab388c08_05088025_0c8c088c_8c08fc05_08f40508_f4050c8c; -defparam bootram.RAM5.INIT_0D=256'h08fc050c_f005088c_050c8c08_0b8c08f0_08883881_8c08fc05_08f0050c_0c800b8c; -defparam bootram.RAM5.INIT_0E=256'hfc050880_0c548c08_8c08f805_3f800870_085181a7_8c088805_8c050852_80538c08; -defparam bootram.RAM5.INIT_0F=256'h048c0802_3d0d8c0c_800c5489_f8050870_050c8c08_308c08f8_08f80508_2e8c388c; -defparam bootram.RAM5.INIT_10=256'h0888050c_0508308c_388c0888_08802593_8c088805_08fc050c_0d800b8c_8c0cfb3d; -defparam bootram.RAM5.INIT_11=256'h538c088c_8c050c81_08308c08_8c088c05_80258c38_088c0508_fc050c8c_810b8c08; -defparam bootram.RAM5.INIT_12=256'h388c08f8_08802e8c_8c08fc05_f8050c54_08708c08_51ad3f80_08880508_0508528c; -defparam bootram.RAM5.INIT_13=256'hfd3d0d81_08028c0c_8c0c048c_54873d0d_0870800c_8c08f805_08f8050c_0508308c; -defparam bootram.RAM5.INIT_14=256'hfc050880_ac388c08_88050827_05088c08_0c8c088c_8c08f805_050c800b_0b8c08fc; -defparam bootram.RAM5.INIT_15=256'h08108c08_8c08fc05_088c050c_0508108c_388c088c_05082499_0b8c088c_2ea33880; -defparam bootram.RAM5.INIT_16=256'h8c088805_0826a138_8c088805_088c0508_80c9388c_0508802e_398c08fc_fc050cc9; -defparam bootram.RAM5.INIT_17=256'h8c08fc05_08f8050c_0508078c_088c08fc_8c08f805_0888050c_0508318c_088c088c; -defparam bootram.RAM5.INIT_18=256'h802e8f38_08900508_ffaf398c_088c050c_08812a8c_8c088c05_08fc050c_08812a8c; -defparam bootram.RAM5.INIT_19=256'hf4050880_0c518c08_8c08f405_f8050870_8d398c08_f4050c51_08708c08_8c088805; -defparam bootram.RAM5.INIT_1A=256'h802eb038_83065170_38747407_8372278c_79565652_3d0d7877_8c0c04fc_0c853d0d; -defparam bootram.RAM5.INIT_1B=256'h54555571_8115ff14_bd388115_2e098106_52537271_74337433_ff2ea038_ff125271; -defparam bootram.RAM5.INIT_1C=256'h38841184_0981068f_0873082e_74545170_3d0d0474_0b800c86_06e23880_ff2e0981; -defparam bootram.RAM5.INIT_1D=256'h3d0d7670_3d0d04fc_31800c86_af397271_735555ff_26e93870_54517183_14fc1454; -defparam bootram.RAM5.INIT_1E=256'h98387270_5271ff2e_a738ff12_5170802e_75078306_278c3872_55558f72_797b5555; -defparam bootram.RAM5.INIT_1F=256'h74517270_863d0d04_3874800c_098106ea_5271ff2e_5634ff12_74708105_81055433; -defparam bootram.RAM5.INIT_20=256'h71708405_84055408_530c7270_71708405_84055408_530c7270_71708405_84055408; -defparam bootram.RAM5.INIT_21=256'h70840554_27953872_c9388372_52718f26_530cf012_71708405_84055408_530c7270; -defparam bootram.RAM5.INIT_22=256'h059f0533_7971028c_fc3d0d76_54ff8339_26ed3870_12527183_05530cfc_08717084; -defparam bootram.RAM5.INIT_23=256'h70810555_93387373_5271ff2e_a238ff12_5170802e_38748306_8372278a_57555355; -defparam bootram.RAM5.INIT_24=256'h2b075154_07707190_74882b75_3d0d0474_74800c86_8106ef38_71ff2e09_34ff1252; -defparam bootram.RAM5.INIT_25=256'h71708405_05530c72_72717084_8405530c_0c727170_70840553_a5387271_518f7227; -defparam bootram.RAM5.INIT_26=256'hf2387053_52718326_530cfc12_71708405_27903872_dd388372_52718f26_530cf012; -defparam bootram.RAM5.INIT_27=256'h2e80d438_06517080_71740783_2e80d938_55527280_7c705455_3d0d787a_ff9039fa; -defparam bootram.RAM5.INIT_28=256'h7081ff06_2e818738_a9387280_2e098106_56517471_71337433_ff2eb138_ff135372; -defparam bootram.RAM5.INIT_29=256'h56517081_71337433_8106d138_72ff2e09_15555552_128115ff_80fc3881_5170802e; -defparam bootram.RAM5.INIT_2A=256'h71087408_73278838_74575583_3d0d0471_70800c88_31515252_ff067171_ff067581; -defparam bootram.RAM5.INIT_2B=256'h70f88482_fdff1206_7009f7fb_b1387408_5372802e_9739fc13_765552ff_2e883874; -defparam bootram.RAM5.INIT_2C=256'h765552fe_2ed03874_74087608_7327d038_17575583_38841584_5151709a_81800651; -defparam bootram.RAM5.INIT_2D=256'hf3a40cff_9e387380_5472812e_e7e80854_0d800b80_0d04fd3d_800c883d_df39800b; -defparam bootram.RAM5.INIT_2E=256'hffad813f_80f3a40c_f6a33f72_3f800851_51ffb5b8_e89c5281_acba3f80_ad9e3fff; -defparam bootram.RAM5.INIT_2F=256'ha40bfc05_3d0d80e8_00ff39ff_51f6863f_9b3f8008_8151ffb5_80e89c52_ffac9d3f; -defparam bootram.RAM5.INIT_30=256'h0404ffad_38833d0d_098106f1_5270ff2e_12700852_38702dfc_70ff2e91_70085252; -defparam bootram.RAM5.INIT_31=256'h636b6574_6c207061_6e74726f_6e20636f_6f722069_21457272_00000040_ac3f0400; -defparam bootram.RAM5.INIT_32=256'h6c697479_74696269_6f6d7061_65642063_70656374_3a204578_646c6572_2068616e; -defparam bootram.RAM5.INIT_33=256'h6f722069_21457272_25640a00_676f7420_62757420_25642c20_62657220_206e756d; -defparam bootram.RAM5.INIT_34=256'h70656374_3a204578_646c6572_2068616e_636b6574_6c207061_6e74726f_6e20636f; -defparam bootram.RAM5.INIT_35=256'h74202564_7420676f_2c206275_68202564_656e6774_6164206c_61796c6f_65642070; -defparam bootram.RAM5.INIT_36=256'h203d2025_70656564_643a2073_616e6765_6b206368_206c696e_0a657468_0a000000; -defparam bootram.RAM5.INIT_37=256'h720a0000_6f616465_6f6f746c_44502062_31302055_50204e32_0a555352_640a0000; -defparam bootram.RAM5.INIT_38=256'h640a0000_723a2025_756d6265_7479206e_62696c69_70617469_20636f6d_46504741; -defparam bootram.RAM5.INIT_39=256'h723a2025_756d6265_7479206e_62696c69_70617469_20636f6d_77617265_4669726d; -defparam bootram.RAM5.INIT_3A=256'h7061636b_65727920_65636f76_69702072_476f7420_00000000_61646472_640a0000; -defparam bootram.RAM5.INIT_3B=256'h00000826_00000826_00000826_00000826_00000826_00000731_00000000_65743a20; -defparam bootram.RAM5.INIT_3C=256'h00000826_00000826_000007fc_00000826_00000826_00000776_0000078d_00000826; -defparam bootram.RAM5.INIT_3D=256'h000007cf_000007ca_000007c5_0000073e_000007aa_00000826_00000826_00000826; -defparam bootram.RAM5.INIT_3E=256'hffffff00_c0a80a01_c0a80a02_3fff0000_0050c285_000007ea_000007dd_000007d6; -defparam bootram.RAM5.INIT_3F=256'h30313233_2e256400_642e2564_25642e25_45000000_01b200d9_05160364_14580a2c; -defparam bootram.RAM6.INIT_00=256'h5f706b74_73656e64_ffff0000_ffffffff_00000000_43444546_38394142_34353637; -defparam bootram.RAM6.INIT_01=256'h72206275_6e642f6f_656e2061_6f66206c_656e7420_69676e6d_6420616c_3a206261; -defparam bootram.RAM6.INIT_02=256'h74206361_6f206869_65642074_6661696c_6f6e3a20_636f6d6d_6e65745f_66000000; -defparam bootram.RAM6.INIT_03=256'h6172703a_646c655f_0a68616e_00000000_666f7220_696e6720_6c6f6f6b_63686520; -defparam bootram.RAM6.INIT_04=256'h6e736973_696e636f_55445020_0a000000_3d202564_697a6520_72642073_20776569; -defparam bootram.RAM6.INIT_05=256'h53746172_0b0b0b0b_00000000_2025640a_3a202564_67746873_206c656e_74656e74; -defparam bootram.RAM6.INIT_06=256'h6164696e_2e204c6f_6d6f6465_61666520_696e2073_50322b20_20555352_74696e67; -defparam bootram.RAM6.INIT_07=256'h20666f72_6b696e67_43686563_00000000_6172652e_69726d77_66652066_67207361; -defparam bootram.RAM6.INIT_08=256'h2e2e2e00_6d616765_47412069_6e204650_6374696f_726f6475_69642070_2076616c; -defparam bootram.RAM6.INIT_09=256'h666f756e_61676520_4120696d_20465047_74696f6e_6f647563_64207072_56616c69; -defparam bootram.RAM6.INIT_0A=256'h616c6964_4e6f2076_742e0000_20626f6f_6720746f_7074696e_7474656d_642e2041; -defparam bootram.RAM6.INIT_0B=256'h2e0a4661_6f756e64_67652066_20696d61_46504741_696f6e20_64756374_2070726f; -defparam bootram.RAM6.INIT_0C=256'h726d7761_6e206669_6c742d69_20627569_6820746f_726f7567_67207468_6c6c696e; -defparam bootram.RAM6.INIT_0D=256'h6520666f_6d776172_20666972_74696f6e_6f647563_64207072_56616c69_72652e00; -defparam bootram.RAM6.INIT_0E=256'h64696e67_206c6f61_73686564_46696e69_2e2e2e00_64696e67_204c6f61_756e642e; -defparam bootram.RAM6.INIT_0F=256'h65747572_523a2052_4552524f_2e000000_6d616765_6e672069_61727469_2e205374; -defparam bootram.RAM6.INIT_10=256'h6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672; -defparam bootram.RAM6.INIT_11=256'h64756374_2070726f_616c6964_4e6f2076_6e210000_61707065_65722068_206e6576; -defparam bootram.RAM6.INIT_12=256'h7468726f_696e6720_46616c6c_6e642e20_20666f75_77617265_6669726d_696f6e20; -defparam bootram.RAM6.INIT_13=256'h53706565_2e000000_77617265_6669726d_2d696e20_75696c74_746f2062_75676820; -defparam bootram.RAM6.INIT_14=256'h58000000_57455f54_00000000_4e4f4e45_00000000_2025640a_7420746f_64207365; -defparam bootram.RAM6.INIT_15=256'h20666c6f_726e6574_65746865_43000000_45545249_53594d4d_58000000_57455f52; -defparam bootram.RAM6.INIT_16=256'h2077726f_4144563a_4e45475f_4155544f_5048595f_6c3a2000_6e74726f_7720636f; -defparam bootram.RAM6.INIT_17=256'h00000001_00030003_00000000_780a0000_20307825_20676f74_7825782c_74652030; -defparam bootram.RAM6.INIT_18=256'h68616e64_6b657420_20706163_64617465_6e207570_6f722069_21457272_00030203; -defparam bootram.RAM6.INIT_19=256'h2025642c_6e677468_64206c65_796c6f61_64207061_65637465_20457870_6c65723a; -defparam bootram.RAM6.INIT_1A=256'h00002261_000022b1_000022b1_0000220b_00000000_2025640a_20676f74_20627574; -defparam bootram.RAM6.INIT_1B=256'h000022b1_000022b1_000022b1_000022b1_000022b1_000022b1_0000222a_0000224c; -defparam bootram.RAM6.INIT_1C=256'h000022b1_000022a7_00002290_000022b1_000022b1_000022b1_000022b1_000022b1; -defparam bootram.RAM6.INIT_1D=256'h34353637_30313233_00000000_6f72740a_0a0a6162_0000227d_0000223c_000022b1; -defparam bootram.RAM6.INIT_1E=256'hffff00ff_ff00ffff_00ffffff_65000000_792e6578_64756d6d_43444546_38394142; -defparam bootram.RAM6.INIT_1F=256'hffff0031_05050400_01010100_0000342c_00000000_00000000_00000000_ffffff00; -defparam bootram.RAM6.INIT_20=256'h000033c8_10101200_000032a8_000032a0_00003298_00003290_000b0000_0018000f; -defparam bootram.RAM6.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_ffffffff_00000000_ffffffff; -defparam bootram.RAM6.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_00=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_02=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_03=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_04=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; diff --git a/fpga/usrp2/top/N2x0/capture_ddrlvds.v b/fpga/usrp2/top/N2x0/capture_ddrlvds.v deleted file mode 100644 index e261dcbe8..000000000 --- a/fpga/usrp2/top/N2x0/capture_ddrlvds.v +++ /dev/null @@ -1,55 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module capture_ddrlvds - #(parameter WIDTH=7) - (input clk, - input ssclk_p, - input ssclk_n, - input [WIDTH-1:0] in_p, - input [WIDTH-1:0] in_n, - output reg [(2*WIDTH)-1:0] out); - - wire [WIDTH-1:0] ddr_dat; - wire ssclk; - wire [(2*WIDTH)-1:0] out_pre1; - reg [(2*WIDTH)-1:0] out_pre2; - - IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) - clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); - - genvar i; - generate - for(i = 0; i < WIDTH; i = i + 1) - begin : gen_lvds_pins - IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("FALSE")) ibufds - (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) ); - IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2 - (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk), - .CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0)); - end - endgenerate - - always @(posedge clk) - out_pre2 <= out_pre1; - - always @(posedge clk) - out <= out_pre2; - -endmodule // capture_ddrlvds diff --git a/fpga/usrp2/top/N2x0/u2plus.ucf b/fpga/usrp2/top/N2x0/u2plus.ucf deleted file mode 100755 index 5fbe55c26..000000000 --- a/fpga/usrp2/top/N2x0/u2plus.ucf +++ /dev/null @@ -1,424 +0,0 @@ -## Main 100 MHz Clock -NET "CLK_FPGA_P" LOC = "AA13" ; -NET "CLK_FPGA_N" LOC = "Y13" ; - -## ADC -NET "ADC_clkout_p" LOC = "P1" ; -NET "ADC_clkout_n" LOC = "P2" ; -NET "ADCA_12_p" LOC = "Y1" ; -NET "ADCA_12_n" LOC = "Y2" ; -NET "ADCA_10_p" LOC = "W3" ; -NET "ADCA_10_n" LOC = "W4" ; -NET "ADCA_8_p" LOC = "T7" ; -NET "ADCA_8_n" LOC = "U6" ; -NET "ADCA_6_p" LOC = "U5" ; -NET "ADCA_6_n" LOC = "V5" ; -NET "ADCA_4_p" LOC = "T10" ; -NET "ADCA_4_n" LOC = "T9" ; -NET "ADCA_2_p" LOC = "V1" ; -NET "ADCA_2_n" LOC = "V2" ; -NET "ADCA_0_p" LOC = "R8" ; -NET "ADCA_0_n" LOC = "R7" ; -NET "ADCB_2_p" LOC = "U7" ; -NET "ADCB_2_n" LOC = "U8" ; -NET "ADCB_0_p" LOC = "AA2" ; -NET "ADCB_0_n" LOC = "AA3" ; -NET "ADCB_4_p" LOC = "AE1" ; -NET "ADCB_4_n" LOC = "AE2" ; -NET "ADCB_6_p" LOC = "W1" ; -NET "ADCB_6_n" LOC = "W2" ; -NET "ADCB_8_p" LOC = "U3" ; -NET "ADCB_8_n" LOC = "V4" ; -NET "ADCB_10_p" LOC = "J1" ; -NET "ADCB_10_n" LOC = "K1" ; -NET "ADCB_12_p" LOC = "J3" ; -NET "ADCB_12_n" LOC = "J2" ; - -## DAC -NET "DAC_LOCK" LOC = "P4" ; -NET "DACA<0>" LOC = "P8" ; -NET "DACA<1>" LOC = "P9" ; -NET "DACA<2>" LOC = "R5" ; -NET "DACA<3>" LOC = "R6" ; -NET "DACA<4>" LOC = "P7" ; -NET "DACA<5>" LOC = "P6" ; -NET "DACA<6>" LOC = "T3" ; -NET "DACA<7>" LOC = "T4" ; -NET "DACA<8>" LOC = "R3" ; -NET "DACA<9>" LOC = "R4" ; -NET "DACA<10>" LOC = "R2" ; -NET "DACA<11>" LOC = "N1" ; -NET "DACA<12>" LOC = "N2" ; -NET "DACA<13>" LOC = "N5" ; -NET "DACA<14>" LOC = "N4" ; -NET "DACA<15>" LOC = "M2" ; -NET "DACB<0>" LOC = "M5" ; -NET "DACB<1>" LOC = "M6" ; -NET "DACB<2>" LOC = "M4" ; -NET "DACB<3>" LOC = "M3" ; -NET "DACB<4>" LOC = "M8" ; -NET "DACB<5>" LOC = "M7" ; -NET "DACB<6>" LOC = "L4" ; -NET "DACB<7>" LOC = "L3" ; -NET "DACB<8>" LOC = "K3" ; -NET "DACB<9>" LOC = "K2" ; -NET "DACB<10>" LOC = "K5" ; -NET "DACB<11>" LOC = "K4" ; -NET "DACB<12>" LOC = "M10" ; -NET "DACB<13>" LOC = "M9" ; -NET "DACB<14>" LOC = "J5" ; -NET "DACB<15>" LOC = "J4" ; - -## TX DB GPIO -NET "io_tx<15>" LOC = "K6" ; -NET "io_tx<14>" LOC = "L7" ; -NET "io_tx<13>" LOC = "H2" ; -NET "io_tx<12>" LOC = "H1" ; -NET "io_tx<11>" LOC = "L10" ; -NET "io_tx<10>" LOC = "L9" ; -NET "io_tx<9>" LOC = "G3" ; -NET "io_tx<8>" LOC = "F3" ; -NET "io_tx<7>" LOC = "K7" ; -NET "io_tx<6>" LOC = "J6" ; -NET "io_tx<5>" LOC = "E1" ; -NET "io_tx<4>" LOC = "F2" ; -NET "io_tx<3>" LOC = "J7" ; -NET "io_tx<2>" LOC = "H6" ; -NET "io_tx<1>" LOC = "F5" ; -NET "io_tx<0>" LOC = "G4" ; - -## RX DB GPIO -NET "io_rx<15>" LOC = "AD1" ; -NET "io_rx<14>" LOC = "AD2" ; -NET "io_rx<13>" LOC = "AC2" ; -NET "io_rx<12>" LOC = "AC3" ; -NET "io_rx<11>" LOC = "W7" ; -NET "io_rx<10>" LOC = "W6" ; -NET "io_rx<9>" LOC = "U9" ; -NET "io_rx<8>" LOC = "V8" ; -NET "io_rx<7>" LOC = "AB1" ; -NET "io_rx<6>" LOC = "AC1" ; -NET "io_rx<5>" LOC = "V7" ; -NET "io_rx<4>" LOC = "V6" ; -NET "io_rx<3>" LOC = "Y5" ; -NET "io_rx<2>" LOC = "R10" ; -NET "io_rx<1>" LOC = "R1" ; -NET "io_rx<0>" LOC = "M1" ; - -## MISC -NET "leds<5>" LOC = "AF25" ; -NET "leds<4>" LOC = "AE25" ; -NET "leds<3>" LOC = "AF23" ; -NET "leds<2>" LOC = "AE23" ; -NET "leds<1>" LOC = "AB18" ; -NET "FPGA_RESET" LOC = "K24" ; - -## Debug -NET "debug_clk<0>" LOC = "AA10" ; -NET "debug_clk<1>" LOC = "AD11" ; -NET "debug<0>" LOC = "AC19" ; -NET "debug<1>" LOC = "AF20" ; -NET "debug<2>" LOC = "AE20" ; -NET "debug<3>" LOC = "AC16" ; -NET "debug<4>" LOC = "AB16" ; -NET "debug<5>" LOC = "AF19" ; -NET "debug<6>" LOC = "AE19" ; -NET "debug<7>" LOC = "V15" ; -NET "debug<8>" LOC = "U15" ; -NET "debug<9>" LOC = "AE17" ; -NET "debug<10>" LOC = "AD17" ; -NET "debug<11>" LOC = "V14" ; -NET "debug<12>" LOC = "W15" ; -NET "debug<13>" LOC = "AC15" ; -NET "debug<14>" LOC = "AD14" ; -NET "debug<15>" LOC = "AC14" ; -NET "debug<16>" LOC = "AC11" ; -NET "debug<17>" LOC = "AB12" ; -NET "debug<18>" LOC = "AC12" ; -NET "debug<19>" LOC = "V13" ; -NET "debug<20>" LOC = "W13" ; -NET "debug<21>" LOC = "AE8" ; -NET "debug<22>" LOC = "AF8" ; -NET "debug<23>" LOC = "V12" ; -NET "debug<24>" LOC = "W12" ; -NET "debug<25>" LOC = "AB9" ; -NET "debug<26>" LOC = "AC9" ; -NET "debug<27>" LOC = "AC8" ; -NET "debug<28>" LOC = "AB7" ; -NET "debug<29>" LOC = "V11" ; -NET "debug<30>" LOC = "U11" ; -NET "debug<31>" LOC = "Y10" ; - -## UARTS -NET "TXD<3>" LOC = "AD20" ; -NET "TXD<2>" LOC = "AC20" ; -NET "TXD<1>" LOC = "AD19" ; -NET "RXD<3>" LOC = "AF17" ; -NET "RXD<2>" LOC = "AF15" ; -NET "RXD<1>" LOC = "AD12" ; - -## AD9510 -NET "clk_status" LOC = "AD22" ; -NET "CLK_FUNC" LOC = "AC21" ; -NET "clk_sel<0>" LOC = "AE21" ; -NET "clk_sel<1>" LOC = "AD21" ; -NET "clk_en<1>" LOC = "AA17" ; -NET "clk_en<0>" LOC = "Y17" ; - -## I2C -NET "SDA" LOC = "V16" ; -NET "SCL" LOC = "U16" ; - -## Timing -NET "PPS_IN" LOC = "AB6" ; -NET "PPS2_IN" LOC = "AA20" ; - -## SPI -NET "SEN_CLK" LOC = "AA18" ; -NET "MOSI_CLK" LOC = "W17" ; -NET "SCLK_CLK" LOC = "V17" ; -NET "MISO_CLK" LOC = "AC10" ; - -NET "SEN_DAC" LOC = "AE7" ; -NET "SCLK_DAC" LOC = "AF5" ; -NET "MOSI_DAC" LOC = "AE6" ; -NET "MISO_DAC" LOC = "Y3" ; - -NET "SCLK_ADC" LOC = "B1" ; -NET "MOSI_ADC" LOC = "J8" ; -NET "SEN_ADC" LOC = "J9" ; - -NET "MOSI_TX_ADC" LOC = "V10" ; -NET "SEN_TX_ADC" LOC = "W10" ; -NET "SCLK_TX_ADC" LOC = "AC6" ; -NET "MISO_TX_ADC" LOC = "G1" ; - -NET "MOSI_TX_DAC" LOC = "AD6" ; -NET "SEN_TX_DAC" LOC = "AE4" ; -NET "SCLK_TX_DAC" LOC = "AF4" ; - -NET "SCLK_TX_DB" LOC = "AE3" ; -NET "MOSI_TX_DB" LOC = "AF3" ; -NET "SEN_TX_DB" LOC = "W9" ; -NET "MISO_TX_DB" LOC = "AA5" ; - -NET "MOSI_RX_ADC" LOC = "E3" ; -NET "SCLK_RX_ADC" LOC = "F4" ; -NET "SEN_RX_ADC" LOC = "D3" ; -NET "MISO_RX_ADC" LOC = "C1" ; - -NET "SCLK_RX_DAC" LOC = "E4" ; -NET "SEN_RX_DAC" LOC = "K9" ; -NET "MOSI_RX_DAC" LOC = "K8" ; - -NET "SCLK_RX_DB" LOC = "G6" ; -NET "MOSI_RX_DB" LOC = "H7" ; -NET "SEN_RX_DB" LOC = "B2" ; -NET "MISO_RX_DB" LOC = "H4" ; - -## ETH PHY -NET "CLK_TO_MAC" LOC = "P26" ; - -NET "GMII_TXD<7>" LOC = "G21" ; -NET "GMII_TXD<6>" LOC = "C26" ; -NET "GMII_TXD<5>" LOC = "C25" ; -NET "GMII_TXD<4>" LOC = "J21" ; -NET "GMII_TXD<3>" LOC = "H21" ; -NET "GMII_TXD<2>" LOC = "D25" ; -NET "GMII_TXD<1>" LOC = "D24" ; -NET "GMII_TXD<0>" LOC = "E26" ; -NET "GMII_TX_EN" LOC = "D26" ; -NET "GMII_TX_ER" LOC = "J19" ; -NET "GMII_GTX_CLK" LOC = "J20" ; -NET "GMII_TX_CLK" LOC = "P25" ; - -NET "GMII_RX_CLK" LOC = "P21" ; -NET "GMII_RXD<7>" LOC = "G22" ; -NET "GMII_RXD<6>" LOC = "K19" ; -NET "GMII_RXD<5>" LOC = "K18" ; -NET "GMII_RXD<4>" LOC = "E24" ; -NET "GMII_RXD<3>" LOC = "F23" ; -NET "GMII_RXD<2>" LOC = "L18" ; -NET "GMII_RXD<1>" LOC = "L17" ; -NET "GMII_RXD<0>" LOC = "F25" ; -NET "GMII_RX_DV" LOC = "F24" ; -NET "GMII_RX_ER" LOC = "L20" ; -NET "GMII_CRS" LOC = "K20" ; -NET "GMII_COL" LOC = "G23" ; - -NET "PHY_INTn" LOC = "L22" ; -NET "MDIO" LOC = "K21" ; -NET "MDC" LOC = "J23" ; -NET "PHY_RESETn" LOC = "J22" ; -NET "ETH_LED" LOC = "H20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; - -## MIMO Interface -NET "exp_time_out_p" LOC = "Y14" ; -NET "exp_time_out_n" LOC = "AA14" ; -NET "exp_time_in_p" LOC = "N18" ; -NET "exp_time_in_n" LOC = "N17" ; -NET "exp_user_out_p" LOC = "AF14" ; -NET "exp_user_out_n" LOC = "AE14" ; -NET "exp_user_in_p" LOC = "L24" ; -NET "exp_user_in_n" LOC = "M23" ; - -## SERDES -NET "ser_enable" LOC = "R20" ; -NET "ser_prbsen" LOC = "U23" ; -NET "ser_loopen" LOC = "R19" ; -NET "ser_rx_en" LOC = "Y21" ; -NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK -NET "ser_t<15>" LOC = "V23" ; -NET "ser_t<14>" LOC = "U22" ; -NET "ser_t<13>" LOC = "V24" ; -NET "ser_t<12>" LOC = "V25" ; -NET "ser_t<11>" LOC = "W23" ; -NET "ser_t<10>" LOC = "V22" ; -NET "ser_t<9>" LOC = "T18" ; -NET "ser_t<8>" LOC = "T17" ; -NET "ser_t<7>" LOC = "Y24" ; -NET "ser_t<6>" LOC = "Y25" ; -NET "ser_t<5>" LOC = "U21" ; -NET "ser_t<4>" LOC = "T20" ; -NET "ser_t<3>" LOC = "Y22" ; -NET "ser_t<2>" LOC = "Y23" ; -NET "ser_t<1>" LOC = "U19" ; -NET "ser_t<0>" LOC = "U18" ; -NET "ser_tkmsb" LOC = "AA24" ; -NET "ser_tklsb" LOC = "AA25" ; -NET "ser_rx_clk" LOC = "P18" ; -NET "ser_r<15>" LOC = "V21" ; -NET "ser_r<14>" LOC = "U20" ; -NET "ser_r<13>" LOC = "AA22" ; -NET "ser_r<12>" LOC = "AA23" ; -NET "ser_r<11>" LOC = "V18" ; -NET "ser_r<10>" LOC = "V19" ; -NET "ser_r<9>" LOC = "AB23" ; -NET "ser_r<8>" LOC = "AC26" ; -NET "ser_r<7>" LOC = "AB26" ; -NET "ser_r<6>" LOC = "AD26" ; -NET "ser_r<5>" LOC = "AC25" ; -NET "ser_r<4>" LOC = "W20" ; -NET "ser_r<3>" LOC = "W21" ; -NET "ser_r<2>" LOC = "AC23" ; -NET "ser_r<1>" LOC = "AC24" ; -NET "ser_r<0>" LOC = "AE26" ; -NET "ser_rkmsb" LOC = "AD25" ; -NET "ser_rklsb" LOC = "Y20" ; - -## SRAM -NET "RAM_D<35>" LOC = "K16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<34>" LOC = "D20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<33>" LOC = "C20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<32>" LOC = "E21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<31>" LOC = "D21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<30>" LOC = "C21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<29>" LOC = "B21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<28>" LOC = "H17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<27>" LOC = "G17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<26>" LOC = "B23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<25>" LOC = "A22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<24>" LOC = "D23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<23>" LOC = "C23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<22>" LOC = "D22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<21>" LOC = "C22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<20>" LOC = "F19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<19>" LOC = "G20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<18>" LOC = "F20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<17>" LOC = "F7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<16>" LOC = "E7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<15>" LOC = "G9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<14>" LOC = "H9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<13>" LOC = "G10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<12>" LOC = "H10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<11>" LOC = "A4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<10>" LOC = "B4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<9>" LOC = "C5" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<8>" LOC = "D6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<7>" LOC = "J11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<6>" LOC = "K11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<5>" LOC = "B7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<4>" LOC = "C7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<3>" LOC = "B6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<2>" LOC = "C6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<1>" LOC = "C8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<0>" LOC = "D8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<0>" LOC = "C11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<1>" LOC = "E12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<2>" LOC = "F12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<3>" LOC = "D13" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<4>" LOC = "C12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<5>" LOC = "A12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<6>" LOC = "B12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<7>" LOC = "E14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<8>" LOC = "F14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<9>" LOC = "B15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<10>" LOC = "A15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<11>" LOC = "D16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<12>" LOC = "C15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<13>" LOC = "D17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<14>" LOC = "C16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<15>" LOC = "F15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<16>" LOC = "C17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<17>" LOC = "B17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<18>" LOC = "B18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<19>" LOC = "A18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<20>" LOC = "D18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_BWn<3>" LOC = "D9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_BWn<2>" LOC = "A9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_BWn<1>" LOC = "B9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_BWn<0>" LOC = "G12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_ZZ" LOC = "J12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_LDn" LOC = "H12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_OEn" LOC = "C10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_WEn" LOC = "D10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_CENn" LOC = "B10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_CLK" LOC = "A10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; - -## SPI Flash -NET "flash_miso" LOC = "AF24" ; -NET "flash_clk" LOC = "AE24" ; -NET "flash_mosi" LOC = "AB15" ; -NET "flash_cs" LOC = "AA7" ; - -## MISC FPGA, unused for now -#NET "PROG_B" LOC = "A2" ; -#NET "PUDC_B" LOC = "G8" ; -#NET "DONE" LOC = "AB21" ; -#NET "INIT_B" LOC = "AA15" ; - - -#NET "unnamed_net19" LOC = "AE9" ; # VS1 -#NET "unnamed_net18" LOC = "AF9" ; # VS0 -#NET "unnamed_net17" LOC = "AA12" ; # VS2 -#NET "unnamed_net16" LOC = "Y7" ; # M2 -#NET "unnamed_net15" LOC = "AC4" ; # M1 -#NET "unnamed_net14" LOC = "AD4" ; # M0 -#NET "unnamed_net13" LOC = "D4" ; # TMS -#NET "unnamed_net12" LOC = "E23" ; # TDO -#NET "unnamed_net11" LOC = "G7" ; # TDI -#NET "unnamed_net10" LOC = "A25" ; # TCK -#NET "unnamed_net20" LOC = "V20" ; # SUSPEND - - -NET "clk_to_mac" TNM_NET = "clk_to_mac"; -TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; - -NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; -TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; - -NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; -TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; - -NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; -TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; - -TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; - -#NET "CLK_FPGA_P" CLOCK_DEDICATED_ROUTE = FALSE; -#PIN "DCM_INST/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; - -#NET "RAM_CLK" CLOCK_DEDICATED_ROUTE = FALSE; -#PIN "DCM_INST1/DCM_SP.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE; - - diff --git a/fpga/usrp2/top/N2x0/u2plus.v b/fpga/usrp2/top/N2x0/u2plus.v deleted file mode 100644 index be1f355d2..000000000 --- a/fpga/usrp2/top/N2x0/u2plus.v +++ /dev/null @@ -1,473 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -`timescale 1ns / 1ps -//`define LVDS 1 -//`define DCM_FOR_RAMCLK -////////////////////////////////////////////////////////////////////////////////// - -module u2plus - ( - input CLK_FPGA_P, input CLK_FPGA_N, // Diff - - // ADC - input ADC_clkout_p, input ADC_clkout_n, - input ADCA_12_p, input ADCA_12_n, - input ADCA_10_p, input ADCA_10_n, - input ADCA_8_p, input ADCA_8_n, - input ADCA_6_p, input ADCA_6_n, - input ADCA_4_p, input ADCA_4_n, - input ADCA_2_p, input ADCA_2_n, - input ADCA_0_p, input ADCA_0_n, - input ADCB_12_p, input ADCB_12_n, - input ADCB_10_p, input ADCB_10_n, - input ADCB_8_p, input ADCB_8_n, - input ADCB_6_p, input ADCB_6_n, - input ADCB_4_p, input ADCB_4_n, - input ADCB_2_p, input ADCB_2_n, - input ADCB_0_p, input ADCB_0_n, - - // DAC - output reg [15:0] DACA, - output reg [15:0] DACB, - input DAC_LOCK, // unused for now - - // DB IO Pins - inout [15:0] io_tx, - inout [15:0] io_rx, - - // Misc, debug - output [5:1] leds, // LED4 is shared w/INIT_B - input FPGA_RESET, - output [1:0] debug_clk, - output [31:0] debug, - output [3:1] TXD, input [3:1] RXD, // UARTs - //input [3:0] dipsw, // Forgot DIP Switches... - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input CLK_FUNC, // FIXME is an input to control the 9510 - input clk_status, - - inout SCL, inout SDA, // I2C - - // PPS - input PPS_IN, input PPS2_IN, - - // SPI - output SEN_CLK, output SCLK_CLK, output MOSI_CLK, input MISO_CLK, - output SEN_DAC, output SCLK_DAC, output MOSI_DAC, input MISO_DAC, - output SEN_ADC, output SCLK_ADC, output MOSI_ADC, - output SEN_TX_DB, output SCLK_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, - output SEN_TX_DAC, output SCLK_TX_DAC, output MOSI_TX_DAC, - output SEN_TX_ADC, output SCLK_TX_ADC, output MOSI_TX_ADC, input MISO_TX_ADC, - output SEN_RX_DB, output SCLK_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, - output SEN_RX_DAC, output SCLK_RX_DAC, output MOSI_RX_DAC, - output SEN_RX_ADC, output SCLK_RX_ADC, output MOSI_RX_ADC, input MISO_RX_ADC, - - // GigE PHY - input CLK_TO_MAC, - - output reg [7:0] GMII_TXD, - output reg GMII_TX_EN, - output reg GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - input GMII_RX_CLK, - input [7:0] GMII_RXD, - input GMII_RX_DV, - input GMII_RX_ER, - input GMII_COL, - input GMII_CRS, - - input PHY_INTn, // open drain - inout MDIO, - output MDC, - output PHY_RESETn, - output ETH_LED, - -// input POR, - - // Expansion - input exp_time_in_p, input exp_time_in_n, // Diff - output exp_time_out_p, output exp_time_out_n, // Diff - input exp_user_in_p, input exp_user_in_n, // Diff - output exp_user_out_p, output exp_user_out_n, // Diff - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output reg [15:0] ser_t, - output reg ser_tklsb, - output reg ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // SRAM - inout [35:0] RAM_D, - output [20:0] RAM_A, - output [3:0] RAM_BWn, - output RAM_ZZ, - output RAM_LDn, - output RAM_OEn, - output RAM_WEn, - output RAM_CENn, - output RAM_CLK, - - // SPI Flash - output flash_cs, - output flash_clk, - output flash_mosi, - input flash_miso - ); - - wire CLK_TO_MAC_int, CLK_TO_MAC_int2; - IBUFG phyclk (.O(CLK_TO_MAC_int), .I(CLK_TO_MAC)); - BUFG phyclk2 (.O(CLK_TO_MAC_int2), .I(CLK_TO_MAC_int)); - - // FPGA-specific pins connections - wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - - wire exp_time_in; - IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); - defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; - - wire exp_time_out; - OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); - defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; - - wire exp_user_in; - IBUFDS exp_user_in_pin (.O(exp_user_in),.I(exp_user_in_p),.IB(exp_user_in_n)); - defparam exp_user_in_pin.IOSTANDARD = "LVDS_25"; - - wire exp_user_out; - OBUFDS exp_user_out_pin (.O(exp_user_out_p),.OB(exp_user_out_n),.I(exp_user_out)); - defparam exp_user_out_pin.IOSTANDARD = "LVDS_25"; - - reg [5:0] clock_ready_d; - always @(posedge clk_fpga) - clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; - wire dcm_rst = ~&clock_ready_d & |clock_ready_d; - - // ADC A is inverted on the schematic to facilitate a clean layout - // We account for that here by inverting it -`ifdef LVDS - wire [13:0] adc_a, adc_a_inv, adc_b; - capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds - (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), - .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, - {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), - .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, - {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), - .out({adc_a_inv,adc_b})); - assign adc_a = ~adc_a_inv; -`else - reg [13:0] adc_a, adc_b, adc_a_pre, adc_b_pre; - always @(posedge dsp_clk) - begin - adc_a_pre <= {ADCA_12_p,ADCA_12_n, ADCA_10_p,ADCA_10_n, ADCA_8_p,ADCA_8_n, ADCA_6_p,ADCA_6_n, - ADCA_4_p,ADCA_4_n, ADCA_2_p,ADCA_2_n, ADCA_0_p,ADCA_0_n }; - adc_b_pre <= {ADCB_12_p,ADCB_12_n, ADCB_10_p,ADCB_10_n, ADCB_8_p,ADCB_8_n, ADCB_6_p,ADCB_6_n, - ADCB_4_p,ADCB_4_n, ADCB_2_p,ADCB_2_n, ADCB_0_p,ADCB_0_n }; - adc_a <= ~adc_a_pre; //Note: A must be inverted, but not B - adc_b <= adc_b_pre; - end -`endif // !`ifdef LVDS - - // Handle Clocks - DCM DCM_INST (.CLKFB(dsp_clk), - .CLKIN(clk_fpga), - .DSSEN(0), - .PSCLK(0), - .PSEN(0), - .PSINCDEC(0), - .RST(dcm_rst), - .CLKDV(clk_div), - .CLKFX(), - .CLKFX180(), - .CLK0(dcm_out), - .CLK2X(), - .CLK2X180(), - .CLK90(), - .CLK180(), - .CLK270(clk270_100), - .LOCKED(LOCKED_OUT), - .PSDONE(), - .STATUS()); - defparam DCM_INST.CLK_FEEDBACK = "1X"; - defparam DCM_INST.CLKDV_DIVIDE = 2.0; - defparam DCM_INST.CLKFX_DIVIDE = 1; - defparam DCM_INST.CLKFX_MULTIPLY = 4; - defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST.CLKIN_PERIOD = 10.000; - defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; - defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST.FACTORY_JF = 16'h8080; - defparam DCM_INST.PHASE_SHIFT = 0; - defparam DCM_INST.STARTUP_WAIT = "FALSE"; - - BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); - BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - - // Create clock for external SRAM thats -90degree phase to DSPCLK (i.e) 2nS earlier at 100MHz. - BUFG clk270_100_buf_i1 (.I(clk270_100), - .O(clk270_100_buf)); - OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), - .C0(clk270_100_buf), - .C1(~clk270_100_buf), - .CE(1'b1), - .D0(1'b1), - .D1(1'b0), - .R(1'b0), - .S(1'b0)); - - // I2C -- Don't use external transistors for open drain, the FPGA implements this - IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); - - // LEDs are active low outputs - wire [5:0] leds_int; - assign {ETH_LED,leds} = {6'b011111 ^ leds_int}; // drive low to turn on leds - - // SPI - wire miso, mosi, sclk; - - assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; - assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; - - assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | - (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | - (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); - - wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; - wire [7:0] GMII_TXD_unreg; - wire GMII_GTX_CLK_int; - - always @(posedge GMII_GTX_CLK_int) - begin - GMII_TX_EN <= GMII_TX_EN_unreg; - GMII_TX_ER <= GMII_TX_ER_unreg; - GMII_TXD <= GMII_TXD_unreg; - end - - OFDDRRSE OFDDRRSE_gmii_inst - (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) - .C0(GMII_GTX_CLK_int), // 0 degree clock input - .C1(~GMII_GTX_CLK_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - - wire ser_tklsb_unreg, ser_tkmsb_unreg; - wire [15:0] ser_t_unreg; - wire ser_tx_clk_int; - - always @(posedge ser_tx_clk_int) - begin - ser_tklsb <= ser_tklsb_unreg; - ser_tkmsb <= ser_tkmsb_unreg; - ser_t <= ser_t_unreg; - end - - assign ser_tx_clk = clk_fpga; - - reg [15:0] ser_r_int; - reg ser_rklsb_int, ser_rkmsb_int; - - always @(posedge ser_rx_clk) - begin - ser_r_int <= ser_r; - ser_rklsb_int <= ser_rklsb; - ser_rkmsb_int <= ser_rkmsb; - end - - /* - OFDDRRSE OFDDRRSE_serdes_inst - (.Q(ser_tx_clk), // Data output (connect directly to top-level port) - .C0(ser_tx_clk_int), // 0 degree clock input - .C1(~ser_tx_clk_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - */ - - - // - // Instantiate IO for Bidirectional bus to SRAM - // - wire [35:0] RAM_D_pi; - wire [35:0] RAM_D_po; - wire RAM_D_poe; - - genvar i; - - generate - for (i=0;i<36;i=i+1) - begin : gen_RAM_D_IO - - IOBUF #( - .DRIVE(12), - .IOSTANDARD("LVCMOS25"), - .SLEW("FAST") - ) - RAM_D_i ( - .O(RAM_D_pi[i]), - .I(RAM_D_po[i]), - .IO(RAM_D[i]), - .T(RAM_D_poe) - ); - end // block: gen_RAM_D_IO - endgenerate - - - - wire [15:0] dac_a_int, dac_b_int; - // DAC A and B are swapped in schematic to facilitate clean layout - // DAC A is also inverted in schematic to facilitate clean layout - always @(negedge dsp_clk) DACA <= ~dac_b_int; - always @(negedge dsp_clk) DACB <= dac_a_int; - - wire pps; - assign pps = PPS_IN ^ PPS2_IN; - - u2plus_core u2p_c(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (CLK_TO_MAC_int2), - .pps_in (pps), - .leds (leds_int), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_time_in (exp_time_in), - .exp_time_out (exp_time_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD_unreg[7:0]), - .GMII_TX_EN (GMII_TX_EN_unreg), - .GMII_TX_ER (GMII_TX_ER_unreg), - .GMII_GTX_CLK (GMII_GTX_CLK_int), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk_int), - .ser_t (ser_t_unreg[15:0]), - .ser_tklsb (ser_tklsb_unreg), - .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r_int[15:0]), - .ser_rklsb (ser_rklsb_int), - .ser_rkmsb (ser_rkmsb_int), - .adc_a (adc_a[13:0]), - .adc_ovf_a (1'b0), - .adc_on_a (), - .adc_oe_a (), - .adc_b (adc_b[13:0]), - .adc_ovf_b (1'b0), - .adc_on_b (), - .adc_oe_b (), - .dac_a (dac_a_int[15:0]), - .dac_b (dac_b_int[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk), - .mosi (mosi), - .miso (miso), - .sen_clk (SEN_CLK), - .sen_dac (SEN_DAC), - .sen_adc (SEN_ADC), - .sen_tx_db (SEN_TX_DB), - .sen_tx_adc (SEN_TX_ADC), - .sen_tx_dac (SEN_TX_DAC), - .sen_rx_db (SEN_RX_DB), - .sen_rx_adc (SEN_RX_ADC), - .sen_rx_dac (SEN_RX_DAC), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D_po (RAM_D_po), - .RAM_D_pi (RAM_D_pi), - .RAM_D_poe (RAM_D_poe), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (TXD[3:1]), - .uart_rx_i ({1'b1,RXD[3:1]}), - .uart_baud_o (), - .sim_mode (1'b0), - .clock_divider (2), - .button (FPGA_RESET), - .spiflash_cs (flash_cs), - .spiflash_clk (flash_clk), - .spiflash_miso (flash_miso), - .spiflash_mosi (flash_mosi) - ); - - // Drive low so that RAM does not sleep. - assign RAM_ZZ = 0; - // Byte Writes are qualified by the global write enable - // Always do 36bit operations to extram. - assign RAM_BWn = 4'b0000; - -endmodule // u2plus diff --git a/fpga/usrp2/top/N2x0/u2plus_core.v b/fpga/usrp2/top/N2x0/u2plus_core.v deleted file mode 100644 index f616681d2..000000000 --- a/fpga/usrp2/top/N2x0/u2plus_core.v +++ /dev/null @@ -1,772 +0,0 @@ -// -// Copyright 2011-2013 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// //////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_core -// //////////////////////////////////////////////////////////////////////////////// - -module u2plus_core - (// Clocks - input dsp_clk, - input wb_clk, - output clock_ready, - input clk_to_mac, - input pps_in, - - // Misc, debug - output [7:0] leds, - output [31:0] debug, - output [1:0] debug_clk, - - // Expansion - input exp_time_in, - output exp_time_out, - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output [7:0] GMII_TXD, - output GMII_TX_EN, - output GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output [15:0] ser_t, - output ser_tklsb, - output ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - input por, - output config_success, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_on_a, - output adc_oe_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_on_b, - output adc_oe_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - - // I2C - input scl_pad_i, - output scl_pad_o, - output scl_pad_oen_o, - input sda_pad_i, - output sda_pad_o, - output sda_pad_oen_o, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Generic SPI - output sclk, - output mosi, - input miso, - output sen_clk, - output sen_dac, - output sen_adc, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output sen_rx_db, - output sen_rx_adc, - output sen_rx_dac, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx, - - // External RAM - input [35:0] RAM_D_pi, - output [35:0] RAM_D_po, - output RAM_D_poe, - output [20:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn, - - // Debug stuff - output [3:0] uart_tx_o, - input [3:0] uart_rx_i, - output [3:0] uart_baud_o, - input sim_mode, - input [3:0] clock_divider, - input button, - - output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi - ); - - localparam SR_MISC = 0; // 7 regs - localparam SR_USER_REGS = 8; // 2 - localparam SR_TIME64 = 10; // 6 - localparam SR_BUF_POOL = 16; // 4 - localparam SR_SPI_CORE = 20; // 3 - localparam SR_RX_FRONT = 24; // 5 - localparam SR_RX_CTRL0 = 32; // 9 - localparam SR_RX_DSP0 = 48; // 7 - localparam SR_RX_CTRL1 = 80; // 9 - localparam SR_RX_DSP1 = 96; // 7 - - localparam SR_TX_FRONT = 128; // ? - localparam SR_TX_CTRL = 144; // 6 - localparam SR_TX_DSP = 160; // 5 - - localparam SR_GPIO = 184; // 5 - localparam SR_UDP_SM = 192; // 64 - - // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 - // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs - // localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo - localparam DSP_RX_FIFOSIZE = 10; - localparam DSP_TX_FIFOSIZE = 10; - localparam ETH_TX_FIFOSIZE = 9; - localparam ETH_RX_FIFOSIZE = 11; - localparam SERDES_TX_FIFOSIZE = 9; - localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? - - wire [7:0] set_addr, set_addr_dsp, set_addr_user; - wire [31:0] set_data, set_data_dsp, set_data_user; - wire set_stb, set_stb_dsp, set_stb_user; - - reg wb_rst; - wire dsp_rst = wb_rst; - - wire [31:0] status; - wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; - wire proc_int, overrun0, overrun1, underrun; - wire [3:0] uart_tx_int, uart_rx_int; - - wire [31:0] debug_gpio_0, debug_gpio_1; - - wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; - - wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; - wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; - wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; - - wire serdes_link_up, good_sync; - wire epoch; - wire [31:0] irq; - wire [63:0] vita_time, vita_time_pps; - - wire run_rx0, run_rx1, run_tx; - reg run_rx0_d1, run_rx1_d1; - - // /////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - localparam dw = 32; // Data bus width - localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m0_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, - s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, - sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o; - wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; - wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; - wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; - wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; - wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; - wire m0_err, m0_rty; - wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; - - wb_1master #(.decode_w(8), - .s0_addr(8'b0000_0000),.s0_mask(8'b1100_0000), // Main RAM (0-16K) - .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // Packet Router (16-20K) - .s2_addr(8'b0101_0000),.s2_mask(8'b1111_1100), // SPI - .s3_addr(8'b0101_0100),.s3_mask(8'b1111_1100), // I2C - .s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100), // Unused - .s5_addr(8'b0101_1100),.s5_mask(8'b1111_1100), // Readback - .s6_addr(8'b0110_0000),.s6_mask(8'b1111_0000), // Ethernet MAC - .s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000), // Settings Bus (only uses 1K) - .s8_addr(8'b1000_0000),.s8_mask(8'b1111_1100), // PIC - .s9_addr(8'b1000_0100),.s9_mask(8'b1111_1100), // Unused - .sa_addr(8'b1000_1000),.sa_mask(8'b1111_1100), // UART - .sb_addr(8'b1000_1100),.sb_mask(8'b1111_1100), // Unused - .sc_addr(8'b1001_0000),.sc_mask(8'b1111_0000), // Unused - .sd_addr(8'b1010_0000),.sd_mask(8'b1111_0000), // ICAP - .se_addr(8'b1011_0000),.se_mask(8'b1111_0000), // SPI Flash - .sf_addr(8'b1100_0000),.sf_mask(8'b1100_0000), // 48K-64K, Boot RAM - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), - .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), - .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), - .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), - .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), - .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), - .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), - .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), - .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), - .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), - .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), - .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), - .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), - .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), - .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); - - assign s2_ack = 0; - assign s4_ack = 0; - assign s9_ack = 0; - assign sb_ack = 0; - assign sc_ack = 0; - - // //////////////////////////////////////////////////////////////////////////////////////// - // Reset Controller - - reg cpu_bldr_ctrl_state; - localparam CPU_BLDR_CTRL_WAIT = 0; - localparam CPU_BLDR_CTRL_DONE = 1; - - wire bldr_done; - wire por_rst; - wire [aw-1:0] cpu_adr; - - // Swap boot ram and main ram when in bootloader mode - assign m0_adr = (^cpu_adr[15:14] | (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_DONE)) ? cpu_adr : - cpu_adr ^ 16'hC000; - - system_control sysctrl - (.wb_clk_i(wb_clk), .wb_rst_o(por_rst), .ram_loader_done_i(1'b1) ); - - always @(posedge wb_clk) - if(por_rst) begin - cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_WAIT; - wb_rst <= 1'b1; - end - else begin - case(cpu_bldr_ctrl_state) - - CPU_BLDR_CTRL_WAIT: begin - wb_rst <= 1'b0; - if (bldr_done == 1'b1) begin //set by the bootloader - cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_DONE; - wb_rst <= 1'b1; - end - end - - CPU_BLDR_CTRL_DONE: begin //stay here forever - wb_rst <= 1'b0; - end - - endcase //cpu_bldr_ctrl_state - end - - // ///////////////////////////////////////////////////////////////////////// - // Processor - - assign bus_error = m0_err | m0_rty; - - wire [63:0] zpu_status; - zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) - zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(~wb_rst), - // Data Wishbone bus to system bus fabric - .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(cpu_adr), - .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), - // Interrupts and exceptions - .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); - - // ///////////////////////////////////////////////////////////////////////// - // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone - // Dual Ported Main RAM -- D-Port is Slave #F on main Wishbone - // I-port connects directly to processor - - bootram bootram(.clk(wb_clk), .reset(wb_rst), - .if_adr(14'b0), .if_data(), - .dwb_adr_i(sf_adr[13:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), - .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel)); - -////blinkenlights v0.1 -//defparam bootram.RAM0.INIT_00=256'hbc32fff0_aa43502b_b00000fe_30630001_80000000_10600000_a48500ff_10a00000; -//defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_308000ff_be23000c_a4640001; - -`include "bootloader.rmi" - - ram_harvard2 #(.AWIDTH(14),.RAM_SIZE(16384)) - sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .if_adr(14'b0), .if_data(), - .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool, slave #1 - wire rd0_ready_i, rd0_ready_o; - wire rd1_ready_i, rd1_ready_o; - wire rd2_ready_i, rd2_ready_o; - wire rd3_ready_i, rd3_ready_o; - wire [35:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_ready_i, wr0_ready_o; - wire wr1_ready_i, wr1_ready_o; - wire wr2_ready_i, wr2_ready_o; - wire wr3_ready_i, wr3_ready_o; - wire [35:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - wire [35:0] sfc_wr_data, sfc_rd_data; - wire sfc_wr_ready, sfc_rd_ready; - wire sfc_wr_valid, sfc_rd_valid; - - wire [35:0] tx_err_data; - wire tx_err_src_rdy, tx_err_dst_rdy; - - wire [31:0] router_debug; - - packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), - - .status(status), .sys_int_o(buffer_int), .debug(router_debug), - - .ser_inp_data(wr0_dat), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), - .dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o), - .dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o), - .eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), - .err_inp_data(tx_err_data), .err_inp_valid(tx_err_src_rdy), .err_inp_ready(tx_err_dst_rdy), - .ctl_inp_data(sfc_wr_data), .ctl_inp_valid(sfc_wr_valid), .ctl_inp_ready(sfc_wr_ready), - - .ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), - .dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), - .ctl_out_data(sfc_rd_data), .ctl_out_valid(sfc_rd_valid), .ctl_out_ready(sfc_rd_ready), - .eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) - ); - - // ///////////////////////////////////////////////////////////////////////// - // SPI -- Slave #2 - wire [31:0] spi_debug; - wire [31:0] spi_readback; - wire spi_ready; - simple_spi_core #(.BASE(SR_SPI_CORE), .WIDTH(9)) shared_spi( - .clock(dsp_clk), .reset(dsp_rst), - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .readback(spi_readback), .ready(spi_ready), - .sen({sen_adc, sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk(sclk), .mosi(mosi), .miso(miso), .debug(spi_debug) - ); - - // ///////////////////////////////////////////////////////////////////////// - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_dat_i[31:8] = 24'd0; - - // ///////////////////////////////////////////////////////////////////////// - // GPIOs - - wire [31:0] gpio_readback; - - gpio_atr #(.BASE(SR_GPIO), .WIDTH(32)) - gpio_atr(.clk(dsp_clk),.reset(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .rx(run_rx0_d1 | run_rx1_d1), .tx(run_tx), - .gpio({io_tx,io_rx}), .gpio_readback(gpio_readback) ); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool Status -- Slave #5 - - //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd10, 16'd1}; //major, minor - - wire [31:0] irq_readback = {18'b0, button, spi_ready, clk_status, serdes_link_up, 10'b0}; - - wb_readback_mux buff_pool_status - (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), - .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - - .word00(spi_readback),.word01(32'hffff_ffff),.word02(32'hffff_ffff),.word03(32'hffff_ffff), - .word04(32'hffff_ffff),.word05(32'hffff_ffff),.word06(32'hffff_ffff),.word07(32'hffff_ffff), - .word08(status),.word09(32'hffff_ffff),.word10(32'hffff_ffff), - .word11(vita_time[31:0]),.word12(compat_num),.word13(irq_readback), - .word14(32'hffff_ffff),.word15(32'hffff_ffff) - ); - - // ///////////////////////////////////////////////////////////////////////// - // Ethernet MAC Slave #6 - - simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), - .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper - (.clk125(clk_to_mac), .reset(wb_rst), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .sys_clk(dsp_clk), - .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), - .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), - .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), - .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), - .mdio(MDIO), .mdc(MDC), - .debug(debug_mac)); - - // ///////////////////////////////////////////////////////////////////////// - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_dat_i = 32'd0; - - wire set_stb_dsp0, set_stb_dsp1; - wire [31:0] set_data_dsp0, set_data_dsp1; - wire [7:0] set_addr_dsp0, set_addr_dsp1; - - //mux settings_bus_crossclock and settings_readback_bus_fifo_ctrl with prio - assign set_stb_dsp = set_stb_dsp0 | set_stb_dsp1; - assign set_addr_dsp = set_stb_dsp1? set_addr_dsp1 : set_addr_dsp0; - assign set_data_dsp = set_stb_dsp1? set_data_dsp1 : set_data_dsp0; - - settings_bus_crossclock #(.FLOW_CTRL(1/*on*/)) settings_bus_crossclock - (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), - .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp0), .set_addr_o(set_addr_dsp0), .set_data_o(set_data_dsp0), - .blocked(set_stb_dsp1)); - - user_settings #(.BASE(SR_USER_REGS)) user_settings - (.clk(dsp_clk),.rst(dsp_rst),.set_stb(set_stb_dsp), - .set_addr(set_addr_dsp),.set_data(set_data_dsp), - .set_addr_user(set_addr_user),.set_data_user(set_data_user), - .set_stb_user(set_stb_user) ); - - // ///////////////////////////////////////////////////////////////////////// - // Settings + Readback Bus -- FIFO controlled - - wire [31:0] sfc_debug; - wire sfc_clear; - settings_fifo_ctrl #(.PROT_DEST(3), .PROT_HDR(1)) sfc - ( - .clock(dsp_clk), .reset(dsp_rst), .clear(sfc_clear), - .vita_time(vita_time), .perfs_ready(spi_ready), - .in_data(sfc_rd_data), .in_valid(sfc_rd_valid), .in_ready(sfc_rd_ready), - .out_data(sfc_wr_data), .out_valid(sfc_wr_valid), .out_ready(sfc_wr_ready), - .strobe(set_stb_dsp1), .addr(set_addr_dsp1), .data(set_data_dsp1), - .word00(spi_readback),.word01(32'hffff_ffff),.word02(32'hffff_ffff),.word03(32'hffff_ffff), - .word04(32'hffff_ffff),.word05(32'hffff_ffff),.word06(32'hffff_ffff),.word07(32'hffff_ffff), - .word08(32'hffff_ffff),.word09(gpio_readback),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(32'hffff_ffff),.word13(irq_readback), - .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]), - .debug(sfc_debug) - ); - - setting_reg #(.my_addr(SR_BUF_POOL+1/*same as packet dispatcher*/),.width(1)) sr_clear_sfc - (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.changed(sfc_clear)); - - // Output control lines - wire [7:0] clock_outs, serdes_outs, adc_outs; - assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; - assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; - assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; - - wire phy_reset; - assign PHY_RESETn = ~phy_reset; - - setting_reg #(.my_addr(SR_MISC+0),.width(8)) sr_clk - (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),.in(set_data),.out(clock_outs),.changed()); - - setting_reg #(.my_addr(SR_MISC+1),.width(8)) sr_ser - (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(serdes_outs),.changed()); - - setting_reg #(.my_addr(SR_MISC+2),.width(8)) sr_adc - (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(adc_outs),.changed()); - - setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy - (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(phy_reset),.changed()); - - setting_reg #(.my_addr(SR_MISC+5),.width(1)) sr_bld - (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),.out(bldr_done),.changed()); - - // ///////////////////////////////////////////////////////////////////////// - // LEDS - // register 8 determines whether leds are controlled by SW or not - // 1 = controlled by HW, 0 = by SW - // In Rev3 there are only 6 leds, and the highest one is on the ETH connector - - wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {run_tx, (run_rx0_d1 | run_rx1_d1), clk_status, serdes_link_up & good_sync, 1'b0}; - - setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led - (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(led_sw),.changed()); - - setting_reg #(.my_addr(SR_MISC+6),.width(8), .at_reset(8'b0001_1110)) sr_led_src - (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp), .in(set_data_dsp),.out(led_src),.changed()); - - assign leds = (led_src & led_hw) | (~led_src & led_sw); - - // ///////////////////////////////////////////////////////////////////////// - // Interrupt Controller, Slave #8 - - assign irq= {{8'b0}, - {uart_tx_int[3:0], uart_rx_int[3:0]}, - {4'b0, clk_status, 3'b0}, - {3'b0, PHY_INTn,i2c_int,spi_int,2'b00}}; - - pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), - .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), - .irq(irq) ); - - // ///////////////////////////////////////////////////////////////////////// - // UART, Slave #10 - - quad_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), - .adr_i(sa_adr[6:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), - .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), - .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); - // ///////////////////////////////////////////////////////////////////////// - // ICAP for reprogramming the FPGA, Slave #13 (D) - - s3a_icap_wb s3a_icap_wb - (.clk(wb_clk), .reset(wb_rst), .cyc_i(sd_cyc), .stb_i(sd_stb), - .we_i(sd_we), .ack_o(sd_ack), .dat_i(sd_dat_o), .dat_o(sd_dat_i)); - - // ///////////////////////////////////////////////////////////////////////// - // SPI for Flash -- Slave #14 (E) - spi_top flash_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(se_adr[4:0]),.wb_dat_i(se_dat_o), - .wb_dat_o(se_dat_i),.wb_sel_i(se_sel),.wb_we_i(se_we),.wb_stb_i(se_stb), - .wb_cyc_i(se_cyc),.wb_ack_o(se_ack),.wb_err_o(se_err),.wb_int_o(spiflash_int), - .ss_pad_o(spiflash_cs), - .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) ); - - // ///////////////////////////////////////////////////////////////////////// - // ADC Frontend - wire [23:0] rx_fe_i, rx_fe_q; - - rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a), - .adc_b({adc_b,2'b00}),.adc_ovf_b(adc_ovf_b), - .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx0_d1 | run_rx1_d1), .debug()); - - // ///////////////////////////////////////////////////////////////////////// - // DSP RX 0 - wire [31:0] sample_rx0; - wire strobe_rx0, clear_rx0; - - always @(posedge dsp_clk) - run_rx0_d1 <= run_rx0; - - ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0 - (.clk(dsp_clk), .rst(dsp_rst), .clr(clear_rx0), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), - .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), - .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), - .debug() ); - - vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE), .DSP_NUMBER(0)) vita_rx_chain0 - (.clk(dsp_clk), .reset(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), - .vita_time(vita_time), .overrun(overrun0), - .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), .clear_o(clear_rx0), - .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o), - .debug() ); - - // ///////////////////////////////////////////////////////////////////////// - // DSP RX 1 - wire [31:0] sample_rx1; - wire strobe_rx1, clear_rx1; - - always @(posedge dsp_clk) - run_rx1_d1 <= run_rx1; - - ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1 - (.clk(dsp_clk), .rst(dsp_rst), .clr(clear_rx1), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), - .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), - .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), - .debug() ); - - vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE), .DSP_NUMBER(1)) vita_rx_chain1 - (.clk(dsp_clk), .reset(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), - .vita_time(vita_time), .overrun(overrun1), - .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), .clear_o(clear_rx1), - .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o), - .debug() ); - - // /////////////////////////////////////////////////////////////////////////////////// - // DSP TX - - wire [35:0] tx_data; - wire tx_src_rdy, tx_dst_rdy; - wire [31:0] debug_vt; - wire clear_tx; - - assign RAM_A[20:18] = 3'b0; - - ext_fifo #(.EXT_WIDTH(36),.INT_WIDTH(36),.RAM_DEPTH(18),.FIFO_DEPTH(18)) - ext_fifo_i1 - (.int_clk(dsp_clk), - .ext_clk(dsp_clk), - .rst(dsp_rst | clear_tx), - .RAM_D_pi(RAM_D_pi), - .RAM_D_po(RAM_D_po), - .RAM_D_poe(RAM_D_poe), - .RAM_A(RAM_A[17:0]), - .RAM_WEn(RAM_WEn), - .RAM_CENn(RAM_CENn), - .RAM_LDn(RAM_LDn), - .RAM_OEn(RAM_OEn), - .RAM_CE1n(RAM_CE1n), - .datain(rd1_dat), - .src_rdy_i(rd1_ready_o), - .dst_rdy_o(rd1_ready_i), - .dataout(tx_data), - .src_rdy_o(tx_src_rdy), - .dst_rdy_i(tx_dst_rdy), - .debug(debug_extfifo), - .debug2(debug_extfifo2) ); - - wire [23:0] tx_fe_i, tx_fe_q; - wire [31:0] sample_tx; - wire strobe_tx; - - vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(DSP_TX_FIFOSIZE), - .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), - .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), - .DSP_NUMBER(0)) - vita_tx_chain - (.clk(dsp_clk), .reset(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), - .vita_time(vita_time), - .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), - .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), - .sample(sample_tx), .strobe(strobe_tx), - .underrun(underrun), .run(run_tx), .clear_o(clear_tx), - .debug(debug_vt)); - - duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain - (.clk(dsp_clk),.rst(dsp_rst), .clr(clear_tx), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), - .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .debug() ); - - tx_frontend #(.BASE(SR_TX_FRONT)) tx_frontend - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1), - .dac_a(dac_a), .dac_b(dac_b)); - - // /////////////////////////////////////////////////////////////////////////////////// - // SERDES - - serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes - (.clk(dsp_clk),.rst(dsp_rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd0_dat[31:0]),.rd_flags_i(rd0_dat[35:32]),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr0_dat[31:0]),.wr_flags_o(wr0_dat[35:32]),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), - .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), - .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), - .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - - // ///////////////////////////////////////////////////////////////////////// - // VITA Timing - - wire [31:0] debug_sync; - - time_64bit #(.BASE(SR_TIME64)) time_64bit - (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), - .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), .good_sync(good_sync), .debug(debug_sync)); - - // ///////////////////////////////////////////////////////////////////////////////////////// - // Debug Pins - - assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; - assign debug = 32'd0; - assign debug_gpio_0 = 32'd0; - assign debug_gpio_1 = 32'd0; - -endmodule // u2_core diff --git a/fpga/usrp2/top/USRP2/.gitignore b/fpga/usrp2/top/USRP2/.gitignore deleted file mode 100644 index f50a2b7e5..000000000 --- a/fpga/usrp2/top/USRP2/.gitignore +++ /dev/null @@ -1,57 +0,0 @@ -/*.ptwx -/*.xrpt -/*.zip -/*_xdb -/templates -/netgen -/_ngo -/_xmsgs -/_pace.ucf -/*.cmd -/*.ibs -/*.lfp -/*.mfp -/*.bit -/*.bin -/*.stx -/*.par -/*.unroutes -/*.ntrc_log -/*.ngr -/*.mrp -/*.html -/*.lso -/*.twr -/*.bld -/*.ncd -/*.txt -/*.cmd_log -/*.drc -/*.map -/*.twr -/*.xml -/*.syr -/*.ngm -/*.xst -/*.csv -/*.html -/*.lock -/*.ncd -/*.twx -/*.ise_ISE_Backup -/*.xml -/*.ut -/*.xpi -/*.ngd -/*.ncd -/*.pad -/*.bgn -/*.ngc -/*.pcf -/*.ngd -/xst -/*.log -/*.rpt -/*.cel -/*.restore -/build* diff --git a/fpga/usrp2/top/USRP2/Makefile b/fpga/usrp2/top/USRP2/Makefile deleted file mode 100644 index 94480a811..000000000 --- a/fpga/usrp2/top/USRP2/Makefile +++ /dev/null @@ -1,104 +0,0 @@ -# -# Copyright 2008-2012 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u2_rev3 -BUILD_DIR = $(abspath build) - -# set me in a custom makefile -CUSTOM_SRCS = -CUSTOM_DEFS = - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../extramfifo/Makefile.srcs - - -################################################## -# Project Properties -################################################## -PROJECT_PROPERTIES = \ -family Spartan3 \ -device xc3s2000 \ -package fg456 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -u2_core.v \ -u2_rev3.v \ -u2_rev3.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto \ -"Verilog Macros" "FIFO_CTRL_NO_TIME=1 $(CUSTOM_DEFS)" - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Generate Detailed MAP Report" TRUE \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/USRP2/u2_core.v b/fpga/usrp2/top/USRP2/u2_core.v deleted file mode 100644 index aed69a9bd..000000000 --- a/fpga/usrp2/top/USRP2/u2_core.v +++ /dev/null @@ -1,771 +0,0 @@ -// -// Copyright 2011-2013 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// //////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_core -// //////////////////////////////////////////////////////////////////////////////// - -module u2_core - (// Clocks - input dsp_clk, - input wb_clk, - output clock_ready, - input clk_to_mac, - input pps_in, - - // Misc, debug - output [7:0] leds, - output [31:0] debug, - output [1:0] debug_clk, - - // Expansion - input exp_time_in, - output exp_time_out, - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output [7:0] GMII_TXD, - output GMII_TX_EN, - output GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output [15:0] ser_t, - output ser_tklsb, - output ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, - output cpld_mode, - output cpld_done, - input cpld_din, - input cpld_clk, - input cpld_detached, - output cpld_misc, - input cpld_init_b, - input por, - output config_success, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_on_a, - output adc_oe_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_on_b, - output adc_oe_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - - // I2C - input scl_pad_i, - output scl_pad_o, - output scl_pad_oen_o, - input sda_pad_i, - output sda_pad_o, - output sda_pad_oen_o, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Generic SPI - output sclk, - output mosi, - input miso, - output sen_clk, - output sen_dac, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output sen_rx_db, - output sen_rx_adc, - output sen_rx_dac, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx, - - // External RAM - input [17:0] RAM_D_pi, - output [17:0] RAM_D_po, - output RAM_D_poe, - output [18:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn, - - // Debug stuff - output uart_tx_o, - input uart_rx_i, - output uart_baud_o, - input sim_mode, - input [3:0] clock_divider - ); - - localparam SR_MISC = 0; // 7 regs - localparam SR_USER_REGS = 8; // 2 - localparam SR_TIME64 = 10; // 6 - localparam SR_BUF_POOL = 16; // 4 - localparam SR_SPI_CORE = 20; // 3 - localparam SR_RX_FRONT = 24; // 5 - localparam SR_RX_CTRL0 = 32; // 9 - localparam SR_RX_DSP0 = 48; // 7 - localparam SR_RX_CTRL1 = 80; // 9 - localparam SR_RX_DSP1 = 96; // 7 - - localparam SR_TX_FRONT = 128; // ? - localparam SR_TX_CTRL = 144; // 6 - localparam SR_TX_DSP = 160; // 5 - - localparam SR_GPIO = 184; // 5 - localparam SR_UDP_SM = 192; // 64 - - // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 - // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs - // localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo - localparam DSP_RX_FIFOSIZE = 10; - localparam DSP_TX_FIFOSIZE = 10; - localparam ETH_TX_FIFOSIZE = 9; - localparam ETH_RX_FIFOSIZE = 11; - localparam SERDES_TX_FIFOSIZE = 9; - localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? - - wire [7:0] set_addr, set_addr_dsp, set_addr_user; - wire [31:0] set_data, set_data_dsp, set_data_user; - wire set_stb, set_stb_dsp, set_stb_user; - - wire ram_loader_done, ram_loader_rst; - wire wb_rst; - wire dsp_rst = wb_rst; - - wire [31:0] status; - wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; - wire proc_int, overrun0, overrun1, underrun; - wire uart_tx_int, uart_rx_int; - - wire [31:0] debug_gpio_0, debug_gpio_1; - - wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; - - wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; - wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; - wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; - - wire serdes_link_up, good_sync; - wire epoch; - wire [31:0] irq; - wire [63:0] vita_time, vita_time_pps; - - wire run_rx0, run_rx1, run_tx; - reg run_rx0_d1, run_rx1_d1; - - // /////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - localparam dw = 32; // Data bus width - localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m0_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, - s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, - sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o; - wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; - wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; - wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; - wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; - wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; - wire m0_err, m0_rty; - wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; - - wb_1master #(.decode_w(8), - .s0_addr(8'b0000_0000),.s0_mask(8'b1100_0000), // Main RAM (0-16K) - .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // Packet Router (16-20K) - .s2_addr(8'b0101_0000),.s2_mask(8'b1111_1100), // SPI - .s3_addr(8'b0101_0100),.s3_mask(8'b1111_1100), // I2C - .s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100), // Unused - .s5_addr(8'b0101_1100),.s5_mask(8'b1111_1100), // Readback - .s6_addr(8'b0110_0000),.s6_mask(8'b1111_0000), // Ethernet MAC - .s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000), // Settings Bus (only uses 1K) - .s8_addr(8'b1000_0000),.s8_mask(8'b1111_1100), // PIC - .s9_addr(8'b1000_0100),.s9_mask(8'b1111_1100), // Unused - .sa_addr(8'b1000_1000),.sa_mask(8'b1111_1100), // UART - .sb_addr(8'b1000_1100),.sb_mask(8'b1111_1100), // Unused - .sc_addr(8'b1001_0000),.sc_mask(8'b1111_0000), // Unused - .sd_addr(8'b1010_0000),.sd_mask(8'b1111_0000), // Unused - .se_addr(8'b1011_0000),.se_mask(8'b1111_0000), // Unused - .sf_addr(8'b1100_0000),.sf_mask(8'b1100_0000), // Unused - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), - .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), - .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), - .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), - .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), - .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), - .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), - .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), - .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), - .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), - .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), - .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), - .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), - .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), - .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); - - assign s2_ack = 0; - assign s4_ack = 0; - assign s9_ack = 0; - assign sb_ack = 0; - assign sc_ack = 0; - assign sd_ack = 0; - assign se_ack = 0; - assign sf_ack = 0; - - // //////////////////////////////////////////////////////////////////////////////////////// - // Reset Controller - system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), - .ram_loader_rst_o(ram_loader_rst), - .wb_rst_o(wb_rst), - .ram_loader_done_i(ram_loader_done)); - - assign config_success = ram_loader_done; - reg takeover = 0; - - wire cpld_start_int, cpld_mode_int, cpld_done_int; - - always @(posedge wb_clk) - if(ram_loader_done) - takeover = 1; - assign cpld_misc = ~takeover; - - wire sd_clk, sd_csn, sd_mosi, sd_miso; - - assign sd_miso = cpld_din; - assign cpld_start = takeover ? sd_clk : cpld_start_int; - assign cpld_mode = takeover ? sd_csn : cpld_mode_int; - assign cpld_done = takeover ? sd_mosi : cpld_done_int; - - // /////////////////////////////////////////////////////////////////// - // RAM Loader - - wire [31:0] ram_loader_dat; - wire [15:0] ram_loader_adr; - wire [3:0] ram_loader_sel; - wire ram_loader_stb, ram_loader_we; - ram_loader #(.AWIDTH(aw),.RAM_SIZE(16384)) - ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst), - .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr), - .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel), - .wb_we(ram_loader_we), - .ram_loader_done(ram_loader_done), - // CPLD Interface - .cpld_clk(cpld_clk), - .cpld_din(cpld_din), - .cpld_start(cpld_start_int), - .cpld_mode(cpld_mode_int), - .cpld_done(cpld_done_int), - .cpld_detached(cpld_detached)); - - // ///////////////////////////////////////////////////////////////////////// - // Processor - - assign bus_error = m0_err | m0_rty; - - wire [63:0] zpu_status; - zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) - zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(ram_loader_done), - // Data Wishbone bus to system bus fabric - .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), - .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), - // Interrupts and exceptions - .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); - - // ///////////////////////////////////////////////////////////////////////// - // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone - // I-port connects directly to processor and ram loader - - ram_harvard #(.AWIDTH(14),.RAM_SIZE(16384),.ICWIDTH(7),.DCWIDTH(6)) - sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - - .ram_loader_adr_i(ram_loader_adr[13:0]), .ram_loader_dat_i(ram_loader_dat), - .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), - .ram_loader_we_i(ram_loader_we), - .ram_loader_done_i(ram_loader_done), - - .if_adr(16'b0), .if_data(), - - .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool, slave #1 - wire rd0_ready_i, rd0_ready_o; - wire rd1_ready_i, rd1_ready_o; - wire rd2_ready_i, rd2_ready_o; - wire rd3_ready_i, rd3_ready_o; - wire [35:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_ready_i, wr0_ready_o; - wire wr1_ready_i, wr1_ready_o; - wire wr2_ready_i, wr2_ready_o; - wire wr3_ready_i, wr3_ready_o; - wire [35:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - wire [35:0] sfc_wr_data, sfc_rd_data; - wire sfc_wr_ready, sfc_rd_ready; - wire sfc_wr_valid, sfc_rd_valid; - - wire [35:0] tx_err_data; - wire tx_err_src_rdy, tx_err_dst_rdy; - - wire [31:0] router_debug; - - packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), - - .status(status), .sys_int_o(buffer_int), .debug(router_debug), - - .ser_inp_data(wr0_dat), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), - .dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o), - .dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o), - .eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), - .err_inp_data(tx_err_data), .err_inp_valid(tx_err_src_rdy), .err_inp_ready(tx_err_dst_rdy), - .ctl_inp_data(sfc_wr_data), .ctl_inp_valid(sfc_wr_valid), .ctl_inp_ready(sfc_wr_ready), - - .ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), - .dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), - .ctl_out_data(sfc_rd_data), .ctl_out_valid(sfc_rd_valid), .ctl_out_ready(sfc_rd_ready), - .eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) - ); - - // ///////////////////////////////////////////////////////////////////////// - // SPI -- Slave #2 - wire [31:0] spi_debug; - wire [31:0] spi_readback; - wire spi_ready; - simple_spi_core #(.BASE(SR_SPI_CORE), .WIDTH(8)) shared_spi( - .clock(dsp_clk), .reset(dsp_rst), - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .readback(spi_readback), .ready(spi_ready), - .sen({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk(sclk), .mosi(mosi), .miso(miso), .debug(spi_debug) - ); - - // ///////////////////////////////////////////////////////////////////////// - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_dat_i[31:8] = 24'd0; - - // ///////////////////////////////////////////////////////////////////////// - // GPIOs - - wire [31:0] gpio_readback; - - gpio_atr #(.BASE(SR_GPIO), .WIDTH(32)) - gpio_atr(.clk(dsp_clk),.reset(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .rx(run_rx0_d1 | run_rx1_d1), .tx(run_tx), - .gpio({io_tx,io_rx}), .gpio_readback(gpio_readback) ); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool Status -- Slave #5 - - //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd10, 16'd1}; //major, minor - - wire [31:0] irq_readback = {19'b0, spi_ready, clk_status, serdes_link_up, 10'b0}; - - wb_readback_mux buff_pool_status - (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), - .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - - .word00(spi_readback),.word01(32'hffff_ffff),.word02(32'hffff_ffff),.word03(32'hffff_ffff), - .word04(32'hffff_ffff),.word05(32'hffff_ffff),.word06(32'hffff_ffff),.word07(32'hffff_ffff), - .word08(status),.word09(gpio_readback),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(compat_num),.word13(irq_readback), - .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]) - ); - - // ///////////////////////////////////////////////////////////////////////// - // Ethernet MAC Slave #6 - - simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), - .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper - (.clk125(clk_to_mac), .reset(wb_rst), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .sys_clk(dsp_clk), - .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), - .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), - .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), - .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), - .mdio(MDIO), .mdc(MDC), - .debug(debug_mac)); - - // ///////////////////////////////////////////////////////////////////////// - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_dat_i = 32'd0; - - wire set_stb_dsp0, set_stb_dsp1; - wire [31:0] set_data_dsp0, set_data_dsp1; - wire [7:0] set_addr_dsp0, set_addr_dsp1; - - //mux settings_bus_crossclock and settings_readback_bus_fifo_ctrl with prio - assign set_stb_dsp = set_stb_dsp0 | set_stb_dsp1; - assign set_addr_dsp = set_stb_dsp1? set_addr_dsp1 : set_addr_dsp0; - assign set_data_dsp = set_stb_dsp1? set_data_dsp1 : set_data_dsp0; - - settings_bus_crossclock #(.FLOW_CTRL(1/*on*/)) settings_bus_crossclock - (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), - .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp0), .set_addr_o(set_addr_dsp0), .set_data_o(set_data_dsp0), - .blocked(set_stb_dsp1)); - - user_settings #(.BASE(SR_USER_REGS)) user_settings - (.clk(dsp_clk),.rst(dsp_rst),.set_stb(set_stb_dsp), - .set_addr(set_addr_dsp),.set_data(set_data_dsp), - .set_addr_user(set_addr_user),.set_data_user(set_data_user), - .set_stb_user(set_stb_user) ); - - // ///////////////////////////////////////////////////////////////////////// - // Settings + Readback Bus -- FIFO controlled - - wire [31:0] sfc_debug; - wire sfc_clear; - /* - settings_fifo_ctrl #(.PROT_DEST(3), .PROT_HDR(1)) sfc - ( - .clock(dsp_clk), .reset(dsp_rst), .clear(sfc_clear), - .vita_time(vita_time), .perfs_ready(spi_ready), - .in_data(sfc_rd_data), .in_valid(sfc_rd_valid), .in_ready(sfc_rd_ready), - .out_data(sfc_wr_data), .out_valid(sfc_wr_valid), .out_ready(sfc_wr_ready), - .strobe(set_stb_dsp1), .addr(set_addr_dsp1), .data(set_data_dsp1), - .word00(spi_readback),.word01(32'hffff_ffff),.word02(32'hffff_ffff),.word03(32'hffff_ffff), - .word04(32'hffff_ffff),.word05(32'hffff_ffff),.word06(32'hffff_ffff),.word07(32'hffff_ffff), - .word08(32'hffff_ffff),.word09(gpio_readback),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(32'hffff_ffff),.word13(irq_readback), - .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]), - .debug(sfc_debug) - ); - */ - assign sfc_debug = 0; - assign set_stb_dsp1 = 0; - assign set_addr_dsp1 = 0; - assign set_data_dsp1 = 0; - assign sfc_rd_ready = 1; - assign sfc_wr_valid = 0; - assign sfc_wr_data = 0; - - setting_reg #(.my_addr(SR_BUF_POOL+1/*same as packet dispatcher*/),.width(1)) sr_clear_sfc - (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.changed(sfc_clear)); - - // Output control lines - wire [7:0] clock_outs, serdes_outs, adc_outs; - assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; - assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; - assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; - - wire phy_reset; - assign PHY_RESETn = ~phy_reset; - - setting_reg #(.my_addr(SR_MISC+0),.width(8)) sr_clk - (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),.in(set_data),.out(clock_outs),.changed()); - - setting_reg #(.my_addr(SR_MISC+1),.width(8)) sr_ser - (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(serdes_outs),.changed()); - - setting_reg #(.my_addr(SR_MISC+2),.width(8)) sr_adc - (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(adc_outs),.changed()); - - setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy - (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(phy_reset),.changed()); - - // ///////////////////////////////////////////////////////////////////////// - // LEDS - // register 8 determines whether leds are controlled by SW or not - // 1 = controlled by HW, 0 = by SW - // In Rev3 there are only 6 leds, and the highest one is on the ETH connector - - wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {run_tx, (run_rx0_d1 | run_rx1_d1), clk_status, serdes_link_up & good_sync, 1'b0}; - - setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led - (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(led_sw),.changed()); - - setting_reg #(.my_addr(SR_MISC+6),.width(8), .at_reset(8'b0001_1110)) sr_led_src - (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp), .in(set_data_dsp),.out(led_src),.changed()); - - assign leds = (led_src & led_hw) | (~led_src & led_sw); - - // ///////////////////////////////////////////////////////////////////////// - // Interrupt Controller, Slave #8 - - assign irq= {{8'b0}, - {3'b0, uart_tx_int, 2'b0, uart_rx_int}, - {4'b0, clk_status, 3'b0}, - {3'b0, PHY_INTn,i2c_int,spi_int,2'b00}}; - - pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), - .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), - .irq(irq) ); - - // ///////////////////////////////////////////////////////////////////////// - // UART, Slave #10 - - simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), - .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), - .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), - .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); - - // ///////////////////////////////////////////////////////////////////////// - // ADC Frontend - wire [23:0] rx_fe_i, rx_fe_q; - - rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a), - .adc_b({adc_b,2'b00}),.adc_ovf_b(adc_ovf_b), - .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx0_d1 | run_rx1_d1), .debug()); - - // ///////////////////////////////////////////////////////////////////////// - // DSP RX 0 - wire [31:0] sample_rx0; - wire strobe_rx0, clear_rx0; - - always @(posedge dsp_clk) - run_rx0_d1 <= run_rx0; - - ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0 - (.clk(dsp_clk), .rst(dsp_rst), .clr(clear_rx0), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), - .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), - .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), - .debug() ); - - vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE), .DSP_NUMBER(0)) vita_rx_chain0 - (.clk(dsp_clk), .reset(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), - .vita_time(vita_time), .overrun(overrun0), - .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), .clear_o(clear_rx0), - .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o), - .debug() ); - - // ///////////////////////////////////////////////////////////////////////// - // DSP RX 1 - wire [31:0] sample_rx1; - wire strobe_rx1, clear_rx1; - - always @(posedge dsp_clk) - run_rx1_d1 <= run_rx1; - - ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1 - (.clk(dsp_clk), .rst(dsp_rst), .clr(clear_rx1), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), - .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), - .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), - .debug() ); - - vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE), .DSP_NUMBER(1)) vita_rx_chain1 - (.clk(dsp_clk), .reset(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), - .vita_time(vita_time), .overrun(overrun1), - .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), .clear_o(clear_rx1), - .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o), - .debug() ); - - // /////////////////////////////////////////////////////////////////////////////////// - // DSP TX - - wire [35:0] tx_data; - wire tx_src_rdy, tx_dst_rdy; - wire [31:0] debug_vt; - wire clear_tx; - - ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) - ext_fifo_i1 - (.int_clk(dsp_clk), - .ext_clk(clk_to_mac), - .rst(dsp_rst | clear_tx), - .RAM_D_pi(RAM_D_pi), - .RAM_D_po(RAM_D_po), - .RAM_D_poe(RAM_D_poe), - .RAM_A(RAM_A), - .RAM_WEn(RAM_WEn), - .RAM_CENn(RAM_CENn), - .RAM_LDn(RAM_LDn), - .RAM_OEn(RAM_OEn), - .RAM_CE1n(RAM_CE1n), - .datain(rd1_dat), - .src_rdy_i(rd1_ready_o), - .dst_rdy_o(rd1_ready_i), - .dataout(tx_data), - .src_rdy_o(tx_src_rdy), - .dst_rdy_i(tx_dst_rdy), - .debug(debug_extfifo), - .debug2(debug_extfifo2) ); - - wire [23:0] tx_fe_i, tx_fe_q; - wire [31:0] sample_tx; - wire strobe_tx; - - vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(DSP_TX_FIFOSIZE), - .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), - .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), - .DSP_NUMBER(0)) - vita_tx_chain - (.clk(dsp_clk), .reset(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), - .vita_time(vita_time), - .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), - .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), - .sample(sample_tx), .strobe(strobe_tx), - .underrun(underrun), .run(run_tx), .clear_o(clear_tx), - .debug(debug_vt)); - - duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain - (.clk(dsp_clk),.rst(dsp_rst), .clr(clear_tx), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), - .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .debug() ); - - tx_frontend #(.BASE(SR_TX_FRONT)) tx_frontend - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1), - .dac_a(dac_a), .dac_b(dac_b)); - - // /////////////////////////////////////////////////////////////////////////////////// - // SERDES - - serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes - (.clk(dsp_clk),.rst(dsp_rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd0_dat[31:0]),.rd_flags_i(rd0_dat[35:32]),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr0_dat[31:0]),.wr_flags_o(wr0_dat[35:32]),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), - .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), - .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), - .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - - assign RAM_CLK = clk_to_mac; - - // ///////////////////////////////////////////////////////////////////////// - // VITA Timing - - wire [31:0] debug_sync; - - time_64bit #(.BASE(SR_TIME64)) time_64bit - (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), - .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), .good_sync(good_sync), .debug(debug_sync)); - - // ///////////////////////////////////////////////////////////////////////////////////////// - // Debug Pins - - assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; - assign debug = 32'd0; - assign debug_gpio_0 = 32'd0; - assign debug_gpio_1 = 32'd0; - -endmodule // u2_core diff --git a/fpga/usrp2/top/USRP2/u2_rev3.ucf b/fpga/usrp2/top/USRP2/u2_rev3.ucf deleted file mode 100644 index 8017f61ff..000000000 --- a/fpga/usrp2/top/USRP2/u2_rev3.ucf +++ /dev/null @@ -1,336 +0,0 @@ -NET "leds[0]" LOC = "E8" ; -NET "leds[1]" LOC = "F7" ; -NET "leds[2]" LOC = "E5" ; -NET "leds[3]" LOC = "B7" ; -NET "leds[4]" LOC = "C11" ; -NET "leds[5]" LOC = "AB19" ; -NET "debug[0]" LOC = "N5" ; -NET "debug[1]" LOC = "N6" ; -NET "debug[2]" LOC = "P1" ; -NET "debug[3]" LOC = "P2" ; -NET "debug[4]" LOC = "P4" ; -NET "debug[5]" LOC = "P5" ; -NET "debug[6]" LOC = "R1" ; -NET "debug[7]" LOC = "R2" ; -NET "debug[8]" LOC = "P6" ; -NET "debug[9]" LOC = "R5" ; -NET "debug[10]" LOC = "R4" ; -NET "debug[11]" LOC = "T3" ; -NET "debug[12]" LOC = "U3" ; -NET "debug[13]" LOC = "M2" ; -NET "debug[14]" LOC = "M3" ; -NET "debug[15]" LOC = "M4" ; -NET "debug[16]" LOC = "M5" ; -NET "debug[17]" LOC = "M6" ; -NET "debug[18]" LOC = "N1" ; -NET "debug[19]" LOC = "N2" ; -NET "debug[20]" LOC = "N3" ; -NET "debug[21]" LOC = "T1" ; -NET "debug[22]" LOC = "T2" ; -NET "debug[23]" LOC = "U2" ; -NET "debug[24]" LOC = "T4" ; -NET "debug[25]" LOC = "U4" ; -NET "debug[26]" LOC = "T5" ; -NET "debug[27]" LOC = "T6" ; -NET "debug[28]" LOC = "U5" ; -NET "debug[29]" LOC = "V5" ; -NET "debug[30]" LOC = "W2" ; -NET "debug[31]" LOC = "W3" ; -NET "debug_clk[0]" LOC = "N4" ; -NET "debug_clk[1]" LOC = "M1" ; -NET "uart_tx_o" LOC = "C7" ; -NET "uart_rx_i" LOC = "A3" ; -NET "exp_time_in_p" LOC = "V3" ; -NET "exp_time_in_n" LOC = "V4" ; -NET "exp_time_out_p" LOC = "V1" ; -NET "exp_time_out_n" LOC = "V2" ; -NET "GMII_COL" LOC = "U16" ; -NET "GMII_CRS" LOC = "U17" ; -NET "GMII_TXD[0]" LOC = "W14" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[1]" LOC = "AA20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[2]" LOC = "AB20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[3]" LOC = "Y18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[4]" LOC = "AA18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[5]" LOC = "AB18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[6]" LOC = "V17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[7]" LOC = "W17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TX_EN" LOC = "Y17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TX_ER" LOC = "V16" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_GTX_CLK" LOC = "AA17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TX_CLK" LOC = "W13" ; -NET "GMII_RXD[0]" LOC = "AA15" ; -NET "GMII_RXD[1]" LOC = "AB15" ; -NET "GMII_RXD[2]" LOC = "U14" ; -NET "GMII_RXD[3]" LOC = "V14" ; -NET "GMII_RXD[4]" LOC = "U13" ; -NET "GMII_RXD[5]" LOC = "V13" ; -NET "GMII_RXD[6]" LOC = "Y13" ; -NET "GMII_RXD[7]" LOC = "AA13" ; -NET "GMII_RX_CLK" LOC = "AA12" ; -NET "GMII_RX_DV" LOC = "AB16" ; -NET "GMII_RX_ER" LOC = "AA16" ; -NET "MDIO" LOC = "Y16" |PULLUP ; -NET "MDC" LOC = "V18" ; -NET "PHY_INTn" LOC = "AB13" ; -NET "PHY_RESETn" LOC = "AA19" ; -NET "PHY_CLK" LOC = "V15" ; -NET "RAM_D[0]" LOC = "N20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[1]" LOC = "N21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[2]" LOC = "N22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[3]" LOC = "M17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[4]" LOC = "M18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[5]" LOC = "M19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[6]" LOC = "M20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[7]" LOC = "M21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[8]" LOC = "M22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[9]" LOC = "Y22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[10]" LOC = "Y21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[11]" LOC = "Y20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[12]" LOC = "Y19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[13]" LOC = "W22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[14]" LOC = "W21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[15]" LOC = "W20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[16]" LOC = "W19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[17]" LOC = "V22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[0]" LOC = "U21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[1]" LOC = "T19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[2]" LOC = "V21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[3]" LOC = "V20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[4]" LOC = "T20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[5]" LOC = "T21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[6]" LOC = "T22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[7]" LOC = "T18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[8]" LOC = "R18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[9]" LOC = "P19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[10]" LOC = "P21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[11]" LOC = "P22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[12]" LOC = "N19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[13]" LOC = "N17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[14]" LOC = "N18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[15]" LOC = "T17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[16]" LOC = "U19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[17]" LOC = "U18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[18]" LOC = "V19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_CE1n" LOC = "U20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_CENn" LOC = "P18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_CLK" LOC = "P17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_WEn" LOC = "R22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_OEn" LOC = "R21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_LDn" LOC = "R19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_enable" LOC = "W11" ; -NET "ser_prbsen" LOC = "AA3" ; -NET "ser_loopen" LOC = "Y4" ; -NET "ser_rx_en" LOC = "AB9" ; -NET "ser_tx_clk" LOC = "U7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[0]" LOC = "V7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[1]" LOC = "V10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[2]" LOC = "AB4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[3]" LOC = "AA4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[4]" LOC = "Y5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[5]" LOC = "W5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[6]" LOC = "AB5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[7]" LOC = "AA5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[8]" LOC = "W6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[9]" LOC = "V6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[10]" LOC = "AA6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[11]" LOC = "Y6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[12]" LOC = "W8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[13]" LOC = "V8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[14]" LOC = "AB8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[15]" LOC = "AA8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_tklsb" LOC = "U10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_tkmsb" LOC = "U11" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_rx_clk" LOC = "AA11" ; -NET "ser_r[0]" LOC = "AB10" ; -NET "ser_r[1]" LOC = "AA10" ; -NET "ser_r[2]" LOC = "U9" ; -NET "ser_r[3]" LOC = "U6" ; -NET "ser_r[4]" LOC = "AB11" ; -NET "ser_r[5]" LOC = "Y7" ; -NET "ser_r[6]" LOC = "W7" ; -NET "ser_r[7]" LOC = "AB7" ; -NET "ser_r[8]" LOC = "AA7" ; -NET "ser_r[9]" LOC = "W9" ; -NET "ser_r[10]" LOC = "W10" ; -NET "ser_r[11]" LOC = "Y1" ; -NET "ser_r[12]" LOC = "Y3" ; -NET "ser_r[13]" LOC = "Y2" ; -NET "ser_r[14]" LOC = "W4" ; -NET "ser_r[15]" LOC = "W1" ; -NET "ser_rklsb" LOC = "V9" ; -NET "ser_rkmsb" LOC = "Y10" ; -NET "cpld_start" LOC = "AA9" ; -NET "cpld_mode" LOC = "U12" ; -NET "cpld_done" LOC = "V12" ; -NET "cpld_din" LOC = "AA14" ; -NET "cpld_clk" LOC = "AB14" ; -NET "cpld_detached" LOC = "V11" ; -NET "cpld_init_b" LOC = "W12" ; -NET "cpld_misc" LOC = "Y12" ; -NET "POR" LOC = "W18" ; -NET "WDI" LOC = "W15" ; -NET "adc_a[0]" LOC = "A14" | IOBDELAY= "NONE" ; -NET "adc_a[1]" LOC = "B14" | IOBDELAY= "NONE" ; -NET "adc_a[2]" LOC = "C13" | IOBDELAY= "NONE" ; -NET "adc_a[3]" LOC = "D13" | IOBDELAY= "NONE" ; -NET "adc_a[4]" LOC = "A13" | IOBDELAY= "NONE" ; -NET "adc_a[5]" LOC = "B13" | IOBDELAY= "NONE" ; -NET "adc_a[6]" LOC = "E12" | IOBDELAY= "NONE" ; -NET "adc_a[7]" LOC = "C22" | IOBDELAY= "NONE" ; -NET "adc_a[8]" LOC = "C20" | IOBDELAY= "NONE" ; -NET "adc_a[9]" LOC = "C21" | IOBDELAY= "NONE" ; -NET "adc_a[10]" LOC = "D20" | IOBDELAY= "NONE" ; -NET "adc_a[11]" LOC = "D19" | IOBDELAY= "NONE" ; -NET "adc_a[12]" LOC = "D21" | IOBDELAY= "NONE" ; -NET "adc_a[13]" LOC = "E18" | IOBDELAY= "NONE" ; -NET "adc_ovf_a" LOC = "F18" ; -NET "adc_oen_a" LOC = "E19" ; -NET "adc_pdn_a" LOC = "E20" ; -NET "adc_b[0]" LOC = "A12" | IOBDELAY= "NONE"; -NET "adc_b[1]" LOC = "E16" | IOBDELAY= "NONE" ; -NET "adc_b[2]" LOC = "F12" | IOBDELAY= "NONE" ; -NET "adc_b[3]" LOC = "F13" | IOBDELAY= "NONE" ; -NET "adc_b[4]" LOC = "F16" | IOBDELAY= "NONE" ; -NET "adc_b[5]" LOC = "F17" | IOBDELAY= "NONE" ; -NET "adc_b[6]" LOC = "C19" | IOBDELAY= "NONE" ; -NET "adc_b[7]" LOC = "B20" | IOBDELAY= "NONE" ; -NET "adc_b[8]" LOC = "B19" | IOBDELAY= "NONE" ; -NET "adc_b[9]" LOC = "C18" | IOBDELAY= "NONE" ; -NET "adc_b[10]" LOC = "D18" | IOBDELAY= "NONE" ; -NET "adc_b[11]" LOC = "B18" | IOBDELAY= "NONE" ; -NET "adc_b[12]" LOC = "D17" | IOBDELAY= "NONE" ; -NET "adc_b[13]" LOC = "E17" | IOBDELAY= "NONE" ; -NET "adc_ovf_b" LOC = "B17" ; -NET "adc_oen_b" LOC = "C17" ; -NET "adc_pdn_b" LOC = "D15" ; -NET "dac_a[0]" LOC = "A5" ; -NET "dac_a[1]" LOC = "B5" ; -NET "dac_a[2]" LOC = "C5" ; -NET "dac_a[3]" LOC = "D5" ; -NET "dac_a[4]" LOC = "A4" ; -NET "dac_a[5]" LOC = "B4" ; -NET "dac_a[6]" LOC = "F6" ; -NET "dac_a[7]" LOC = "D10" ; -NET "dac_a[8]" LOC = "D9" ; -NET "dac_a[9]" LOC = "A10" ; -NET "dac_a[10]" LOC = "L2" ; -NET "dac_a[11]" LOC = "L4" ; -NET "dac_a[12]" LOC = "L3" ; -NET "dac_a[13]" LOC = "L6" ; -NET "dac_a[14]" LOC = "L5" ; -NET "dac_a[15]" LOC = "K2" ; -NET "dac_b[0]" LOC = "D11" ; -NET "dac_b[1]" LOC = "E11" ; -NET "dac_b[2]" LOC = "F11" ; -NET "dac_b[3]" LOC = "B10" ; -NET "dac_b[4]" LOC = "C10" ; -NET "dac_b[5]" LOC = "E10" ; -NET "dac_b[6]" LOC = "F10" ; -NET "dac_b[7]" LOC = "A9" ; -NET "dac_b[8]" LOC = "B9" ; -NET "dac_b[9]" LOC = "E9" ; -NET "dac_b[10]" LOC = "F9" ; -NET "dac_b[11]" LOC = "A8" ; -NET "dac_b[12]" LOC = "B8" ; -NET "dac_b[13]" LOC = "D7" ; -NET "dac_b[14]" LOC = "E7" ; -NET "dac_b[15]" LOC = "B6" ; -NET "dac_lock" LOC = "D6" ; -NET "SCL" LOC = "A7" ; -NET "SDA" LOC = "D8" ; -NET "clk_en[0]" LOC = "C4" ; -NET "clk_en[1]" LOC = "D1" ; -NET "clk_sel[0]" LOC = "C3" ; -NET "clk_sel[1]" LOC = "C2" ; -NET "clk_func" LOC = "C12" ; -NET "clk_status" LOC = "B12" ; -NET "clk_fpga_p" LOC = "A11" ; -NET "clk_fpga_n" LOC = "B11" ; -NET "clk_to_mac" LOC = "AB12" ; -NET "pps_in" LOC = "K1" ; -NET "sclk" LOC = "K5" ; -NET "sen_clk" LOC = "K6" ; -NET "sen_dac" LOC = "L1" ; -NET "sdi" LOC = "J1" ; -NET "sdo" LOC = "J2" ; -NET "sen_tx_db" LOC = "C1" ; -NET "sclk_tx_db" LOC = "D3" ; -NET "sdo_tx_db" LOC = "G3" ; -NET "sdi_tx_db" LOC = "G4" ; -NET "sen_tx_adc" LOC = "G2" ; -NET "sclk_tx_adc" LOC = "H1" ; -NET "sdo_tx_adc" LOC = "H2" ; -NET "sdi_tx_adc" LOC = "J4" ; -NET "sen_tx_dac" LOC = "H4" ; -NET "sclk_tx_dac" LOC = "J5" ; -NET "sdi_tx_dac" LOC = "J6" ; -NET "io_tx[0]" LOC = "K4" ; -NET "io_tx[1]" LOC = "K3" ; -NET "io_tx[2]" LOC = "G1" ; -NET "io_tx[3]" LOC = "G5" ; -NET "io_tx[4]" LOC = "H5" ; -NET "io_tx[5]" LOC = "F3" ; -NET "io_tx[6]" LOC = "F2" ; -NET "io_tx[7]" LOC = "F5" ; -NET "io_tx[8]" LOC = "G6" ; -NET "io_tx[9]" LOC = "E2" ; -NET "io_tx[10]" LOC = "E1" ; -NET "io_tx[11]" LOC = "E3" ; -NET "io_tx[12]" LOC = "F4" ; -NET "io_tx[13]" LOC = "D2" ; -NET "io_tx[14]" LOC = "D4" ; -NET "io_tx[15]" LOC = "E4" ; -NET "sen_rx_db" LOC = "D22" ; -NET "sclk_rx_db" LOC = "F19" ; -NET "sdo_rx_db" LOC = "G20" ; -NET "sdi_rx_db" LOC = "H19" ; -NET "sen_rx_adc" LOC = "H18" ; -NET "sclk_rx_adc" LOC = "J17" ; -NET "sdo_rx_adc" LOC = "H21" ; -NET "sdi_rx_adc" LOC = "H22" ; -NET "sen_rx_dac" LOC = "J18" ; -NET "sclk_rx_dac" LOC = "J19" ; -NET "sdi_rx_dac" LOC = "J21" ; -NET "io_rx[0]" LOC = "L21" ; -NET "io_rx[1]" LOC = "L20" ; -NET "io_rx[2]" LOC = "L19" ; -NET "io_rx[3]" LOC = "L18" ; -NET "io_rx[4]" LOC = "L17" ; -NET "io_rx[5]" LOC = "K22" ; -NET "io_rx[6]" LOC = "K21" ; -NET "io_rx[7]" LOC = "K20" ; -NET "io_rx[8]" LOC = "G22" ; -NET "io_rx[9]" LOC = "G21" ; -NET "io_rx[10]" LOC = "F21" ; -NET "io_rx[11]" LOC = "F20" ; -NET "io_rx[12]" LOC = "G19" ; -NET "io_rx[13]" LOC = "G18" ; -NET "io_rx[14]" LOC = "G17" ; -NET "io_rx[15]" LOC = "E22" ; - -NET "clk_to_mac" TNM_NET = "clk_to_mac"; -TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; - -NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; -TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; - -NET "cpld_clk" TNM_NET = "cpld_clk"; -TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; - -NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; -TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; - -NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; -TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; - -NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE; -NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; - -#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; -#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; -#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; - -#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; -#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; - -TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; diff --git a/fpga/usrp2/top/USRP2/u2_rev3.v b/fpga/usrp2/top/USRP2/u2_rev3.v deleted file mode 100644 index 4b0bb5541..000000000 --- a/fpga/usrp2/top/USRP2/u2_rev3.v +++ /dev/null @@ -1,589 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module u2_rev3 - ( - // Misc, debug - output [5:0] leds, - output [31:0] debug, - output [1:0] debug_clk, - output uart_tx_o, - input uart_rx_i, - - // Expansion - input exp_time_in_p, // Diff - input exp_time_in_n, // Diff - output exp_time_out_p, // Diff - output exp_time_out_n, // Diff - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output reg [7:0] GMII_TXD, - output reg GMII_TX_EN, - output reg GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - input PHY_CLK, // possibly use on-board osc - - // RAM - inout [17:0] RAM_D, - output [18:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - output RAM_CLK, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output reg [15:0] ser_t, - output reg ser_tklsb, - output reg ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, // AA9 - output cpld_mode, // U12 - output cpld_done, // V12 - input cpld_din, // AA14 Now shared with CFG_Din - input cpld_clk, // AB14 serial clock - input cpld_detached,// V11 unused - output cpld_init_b, // W12 unused dual purpose - output cpld_misc, // Y12 - - // Watchdog interface - input POR, - output WDI, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_oen_a, - output adc_pdn_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_oen_b, - output adc_pdn_b, - - // DAC - output reg [15:0] dac_a, - output reg [15:0] dac_b, - input dac_lock, // unused for now - - // I2C - inout SCL, - inout SDA, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Clocks - input clk_fpga_p, // Diff - input clk_fpga_n, // Diff - input clk_to_mac, - input pps_in, - - // Generic SPI - output sclk, - output sen_clk, - output sen_dac, - output sdi, - input sdo, - - // TX DBoard - output sen_tx_db, - output sclk_tx_db, - input sdo_tx_db, - output sdi_tx_db, - - output sen_tx_adc, - output sclk_tx_adc, - input sdo_tx_adc, - output sdi_tx_adc, - - output sen_tx_dac, - output sclk_tx_dac, - output sdi_tx_dac, - - inout [15:0] io_tx, - - // RX DBoard - output sen_rx_db, - output sclk_rx_db, - input sdo_rx_db, - output sdi_rx_db, - - output sen_rx_adc, - output sclk_rx_adc, - input sdo_rx_adc, - output sdi_rx_adc, - - output sen_rx_dac, - output sclk_rx_dac, - output sdi_rx_dac, - - inout [15:0] io_rx - ); - - assign cpld_init_b = 0; - // FPGA-specific pins connections - wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - wire clk90, clk180, clk270; - - // reset the watchdog continuously - reg [15:0] wd; - wire config_success; - - always @(posedge wb_clk) - if(~config_success) - wd <= 0; - else - wd <= wd + 1; - assign WDI = wd[15]; - - wire clk_fpga_unbuf; - - IBUFGDS clk_fpga_pin (.O(clk_fpga_unbuf),.I(clk_fpga_p),.IB(clk_fpga_n)); - BUFG clk_fpga_BUF (.O(clk_fpga),.I(clk_fpga_unbuf)); - - defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - - wire cpld_clock_buf; - BUFG cpld_clock_BUF (.O(cpld_clock_buf),.I(cpld_clock)); - - wire exp_time_in; - IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); - defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; - - wire exp_time_out; - OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); - defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; - - reg [5:0] clock_ready_d; - always @(posedge clk_fpga) - clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; - wire dcm_rst = ~&clock_ready_d & |clock_ready_d; - - wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; - assign adc_oen_a = ~adc_oe_a; - assign adc_oen_b = ~adc_oe_b; - assign adc_pdn_a = ~adc_on_a; - assign adc_pdn_b = ~adc_on_b; - - reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; - reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; - - // ADC A and B are swapped in schematic to facilitate clean layout - always @(posedge dsp_clk) - begin - adc_a_reg1 <= adc_b; - adc_b_reg1 <= adc_a; - adc_ovf_a_reg1 <= adc_ovf_b; - adc_ovf_b_reg1 <= adc_ovf_a; - end - - always @(posedge dsp_clk) - begin - adc_a_reg2 <= adc_a_reg1; - adc_b_reg2 <= adc_b_reg1; - adc_ovf_a_reg2 <= adc_ovf_a_reg1; - adc_ovf_b_reg2 <= adc_ovf_b_reg1; - end // always @ (posedge dsp_clk) - - // Handle Clocks - DCM DCM_INST (.CLKFB(dsp_clk), - .CLKIN(clk_fpga), - .DSSEN(0), - .PSCLK(0), - .PSEN(0), - .PSINCDEC(0), - .RST(dcm_rst), - .CLKDV(clk_div), - .CLKFX(), - .CLKFX180(), - .CLK0(dcm_out), - .CLK2X(), - .CLK2X180(), - .CLK90(clk90), - .CLK180(clk180), - .CLK270(clk270), - .LOCKED(LOCKED_OUT), - .PSDONE(), - .STATUS()); - defparam DCM_INST.CLK_FEEDBACK = "1X"; - defparam DCM_INST.CLKDV_DIVIDE = 2.0; - defparam DCM_INST.CLKFX_DIVIDE = 1; - defparam DCM_INST.CLKFX_MULTIPLY = 4; - defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST.CLKIN_PERIOD = 10.000; - defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; - defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST.FACTORY_JF = 16'h8080; - defparam DCM_INST.PHASE_SHIFT = 0; - defparam DCM_INST.STARTUP_WAIT = "FALSE"; - - BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); - BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - - // I2C -- Don't use external transistors for open drain, the FPGA implements this - IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); - - // LEDs are active low outputs - wire [5:0] leds_int; - assign leds = 6'b011111 ^ leds_int; // all except eth are active-low - - // SPI - wire miso, mosi, sclk_int; - assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; - - assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | - (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | - (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); - - wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; - wire [7:0] GMII_TXD_unreg; - wire GMII_GTX_CLK_int; - - always @(posedge GMII_GTX_CLK_int) - begin - GMII_TX_EN <= GMII_TX_EN_unreg; - GMII_TX_ER <= GMII_TX_ER_unreg; - GMII_TXD <= GMII_TXD_unreg; - end - - OFDDRRSE OFDDRRSE_gmii_inst - (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) - .C0(GMII_GTX_CLK_int), // 0 degree clock input - .C1(~GMII_GTX_CLK_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - - wire ser_tklsb_unreg, ser_tkmsb_unreg; - wire [15:0] ser_t_unreg; - wire ser_tx_clk_int; - - always @(posedge ser_tx_clk_int) - begin - ser_tklsb <= ser_tklsb_unreg; - ser_tkmsb <= ser_tkmsb_unreg; - ser_t <= ser_t_unreg; - end - - assign ser_tx_clk = clk_fpga; - - reg [15:0] ser_r_int; - reg ser_rklsb_int, ser_rkmsb_int; - - wire ser_rx_clk_buf; - BUFG ser_rx_clk_BUF (.O(ser_rx_clk_buf),.I(ser_rx_clk)); - always @(posedge ser_rx_clk_buf) - begin - ser_r_int <= ser_r; - ser_rklsb_int <= ser_rklsb; - ser_rkmsb_int <= ser_rkmsb; - end - - wire [15:0] dac_a_int, dac_b_int; - // DAC A and B are swapped in schematic to facilitate clean layout - // DAC A is also inverted in schematic to facilitate clean layout - always @(posedge dsp_clk) dac_a <= ~dac_b_int; - always @(posedge dsp_clk) dac_b <= dac_a_int; - - /* - OFDDRRSE OFDDRRSE_serdes_inst - (.Q(ser_tx_clk), // Data output (connect directly to top-level port) - .C0(ser_tx_clk_int), // 0 degree clock input - .C1(~ser_tx_clk_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - */ - - wire [17:0] RAM_D_pi; - wire [17:0] RAM_D_po; - wire RAM_D_poe; - - genvar i; - - // - // Instantiate IO for Bidirectional bus to SRAM - // - - generate - for (i=0;i<18;i=i+1) - begin : gen_RAM_D_IO - - IOBUF #( - .DRIVE(12), - .IOSTANDARD("LVCMOS25"), - .SLEW("FAST") - ) - RAM_D_i ( - .O(RAM_D_pi[i]), - .I(RAM_D_po[i]), - .IO(RAM_D[i]), - .T(RAM_D_poe) - ); - end // block: gen_RAM_D_IO - endgenerate - - // - // DCM edits start here - // - - - wire RAM_CLK_buf; - wire clk_to_mac_buf; - wire clk125_ext_clk0; - wire clk125_ext_clk180; - wire clk125_ext_clk0_buf; - wire clk125_ext_clk180_buf; - wire clk125_int_buf; - wire clk125_int; - - IBUFG clk_to_mac_buf_i1 (.I(clk_to_mac), - .O(clk_to_mac_buf)); - - DCM DCM_INST1 (.CLKFB(RAM_CLK_buf), - .CLKIN(clk_to_mac_buf), - .DSSEN(1'b0), - .PSCLK(1'b0), - .PSEN(1'b0), - .PSINCDEC(1'b0), - .RST(1'b0), - .CLK0(clk125_ext_clk0), - .CLK180(clk125_ext_clk180) ); - defparam DCM_INST1.CLK_FEEDBACK = "1X"; - defparam DCM_INST1.CLKDV_DIVIDE = 2.0; - defparam DCM_INST1.CLKFX_DIVIDE = 1; - defparam DCM_INST1.CLKFX_MULTIPLY = 4; - defparam DCM_INST1.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST1.CLKIN_PERIOD = 8.000; - defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "FIXED"; - defparam DCM_INST1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST1.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST1.FACTORY_JF = 16'h8080; - defparam DCM_INST1.PHASE_SHIFT = -64; - defparam DCM_INST1.STARTUP_WAIT = "FALSE"; - - IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), - .O(RAM_CLK_buf)); - BUFG clk125_ext_clk0_buf_i1 (.I(clk125_ext_clk0), - .O(clk125_ext_clk0_buf)); - BUFG clk125_ext_clk180_buf_i1 (.I(clk125_ext_clk180), - .O(clk125_ext_clk180_buf)); - - OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), - .C0(clk125_ext_clk0_buf), - .C1(clk125_ext_clk180_buf), - .CE(1'b1), - .D0(1'b1), - .D1(1'b0), - .R(1'b0), - .S(1'b0)); - -// SRL16 dcm2_rst_i1 (.D(1'b0), -// .CLK(clk_to_mac_buf), -// .Q(dcm2_rst), -// .A0(1'b1), -// .A1(1'b1), -// .A2(1'b1), -// .A3(1'b1)); - // synthesis attribute init of dcm2_rst_i1 is "000F"; - - DCM DCM_INST2 (.CLKFB(clk125_int_buf), - .CLKIN(clk_to_mac_buf), - .DSSEN(1'b0), - .PSCLK(1'b0), - .PSEN(1'b0), - .PSINCDEC(1'b0), - .RST(1'b0), - .CLK0(clk125_int)); - defparam DCM_INST2.CLK_FEEDBACK = "1X"; - defparam DCM_INST2.CLKDV_DIVIDE = 2.0; - defparam DCM_INST2.CLKFX_DIVIDE = 1; - defparam DCM_INST2.CLKFX_MULTIPLY = 4; - defparam DCM_INST2.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST2.CLKIN_PERIOD = 8.000; - defparam DCM_INST2.CLKOUT_PHASE_SHIFT = "NONE"; - defparam DCM_INST2.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST2.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST2.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST2.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST2.FACTORY_JF = 16'h8080; - defparam DCM_INST2.PHASE_SHIFT = 0; - defparam DCM_INST2.STARTUP_WAIT = "FALSE"; - - BUFG clk125_int_buf_i1 (.I(clk125_int), - .O(clk125_int_buf)); - - // - // DCM edits end here - // - - - u2_core - u2_core(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk125_int_buf), - .pps_in (pps_in), - .leds (leds_int), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_time_in (exp_time_in), - .exp_time_out (exp_time_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD_unreg[7:0]), - .GMII_TX_EN (GMII_TX_EN_unreg), - .GMII_TX_ER (GMII_TX_ER_unreg), - .GMII_GTX_CLK (GMII_GTX_CLK_int), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk_int), - .ser_t (ser_t_unreg[15:0]), - .ser_tklsb (ser_tklsb_unreg), - .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk_buf), - .ser_r (ser_r_int[15:0]), - .ser_rklsb (ser_rklsb_int), - .ser_rkmsb (ser_rkmsb_int), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .cpld_misc (cpld_misc), - .cpld_init_b (cpld_init_b), - .por (~POR), - .config_success (config_success), - .adc_a (adc_a_reg2), - .adc_ovf_a (adc_ovf_a_reg2), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b_reg2), - .adc_ovf_b (adc_ovf_b_reg2), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (dac_a_int), - .dac_b (dac_b_int), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk_int), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D_pi (RAM_D_pi), - .RAM_D_po (RAM_D_po), - .RAM_D_poe (RAM_D_poe), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - // .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - .uart_rx_i (uart_rx_i), - .uart_baud_o (), - .sim_mode (1'b0), - .clock_divider (2) - ); - -endmodule // u2_rev2 diff --git a/fpga/usrp2/top/extract_usage.py b/fpga/usrp2/top/extract_usage.py deleted file mode 100755 index 55fbf384c..000000000 --- a/fpga/usrp2/top/extract_usage.py +++ /dev/null @@ -1,60 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2012 Ettus Research LLC -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# - -import os -import sys - -ALL_MAP_FILES = """\ -./N2x0/build-N210R4/u2plus_map.map N210 -./N2x0/build-N200R4/u2plus_map.map N200 -./USRP2/build/u2_rev3_map.map USRP2 -./E1x0/build-E100/u1e_map.map E100 -./E1x0/build-E110/u1e_map.map E110 -./B100/build-B100/B100_map.map B100 -""" - -def extract_map_from_file(path): - output = '' - found = False - for line in open(path).readlines(): - if line.strip() == 'Mapping completed.': found = False - if line.strip() == 'Logic Utilization:': found = True - if found: output += line - return output - -def extract_maps(): - output = '' - for line in ALL_MAP_FILES.splitlines(): - path, name = line.split() - if not os.path.exists(path): - print 'DNE ', path, ' skipping...' - output += """ - - - -######################################################################## -## %s Usage Summary -######################################################################## - -%s"""%(name, extract_map_from_file(path).strip()) - return output + '\n\n' - -if __name__ == '__main__': - summary = extract_maps() - if len(sys.argv) == 1: print summary - else: open(sys.argv[1], 'w').write(summary) diff --git a/fpga/usrp2/top/impactor.sh b/fpga/usrp2/top/impactor.sh deleted file mode 100755 index c6699424d..000000000 --- a/fpga/usrp2/top/impactor.sh +++ /dev/null @@ -1,17 +0,0 @@ -#!/bin/bash - -echo "loading $1 into FPGA..." - -CMD_PATH=/tmp/impact.cmd - -echo "generating ${CMD_PATH}..." - -echo "setmode -bscan" > ${CMD_PATH} -echo "setcable -p auto" >> ${CMD_PATH} -echo "addDevice -p 1 -file $1" >> ${CMD_PATH} -echo "program -p 1" >> ${CMD_PATH} -echo "quit" >> ${CMD_PATH} - -impact -batch ${CMD_PATH} - -echo "done!" diff --git a/fpga/usrp2/top/python/check_inout.py b/fpga/usrp2/top/python/check_inout.py deleted file mode 100755 index ff371d378..000000000 --- a/fpga/usrp2/top/python/check_inout.py +++ /dev/null @@ -1,62 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2010 Ettus Research LLC -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# Description: -# generates a list of inputs and outputs from the top-level Verilog file and cross-references them to the .ucf. -# outputs errors for pins that aren't found in the UCF, checks for capitalization errors and other common mistakes - -import sys -import re - -if __name__=='__main__': - if len(sys.argv) == 2: - print "Usage: %s " - sys.exit(-1) - - verilog_filename = sys.argv[1] - ucf_filename = sys.argv[2] - - verilog_file = open(verilog_filename, 'r') - ucf_file = open(ucf_filename, 'r') - - verilog_iolist = list() - ucf_iolist = list() - - #read in all input, inout, and output declarations and compile a list - for line in verilog_file: - for match in re.findall(r"(?:input|inout|output) (?:reg )*(?:\[.*\] )*(\w+)", line.split("//")[0]): - verilog_iolist.append(match) - - for line in ucf_file: - m = re.search(r"""NET "(\w+).*" """, line.split("#")[0]) - if m is not None: - ucf_iolist.append(m.group(1)) - - #now find corresponding matches and error when you don't find one - #we search for .v defs without matching .ucf defs since the reverse isn't necessarily a problem - err = False - - for item in verilog_iolist: - if item not in ucf_iolist: - print "Error: %s appears in the top-level Verilog file, but is not in the UCF definition file!" % item - err = True - - if err: - sys.exit(-1) - - print "No errors found." - sys.exit(0) diff --git a/fpga/usrp2/top/python/check_timing.py b/fpga/usrp2/top/python/check_timing.py deleted file mode 100755 index 0c5918096..000000000 --- a/fpga/usrp2/top/python/check_timing.py +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2011 Ettus Research LLC -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . - -import sys -import re - -def print_timing_constraint_summary(twr_file): - output = "" - keep = False - done = False - for line in open(twr_file).readlines(): - if 'Derived Constraint Report' in line: keep = True - if 'constraint' in line and 'met' in line: done = True - if not keep and done: keep = True - if keep: output += line - if done: break - print("\n\n"+output) - -if __name__=='__main__': map(print_timing_constraint_summary, sys.argv[1:]) diff --git a/fpga/usrp2/top/tcl/ise_helper.tcl b/fpga/usrp2/top/tcl/ise_helper.tcl deleted file mode 100644 index c5ceded1b..000000000 --- a/fpga/usrp2/top/tcl/ise_helper.tcl +++ /dev/null @@ -1,94 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -proc set_props {process options} { - if ![string compare $options ""] { - return - } - set state 1 - foreach opt $options { - if $state { - set key $opt - set state 0 - } else { - puts ">>> Setting: $process\[$key\] = $opt" - if ![string compare $process "Project"] { - project set $key $opt - } else { - project set $key $opt -process $process - } - set state 1 - } - } -} - -if [file isfile $env(ISE_FILE)] { - puts ">>> Opening project: $env(ISE_FILE)" - project open $env(ISE_FILE) -} else { - puts ">>> Creating project: $env(ISE_FILE)" - project new $env(ISE_FILE) - - ################################################## - # Set the project properties - ################################################## - set_props "Project" $env(PROJECT_PROPERTIES) - - ################################################## - # Add the sources - ################################################## - foreach source $env(SOURCES) { - puts ">>> Adding source to project: $source" - xfile add $source - } - - ################################################## - # Add the custom sources - ################################################## - foreach source $env(CUSTOM_SRCS) { - puts ">>> Adding custom source to project: $source" - xfile add $source -include_global - } - - ################################################## - # Set the top level module - ################################################## - project set top $env(TOP_MODULE) - - ################################################## - # Set the process properties - ################################################## - set_props "Synthesize - XST" $env(SYNTHESIZE_PROPERTIES) - set_props "Translate" $env(TRANSLATE_PROPERTIES) - set_props "Map" $env(MAP_PROPERTIES) - set_props "Place & Route" $env(PLACE_ROUTE_PROPERTIES) - set_props "Generate Post-Place & Route Static Timing" $env(STATIC_TIMING_PROPERTIES) - set_props "Generate Programming File" $env(GEN_PROG_FILE_PROPERTIES) - set_props "Generate Post-Place & Route Simulation Model" $env(SIM_MODEL_PROPERTIES) -} - -if [string compare [lindex $argv 0] ""] { - puts ">>> Running Process: [lindex $argv 0]" - process run [lindex $argv 0] -} - -project close -exit - - diff --git a/fpga/usrp2/udp/Makefile.srcs b/fpga/usrp2/udp/Makefile.srcs deleted file mode 100644 index 293094abe..000000000 --- a/fpga/usrp2/udp/Makefile.srcs +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright 2010 Ettus Research LLC -# - -################################################## -# UDP Sources -################################################## -UDP_SRCS = $(abspath $(addprefix $(BASE_DIR)/../udp/, \ -udp_wrapper.v \ -fifo19_rxrealign.v \ -prot_eng_tx.v \ -add_onescomp.v \ -)) diff --git a/fpga/usrp2/udp/add_onescomp.v b/fpga/usrp2/udp/add_onescomp.v deleted file mode 100644 index e02604114..000000000 --- a/fpga/usrp2/udp/add_onescomp.v +++ /dev/null @@ -1,29 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module add_onescomp - #(parameter WIDTH = 16) - (input [WIDTH-1:0] A, - input [WIDTH-1:0] B, - output [WIDTH-1:0] SUM); - - wire [WIDTH:0] SUM_INT = {1'b0,A} + {1'b0,B}; - assign SUM = SUM_INT[WIDTH-1:0] + {{WIDTH-1{1'b0}},SUM_INT[WIDTH]}; - -endmodule // add_onescomp diff --git a/fpga/usrp2/udp/fifo19_rxrealign.v b/fpga/usrp2/udp/fifo19_rxrealign.v deleted file mode 100644 index da5fd20af..000000000 --- a/fpga/usrp2/udp/fifo19_rxrealign.v +++ /dev/null @@ -1,59 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -// Adds a junk line at the beginning of every packet, which the -// following stages should ignore. This gives us proper alignment due -// to the 14 byte ethernet header - -// Bit 18 -- odd length -// Bit 17 -- eof -// Bit 16 -- sof -// Bit 15:0 -- data - -module fifo19_rxrealign - (input clk, input reset, input clear, - input [18:0] datain, input src_rdy_i, output dst_rdy_o, - output [18:0] dataout, output src_rdy_o, input dst_rdy_i); - - reg rxre_state; - localparam RXRE_DUMMY = 0; - localparam RXRE_PKT = 1; - - assign dataout[18] = datain[18]; - assign dataout[17] = datain[17]; - assign dataout[16] = (rxre_state==RXRE_DUMMY) | (datain[17] & datain[16]); // allows for passing error signal - assign dataout[15:0] = datain[15:0]; - - always @(posedge clk) - if(reset | clear) - rxre_state <= RXRE_DUMMY; - else if(src_rdy_i & dst_rdy_i) - case(rxre_state) - RXRE_DUMMY : - rxre_state <= RXRE_PKT; - RXRE_PKT : - if(datain[17]) // if eof or error - rxre_state <= RXRE_DUMMY; - endcase // case (rxre_state) - - assign src_rdy_o = src_rdy_i & dst_rdy_i; // Send anytime both sides are ready - assign dst_rdy_o = src_rdy_i & dst_rdy_i & (rxre_state == RXRE_PKT); // Only consume after the dummy - -endmodule // fifo19_rxrealign - diff --git a/fpga/usrp2/udp/prot_eng_rx.v b/fpga/usrp2/udp/prot_eng_rx.v deleted file mode 100644 index ccb59b7ff..000000000 --- a/fpga/usrp2/udp/prot_eng_rx.v +++ /dev/null @@ -1,138 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - - -// Protocol Engine Receiver -// Checks each line (16 bits) against values in setting regs -// 3 options for each line -- -// Error if mismatch, Slowpath if mismatch, or ignore line -// The engine increases the length of each packet by 32 or 48 bits, -// bringing the total length to a multiple of 32 bits. The last line -// is entirely new, and contains the results of the matching operation: -// 16 bits of flags, 16 bits of data. Flags indicate error or slowpath -// Data indicates line that caused mismatch if any. - - -// Flags[2:0] is {occ, eop, sop} -// Protocol word format is: -// 22 Last Header Line -// 21 SLOWPATH if mismatch -// 20 ERROR if mismatch -// 19 This is the IP checksum -// 18 This is the UDP checksum -// 17 Compute IP checksum on this word -// 16 Compute UDP checksum on this word -// 15:0 data word to be matched - -module prot_eng_rx - #(parameter BASE=0) - (input clk, input reset, input clear, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - input [18:0] datain, input src_rdy_i, output dst_rdy_o, - output [18:0] dataout, output src_rdy_o, input dst_rdy_i); - - localparam HDR_WIDTH = 16 + 7; // 16 bits plus flags - localparam HDR_LEN = 32; // Up to 64 bytes of protocol - - // Store header values in a small dual-port (distributed) ram - reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1]; - wire [HDR_WIDTH-1:0] header_word; - - always @(posedge clk) - if(set_stb & ((set_addr & 8'hE0) == BASE)) - header_ram[set_addr[4:0]] <= set_data; - - assign header_word = header_ram[state]; - - wire consume_input = src_rdy_i & dst_rdy_o; - wire produce_output = src_rdy_o & dst_rdy_i; - - // Main State Machine - reg [15:0] pkt_length, fail_word, dataout_int; - - reg slowpath, error, sof_o, eof_o, occ_o, odd; - - assign dataout = {occ_o, eof_o, sof_o, dataout_int}; - - wire [15:0] calc_ip_checksum, calc_udp_checksum; - reg [15:0] rx_ip_checksum, rx_udp_checksum; - - always @(posedge clk) - if(header_word[19]) - rx_ip_checksum <= datain[15:0]; - always @(posedge clk) - if(header_word[18]) - rx_udp_checksum <= datain[15:0]; - - always @(posedge clk) - if(reset | clear) - begin - slowpath <= 0; - error <= 0; - state <= 0; - fail_word <= 0; - eof_o <= 0; - occ_o <= 0; - end - else if(src_rdy_i & dst_rdy_i) - case (state) - 0 : - begin - slowpath <= 0; - error <= 0; - eof_o <= 0; - occ_o <= 0; - state <= 1; - end - - ST_SLOWPATH : - ; - ST_ERROR : - ; - ST_PAYLOAD : - ; - ST_FILLER : - ; - ST_END1 : - ; - ST_END2 : - ; - default : - if(header_word[21] && mismatch) - state <= ST_SLOWPATH; - else if(header_word[20] && mismatch) - state <= ST_ERROR; - else if(header_word[22]) - state <= ST_PAYLOAD; - else - state <= state + 1; - endcase // case (state) - - - - // IP + UDP checksum state machines - checksum_sm ip_chk - (.clk(clk), .reset(reset), .in(datain), - .calc(consume_input & header_word[17]), .clear(state==0), .checksum(ip_checksum)); - - checksum_sm udp_chk - (.clk(clk), .reset(reset), .in(datain), - .calc(consume_input & header_word[16]), .clear(state==0), .checksum(udp_checksum)); - -endmodule // prot_eng_rx diff --git a/fpga/usrp2/udp/prot_eng_tx.v b/fpga/usrp2/udp/prot_eng_tx.v deleted file mode 100644 index 40abf3c04..000000000 --- a/fpga/usrp2/udp/prot_eng_tx.v +++ /dev/null @@ -1,127 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module prot_eng_tx - #(parameter BASE=0) - (input clk, input reset, input clear, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - input [35:0] datain, input src_rdy_i, output dst_rdy_o, - output [35:0] dataout, output src_rdy_o, input dst_rdy_i); - - wire src_rdy_int1, dst_rdy_int1; - wire src_rdy_int2, dst_rdy_int2; - wire [35:0] data_int1, data_int2; - - // Shortfifo on input to guarantee no deadlock - fifo_short #(.WIDTH(36)) head_fifo - (.clk(clk),.reset(reset),.clear(clear), - .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), - .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1), - .space(),.occupied() ); - - // Store header values in a small dual-port (distributed) ram - reg [31:0] header_ram[0:63]; - reg [3:0] state; - reg [1:0] port_sel; - - always @(posedge clk) - if(set_stb & ((set_addr & 8'hC0) == BASE)) - header_ram[set_addr[5:0]] <= set_data; - - wire [31:0] header_word = header_ram[{port_sel[1:0],state[3:0]}]; - - reg [15:0] pre_checksums [0:3]; - always @(posedge clk) - if(set_stb & ((set_addr & 8'hCF)== (BASE+7))) - pre_checksums[set_addr[5:4]] <= set_data[15:0]; - - wire [15:0] pre_checksum = pre_checksums[port_sel[1:0]]; - - // Protocol State Machine - reg [15:0] length; - wire [15:0] ip_length = length + 28; // IP HDR + UDP HDR - wire [15:0] udp_length = length + 8; // UDP HDR - reg sof_o; - reg [31:0] prot_data; - - always @(posedge clk) - if(reset) - begin - state <= 0; - sof_o <= 0; - end - else - if(src_rdy_int1 & dst_rdy_int2) - case(state) - 0 : - begin - port_sel <= data_int1[18:17]; - length <= data_int1[15:0]; - sof_o <= 1; - if(data_int1[16]) - state <= 1; - else - state <= 12; - end - 12 : - begin - sof_o <= 0; - if(data_int1[33]) // eof - state <= 0; - end - default : - begin - sof_o <= 0; - state <= state + 1; - end - endcase // case (state) - - wire [15:0] ip_checksum; - add_onescomp #(.WIDTH(16)) add_onescomp - (.A(pre_checksum),.B(ip_length),.SUM(ip_checksum)); - reg [15:0] ip_checksum_reg; - always @(posedge clk) ip_checksum_reg <= ip_checksum; - - always @* - case(state) - 1 : prot_data <= header_word; // ETH, top half ignored - 2 : prot_data <= header_word; // ETH - 3 : prot_data <= header_word; // ETH - 4 : prot_data <= header_word; // ETH - 5 : prot_data <= { header_word[31:16], ip_length }; // IP - 6 : prot_data <= header_word; // IP - 7 : prot_data <= { header_word[31:16], (16'hFFFF ^ ip_checksum_reg) }; // IP - 8 : prot_data <= header_word; // IP - 9 : prot_data <= header_word; // IP - 10: prot_data <= header_word; // UDP - 11: prot_data <= { udp_length, header_word[15:0]}; // UDP - default : prot_data <= data_int1[31:0]; - endcase // case (state) - - assign data_int2 = { data_int1[35:33] & {3{state[3]}}, sof_o, prot_data }; - assign dst_rdy_int1 = dst_rdy_int2 & ((state == 0) | (state == 12)); - assign src_rdy_int2 = src_rdy_int1 & (state != 0); - - // Shortfifo on output to guarantee no deadlock - fifo_short #(.WIDTH(36)) tail_fifo - (.clk(clk),.reset(reset),.clear(clear), - .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2), - .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), - .space(),.occupied() ); - -endmodule // prot_eng_tx diff --git a/fpga/usrp2/udp/prot_eng_tx_tb.v b/fpga/usrp2/udp/prot_eng_tx_tb.v deleted file mode 100644 index 866093ef5..000000000 --- a/fpga/usrp2/udp/prot_eng_tx_tb.v +++ /dev/null @@ -1,198 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module prot_eng_tx_tb(); - - localparam BASE = 128; - reg clk = 0; - reg rst = 1; - reg clear = 0; - initial #1000 rst = 0; - always #50 clk = ~clk; - - reg [31:0] f36_data; - reg [1:0] f36_occ; - reg f36_sof, f36_eof; - wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data}; - reg src_rdy_f36i = 0; - wire dst_rdy_f36i; - - - wire [35:0] casc_do; - wire src_rdy_f36o, dst_rdy_f36o; - - wire [35:0] prot_out; - wire src_rdy_prot, dst_rdy_prot; - - wire [35:0] realign_out; - wire src_rdy_realign; - reg dst_rdy_realign = 1; - - reg [15:0] count; - - reg set_stb; - reg [7:0] set_addr; - reg [31:0] set_data; - - fifo_short #(.WIDTH(36)) fifo_cascade36 - (.clk(clk),.reset(rst),.clear(clear), - .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i), - .dataout(casc_do),.src_rdy_o(src_rdy_f36o),.dst_rdy_i(dst_rdy_f36o)); - - prot_eng_tx #(.BASE(BASE)) prot_eng_tx - (.clk(clk), .reset(rst), .clear(0), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .datain(casc_do),.src_rdy_i(src_rdy_f36o),.dst_rdy_o(dst_rdy_f36o), - .dataout(prot_out),.src_rdy_o(src_rdy_prot),.dst_rdy_i(dst_rdy_prot)); - - ethtx_realign ethtx_realign - (.clk(clk), .reset(rst), .clear(0), - .datain(prot_out),.src_rdy_i(src_rdy_prot),.dst_rdy_o(dst_rdy_prot), - .dataout(realign_out),.src_rdy_o(src_rdy_realign),.dst_rdy_i(dst_rdy_realign)); - - reg [35:0] printer; - - task WriteSREG; - input [7:0] addr; - input [31:0] data; - - begin - @(posedge clk); - set_addr <= addr; - set_data <= data; - set_stb <= 1; - @(posedge clk); - set_stb <= 0; - end - endtask // WriteSREG - - always @(posedge clk) - if(src_rdy_realign) - $display("Read: %h",realign_out); - - - task ReadFromFIFO36; - begin - $display("Read from FIFO36"); - #1 dst_rdy_realign <= 1; - while(~src_rdy_prot) - @(posedge clk); - while(1) - begin - while(~src_rdy_prot) - @(posedge clk); - $display("Read: %h",realign_out); - @(posedge clk); - end - end - endtask // ReadFromFIFO36 - - task PutPacketInFIFO36; - input [31:0] data_start; - input [31:0] data_len; - begin - count <= 4; - src_rdy_f36i <= 1; - f36_data <= 32'h0001_000c; - f36_sof <= 1; - f36_eof <= 0; - f36_occ <= 0; - - $display("Put Packet in FIFO36"); - while(~dst_rdy_f36i) - @(posedge clk); - @(posedge clk); - $display("PPI_FIFO36: Entered First Line"); - f36_sof <= 0; - f36_data <= data_start; - while(~dst_rdy_f36i) - @(posedge clk); - @(posedge clk); - while(count+4 < data_len) - begin - f36_data <= f36_data + 32'h01010101; - count <= count + 4; - while(~dst_rdy_f36i) - @(posedge clk); - @(posedge clk); - $display("PPI_FIFO36: Entered New Line"); - end - f36_data <= f36_data + 32'h01010101; - f36_eof <= 1; - if(count + 4 == data_len) - f36_occ <= 0; - else if(count + 3 == data_len) - f36_occ <= 3; - else if(count + 2 == data_len) - f36_occ <= 2; - else - f36_occ <= 1; - while(~dst_rdy_f36i) - @(posedge clk); - @(posedge clk); - f36_occ <= 0; - f36_eof <= 0; - f36_data <= 0; - src_rdy_f36i <= 0; - $display("PPI_FIFO36: Entered Last Line"); - end - endtask // PutPacketInFIFO36 - - initial $dumpfile("prot_eng_tx_tb.vcd"); - initial $dumpvars(0,prot_eng_tx_tb); - - initial - begin - #10000; - @(posedge clk); - //ReadFromFIFO36; - end - - initial - begin - @(negedge rst); - @(posedge clk); - WriteSREG(BASE, 32'h89AB_CDEF); - WriteSREG(BASE+1, 32'h1111_2222); - WriteSREG(BASE+2, 32'h3333_4444); - WriteSREG(BASE+3, 32'h5555_6666); - WriteSREG(BASE+4, 32'h7777_8888); - WriteSREG(BASE+5, 32'h9999_aaaa); - WriteSREG(BASE+6, 32'hbbbb_cccc); - WriteSREG(BASE+7, 32'hdddd_eeee); - WriteSREG(BASE+8, 32'h0f0f_0011); - WriteSREG(BASE+9, 32'h0022_0033); - WriteSREG(BASE+10, 32'h0044_0055); - WriteSREG(BASE+11, 32'h0066_0077); - WriteSREG(BASE+12, 32'h0088_0099); - @(posedge clk); - - PutPacketInFIFO36(32'hA0B0C0D0,16); - @(posedge clk); - @(posedge clk); - #10000; - @(posedge clk); - //PutPacketInFIFO36(32'hE0F0A0B0,36); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - end - - initial #20000 $finish; -endmodule // prot_eng_tx_tb diff --git a/fpga/usrp2/udp/udp_wrapper.v b/fpga/usrp2/udp/udp_wrapper.v deleted file mode 100644 index 20bcb477b..000000000 --- a/fpga/usrp2/udp/udp_wrapper.v +++ /dev/null @@ -1,109 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module udp_wrapper - #(parameter BASE=0) - (input clk, input reset, input clear, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - input [18:0] rx_f19_data, input rx_f19_src_rdy_i, output rx_f19_dst_rdy_o, - output [18:0] tx_f19_data, output tx_f19_src_rdy_o, input tx_f19_dst_rdy_i, - - output [35:0] rx_f36_data, output rx_f36_src_rdy_o, input rx_f36_dst_rdy_i, - input [35:0] tx_f36_data, input tx_f36_src_rdy_i, output tx_f36_dst_rdy_o, - output [31:0] debug - ); - - wire tx_int1_src_rdy, tx_int1_dst_rdy; - wire [18:0] tx_int1_data; - - wire tx_int2_src_rdy, tx_int2_dst_rdy; - wire [18:0] tx_int2_data; - wire [31:0] debug_state; - - // TX side - fifo36_to_fifo19 fifo36_to_fifo19 - (.clk(clk), .reset(reset), .clear(clear), - .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy_i), .f36_dst_rdy_o(tx_f36_dst_rdy_o), - .f19_dataout(tx_int1_data), .f19_src_rdy_o(tx_int1_src_rdy), .f19_dst_rdy_i(tx_int1_dst_rdy) ); - - fifo_short #(.WIDTH(19)) shortfifo19_a - (.clk(clk), .reset(reset), .clear(clear), - .datain(tx_int1_data), .src_rdy_i(tx_int1_src_rdy), .dst_rdy_o(tx_int1_dst_rdy), - .dataout(tx_int2_data), .src_rdy_o(tx_int2_src_rdy), .dst_rdy_i(tx_int2_dst_rdy), - .space(), .occupied() ); - - prot_eng_tx #(.BASE(BASE)) prot_eng_tx - (.clk(clk), .reset(reset), .clear(clear), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .datain(tx_int2_data), .src_rdy_i(tx_int2_src_rdy), .dst_rdy_o(tx_int2_dst_rdy), - .dataout(tx_f19_data), .src_rdy_o(tx_f19_src_rdy_o), .dst_rdy_i(tx_f19_dst_rdy_i) ); - - // RX side - wire rx_int1_src_rdy, rx_int1_dst_rdy; - wire [18:0] rx_int1_data; - - wire rx_int2_src_rdy, rx_int2_dst_rdy; - wire [18:0] rx_int2_data; - - //wire rx_int3_src_rdy, rx_int3_dst_rdy; - //wire [35:0] rx_int3_data; - -`ifdef USE_PROT_ENG - prot_eng_rx #(.BASE(BASE+32)) prot_eng_rx - (.clk(clk), .reset(reset), .clear(clear), - .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), .dst_rdy_o(rx_f19_dst_rdy_o), - .dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), .dst_rdy_i(rx_int1_dst_rdy) ); -`else - fifo19_rxrealign fifo19_rxrealign - (.clk(clk), .reset(reset), .clear(clear), - .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), .dst_rdy_o(rx_f19_dst_rdy_o), - .dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), .dst_rdy_i(rx_int1_dst_rdy) ); -`endif // !`ifdef USE_PROT_ENG - - fifo_short #(.WIDTH(19)) shortfifo19_b - (.clk(clk), .reset(reset), .clear(clear), - .datain(rx_int1_data), .src_rdy_i(rx_int1_src_rdy), .dst_rdy_o(rx_int1_dst_rdy), - .dataout(rx_int2_data), .src_rdy_o(rx_int2_src_rdy), .dst_rdy_i(rx_int2_dst_rdy), - .space(), .occupied() ); - - fifo19_to_fifo36 fifo19_to_fifo36 - (.clk(clk), .reset(reset), .clear(clear), - .f19_datain(rx_int2_data), .f19_src_rdy_i(rx_int2_src_rdy), .f19_dst_rdy_o(rx_int2_dst_rdy), - .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy_o), .f36_dst_rdy_i(rx_f36_dst_rdy_i), - .debug(debug_state)); - - /* - fifo_cascade #(.WIDTH(36),.SIZE(RXFIFOSIZE)) eth0_rxfifo - (.clk(clk), .reset(reset), .clear(clear), - .datain(rx_int3_data), .src_rdy_i(rx_int3_src_rdy), .dst_rdy_o(rx_int3_dst_rdy), - .dataout(rx_f36_data), .src_rdy_o(rx_f36_src_rdy_o), .dst_rdy_i(rx_f36_dst_rdy_i), - .space(), .occupied() ); -*/ - /* - assign debug = { { 1'b0, rx_f19_data[18:16], rx_f19_src_rdy_i, rx_f19_dst_rdy_o, rx_f36_src_rdy_o, rx_f36_dst_rdy_i }, - { 2'b0, rx_int1_src_rdy, rx_int1_dst_rdy, rx_int2_src_rdy, rx_int2_dst_rdy, rx_int3_src_rdy, rx_int3_dst_rdy}, - { rx_int3_data[35:32], rx_f36_data[35:32] }, - { debug_state[1:0], rx_int1_data[18:16], rx_int2_data[18:16] } }; - */ - - assign debug = { { 3'd0, tx_int1_src_rdy, tx_int1_dst_rdy, tx_int1_data[18:16] }, - { 3'd0, tx_int2_src_rdy, tx_int2_dst_rdy, tx_int2_data[18:16] }, - { tx_int2_data[15:8] }, - { tx_int2_data[7:0] } }; - -endmodule // udp_wrapper diff --git a/fpga/usrp2/vrt/.gitignore b/fpga/usrp2/vrt/.gitignore deleted file mode 100644 index 446b2daae..000000000 --- a/fpga/usrp2/vrt/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -vita_rx_tb -vita_tx_tb -*.vcd -*.sav diff --git a/fpga/usrp2/vrt/Makefile.srcs b/fpga/usrp2/vrt/Makefile.srcs deleted file mode 100644 index 84ba5dc29..000000000 --- a/fpga/usrp2/vrt/Makefile.srcs +++ /dev/null @@ -1,20 +0,0 @@ -# -# Copyright 2010 Ettus Research LLC -# - -################################################## -# VRT Sources -################################################## -VRT_SRCS = $(abspath $(addprefix $(BASE_DIR)/../vrt/, \ -vita_rx_control.v \ -vita_rx_framer.v \ -vita_rx_chain.v \ -vita_tx_control.v \ -vita_tx_deframer.v \ -vita_tx_chain.v \ -gen_context_pkt.v \ -trigger_context_pkt.v \ -vita_pkt_gen.v \ -vita_rx_engine_glue.v \ -vita_tx_engine_glue.v \ -)) diff --git a/fpga/usrp2/vrt/gen_context_pkt.v b/fpga/usrp2/vrt/gen_context_pkt.v deleted file mode 100644 index d6674e887..000000000 --- a/fpga/usrp2/vrt/gen_context_pkt.v +++ /dev/null @@ -1,106 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module gen_context_pkt - #(parameter PROT_ENG_FLAGS=1, - parameter DSP_NUMBER=0) - (input clk, input reset, input clear, - input trigger, output sent, - input [31:0] streamid, - input [63:0] vita_time, - input [31:0] message, - input [31:0] seqnum, - output [35:0] data_o, output src_rdy_o, input dst_rdy_i); - - localparam CTXT_IDLE = 0; - localparam CTXT_PROT_ENG = 1; - localparam CTXT_HEADER = 2; - localparam CTXT_STREAMID = 3; - localparam CTXT_TICS = 4; - localparam CTXT_TICS2 = 5; - localparam CTXT_MESSAGE = 6; - localparam CTXT_FLOWCTRL = 7; - localparam CTXT_DONE = 8; - - reg [33:0] data_int; - wire src_rdy_int, dst_rdy_int; - reg [3:0] seqno; - reg [3:0] ctxt_state; - reg [63:0] err_time; - reg [31:0] stored_message; - - always @(posedge clk) - if(reset | clear) - stored_message <= 0; - else - if(trigger) - stored_message <= message; - else if(ctxt_state == CTXT_DONE) - stored_message <= 0; - - // Don't want to clear most of this to avoid getting stuck with a half packet in the pipe - always @(posedge clk) - if(reset) - begin - ctxt_state <= CTXT_IDLE; - seqno <= 0; - end - else - case(ctxt_state) - CTXT_IDLE : - if(trigger) - begin - err_time <= vita_time; - if(PROT_ENG_FLAGS) - ctxt_state <= CTXT_PROT_ENG; - else - ctxt_state <= CTXT_HEADER; - end - - CTXT_DONE : - begin - ctxt_state <= CTXT_IDLE; - seqno <= seqno + 4'd1; - end - default : - if(dst_rdy_int) - ctxt_state <= ctxt_state + 1; - endcase // case (ctxt_state) - - assign src_rdy_int = ~( (ctxt_state == CTXT_IDLE) | (ctxt_state == CTXT_DONE) ); - - always @* - case(ctxt_state) - CTXT_PROT_ENG : data_int <= { 2'b01, 13'b0, DSP_NUMBER[0], 1'b1, 1'b1, 16'd24 }; // UDP port 1 or 3 - CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100000001, seqno, 16'd6 }; - CTXT_STREAMID : data_int <= { 2'b00, streamid }; - CTXT_TICS : data_int <= { 2'b00, err_time[63:32] }; - CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] }; - CTXT_MESSAGE : data_int <= { 2'b00, message }; - CTXT_FLOWCTRL : data_int <= { 2'b10, seqnum }; - default : data_int <= {2'b00, 32'b00}; - endcase // case (ctxt_state) - - fifo_short #(.WIDTH(34)) ctxt_fifo - (.clk(clk), .reset(reset), .clear(0), - .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), - .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); - assign data_o[35:34] = 2'b00; - -endmodule // gen_context_pkt diff --git a/fpga/usrp2/vrt/trigger_context_pkt.v b/fpga/usrp2/vrt/trigger_context_pkt.v deleted file mode 100644 index 3d9c2e5c6..000000000 --- a/fpga/usrp2/vrt/trigger_context_pkt.v +++ /dev/null @@ -1,69 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module trigger_context_pkt - #(parameter BASE=0) - (input clk, input reset, input clear, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - input packet_consumed, output reg trigger); - - wire [23:0] cycles; - wire [15:0] packets; - wire [6:0] dummy1; - wire [14:0] dummy2; - wire enable_cycle, enable_consumed; - reg [30:0] cycle_count, packet_count; - - - setting_reg #(.my_addr(BASE+4), .at_reset(0)) sr_cycles - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({enable_cycle,dummy1,cycles}),.changed()); - - setting_reg #(.my_addr(BASE+5), .at_reset(0)) sr_packets - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({enable_consumed,dummy2,packets}),.changed()); - - always @(posedge clk) - if(reset | clear) - cycle_count <= 0; - else - if(trigger) - cycle_count <= 0; - else if(enable_cycle) - cycle_count <= cycle_count + 1; - - always @(posedge clk) - if(reset | clear) - packet_count <= 0; - else - if(trigger) - packet_count <= 0; - else if(packet_consumed & enable_consumed) - packet_count <= packet_count + 1; - - always @(posedge clk) - if(reset | clear) - trigger <= 0; - else - if((cycle_count > cycles)|(packet_count > packets)) - trigger <= 1; - else - trigger <= 0; - -endmodule // trigger_context_pkt diff --git a/fpga/usrp2/vrt/vita_packet_demux36.v b/fpga/usrp2/vrt/vita_packet_demux36.v deleted file mode 100644 index 83fb26215..000000000 --- a/fpga/usrp2/vrt/vita_packet_demux36.v +++ /dev/null @@ -1,102 +0,0 @@ -// -// Copyright 2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -//demux an input stream based on the SID -//output packet has SID removed from header - -module vita_packet_demux36 -#( - parameter NUMCHAN = 1, - parameter SID_BASE = 0 -) -( - input clk, input rst, - - input [35:0] in_data, - input in_src_rdy, - output in_dst_rdy, - - output [35:0] out_data, - output [NUMCHAN-1:0] out_src_rdy, - input [NUMCHAN-1:0] out_dst_rdy -); - - reg [1:0] state; - localparam STATE_WAIT_HDR = 0; - localparam STATE_PROC_SID = 1; - localparam STATE_WRITE_HDR = 2; - localparam STATE_FORWARD = 3; - - reg [31:0] hdr; - reg [NUMCHAN-1:0] sid; - wire has_sid = in_data[28]; - reg has_sid_reg; - - wire my_out_dst_rdy = out_dst_rdy[sid]; - wire my_out_src_rdy = out_src_rdy[sid]; - - always @(posedge clk) begin - if (rst) begin - state <= STATE_WAIT_HDR; - end - else case(state) - - STATE_WAIT_HDR: begin - if (in_src_rdy && in_dst_rdy && in_data[32]) begin - state <= (has_sid)? STATE_PROC_SID : STATE_WRITE_HDR; - end - sid <= 0; - hdr <= in_data[31:0]; - has_sid_reg <= has_sid; - end - - STATE_PROC_SID: begin - if (in_src_rdy && in_dst_rdy) begin - state <= STATE_WRITE_HDR; - sid <= in_data[31:0] - SID_BASE; - hdr[28] <= 1'b0; //clear has sid - hdr[15:0] <= hdr[15:0] - 1'b1; //subtract a line - end - end - - STATE_WRITE_HDR: begin - if (my_out_src_rdy && my_out_dst_rdy) begin - state <= STATE_FORWARD; - end - end - - STATE_FORWARD: begin - if (my_out_src_rdy && my_out_dst_rdy && out_data[33]) begin - state <= STATE_WAIT_HDR; - end - end - - endcase //state - end - - assign out_data = (state == STATE_WRITE_HDR)? {4'b0001, hdr} : in_data; - wire out_src_rdy_i = (state == STATE_WRITE_HDR)? 1'b1 : ((state == STATE_FORWARD)? in_src_rdy : 1'b0); - assign in_dst_rdy = (state == STATE_WAIT_HDR || state == STATE_PROC_SID)? 1'b1 : ((state == STATE_FORWARD)? my_out_dst_rdy : 1'b0); - - genvar i; - generate - for(i = 0; i < NUMCHAN; i = i + 1) begin:valid_assign - assign out_src_rdy[i] = (i == sid)? out_src_rdy_i : 1'b0; - end - endgenerate - -endmodule //vita_packet_demux36 diff --git a/fpga/usrp2/vrt/vita_pkt_gen.v b/fpga/usrp2/vrt/vita_pkt_gen.v deleted file mode 100644 index b962254a6..000000000 --- a/fpga/usrp2/vrt/vita_pkt_gen.v +++ /dev/null @@ -1,59 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module vita_pkt_gen - (input clk, input reset, input clear, - input [15:0] len, - output [35:0] data_o, output src_rdy_o, input dst_rdy_i); - - reg [15:0] state; - reg [31:0] seq, data; - - wire sof = (state == 0); - wire eof = (state == (len-1)); - wire consume = src_rdy_o & dst_rdy_i; - - assign src_rdy_o = 1; - - always @(posedge clk) - if(reset | clear) - begin - state <= 0; - seq <= 0; - end - else - if(consume) - if(eof) - begin - state <= 0; - seq <= seq + 1; - end - else - state <= state + 1; - - always @* - case(state) - 0 : data <= {24'h000,seq[3:0],len}; - 1 : data <= seq; - default : data <= {~state,state}; - endcase // case (state) - - assign data_o = {2'b00, eof, sof, data}; - -endmodule // vita_pkt_gen diff --git a/fpga/usrp2/vrt/vita_rx.build b/fpga/usrp2/vrt/vita_rx.build deleted file mode 100755 index 010d1be6e..000000000 --- a/fpga/usrp2/vrt/vita_rx.build +++ /dev/null @@ -1 +0,0 @@ -iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../fifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v diff --git a/fpga/usrp2/vrt/vita_rx_chain.v b/fpga/usrp2/vrt/vita_rx_chain.v deleted file mode 100644 index 2788dc9d5..000000000 --- a/fpga/usrp2/vrt/vita_rx_chain.v +++ /dev/null @@ -1,114 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module vita_rx_chain - #(parameter BASE=0, - parameter UNIT=0, - parameter FIFOSIZE=10, - parameter PROT_ENG_FLAGS=1, - parameter DSP_NUMBER=0) - (input clk, input reset, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user, - input [63:0] vita_time, - input [31:0] sample, input strobe, - output [35:0] rx_data_o, output rx_src_rdy_o, input rx_dst_rdy_i, - output overrun, output run, output clear_o, - output [31:0] debug ); - - wire [100:0] sample_data; - wire sample_dst_rdy, sample_src_rdy; - wire [31:0] vrc_debug, vrf_debug; - - wire [35:0] rx_data_int; - wire rx_src_rdy_int, rx_dst_rdy_int; - - wire clear; - assign clear_o = clear; - wire clear_int; - setting_reg #(.my_addr(BASE+8)) sr - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_int)); - - vita_rx_control #(.BASE(BASE), .WIDTH(32)) vita_rx_control - (.clk(clk), .reset(reset), .clear(clear), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), .overrun(overrun), - .sample(sample), .run(run), .strobe(strobe), - .sample_fifo_o(sample_data), .sample_fifo_dst_rdy_i(sample_dst_rdy), .sample_fifo_src_rdy_o(sample_src_rdy), - .debug_rx(vrc_debug)); - - vita_rx_framer #(.BASE(BASE), .MAXCHAN(1)) vita_rx_framer - (.clk(clk), .reset(reset), .clear(clear), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .sample_fifo_i(sample_data), .sample_fifo_dst_rdy_o(sample_dst_rdy), .sample_fifo_src_rdy_i(sample_src_rdy), - .data_o(rx_data_int), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int), - .debug_rx(vrf_debug) ); - - wire [FIFOSIZE-1:0] access_adr, access_len; - wire access_we, access_stb, access_ok, access_done, access_skip_read; - wire [35:0] dsp_to_buf, buf_to_dsp; - wire [35:0] rx_data_int2; - wire rx_src_rdy_int2, rx_dst_rdy_int2; - - double_buffer #(.BUF_SIZE(FIFOSIZE)) db - (.clk(clk),.reset(reset),.clear(clear), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(dsp_to_buf), .access_dat_o(buf_to_dsp), - - .data_i(rx_data_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int), - .data_o(rx_data_int2), .src_rdy_o(rx_src_rdy_int2), .dst_rdy_i(rx_dst_rdy_int2)); - - vita_rx_engine_glue #(.DSPNO(DSP_NUMBER), .MAIN_SETTINGS_BASE(BASE+3), .BUF_SIZE(FIFOSIZE)) dspengine_rx - (.clock(clk),.reset(reset),.clear(clear), - .set_stb_main(set_stb), .set_addr_main(set_addr), .set_data_main(set_data), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf)); - - add_routing_header #(.PORT_SEL(UNIT), - .PROT_ENG_FLAGS(PROT_ENG_FLAGS)) dsp_routing_header - (.clk(clk), .reset(reset), .clear(clear), - .data_i(rx_data_int2), .src_rdy_i(rx_src_rdy_int2), .dst_rdy_o(rx_dst_rdy_int2), - .data_o(rx_data_o), .src_rdy_o(rx_src_rdy_o), .dst_rdy_i(rx_dst_rdy_i) ); - - //only clear once a full packet has passed through the output interface - reg xfer_pkt, clear_oneshot; - assign clear = (clear_oneshot)? ~xfer_pkt : 0; - always @(posedge clk) begin - - if (reset || clear) begin - clear_oneshot <= 0; - end - else if (clear_int) begin - clear_oneshot <= 1; - end - - if (reset || clear) begin - xfer_pkt <= 0; - end - else if (rx_src_rdy_o && rx_dst_rdy_i) begin - xfer_pkt <= ~rx_data_o[33]; - end - end - - assign debug = vrc_debug; // | vrf_debug; - -endmodule // vita_rx_chain diff --git a/fpga/usrp2/vrt/vita_rx_control.v b/fpga/usrp2/vrt/vita_rx_control.v deleted file mode 100644 index daec734a8..000000000 --- a/fpga/usrp2/vrt/vita_rx_control.v +++ /dev/null @@ -1,231 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module vita_rx_control - #(parameter BASE=0, - parameter WIDTH=32) - (input clk, input reset, input clear, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - input [63:0] vita_time, - output overrun, - - // To vita_rx_framer - output [5+64+WIDTH-1:0] sample_fifo_o, - output sample_fifo_src_rdy_o, - input sample_fifo_dst_rdy_i, - - // From DSP Core - input [WIDTH-1:0] sample, - output run, - input strobe, - - output [31:0] debug_rx - ); - - // FIXME add TX Interruption (halt, pause, continue) functionality - - wire [63:0] new_time; - wire [31:0] new_command; - wire sc_pre1; - - wire [63:0] rcvtime_pre; - reg [63:0] rcvtime; - wire [27:0] numlines_pre; - wire send_imm_pre, chain_pre, reload_pre, stop_pre; - reg send_imm, chain, reload; - wire read_ctrl, not_empty_ctrl, write_ctrl; - reg sc_pre2; - wire [33:0] fifo_line; - reg [27:0] lines_left, lines_total; - reg [2:0] ibs_state; - wire now, early, late; - wire sample_fifo_in_rdy; - - setting_reg #(.my_addr(BASE)) sr_cmd - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(new_command),.changed()); - - setting_reg #(.my_addr(BASE+1)) sr_time_h - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(new_time[63:32]),.changed()); - - setting_reg #(.my_addr(BASE+2)) sr_time_l - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(new_time[31:0]),.changed(sc_pre1)); - - // FIFO to store commands sent from the settings bus - always @(posedge clk) - if(reset | clear) - sc_pre2 <= 0; - else - sc_pre2 <= sc_pre1; - - assign write_ctrl = sc_pre1 & ~sc_pre2; - - wire [4:0] command_queue_len; - - fifo_short #(.WIDTH(96)) commandfifo - (.clk(clk),.reset(reset),.clear(clear), - .datain({new_command,new_time}), .src_rdy_i(write_ctrl), .dst_rdy_o(), - .dataout({send_imm_pre,chain_pre,reload_pre,stop_pre,numlines_pre,rcvtime_pre}), - .src_rdy_o(not_empty_ctrl), .dst_rdy_i(read_ctrl), - .occupied(command_queue_len), .space() ); - - reg [33:0] pkt_fifo_line; - - localparam IBS_IDLE = 0; - localparam IBS_WAITING = 1; - localparam IBS_RUNNING = 2; - localparam IBS_OVERRUN = 4; - localparam IBS_BROKENCHAIN = 5; - localparam IBS_LATECMD = 6; - localparam IBS_ZEROLEN = 7; - - wire signal_cmd_done = (lines_left == 1) & (~chain | (not_empty_ctrl & stop_pre)); - wire signal_overrun = (ibs_state == IBS_OVERRUN); - wire signal_brokenchain = (ibs_state == IBS_BROKENCHAIN); - wire signal_latecmd = (ibs_state == IBS_LATECMD); - wire signal_zerolen = (ibs_state == IBS_ZEROLEN); - - // Buffer of samples for while we're writing the packet headers - wire [4:0] flags = {signal_zerolen,signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done}; - - wire attempt_sample_write = ((run & strobe) | (ibs_state==IBS_OVERRUN) | - (ibs_state==IBS_BROKENCHAIN) | (ibs_state==IBS_LATECMD) | - (ibs_state==IBS_ZEROLEN)); - - fifo_short #(.WIDTH(5+64+WIDTH)) rx_sample_fifo - (.clk(clk),.reset(reset),.clear(clear), - .datain({flags,vita_time,sample}), .src_rdy_i(attempt_sample_write), .dst_rdy_o(sample_fifo_in_rdy), - .dataout(sample_fifo_o), - .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i), - .space(), .occupied() ); - - // Inband Signalling State Machine - time_compare - time_compare (.time_now(vita_time), .trigger_time(rcvtime), .now(now), .early(early), .late(late)); - - wire go_now = now | send_imm; - wire full = ~sample_fifo_in_rdy; - - reg too_late; - - always @(posedge clk) - if(reset | clear) - too_late <= 0; - else - too_late <= late & ~send_imm; - - reg late_valid; - - always @(posedge clk) - if(reset | clear) - begin - ibs_state <= IBS_IDLE; - lines_left <= 0; - lines_total <= 0; - rcvtime <= 0; - send_imm <= 0; - chain <= 0; - reload <= 0; - late_valid <= 0; - end - else - case(ibs_state) - IBS_IDLE : - if(not_empty_ctrl) - begin - lines_left <= numlines_pre; - lines_total <= numlines_pre; - rcvtime <= rcvtime_pre; - late_valid <= 0; - if(stop_pre) - ibs_state <= IBS_ZEROLEN; - else - ibs_state <= IBS_WAITING; - send_imm <= send_imm_pre; - chain <= chain_pre; - reload <= reload_pre; - end - IBS_WAITING : - begin - late_valid <= 1; - if(late_valid) - if(go_now) - ibs_state <= IBS_RUNNING; - else if(too_late) - ibs_state <= IBS_LATECMD; - end - IBS_RUNNING : - if(strobe) - if(full) - ibs_state <= IBS_OVERRUN; - else - begin - lines_left <= lines_left - 1; - if(lines_left == 1) - if(~chain) - ibs_state <= IBS_IDLE; - else if(~not_empty_ctrl & reload) - begin - ibs_state <= IBS_RUNNING; - lines_left <= lines_total; - end - else if(~not_empty_ctrl) - ibs_state <= IBS_BROKENCHAIN; - else - begin - lines_left <= numlines_pre; - lines_total <= numlines_pre; - rcvtime <= rcvtime_pre; - send_imm <= send_imm_pre; - chain <= chain_pre; - reload <= reload_pre; - if(stop_pre) // If we are told to stop here - ibs_state <= IBS_IDLE; - else - ibs_state <= IBS_RUNNING; - end - end // else: !if(full) - IBS_OVERRUN : - if(sample_fifo_in_rdy) - ibs_state <= IBS_IDLE; - IBS_LATECMD : - if(sample_fifo_in_rdy) - ibs_state <= IBS_IDLE; - IBS_BROKENCHAIN : - if(sample_fifo_in_rdy) - ibs_state <= IBS_IDLE; - IBS_ZEROLEN : - if(sample_fifo_in_rdy) - ibs_state <= IBS_IDLE; - endcase // case(ibs_state) - - assign overrun = (ibs_state == IBS_OVERRUN); - assign run = (ibs_state == IBS_RUNNING); - - assign read_ctrl = ( (ibs_state == IBS_IDLE) | ((ibs_state == IBS_RUNNING) & strobe & ~full & (lines_left==1) & chain) ) - & not_empty_ctrl; - - assign debug_rx = { { ibs_state[2:0], command_queue_len }, - { 8'd0 }, - { go_now, too_late, run, strobe, read_ctrl, write_ctrl, 1'b0, ~not_empty_ctrl }, - { 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} }; - -endmodule // vita_rx_control diff --git a/fpga/usrp2/vrt/vita_rx_engine_glue.v b/fpga/usrp2/vrt/vita_rx_engine_glue.v deleted file mode 100644 index 56447a7aa..000000000 --- a/fpga/usrp2/vrt/vita_rx_engine_glue.v +++ /dev/null @@ -1,95 +0,0 @@ -// -// Copyright 2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -//The following module is used to re-write receive packets to the host. -//This module provides a packet-based ram interface for manipulating packets. -//By default, this module uses the built-in 16 to 8 bit converter engine. - -module vita_rx_engine_glue -#( - //the dsp unit number: 0, 1, 2... - parameter DSPNO = 0, - - //buffer size for ram interface engine - parameter BUF_SIZE = 10, - - //base address for built-in settings registers used in this module - parameter MAIN_SETTINGS_BASE = 0 -) -( - //control signals - input clock, input reset, input clear, - - //main settings bus for built-in modules - input set_stb_main, input [7:0] set_addr_main, input [31:0] set_data_main, - - //user settings bus, controlled through user setting regs API - input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user, - - //ram interface for engine - output access_we, - output access_stb, - input access_ok, - output access_done, - output access_skip_read, - output [BUF_SIZE-1:0] access_adr, - input [BUF_SIZE-1:0] access_len, - output [35:0] access_dat_o, - input [35:0] access_dat_i, - - //debug output (optional) - output [31:0] debug -); - - generate - if (DSPNO==0) begin - `ifndef RX_ENG0_MODULE - dspengine_16to8 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE)) dspengine_16to8 - (.clk(clock),.reset(reset),.clear(clear), - .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); - `else - `RX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng0_custom - (.clock(clock),.reset(reset),.clear(clear), - .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); - `endif - end - else begin - `ifndef RX_ENG1_MODULE - dspengine_16to8 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE)) dspengine_16to8 - (.clk(clock),.reset(reset),.clear(clear), - .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); - `else - `RX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng1_custom - (.clock(clock),.reset(reset),.clear(clear), - .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); - `endif - end - endgenerate - -endmodule //vita_rx_engine_glue diff --git a/fpga/usrp2/vrt/vita_rx_framer.v b/fpga/usrp2/vrt/vita_rx_framer.v deleted file mode 100644 index 6e4b8025d..000000000 --- a/fpga/usrp2/vrt/vita_rx_framer.v +++ /dev/null @@ -1,224 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module vita_rx_framer - #(parameter BASE=0, - parameter MAXCHAN=1) - (input clk, input reset, input clear, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - // To FIFO interface of Buffer Pool - output [35:0] data_o, - input dst_rdy_i, - output src_rdy_o, - - // From vita_rx_control - input [5+64+(32*MAXCHAN)-1:0] sample_fifo_i, - input sample_fifo_src_rdy_i, - output sample_fifo_dst_rdy_o, - - output [31:0] debug_rx - ); - - localparam SAMP_WIDTH = 5+64+(32*MAXCHAN); - reg [3:0] sample_phase; - wire [3:0] numchan; - wire [4:0] flags_fifo_o = sample_fifo_i[SAMP_WIDTH-1:SAMP_WIDTH-5]; - wire [63:0] vita_time_fifo_o = sample_fifo_i[SAMP_WIDTH-6:SAMP_WIDTH-69]; - - reg [31:0] data_fifo_o; - - // The tools won't synthesize properly without this kludge because of the variable - // parameter length - - wire [127:0] FIXED_WIDTH_KLUDGE = sample_fifo_i; - always @* - case(sample_phase) - 4'd0 : data_fifo_o = FIXED_WIDTH_KLUDGE[31:0]; - 4'd1 : data_fifo_o = FIXED_WIDTH_KLUDGE[63:32]; - 4'd2 : data_fifo_o = FIXED_WIDTH_KLUDGE[95:64]; - 4'd3 : data_fifo_o = FIXED_WIDTH_KLUDGE[127:96]; - default : data_fifo_o = 32'hDEADBEEF; - endcase // case (sample_phase) - - wire clear_pkt_count, pkt_fifo_rdy, sample_fifo_in_rdy; - - wire [31:0] vita_header, vita_streamid, vita_trailer; - wire [15:0] samples_per_packet; - - reg [33:0] pkt_fifo_line; - reg [3:0] vita_state; - reg [15:0] sample_ctr; - reg [3:0] pkt_count; - - wire [15:0] vita_pkt_len = samples_per_packet + 6; - //wire [4:0] flags = {signal_zerolen,signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done}; - - setting_reg #(.my_addr(BASE+4)) sr_header - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(vita_header),.changed()); - - setting_reg #(.my_addr(BASE+5)) sr_streamid - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(vita_streamid),.changed(clear_pkt_count)); - - setting_reg #(.my_addr(BASE+6)) sr_trailer - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(vita_trailer),.changed()); - - setting_reg #(.my_addr(BASE+7),.width(16)) sr_samples_per_pkt - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(samples_per_packet),.changed()); - - assign numchan = 0;/* - setting_reg #(.my_addr(BASE+8),.width(4), .at_reset(0)) sr_numchan - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(numchan),.changed()); - */ - - // Output FIFO for packetized data - localparam VITA_IDLE = 0; - localparam VITA_HEADER = 1; - localparam VITA_STREAMID = 2; - localparam VITA_TICS = 3; - localparam VITA_TICS2 = 4; - localparam VITA_PAYLOAD = 5; - localparam VITA_TRAILER = 6; - localparam VITA_ERR_HEADER = 7; // All ERR at 4'b1000 or'ed with base - localparam VITA_ERR_STREAMID = 8; - localparam VITA_ERR_TICS = 9; - localparam VITA_ERR_TICS2 = 10; - localparam VITA_ERR_PAYLOAD = 11; - localparam VITA_ERR_TRAILER = 12; // Extension context packets have no trailer - - always @(posedge clk) - if(reset | clear | clear_pkt_count) - pkt_count <= 0; - else if((vita_state == VITA_TRAILER) & pkt_fifo_rdy) - pkt_count <= pkt_count + 1; - - wire has_streamid = vita_header[28]; - wire has_trailer = vita_header[26]; - reg trl_eob; - - always @* - case(vita_state) - // Data packets are IF Data packets with or w/o streamid, no classid, with trailer - VITA_HEADER : pkt_fifo_line <= {2'b01,3'b000,vita_header[28],2'b01,vita_header[25:24], - vita_header[23:20],pkt_count[3:0],vita_pkt_len[15:0]}; - VITA_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid}; - VITA_TICS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]}; - VITA_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]}; - VITA_PAYLOAD : pkt_fifo_line <= {2'b00,data_fifo_o}; - VITA_TRAILER : pkt_fifo_line <= {2'b10,vita_trailer[31:21],1'b1,vita_trailer[19:9],trl_eob,8'd0}; - - // Error packets are Extension Context packets, which have no trailer - VITA_ERR_HEADER : pkt_fifo_line <= {2'b01,4'b0101,4'b0000,vita_header[23:20],pkt_count,16'd5}; - VITA_ERR_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid}; - VITA_ERR_TICS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]}; - VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]}; - VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b10,27'd0,flags_fifo_o}; - //VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer}; - - default : pkt_fifo_line <= 34'h0_FFFF_FFFF; - endcase // case (vita_state) - - always @(posedge clk) - if(reset | clear) - begin - vita_state <= VITA_IDLE; - sample_ctr <= 0; - sample_phase <= 0; - end - else - if(vita_state==VITA_IDLE) - begin - sample_ctr <= 1; - sample_phase <= 0; - if(sample_fifo_src_rdy_i) - if(|flags_fifo_o[4:1]) - vita_state <= VITA_ERR_HEADER; - else - vita_state <= VITA_HEADER; - end - else if(pkt_fifo_rdy) - case(vita_state) - VITA_HEADER : - if(has_streamid) - vita_state <= VITA_STREAMID; - else - vita_state <= VITA_TICS; - VITA_PAYLOAD : - if(sample_fifo_src_rdy_i) - begin - if(sample_phase == numchan) - begin - sample_phase <= 0; - sample_ctr <= sample_ctr + 1; - trl_eob <= flags_fifo_o[0]; - if(sample_ctr == samples_per_packet) - vita_state <= VITA_TRAILER; - if(|flags_fifo_o) // end early if any flag is set - vita_state <= VITA_TRAILER; - end - else - sample_phase <= sample_phase + 1; - end // if (sample_fifo_src_rdy_i) - VITA_ERR_PAYLOAD : - vita_state <= VITA_IDLE; - VITA_TRAILER : - vita_state <= VITA_IDLE; - default : - vita_state <= vita_state + 1; - endcase // case (vita_state) - - reg req_write_pkt_fifo; - always @* - case(vita_state) - VITA_IDLE : - req_write_pkt_fifo <= 0; - VITA_HEADER, VITA_STREAMID, VITA_TICS, VITA_TICS2, VITA_TRAILER : - req_write_pkt_fifo <= 1; - VITA_PAYLOAD : - // Write if sample ready and no error flags - req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[4:1]); - VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_TICS, VITA_ERR_TICS2, VITA_ERR_PAYLOAD : - req_write_pkt_fifo <= 1; - default : - req_write_pkt_fifo <= 0; - endcase // case (vita_state) - - //wire req_write_pkt_fifo = (vita_state != VITA_IDLE) & (sample_fifo_src_rdy_i | (vita_state != VITA_PAYLOAD)); - - // Short FIFO to buffer between us and the FIFOs outside - fifo_short #(.WIDTH(34)) rx_pkt_fifo - (.clk(clk), .reset(reset), .clear(clear), - .datain(pkt_fifo_line), .src_rdy_i(req_write_pkt_fifo), .dst_rdy_o(pkt_fifo_rdy), - .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), - .space(),.occupied() ); - - assign data_o[35:34] = 2'b00; // Always write full lines - assign sample_fifo_dst_rdy_o = pkt_fifo_rdy & - ( ((vita_state==VITA_PAYLOAD) & - (sample_phase == numchan) & - ~|flags_fifo_o[4:1]) | - (vita_state==VITA_ERR_PAYLOAD)); - - assign debug_rx = vita_state; - -endmodule // vita_rx_framer diff --git a/fpga/usrp2/vrt/vita_rx_tb.v b/fpga/usrp2/vrt/vita_rx_tb.v deleted file mode 100644 index 8cd08a972..000000000 --- a/fpga/usrp2/vrt/vita_rx_tb.v +++ /dev/null @@ -1,246 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module vita_rx_tb; - - localparam DECIM = 8'd4; - localparam MAXCHAN=1; - localparam NUMCHAN=1; - - reg clk = 0; - reg reset = 1; - - initial #1000 reset = 0; - always #50 clk = ~clk; - - initial $dumpfile("vita_rx_tb.vcd"); - initial $dumpvars(0,vita_rx_tb); - - wire [(MAXCHAN*32)-1:0] sample; - wire strobe, run; - wire [35:0] data_o; - wire src_rdy; - reg dst_rdy = 1; - wire [63:0] vita_time; - - reg set_stb = 0; - reg [7:0] set_addr; - reg [31:0] set_data; - wire set_stb_dsp; - wire [7:0] set_addr_dsp; - wire [31:0] set_data_dsp; - - /* - settings_bus_crossclock settings_bus_xclk_dsp - (.clk_i(clk), .rst_i(reset), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), - .clk_o(clk), .rst_o(reset), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); - */ - - wire sample_dst_rdy, sample_src_rdy; - //wire [99:0] sample_data_o; - wire [64+5+(MAXCHAN*32)-1:0] sample_data_o; - - vita_rx_control #(.BASE(0), .WIDTH(32*MAXCHAN)) vita_rx_control - (.clk(clk), .reset(reset), .clear(0), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .vita_time(vita_time), .overrun(overrun), - .sample_fifo_o(sample_data_o), .sample_fifo_dst_rdy_i(sample_dst_rdy), .sample_fifo_src_rdy_o(sample_src_rdy), - .sample(sample), .run(run), .strobe(strobe)); - - vita_rx_framer #(.BASE(0), .MAXCHAN(MAXCHAN)) vita_rx_framer - (.clk(clk), .reset(reset), .clear(0), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .data_o(data_o), .dst_rdy_i(dst_rdy), .src_rdy_o(src_rdy), - .sample_fifo_i(sample_data_o), .sample_fifo_dst_rdy_o(sample_dst_rdy), .sample_fifo_src_rdy_i(sample_src_rdy), - .fifo_occupied(), .fifo_full(), .fifo_empty() ); - - rx_dsp_model rx_dsp_model - (.clk(clk), .reset(reset), .run(run), .decim(DECIM), .strobe(strobe), .sample(sample[31:0])); - - generate - if(MAXCHAN>1) - assign sample[(MAXCHAN*32)-1:32] = 0; - endgenerate - - time_64bit #(.TICKS_PER_SEC(120000000), .BASE(0)) time_64bit - (.clk(clk), .rst(reset), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .pps(0), .vita_time(vita_time)); - - always @(posedge clk) - if(src_rdy & dst_rdy) - begin - if(data_o[32] & ~data_o[33]) - begin - $display("RX-PKT-START %d",$time); - $display(" RX-PKT-DAT %x",data_o[31:0]); - end - else if(data_o[32] & data_o[33]) - begin - $display(" RX-PKT-DAT %x -- With ERR",data_o[31:0]); - $display("RX-PKT-ERR %d",$time); - end - else if(~data_o[32] & data_o[33]) - begin - $display(" RX-PKT-DAT %x",data_o[31:0]); - $display("RX-PKT-END %d",$time); - end - else - $display(" RX-PKT DAT %x",data_o[31:0]); - end - - initial - begin - @(negedge reset); - @(posedge clk); - write_setting(4,32'h15F00000); // VITA header - write_setting(5,32'hF00D1234); // VITA streamid - write_setting(6,32'hE0000000); // VITA trailer - write_setting(7,8); // Samples per VITA packet - write_setting(8,NUMCHAN); // Vector length - - queue_rx_cmd(1,1,0,10,32'h0,32'h0); // send imm, single packet - #10000; - - queue_rx_cmd(1,0,0,0,32'h0,32'h0); // send imm, single packet - //queue_rx_cmd(1,1,0,0,32'h0,32'h0); // send imm, single packet - - //queue_rx_cmd(1,0,0,0,32'h0,32'h0); // send imm, single packet - - /* - queue_rx_cmd(1,0,0,8,32'h0,32'h0); // send imm, single packet - queue_rx_cmd(1,0,0,16,32'h0,32'h0); // send imm, 2 packets worth - queue_rx_cmd(1,0,0,7,32'h0,32'h0); // send imm, 1 short packet worth - queue_rx_cmd(1,0,0,9,32'h0,32'h0); // send imm, just longer than 1 packet - - queue_rx_cmd(1,1,0,16,32'h0,32'h0); // chained - queue_rx_cmd(0,0,0,8,32'h0,32'h0); // 2nd in chain - - queue_rx_cmd(1,1,0,17,32'h0,32'h0); // chained, odd length - queue_rx_cmd(0,0,0,9,32'h0,32'h0); // 2nd in chain, also odd length - - queue_rx_cmd(0,0,0,8,32'h0,32'h340); // send at, on time - queue_rx_cmd(0,0,0,8,32'h0,32'h100); // send at, but late - - #100000; - $display("\nChained, break chain\n"); - queue_rx_cmd(1,1,0,8,32'h0,32'h0); // chained, but break chain - #100000; - $display("\nSingle packet\n"); - queue_rx_cmd(1,0,0,8,32'h0,32'h0); // send imm, single packet - #100000; - $display("\nEnd chain with zero samples, shouldn't error\n"); - queue_rx_cmd(1,1,0,8,32'h0,32'h0); // chained - queue_rx_cmd(0,0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error - #100000; - - $display("\nEnd chain with zero samples on odd-length, shouldn't error\n"); - queue_rx_cmd(1,1,0,14,32'h0,32'h0); // chained - queue_rx_cmd(0,0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error - #100000; - $display("Should have gotten 14 samples and EOF by now\n"); - - queue_rx_cmd(1,1,0,9,32'h0,32'h0); // chained, but break chain, odd length - #100000; - dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun - queue_rx_cmd(1,0,0,100,32'h0,32'h0); // long enough to fill the fifos - queue_rx_cmd(1,0,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent - #100000; - dst_rdy <= 1; // restart the reads so we can see what we got - #100000; - dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun - queue_rx_cmd(1,1,0,100,32'h0,32'h0); // long enough to fill the fifos - //queue_rx_cmd(1,0,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent - #100000; - @(posedge clk); - dst_rdy <= 1; - */ - #100000 $finish; - end - - task write_setting; - input [7:0] addr; - input [31:0] data; - begin - set_stb <= 0; - @(posedge clk); - set_addr <= addr; - set_data <= data; - set_stb <= 1; - @(posedge clk); - set_stb <= 0; - end - endtask // write_setting - - task queue_rx_cmd; - input send_imm; - input chain; - input reload; - input [28:0] lines; - input [31:0] secs; - input [31:0] tics; - begin - write_setting(0,{send_imm,chain,reload,lines}); - write_setting(1,secs); - write_setting(2,tics); - end - endtask // queue_rx_cmd - -endmodule // rx_control_tb - -module rx_dsp_model - (input clk, input reset, - input run, - input [7:0] decim, - output strobe, - output [31:0] sample); - - reg [15:0] pktnum = 0; - reg [15:0] counter = 0; - - reg run_d1; - always @(posedge clk) run_d1 <= run; - - always @(posedge clk) - if(run & ~run_d1) - begin - counter <= 0; - pktnum <= pktnum + 1; - end - else if(run & strobe) - counter <= counter + 1; - - assign sample = {pktnum,counter}; - - reg [7:0] stb_ctr = 0; - - always @(posedge clk) - if(reset) - stb_ctr <= 0; - else if(run & ~run_d1) - stb_ctr <= 1; - else if(run) - if(stb_ctr == decim-1) - stb_ctr <= 0; - else - stb_ctr <= stb_ctr + 1; - - assign strobe = stb_ctr == decim-1; - -endmodule // rx_dsp_model diff --git a/fpga/usrp2/vrt/vita_tx.build b/fpga/usrp2/vrt/vita_tx.build deleted file mode 100755 index e7106aa10..000000000 --- a/fpga/usrp2/vrt/vita_tx.build +++ /dev/null @@ -1 +0,0 @@ -iverilog -Wimplict -Wportbind -y ../sdr_lib -y ../models -y . -y ../control_lib/ -y ../fifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_tx_tb vita_tx_tb.v diff --git a/fpga/usrp2/vrt/vita_tx_chain.v b/fpga/usrp2/vrt/vita_tx_chain.v deleted file mode 100644 index 82a43d57a..000000000 --- a/fpga/usrp2/vrt/vita_tx_chain.v +++ /dev/null @@ -1,162 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module vita_tx_chain - #(parameter BASE=0, - parameter FIFOSIZE=10, - parameter POST_ENGINE_FIFOSIZE=10, - parameter REPORT_ERROR=0, - parameter DO_FLOW_CONTROL=0, - parameter PROT_ENG_FLAGS=0, - parameter USE_TRANS_HEADER=0, - parameter DSP_NUMBER=0) - (input clk, input reset, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user, - input [63:0] vita_time, - input [35:0] tx_data_i, input tx_src_rdy_i, output tx_dst_rdy_o, - output [35:0] err_data_o, output err_src_rdy_o, input err_dst_rdy_i, - output [31:0] sample, input strobe, - output underrun, output run, output clear_o, - output [31:0] debug); - - localparam MAXCHAN = 1; - localparam FIFOWIDTH = 5+64+16+(32*MAXCHAN); - - wire [FIFOWIDTH-1:0] tx1_data; - wire tx1_src_rdy, tx1_dst_rdy; - wire [31:0] streamid, message; - wire trigger, sent; - wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; - - wire error, packet_consumed, ack; - wire [31:0] error_code; - wire clear_seqnum; - wire [31:0] current_seqnum; - - wire clear, flush; - assign clear_o = clear; - assign underrun = error; - assign message = error_code; - - setting_reg #(.my_addr(BASE+0), .width(1)) sr - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(flush),.changed(clear)); - - setting_reg #(.my_addr(BASE+2), .at_reset(0)) sr_streamid - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(streamid),.changed(clear_seqnum)); - - //flush control - full rate vacuum of input until flush cleared - wire tx_dst_rdy_int, tx_src_rdy_int; - wire [35:0] tx_data_int; - valve36 flusher_valve - (.clk(clk), .reset(reset), .clear(clear & flush), .shutoff(flush), - .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o), - .data_o(tx_data_int), .src_rdy_o(tx_src_rdy_int), .dst_rdy_i(tx_dst_rdy_int)); - - wire [35:0] tx_data_int1; - wire tx_src_rdy_int1, tx_dst_rdy_int1; - - generate - if (FIFOSIZE==0) begin - assign tx_data_int1 = tx_data_int; - assign tx_src_rdy_int1 = tx_src_rdy_int; - assign tx_dst_rdy_int = tx_dst_rdy_int1; - end - else begin - wire [FIFOSIZE-1:0] access_adr, access_len; - wire access_we, access_stb, access_ok, access_done, access_skip_read; - wire [35:0] dsp_to_buf, buf_to_dsp; - wire [35:0] tx_data_int0; - wire tx_src_rdy_int0, tx_dst_rdy_int0; - - double_buffer #(.BUF_SIZE(FIFOSIZE)) db - (.clk(clk),.reset(reset),.clear(clear), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(dsp_to_buf), .access_dat_o(buf_to_dsp), - - .data_i(tx_data_int), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int), - .data_o(tx_data_int0), .src_rdy_o(tx_src_rdy_int0), .dst_rdy_i(tx_dst_rdy_int0)); - - vita_tx_engine_glue #(.DSPNO(DSP_NUMBER), .MAIN_SETTINGS_BASE(BASE+1), .BUF_SIZE(FIFOSIZE), .HEADER_OFFSET(USE_TRANS_HEADER)) dspengine_tx - (.clock(clk),.reset(reset),.clear(clear), - .set_stb_main(set_stb), .set_addr_main(set_addr), .set_data_main(set_data), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf)); - - fifo_cascade #(.WIDTH(36), .SIZE(POST_ENGINE_FIFOSIZE)) post_engine_buffering( - .clk(clk), .reset(reset), .clear(clear), - .datain(tx_data_int0), .src_rdy_i(tx_src_rdy_int0), .dst_rdy_o(tx_dst_rdy_int0), - .dataout(tx_data_int1), .src_rdy_o(tx_src_rdy_int1), .dst_rdy_i(tx_dst_rdy_int1)); - - end - endgenerate - - vita_tx_deframer #(.BASE(BASE), - .MAXCHAN(MAXCHAN), - .USE_TRANS_HEADER(USE_TRANS_HEADER)) - vita_tx_deframer - (.clk(clk), .reset(reset), .clear(clear), .clear_seqnum(clear_seqnum), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .data_i(tx_data_int1), .src_rdy_i(tx_src_rdy_int1), .dst_rdy_o(tx_dst_rdy_int1), - .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), - .current_seqnum(current_seqnum), - .debug(debug_vtd) ); - - vita_tx_control #(.BASE(BASE), .WIDTH(32*MAXCHAN)) vita_tx_control - (.clk(clk), .reset(reset), .clear(clear), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), .error(error), .ack(ack), .error_code(error_code), - .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), - .sample(sample), .run(run), .strobe(strobe), .packet_consumed(packet_consumed), - .debug(debug_vtc) ); - - wire [35:0] flow_data, err_data_int; - wire flow_src_rdy, flow_dst_rdy, err_src_rdy_int, err_dst_rdy_int; - - gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS),.DSP_NUMBER(DSP_NUMBER)) gen_flow_pkt - (.clk(clk), .reset(reset), .clear(clear), - .trigger(trigger & (DO_FLOW_CONTROL==1)), .sent(), - .streamid(streamid), .vita_time(vita_time), .message(32'd0), - .seqnum(current_seqnum), - .data_o(flow_data), .src_rdy_o(flow_src_rdy), .dst_rdy_i(flow_dst_rdy)); - trigger_context_pkt #(.BASE(BASE)) trigger_context_pkt - (.clk(clk), .reset(reset), .clear(clear), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .packet_consumed(packet_consumed), .trigger(trigger)); - - gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS),.DSP_NUMBER(DSP_NUMBER)) gen_tx_err_pkt - (.clk(clk), .reset(reset), .clear(clear), - .trigger((error|ack) & (REPORT_ERROR==1)), .sent(), - .streamid(streamid), .vita_time(vita_time), .message(message), - .seqnum(current_seqnum), - .data_o(err_data_int), .src_rdy_o(err_src_rdy_int), .dst_rdy_i(err_dst_rdy_int)); - - assign debug = debug_vtc | debug_vtd; - - fifo36_mux #(.prio(1)) mux_err_and_flow // Priority to err messages - (.clk(clk), .reset(reset), .clear(0), // Don't clear this or it could get clogged - .data0_i(err_data_int), .src0_rdy_i(err_src_rdy_int), .dst0_rdy_o(err_dst_rdy_int), - .data1_i(flow_data), .src1_rdy_i(flow_src_rdy), .dst1_rdy_o(flow_dst_rdy), - .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); - -endmodule // vita_tx_chain diff --git a/fpga/usrp2/vrt/vita_tx_control.v b/fpga/usrp2/vrt/vita_tx_control.v deleted file mode 100644 index c3ce2b96a..000000000 --- a/fpga/usrp2/vrt/vita_tx_control.v +++ /dev/null @@ -1,238 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module vita_tx_control - #(parameter BASE=0, - parameter WIDTH=32) - (input clk, input reset, input clear, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - input [63:0] vita_time, - output error, output ack, - output reg [31:0] error_code, - output reg packet_consumed, - - // From vita_tx_deframer - input [5+64+16+WIDTH-1:0] sample_fifo_i, - input sample_fifo_src_rdy_i, - output sample_fifo_dst_rdy_o, - - // To DSP Core - output [WIDTH-1:0] sample, - output reg run, - input strobe, - - output [31:0] debug - ); - - wire [63:0] send_time = sample_fifo_i[63:0]; - wire [15:0] seqnum = sample_fifo_i[79:64]; - wire eop = sample_fifo_i[80]; - wire eob = sample_fifo_i[81]; - wire sob = sample_fifo_i[82]; - wire send_at = sample_fifo_i[83]; - wire seqnum_err = sample_fifo_i[84]; - - wire now, early, late, too_early; - - time_compare - time_compare (.time_now(vita_time), .trigger_time(send_time), - .now(now), .early(early), .late(late), .too_early(too_early)); - - reg late_qual, late_del; - - always @(posedge clk) - if(reset | clear) - late_del <= 0; - else - late_del <= late; - - always @(posedge clk) - if(reset | clear) - late_qual <= 0; - else - late_qual <= (sample_fifo_src_rdy_i & ~sample_fifo_dst_rdy_o); - - localparam IBS_IDLE = 0; - localparam IBS_RUN = 1; // FIXME do we need this? - localparam IBS_CONT_BURST = 2; - localparam IBS_ERROR = 3; - localparam IBS_ERROR_DONE = 4; - localparam IBS_ERROR_WAIT = 5; - - wire [31:0] CODE_EOB_ACK = {seqnum,16'd1}; - wire [31:0] CODE_UNDERRUN = {seqnum,16'd2}; - wire [31:0] CODE_SEQ_ERROR = {seqnum,16'd4}; - wire [31:0] CODE_TIME_ERROR = {seqnum,16'd8}; - wire [31:0] CODE_UNDERRUN_MIDPKT = {seqnum,16'd16}; - wire [31:0] CODE_SEQ_ERROR_MIDBURST = {seqnum,16'd32}; - - reg [2:0] ibs_state; - - wire [31:0] error_policy; - setting_reg #(.my_addr(BASE+3)) sr_error_policy - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(error_policy),.changed()); - - wire policy_wait = error_policy[0]; - wire policy_next_packet = error_policy[1]; - wire policy_next_burst = error_policy[2]; - reg send_error, send_ack; - - always @(posedge clk) - if(reset | clear) - begin - ibs_state <= IBS_IDLE; - send_error <= 0; - send_ack <= 0; - error_code <= 0; - end - else - case(ibs_state) - IBS_IDLE : - if(sample_fifo_src_rdy_i) - if(seqnum_err) - begin - ibs_state <= IBS_ERROR; - error_code <= CODE_SEQ_ERROR; - send_error <= 1; - end - else if(~send_at | now) - ibs_state <= IBS_RUN; - else if((late_qual & late_del) | too_early) - begin - ibs_state <= IBS_ERROR; - error_code <= CODE_TIME_ERROR; - send_error <= 1; - end - - IBS_RUN : - if(strobe) - if(~sample_fifo_src_rdy_i) - begin - ibs_state <= IBS_ERROR; - error_code <= CODE_UNDERRUN_MIDPKT; - send_error <= 1; - end - else if(eop) - if(eob) - begin - ibs_state <= IBS_ERROR_DONE; // Not really an error - error_code <= CODE_EOB_ACK; - send_ack <= 1; - end - else - ibs_state <= IBS_CONT_BURST; - - IBS_CONT_BURST : - if(strobe) - begin - if(policy_next_packet) - ibs_state <= IBS_ERROR_DONE; - else if(policy_wait) - ibs_state <= IBS_ERROR_WAIT; - else - ibs_state <= IBS_ERROR; - error_code <= CODE_UNDERRUN; - send_error <= 1; - end - else if(sample_fifo_src_rdy_i) - if(seqnum_err) - begin - ibs_state <= IBS_ERROR; - error_code <= CODE_SEQ_ERROR_MIDBURST; - send_error <= 1; - end - else - ibs_state <= IBS_RUN; - - IBS_ERROR : - begin - send_error <= 0; - if(sample_fifo_src_rdy_i & eop) - if(policy_next_packet | (policy_next_burst & eob)) - ibs_state <= IBS_IDLE; - else if(policy_wait) - ibs_state <= IBS_ERROR_WAIT; - end - - IBS_ERROR_DONE : - begin - send_error <= 0; - send_ack <= 0; - ibs_state <= IBS_IDLE; - end - - IBS_ERROR_WAIT : - send_error <= 0; - endcase // case (ibs_state) - - - assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout - - //register the output sample - reg [31:0] sample_held; - assign sample = sample_held; - always @(posedge clk) - if(reset | clear) - sample_held <= 0; - else if (~run) - sample_held <= 0; - else if (strobe) - sample_held <= sample_fifo_i[5+64+16+WIDTH-1:5+64+16]; - - assign error = send_error; - assign ack = send_ack; - - localparam MAX_IDLE = 1000000; - // approx 10 ms timeout with a 100 MHz clock, but burning samples will slow that down - reg [19:0] countdown; - - always @(posedge clk) - if(reset | clear) - begin - run <= 0; - countdown <= 0; - end - else - if (ibs_state == IBS_RUN) - if(eob & eop & strobe & sample_fifo_src_rdy_i) - run <= 0; - else - begin - run <= 1; - countdown <= MAX_IDLE; - end - else - if (countdown == 0) - run <= 0; - else - countdown <= countdown - 1; - - always @(posedge clk) - if(reset | clear) - packet_consumed <= 0; - else - packet_consumed <= eop & sample_fifo_src_rdy_i & sample_fifo_dst_rdy_o; - - assign debug = { { now,late_qual,late_del,ack,eop,eob,sob,send_at }, - { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] }, - { 8'b0 }, - { 8'b0 } }; - -endmodule // vita_tx_control diff --git a/fpga/usrp2/vrt/vita_tx_deframer.v b/fpga/usrp2/vrt/vita_tx_deframer.v deleted file mode 100644 index ed3916311..000000000 --- a/fpga/usrp2/vrt/vita_tx_deframer.v +++ /dev/null @@ -1,261 +0,0 @@ -// -// Copyright 2011-2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - -module vita_tx_deframer - #(parameter BASE=0, - parameter MAXCHAN=1, - parameter USE_TRANS_HEADER=0) - (input clk, input reset, input clear, input clear_seqnum, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - // To FIFO interface of Buffer Pool - input [35:0] data_i, - input src_rdy_i, - output dst_rdy_o, - - output [5+64+16+(32*MAXCHAN)-1:0] sample_fifo_o, - output sample_fifo_src_rdy_o, - input sample_fifo_dst_rdy_i, - - output [31:0] current_seqnum, - - // FIFO Levels - output [15:0] fifo_occupied, - output fifo_full, - output fifo_empty, - output [31:0] debug - ); - - localparam FIFOWIDTH = 5+64+16+(32*MAXCHAN); - - wire [1:0] numchan = 0;/* - setting_reg #(.my_addr(BASE), .at_reset(0), .width(2)) sr_numchan - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(numchan),.changed()); - */ - - reg [3:0] vita_state; - wire has_streamid, has_classid, has_secs, has_tics, has_trailer; - assign has_streamid = (data_i[31:28]==4'b0001); - assign has_classid = data_i[27]; - assign has_secs = ~(data_i[23:22]==2'b00); - assign has_tics = ~(data_i[21:20]==2'b00); - assign has_trailer = data_i[26]; - wire is_sob = data_i[25]; - wire is_eob = data_i[24]; - wire eof = data_i[33]; - reg has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg; - reg has_trailer_reg, is_sob_reg, is_eob_reg; - - reg [15:0] pkt_len; - reg [1:0] vector_phase; - wire line_done; - - wire [31:0] seqnum = data_i; - reg [31:0] seqnum_reg; - wire [31:0] next_seqnum = seqnum_reg + 32'd1; - wire [3:0] vita_seqnum = data_i[19:16]; - reg [3:0] vita_seqnum_reg; - wire [3:0] next_vita_seqnum = vita_seqnum_reg[3:0] + 4'd1; - reg seqnum_err; - - assign current_seqnum = seqnum_reg; - - // Output FIFO for packetized data - localparam VITA_TRANS_HEADER = 0; - localparam VITA_HEADER = 1; - localparam VITA_STREAMID = 2; - localparam VITA_CLASSID = 3; - localparam VITA_CLASSID2 = 4; - localparam VITA_SECS = 5; - localparam VITA_TICS = 6; - localparam VITA_TICS2 = 7; - localparam VITA_PAYLOAD = 8; - localparam VITA_TRAILER = 10; - localparam VITA_DUMP = 11; - - wire [15:0] hdr_len = 2 + has_streamid_reg + has_classid_reg + has_classid_reg + has_secs_reg + - has_tics_reg + has_tics_reg + has_trailer_reg; - - wire vita_eof = (pkt_len==hdr_len); - wire eop = eof | vita_eof; // FIXME would ignoring eof allow larger VITA packets? - wire fifo_space; - - always @(posedge clk) - if(reset | clear | clear_seqnum) - begin - seqnum_reg <= 32'hFFFF_FFFF; - vita_seqnum_reg <= 4'hF; - end - else - begin - if((vita_state==VITA_TRANS_HEADER) & src_rdy_i) - seqnum_reg <= seqnum; - if((vita_state==VITA_HEADER) & src_rdy_i) - vita_seqnum_reg <= vita_seqnum; - end // else: !if(reset | clear_seqnum) - - always @(posedge clk) - if(reset | clear) - begin - vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; - {has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg} - <= 0; - seqnum_err <= 0; - end - else if(src_rdy_i & dst_rdy_o) begin //valid read - case(vita_state) - VITA_TRANS_HEADER : - begin - seqnum_err <= ~(seqnum == next_seqnum); - vita_state <= VITA_HEADER; - end - VITA_HEADER : - begin - {has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg} - <= {has_streamid, has_classid, has_secs, has_tics, has_trailer, is_sob, is_eob}; - pkt_len <= data_i[15:0]; - vector_phase <= 0; - if(has_streamid) - vita_state <= VITA_STREAMID; - else if(has_classid) - vita_state <= VITA_CLASSID; - else if(has_secs) - vita_state <= VITA_SECS; - else if(has_tics) - vita_state <= VITA_TICS; - else - vita_state <= VITA_PAYLOAD; - seqnum_err <= seqnum_err | ~(vita_seqnum == next_vita_seqnum); - end // case: VITA_HEADER - VITA_STREAMID : - if(has_classid_reg) - vita_state <= VITA_CLASSID; - else if(has_secs_reg) - vita_state <= VITA_SECS; - else if(has_tics_reg) - vita_state <= VITA_TICS; - else - vita_state <= VITA_PAYLOAD; - VITA_CLASSID : - vita_state <= VITA_CLASSID2; - VITA_CLASSID2 : - if(has_secs_reg) - vita_state <= VITA_SECS; - else if(has_tics_reg) - vita_state <= VITA_TICS; - else - vita_state <= VITA_PAYLOAD; - VITA_SECS : - if(has_tics_reg) - vita_state <= VITA_TICS; - else - vita_state <= VITA_PAYLOAD; - VITA_TICS : - vita_state <= VITA_TICS2; - VITA_TICS2 : - vita_state <= VITA_PAYLOAD; - - VITA_PAYLOAD : begin - - //step through each element until line done, then reset - vector_phase <= (line_done)? 0: vector_phase + 1; - - //decrement the packet count after each line - pkt_len <= (line_done)? pkt_len - 1 : pkt_len; - - //end of frame reached, determine next state - //otherwise, keep processing through the payload - if (line_done && vita_eof) begin - - if (eof) begin - vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; - end - else if (has_trailer_reg) begin - vita_state <= VITA_TRAILER; - end - else begin - vita_state <= VITA_DUMP; - end - - end //line_done && vita_eof - - end //end VITA_PAYLOAD - - VITA_TRAILER : - if(eof) - vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; - else - vita_state <= VITA_DUMP; - VITA_DUMP : - if(eof) - vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; - default : - vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; - endcase // case (vita_state) - - end //valid read - - assign line_done = (MAXCHAN == 1)? 1 : (vector_phase == numchan); - - wire [FIFOWIDTH-1:0] fifo_i; - reg [63:0] send_time; - - always @(posedge clk) - case(vita_state) - VITA_TICS : - send_time[63:32] <= data_i[31:0]; - VITA_TICS2 : - send_time[31:0] <= data_i[31:0]; - endcase // case (vita_state) - - //sample registers for de-framing a vector input - reg [31:0] sample_reg [1:0]; - always @(posedge clk) - if(src_rdy_i && dst_rdy_o) - sample_reg[vector_phase] <= data_i[31:0]; - - wire store = (vita_state == VITA_PAYLOAD)? (src_rdy_i && line_done) : 0; - assign dst_rdy_o = (vita_state == VITA_PAYLOAD)? fifo_space : 1; - - fifo_short #(.WIDTH(FIFOWIDTH)) short_tx_q - (.clk(clk), .reset(reset), .clear(clear), - .datain(fifo_i), .src_rdy_i(store), .dst_rdy_o(fifo_space), - .dataout(sample_fifo_o), .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i) ); - - //assign registered/live data to the samples vector - //the numchan'th sample vector is muxed to live data - wire [(32*MAXCHAN)-1:0] samples; - generate - genvar i; - for (i=0; i < MAXCHAN; i = i +1) begin : assign_samples - wire live_data = (i == (MAXCHAN-1))? 1 : numchan == i; - assign samples[32*i + 31:32*i] = (live_data)? data_i[31:0] : sample_reg[i]; - end - endgenerate - - // sob, eob, has_tics (send_at) ignored on all lines except first - assign fifo_i = {samples,seqnum_err,has_tics_reg,is_sob_reg,is_eob_reg,eop, - 12'd0,seqnum_reg[3:0],send_time}; - - assign debug = { { 8'b0 }, - { 8'b0 }, - { eof, line_done, store, fifo_space, src_rdy_i, dst_rdy_o, vector_phase[1:0] }, - { has_secs_reg, is_sob_reg, is_eob_reg, eop, vita_state[3:0] } }; - -endmodule // vita_tx_deframer diff --git a/fpga/usrp2/vrt/vita_tx_engine_glue.v b/fpga/usrp2/vrt/vita_tx_engine_glue.v deleted file mode 100644 index db0d55dee..000000000 --- a/fpga/usrp2/vrt/vita_tx_engine_glue.v +++ /dev/null @@ -1,99 +0,0 @@ -// -// Copyright 2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -//The following module is used to re-write transmit packets from the host. -//This module provides a packet-based ram interface for manipulating packets. -//By default, this module uses the built-in 8 to 16 bit converter engine. - -module vita_tx_engine_glue -#( - //the dsp unit number: 0, 1, 2... - parameter DSPNO = 0, - - //buffer size for ram interface engine - parameter BUF_SIZE = 10, - - //base address for built-in settings registers used in this module - parameter MAIN_SETTINGS_BASE = 0, - - //the number of 32bit lines between start of buffer and vita header - //the metadata before the header should be preserved by the engine - parameter HEADER_OFFSET = 0 -) -( - //control signals - input clock, input reset, input clear, - - //main settings bus for built-in modules - input set_stb_main, input [7:0] set_addr_main, input [31:0] set_data_main, - - //user settings bus, controlled through user setting regs API - input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user, - - //ram interface for engine - output access_we, - output access_stb, - input access_ok, - output access_done, - output access_skip_read, - output [BUF_SIZE-1:0] access_adr, - input [BUF_SIZE-1:0] access_len, - output [35:0] access_dat_o, - input [35:0] access_dat_i, - - //debug output (optional) - output [31:0] debug -); - - generate - if (DSPNO==0) begin - `ifndef TX_ENG0_MODULE - dspengine_8to16 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) dspengine_8to16 - (.clk(clock),.reset(reset),.clear(clear), - .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); - `else - `TX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) tx_eng0_custom - (.clock(clock),.reset(reset),.clear(clear), - .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); - `endif - end - else begin - `ifndef TX_ENG1_MODULE - dspengine_8to16 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) dspengine_8to16 - (.clk(clock),.reset(reset),.clear(clear), - .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); - `else - `TX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) tx_eng1_custom - (.clock(clock),.reset(reset),.clear(clear), - .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); - `endif - end - endgenerate - -endmodule //vita_tx_engine_glue diff --git a/fpga/usrp2/vrt/vita_tx_tb.v b/fpga/usrp2/vrt/vita_tx_tb.v deleted file mode 100644 index b686a8a16..000000000 --- a/fpga/usrp2/vrt/vita_tx_tb.v +++ /dev/null @@ -1,193 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module vita_tx_tb; - - localparam DECIM = 8'd4; - localparam INTERP = 8'd4; - - localparam MAXCHAN=1; - localparam NUMCHAN=1; - - reg clk = 0; - reg reset = 1; - - initial #1000 reset = 0; - always #50 clk = ~clk; - - initial $dumpfile("vita_tx_tb.vcd"); - initial $dumpvars(0,vita_tx_tb); - - wire [(MAXCHAN*32)-1:0] sample, sample_tx; - wire strobe, run; - reg [35:0] data_o = 36'h0; - reg src_rdy = 0; - wire dst_rdy; - - wire [63:0] vita_time; - - reg set_stb = 0; - reg [7:0] set_addr; - reg [31:0] set_data; - wire set_stb_dsp; - wire [7:0] set_addr_dsp; - wire [31:0] set_data_dsp; - - wire sample_dst_rdy, sample_src_rdy; - wire [5+64+16+(MAXCHAN*32)-1:0] sample_data_o, sample_data_tx; - - time_64bit #(.TICKS_PER_SEC(100000000), .BASE(0)) time_64bit - (.clk(clk), .rst(reset), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .pps(0), .vita_time(vita_time)); - - wire [35:0] data_tx; - wire src_rdy_tx, dst_rdy_tx; - wire sample_dst_rdy_tx, sample_src_rdy_tx; - - fifo_long #(.WIDTH(36)) fifo_short - (.clk(clk), .reset(reset), .clear(0), - .datain(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), - .dataout(data_tx), .src_rdy_o(src_rdy_tx), .dst_rdy_i(dst_rdy_tx)); - - vita_tx_deframer #(.BASE(16), .MAXCHAN(MAXCHAN), .USE_TRANS_HEADER(0)) vita_tx_deframer - (.clk(clk), .reset(reset), .clear(0), .clear_seqnum(0), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .data_i(data_tx), .dst_rdy_o(dst_rdy_tx), .src_rdy_i(src_rdy_tx), - .sample_fifo_o(sample_data_tx), - .sample_fifo_dst_rdy_i(sample_dst_rdy_tx), .sample_fifo_src_rdy_o(sample_src_rdy_tx), - .fifo_occupied(), .fifo_full(), .fifo_empty() ); - - vita_tx_control #(.BASE(16), .WIDTH(MAXCHAN*32)) vita_tx_control - (.clk(clk), .reset(reset), .clear(0), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .vita_time(vita_time), .error(underrun), .error_code(), - .sample_fifo_i(sample_data_tx), - .sample_fifo_dst_rdy_o(sample_dst_rdy_tx), .sample_fifo_src_rdy_i(sample_src_rdy_tx), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx)); - - tx_dsp_model tx_dsp_model - (.clk(clk), .reset(reset), .run(run_tx), .interp(INTERP), .strobe(strobe_tx), .sample(sample_tx[31:0] )); - - task write_setting; - input [7:0] addr; - input [31:0] data; - begin - set_stb <= 0; - @(posedge clk); - set_addr <= addr; - set_data <= data; - set_stb <= 1; - @(posedge clk); - set_stb <= 0; - end - endtask // write_setting - - initial - begin - @(negedge reset); - @(posedge clk); - write_setting(4,32'h14900008); // VITA header - write_setting(5,32'hF00D1234); // VITA streamid - write_setting(6,32'h98765432); // VITA trailer - write_setting(7,8); // Samples per VITA packet - write_setting(8,NUMCHAN); // Samples per VITA packet - #10000; - queue_vita_packets(0, 32'h300, 5, 32'h0000_1000, 32'h0, 4'h0, 1, 0, 1); - queue_vita_packets(0, 32'h0, 5, 32'h0000_2000, 32'h0, 4'h1, 0, 0, 0); - queue_vita_packets(0, 32'h0, 5, 32'h0000_3000, 32'h0, 4'h2, 0, 0, 0); - - queue_vita_packets(0, 32'h400, 3, 32'h0000_4000, 32'h0, 4'h3, 1, 0, 1); - queue_vita_packets(0, 32'h0, 3, 32'h0000_5000, 32'h0, 4'h4, 0, 0, 0); - queue_vita_packets(0, 32'h0, 3, 32'h0000_6000, 32'h0, 4'h5, 0, 1, 0); - - #300000 $finish; - end - - task queue_vita_packets; - input [31:0] send_secs; - input [31:0] sendtime; - input [15:0] samples; - input [15:0] word; - input [31:0] trailer; - input [3:0] seqnum; - input sob; - input eob; - input sendat; - - reg [15:0] i; - - begin - src_rdy <= 0; - @(posedge clk); - src_rdy <= 1; - data_o <= {4'b0001,4'h0,1'b0,|trailer,sob,eob,{2{sendat}},1'b0,sendat,seqnum,(16'd1+samples+|trailer+sendat+sendat+sendat)}; // header - @(posedge clk); - //data_o <= {4'b0000,32'h0}; // streamid - //@(posedge clk); - if(sendat) - begin - data_o <= {4'b0000,send_secs}; // SECS - @(posedge clk); - data_o <= {4'b0000,32'h0}; // TICS - @(posedge clk); - data_o <= {4'b0000,sendtime}; // TICS - @(posedge clk); - end - for(i=0;i