From bb0572a960edf54486a4be746c681adaac0fa398 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 23 Nov 2010 13:36:42 -0800 Subject: fpga: performed a forceful checkout of fpga to overwrite with current fpga code --- fpga/usrp2/vrt/vita_tx.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'fpga/usrp2/vrt/vita_tx.build') diff --git a/fpga/usrp2/vrt/vita_tx.build b/fpga/usrp2/vrt/vita_tx.build index 902929c08..e7106aa10 100755 --- a/fpga/usrp2/vrt/vita_tx.build +++ b/fpga/usrp2/vrt/vita_tx.build @@ -1 +1 @@ -iverilog -Wimplict -Wportbind -y ../sdr_lib -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_tx_tb vita_tx_tb.v +iverilog -Wimplict -Wportbind -y ../sdr_lib -y ../models -y . -y ../control_lib/ -y ../fifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_tx_tb vita_tx_tb.v -- cgit v1.2.3