From 8fd2aa80ab7609cc16e5922149c8ec453153c7c8 Mon Sep 17 00:00:00 2001 From: Matthew Crymble Date: Tue, 30 Nov 2021 14:50:14 -0600 Subject: fpga: usrp2: update build tools to use python3 --- fpga/usrp2/top/python/check_inout.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'fpga/usrp2/top/python/check_inout.py') diff --git a/fpga/usrp2/top/python/check_inout.py b/fpga/usrp2/top/python/check_inout.py index ff371d378..49330344b 100755 --- a/fpga/usrp2/top/python/check_inout.py +++ b/fpga/usrp2/top/python/check_inout.py @@ -23,8 +23,8 @@ import sys import re if __name__=='__main__': - if len(sys.argv) == 2: - print "Usage: %s " + if len(sys.argv) != 3: + print("Usage: {} ".format(sys.argv[0])) sys.exit(-1) verilog_filename = sys.argv[1] @@ -52,11 +52,11 @@ if __name__=='__main__': for item in verilog_iolist: if item not in ucf_iolist: - print "Error: %s appears in the top-level Verilog file, but is not in the UCF definition file!" % item + print("Error: {} appears in the top-level Verilog file, but is not in the UCF definition file!".format(item)) err = True if err: sys.exit(-1) - print "No errors found." + print("No errors found.") sys.exit(0) -- cgit v1.2.3