From fd3e84941de463fa1a7ebab0a69515b4bf2614cd Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Tue, 7 Oct 2014 11:25:20 +0200 Subject: Removed copy of FPGA source files. --- fpga/usrp2/top/E1x0/core_compile | 3 --- 1 file changed, 3 deletions(-) delete mode 100755 fpga/usrp2/top/E1x0/core_compile (limited to 'fpga/usrp2/top/E1x0/core_compile') diff --git a/fpga/usrp2/top/E1x0/core_compile b/fpga/usrp2/top/E1x0/core_compile deleted file mode 100755 index ab992f29d..000000000 --- a/fpga/usrp2/top/E1x0/core_compile +++ /dev/null @@ -1,3 +0,0 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../B100 -y $XILINX/verilog/src/unisims E1x0.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models - - -- cgit v1.2.3