From 05d77f772317de5d925301aa11bb9a880656dd05 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 15 Apr 2010 11:24:24 -0700 Subject: moved usrp1 and usrp2 fpga dirs into fpga subdirectory --- fpga/usrp2/serdes/serdes_fc_tx.v | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 fpga/usrp2/serdes/serdes_fc_tx.v (limited to 'fpga/usrp2/serdes/serdes_fc_tx.v') diff --git a/fpga/usrp2/serdes/serdes_fc_tx.v b/fpga/usrp2/serdes/serdes_fc_tx.v new file mode 100644 index 000000000..2fe967c8d --- /dev/null +++ b/fpga/usrp2/serdes/serdes_fc_tx.v @@ -0,0 +1,24 @@ + + +module serdes_fc_tx + (input clk, input rst, + input xon_rcvd, input xoff_rcvd, output reg inhibit_tx); + + // XOFF means stop sending, XON means start sending + // clock domain stuff happens elsewhere, everything here is on main clk + + reg [15:0] state; + always @(posedge clk) + if(rst) + state <= 0; + else if(xoff_rcvd) + state <= 255; + else if(xon_rcvd) + state <= 0; + else if(state !=0) + state <= state - 1; + + always @(posedge clk) + inhibit_tx <= (state != 0); + +endmodule // serdes_fc_tx -- cgit v1.2.3