From 05d77f772317de5d925301aa11bb9a880656dd05 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Thu, 15 Apr 2010 11:24:24 -0700
Subject: moved usrp1 and usrp2 fpga dirs into fpga subdirectory

---
 fpga/usrp2/sdr_lib/rx_dcoffset_tb.v | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 fpga/usrp2/sdr_lib/rx_dcoffset_tb.v

(limited to 'fpga/usrp2/sdr_lib/rx_dcoffset_tb.v')

diff --git a/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v b/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v
new file mode 100644
index 000000000..a8b4ec20f
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v
@@ -0,0 +1,25 @@
+
+`timescale 1ns/1ns
+module rx_dcoffset_tb();
+   
+   reg clk, rst;
+
+   initial rst = 1;
+   initial #1000 rst = 0;
+   initial clk = 0;
+   always #5 clk = ~clk;
+   
+   initial $dumpfile("rx_dcoffset_tb.vcd");
+   initial $dumpvars(0,rx_dcoffset_tb);
+
+   reg [13:0] adc_in = 7;
+   wire [13:0] adc_out;
+
+   always @(posedge clk)
+     $display("%d\t%d",adc_in,adc_out);
+   
+   rx_dcoffset #(.WIDTH(14),.ADDR(0))
+     rx_dcoffset(.clk(clk),.rst(rst),.set_stb(0),.set_addr(0),.set_data(0),
+		 .adc_in(adc_in),.adc_out(adc_out));
+   
+endmodule // longfifo_tb
-- 
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