From 05d77f772317de5d925301aa11bb9a880656dd05 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Thu, 15 Apr 2010 11:24:24 -0700
Subject: moved usrp1 and usrp2 fpga dirs into fpga subdirectory

---
 fpga/usrp2/sdr_lib/hb/coeff_ram.v | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 fpga/usrp2/sdr_lib/hb/coeff_ram.v

(limited to 'fpga/usrp2/sdr_lib/hb/coeff_ram.v')

diff --git a/fpga/usrp2/sdr_lib/hb/coeff_ram.v b/fpga/usrp2/sdr_lib/hb/coeff_ram.v
new file mode 100644
index 000000000..65460822f
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb/coeff_ram.v
@@ -0,0 +1,26 @@
+
+
+module coeff_ram (input clock, input [3:0] rd_addr, output reg [15:0] rd_data);
+
+   always @(posedge clock)
+     case (rd_addr)
+       4'd0 : rd_data <= #1 -16'd16;
+       4'd1 : rd_data <= #1 16'd74;
+       4'd2 : rd_data <= #1 -16'd254;
+       4'd3 : rd_data <= #1 16'd669;
+       4'd4 : rd_data <= #1 -16'd1468;
+       4'd5 : rd_data <= #1 16'd2950;
+       4'd6 : rd_data <= #1 -16'd6158;
+       4'd7 : rd_data <= #1 16'd20585;
+       4'd8 : rd_data <= #1 16'd20585;
+       4'd9 : rd_data <= #1 -16'd6158;
+       4'd10 : rd_data <= #1 16'd2950;
+       4'd11 : rd_data <= #1 -16'd1468;
+       4'd12 : rd_data <= #1 16'd669;
+       4'd13 : rd_data <= #1 -16'd254;
+       4'd14 : rd_data <= #1 16'd74;
+       4'd15 : rd_data <= #1 -16'd16;
+       default : rd_data <= #1 16'd0;
+     endcase // case(rd_addr)
+   
+endmodule // ram
-- 
cgit v1.2.3