From 05d77f772317de5d925301aa11bb9a880656dd05 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Thu, 15 Apr 2010 11:24:24 -0700
Subject: moved usrp1 and usrp2 fpga dirs into fpga subdirectory

---
 fpga/usrp2/opencores/aemb/sim/iversim | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100755 fpga/usrp2/opencores/aemb/sim/iversim

(limited to 'fpga/usrp2/opencores/aemb/sim/iversim')

diff --git a/fpga/usrp2/opencores/aemb/sim/iversim b/fpga/usrp2/opencores/aemb/sim/iversim
new file mode 100755
index 000000000..9d2384b5a
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sim/iversim
@@ -0,0 +1,21 @@
+#!/bin/sh
+# $Id: iversim,v 1.5 2007/12/11 00:44:30 sybreon Exp $
+# $Log: iversim,v $
+# Revision 1.5  2007/12/11 00:44:30  sybreon
+# Modified for AEMB2
+#
+# Revision 1.4  2007/11/30 17:08:30  sybreon
+# Moved simulation kernel into code.
+#
+# Revision 1.3  2007/11/09 20:50:51  sybreon
+# Added log output to iverilog.log
+#
+# Revision 1.2  2007/11/05 10:59:31  sybreon
+# Added random seed for simulation.
+#
+# Revision 1.1  2007/03/09 17:41:55  sybreon
+# initial import
+#
+RANDOM=$(date +%s)
+echo "parameter randseed = $RANDOM;" > random.v
+iverilog $@ -DAEMBX_SIMULATION_KERNEL ../rtl/verilog/*.v && vvp -l iverilog.log a.out && rm a.out
-- 
cgit v1.2.3