From 05d77f772317de5d925301aa11bb9a880656dd05 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Thu, 15 Apr 2010 11:24:24 -0700
Subject: moved usrp1 and usrp2 fpga dirs into fpga subdirectory

---
 fpga/usrp2/opencores/aemb/sim/cversim | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100755 fpga/usrp2/opencores/aemb/sim/cversim

(limited to 'fpga/usrp2/opencores/aemb/sim/cversim')

diff --git a/fpga/usrp2/opencores/aemb/sim/cversim b/fpga/usrp2/opencores/aemb/sim/cversim
new file mode 100755
index 000000000..0dbb7aea1
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sim/cversim
@@ -0,0 +1,22 @@
+#!/bin/sh
+# $Id: cversim,v 1.5 2007/12/11 00:44:30 sybreon Exp $
+# $Log: cversim,v $
+# Revision 1.5  2007/12/11 00:44:30  sybreon
+# Modified for AEMB2
+#
+# Revision 1.4  2007/11/30 17:08:30  sybreon
+# Moved simulation kernel into code.
+#
+# Revision 1.3  2007/11/05 10:59:31  sybreon
+# Added random seed for simulation.
+#
+# Revision 1.2  2007/04/12 20:21:33  sybreon
+# Moved testbench into /sim/verilog.
+# Simulation cleanups.
+#
+# Revision 1.1  2007/03/09 17:41:55  sybreon
+# initial import
+#
+RANDOM=$(date +%s)
+echo "parameter randseed = $RANDOM;" > random.v
+cver -q -w +define+AEMBX_SIMULATION_KERNEL $@ ../rtl/verilog/*.v
-- 
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