From 05d77f772317de5d925301aa11bb9a880656dd05 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 15 Apr 2010 11:24:24 -0700 Subject: moved usrp1 and usrp2 fpga dirs into fpga subdirectory --- fpga/usrp2/models/serdes_model.v | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 fpga/usrp2/models/serdes_model.v (limited to 'fpga/usrp2/models/serdes_model.v') diff --git a/fpga/usrp2/models/serdes_model.v b/fpga/usrp2/models/serdes_model.v new file mode 100644 index 000000000..f10e55554 --- /dev/null +++ b/fpga/usrp2/models/serdes_model.v @@ -0,0 +1,34 @@ + +module serdes_model + (input ser_tx_clk, + input ser_tkmsb, + input ser_tklsb, + input [15:0] ser_t, + + output ser_rx_clk, + output ser_rkmsb, + output ser_rklsb, + output [15:0] ser_r, + + input even, + input error); + + wire [15:0] ser_r_odd; + wire ser_rklsb_odd, ser_rkmsb_odd; + + reg [7:0] hold_dat; + reg hold_k; + + always @(posedge ser_tx_clk) hold_k <= ser_tklsb; + always @(posedge ser_tx_clk) hold_dat <= ser_t[15:8]; + assign ser_rklsb_odd = hold_k; + assign ser_rkmsb_odd = ser_tklsb; + assign ser_r_odd = {ser_t[7:0], hold_dat}; + + // Set outputs + assign ser_rx_clk = ser_tx_clk; + assign ser_rkmsb = even ? ser_tkmsb : ser_rkmsb_odd; + assign ser_rklsb = even ? ser_tklsb : ser_rklsb_odd; + assign ser_r = error ^ (even ? ser_t : ser_r_odd); + +endmodule // serdes_model -- cgit v1.2.3