From 05d77f772317de5d925301aa11bb9a880656dd05 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 15 Apr 2010 11:24:24 -0700 Subject: moved usrp1 and usrp2 fpga dirs into fpga subdirectory --- fpga/usrp2/models/MULT18X18S.v | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 fpga/usrp2/models/MULT18X18S.v (limited to 'fpga/usrp2/models/MULT18X18S.v') diff --git a/fpga/usrp2/models/MULT18X18S.v b/fpga/usrp2/models/MULT18X18S.v new file mode 100644 index 000000000..5d39eeaa6 --- /dev/null +++ b/fpga/usrp2/models/MULT18X18S.v @@ -0,0 +1,20 @@ + +// Model of the Xilinx mult18x18s for signed 18x18 bit multiplies, +// As in the Spartan 3 series + +module MULT18X18S + (output reg signed [35:0] P, + input signed [17:0] A, + input signed [17:0] B, + input C, // Clock + input CE, // Clock Enable + input R // Synchronous Reset + ); + + always @(posedge C) + if(R) + P <= 36'sd0; + else if(CE) + P <= A * B; + +endmodule // MULT18X18S -- cgit v1.2.3