From 05d77f772317de5d925301aa11bb9a880656dd05 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Thu, 15 Apr 2010 11:24:24 -0700
Subject: moved usrp1 and usrp2 fpga dirs into fpga subdirectory

---
 fpga/usrp2/models/CY7C1356C/readme.txt | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 fpga/usrp2/models/CY7C1356C/readme.txt

(limited to 'fpga/usrp2/models/CY7C1356C/readme.txt')

diff --git a/fpga/usrp2/models/CY7C1356C/readme.txt b/fpga/usrp2/models/CY7C1356C/readme.txt
new file mode 100644
index 000000000..3578c80dc
--- /dev/null
+++ b/fpga/usrp2/models/CY7C1356C/readme.txt
@@ -0,0 +1,33 @@
+***************************
+Cypress Semiconductor
+MPD Applications
+Verilog  model for NoBL SRAM CY7C1356
+Created: August 04, 2004
+Rev: 1.0
+***************************
+
+This is the verilog model for the CY7C1356 along with the testbench and test vectors.
+
+Contact support@cypress.com if you have any questions.
+
+This directory has 4 files. including this readme.
+
+1)cy7c1356c.v -> Verilog model for CY7C1356c
+
+2)cy1356.inp -> Test Vector File used for testing the verilog model  
+
+3)testbench.v -> Test bench used for testing the verilog model
+
+
+COMPILING METHOD :
+------------------
+
+        	verilog  +define+<speed_bin>	<Main File>	<Test bench File>
+
+	Ex:
+		verilog  +define+sb133  	CY7C1356c.v 	testbench.v
+
+VERIFIED WITH:
+--------------
+
+VERILOG-XL 2.2
\ No newline at end of file
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