From bb0572a960edf54486a4be746c681adaac0fa398 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 23 Nov 2010 13:36:42 -0800 Subject: fpga: performed a forceful checkout of fpga to overwrite with current fpga code --- fpga/usrp2/extramfifo/ext_fifo.v | 37 ++++++++++++++++---------------- fpga/usrp2/extramfifo/ext_fifo_tb.sh | 0 fpga/usrp2/extramfifo/nobl_fifo.v | 41 ++++++++++++++++++------------------ fpga/usrp2/extramfifo/nobl_if.v | 9 +++++--- 4 files changed, 45 insertions(+), 42 deletions(-) mode change 100644 => 100755 fpga/usrp2/extramfifo/ext_fifo_tb.sh (limited to 'fpga/usrp2/extramfifo') diff --git a/fpga/usrp2/extramfifo/ext_fifo.v b/fpga/usrp2/extramfifo/ext_fifo.v index 6888617a7..80f82fc63 100644 --- a/fpga/usrp2/extramfifo/ext_fifo.v +++ b/fpga/usrp2/extramfifo/ext_fifo.v @@ -45,9 +45,7 @@ module ext_fifo wire [EXT_WIDTH-1:0] write_data; wire [EXT_WIDTH-1:0] read_data; wire full1, empty1; - wire almost_full2, full2, empty2; - wire [INT_WIDTH-1:0] data_to_fifo; - wire [INT_WIDTH-1:0] data_from_fifo; + wire almost_full2, almost_full2_spread, full2, empty2; wire [FIFO_DEPTH-1:0] capacity; wire space_avail; wire data_avail; @@ -134,17 +132,17 @@ module ext_fifo .empty(empty1)); // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP. - fifo_xlnx_32x36_2clk fifo_xlnx_32x36_2clk_i2 ( - .rst(rst), - .wr_clk(ext_clk), - .rd_clk(int_clk), - .din(read_data), // Bus [35 : 0] - .wr_en(write_output_fifo), - .rd_en(dst_rdy_i), - .dout(dataout), // Bus [35 : 0] - .full(full2), - .empty(empty2), - .prog_full(almost_full2)); + fifo_xlnx_512x36_2clk_prog_full fifo_xlnx_32x36_2clk_prog_full_i1 ( + .rst(rst), + .wr_clk(ext_clk), + .rd_clk(int_clk), + .din(read_data), // Bus [35 : 0] + .wr_en(write_output_fifo), + .rd_en(dst_rdy_i), + .dout(dataout), // Bus [35 : 0] + .full(full2), + .empty(empty2), + .prog_full(almost_full2)); end endgenerate @@ -158,13 +156,14 @@ module ext_fifo .full_out(almost_full2_spread) ); - - always @ (posedge int_clk) - debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i }; +// always @ (posedge int_clk) +// debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i }; always @ (posedge ext_clk) - debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 }; - + // debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 }; + debug[31:0] <= {7'h0,src_rdy_i,read_input_fifo,write_output_fifo,dst_rdy_i,full2,almost_full2,empty2,full1,empty1,write_data[7:0],read_data[7:0]}; + + always@ (posedge ext_clk) // debug2[31:0] <= {write_data[15:0],read_data[15:0]}; debug2[31:0] <= 0; diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.sh b/fpga/usrp2/extramfifo/ext_fifo_tb.sh old mode 100644 new mode 100755 diff --git a/fpga/usrp2/extramfifo/nobl_fifo.v b/fpga/usrp2/extramfifo/nobl_fifo.v index 4c009d980..0b63768fc 100644 --- a/fpga/usrp2/extramfifo/nobl_fifo.v +++ b/fpga/usrp2/extramfifo/nobl_fifo.v @@ -70,26 +70,27 @@ module nobl_fifo // Simple NoBL SRAM interface, 4 cycle read latency. // Read/Write arbitration via temprary application of empty/full flags. // - nobl_if nobl_if_i1 - ( - .clk(clk), - .rst(rst), - .RAM_D_pi(RAM_D_pi), - .RAM_D_po(RAM_D_po), - .RAM_D_poe(RAM_D_poe), - .RAM_A(RAM_A), - .RAM_WEn(RAM_WEn), - .RAM_CENn(RAM_CENn), - .RAM_LDn(RAM_LDn), - .RAM_OEn(RAM_OEn), - .RAM_CE1n(RAM_CE1n), - .address(address), - .data_out(write_data), - .data_in(read_data), - .data_in_valid(data_avail), - .write(write), - .enable(enable) - ); + nobl_if #(.WIDTH(WIDTH),.DEPTH(RAM_DEPTH)) + nobl_if_i1 + ( + .clk(clk), + .rst(rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .address(address), + .data_out(write_data), + .data_in(read_data), + .data_in_valid(data_avail), + .write(write), + .enable(enable) + ); diff --git a/fpga/usrp2/extramfifo/nobl_if.v b/fpga/usrp2/extramfifo/nobl_if.v index adf9f165b..b5ebe9c6b 100644 --- a/fpga/usrp2/extramfifo/nobl_if.v +++ b/fpga/usrp2/extramfifo/nobl_if.v @@ -56,18 +56,21 @@ module nobl_if address_pipe1 <= 0; write_pipe1 <= 0; data_out_pipe1 <= 0; + RAM_WEn <= 1; + RAM_CE1n <= 1; + end else begin enable_pipe1 <= enable; - RAM_CE1n <= ~enable; // Creates IOB flob - + RAM_CE1n <= ~enable; // Creates IOB flop + RAM_WEn <= ~write; // Creates IOB flop if (enable) begin address_pipe1 <= address_gray; write_pipe1 <= write; - RAM_WEn <= ~write; // Creates IOB flob +// RAM_WEn <= ~write; // Creates IOB flop if (write) -- cgit v1.2.3