From bafa9d95453387814ef25e6b6256ba8db2df612f Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Thu, 23 Jan 2020 16:10:22 -0800 Subject: Merge FPGA repository back into UHD repository MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams Co-authored-by: Andrej Rode Co-authored-by: Ashish Chaudhari Co-authored-by: Ben Hilburn Co-authored-by: Ciro Nishiguchi Co-authored-by: Daniel Jepson Co-authored-by: Derek Kozel Co-authored-by: EJ Kreinar Co-authored-by: Humberto Jimenez Co-authored-by: Ian Buckley Co-authored-by: Jörg Hofrichter Co-authored-by: Jon Kiser Co-authored-by: Josh Blum Co-authored-by: Jonathon Pendlum Co-authored-by: Martin Braun Co-authored-by: Matt Ettus Co-authored-by: Michael West Co-authored-by: Moritz Fischer Co-authored-by: Nick Foster Co-authored-by: Nicolas Cuervo Co-authored-by: Paul Butler Co-authored-by: Paul David Co-authored-by: Ryan Marlow Co-authored-by: Sugandha Gupta Co-authored-by: Sylvain Munaut Co-authored-by: Trung Tran Co-authored-by: Vidush Vishwanath Co-authored-by: Wade Fife --- fpga/usrp2/coregen/.gitignore | 3 + fpga/usrp2/coregen/Makefile.srcs | 27 + fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs | 18 + fpga/usrp2/coregen/coregen.cgp | 22 + fpga/usrp2/coregen/coregen_s6.cgc | 2352 ++++++++++++ fpga/usrp2/coregen/coregen_s6.cgp | 22 + .../usrp2/coregen/fifo_generator_release_notes.txt | 160 + fpga/usrp2/coregen/fifo_generator_ug175.pdf | Bin 0 -> 2895895 bytes fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.asy | 49 + fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.gise | 31 + fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.ngc | 3 + fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.v | 173 + fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.veo | 53 + fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xco | 84 + fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xise | 392 ++ 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fpga/usrp2/coregen/pll_100_40_75/simulation/timing/vcs_session.tcl create mode 100755 fpga/usrp2/coregen/pll_100_40_75/simulation/timing/wave.do create mode 100644 fpga/usrp2/coregen/pll_100_40_75_exdes.ncf create mode 100644 fpga/usrp2/coregen/pll_100_40_75_flist.txt create mode 100755 fpga/usrp2/coregen/pll_100_40_75_xmdf.tcl (limited to 'fpga/usrp2/coregen') diff --git a/fpga/usrp2/coregen/.gitignore b/fpga/usrp2/coregen/.gitignore new file mode 100644 index 000000000..956cab52b --- /dev/null +++ b/fpga/usrp2/coregen/.gitignore @@ -0,0 +1,3 @@ +/xlnx_auto* +/*log +/tmp diff --git a/fpga/usrp2/coregen/Makefile.srcs b/fpga/usrp2/coregen/Makefile.srcs new file mode 100644 index 000000000..a3a5d826d --- /dev/null +++ b/fpga/usrp2/coregen/Makefile.srcs @@ -0,0 +1,27 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# Coregen Sources +################################################## +COREGEN_SRCS = $(abspath $(addprefix $(BASE_DIR)/../coregen/, \ +fifo_xlnx_2Kx36_2clk.v \ +fifo_xlnx_2Kx36_2clk.xco \ +fifo_xlnx_512x36_2clk.v \ +fifo_xlnx_512x36_2clk.xco \ +fifo_xlnx_64x36_2clk.v \ +fifo_xlnx_64x36_2clk.xco \ +fifo_xlnx_16x19_2clk.v \ +fifo_xlnx_16x19_2clk.xco \ +fifo_xlnx_16x40_2clk.v \ +fifo_xlnx_16x40_2clk.xco \ +fifo_xlnx_32x36_2clk.v \ +fifo_xlnx_32x36_2clk.xco \ +fifo_xlnx_512x36_2clk_36to18.v \ +fifo_xlnx_512x36_2clk_36to18.xco \ +fifo_xlnx_512x36_2clk_18to36.v \ +fifo_xlnx_512x36_2clk_18to36.xco \ +fifo_xlnx_512x36_2clk_prog_full.v \ +fifo_xlnx_512x36_2clk_prog_full.xco \ +)) diff --git a/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs b/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs new file mode 100644 index 000000000..e7bbdb9d5 --- /dev/null +++ b/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,18 @@ + + + + + + + + + + +Parsing Verilog file "/home/jblum/src/ettus/fpga_b200/usrp2/coregen/pll_100_40_75.v" into library work + + +Parsing Verilog file "/home/jblum/src/ettus/fpga_b200/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.v" into library work + + + + diff --git a/fpga/usrp2/coregen/coregen.cgp b/fpga/usrp2/coregen/coregen.cgp new file mode 100644 index 000000000..dd85a7f50 --- /dev/null +++ b/fpga/usrp2/coregen/coregen.cgp @@ -0,0 +1,22 @@ +# Date: Fri Oct 15 07:50:19 2010 + +SET addpads = false +SET asysymbol = false +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Structural +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +SET workingdirectory = /tmp/ + +# CRC: 983b9b45 diff --git a/fpga/usrp2/coregen/coregen_s6.cgc b/fpga/usrp2/coregen/coregen_s6.cgc new file mode 100644 index 000000000..90b359eab --- /dev/null +++ b/fpga/usrp2/coregen/coregen_s6.cgc @@ -0,0 +1,2352 @@ + + + xilinx.com + project + coregen_s6 + 1.0 + + + fifo_s6_1Kx36_2clk + + + fifo_s6_1Kx36_2clk + false + true + 1022 + 5 + 36 + 1024 + false + No_Programmable_Empty_Threshold + false + false + Independent_Clocks_Block_RAM + false + true + 1 + Active_High + 11 + false + 10 + 1024 + 0 + true + true + Active_High + Active_High + false + true + false + No_Programmable_Full_Threshold + false + 11 + Asynchronous_Reset + First_Word_Fall_Through + 1023 + true + false + false + 1 + Active_High + false + 4 + 36 + 1 + false + + + + + coregen_s6 + ./ + ./tmp/ + ./tmp/_cg/ + + + xc6slx75 + spartan6 + csg484 + -3 + + + BusFormatAngleBracketNotRipped + Verilog + true + Other + false + false + false + Ngc + false + + + Behavioral + Verilog + false + + + 2012-04-24+06:33 + + + + + + fifo_s6_2Kx36_2clk + + + fifo_s6_2Kx36_2clk + false + true + 2046 + 5 + 36 + 2048 + false + No_Programmable_Empty_Threshold + false + false + Independent_Clocks_Block_RAM + false + true + 1 + Active_High + 12 + false + 11 + 2048 + 0 + true + true + Active_High + Active_High + false + true + false + No_Programmable_Full_Threshold + false + 12 + Asynchronous_Reset + First_Word_Fall_Through + 2047 + true + false + false + 1 + Active_High + false + 4 + 36 + 1 + false + + + + + coregen_s6 + ./ + ./tmp/ + ./tmp/_cg/ + + + xc6slx75 + spartan6 + csg484 + -3 + + + BusFormatAngleBracketNotRipped + Verilog + true + Other + false + false + false + Ngc + false + + + Behavioral + Verilog + false + + + 2012-04-24+06:33 + + + + + + fifo_s6_512x36_2clk + + + fifo_s6_512x36_2clk + false + true + 510 + 5 + 36 + 512 + false + No_Programmable_Empty_Threshold + false + false + Independent_Clocks_Block_RAM + false + true + 1 + Active_High + 10 + false + 9 + 512 + 0 + true + true + Active_High + Active_High + false + true + false + No_Programmable_Full_Threshold + false + 10 + Asynchronous_Reset + First_Word_Fall_Through + 511 + true + false + false + 1 + Active_High + false + 4 + 36 + 1 + false + + + + + coregen_s6 + ./ + ./tmp/ + ./tmp/_cg/ + + + xc6slx75 + spartan6 + csg484 + -3 + + + BusFormatAngleBracketNotRipped + Verilog + true + Other + false + false + false + Ngc + false + + + Behavioral + Verilog + false + + + 2012-04-24+06:33 + + + + + + fifo_xlnx_16x19_2clk + + + fifo_xlnx_16x19_2clk + false + true + 14 + 5 + 19 + 16 + false + No_Programmable_Empty_Threshold + false + false + Independent_Clocks_Distributed_RAM + false + true + 1 + Active_High + 5 + 5 + 16 + 0 + true + Active_High + Active_High + false + true + false + No_Programmable_Full_Threshold + 5 + Asynchronous_Reset + First_Word_Fall_Through + 15 + true + false + false + 1 + Active_High + false + 4 + 19 + 1 + false + + + + + coregen_s6 + ./ + ./tmp/ + ./tmp/_cg/ + + + xc3s2000 + spartan3 + fg456 + -5 + + + BusFormatAngleBracketNotRipped + Verilog + false + Other + false + false + false + Ngc + false + + + Behavioral + Verilog + false + + + 2012-04-24+06:33 + + + + + + fifo_xlnx_16x40_2clk + + + fifo_xlnx_16x40_2clk + false + false + 14 + 5 + 40 + 16 + false + No_Programmable_Empty_Threshold + false + false + Independent_Clocks_Distributed_RAM + false + false + 1 + Active_High + 4 + 4 + 16 + 0 + true + Active_High + Active_High + false + false + false + No_Programmable_Full_Threshold + 4 + Asynchronous_Reset + First_Word_Fall_Through + 15 + true + false + false + 1 + Active_High + false + 4 + 40 + 1 + false + + + + + coregen_s6 + ./ + ./tmp/ + ./tmp/_cg/ + + + xc3s2000 + spartan3 + fg456 + -5 + + + BusFormatAngleBracketNotRipped + Verilog + false + Other + false + false + false + Ngc + false + + + Behavioral + Verilog + false + + + 2012-04-24+06:33 + + + + + + fifo_xlnx_2Kx36_2clk + + + fifo_xlnx_2Kx36_2clk + false + true + 2046 + 5 + 36 + 2048 + false + No_Programmable_Empty_Threshold + false + false + Independent_Clocks_Block_RAM + false + true + 1 + Active_High + 12 + 12 + 2048 + 0 + true + Active_High + Active_High + false + true + false + No_Programmable_Full_Threshold + 12 + Asynchronous_Reset + First_Word_Fall_Through + 2047 + true + false + false + 1 + Active_High + false + 4 + 36 + 1 + false + + + + + coregen_s6 + ./ + ./tmp/ + ./tmp/_cg/ + + + xc3s2000 + spartan3 + fg456 + -5 + + + BusFormatAngleBracketNotRipped + VHDL + true + Foundation_ISE + false + false + false + Ngc + false + + + Behavioral + VHDL_and_Verilog + false + + + 2012-04-24+06:33 + + + + + + fifo_xlnx_32x36_2clk + + + fifo_xlnx_32x36_2clk + false + false + 23 + 5 + 36 + 32 + false + No_Programmable_Empty_Threshold + false + false + Independent_Clocks_Distributed_RAM + false + false + 1 + Active_High + 5 + false + 5 + 32 + 0 + true + true + Active_High + Active_High + false + false + false + Single_Programmable_Full_Threshold_Constant + false + 5 + Asynchronous_Reset + First_Word_Fall_Through + 24 + true + true + false + 1 + Active_High + false + 4 + 36 + 1 + false + + + + + coregen_s6 + ./ + ./tmp/ + ./tmp/_cg/ + + + xc3s2000 + spartan3 + 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2012 + 0x196566F3 + generationID_4013899584 + + + ./pll_100_40_75/simulation/functional/simulate_mti.sh + ignore + unknown + Mon Jun 25 01:22:04 GMT 2012 + 0xA92E962D + generationID_4013899584 + + + ./pll_100_40_75/simulation/functional/simulate_ncsim.sh + ignore + unknown + Mon Jun 25 01:22:04 GMT 2012 + 0x414DA0D8 + generationID_4013899584 + + + ./pll_100_40_75/simulation/functional/simulate_vcs.sh + ignore + unknown + Mon Jun 25 01:22:04 GMT 2012 + 0x040C0268 + generationID_4013899584 + + + ./pll_100_40_75/simulation/functional/ucli_commands.key + ignore + unknown + Mon Jun 25 01:22:04 GMT 2012 + 0x957E258B + generationID_4013899584 + + + ./pll_100_40_75/simulation/functional/vcs_session.tcl + ignore + tcl + Mon Jun 25 01:22:04 GMT 2012 + 0x859D76CE + generationID_4013899584 + + + ./pll_100_40_75/simulation/functional/wave.do + ignore + unknown + Mon Jun 25 01:22:04 GMT 2012 + 0xF6D99A50 + generationID_4013899584 + + + ./pll_100_40_75/simulation/functional/wave.sv + ignore + unknown + Mon Jun 25 01:22:04 GMT 2012 + 0x5BAF49BA + generationID_4013899584 + + + ./pll_100_40_75/simulation/pll_100_40_75_tb.v + ignore + verilog + Mon Jun 25 01:22:04 GMT 2012 + 0x338F9EC4 + generationID_4013899584 + + + ./pll_100_40_75/simulation/timing/pll_100_40_75_tb.v + ignore + verilog + Mon Jun 25 01:22:04 GMT 2012 + 0xF8A7FBD8 + generationID_4013899584 + + + ./pll_100_40_75/simulation/timing/sdf_cmd_file + ignore + unknown + Mon Jun 25 01:22:04 GMT 2012 + 0xE37E41C3 + generationID_4013899584 + + + ./pll_100_40_75/simulation/timing/simcmds.tcl + ignore + tcl + Mon Jun 25 01:22:04 GMT 2012 + 0x59F13085 + generationID_4013899584 + + + ./pll_100_40_75/simulation/timing/simulate_isim.sh + ignore + unknown + Mon Jun 25 01:22:04 GMT 2012 + 0x513F3CD7 + generationID_4013899584 + + + ./pll_100_40_75/simulation/timing/simulate_mti.bat + ignore + unknown + Mon Jun 25 01:22:04 GMT 2012 + 0x6032836B + generationID_4013899584 + + + ./pll_100_40_75/simulation/timing/simulate_mti.do + ignore + unknown + Mon Jun 25 01:22:04 GMT 2012 + 0x8556A6D6 + generationID_4013899584 + + + ./pll_100_40_75/simulation/timing/simulate_mti.sh + ignore + unknown + Mon Jun 25 01:22:04 GMT 2012 + 0xF19800C9 + generationID_4013899584 + + + ./pll_100_40_75/simulation/timing/simulate_ncsim.sh + ignore + unknown + Mon Jun 25 01:22:04 GMT 2012 + 0xEFFEEFB9 + generationID_4013899584 + + + ./pll_100_40_75/simulation/timing/simulate_vcs.sh + ignore + unknown + Mon Jun 25 01:22:04 GMT 2012 + 0xE87CCB6C + generationID_4013899584 + + + ./pll_100_40_75/simulation/timing/ucli_commands.key + ignore + unknown + Mon Jun 25 01:22:04 GMT 2012 + 0x9DC0E037 + generationID_4013899584 + + + ./pll_100_40_75/simulation/timing/vcs_session.tcl + ignore + tcl + Mon Jun 25 01:22:04 GMT 2012 + 0x28340249 + generationID_4013899584 + + + ./pll_100_40_75/simulation/timing/wave.do + ignore + unknown + Mon Jun 25 01:22:04 GMT 2012 + 0x251C4591 + generationID_4013899584 + + + ./pll_100_40_75.ucf + ignore + ucf + Mon Jun 25 01:22:04 GMT 2012 + 0x4904DEF4 + generationID_4013899584 + + + ./pll_100_40_75.v + verilog + Mon Jun 25 01:22:03 GMT 2012 + 0xF7DE77A9 + generationID_4013899584 + + + ./pll_100_40_75.veo + veo + Mon Jun 25 01:22:04 GMT 2012 + 0xC3431095 + generationID_4013899584 + + + ./pll_100_40_75.xdc + ignore + xdc + Mon Jun 25 01:22:04 GMT 2012 + 0x590C1CA7 + generationID_4013899584 + + + ./pll_100_40_75_xmdf.tcl + tcl + Mon Jun 25 01:22:04 GMT 2012 + 0x970F3026 + generationID_4013899584 + + + + all_documents_generator + + ./pll_100_40_75/doc/clk_wiz_gsg521.pdf + ignore + pdf + Mon Jun 25 01:22:08 GMT 2012 + 0x7660EFEE + generationID_4013899584 + + + ./pll_100_40_75/doc/clk_wiz_v3_5_readme.txt + ignore + txt + Mon Jun 25 01:22:08 GMT 2012 + 0x1BF90E4F + generationID_4013899584 + + + ./pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html + ignore + unknown + Mon Jun 25 01:22:08 GMT 2012 + 0xD0135075 + generationID_4013899584 + + + + readme_documents_generator + + ./pll_100_40_75/doc/clk_wiz_v3_5_readme.txt + ignore + txt + Mon Jun 25 01:22:09 GMT 2012 + 0x1BF90E4F + generationID_4013899584 + + + + asy_generator + + ./pll_100_40_75.asy + asy + Mon Jun 25 01:22:17 GMT 2012 + 0x61F47740 + generationID_4013899584 + + + + ise_generator + + ./_xmsgs/pn_parser.xmsgs + ignore + unknown + Mon Jun 25 01:22:24 GMT 2012 + 0xEDD97934 + generationID_4013899584 + + + ./pll_100_40_75.gise + ignore + gise + Mon Jun 25 01:22:25 GMT 2012 + 0x3AB6E652 + generationID_4013899584 + + + ./pll_100_40_75.xise + ignore + xise + Mon Jun 25 01:22:25 GMT 2012 + 0xAD3860B6 + generationID_4013899584 + + + + deliver_readme_generator + + + flist_generator + + ./pll_100_40_75_flist.txt + ignore + txtFlist + txt + Mon Jun 25 01:22:25 GMT 2012 + 0x4D0B8946 + generationID_4013899584 + + + + view_readme_generator + + + + + + + + + coregen_s6 + ./ + ./tmp/ + ./tmp/_cg/ + + + xc6slx75 + spartan6 + csg484 + -3 + + + BusFormatAngleBracketNotRipped + Verilog + true + Other + false + false + false + Ngc + false + + + Behavioral + Verilog + false + + + + + diff --git a/fpga/usrp2/coregen/coregen_s6.cgp b/fpga/usrp2/coregen/coregen_s6.cgp new file mode 100644 index 000000000..1abd1b021 --- /dev/null +++ b/fpga/usrp2/coregen/coregen_s6.cgp @@ -0,0 +1,22 @@ +# Date: Fri May 4 20:42:23 2012 + +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +SET workingdirectory = ./tmp/ + +# CRC: f7d4ca66 diff --git a/fpga/usrp2/coregen/fifo_generator_release_notes.txt b/fpga/usrp2/coregen/fifo_generator_release_notes.txt new file mode 100644 index 000000000..554ec87f4 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_generator_release_notes.txt @@ -0,0 +1,160 @@ +COPYRIGHT (c) 2006, 2007 XILINX, INC. +ALL RIGHTS RESERVED + +Core name : FIFO Generator +Version : v4.1 +Release Date : August 8, 2007 +File : fifo_generator_release_notes.txt + +Revision History +Date By Version Change Description +======================================================================== +09/2006 Xilinx, Inc. 3.2 Initial creation. +02/2007 Xilinx, Inc. 3.3 Revised for v3.3. +02/2007 Xilinx, Inc. 3.3 Revised for v3.3 rev 1. +08/2007 Xilinx, Inc. 3.4 Revised for v4.1. +======================================================================== + +INTRODUCTION +RELEASE NOTES + 1. General Core Design + 1.1 Enhancements + 1.2 Resolved Issues + 1.3 Outstanding Issues + 2. General Simulation + 2.1 Enhancements + 2.2 Resolved Issues + 2.3 Outstanding Issues + 3. Documentation + 3.1 Enhancements + 3.2 Resolved Issues + 3.3 Outstanding Issues +OTHER GENERAL INFORMATION +TECHNICAL SUPPORT + +======================================================================== + +INTRODUCTION +============ +Thank you using the FIFO Generator core from Xilinx! +In order to obtain the latest core updates and documentation, +please visit the Intellectual Property page located at: +http://www.xilinx.com/ipcenter/index.htm +This document contains the release notes for FIFO Generator v4.1 +which includes enhancements, resolved issues and outstanding known +issues. For release notes and known issues for CORE Generator 9.2i IP +Update 1 and FIFO Generator v4.1 please see Answer Record 25222. + +RELEASE NOTES +============= +This section lists any enhancements, resolved issues and outstanding +known issues. + + +1. General Core Design + 1.1 Enhancements + 1.1.1 Error Correction Checking (ECC) feature support for + Virtex-5 block RAM FIFO configurations + + 1.1.2 Full range data count widths now supported for non-symmetric + aspect ratio configurations + + 1.1.3 Option to define asynchronous reset value for full condition + flags (FULL, ALMOST_FULL, PROG_FULL). Applies to block RAM, + distributed RAM and shift RAM-based FIFO configurations only + + 1.1.4 Support added for use embedded output registers in block RAM + FIFO configurations (Virtex-4 and Virtex-5 only) + + 1.2 Resolved Issues + 1.2.1 Coregen GUI - For built-in FIFOs, GUI reports incorrect + number of built-in FIFO primitives used. + Change request: 4433738 + + 1.2.2 Programmable full flag is always asserted even when FIFO is + empty due to incorrect threshold setting. + Change request: 435835 + + 1.2.3 "ERROR:LIT:250 - Pins WEA0, WEA1, WEA2, WEA3 of RAMB16 symbol + .. , these pins should be connected to the same signal" occur + during MAP when targeting Virtex-4 and Virtex-5. + Change request: 338260 + + 1.2.4 Write Data Count and Read Data Count overestimate the number + of words written or read when core is configured with this + combination of options: First-Word-Fall-Through(FWFT), + accurate data count using extra logic, non-symmetric port + aspect ratio. + Change request: 436886 + + 1.2.5 SBITERR and DBITERR outputs are not driven in behavior + models. + Change request: 433637 + + 1.2.6 Maximum programmable empty threshold negate value is + incorrect. + Change request: 433921 + + 1.2.7 Programmable full flag behavior is incorrect when the + core is configured with this combination of options: + FWFT, non-symmetric port aspect ratio, single or + multiple programmable full threshold input port. + Change request: 435874 + + 1.2.8 Programmable empty flag stuck high when the core is + configured with this combination of options: block or + distributed RAM FIFO, single or multiple programmable + empty threshold input port. + Change request: 443569 + + 1.3 Outstanding Issues + 1.3.1 "WARNING:Ngdbuild:452 - logical net + 'u1/BU2/prog_*_thresh_assert<*>' has no driver" occur during + NgdBuild although programmable empty or full is not selected. + Warnings can be safely ignored. + Change request: 431975 + +2. General Simulation + 2.1 Enhancements + None at this time. + + 2.2 Resolved Issues + None at this time. + + 2.3 Outstanding Issues + 2.3.1 Ncelab warnings during Verilog structural and timing simulations + in ncsim for Virtex5 Block RAM FIFOs. + The simulations will be successful, but there will be warnings + similar to the following in the log file: "memory index out of + declared bounds" in simprims_ver_virtex5_source.v or + unisims_ver_virtex5_source.v. Cadence does not want to fix this + issue. These warning messages can safely be ignored. + Change request: 423374, 423375 + +3. Documentation + 3.1 Enhancements + 3.1.1 Added clarification on FIFO flag latency. + + 3.1.1 Added clarification on actual FIFO depth. + + 3.2 Resolved Issues + None at this time. + + 3.3 Outstanding Issues + None at this time. + + +TECHNICAL SUPPORT +================= +The fastest method for obtaining specific technical support for the +FIFO Generator core is through the http://support.xilinx.com/ +website. Questions are routed to a team of engineers with specific +expertise in using the FIFO Generator core. Xilinx will provide +technical support for use of this product as described in the FIFO +Generator Datasheet. Xilinx cannot guarantee timing, functionality, +or support of this product for designs that do not follow these +guidelines. + + + + diff --git a/fpga/usrp2/coregen/fifo_generator_ug175.pdf b/fpga/usrp2/coregen/fifo_generator_ug175.pdf new file mode 100644 index 000000000..5fba6029c Binary files /dev/null and b/fpga/usrp2/coregen/fifo_generator_ug175.pdf differ diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.asy b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.asy new file mode 100644 index 000000000..9664f3a57 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 fifo_s6_1Kx36_2clk +RECTANGLE Normal 32 32 544 768 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName din[35:0] +PINATTR Polarity IN +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Normal 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Normal 144 800 144 768 +PIN 144 800 BOTTOM 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Wide 576 80 544 80 +PIN 576 80 RIGHT 36 +PINATTR PinName dout[35:0] +PINATTR Polarity OUT +LINE Normal 576 208 544 208 +PIN 576 208 RIGHT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Wide 576 368 544 368 +PIN 576 368 RIGHT 36 +PINATTR PinName wr_data_count[10:0] +PINATTR Polarity OUT +LINE Normal 576 432 544 432 +PIN 576 432 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +LINE Wide 576 592 544 592 +PIN 576 592 RIGHT 36 +PINATTR PinName rd_data_count[10:0] +PINATTR Polarity OUT + diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.gise b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.gise new file mode 100644 index 000000000..5b40bcb30 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.gise @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.ngc b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.ngc new file mode 100644 index 000000000..f7e21b27e --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.v b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.v new file mode 100644 index 000000000..593d3f82c --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.v @@ -0,0 +1,173 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_s6_1Kx36_2clk.v when simulating +// the core, fifo_s6_1Kx36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_s6_1Kx36_2clk( + rst, + wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + empty, + rd_data_count, + wr_data_count); + + +input rst; +input wr_clk; +input rd_clk; +input [35 : 0] din; +input wr_en; +input rd_en; +output [35 : 0] dout; +output full; +output empty; +output [10 : 0] rd_data_count; +output [10 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V6_1 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(10), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_ENABLE_RST_SYNC(1), + .C_ERROR_INJECTION_TYPE(0), + .C_FAMILY("spartan6"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("1kx36"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(1023), + .C_PROG_FULL_THRESH_NEGATE_VAL(1022), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(11), + .C_RD_DEPTH(1024), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(10), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(1), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(11), + .C_WR_DEPTH(1024), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(10), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .RST(rst), + .WR_CLK(wr_clk), + .RD_CLK(rd_clk), + .DIN(din), + .WR_EN(wr_en), + .RD_EN(rd_en), + .DOUT(dout), + .FULL(full), + .EMPTY(empty), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .BACKUP(), + .BACKUP_MARKER(), + .CLK(), + .SRST(), + .WR_RST(), + .RD_RST(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .INT_CLK(), + .INJECTDBITERR(), + .INJECTSBITERR(), + .ALMOST_FULL(), + .WR_ACK(), + .OVERFLOW(), + .ALMOST_EMPTY(), + .VALID(), + .UNDERFLOW(), + .DATA_COUNT(), + .PROG_FULL(), + .PROG_EMPTY(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.veo b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.veo new file mode 100644 index 000000000..e348767a3 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.veo @@ -0,0 +1,53 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_s6_1Kx36_2clk YourInstanceName ( + .rst(rst), + .wr_clk(wr_clk), + .rd_clk(rd_clk), + .din(din), // Bus [35 : 0] + .wr_en(wr_en), + .rd_en(rd_en), + .dout(dout), // Bus [35 : 0] + .full(full), + .empty(empty), + .rd_data_count(rd_data_count), // Bus [10 : 0] + .wr_data_count(wr_data_count)); // Bus [10 : 0] + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_s6_1Kx36_2clk.v when simulating +// the core, fifo_s6_1Kx36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xco b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xco new file mode 100644 index 000000000..14ad27c2a --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xco @@ -0,0 +1,84 @@ +############################################################## +# +# Xilinx Core Generator version 12.1 +# Date: Fri May 4 20:49:07 2012 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 6.1 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_s6_1Kx36_2clk +CSET data_count=false +CSET data_count_width=10 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET enable_reset_synchronization=true +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=1023 +CSET full_threshold_negate_value=1022 +CSET inject_dbit_error=false +CSET inject_sbit_error=false +CSET input_data_width=36 +CSET input_depth=1024 +CSET output_data_width=36 +CSET output_depth=1024 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=11 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=11 +# END Parameters +GENERATE +# CRC: 5f5a2e48 diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xise b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xise new file mode 100644 index 000000000..b6109869c --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xise @@ -0,0 +1,392 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_flist.txt new file mode 100644 index 000000000..4f5b34b9b --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_flist.txt @@ -0,0 +1,13 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +fifo_generator_ug175.pdf +fifo_s6_1Kx36_2clk.asy +fifo_s6_1Kx36_2clk.gise +fifo_s6_1Kx36_2clk.ngc +fifo_s6_1Kx36_2clk.v +fifo_s6_1Kx36_2clk.veo +fifo_s6_1Kx36_2clk.xco +fifo_s6_1Kx36_2clk.xise +fifo_s6_1Kx36_2clk_flist.txt +fifo_s6_1Kx36_2clk_readme.txt +fifo_s6_1Kx36_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_readme.txt new file mode 100644 index 000000000..b101bd8cf --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_readme.txt @@ -0,0 +1,51 @@ +The following files were generated for 'fifo_s6_1Kx36_2clk' in directory +/home/matt/fpgapriv/usrp2/coregen/ + +fifo_generator_ug175.pdf: + Please see the core data sheet. + +fifo_s6_1Kx36_2clk.asy: + Graphical symbol information file. Used by the ISE tools and some + third party tools to create a symbol representing the core. + +fifo_s6_1Kx36_2clk.gise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_s6_1Kx36_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_s6_1Kx36_2clk.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_s6_1Kx36_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_s6_1Kx36_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_s6_1Kx36_2clk.xise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_s6_1Kx36_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_s6_1Kx36_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + +fifo_s6_1Kx36_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_xmdf.tcl new file mode 100644 index 000000000..f9a9ac233 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_xmdf.tcl @@ -0,0 +1,72 @@ +# The package naming convention is _xmdf +package provide fifo_s6_1Kx36_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_s6_1Kx36_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_s6_1Kx36_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_s6_1Kx36_2clk +} +# ::fifo_s6_1Kx36_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_s6_1Kx36_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_s6_1Kx36_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.asy b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.asy new file mode 100644 index 000000000..0b429a886 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 fifo_s6_2Kx36_2clk +RECTANGLE Normal 32 32 544 768 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName din[35:0] +PINATTR Polarity IN +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Normal 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Normal 144 800 144 768 +PIN 144 800 BOTTOM 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Wide 576 80 544 80 +PIN 576 80 RIGHT 36 +PINATTR PinName dout[35:0] +PINATTR Polarity OUT +LINE Normal 576 208 544 208 +PIN 576 208 RIGHT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Wide 576 368 544 368 +PIN 576 368 RIGHT 36 +PINATTR PinName wr_data_count[11:0] +PINATTR Polarity OUT +LINE Normal 576 432 544 432 +PIN 576 432 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +LINE Wide 576 592 544 592 +PIN 576 592 RIGHT 36 +PINATTR PinName rd_data_count[11:0] +PINATTR Polarity OUT + diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.gise b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.gise new file mode 100644 index 000000000..bfdef1560 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.gise @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.ngc b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.ngc new file mode 100644 index 000000000..994b767ea --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.v b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.v new file mode 100644 index 000000000..9f2cc7d4e --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.v @@ -0,0 +1,173 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_s6_2Kx36_2clk.v when simulating +// the core, fifo_s6_2Kx36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_s6_2Kx36_2clk( + rst, + wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + empty, + rd_data_count, + wr_data_count); + + +input rst; +input wr_clk; +input rd_clk; +input [35 : 0] din; +input wr_en; +input rd_en; +output [35 : 0] dout; +output full; +output empty; +output [11 : 0] rd_data_count; +output [11 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V6_1 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(11), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_ENABLE_RST_SYNC(1), + .C_ERROR_INJECTION_TYPE(0), + .C_FAMILY("spartan6"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("2kx18"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(2047), + .C_PROG_FULL_THRESH_NEGATE_VAL(2046), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(12), + .C_RD_DEPTH(2048), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(11), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(1), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(12), + .C_WR_DEPTH(2048), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(11), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .RST(rst), + .WR_CLK(wr_clk), + .RD_CLK(rd_clk), + .DIN(din), + .WR_EN(wr_en), + .RD_EN(rd_en), + .DOUT(dout), + .FULL(full), + .EMPTY(empty), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .BACKUP(), + .BACKUP_MARKER(), + .CLK(), + .SRST(), + .WR_RST(), + .RD_RST(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .INT_CLK(), + .INJECTDBITERR(), + .INJECTSBITERR(), + .ALMOST_FULL(), + .WR_ACK(), + .OVERFLOW(), + .ALMOST_EMPTY(), + .VALID(), + .UNDERFLOW(), + .DATA_COUNT(), + .PROG_FULL(), + .PROG_EMPTY(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.veo b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.veo new file mode 100644 index 000000000..7657f41bc --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.veo @@ -0,0 +1,53 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_s6_2Kx36_2clk YourInstanceName ( + .rst(rst), + .wr_clk(wr_clk), + .rd_clk(rd_clk), + .din(din), // Bus [35 : 0] + .wr_en(wr_en), + .rd_en(rd_en), + .dout(dout), // Bus [35 : 0] + .full(full), + .empty(empty), + .rd_data_count(rd_data_count), // Bus [11 : 0] + .wr_data_count(wr_data_count)); // Bus [11 : 0] + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_s6_2Kx36_2clk.v when simulating +// the core, fifo_s6_2Kx36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xco b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xco new file mode 100644 index 000000000..659795e5f --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xco @@ -0,0 +1,84 @@ +############################################################## +# +# Xilinx Core Generator version 12.1 +# Date: Fri May 4 20:55:54 2012 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 6.1 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_s6_2Kx36_2clk +CSET data_count=false +CSET data_count_width=11 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET enable_reset_synchronization=true +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=2047 +CSET full_threshold_negate_value=2046 +CSET inject_dbit_error=false +CSET inject_sbit_error=false +CSET input_data_width=36 +CSET input_depth=2048 +CSET output_data_width=36 +CSET output_depth=2048 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=12 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=12 +# END Parameters +GENERATE +# CRC: e7a1c106 diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xise b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xise new file mode 100644 index 000000000..c09cc4b35 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xise @@ -0,0 +1,392 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_flist.txt new file mode 100644 index 000000000..3466e5f91 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_flist.txt @@ -0,0 +1,13 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +fifo_generator_ug175.pdf +fifo_s6_2Kx36_2clk.asy +fifo_s6_2Kx36_2clk.gise +fifo_s6_2Kx36_2clk.ngc +fifo_s6_2Kx36_2clk.v +fifo_s6_2Kx36_2clk.veo +fifo_s6_2Kx36_2clk.xco +fifo_s6_2Kx36_2clk.xise +fifo_s6_2Kx36_2clk_flist.txt +fifo_s6_2Kx36_2clk_readme.txt +fifo_s6_2Kx36_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_readme.txt new file mode 100644 index 000000000..3a017fbb0 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_readme.txt @@ -0,0 +1,51 @@ +The following files were generated for 'fifo_s6_2Kx36_2clk' in directory +/home/matt/fpgapriv/usrp2/coregen/ + +fifo_generator_ug175.pdf: + Please see the core data sheet. + +fifo_s6_2Kx36_2clk.asy: + Graphical symbol information file. Used by the ISE tools and some + third party tools to create a symbol representing the core. + +fifo_s6_2Kx36_2clk.gise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_s6_2Kx36_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_s6_2Kx36_2clk.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_s6_2Kx36_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_s6_2Kx36_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_s6_2Kx36_2clk.xise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_s6_2Kx36_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_s6_2Kx36_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + +fifo_s6_2Kx36_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_xmdf.tcl new file mode 100644 index 000000000..63b4f2099 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_xmdf.tcl @@ -0,0 +1,72 @@ +# The package naming convention is _xmdf +package provide fifo_s6_2Kx36_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_s6_2Kx36_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_s6_2Kx36_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_s6_2Kx36_2clk +} +# ::fifo_s6_2Kx36_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_s6_2Kx36_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_s6_2Kx36_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.asy b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.asy new file mode 100644 index 000000000..5adf4bfb4 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 fifo_s6_512x36_2clk +RECTANGLE Normal 32 32 544 768 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName din[35:0] +PINATTR Polarity IN +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Normal 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Normal 144 800 144 768 +PIN 144 800 BOTTOM 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Wide 576 80 544 80 +PIN 576 80 RIGHT 36 +PINATTR PinName dout[35:0] +PINATTR Polarity OUT +LINE Normal 576 208 544 208 +PIN 576 208 RIGHT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Wide 576 368 544 368 +PIN 576 368 RIGHT 36 +PINATTR PinName wr_data_count[9:0] +PINATTR Polarity OUT +LINE Normal 576 432 544 432 +PIN 576 432 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +LINE Wide 576 592 544 592 +PIN 576 592 RIGHT 36 +PINATTR PinName rd_data_count[9:0] +PINATTR Polarity OUT + diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.gise b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.gise new file mode 100644 index 000000000..f5871667d --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.gise @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.ngc b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.ngc new file mode 100644 index 000000000..523080a69 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.v b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.v new file mode 100644 index 000000000..4b7a31173 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.v @@ -0,0 +1,173 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_s6_512x36_2clk.v when simulating +// the core, fifo_s6_512x36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_s6_512x36_2clk( + rst, + wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + empty, + rd_data_count, + wr_data_count); + + +input rst; +input wr_clk; +input rd_clk; +input [35 : 0] din; +input wr_en; +input rd_en; +output [35 : 0] dout; +output full; +output empty; +output [9 : 0] rd_data_count; +output [9 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V6_1 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(9), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_ENABLE_RST_SYNC(1), + .C_ERROR_INJECTION_TYPE(0), + .C_FAMILY("spartan6"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x36"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(511), + .C_PROG_FULL_THRESH_NEGATE_VAL(510), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(10), + .C_RD_DEPTH(512), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(9), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(1), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(10), + .C_WR_DEPTH(512), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(9), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .RST(rst), + .WR_CLK(wr_clk), + .RD_CLK(rd_clk), + .DIN(din), + .WR_EN(wr_en), + .RD_EN(rd_en), + .DOUT(dout), + .FULL(full), + .EMPTY(empty), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .BACKUP(), + .BACKUP_MARKER(), + .CLK(), + .SRST(), + .WR_RST(), + .RD_RST(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .INT_CLK(), + .INJECTDBITERR(), + .INJECTSBITERR(), + .ALMOST_FULL(), + .WR_ACK(), + .OVERFLOW(), + .ALMOST_EMPTY(), + .VALID(), + .UNDERFLOW(), + .DATA_COUNT(), + .PROG_FULL(), + .PROG_EMPTY(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.veo b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.veo new file mode 100644 index 000000000..766965d02 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.veo @@ -0,0 +1,53 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_s6_512x36_2clk YourInstanceName ( + .rst(rst), + .wr_clk(wr_clk), + .rd_clk(rd_clk), + .din(din), // Bus [35 : 0] + .wr_en(wr_en), + .rd_en(rd_en), + .dout(dout), // Bus [35 : 0] + .full(full), + .empty(empty), + .rd_data_count(rd_data_count), // Bus [9 : 0] + .wr_data_count(wr_data_count)); // Bus [9 : 0] + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_s6_512x36_2clk.v when simulating +// the core, fifo_s6_512x36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xco b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xco new file mode 100644 index 000000000..4f40b8702 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xco @@ -0,0 +1,84 @@ +############################################################## +# +# Xilinx Core Generator version 12.1 +# Date: Fri May 4 20:46:48 2012 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 6.1 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_s6_512x36_2clk +CSET data_count=false +CSET data_count_width=9 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET enable_reset_synchronization=true +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=511 +CSET full_threshold_negate_value=510 +CSET inject_dbit_error=false +CSET inject_sbit_error=false +CSET input_data_width=36 +CSET input_depth=512 +CSET output_data_width=36 +CSET output_depth=512 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=10 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=10 +# END Parameters +GENERATE +# CRC: a4cd75c3 diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xise b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xise new file mode 100644 index 000000000..9f43a161e --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xise @@ -0,0 +1,392 @@ + + + +

+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_s6_512x36_2clk_flist.txt new file mode 100644 index 000000000..e72108931 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk_flist.txt @@ -0,0 +1,13 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +fifo_generator_ug175.pdf +fifo_s6_512x36_2clk.asy +fifo_s6_512x36_2clk.gise +fifo_s6_512x36_2clk.ngc +fifo_s6_512x36_2clk.v +fifo_s6_512x36_2clk.veo +fifo_s6_512x36_2clk.xco +fifo_s6_512x36_2clk.xise +fifo_s6_512x36_2clk_flist.txt +fifo_s6_512x36_2clk_readme.txt +fifo_s6_512x36_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_s6_512x36_2clk_readme.txt new file mode 100644 index 000000000..21f058c0b --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk_readme.txt @@ -0,0 +1,51 @@ +The following files were generated for 'fifo_s6_512x36_2clk' in directory +/home/matt/fpgapriv/usrp2/coregen/ + +fifo_generator_ug175.pdf: + Please see the core data sheet. + +fifo_s6_512x36_2clk.asy: + Graphical symbol information file. Used by the ISE tools and some + third party tools to create a symbol representing the core. + +fifo_s6_512x36_2clk.gise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_s6_512x36_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_s6_512x36_2clk.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_s6_512x36_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_s6_512x36_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_s6_512x36_2clk.xise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_s6_512x36_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_s6_512x36_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + +fifo_s6_512x36_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_s6_512x36_2clk_xmdf.tcl new file mode 100644 index 000000000..150807984 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk_xmdf.tcl @@ -0,0 +1,72 @@ +# The package naming convention is _xmdf +package provide fifo_s6_512x36_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_s6_512x36_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_s6_512x36_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_s6_512x36_2clk +} +# ::fifo_s6_512x36_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_s6_512x36_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_s6_512x36_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.ngc new file mode 100644 index 000000000..b12d34d7c --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$3f24g<,[o}e~g`n;"2*413&;$>"9 > %10?*nhel%fmyz cnpfc`h(|dz$Sni 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v new file mode 100644 index 000000000..1d633384b --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v @@ -0,0 +1,169 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_16x19_2clk.v when simulating +// the core, fifo_xlnx_16x19_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_16x19_2clk( + din, + rd_clk, + rd_en, + rst, + wr_clk, + wr_en, + dout, + empty, + full, + rd_data_count, + wr_data_count); + + +input [18 : 0] din; +input rd_clk; +input rd_en; +input rst; +input wr_clk; +input wr_en; +output [18 : 0] dout; +output empty; +output full; +output [4 : 0] rd_data_count; +output [4 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V4_3 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(5), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(19), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(19), + .C_ENABLE_RLOCS(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(2), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x36"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(15), + .C_PROG_FULL_THRESH_NEGATE_VAL(14), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(5), + .C_RD_DEPTH(16), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(4), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(1), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(5), + .C_WR_DEPTH(16), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(4), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .DIN(din), + .RD_CLK(rd_clk), + .RD_EN(rd_en), + .RST(rst), + .WR_CLK(wr_clk), + .WR_EN(wr_en), + .DOUT(dout), + .EMPTY(empty), + .FULL(full), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .CLK(), + .INT_CLK(), + .BACKUP(), + .BACKUP_MARKER(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .RD_RST(), + .SRST(), + .WR_RST(), + .ALMOST_EMPTY(), + .ALMOST_FULL(), + .DATA_COUNT(), + .OVERFLOW(), + .PROG_EMPTY(), + .PROG_FULL(), + .VALID(), + .UNDERFLOW(), + .WR_ACK(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.veo new file mode 100644 index 000000000..2e9af1efa --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.veo @@ -0,0 +1,53 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_16x19_2clk YourInstanceName ( + .din(din), // Bus [18 : 0] + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .wr_clk(wr_clk), + .wr_en(wr_en), + .dout(dout), // Bus [18 : 0] + .empty(empty), + .full(full), + .rd_data_count(rd_data_count), // Bus [4 : 0] + .wr_data_count(wr_data_count)); // Bus [4 : 0] + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_16x19_2clk.v when simulating +// the core, fifo_xlnx_16x19_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco new file mode 100644 index 000000000..d0f638026 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco @@ -0,0 +1,82 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Fri Sep 11 04:33:27 2009 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = True +SET vhdlsim = False +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.3 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_16x19_2clk +CSET data_count=false +CSET data_count_width=5 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Independent_Clocks_Distributed_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=15 +CSET full_threshold_negate_value=14 +CSET input_data_width=19 +CSET input_depth=16 +CSET output_data_width=19 +CSET output_depth=16 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=5 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=5 +# END Parameters +GENERATE +# CRC: 60b85dda + diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso new file mode 100644 index 000000000..f1a6f7899 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso @@ -0,0 +1,3 @@ +blkmemdp_v6_2 +blk_mem_gen_v2_6 +fifo_generator_v4_3 diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt new file mode 100644 index 000000000..ef33fff67 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt @@ -0,0 +1,103 @@ + + + + + + +
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+ + + diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_flist.txt new file mode 100644 index 000000000..5e1a6ed35 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_flist.txt @@ -0,0 +1,8 @@ +# Output products list for +fifo_xlnx_16x19_2clk.ngc +fifo_xlnx_16x19_2clk.v +fifo_xlnx_16x19_2clk.veo +fifo_xlnx_16x19_2clk.xco +fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_16x19_2clk_flist.txt +fifo_xlnx_16x19_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_readme.txt new file mode 100644 index 000000000..1b5976555 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_readme.txt @@ -0,0 +1,39 @@ +The following files were generated for 'fifo_xlnx_16x19_2clk' in directory +/home/matt/gnuradio.git/usrp2/fpga/coregen/: + +fifo_xlnx_16x19_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_16x19_2clk.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_16x19_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_16x19_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: + Please see the core data sheet. + +fifo_xlnx_16x19_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +fifo_xlnx_16x19_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_16x19_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl new file mode 100644 index 000000000..8d633e9c2 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_16x19_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_16x19_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_16x19_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_16x19_2clk +} +# ::fifo_xlnx_16x19_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_16x19_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_16x19_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.ngc new file mode 100644 index 000000000..f42663419 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$2604g<,[o}e~g`n;"2*413&;$>"9 > %10?*nhel%fmyz cnpfc`h(|dz$Sni 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v new file mode 100644 index 000000000..8a08330d5 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v @@ -0,0 +1,165 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_16x40_2clk.v when simulating +// the core, fifo_xlnx_16x40_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_16x40_2clk( + din, + rd_clk, + rd_en, + rst, + wr_clk, + wr_en, + dout, + empty, + full); + + +input [39 : 0] din; +input rd_clk; +input rd_en; +input rst; +input wr_clk; +input wr_en; +output [39 : 0] dout; +output empty; +output full; + +// synthesis translate_off + + FIFO_GENERATOR_V4_3 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(4), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(40), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(40), + .C_ENABLE_RLOCS(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(0), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(0), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(2), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x72"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(15), + .C_PROG_FULL_THRESH_NEGATE_VAL(14), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(4), + .C_RD_DEPTH(16), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(4), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(0), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(4), + .C_WR_DEPTH(16), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(4), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .DIN(din), + .RD_CLK(rd_clk), + .RD_EN(rd_en), + .RST(rst), + .WR_CLK(wr_clk), + .WR_EN(wr_en), + .DOUT(dout), + .EMPTY(empty), + .FULL(full), + .CLK(), + .INT_CLK(), + .BACKUP(), + .BACKUP_MARKER(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .RD_RST(), + .SRST(), + .WR_RST(), + .ALMOST_EMPTY(), + .ALMOST_FULL(), + .DATA_COUNT(), + .OVERFLOW(), + .PROG_EMPTY(), + .PROG_FULL(), + .VALID(), + .RD_DATA_COUNT(), + .UNDERFLOW(), + .WR_ACK(), + .WR_DATA_COUNT(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.veo new file mode 100644 index 000000000..684078e58 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.veo @@ -0,0 +1,51 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_16x40_2clk YourInstanceName ( + .din(din), // Bus [39 : 0] + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .wr_clk(wr_clk), + .wr_en(wr_en), + .dout(dout), // Bus [39 : 0] + .empty(empty), + .full(full)); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_16x40_2clk.v when simulating +// the core, fifo_xlnx_16x40_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco new file mode 100644 index 000000000..d0da5a6e8 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco @@ -0,0 +1,82 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Tue May 11 20:27:53 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = True +SET vhdlsim = False +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.3 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_16x40_2clk +CSET data_count=false +CSET data_count_width=4 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Independent_Clocks_Distributed_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=15 +CSET full_threshold_negate_value=14 +CSET input_data_width=40 +CSET input_depth=16 +CSET output_data_width=40 +CSET output_depth=16 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=4 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=4 +# END Parameters +GENERATE +# CRC: 6bcb05e1 + diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt new file mode 100644 index 000000000..544bda31d --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt @@ -0,0 +1,98 @@ + + + + + + +
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+ + + +
+ + + diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_flist.txt new file mode 100644 index 000000000..c38f4e991 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_flist.txt @@ -0,0 +1,8 @@ +# Output products list for +fifo_xlnx_16x40_2clk.ngc +fifo_xlnx_16x40_2clk.v +fifo_xlnx_16x40_2clk.veo +fifo_xlnx_16x40_2clk.xco +fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_16x40_2clk_flist.txt +fifo_xlnx_16x40_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_readme.txt new file mode 100644 index 000000000..bbcd4af79 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_readme.txt @@ -0,0 +1,39 @@ +The following files were generated for 'fifo_xlnx_16x40_2clk' in directory +/home/matt/sourcerepo/fpga/usrp2/coregen/: + +fifo_xlnx_16x40_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_16x40_2clk.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_16x40_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_16x40_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: + Please see the core data sheet. + +fifo_xlnx_16x40_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +fifo_xlnx_16x40_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_16x40_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_xmdf.tcl new file mode 100644 index 000000000..2b4824831 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_16x40_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_16x40_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_16x40_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_16x40_2clk +} +# ::fifo_xlnx_16x40_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_16x40_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_16x40_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.asy b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.asy new file mode 100644 index 000000000..a87aa2f84 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 fifo_xlnx_2Kx36_2clk +RECTANGLE Normal 32 32 544 672 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName din[35:0] +PINATTR Polarity IN +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Normal 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Normal 144 704 144 672 +PIN 144 704 BOTTOM 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Wide 576 80 544 80 +PIN 576 80 RIGHT 36 +PINATTR PinName dout[35:0] +PINATTR Polarity OUT +LINE Normal 576 208 544 208 +PIN 576 208 RIGHT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Wide 576 368 544 368 +PIN 576 368 RIGHT 36 +PINATTR PinName wr_data_count[11:0] +PINATTR Polarity OUT +LINE Normal 576 432 544 432 +PIN 576 432 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +LINE Wide 576 592 544 592 +PIN 576 592 RIGHT 36 +PINATTR PinName rd_data_count[11:0] +PINATTR Polarity OUT + diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.ngc new file mode 100644 index 000000000..684eb74f4 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$7134g<,[o}e~g`n;"2*413&;$>"9 > %10?*nhel%fmyz cnpfc`h(|dz$Sni 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.sym b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.sym new file mode 100644 index 000000000..5d56b5c98 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.sym @@ -0,0 +1,74 @@ +VERSION 5 +BEGIN SYMBOL fifo_xlnx_2Kx36_2clk +SYMBOLTYPE BLOCK +TIMESTAMP 2009 9 3 17 25 13 +SYMPIN 0 80 Input din[35:0] +SYMPIN 0 144 Input wr_en +SYMPIN 0 176 Input wr_clk +SYMPIN 0 240 Input rd_en +SYMPIN 0 272 Input rd_clk +SYMPIN 144 704 Input rst +SYMPIN 576 80 Output dout[35:0] +SYMPIN 576 208 Output full +SYMPIN 576 368 Output wr_data_count[11:0] +SYMPIN 576 432 Output empty +SYMPIN 576 592 Output rd_data_count[11:0] +BEGIN DISPLAY 32 32 TEXT fifo_xlnx_2Kx36_2clk + FONT 40 "Arial" +END DISPLAY +RECTANGLE N 32 32 544 672 +BEGIN LINE W 0 80 32 80 +END LINE +BEGIN DISPLAY 36 80 PIN din[35:0] ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 144 32 144 +BEGIN DISPLAY 36 144 PIN wr_en ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 176 32 176 +BEGIN DISPLAY 36 176 PIN wr_clk ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 240 32 240 +BEGIN DISPLAY 36 240 PIN rd_en ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 272 32 272 +BEGIN DISPLAY 36 272 PIN rd_clk ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 144 704 144 672 +BEGIN DISPLAY 144 668 PIN rst ATTR PinName + ALIGNMENT BCENTER + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 80 544 80 +END LINE +BEGIN DISPLAY 540 80 PIN dout[35:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +LINE N 576 208 544 208 +BEGIN DISPLAY 540 208 PIN full ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 368 544 368 +END LINE +BEGIN DISPLAY 540 368 PIN wr_data_count[11:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +LINE N 576 432 544 432 +BEGIN DISPLAY 540 432 PIN empty ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 592 544 592 +END LINE +BEGIN DISPLAY 540 592 PIN rd_data_count[11:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +END SYMBOL diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v new file mode 100644 index 000000000..0762b3ae9 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v @@ -0,0 +1,173 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_2Kx36_2clk.v when simulating +// the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_2Kx36_2clk( + din, + rd_clk, + rd_en, + rst, + wr_clk, + wr_en, + dout, + empty, + full, + rd_data_count, + wr_data_count); + + +input [35 : 0] din; +input rd_clk; +input rd_en; +input rst; +input wr_clk; +input wr_en; +output [35 : 0] dout; +output empty; +output full; +output [11 : 0] rd_data_count; +output [11 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V4_3 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(12), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("2kx18"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(2047), + .C_PROG_FULL_THRESH_NEGATE_VAL(2046), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(12), + .C_RD_DEPTH(2048), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(11), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(1), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(12), + .C_WR_DEPTH(2048), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(11), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .DIN(din), + .RD_CLK(rd_clk), + .RD_EN(rd_en), + .RST(rst), + .WR_CLK(wr_clk), + .WR_EN(wr_en), + .DOUT(dout), + .EMPTY(empty), + .FULL(full), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .CLK(), + .INT_CLK(), + .BACKUP(), + .BACKUP_MARKER(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .RD_RST(), + .SRST(), + .WR_RST(), + .ALMOST_EMPTY(), + .ALMOST_FULL(), + .DATA_COUNT(), + .OVERFLOW(), + .PROG_EMPTY(), + .PROG_FULL(), + .VALID(), + .UNDERFLOW(), + .WR_ACK(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +// XST black box declaration +// box_type "black_box" +// synthesis attribute box_type of fifo_xlnx_2Kx36_2clk is "black_box" + +endmodule + diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.veo new file mode 100644 index 000000000..af9191555 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.veo @@ -0,0 +1,53 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_2Kx36_2clk YourInstanceName ( + .din(din), // Bus [35 : 0] + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .wr_clk(wr_clk), + .wr_en(wr_en), + .dout(dout), // Bus [35 : 0] + .empty(empty), + .full(full), + .rd_data_count(rd_data_count), // Bus [11 : 0] + .wr_data_count(wr_data_count)); // Bus [11 : 0] + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_2Kx36_2clk.v when simulating +// the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd new file mode 100644 index 000000000..53033dc97 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd @@ -0,0 +1,156 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file fifo_xlnx_2Kx36_2clk.vhd when simulating +-- the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY fifo_xlnx_2Kx36_2clk IS + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(11 downto 0); + wr_data_count: OUT std_logic_VECTOR(11 downto 0)); +END fifo_xlnx_2Kx36_2clk; + +ARCHITECTURE fifo_xlnx_2Kx36_2clk_a OF fifo_xlnx_2Kx36_2clk IS +-- synthesis translate_off +component wrapped_fifo_xlnx_2Kx36_2clk + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(11 downto 0); + wr_data_count: OUT std_logic_VECTOR(11 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_fifo_xlnx_2Kx36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral) + generic map( + c_has_int_clk => 0, + c_rd_freq => 1, + c_wr_response_latency => 1, + c_has_srst => 0, + c_has_rd_data_count => 1, + c_din_width => 36, + c_has_wr_data_count => 1, + c_full_flags_rst_val => 1, + c_implementation_type => 2, + c_family => "spartan3", + c_use_embedded_reg => 0, + c_has_wr_rst => 0, + c_wr_freq => 1, + c_use_dout_rst => 1, + c_underflow_low => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_preload_latency => 0, + c_dout_width => 36, + c_msgon_val => 1, + c_rd_depth => 2048, + c_default_value => "BlankString", + c_mif_file_name => "BlankString", + c_has_underflow => 0, + c_has_rd_rst => 0, + c_has_almost_full => 0, + c_has_rst => 1, + c_data_count_width => 12, + c_has_wr_ack => 0, + c_use_ecc => 0, + c_wr_ack_low => 0, + c_common_clock => 0, + c_rd_pntr_width => 11, + c_use_fwft_data_count => 1, + c_has_almost_empty => 0, + c_rd_data_count_width => 12, + c_enable_rlocs => 0, + c_wr_pntr_width => 11, + c_overflow_low => 0, + c_prog_empty_type => 0, + c_optimization_mode => 0, + c_wr_data_count_width => 12, + c_preload_regs => 1, + c_dout_rst_val => "0", + c_has_data_count => 0, + c_prog_full_thresh_negate_val => 2046, + c_wr_depth => 2048, + c_prog_empty_thresh_negate_val => 5, + c_prog_empty_thresh_assert_val => 4, + c_has_valid => 0, + c_init_wr_pntr_val => 0, + c_prog_full_thresh_assert_val => 2047, + c_use_fifo16_flags => 0, + c_has_backup => 0, + c_valid_low => 0, + c_prim_fifo_type => "2kx18", + c_count_type => 0, + c_prog_full_type => 0, + c_memory_type => 1); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_fifo_xlnx_2Kx36_2clk + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full, + rd_data_count => rd_data_count, + wr_data_count => wr_data_count); +-- synthesis translate_on + +END fifo_xlnx_2Kx36_2clk_a; + diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vho b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vho new file mode 100644 index 000000000..5165b0bc4 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vho @@ -0,0 +1,76 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component fifo_xlnx_2Kx36_2clk + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(11 downto 0); + wr_data_count: OUT std_logic_VECTOR(11 downto 0)); +end component; + +-- Synplicity black box declaration +attribute syn_black_box : boolean; +attribute syn_black_box of fifo_xlnx_2Kx36_2clk: component is true; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : fifo_xlnx_2Kx36_2clk + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full, + rd_data_count => rd_data_count, + wr_data_count => wr_data_count); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file fifo_xlnx_2Kx36_2clk.vhd when simulating +-- the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco new file mode 100644 index 000000000..e25ad38da --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco @@ -0,0 +1,82 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Thu Sep 3 17:25:43 2009 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = True +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Foundation_iSE +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = True +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.3 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_2Kx36_2clk +CSET data_count=false +CSET data_count_width=12 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=2047 +CSET full_threshold_negate_value=2046 +CSET input_data_width=36 +CSET input_depth=2048 +CSET output_data_width=36 +CSET output_depth=2048 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=12 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=12 +# END Parameters +GENERATE +# CRC: 2ae9f6ef + diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso new file mode 100644 index 000000000..f1a6f7899 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso @@ -0,0 +1,3 @@ +blkmemdp_v6_2 +blk_mem_gen_v2_6 +fifo_generator_v4_3 diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt new file mode 100644 index 000000000..5108be2c5 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt @@ -0,0 +1,106 @@ + + + + + + +
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+ + + diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_flist.txt new file mode 100644 index 000000000..670d84713 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_flist.txt @@ -0,0 +1,12 @@ +# Output products list for +fifo_xlnx_2Kx36_2clk.asy +fifo_xlnx_2Kx36_2clk.ngc +fifo_xlnx_2Kx36_2clk.sym +fifo_xlnx_2Kx36_2clk.v +fifo_xlnx_2Kx36_2clk.veo +fifo_xlnx_2Kx36_2clk.vhd +fifo_xlnx_2Kx36_2clk.vho +fifo_xlnx_2Kx36_2clk.xco +fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_2Kx36_2clk_flist.txt +fifo_xlnx_2Kx36_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_readme.txt new file mode 100644 index 000000000..1879503a9 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_readme.txt @@ -0,0 +1,55 @@ +The following files were generated for 'fifo_xlnx_2Kx36_2clk' in directory +/home/matt/gnuradio.git/usrp2/fpga/coregen/: + +fifo_xlnx_2Kx36_2clk.asy: + Graphical symbol information file. Used by the ISE tools and some + third party tools to create a symbol representing the core. + +fifo_xlnx_2Kx36_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_2Kx36_2clk.sym: + Please see the core data sheet. + +fifo_xlnx_2Kx36_2clk.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_2Kx36_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_2Kx36_2clk.vhd: + VHDL wrapper file provided to support functional simulation. This + file contains simulation model customization data that is passed to + a parameterized simulation model for the core. + +fifo_xlnx_2Kx36_2clk.vho: + VHO template file containing code that can be used as a model for + instantiating a CORE Generator module in a VHDL design. + +fifo_xlnx_2Kx36_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: + Please see the core data sheet. + +fifo_xlnx_2Kx36_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +fifo_xlnx_2Kx36_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_2Kx36_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl new file mode 100644 index 000000000..cac25efd2 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl @@ -0,0 +1,84 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_2Kx36_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_2Kx36_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_2Kx36_2clk +} +# ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.sym +utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_2Kx36_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise new file mode 100644 index 000000000..c078f4dd7 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc new file mode 100644 index 000000000..d1ed419a7 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$56140<,[o}e~g`n;"2*726&;$9,)<>;.vnt*Ydo&lbjbQwloz\77~4>V8h`f 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6202>80q~:>5;296~X39<16>o4;149'711=?<1vqcm50;0xL62?3tdh8<4?:3yK71>7>52zJ00==zfj>86=4={I17<>{ik=>1<73:1>vF<499~jf202909wE=;8:mg1>=838pD>:7;|l`0<<72;qC?964}oa7e?6=:rB8855rnb6a>5<5sA9?46sac5a94?4|@:>37p`l4e83>7}O;=20qcm;e;296~N4<11vbn:i:181M5302weo8>50;0xL62?3tdh9<4?:3yK71>>7>52zJ00==zfj?86=4={I17<>{ik<>1<73:1>vF<499~jf302909wE=;8:mg0>=838pD>:7;|l`1<<72;qC?964}oa6e?6=:rB8855rnb7a>5<5sA9?46sac4a94?4|@:>37p`l5e83>7}O;=20qcm:e;296~N4<11vbn;i:181M5302weo;>50;0xL62?3tdh:<4?:3yK71>7>52zJ00==zfj<86=4={I17<>{ik?>1<7<0;6?uG35:8yke1>3:1>vF<499~jf002909wE=;8:mg3>=838pD>:7;|l`2<<72;qC?964}oa5e?6=:rB8855rnb4a>5<5sA9?46sac7a94?4|@:>37p`l6e83>7}O;=20qcm9e;296~N4<11vbn8i:181M5302weo:>50;0xL62?3tdh;<4?:3yK71>7>52zJ00==zfj=86=4={I17<>{ik>>1<73:1>vF<499~jf102909wE=;8:mg2>=838pD>:7;|l`3<<72;qC?964}oa4e?6=:rB8855rnb5a>5<5sA9?46sac6a94?4|@:>37p`l7e83>7}O;=20qcm8e;296~N4<11vbn9i:181M5302weo5>50;0xL62?3tdh4<4?:3yK71>7>52zJ00==zfj286=4={I17<>{ik1>1<73:1>vF<499~jf>02909wE=;8:mg=>=838pD>:7;|l`<<<72;qC?964}oa;e?6=:rB8855rnb:a>5<5sA9?46sac9a94?4|@:>37p`l8e83>7}O;=20qcm7e;296~N4<11vbll9:182M5302wen=950;3xL62?3tdi<54?:0yK71>51zJ00==zfk:j6=4>{I17<>{ij9h1<7?tH26;?xhe8j0;6:7;|la55<728qC?964}o`25?6=9rB8855rnc31>5<6sA9?46sab0194?7|@:>37p`m1583>4}O;=20qcl>5;295~N4<11vbo?9:182M5302wen<950;3xL62?3tdi=54?:0yK71>51zJ00==zfk;j6=4>{I17<>{ij8h1<7?tH26;?xhe9j0;6:7;|la65<728qC?964}o`15?6=9rB8855rnc01>5<6sA9?46sab3194?7|@:>37p`m2583>4}O;=20qcl=5;295~N4<11vbo<9:182M5302wen?950;3xL62?3tdi>54?:0yK71>51zJ00==zfk8j6=4>{I17<>{ij;h1<7?tH26;?xhe:j0;6:7;|la75<728qC?964}o`05?6=9rB8855rnc11>5<6sA9?46sab2194?7|@:>37p`m3583>4}O;=20qcl<5;295~N4<11vbo=9:182M5302wen>950;3xL62?3tdi?54?:0yK71>51zJ00==zfk9j6=4>{I17<>{ij:h1<7?tH26;?xhe;j0;6:7;|la05<728qC?964}o`75?6=9rB8855rnc61>5<6sA9?46sab5194?7|@:>37p`m4583>4}O;=20qcl;5;295~N4<11vbo:9:182M5302wen9950;3xL62?3tdi854?:0yK71>51zJ00==zfk>j6=4>{I17<>{ij=h1<7?tH26;?xhe:7;|la15<728qC?964}o`65?6=9rB8855rnc71>5<6sA9?46sab4194?7|@:>37p`m5583>4}O;=20qcl:5;295~N4<11vbo;9:182M5302wen8950;3xL62?3tdi954?:0yK71>57>51zJ00==zfk?j6=4>{I17<>{ij:7;|la25<728qC?964}o`55?6=9rB8855rnc41>5<6sA9?46sab7194?7|@:>37p`m6583>4}O;=20qcl95;295~N4<11vbo89:182M5302wen;950;3xL62?3tdi:54?:0yK71>51zJ00==zfk{I17<>{ij?h1<7?tH26;?xhe>j0;6:7;|la35<728qC?964}o`45?6=9rB8855rnc51>5<6sA9?46sab6194?7|@:>37p`m7583>4}O;=20qcl85;295~N4<11vbo99:182M5302wen:950;3xL62?3tdi;54?:0yK71>51zJ00==zfk=j6=4>{I17<>{ij>h1<7?tH26;?xhe?j0;6:7;|la<5<728qC?964}o`;5?6=9rB8855rnc:1>5<6sA9?46sab9194?7|@:>37p`m8583>4}O;=20qcl75;295~N4<11vbo69:182M5302wen5950;3xL62?3tdi454?:0yK71>51zJ00==zfk2j6=4>{I17<>{ij1h1<7?tH26;?xhe0j0;6b290:wE=;8:mf=`=83;pD>:7;|la=5<728qC?964}o`:5?6=9rB8855rnc;1>5<6sA9?46sab8194?7|@:>37p`m9583>4}O;=20qcl65;295~N4<11vbo79:182M5302wen4950;3xL62?3tdi554?:0yK71>51zJ00==zfk3j6=4>{I17<>{ij0h1<7?tH26;?xhe1j0;6l3:1=vF<499~jg?b290:wE=;8:mf<`=83;pD>:7;|lae5<728qC?964}o`b5?6=9rB8855rncc1>5<6sA9?46sab`194?7|@:>37p`ma583>4}O;=20qcln5;295~N4<11vboo9:182M5302wenl950;3xL62?3tdim54?:0yK71>51zJ00==zfkkj6=4>{I17<>{ijhh1<7?tH26;?xheij0;6:7;|laf5<728qC?964}o`a5?6=9rB8855rnc`1>5<6sA9?46sabc194?7|@:>37p`mb583>4}O;=20qclm5;295~N4<11vbol9:182M5302weno950;3xL62?3tdin54?:0yK71>51zJ00==zfkhj6=4>{I17<>{ijkh1<7?tH26;?xhejj0;6:7;|lag5<728qC?964}o``5?6=9rB8855rnca1>5<6sA9?46sabb194?7|@:>37p`mc583>4}O;=20qcll5;295~N4<11vbom9:182M5302wenn950;3xL62?3tdio54?:0yK71>51zJ00==zfkij6=4>{I17<>{ijjh1<7?tH26;?xhekj0;6:7;|la`5<728qC?964}o`g5?6=9rB8855rncf1>5<6sA9?46sabe194?7|@:>37p`md583>4}O;=20qclk5;295~N4<11vboj9:182M5302weni950;3xL62?3tdih54?:0yK71>51zJ00==zfknj6=4>{I17<>{ijmh1<7?tH26;?xhelj0;6:7;|laa5<728qC?964}o`f5?6=9rB8855rncg1>5<6sA9?46sabd194?7|@:>37p`me583>4}O;=20qclj5;295~N4<11vbok9:182M5302wenh950;3xL62?3tdii54?:0yK71>51zJ00==zfkoj6=4>{I17<>{ijlh1<7?tH26;?xhemj0;6:7;|lab5<728qC?964}o`e5?6=9rB8855rncd1>5<6sA9?46sabg194?7|@:>37p`mf583>4}O;=20qcli5;295~N4<11vboh9:182M5302wenk950;3xL62?3tdij54?:0yK71>51zJ00==zfklj6=4>{I17<>{ijoh1<7?tH26;?xhenj0;6:7;|l`45<728qC?964}oa35?6=9rB8855rnb21>5<6sA9?46sac1194?7|@:>37p`l0583>4}O;=20qcm?5;295~N4<11vbn>9:182M5302weo=950;3xL62?3tdh<54?:0yK71>51zJ00==zfj:j6=4>{I17<>{ik9h1<7?tH26;?xhd8j0;6:7;|l`55<728qC?964}oa25?6=9rB8855rnb31>5<6sA9?46sac0194?7|@:>37p`l1583>4}O;=20qcm>5;295~N4<11vbn?9:182M5302weo<950;3xL62?3tdh=54?:0yK71>51zJ00==zfj;j6=4>{I17<>{ik8h1<7?tH26;?xhd9j0;6:7;|l`65<728qC?964}oa15?6=9rB8855rnb01>5<6sA9?46sac3194?7|@:>37p`l2583>4}O;=20qcm=5;295~N4<11vbn<9:182M5302weo?950;3xL62?3tdh>54?:0yK71>51zJ00==zfj8j6=4>{I17<>{ik;h1<7?tH26;?xhd:j0;6:7;|l`75<728qC?964}oa05?6=9rB8855rnb11>5<6sA9?46sac2194?7|@:>37p`l3583>4}O;=20qcm<5;295~N4<11vbn=9:182M5302weo>950;3xL62?3tdh?54?:0yK71>51zJ00==zfj9j6=4>{I17<>{ik:h1<7?tH26;?xhd;j0;6111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), + .LO(\BU2/U0/grf.rf/gl0.rd/rpntr/N11 ) + ); + LUT3_L #( + .INIT ( 8'h7F )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3>111 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), + .LO(\BU2/U0/grf.rf/gl0.wr/wpntr/N11 ) + ); + LUT2_L #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_SW0 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]), + .LO(\BU2/N16 ) + ); + LUT2_L #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_SW0 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]), + .LO(\BU2/N14 ) + ); + INV \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<0>11_INV_0 ( + .I(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ) + ); + INV \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<0>11_INV_0 ( + .I(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_1 ( + .I0(wr_en), + .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), + .O(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ) + ); + LUT4 #( + .INIT ( 16'h2333 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_1 ( + .I0(rd_en), + .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), + .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ) + ); + LUT4 #( + .INIT ( 16'h6AAA )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<3>12 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), + .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ) + ); + LUT4 #( + .INIT ( 16'h6AAA )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3>12 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1 ( + .I0(wr_en), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]), + .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ) + ); + LUT3 #( + .INIT ( 8'h10 )) + \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]), + .I2(wr_en), + .O(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<5> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [5]) + ); + LUT4 #( + .INIT ( 16'h9000 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i78 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]), + .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 ), + .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ) + ); + LUT4 #( + .INIT ( 16'h9000 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 ), + .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 ), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<4> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<3> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [3]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<2> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [2]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<1> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [1]) + ); + LUT4 #( + .INIT ( 16'h5450 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000105 ( + .I0(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 ), + .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 ), + .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]), + .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]), + .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 ) + ); + LUT4 #( + .INIT ( 16'h8421 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 ) + ); + LUT4 #( + .INIT ( 16'h5450 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000107 ( + .I0(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ), + .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 ), + .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ), + .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]), + .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]), + .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1 ( + .I0(wr_en), + .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 ) + ); + LUT4 #( + .INIT ( 16'hECA0 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000183 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 ), + .I3(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 ), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 ) + ); + LUT4 #( + .INIT ( 16'h8421 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 ) + ); + LUT4 #( + .INIT ( 16'h8241 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 ) + ); + LUT4 #( + .INIT ( 16'h2333 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21 ( + .I0(rd_en), + .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), + .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 ) + ); + LUT3 #( + .INIT ( 8'hA6 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<4>11 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/N11 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ) + ); + LUT3 #( + .INIT ( 8'hA6 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<4>11 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/N11 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX11 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N5 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N7 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [0]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1011 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N45 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N47 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [10]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N9 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N11 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [1]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX11111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N49 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N51 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [11]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1211 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N53 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N55 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [12]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1311 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N57 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N59 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [13]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1411 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N61 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N63 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [14]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1511 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N65 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N67 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [15]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1611 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N69 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N71 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [16]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1711 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N73 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N75 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [17]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1811 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N77 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N79 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [18]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1911 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N81 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N83 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [19]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2011 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N85 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N87 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [20]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N13 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N15 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [2]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX21111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N89 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N91 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [21]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2211 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N93 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N95 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [22]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2311 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N97 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N99 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [23]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2411 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N101 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N103 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [24]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2511 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N105 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N107 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [25]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2611 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N109 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N111 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [26]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2711 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N113 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N115 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [27]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2811 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N117 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N119 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [28]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2911 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N121 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N123 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [29]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3011 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N125 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N127 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [30]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N17 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N19 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [3]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX31111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N129 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N131 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [31]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3211 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N133 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N135 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [32]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3311 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N137 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N139 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [33]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3411 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N141 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N143 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [34]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3511 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N145 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N147 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [35]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX411 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N21 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N23 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [4]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX511 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N25 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N27 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [5]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX611 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N29 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N31 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [6]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX711 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N33 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N35 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [7]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX811 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N37 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N39 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [8]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX911 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N41 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N43 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [9]) + ); + LUT4 #( + .INIT ( 16'h6996 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), + .I3(\BU2/N16 ), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 ) + ); + LUT4 #( + .INIT ( 16'h6996 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0]), + .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), + .I3(\BU2/N14 ), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 ) + ); + LUT3 #( + .INIT ( 8'hA2 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_REGOUT_EN11 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), + .I2(rd_en), + .O(\BU2/U0/grf.rf/mem/dout_i_not0001 ) + ); + LUT2 #( + .INIT ( 4'hD )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_not00011 ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), + .I1(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ) + ); + LUT4 #( + .INIT ( 16'h8E8A )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux00001 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), + .I3(rd_en), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ) + ); + LUT4 #( + .INIT ( 16'h6996 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00021 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ) + ); + LUT4 #( + .INIT ( 16'h6996 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00021 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]), + .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ) + ); + LUT4 #( + .INIT ( 16'h40FF )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001<0>1 ( + .I0(rd_en), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), + .I3(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [0]) + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<2>11 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<2>11 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00011 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00011 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]), + .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ) + ); + LUT3 #( + .INIT ( 8'hF2 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001<1>1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), + .I1(rd_en), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [1]) + ); + LUT3 #( + .INIT ( 8'h08 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux00031 ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [4]), + .I1(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [5]), + .I2(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0000_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0001_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0002_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0003_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0000_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0001_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0002_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0003_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<1>11 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<1>11 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00001 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00001 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \BU2/U0/grf.rf/rstblk/rd_rst_comb1 ( + .I0(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 ), + .I1(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ), + .O(\BU2/U0/grf.rf/rstblk/rd_rst_comb ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \BU2/U0/grf.rf/rstblk/wr_rst_comb1 ( + .I0(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 ), + .I1(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ), + .O(\BU2/U0/grf.rf/rstblk/wr_rst_comb ) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), + .Q(almost_full) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), + .Q(full) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), + .Q(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_0 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [0]), + .Q(dout_3[0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_1 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [1]), + .Q(dout_3[1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_2 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [2]), + .Q(dout_3[2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_3 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [3]), + .Q(dout_3[3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_4 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [4]), + .Q(dout_3[4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_5 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [5]), + .Q(dout_3[5]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_6 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [6]), + .Q(dout_3[6]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_7 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [7]), + .Q(dout_3[7]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_8 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [8]), + .Q(dout_3[8]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_9 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [9]), + .Q(dout_3[9]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_10 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [10]), + .Q(dout_3[10]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_11 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [11]), + .Q(dout_3[11]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_12 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [12]), + .Q(dout_3[12]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_13 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [13]), + .Q(dout_3[13]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_14 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [14]), + .Q(dout_3[14]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_15 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [15]), + .Q(dout_3[15]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_16 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [16]), + .Q(dout_3[16]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_17 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [17]), + .Q(dout_3[17]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_18 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [18]), + .Q(dout_3[18]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_19 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [19]), + .Q(dout_3[19]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_20 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [20]), + .Q(dout_3[20]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_21 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [21]), + .Q(dout_3[21]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_22 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [22]), + .Q(dout_3[22]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_23 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [23]), + .Q(dout_3[23]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_24 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [24]), + .Q(dout_3[24]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_25 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [25]), + .Q(dout_3[25]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_26 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [26]), + .Q(dout_3[26]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_27 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [27]), + .Q(dout_3[27]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_28 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [28]), + .Q(dout_3[28]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_29 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [29]), + .Q(dout_3[29]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_30 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [30]), + .Q(dout_3[30]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_31 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [31]), + .Q(dout_3[31]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_32 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [32]), + .Q(dout_3[32]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_33 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [33]), + .Q(dout_3[33]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_34 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [34]), + .Q(dout_3[34]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_35 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [35]), + .Q(dout_3[35]) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[35]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N147 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[35]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N145 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[34]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N143 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[34]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N141 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[33]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N137 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[32]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N135 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[33]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N139 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[32]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N133 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[31]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N131 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[31]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N129 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[30]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N127 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[29]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N123 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[29]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N121 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[30]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N125 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[28]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N119 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[28]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N117 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[27]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N115 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[27]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N113 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[26]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N109 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[25]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N107 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[26]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N111 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[24]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N103 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[24]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N101 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[25]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N105 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[23]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N97 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[22]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N95 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[23]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N99 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[22]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N93 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[21]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N91 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[21]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N89 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[20]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N87 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[19]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N83 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[19]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N81 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[20]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N85 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[18]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N79 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[18]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N77 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[17]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N75 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[17]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N73 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[16]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N69 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[15]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N67 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[16]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N71 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[15]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N65 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[14]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N63 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[14]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N61 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[13]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N59 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[12]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N55 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[12]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N53 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[13]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N57 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[11]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N51 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[11]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N49 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[10]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N47 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[10]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N45 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[9]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N41 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[8]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N39 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[9]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N43 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[8]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N37 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[7]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N35 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[7]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N33 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[6]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N31 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[5]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N27 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[5]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N25 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[6]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N29 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[4]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N23 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[4]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N21 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[3]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N19 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[3]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N17 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[2]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N13 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[1]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N11 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[2]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N15 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[1]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N9 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[0]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N7 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[0]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N5 ) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_35 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [35]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [35]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_34 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [34]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [34]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_33 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [33]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [33]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_32 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [32]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [32]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_31 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [31]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [31]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_30 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [30]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [30]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_29 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [29]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [29]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_28 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [28]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [28]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_27 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [27]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [27]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_26 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [26]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [26]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_25 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [25]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [25]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_24 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [24]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [24]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_23 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [23]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [23]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_22 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [22]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [22]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_21 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [21]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [21]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_20 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [20]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [20]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_19 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [19]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [19]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_18 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [18]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [18]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_17 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [17]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [17]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_16 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [16]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [16]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_15 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [15]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [15]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_14 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [14]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [14]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_13 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [13]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [13]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_12 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [12]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [12]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_11 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [11]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [11]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_10 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [10]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [10]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_9 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [9]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [9]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_8 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [8]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [8]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_7 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [7]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [7]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_6 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [6]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [6]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_5 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [5]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [5]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_4 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [4]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_3 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [3]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_2 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [2]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_1 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [1]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_0 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [0]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_0 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_1 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_2 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_3 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_4 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_4 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_3 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_1 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_0 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_2 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_4 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_3 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_1 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_0 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_2 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_2 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_0 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_1 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_3 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_4 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 ), + .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), + .Q(prog_full) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [4]), + .Q(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_5 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [5]), + .Q(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [5]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<0> ( + .CI(\BU2/N1 ), + .DI(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .S(\BU2/rd_data_count [0]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [0]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<1> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [0]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [1]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [1]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<2> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [1]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [2]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [2]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<3> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [2]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [3]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<4> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [4]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_xor<4> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]), + .LI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [4]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_xor<5> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [4]), + .LI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [5]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [5]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [1]), + .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [0]), + .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .Q(empty) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 ) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_0 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_1 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_2 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_3 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_4 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_2 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_0 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_1 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_3 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_4 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_0 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_1 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_2 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_3 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_2 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_3 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_4 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_0 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_1 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_2 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_3 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_2 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_3 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_4 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_0 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_1 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_2 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_3 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_2 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_3 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_4 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_2 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_3 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_4 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_0 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_1 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_2 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_3 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/wr_rst_reg_0 ( + .C(wr_clk), + .D(\BU2/rd_data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/wr_rst_reg_1 ( + .C(wr_clk), + .D(\BU2/rd_data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/rd_rst_reg_0 ( + .C(rd_clk), + .D(\BU2/rd_data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/rd_rst_reg_1 ( + .C(rd_clk), + .D(\BU2/rd_data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/rd_rst_reg_2 ( + .C(rd_clk), + .D(\BU2/rd_data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/rst_d1 ( + .C(wr_clk), + .D(\BU2/rd_data_count [0]), + .PRE(rst), + .Q(\BU2/U0/grf.rf/rstblk/rst_d1_93 ) + ); + FDPE \BU2/U0/grf.rf/rstblk/rd_rst_asreg ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ), + .D(\BU2/rd_data_count [0]), + .PRE(rst), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1 ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ) + ); + FDPE \BU2/U0/grf.rf/rstblk/wr_rst_asreg ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ), + .D(\BU2/rd_data_count [0]), + .PRE(rst), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1 ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/rst_d2 ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/rstblk/rst_d1_93 ), + .PRE(rst), + .Q(\BU2/U0/grf.rf/rstblk/rst_d2_88 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2 ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2 ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 ) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/rst_d3 ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), + .PRE(rst), + .Q(\BU2/U0/grf.rf/rstblk/rst_d3_86 ) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/RST_FULL_GEN ( + .C(wr_clk), + .CLR(rst), + .D(\BU2/U0/grf.rf/rstblk/rst_d3_86 ), + .Q(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .Q(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ) + ); + VCC \BU2/XST_VCC ( + .P(\BU2/N1 ) + ); + GND \BU2/XST_GND ( + .G(\BU2/rd_data_count [0]) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo new file mode 100644 index 000000000..eb98a2b70 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo @@ -0,0 +1,47 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_32x36_2clk YourInstanceName ( + .rst(rst), + .wr_clk(wr_clk), + .rd_clk(rd_clk), + .din(din), // Bus [35 : 0] + .wr_en(wr_en), + .rd_en(rd_en), + .dout(dout), // Bus [35 : 0] + .full(full), + .almost_full(almost_full), + .empty(empty), + .prog_full(prog_full)); + +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco new file mode 100644 index 000000000..1cf4c8ba5 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco @@ -0,0 +1,84 @@ +############################################################## +# +# Xilinx Core Generator version 12.2 +# Date: Fri Oct 15 07:50:15 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = false +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Structural +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 6.1 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=true +CSET component_name=fifo_xlnx_32x36_2clk +CSET data_count=false +CSET data_count_width=5 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET enable_reset_synchronization=true +CSET fifo_implementation=Independent_Clocks_Distributed_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=24 +CSET full_threshold_negate_value=23 +CSET inject_dbit_error=false +CSET inject_sbit_error=false +CSET input_data_width=36 +CSET input_depth=32 +CSET output_data_width=36 +CSET output_depth=32 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=5 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=5 +# END Parameters +GENERATE +# CRC: 8e84ee7f diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise new file mode 100644 index 000000000..b9eb7bd1a --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise @@ -0,0 +1,72 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt new file mode 100644 index 000000000..b8c69a9f7 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt @@ -0,0 +1,12 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +fifo_generator_ug175.pdf +fifo_xlnx_32x36_2clk.gise +fifo_xlnx_32x36_2clk.ngc +fifo_xlnx_32x36_2clk.v +fifo_xlnx_32x36_2clk.veo +fifo_xlnx_32x36_2clk.xco +fifo_xlnx_32x36_2clk.xise +fifo_xlnx_32x36_2clk_flist.txt +fifo_xlnx_32x36_2clk_readme.txt +fifo_xlnx_32x36_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt new file mode 100644 index 000000000..8ab5679fd --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt @@ -0,0 +1,46 @@ +The following files were generated for 'fifo_xlnx_32x36_2clk' in directory +/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ + +fifo_generator_ug175.pdf: + Please see the core data sheet. + +fifo_xlnx_32x36_2clk.gise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_32x36_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_32x36_2clk.v: + Unisim Verilog file containing the information required to simulate + the module. + +fifo_xlnx_32x36_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_32x36_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_32x36_2clk.xise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_32x36_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_32x36_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + +fifo_xlnx_32x36_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl new file mode 100644 index 000000000..ec9426357 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_32x36_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_32x36_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_32x36_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_32x36_2clk +} +# ::fifo_xlnx_32x36_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_32x36_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_32x36_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.asy b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.asy new file mode 100644 index 000000000..ecc80b648 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 fifo_xlnx_512x36_2clk +RECTANGLE Normal 32 32 544 672 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName din[35:0] +PINATTR Polarity IN +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Normal 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Normal 144 704 144 672 +PIN 144 704 BOTTOM 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Wide 576 80 544 80 +PIN 576 80 RIGHT 36 +PINATTR PinName dout[35:0] +PINATTR Polarity OUT +LINE Normal 576 208 544 208 +PIN 576 208 RIGHT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Wide 576 368 544 368 +PIN 576 368 RIGHT 36 +PINATTR PinName wr_data_count[8:0] +PINATTR Polarity OUT +LINE Normal 576 432 544 432 +PIN 576 432 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +LINE Wide 576 592 544 592 +PIN 576 592 RIGHT 36 +PINATTR PinName rd_data_count[8:0] +PINATTR Polarity OUT + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.ngc new file mode 100644 index 000000000..55486485a --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$4g64g<,[o}e~g`n;"2*413&;$>"9 > %17?*nhel%fmyz cnpfc`h(|dz$Sni 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.sym b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.sym new file mode 100644 index 000000000..13e8af33d --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.sym @@ -0,0 +1,74 @@ +VERSION 5 +BEGIN SYMBOL fifo_xlnx_512x36_2clk +SYMBOLTYPE BLOCK +TIMESTAMP 2008 7 28 22 45 53 +SYMPIN 0 80 Input din[35:0] +SYMPIN 0 144 Input wr_en +SYMPIN 0 176 Input wr_clk +SYMPIN 0 240 Input rd_en +SYMPIN 0 272 Input rd_clk +SYMPIN 144 704 Input rst +SYMPIN 576 80 Output dout[35:0] +SYMPIN 576 208 Output full +SYMPIN 576 368 Output wr_data_count[8:0] +SYMPIN 576 432 Output empty +SYMPIN 576 592 Output rd_data_count[8:0] +BEGIN DISPLAY 32 32 TEXT fifo_xlnx_512x36_2clk + FONT 40 "Arial" +END DISPLAY +RECTANGLE N 32 32 544 672 +BEGIN LINE W 0 80 32 80 +END LINE +BEGIN DISPLAY 36 80 PIN din[35:0] ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 144 32 144 +BEGIN DISPLAY 36 144 PIN wr_en ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 176 32 176 +BEGIN DISPLAY 36 176 PIN wr_clk ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 240 32 240 +BEGIN DISPLAY 36 240 PIN rd_en ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 272 32 272 +BEGIN DISPLAY 36 272 PIN rd_clk ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 144 704 144 672 +BEGIN DISPLAY 144 668 PIN rst ATTR PinName + ALIGNMENT BCENTER + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 80 544 80 +END LINE +BEGIN DISPLAY 540 80 PIN dout[35:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +LINE N 576 208 544 208 +BEGIN DISPLAY 540 208 PIN full ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 368 544 368 +END LINE +BEGIN DISPLAY 540 368 PIN wr_data_count[8:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +LINE N 576 432 544 432 +BEGIN DISPLAY 540 432 PIN empty ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 592 544 592 +END LINE +BEGIN DISPLAY 540 592 PIN rd_data_count[8:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +END SYMBOL diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v new file mode 100644 index 000000000..905069743 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v @@ -0,0 +1,169 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_512x36_2clk.v when simulating +// the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_512x36_2clk( + din, + rd_clk, + rd_en, + rst, + wr_clk, + wr_en, + dout, + empty, + full, + rd_data_count, + wr_data_count); + + +input [35 : 0] din; +input rd_clk; +input rd_en; +input rst; +input wr_clk; +input wr_en; +output [35 : 0] dout; +output empty; +output full; +output [9 : 0] rd_data_count; +output [9 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V4_3 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(10), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x36"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(511), + .C_PROG_FULL_THRESH_NEGATE_VAL(510), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(10), + .C_RD_DEPTH(512), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(9), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(1), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(10), + .C_WR_DEPTH(512), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(9), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .DIN(din), + .RD_CLK(rd_clk), + .RD_EN(rd_en), + .RST(rst), + .WR_CLK(wr_clk), + .WR_EN(wr_en), + .DOUT(dout), + .EMPTY(empty), + .FULL(full), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .CLK(), + .INT_CLK(), + .BACKUP(), + .BACKUP_MARKER(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .RD_RST(), + .SRST(), + .WR_RST(), + .ALMOST_EMPTY(), + .ALMOST_FULL(), + .DATA_COUNT(), + .OVERFLOW(), + .PROG_EMPTY(), + .PROG_FULL(), + .VALID(), + .UNDERFLOW(), + .WR_ACK(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.veo new file mode 100644 index 000000000..6699ee73b --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.veo @@ -0,0 +1,53 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_512x36_2clk YourInstanceName ( + .din(din), // Bus [35 : 0] + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .wr_clk(wr_clk), + .wr_en(wr_en), + .dout(dout), // Bus [35 : 0] + .empty(empty), + .full(full), + .rd_data_count(rd_data_count), // Bus [9 : 0] + .wr_data_count(wr_data_count)); // Bus [9 : 0] + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_512x36_2clk.v when simulating +// the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd new file mode 100644 index 000000000..d9c2dd307 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd @@ -0,0 +1,156 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating +-- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY fifo_xlnx_512x36_2clk IS + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(8 downto 0); + wr_data_count: OUT std_logic_VECTOR(8 downto 0)); +END fifo_xlnx_512x36_2clk; + +ARCHITECTURE fifo_xlnx_512x36_2clk_a OF fifo_xlnx_512x36_2clk IS +-- synthesis translate_off +component wrapped_fifo_xlnx_512x36_2clk + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(8 downto 0); + wr_data_count: OUT std_logic_VECTOR(8 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_fifo_xlnx_512x36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral) + generic map( + c_has_int_clk => 0, + c_rd_freq => 1, + c_wr_response_latency => 1, + c_has_srst => 0, + c_has_rd_data_count => 1, + c_din_width => 36, + c_has_wr_data_count => 1, + c_full_flags_rst_val => 1, + c_implementation_type => 2, + c_family => "spartan3", + c_use_embedded_reg => 0, + c_has_wr_rst => 0, + c_wr_freq => 1, + c_use_dout_rst => 0, + c_underflow_low => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_preload_latency => 0, + c_dout_width => 36, + c_msgon_val => 1, + c_rd_depth => 512, + c_default_value => "BlankString", + c_mif_file_name => "BlankString", + c_has_underflow => 0, + c_has_rd_rst => 0, + c_has_almost_full => 0, + c_has_rst => 1, + c_data_count_width => 9, + c_has_wr_ack => 0, + c_use_ecc => 0, + c_wr_ack_low => 0, + c_common_clock => 0, + c_rd_pntr_width => 9, + c_use_fwft_data_count => 0, + c_has_almost_empty => 0, + c_rd_data_count_width => 9, + c_enable_rlocs => 0, + c_wr_pntr_width => 9, + c_overflow_low => 0, + c_prog_empty_type => 0, + c_optimization_mode => 0, + c_wr_data_count_width => 9, + c_preload_regs => 1, + c_dout_rst_val => "0", + c_has_data_count => 0, + c_prog_full_thresh_negate_val => 510, + c_wr_depth => 512, + c_prog_empty_thresh_negate_val => 5, + c_prog_empty_thresh_assert_val => 4, + c_has_valid => 0, + c_init_wr_pntr_val => 0, + c_prog_full_thresh_assert_val => 511, + c_use_fifo16_flags => 0, + c_has_backup => 0, + c_valid_low => 0, + c_prim_fifo_type => "512x36", + c_count_type => 0, + c_prog_full_type => 0, + c_memory_type => 1); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_fifo_xlnx_512x36_2clk + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full, + rd_data_count => rd_data_count, + wr_data_count => wr_data_count); +-- synthesis translate_on + +END fifo_xlnx_512x36_2clk_a; + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vho b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vho new file mode 100644 index 000000000..70eac27a5 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vho @@ -0,0 +1,76 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component fifo_xlnx_512x36_2clk + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(8 downto 0); + wr_data_count: OUT std_logic_VECTOR(8 downto 0)); +end component; + +-- Synplicity black box declaration +attribute syn_black_box : boolean; +attribute syn_black_box of fifo_xlnx_512x36_2clk: component is true; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : fifo_xlnx_512x36_2clk + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full, + rd_data_count => rd_data_count, + wr_data_count => wr_data_count); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating +-- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco new file mode 100644 index 000000000..5934ef285 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco @@ -0,0 +1,82 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Thu Sep 3 17:24:24 2009 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = True +SET vhdlsim = False +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.3 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_512x36_2clk +CSET data_count=false +CSET data_count_width=10 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=511 +CSET full_threshold_negate_value=510 +CSET input_data_width=36 +CSET input_depth=512 +CSET output_data_width=36 +CSET output_depth=512 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=10 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=10 +# END Parameters +GENERATE +# CRC: b7f2a9ba + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise new file mode 100644 index 000000000..fcf55f25a --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc new file mode 100644 index 000000000..d9277b0c3 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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+ + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt new file mode 100644 index 000000000..2f8d522f6 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt @@ -0,0 +1,12 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +fifo_generator_ug175.pdf +fifo_xlnx_512x36_2clk_18to36.gise +fifo_xlnx_512x36_2clk_18to36.ngc +fifo_xlnx_512x36_2clk_18to36.v +fifo_xlnx_512x36_2clk_18to36.veo +fifo_xlnx_512x36_2clk_18to36.xco +fifo_xlnx_512x36_2clk_18to36.xise +fifo_xlnx_512x36_2clk_18to36_flist.txt +fifo_xlnx_512x36_2clk_18to36_readme.txt +fifo_xlnx_512x36_2clk_18to36_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt new file mode 100644 index 000000000..03829e876 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt @@ -0,0 +1,47 @@ +The following files were generated for 'fifo_xlnx_512x36_2clk_18to36' in directory +/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ + +fifo_generator_ug175.pdf: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk_18to36.gise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_512x36_2clk_18to36.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_512x36_2clk_18to36.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_512x36_2clk_18to36.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_512x36_2clk_18to36.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_512x36_2clk_18to36.xise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_512x36_2clk_18to36_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_512x36_2clk_18to36_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + +fifo_xlnx_512x36_2clk_18to36_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl new file mode 100644 index 000000000..9b9b1f37a --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_512x36_2clk_18to36_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_512x36_2clk_18to36_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_18to36 +} +# ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_18to36 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise new file mode 100644 index 000000000..baed31484 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc new file mode 100644 index 000000000..00814f02e --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v new file mode 100644 index 000000000..b3d994ae8 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v @@ -0,0 +1,169 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_36to18.v when simulating +// the core, fifo_xlnx_512x36_2clk_36to18. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_512x36_2clk_36to18( + rst, + wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + empty); + + +input rst; +input wr_clk; +input rd_clk; +input [35 : 0] din; +input wr_en; +input rd_en; +output [17 : 0] dout; +output full; +output empty; + +// synthesis translate_off + + FIFO_GENERATOR_V6_1 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(9), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(18), + .C_ENABLE_RLOCS(0), + .C_ENABLE_RST_SYNC(1), + .C_ERROR_INJECTION_TYPE(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(0), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(0), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(0), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x36"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(509), + .C_PROG_FULL_THRESH_NEGATE_VAL(508), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(10), + .C_RD_DEPTH(1024), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(10), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(0), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(9), + .C_WR_DEPTH(512), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(9), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .RST(rst), + .WR_CLK(wr_clk), + .RD_CLK(rd_clk), + .DIN(din), + .WR_EN(wr_en), + .RD_EN(rd_en), + .DOUT(dout), + .FULL(full), + .EMPTY(empty), + .BACKUP(), + .BACKUP_MARKER(), + .CLK(), + .SRST(), + .WR_RST(), + .RD_RST(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .INT_CLK(), + .INJECTDBITERR(), + .INJECTSBITERR(), + .ALMOST_FULL(), + .WR_ACK(), + .OVERFLOW(), + .ALMOST_EMPTY(), + .VALID(), + .UNDERFLOW(), + .DATA_COUNT(), + .RD_DATA_COUNT(), + .WR_DATA_COUNT(), + .PROG_FULL(), + .PROG_EMPTY(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo new file mode 100644 index 000000000..e93be1591 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo @@ -0,0 +1,51 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_512x36_2clk_36to18 YourInstanceName ( + .rst(rst), + .wr_clk(wr_clk), + .rd_clk(rd_clk), + .din(din), // Bus [35 : 0] + .wr_en(wr_en), + .rd_en(rd_en), + .dout(dout), // Bus [17 : 0] + .full(full), + .empty(empty)); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_36to18.v when simulating +// the core, fifo_xlnx_512x36_2clk_36to18. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco new file mode 100644 index 000000000..d3115e7d5 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco @@ -0,0 +1,84 @@ +############################################################## +# +# Xilinx Core Generator version 12.1 +# Date: Thu Aug 12 21:06:13 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = false +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 6.1 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_512x36_2clk_36to18 +CSET data_count=false +CSET data_count_width=9 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET enable_reset_synchronization=true +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=0 +CSET full_threshold_assert_value=509 +CSET full_threshold_negate_value=508 +CSET inject_dbit_error=false +CSET inject_sbit_error=false +CSET input_data_width=36 +CSET input_depth=512 +CSET output_data_width=18 +CSET output_depth=1024 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=10 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=9 +# END Parameters +GENERATE +# CRC: a4e70980 diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise new file mode 100644 index 000000000..cfe983130 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise @@ -0,0 +1,72 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt new file mode 100644 index 000000000..54c85b15e --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt @@ -0,0 +1,12 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +fifo_generator_ug175.pdf +fifo_xlnx_512x36_2clk_36to18.gise +fifo_xlnx_512x36_2clk_36to18.ngc +fifo_xlnx_512x36_2clk_36to18.v +fifo_xlnx_512x36_2clk_36to18.veo +fifo_xlnx_512x36_2clk_36to18.xco +fifo_xlnx_512x36_2clk_36to18.xise +fifo_xlnx_512x36_2clk_36to18_flist.txt +fifo_xlnx_512x36_2clk_36to18_readme.txt +fifo_xlnx_512x36_2clk_36to18_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt new file mode 100644 index 000000000..3efc586bf --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt @@ -0,0 +1,47 @@ +The following files were generated for 'fifo_xlnx_512x36_2clk_36to18' in directory +/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ + +fifo_generator_ug175.pdf: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk_36to18.gise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_512x36_2clk_36to18.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_512x36_2clk_36to18.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_512x36_2clk_36to18.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_512x36_2clk_36to18.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_512x36_2clk_36to18.xise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_512x36_2clk_36to18_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_512x36_2clk_36to18_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + +fifo_xlnx_512x36_2clk_36to18_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl new file mode 100644 index 000000000..5161c1826 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_512x36_2clk_36to18_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_512x36_2clk_36to18_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_36to18 +} +# ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_36to18 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso new file mode 100644 index 000000000..f1a6f7899 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso @@ -0,0 +1,3 @@ +blkmemdp_v6_2 +blk_mem_gen_v2_6 +fifo_generator_v4_3 diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt new file mode 100644 index 000000000..d110a0158 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt @@ -0,0 +1,109 @@ + + + + + + +
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+ + + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt new file mode 100644 index 000000000..b0975be2d --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt @@ -0,0 +1,8 @@ +# Output products list for +fifo_xlnx_512x36_2clk.ngc +fifo_xlnx_512x36_2clk.v +fifo_xlnx_512x36_2clk.veo +fifo_xlnx_512x36_2clk.xco +fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_512x36_2clk_flist.txt +fifo_xlnx_512x36_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise new file mode 100644 index 000000000..c1717e9b5 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise @@ -0,0 +1,28 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc new file mode 100644 index 000000000..9cb73d5ce --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v new file mode 100644 index 000000000..6ec1e3f88 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v @@ -0,0 +1,173 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_prog_full.v when simulating +// the core, fifo_xlnx_512x36_2clk_prog_full. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_512x36_2clk_prog_full( + rst, + wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + almost_full, + empty, + prog_full); + + +input rst; +input wr_clk; +input rd_clk; +input [35 : 0] din; +input wr_en; +input rd_en; +output [35 : 0] dout; +output full; +output almost_full; +output empty; +output prog_full; + +// synthesis translate_off + + FIFO_GENERATOR_V6_1 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(9), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_ENABLE_RST_SYNC(1), + .C_ERROR_INJECTION_TYPE(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(1), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(0), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(0), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x36"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(500), + .C_PROG_FULL_THRESH_NEGATE_VAL(499), + .C_PROG_FULL_TYPE(1), + .C_RD_DATA_COUNT_WIDTH(9), + .C_RD_DEPTH(512), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(9), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(0), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(9), + .C_WR_DEPTH(512), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(9), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .RST(rst), + .WR_CLK(wr_clk), + .RD_CLK(rd_clk), + .DIN(din), + .WR_EN(wr_en), + .RD_EN(rd_en), + .DOUT(dout), + .FULL(full), + .ALMOST_FULL(almost_full), + .EMPTY(empty), + .PROG_FULL(prog_full), + .BACKUP(), + .BACKUP_MARKER(), + .CLK(), + .SRST(), + .WR_RST(), + .RD_RST(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .INT_CLK(), + .INJECTDBITERR(), + .INJECTSBITERR(), + .WR_ACK(), + .OVERFLOW(), + .ALMOST_EMPTY(), + .VALID(), + .UNDERFLOW(), + .DATA_COUNT(), + .RD_DATA_COUNT(), + .WR_DATA_COUNT(), + .PROG_EMPTY(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo new file mode 100644 index 000000000..64e6769d6 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo @@ -0,0 +1,53 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_512x36_2clk_prog_full YourInstanceName ( + .rst(rst), + .wr_clk(wr_clk), + .rd_clk(rd_clk), + .din(din), // Bus [35 : 0] + .wr_en(wr_en), + .rd_en(rd_en), + .dout(dout), // Bus [35 : 0] + .full(full), + .almost_full(almost_full), + .empty(empty), + .prog_full(prog_full)); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_prog_full.v when simulating +// the core, fifo_xlnx_512x36_2clk_prog_full. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco new file mode 100644 index 000000000..f99c3c6fb --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco @@ -0,0 +1,84 @@ +############################################################## +# +# Xilinx Core Generator version 12.2 +# Date: Thu Nov 11 17:27:10 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = false +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 6.1 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=true +CSET component_name=fifo_xlnx_512x36_2clk_prog_full +CSET data_count=false +CSET data_count_width=9 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET enable_reset_synchronization=true +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=500 +CSET full_threshold_negate_value=499 +CSET inject_dbit_error=false +CSET inject_sbit_error=false +CSET input_data_width=36 +CSET input_depth=512 +CSET output_data_width=36 +CSET output_depth=512 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=9 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=9 +# END Parameters +GENERATE +# CRC: 6b9f6232 diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise new file mode 100644 index 000000000..91dbf5819 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise @@ -0,0 +1,72 @@ + + + +

+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt new file mode 100644 index 000000000..2eb837a3f --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt @@ -0,0 +1,12 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +fifo_generator_ug175.pdf +fifo_xlnx_512x36_2clk_prog_full.gise +fifo_xlnx_512x36_2clk_prog_full.ngc +fifo_xlnx_512x36_2clk_prog_full.v +fifo_xlnx_512x36_2clk_prog_full.veo +fifo_xlnx_512x36_2clk_prog_full.xco +fifo_xlnx_512x36_2clk_prog_full.xise +fifo_xlnx_512x36_2clk_prog_full_flist.txt +fifo_xlnx_512x36_2clk_prog_full_readme.txt +fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt new file mode 100644 index 000000000..33d50a91d --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt @@ -0,0 +1,47 @@ +The following files were generated for 'fifo_xlnx_512x36_2clk_prog_full' in directory +/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ + +fifo_generator_ug175.pdf: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk_prog_full.gise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_512x36_2clk_prog_full.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_512x36_2clk_prog_full.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_512x36_2clk_prog_full.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_512x36_2clk_prog_full.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_512x36_2clk_prog_full.xise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_512x36_2clk_prog_full_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + +fifo_xlnx_512x36_2clk_prog_full_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl new file mode 100644 index 000000000..e1aecccff --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_512x36_2clk_prog_full_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_512x36_2clk_prog_full_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_prog_full +} +# ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_prog_full +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_readme.txt new file mode 100644 index 000000000..a250a74f5 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_readme.txt @@ -0,0 +1,39 @@ +The following files were generated for 'fifo_xlnx_512x36_2clk' in directory +/home/matt/gnuradio.git/usrp2/fpga/coregen/: + +fifo_xlnx_512x36_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_512x36_2clk.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_512x36_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_512x36_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +fifo_xlnx_512x36_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_512x36_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl new file mode 100644 index 000000000..8a0c0e3ff --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_512x36_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_512x36_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_512x36_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk +} +# ::fifo_xlnx_512x36_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_512x36_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.ngc new file mode 100644 index 000000000..e8c55a1af --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$4;14g<,[o}e~g`n;"2*413&;$>"9 > %10?*nhel%fmyz cnpfc`h(|dz$Sni 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\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v new file mode 100644 index 000000000..e84237689 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v @@ -0,0 +1,169 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_64x36_2clk.v when simulating +// the core, fifo_xlnx_64x36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_64x36_2clk( + din, + rd_clk, + rd_en, + rst, + wr_clk, + wr_en, + dout, + empty, + full, + rd_data_count, + wr_data_count); + + +input [35 : 0] din; +input rd_clk; +input rd_en; +input rst; +input wr_clk; +input wr_en; +output [35 : 0] dout; +output empty; +output full; +output [6 : 0] rd_data_count; +output [6 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V4_3 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(7), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(2), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x36"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(63), + .C_PROG_FULL_THRESH_NEGATE_VAL(62), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(7), + .C_RD_DEPTH(64), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(6), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(1), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(7), + .C_WR_DEPTH(64), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(6), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .DIN(din), + .RD_CLK(rd_clk), + .RD_EN(rd_en), + .RST(rst), + .WR_CLK(wr_clk), + .WR_EN(wr_en), + .DOUT(dout), + .EMPTY(empty), + .FULL(full), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .CLK(), + .INT_CLK(), + .BACKUP(), + .BACKUP_MARKER(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .RD_RST(), + .SRST(), + .WR_RST(), + .ALMOST_EMPTY(), + .ALMOST_FULL(), + .DATA_COUNT(), + .OVERFLOW(), + .PROG_EMPTY(), + .PROG_FULL(), + .VALID(), + .UNDERFLOW(), + .WR_ACK(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.veo new file mode 100644 index 000000000..9c761370c --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.veo @@ -0,0 +1,53 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_64x36_2clk YourInstanceName ( + .din(din), // Bus [35 : 0] + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .wr_clk(wr_clk), + .wr_en(wr_en), + .dout(dout), // Bus [35 : 0] + .empty(empty), + .full(full), + .rd_data_count(rd_data_count), // Bus [6 : 0] + .wr_data_count(wr_data_count)); // Bus [6 : 0] + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_64x36_2clk.v when simulating +// the core, fifo_xlnx_64x36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco new file mode 100644 index 000000000..c6e9aae27 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco @@ -0,0 +1,82 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Thu Sep 3 17:22:56 2009 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = True +SET vhdlsim = False +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.3 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_64x36_2clk +CSET data_count=false +CSET data_count_width=7 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Independent_Clocks_Distributed_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=63 +CSET full_threshold_negate_value=62 +CSET input_data_width=36 +CSET input_depth=64 +CSET output_data_width=36 +CSET output_depth=64 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=7 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=7 +# END Parameters +GENERATE +# CRC: 2bb925ae + diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso new file mode 100644 index 000000000..f1a6f7899 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso @@ -0,0 +1,3 @@ +blkmemdp_v6_2 +blk_mem_gen_v2_6 +fifo_generator_v4_3 diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt new file mode 100644 index 000000000..a23402f56 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt @@ -0,0 +1,104 @@ + + + + + + +
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+ + + diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_flist.txt new file mode 100644 index 000000000..44e31eb6c --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_flist.txt @@ -0,0 +1,8 @@ +# Output products list for +fifo_xlnx_64x36_2clk.ngc +fifo_xlnx_64x36_2clk.v +fifo_xlnx_64x36_2clk.veo +fifo_xlnx_64x36_2clk.xco +fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_64x36_2clk_flist.txt +fifo_xlnx_64x36_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_readme.txt new file mode 100644 index 000000000..7734c0087 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_readme.txt @@ -0,0 +1,39 @@ +The following files were generated for 'fifo_xlnx_64x36_2clk' in directory +/home/matt/gnuradio.git/usrp2/fpga/coregen/: + +fifo_xlnx_64x36_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_64x36_2clk.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_64x36_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_64x36_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: + Please see the core data sheet. + +fifo_xlnx_64x36_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +fifo_xlnx_64x36_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_64x36_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl new file mode 100644 index 000000000..ff5dfd3c2 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_64x36_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_64x36_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_64x36_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_64x36_2clk +} +# ::fifo_xlnx_64x36_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_64x36_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_64x36_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/pll_100_40_75.asy b/fpga/usrp2/coregen/pll_100_40_75.asy new file mode 100644 index 000000000..9cd1ec359 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 pll_100_40_75 +RECTANGLE Normal 32 32 576 1088 +LINE Normal 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName clk_in1 +PINATTR Polarity IN +LINE Normal 0 432 32 432 +PIN 0 432 LEFT 36 +PINATTR PinName reset +PINATTR Polarity IN +LINE Normal 608 80 576 80 +PIN 608 80 RIGHT 36 +PINATTR PinName clk_out1 +PINATTR Polarity OUT +LINE Normal 608 176 576 176 +PIN 608 176 RIGHT 36 +PINATTR PinName clk_out2 +PINATTR Polarity OUT +LINE Normal 608 272 576 272 +PIN 608 272 RIGHT 36 +PINATTR PinName clk_out3 +PINATTR Polarity OUT +LINE Normal 608 976 576 976 +PIN 608 976 RIGHT 36 +PINATTR PinName locked +PINATTR Polarity OUT + diff --git a/fpga/usrp2/coregen/pll_100_40_75.gise b/fpga/usrp2/coregen/pll_100_40_75.gise new file mode 100644 index 000000000..46f204815 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75.gise @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + diff --git a/fpga/usrp2/coregen/pll_100_40_75.ucf b/fpga/usrp2/coregen/pll_100_40_75.ucf new file mode 100755 index 000000000..d8590fabb --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75.ucf @@ -0,0 +1,71 @@ +# file: pll_100_40_75.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 25.000 ns HIGH 50% INPUT_JITTER 250.0ps; + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- +# NET "clk_int[1]" TNM_NET = "CLK_OUT1"; +# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 100.000 MHz; + +# NET "clk_int[2]" TNM_NET = "CLK_OUT2"; +# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 40.000 MHz; +# NET "clk_int[3]" TNM_NET = "CLK_OUT3"; +# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 75.000 MHz; + +# FALSE PATH constraints +PIN "RESET" TIG; + diff --git a/fpga/usrp2/coregen/pll_100_40_75.v b/fpga/usrp2/coregen/pll_100_40_75.v new file mode 100755 index 000000000..b400ece75 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75.v @@ -0,0 +1,158 @@ +// file: pll_100_40_75.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// "Output Output Phase Duty Pk-to-Pk Phase" +// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +//---------------------------------------------------------------------------- +// CLK_OUT1___100.000______0.000______50.0______252.791____220.216 +// CLK_OUT2____40.000______0.000______50.0______309.264____220.216 +// CLK_OUT3____75.000______0.000______50.0______269.846____220.216 +// +//---------------------------------------------------------------------------- +// "Input Clock Freq (MHz) Input Jitter (UI)" +//---------------------------------------------------------------------------- +// __primary__________40.000____________0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "pll_100_40_75,clk_wiz_v4_1,{component_name=pll_100_40_75,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=25.000,clkin2_period=25.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *) +module pll_100_40_75 + (// Clock in ports + input CLK_IN1, + // Clock out ports + output CLK_OUT1, + output CLK_OUT2, + output CLK_OUT3, + // Status and control signals + input RESET, + output LOCKED + ); + + // Input buffering + //------------------------------------ + IBUFG clkin1_buf + (.O (clkin1), + .I (CLK_IN1)); + + + // Clocking primitive + //------------------------------------ + // Instantiation of the PLL primitive + // * Unused inputs are tied off + // * Unused outputs are labeled unused + wire [15:0] do_unused; + wire drdy_unused; + wire clkfbout; + wire clkfbout_buf; + wire clkout3_unused; + wire clkout4_unused; + wire clkout5_unused; + + PLL_BASE + #(.BANDWIDTH ("OPTIMIZED"), + .CLK_FEEDBACK ("CLKFBOUT"), + .COMPENSATION ("SYSTEM_SYNCHRONOUS"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_MULT (15), + .CLKFBOUT_PHASE (0.000), + .CLKOUT0_DIVIDE (6), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT1_DIVIDE (15), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT2_DIVIDE (8), + .CLKOUT2_PHASE (0.000), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKIN_PERIOD (25.000), + .REF_JITTER (0.010)) + pll_base_inst + // Output clocks + (.CLKFBOUT (clkfbout), + .CLKOUT0 (clkout0), + .CLKOUT1 (clkout1), + .CLKOUT2 (clkout2), + .CLKOUT3 (clkout3_unused), + .CLKOUT4 (clkout4_unused), + .CLKOUT5 (clkout5_unused), + // Status and control signals + .LOCKED (LOCKED), + .RST (RESET), + // Input clock control + .CLKFBIN (clkfbout_buf), + .CLKIN (clkin1)); + + + // Output buffering + //----------------------------------- + BUFG clkf_buf + (.O (clkfbout_buf), + .I (clkfbout)); + + BUFG clkout1_buf + (.O (CLK_OUT1), + .I (clkout0)); + + + BUFG clkout2_buf + (.O (CLK_OUT2), + .I (clkout1)); + + BUFG clkout3_buf + (.O (CLK_OUT3), + .I (clkout2)); + + + +endmodule diff --git a/fpga/usrp2/coregen/pll_100_40_75.veo b/fpga/usrp2/coregen/pll_100_40_75.veo new file mode 100755 index 000000000..c6ebc5f5c --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75.veo @@ -0,0 +1,82 @@ +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// "Output Output Phase Duty Pk-to-Pk Phase" +// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +//---------------------------------------------------------------------------- +// CLK_OUT1___100.000______0.000______50.0______252.791____220.216 +// CLK_OUT2____40.000______0.000______50.0______309.264____220.216 +// CLK_OUT3____75.000______0.000______50.0______269.846____220.216 +// +//---------------------------------------------------------------------------- +// "Input Clock Freq (MHz) Input Jitter (UI)" +//---------------------------------------------------------------------------- +// __primary__________40.000____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + pll_100_40_75 instance_name + (// Clock in ports + .CLK_IN1(CLK_IN1), // IN + // Clock out ports + .CLK_OUT1(CLK_OUT1), // OUT + .CLK_OUT2(CLK_OUT2), // OUT + .CLK_OUT3(CLK_OUT3), // OUT + // Status and control signals + .RESET(RESET),// IN + .LOCKED(LOCKED)); // OUT +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/fpga/usrp2/coregen/pll_100_40_75.xco b/fpga/usrp2/coregen/pll_100_40_75.xco new file mode 100644 index 000000000..a3a0eb4fb --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75.xco @@ -0,0 +1,266 @@ +############################################################## +# +# Xilinx Core Generator version 14.1 +# Date: Mon Jun 25 01:21:52 2012 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:clk_wiz:3.5 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.5 +# END Select +# BEGIN Parameters +CSET calc_done=DONE +CSET clk_in_sel_port=CLK_IN_SEL +CSET clk_out1_port=CLK_OUT1 +CSET clk_out1_use_fine_ps_gui=false +CSET clk_out2_port=CLK_OUT2 +CSET clk_out2_use_fine_ps_gui=false +CSET clk_out3_port=CLK_OUT3 +CSET clk_out3_use_fine_ps_gui=false +CSET clk_out4_port=CLK_OUT4 +CSET clk_out4_use_fine_ps_gui=false +CSET clk_out5_port=CLK_OUT5 +CSET clk_out5_use_fine_ps_gui=false +CSET clk_out6_port=CLK_OUT6 +CSET clk_out6_use_fine_ps_gui=false +CSET clk_out7_port=CLK_OUT7 +CSET clk_out7_use_fine_ps_gui=false +CSET clk_valid_port=CLK_VALID +CSET clkfb_in_n_port=CLKFB_IN_N +CSET clkfb_in_p_port=CLKFB_IN_P +CSET clkfb_in_port=CLKFB_IN +CSET clkfb_in_signaling=SINGLE +CSET clkfb_out_n_port=CLKFB_OUT_N +CSET clkfb_out_p_port=CLKFB_OUT_P +CSET clkfb_out_port=CLKFB_OUT +CSET clkfb_stopped_port=CLKFB_STOPPED +CSET clkin1_jitter_ps=250.0 +CSET clkin1_ui_jitter=0.010 +CSET clkin2_jitter_ps=100.0 +CSET clkin2_ui_jitter=0.010 +CSET clkout1_drives=BUFG +CSET clkout1_requested_duty_cycle=50.0 +CSET clkout1_requested_out_freq=100.000 +CSET clkout1_requested_phase=0.000 +CSET clkout2_drives=BUFG +CSET clkout2_requested_duty_cycle=50.0 +CSET clkout2_requested_out_freq=40.000 +CSET clkout2_requested_phase=0.000 +CSET clkout2_used=true +CSET clkout3_drives=BUFG +CSET clkout3_requested_duty_cycle=50.0 +CSET clkout3_requested_out_freq=75.000 +CSET clkout3_requested_phase=0.000 +CSET clkout3_used=true +CSET clkout4_drives=BUFG +CSET clkout4_requested_duty_cycle=50.0 +CSET clkout4_requested_out_freq=75.000 +CSET clkout4_requested_phase=0.000 +CSET clkout4_used=false +CSET clkout5_drives=BUFG +CSET clkout5_requested_duty_cycle=50.0 +CSET clkout5_requested_out_freq=100.000 +CSET clkout5_requested_phase=0.000 +CSET clkout5_used=false +CSET clkout6_drives=BUFG +CSET clkout6_requested_duty_cycle=50.0 +CSET clkout6_requested_out_freq=100.000 +CSET clkout6_requested_phase=0.000 +CSET clkout6_used=false +CSET clkout7_drives=BUFG +CSET clkout7_requested_duty_cycle=50.0 +CSET clkout7_requested_out_freq=100.000 +CSET clkout7_requested_phase=0.000 +CSET clkout7_used=false +CSET clock_mgr_type=AUTO +CSET component_name=pll_100_40_75 +CSET daddr_port=DADDR +CSET dclk_port=DCLK +CSET dcm_clk_feedback=1X +CSET dcm_clk_out1_port=CLKFX +CSET dcm_clk_out2_port=CLK0 +CSET dcm_clk_out3_port=CLKFX +CSET dcm_clk_out4_port=CLKFX +CSET dcm_clk_out5_port=CLK0 +CSET dcm_clk_out6_port=CLK0 +CSET dcm_clkdv_divide=2.0 +CSET dcm_clkfx_divide=2 +CSET dcm_clkfx_multiply=5 +CSET dcm_clkgen_clk_out1_port=CLKFX +CSET dcm_clkgen_clk_out2_port=CLKFX +CSET dcm_clkgen_clk_out3_port=CLKFX +CSET dcm_clkgen_clkfx_divide=1 +CSET dcm_clkgen_clkfx_md_max=0.000 +CSET dcm_clkgen_clkfx_multiply=4 +CSET dcm_clkgen_clkfxdv_divide=2 +CSET dcm_clkgen_clkin_period=10.000 +CSET dcm_clkgen_notes=None +CSET dcm_clkgen_spread_spectrum=NONE +CSET dcm_clkgen_startup_wait=false +CSET dcm_clkin_divide_by_2=false +CSET dcm_clkin_period=25.000 +CSET dcm_clkout_phase_shift=NONE +CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS +CSET dcm_notes=None +CSET dcm_phase_shift=0 +CSET dcm_pll_cascade=NONE +CSET dcm_startup_wait=false +CSET den_port=DEN +CSET din_port=DIN +CSET dout_port=DOUT +CSET drdy_port=DRDY +CSET dwe_port=DWE +CSET feedback_source=FDBK_AUTO +CSET in_freq_units=Units_MHz +CSET in_jitter_units=Units_UI +CSET input_clk_stopped_port=INPUT_CLK_STOPPED +CSET jitter_options=UI +CSET jitter_sel=No_Jitter +CSET locked_port=LOCKED +CSET mmcm_bandwidth=OPTIMIZED +CSET mmcm_clkfbout_mult_f=4.000 +CSET mmcm_clkfbout_phase=0.000 +CSET mmcm_clkfbout_use_fine_ps=false +CSET mmcm_clkin1_period=10.000 +CSET mmcm_clkin2_period=10.000 +CSET mmcm_clkout0_divide_f=4.000 +CSET mmcm_clkout0_duty_cycle=0.500 +CSET mmcm_clkout0_phase=0.000 +CSET mmcm_clkout0_use_fine_ps=false +CSET mmcm_clkout1_divide=1 +CSET mmcm_clkout1_duty_cycle=0.500 +CSET mmcm_clkout1_phase=0.000 +CSET mmcm_clkout1_use_fine_ps=false +CSET mmcm_clkout2_divide=1 +CSET mmcm_clkout2_duty_cycle=0.500 +CSET mmcm_clkout2_phase=0.000 +CSET mmcm_clkout2_use_fine_ps=false +CSET mmcm_clkout3_divide=1 +CSET mmcm_clkout3_duty_cycle=0.500 +CSET mmcm_clkout3_phase=0.000 +CSET mmcm_clkout3_use_fine_ps=false +CSET mmcm_clkout4_cascade=false +CSET mmcm_clkout4_divide=1 +CSET mmcm_clkout4_duty_cycle=0.500 +CSET mmcm_clkout4_phase=0.000 +CSET mmcm_clkout4_use_fine_ps=false +CSET mmcm_clkout5_divide=1 +CSET mmcm_clkout5_duty_cycle=0.500 +CSET mmcm_clkout5_phase=0.000 +CSET mmcm_clkout5_use_fine_ps=false +CSET mmcm_clkout6_divide=1 +CSET mmcm_clkout6_duty_cycle=0.500 +CSET mmcm_clkout6_phase=0.000 +CSET mmcm_clkout6_use_fine_ps=false +CSET mmcm_clock_hold=false +CSET mmcm_compensation=ZHOLD +CSET mmcm_divclk_divide=1 +CSET mmcm_notes=None +CSET mmcm_ref_jitter1=0.010 +CSET mmcm_ref_jitter2=0.010 +CSET mmcm_startup_wait=false +CSET num_out_clks=3 +CSET override_dcm=false +CSET override_dcm_clkgen=false +CSET override_mmcm=false +CSET override_pll=false +CSET platform=lin +CSET pll_bandwidth=OPTIMIZED +CSET pll_clk_feedback=CLKFBOUT +CSET pll_clkfbout_mult=15 +CSET pll_clkfbout_phase=0.000 +CSET pll_clkin_period=25.000 +CSET pll_clkout0_divide=6 +CSET pll_clkout0_duty_cycle=0.500 +CSET pll_clkout0_phase=0.000 +CSET pll_clkout1_divide=15 +CSET pll_clkout1_duty_cycle=0.500 +CSET pll_clkout1_phase=0.000 +CSET pll_clkout2_divide=8 +CSET pll_clkout2_duty_cycle=0.500 +CSET pll_clkout2_phase=0.000 +CSET pll_clkout3_divide=8 +CSET pll_clkout3_duty_cycle=0.500 +CSET pll_clkout3_phase=0.000 +CSET pll_clkout4_divide=1 +CSET pll_clkout4_duty_cycle=0.500 +CSET pll_clkout4_phase=0.000 +CSET pll_clkout5_divide=1 +CSET pll_clkout5_duty_cycle=0.500 +CSET pll_clkout5_phase=0.000 +CSET pll_compensation=SYSTEM_SYNCHRONOUS +CSET pll_divclk_divide=1 +CSET pll_notes=None +CSET pll_ref_jitter=0.010 +CSET power_down_port=POWER_DOWN +CSET prim_in_freq=40.000 +CSET prim_in_jitter=0.010 +CSET prim_source=Single_ended_clock_capable_pin +CSET primary_port=CLK_IN1 +CSET primitive=MMCM +CSET primtype_sel=DCM_SP +CSET psclk_port=PSCLK +CSET psdone_port=PSDONE +CSET psen_port=PSEN +CSET psincdec_port=PSINCDEC +CSET relative_inclk=REL_PRIMARY +CSET reset_port=RESET +CSET secondary_in_freq=100.000 +CSET secondary_in_jitter=0.010 +CSET secondary_port=CLK_IN2 +CSET secondary_source=Single_ended_clock_capable_pin +CSET status_port=STATUS +CSET summary_strings=empty +CSET use_clk_valid=false +CSET use_clkfb_stopped=false +CSET use_dyn_phase_shift=false +CSET use_dyn_reconfig=false +CSET use_freeze=false +CSET use_freq_synth=true +CSET use_inclk_stopped=false +CSET use_inclk_switchover=false +CSET use_locked=true +CSET use_max_i_jitter=false +CSET use_min_o_jitter=false +CSET use_min_power=false +CSET use_phase_alignment=true +CSET use_power_down=false +CSET use_reset=true +CSET use_spread_spectrum=false +CSET use_status=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-12-28T09:11:49Z +# END Extra information +GENERATE +# CRC: e73fbe14 diff --git a/fpga/usrp2/coregen/pll_100_40_75.xdc b/fpga/usrp2/coregen/pll_100_40_75.xdc new file mode 100755 index 000000000..4cf03fee7 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75.xdc @@ -0,0 +1,67 @@ +# file: pll_100_40_75.xdc +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +create_clock -name CLK_IN1 -period 25.000 [get_ports CLK_IN1] +set_propagated_clock CLK_IN1 +set_input_jitter CLK_IN1 0.25 + +set_false_path -from [get_ports "RESET"] + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- + +#----------------------------------------------------------------- + +#----------------------------------------------------------------- diff --git a/fpga/usrp2/coregen/pll_100_40_75.xise b/fpga/usrp2/coregen/pll_100_40_75.xise new file mode 100644 index 000000000..55dbd6ddb --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75.xise @@ -0,0 +1,78 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp2/coregen/pll_100_40_75/clk_wiz_v3_5_readme.txt b/fpga/usrp2/coregen/pll_100_40_75/clk_wiz_v3_5_readme.txt new file mode 100644 index 000000000..4e06648c2 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/clk_wiz_v3_5_readme.txt @@ -0,0 +1,183 @@ + Core name: Xilinx LogiCORE Clocking Wizard + Version: 3.5 + Release: ISE 14.1 + Release Date: April 24, 2012 + + +================================================================================ + +This document contains the following sections: + +1. Introduction +2. New Features + 2.1 ISE +3. Supported Devices + 3.1 ISE +4. Resolved Issues + 4.1 ISE +5. Known Issues + 5.1 ISE +6. Technical Support +7. Core Release History +8. Legal Disclaimer + +================================================================================ + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.5 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ + +................................................................................ + +2. NEW FEATURES + + + 2.1 ISE + + - ISE 14.1 software support + +................................................................................ + +3. SUPPORTED DEVICES + + + 3.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + - NA + +................................................................................ + +5. KNOWN ISSUES + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +................................................................................ + +6. TECHNICAL SUPPORT + + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + diff --git a/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_gsg521.pdf b/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_gsg521.pdf new file mode 100644 index 000000000..998385638 Binary files /dev/null and b/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_gsg521.pdf differ diff --git a/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_readme.txt b/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_readme.txt new file mode 100644 index 000000000..4e06648c2 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_readme.txt @@ -0,0 +1,183 @@ + Core name: Xilinx LogiCORE Clocking Wizard + Version: 3.5 + Release: ISE 14.1 + Release Date: April 24, 2012 + + +================================================================================ + +This document contains the following sections: + +1. Introduction +2. New Features + 2.1 ISE +3. Supported Devices + 3.1 ISE +4. Resolved Issues + 4.1 ISE +5. Known Issues + 5.1 ISE +6. Technical Support +7. Core Release History +8. Legal Disclaimer + +================================================================================ + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.5 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ + +................................................................................ + +2. NEW FEATURES + + + 2.1 ISE + + - ISE 14.1 software support + +................................................................................ + +3. SUPPORTED DEVICES + + + 3.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + - NA + +................................................................................ + +5. KNOWN ISSUES + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +................................................................................ + +6. TECHNICAL SUPPORT + + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + diff --git a/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html b/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html new file mode 100644 index 000000000..8dc6bb6ba --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html @@ -0,0 +1,194 @@ + + +clk_wiz_v3_5_vinfo + + + +

+		Core name: Xilinx LogiCORE Clocking Wizard
+                Version: 3.5
+                Release: ISE 14.1
+                Release Date: April 24, 2012
+
+
+================================================================================
+
+This document contains the following sections:
+
+1. Introduction
+2. New Features
+  2.1 ISE
+3. Supported Devices
+  3.1 ISE
+4. Resolved Issues
+  4.1 ISE
+5. Known Issues
+  5.1 ISE
+6. Technical Support
+7. Core Release History
+8. Legal Disclaimer
+
+================================================================================
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.5
+solution. For the latest core updates, see the product page at:
+
+   www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
+
+................................................................................
+
+2. NEW FEATURES
+
+
+  2.1 ISE 
+  
+    - ISE 14.1 software support
+
+................................................................................
+
+3. SUPPORTED DEVICES
+
+
+  3.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+  - NA
+
+................................................................................
+
+5. KNOWN ISSUES 
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
+
+
+ + diff --git a/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.ucf b/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.ucf new file mode 100755 index 000000000..1892548b4 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.ucf @@ -0,0 +1,72 @@ +# file: pll_100_40_75_exdes.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 25.000 ns HIGH 50% INPUT_JITTER 250.0ps; + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- +# NET "clk_int[1]" TNM_NET = "CLK_OUT1"; +# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 100.000 MHz; + +# NET "clk_int[2]" TNM_NET = "CLK_OUT2"; +# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 40.000 MHz; +# NET "clk_int[3]" TNM_NET = "CLK_OUT3"; +# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 75.000 MHz; + +# FALSE PATH constraints +PIN "COUNTER_RESET" TIG; +PIN "RESET" TIG; + diff --git a/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.v b/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.v new file mode 100755 index 000000000..a79d6ab10 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.v @@ -0,0 +1,160 @@ +// file: pll_100_40_75_exdes.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard example design +//---------------------------------------------------------------------------- +// This example design instantiates the created clocking network, where each +// output clock drives a counter. The high bit of each counter is ported. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +module pll_100_40_75_exdes + #( + parameter TCQ = 100 + ) + (// Clock in ports + input CLK_IN1, + // Reset that only drives logic in example design + input COUNTER_RESET, + output [3:1] CLK_OUT, + // High bits of counters driven by clocks + output [3:1] COUNT, + // Status and control signals + input RESET, + output LOCKED + ); + + // Parameters for the counters + //------------------------------- + // Counter width + localparam C_W = 16; + // Number of counters + localparam NUM_C = 3; + genvar count_gen; + // When the clock goes out of lock, reset the counters + wire reset_int = !LOCKED || RESET || COUNTER_RESET; + + reg [NUM_C:1] rst_sync; + reg [NUM_C:1] rst_sync_int; + reg [NUM_C:1] rst_sync_int1; + reg [NUM_C:1] rst_sync_int2; + + + // Declare the clocks and counters + wire [NUM_C:1] clk_int; + wire [NUM_C:1] clk; + reg [C_W-1:0] counter [NUM_C:1]; + + // Instantiation of the clocking network + //-------------------------------------- + pll_100_40_75 clknetwork + (// Clock in ports + .CLK_IN1 (CLK_IN1), + // Clock out ports + .CLK_OUT1 (clk_int[1]), + .CLK_OUT2 (clk_int[2]), + .CLK_OUT3 (clk_int[3]), + // Status and control signals + .RESET (RESET), + .LOCKED (LOCKED)); + + assign CLK_OUT = clk_int; + + // Connect the output clocks to the design + //----------------------------------------- + assign clk[1] = clk_int[1]; + assign clk[2] = clk_int[2]; + assign clk[3] = clk_int[3]; + + + // Reset synchronizer + //----------------------------------- + generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1 + always @(posedge reset_int or posedge clk[count_gen]) begin + if (reset_int) begin + rst_sync[count_gen] <= 1'b1; + rst_sync_int[count_gen]<= 1'b1; + rst_sync_int1[count_gen]<= 1'b1; + rst_sync_int2[count_gen]<= 1'b1; + end + else begin + rst_sync[count_gen] <= 1'b0; + rst_sync_int[count_gen] <= rst_sync[count_gen]; + rst_sync_int1[count_gen] <= rst_sync_int[count_gen]; + rst_sync_int2[count_gen] <= rst_sync_int1[count_gen]; + end + end + end + endgenerate + + + // Output clock sampling + //----------------------------------- + generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters + + always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin + if (rst_sync_int2[count_gen]) begin + counter[count_gen] <= #TCQ { C_W { 1'b 0 } }; + end else begin + counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1; + end + end + // alias the high bit of each counter to the corresponding + // bit in the output bus + assign COUNT[count_gen] = counter[count_gen][C_W-1]; + end + endgenerate + + + + + +endmodule diff --git a/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.xdc b/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.xdc new file mode 100755 index 000000000..bd0f53e4e --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.xdc @@ -0,0 +1,69 @@ +# file: pll_100_40_75_exdes.xdc +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +create_clock -name CLK_IN1 -period 25.000 [get_ports CLK_IN1] +set_propagated_clock CLK_IN1 +set_input_jitter CLK_IN1 0.25 + +# FALSE PATH constraint added on COUNTER_RESET +set_false_path -from [get_ports "COUNTER_RESET"] +set_false_path -from [get_ports "RESET"] + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- + +#----------------------------------------------------------------- + +#----------------------------------------------------------------- diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/implement.bat b/fpga/usrp2/coregen/pll_100_40_75/implement/implement.bat new file mode 100755 index 000000000..a362117a4 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/implement/implement.bat @@ -0,0 +1,90 @@ +REM file: implement.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM ----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the clocking wizard +REM ----------------------------------------------------------------------------- + +REM Clean up the results directory +rmdir /S /Q results +mkdir results + +REM Copy unisim_comp.v file to results directory +copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\ + +REM Synthesize the Verilog Wrapper Files +echo 'Synthesizing Clocking Wizard design with XST' +xst -ifn xst.scr +move pll_100_40_75_exdes.ngc results\ + +REM Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\pll_100_40_75_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' +ngdbuild -uc pll_100_40_75_exdes.ucf pll_100_40_75_exdes + +echo 'Running map' +map -timing -pr b pll_100_40_75_exdes -o mapped.ncd + +echo 'Running par' +par -w mapped.ncd routed mapped.pcf + +echo 'Running trce' +trce -e 10 routed -o routed mapped.pcf + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level model for the clocking wizard example design' +netgen -ofmt verilog -sim -sdf_anno false -tm pll_100_40_75_exdes -w routed.ncd routed.v +cd .. + diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/implement.sh b/fpga/usrp2/coregen/pll_100_40_75/implement/implement.sh new file mode 100755 index 000000000..e3ff2ce97 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/implement/implement.sh @@ -0,0 +1,91 @@ +#!/bin/sh +# file: implement.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the clocking wizard +#----------------------------------------------------------------------------- + +# Clean up the results directory +rm -rf results +mkdir results + +# Copy unisim_comp.v file to results directory +cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/ + +# Synthesize the Verilog Wrapper Files +echo 'Synthesizing Clocking Wizard design with XST' +xst -ifn xst.scr +mv pll_100_40_75_exdes.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/pll_100_40_75_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' +ngdbuild -uc pll_100_40_75_exdes.ucf pll_100_40_75_exdes + +echo 'Running map' +map -timing pll_100_40_75_exdes -o mapped.ncd + +echo 'Running par' +par -w mapped.ncd routed mapped.pcf + +echo 'Running trce' +trce -e 10 routed -o routed mapped.pcf + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level model for the clocking wizard example design' +netgen -ofmt verilog -sim -sdf_anno false -tm pll_100_40_75_exdes -w routed.ncd routed.v + +cd .. diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.bat b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.bat new file mode 100755 index 000000000..8ac771810 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.bat @@ -0,0 +1,58 @@ +REM file: planAhead_ise.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the clocking wizard +REM----------------------------------------------------------------------------- + +del \f results +mkdir results +cd results + +planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.sh b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.sh new file mode 100755 index 000000000..6c8c837d3 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.sh @@ -0,0 +1,59 @@ +#!/bin/sh +# file: planAhead_ise.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the clocking wizard +#----------------------------------------------------------------------------- + +rm -rf results +mkdir results +cd results + +planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.tcl b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.tcl new file mode 100755 index 000000000..f4e6c57ae --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.tcl @@ -0,0 +1,78 @@ +# file: planAhead_ise.tcl +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +set projDir [file dirname [info script]] +set projName pll_100_40_75 +set topName pll_100_40_75_exdes +set device xc6slx75csg484-3 + +create_project $projName $projDir/results/$projName -part $device + +set_property design_mode RTL [get_filesets sources_1] + +## Source files +#set verilogSources [glob $srcDir/*.v] +import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/pll_100_40_75_exdes.v +import_files -fileset [get_filesets sources_1] -force -norecurse ../../../pll_100_40_75.v + + +#UCF file +import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/pll_100_40_75_exdes.ucf + +set_property top $topName [get_property srcset [current_run]] + +launch_runs -runs synth_1 +wait_on_run synth_1 + +set_property add_step Bitgen [get_runs impl_1] +launch_runs -runs impl_1 +wait_on_run impl_1 + + + diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.bat b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.bat new file mode 100755 index 000000000..42273f5d4 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.bat @@ -0,0 +1,58 @@ +REM file: planAhead_rdn.sh +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the XADC wizard +REM----------------------------------------------------------------------------- + +del \f results +mkdir results +cd results + +planAhead -mode batch -source ..\planAhead_rdn.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.sh b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.sh new file mode 100755 index 000000000..f4c14729e --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.sh @@ -0,0 +1,57 @@ +#!/bin/sh +# file: planAhead_rdn.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the XADC wizard +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +planAhead -mode batch -source ../planAhead_rdn.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.tcl b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.tcl new file mode 100755 index 000000000..56f9c65af --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.tcl @@ -0,0 +1,69 @@ +# file : planAhead_rdn.tcl +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +set device xc6slx75csg484-3 +set projName pll_100_40_75 +set design pll_100_40_75 +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module pll_100_40_75_exdes +set_property top pll_100_40_75_exdes [get_property srcset [current_run]] +add_files -norecurse {../../../pll_100_40_75.v} +add_files -norecurse {../../example_design/pll_100_40_75_exdes.v} +import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/pll_100_40_75_exdes.xdc} +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module pll_100_40_75_exdes -file routed.sdf +write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module pll_100_40_75_exdes -file routed.v +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/xst.prj b/fpga/usrp2/coregen/pll_100_40_75/implement/xst.prj new file mode 100755 index 000000000..8409c83dd --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/implement/xst.prj @@ -0,0 +1,2 @@ +verilog work ../../pll_100_40_75.v +verilog work ../example_design/pll_100_40_75_exdes.v diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/xst.scr b/fpga/usrp2/coregen/pll_100_40_75/implement/xst.scr new file mode 100755 index 000000000..af176e2e4 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/implement/xst.scr @@ -0,0 +1,9 @@ +run +-ifmt MIXED +-top pll_100_40_75_exdes +-p xc6slx75-csg484-3 +-ifn xst.prj +-ofn pll_100_40_75_exdes +-keep_hierarchy soft +-equivalent_register_removal no +-max_fanout 65535 diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simcmds.tcl b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simcmds.tcl new file mode 100755 index 000000000..6692a790e --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simcmds.tcl @@ -0,0 +1,8 @@ +# file: simcmds.tcl + +# create the simulation script +vcd dumpfile isim.vcd +vcd dumpvars -m /pll_100_40_75_tb -l 0 +wave add / +run 50000ns +quit diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.bat b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.bat new file mode 100755 index 000000000..783ddc0e3 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.bat @@ -0,0 +1,59 @@ +REM file: simulate_isim.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +vlogcomp -work work %XILINX%\verilog\src\glbl.v +vlogcomp -work work ..\..\..\pll_100_40_75.v +vlogcomp -work work ..\..\example_design\pll_100_40_75_exdes.v +vlogcomp -work work ..\pll_100_40_75_tb.v + +REM compile the project +fuse work.pll_100_40_75_tb work.glbl -L unisims_ver -o pll_100_40_75_isim.exe + +REM run the simulation script +.\pll_100_40_75_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.sh new file mode 100755 index 000000000..cb197ed97 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.sh @@ -0,0 +1,61 @@ +# file: simulate_isim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# lin +# create the project +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work ../../../pll_100_40_75.v +vlogcomp -work work ../../example_design/pll_100_40_75_exdes.v +vlogcomp -work work ../pll_100_40_75_tb.v + +# compile the project +fuse work.pll_100_40_75_tb work.glbl -L unisims_ver -o pll_100_40_75_isim.exe + +# run the simulation script +./pll_100_40_75_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.bat b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.bat new file mode 100755 index 000000000..756d94e7a --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.bat @@ -0,0 +1,61 @@ +REM file: simulate_mti.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM set up the working directory +vlib work + +REM compile all of the files +vlog -work work %XILINX%\verilog\src\glbl.v +vlog -work work ..\..\..\pll_100_40_75.v +vlog -work work ..\..\example_design\pll_100_40_75_exdes.v +vlog -work work ..\pll_100_40_75_tb.v + +REM run the simulation +vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.pll_100_40_75_tb work.glbl + diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.do b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.do new file mode 100755 index 000000000..c74e73aa5 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.do @@ -0,0 +1,65 @@ +# file: simulate_mti.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $env(XILINX)/verilog/src/glbl.v +vlog -work work ../../../pll_100_40_75.v +vlog -work work ../../example_design/pll_100_40_75_exdes.v +vlog -work work ../pll_100_40_75_tb.v + +# run the simulation +vsim -t ps -voptargs="+acc" -L unisims_ver work.pll_100_40_75_tb work.glbl +do wave.do +log pll_100_40_75_tb/dut/counter +log -r /* +run 50000ns diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.sh new file mode 100755 index 000000000..a49ca05c6 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.sh @@ -0,0 +1,61 @@ +#/bin/sh +# file: simulate_mti.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $XILINX/verilog/src/glbl.v +vlog -work work ../../../pll_100_40_75.v +vlog -work work ../../example_design/pll_100_40_75_exdes.v +vlog -work work ../pll_100_40_75_tb.v + +# run the simulation +vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.pll_100_40_75_tb work.glbl diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_ncsim.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_ncsim.sh new file mode 100755 index 000000000..5978c8eb7 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_ncsim.sh @@ -0,0 +1,62 @@ +#/bin/sh +# file: simulate_ncsim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +mkdir work + +# compile all of the files +ncvlog -work work ${XILINX}/verilog/src/glbl.v +ncvlog -work work ../../../pll_100_40_75.v +ncvlog -work work ../../example_design/pll_100_40_75_exdes.v +ncvlog -work work ../pll_100_40_75_tb.v + +# elaborate and run the simulation +ncelab -work work -access +wc work.pll_100_40_75_tb work.glbl +ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.pll_100_40_75_tb diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_vcs.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_vcs.sh new file mode 100755 index 000000000..bebd99d7d --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_vcs.sh @@ -0,0 +1,72 @@ +#!/bin/sh +# file: simulate_vcs.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# remove old files +rm -rf simv* csrc DVEfiles AN.DB + +# compile all of the files +# Note that -sverilog is not strictly required- You can +# remove the -sverilog if you change the type of the +# localparam for the periods in the testbench file to +# [63:0] from time +vlogan -sverilog \ + ${XILINX}/verilog/src/glbl.v \ + ../../../pll_100_40_75.v \ + ../../example_design/pll_100_40_75_exdes.v \ + ../pll_100_40_75_tb.v + +# prepare the simulation +vcs +vcs+lic+wait -debug pll_100_40_75_tb glbl + +# run the simulation +./simv -ucli -i ucli_commands.key + +# launch the viewer +dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/ucli_commands.key b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/ucli_commands.key new file mode 100755 index 000000000..b56d68a2d --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/ucli_commands.key @@ -0,0 +1,5 @@ +call {$vcdpluson} +call {$vcdplusmemon(pll_100_40_75_tb.dut.counter)} +run +call {$vcdplusclose} +quit diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/vcs_session.tcl b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/vcs_session.tcl new file mode 100755 index 000000000..19b1ea0f5 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/vcs_session.tcl @@ -0,0 +1,18 @@ +gui_open_window Wave +gui_sg_create pll_100_40_75_group +gui_list_add_group -id Wave.1 {pll_100_40_75_group} +gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.test_phase} +gui_set_radix -radix {ascii} -signals {pll_100_40_75_tb.test_phase} +gui_sg_addsignal -group pll_100_40_75_group {{Input_clocks}} -divider +gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.CLK_IN1} +gui_sg_addsignal -group pll_100_40_75_group {{Output_clocks}} -divider +gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.dut.clk} +gui_list_expand -id Wave.1 pll_100_40_75_tb.dut.clk +gui_sg_addsignal -group pll_100_40_75_group {{Status_control}} -divider +gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.RESET} +gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.LOCKED} +gui_sg_addsignal -group pll_100_40_75_group {{Counters}} -divider +gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.COUNT} +gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.dut.counter} +gui_list_expand -id Wave.1 pll_100_40_75_tb.dut.counter +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.do b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.do new file mode 100755 index 000000000..4178de1c7 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.do @@ -0,0 +1,60 @@ +# file: wave.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +add wave -noupdate -format Literal -radix ascii /pll_100_40_75_tb/test_phase +add wave -noupdate -divider {Input clocks} +add wave -noupdate -format Logic /pll_100_40_75_tb/CLK_IN1 +add wave -noupdate -divider {Output clocks} +add wave -noupdate -format Literal -expand /pll_100_40_75_tb/dut/clk +add wave -noupdate -divider Status/control +add wave -noupdate -format Logic /pll_100_40_75_tb/RESET +add wave -noupdate -format Logic /pll_100_40_75_tb/LOCKED +add wave -noupdate -divider Counters +add wave -noupdate -format Literal -radix hexadecimal /pll_100_40_75_tb/COUNT +add wave -noupdate -format Literal -radix hexadecimal -expand /pll_100_40_75_tb/dut/counter diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.sv b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.sv new file mode 100755 index 000000000..57e72bdec --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.sv @@ -0,0 +1,119 @@ +# file: wave.sv +# +# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# Get the windows set up +# +if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} { + window geometry "Design Browser 1" 1054x819+536+322 +} +window target "Design Browser 1" on +browser using {Design Browser 1} +browser set \ + -scope nc::pll_100_40_75_tb +browser yview see nc::pll_100_40_75_tb +browser timecontrol set -lock 0 + +if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} { + window geometry "Waveform 1" 1010x600+0+541 +} +window target "Waveform 1" on +waveform using {Waveform 1} +waveform sidebar visibility partial +waveform set \ + -primarycursor TimeA \ + -signalnames name \ + -signalwidth 175 \ + -units ns \ + -valuewidth 75 +cursor set -using TimeA -time 0 +waveform baseline set -time 0 +waveform xview limits 0 20000n + +# +# Define signal groups +# +catch {group new -name {Output clocks} -overlay 0} +catch {group new -name {Status/control} -overlay 0} +catch {group new -name {Counters} -overlay 0} + +set id [waveform add -signals [list {nc::pll_100_40_75_tb.CLK_IN1}]] + +group using {Output clocks} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {pll_100_40_75_tb.dut.clk[1]} \ + {pll_100_40_75_tb.dut.clk[2]} \ {pll_100_40_75_tb.dut.clk[3]} +group using {Counters} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {pll_100_40_75_tb.dut.counter[1]} \ + {pll_100_40_75_tb.dut.counter[2]} \ {pll_100_40_75_tb.dut.counter[3]} +group using {Status/control} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {nc::pll_100_40_75_tb.RESET} {nc::pll_100_40_75_tb.LOCKED} + + +set id [waveform add -signals [list {nc::pll_100_40_75_tb.COUNT} ]] + +set id [waveform add -signals [list {nc::pll_100_40_75_tb.test_phase} ]] +waveform format $id -radix %a + +set groupId [waveform add -groups {{Input clocks}}] +set groupId [waveform add -groups {{Output clocks}}] +set groupId [waveform add -groups {{Status/control}}] +set groupId [waveform add -groups {{Counters}}] diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/pll_100_40_75_tb.v b/fpga/usrp2/coregen/pll_100_40_75/simulation/pll_100_40_75_tb.v new file mode 100755 index 000000000..fe800f0cc --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/pll_100_40_75_tb.v @@ -0,0 +1,143 @@ +// file: pll_100_40_75_tb.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard demonstration testbench +//---------------------------------------------------------------------------- +// This demonstration testbench instantiates the example design for the +// clocking wizard. Input clocks are toggled, which cause the clocking +// network to lock and the counters to increment. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +`define wait_lock @(posedge LOCKED) + +module pll_100_40_75_tb (); + + // Clock to Q delay of 100ps + localparam TCQ = 100; + + + // timescale is 1ps/1ps + localparam ONE_NS = 1000; + localparam PHASE_ERR_MARGIN = 100; // 100ps + // how many cycles to run + localparam COUNT_PHASE = 1024; + // we'll be using the period in many locations + localparam time PER1 = 25.000*ONE_NS; + localparam time PER1_1 = PER1/2; + localparam time PER1_2 = PER1 - PER1/2; + + // Declare the input clock signals + reg CLK_IN1 = 1; + + // The high bits of the sampling counters + wire [3:1] COUNT; + // Status and control signals + reg RESET = 0; + wire LOCKED; + reg COUNTER_RESET = 0; +wire [3:1] CLK_OUT; +//Freq Check using the M & D values setting and actual Frequency generated + + + // Input clock generation + //------------------------------------ + always begin + CLK_IN1 = #PER1_1 ~CLK_IN1; + CLK_IN1 = #PER1_2 ~CLK_IN1; + end + + // Test sequence + reg [15*8-1:0] test_phase = ""; + initial begin + // Set up any display statements using time to be readable + $timeformat(-12, 2, "ps", 10); + COUNTER_RESET = 0; + test_phase = "reset"; + RESET = 1; + #(PER1*6); + RESET = 0; + test_phase = "wait lock"; + `wait_lock; + #(PER1*6); + COUNTER_RESET = 1; + #(PER1*20) + COUNTER_RESET = 0; + + test_phase = "counting"; + #(PER1*COUNT_PHASE); + + $display("SIMULATION PASSED"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + + // Instantiation of the example design containing the clock + // network and sampling counters + //--------------------------------------------------------- + pll_100_40_75_exdes + #( + .TCQ (TCQ) + ) dut + (// Clock in ports + .CLK_IN1 (CLK_IN1), + // Reset for logic in example design + .COUNTER_RESET (COUNTER_RESET), + .CLK_OUT (CLK_OUT), + // High bits of the counters + .COUNT (COUNT), + // Status and control signals + .RESET (RESET), + .LOCKED (LOCKED)); + +// Freq Check + +endmodule diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/pll_100_40_75_tb.v b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/pll_100_40_75_tb.v new file mode 100755 index 000000000..0e6be6e9d --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/pll_100_40_75_tb.v @@ -0,0 +1,157 @@ +// file: pll_100_40_75_tb.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard demonstration testbench +//---------------------------------------------------------------------------- +// This demonstration testbench instantiates the example design for the +// clocking wizard. Input clocks are toggled, which cause the clocking +// network to lock and the counters to increment. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +`define wait_lock @(posedge LOCKED) + +module pll_100_40_75_tb (); + + // Clock to Q delay of 100ps + localparam TCQ = 100; + + + // timescale is 1ps/1ps + localparam ONE_NS = 1000; + localparam PHASE_ERR_MARGIN = 100; // 100ps + // how many cycles to run + localparam COUNT_PHASE = 1024; + // we'll be using the period in many locations + localparam time PER1 = 25.000*ONE_NS; + localparam time PER1_1 = PER1/2; + localparam time PER1_2 = PER1 - PER1/2; + + // Declare the input clock signals + reg CLK_IN1 = 1; + + // The high bits of the sampling counters + wire [3:1] COUNT; + // Status and control signals + reg RESET = 0; + wire LOCKED; + reg COUNTER_RESET = 0; +wire [3:1] CLK_OUT; +//Freq Check using the M & D values setting and actual Frequency generated + + reg [13:0] timeout_counter = 14'b00000000000000; + + // Input clock generation + //------------------------------------ + always begin + CLK_IN1 = #PER1_1 ~CLK_IN1; + CLK_IN1 = #PER1_2 ~CLK_IN1; + end + + // Test sequence + reg [15*8-1:0] test_phase = ""; + initial begin + // Set up any display statements using time to be readable + $timeformat(-12, 2, "ps", 10); + $display ("Timing checks are not valid"); + COUNTER_RESET = 0; + test_phase = "reset"; + RESET = 1; + #(PER1*6); + RESET = 0; + test_phase = "wait lock"; + `wait_lock; + #(PER1*6); + COUNTER_RESET = 1; + #(PER1*19.5) + COUNTER_RESET = 0; + #(PER1*1) + $display ("Timing checks are valid"); + test_phase = "counting"; + #(PER1*COUNT_PHASE); + + $display("SIMULATION PASSED"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + + + always@(posedge CLK_IN1) begin + timeout_counter <= timeout_counter + 1'b1; + if (timeout_counter == 14'b10000000000000) begin + if (LOCKED != 1'b1) begin + $display("ERROR : NO LOCK signal"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + end + end + + // Instantiation of the example design containing the clock + // network and sampling counters + //--------------------------------------------------------- + pll_100_40_75_exdes + dut + (// Clock in ports + .CLK_IN1 (CLK_IN1), + // Reset for logic in example design + .COUNTER_RESET (COUNTER_RESET), + .CLK_OUT (CLK_OUT), + // High bits of the counters + .COUNT (COUNT), + // Status and control signals + .RESET (RESET), + .LOCKED (LOCKED)); + + +// Freq Check + +endmodule diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/sdf_cmd_file b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/sdf_cmd_file new file mode 100755 index 000000000..61dacfed8 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/sdf_cmd_file @@ -0,0 +1,2 @@ +COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X", +SCOPE = pll_100_40_75_tb.dut; diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simcmds.tcl b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simcmds.tcl new file mode 100755 index 000000000..857329884 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simcmds.tcl @@ -0,0 +1,9 @@ +# file: simcmds.tcl + +# create the simulation script +vcd dumpfile isim.vcd +vcd dumpvars -m /pll_100_40_75_tb -l 0 +wave add / +run 50000ns +quit + diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_isim.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_isim.sh new file mode 100755 index 000000000..e3b06d7c5 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_isim.sh @@ -0,0 +1,62 @@ +# file: simulate_isim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# create the project +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work ../../implement/results/routed.v +vlogcomp -work work pll_100_40_75_tb.v + +# compile the project +fuse work.pll_100_40_75_tb work.glbl -L secureip -L simprims_ver -o pll_100_40_75_isim.exe + +# run the simulation script +./pll_100_40_75_isim.exe -tclbatch simcmds.tcl -sdfmax /pll_100_40_75_tb/dut=../../implement/results/routed.sdf + +# run the simulation script +#./pll_100_40_75_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.bat b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.bat new file mode 100755 index 000000000..7e5890086 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.bat @@ -0,0 +1,59 @@ +REM file: simulate_mti.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM +# set up the working directory +set work work +vlib work + +REM compile all of the files +vlog -work work %XILINX%\verilog\src\glbl.v +vlog -work work ..\..\implement\results\routed.v +vlog -work work pll_100_40_75_tb.v + +REM run the simulation +vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax pll_100_40_75_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.pll_100_40_75_tb work.glbl diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.do b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.do new file mode 100755 index 000000000..03f8a3965 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.do @@ -0,0 +1,65 @@ +# file: simulate_mti.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $env(XILINX)/verilog/src/glbl.v +vlog -work work ../../implement/results/routed.v +vlog -work work pll_100_40_75_tb.v + +# run the simulation +vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax pll_100_40_75_tb/dut=../../implement/results/routed.sdf +no_notifier work.pll_100_40_75_tb work.glbl +#do wave.do +#log -r /* +run 50000ns + + diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.sh new file mode 100755 index 000000000..055768aa8 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.sh @@ -0,0 +1,61 @@ +#/bin/sh +# file: simulate_mti.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $XILINX/verilog/src/glbl.v +vlog -work work ../../implement/results/routed.v +vlog -work work pll_100_40_75_tb.v + +# run the simulation +vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax pll_100_40_75_tb/dut=../../implement/results/routed.sdf +no_notifier work.pll_100_40_75_tb work.glbl diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_ncsim.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_ncsim.sh new file mode 100755 index 000000000..aa3a2b441 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_ncsim.sh @@ -0,0 +1,64 @@ +#!/bin/sh +# file: simulate_ncsim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +mkdir work + +# compile all of the files +ncvlog -work work ${XILINX}/verilog/src/glbl.v +ncvlog -work work ../../implement/results/routed.v +ncvlog -work work pll_100_40_75_tb.v + +# elaborate and run the simulation +ncsdfc ../../implement/results/routed.sdf + +ncelab -work work -access +wc -pulse_r 10 -nonotifier work.pll_100_40_75_tb work.glbl -sdf_cmd_file sdf_cmd_file +ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.pll_100_40_75_tb + diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_vcs.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_vcs.sh new file mode 100755 index 000000000..3cc21dd69 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_vcs.sh @@ -0,0 +1,72 @@ +#!/bin/sh +# file: simulate_vcs.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# remove old files +rm -rf simv* csrc DVEfiles AN.DB + +# compile all of the files +# Note that -sverilog is not strictly required- You can +# remove the -sverilog if you change the type of the +# localparam for the periods in the testbench file to +# [63:0] from time + vlogan -sverilog \ + pll_100_40_75_tb.v \ + ../../implement/results/routed.v + + +# prepare the simulation +vcs -sdf max:pll_100_40_75_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \ + +libext+.v -debug pll_100_40_75_tb.v ../../implement/results/routed.v + +# run the simulation +./simv -ucli -i ucli_commands.key + +# launch the viewer +#dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/ucli_commands.key b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/ucli_commands.key new file mode 100755 index 000000000..0548d1733 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/ucli_commands.key @@ -0,0 +1,5 @@ + +call {$vcdpluson} +run 50000ns +call {$vcdplusclose} +quit diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/vcs_session.tcl b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/vcs_session.tcl new file mode 100755 index 000000000..1438f6bed --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/vcs_session.tcl @@ -0,0 +1 @@ +gui_open_window Wave diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/wave.do b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/wave.do new file mode 100755 index 000000000..fe9b59354 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/wave.do @@ -0,0 +1,72 @@ +# file: wave.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /pll_100_40_75_tb/CLK_IN1 +add wave -noupdate /pll_100_40_75_tb/COUNT +add wave -noupdate /pll_100_40_75_tb/LOCKED +add wave -noupdate /pll_100_40_75_tb/RESET +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {3223025 ps} 0} +configure wave -namecolwidth 238 +configure wave -valuecolwidth 107 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {74848022 ps} diff --git a/fpga/usrp2/coregen/pll_100_40_75_exdes.ncf b/fpga/usrp2/coregen/pll_100_40_75_exdes.ncf new file mode 100644 index 000000000..ddff6a6e9 --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75_exdes.ncf @@ -0,0 +1,73 @@ +# file: pll_100_40_75_exdes.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 25.000 ns HIGH 50% INPUT_JITTER 250.0ps; + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- +# NET "clk_int[1]" TNM_NET = "CLK_OUT1"; +# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 100.000 MHz; + +# NET "clk_int[2]" TNM_NET = "CLK_OUT2"; +# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 40.000 MHz; +# NET "clk_int[3]" TNM_NET = "CLK_OUT3"; +# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 75.000 MHz; + +# FALSE PATH constraints +PIN "COUNTER_RESET" TIG; +PIN "RESET" TIG; + + diff --git a/fpga/usrp2/coregen/pll_100_40_75_flist.txt b/fpga/usrp2/coregen/pll_100_40_75_flist.txt new file mode 100644 index 000000000..04c7f882d --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75_flist.txt @@ -0,0 +1,54 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +pll_100_40_75/clk_wiz_v3_5_readme.txt +pll_100_40_75/doc/clk_wiz_gsg521.pdf +pll_100_40_75/doc/clk_wiz_v3_5_readme.txt +pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html +pll_100_40_75/example_design/pll_100_40_75_exdes.ucf +pll_100_40_75/example_design/pll_100_40_75_exdes.v +pll_100_40_75/example_design/pll_100_40_75_exdes.xdc +pll_100_40_75/implement/implement.bat +pll_100_40_75/implement/implement.sh +pll_100_40_75/implement/planAhead_ise.bat +pll_100_40_75/implement/planAhead_ise.sh +pll_100_40_75/implement/planAhead_ise.tcl +pll_100_40_75/implement/planAhead_rdn.bat +pll_100_40_75/implement/planAhead_rdn.sh +pll_100_40_75/implement/planAhead_rdn.tcl +pll_100_40_75/implement/xst.prj +pll_100_40_75/implement/xst.scr +pll_100_40_75/simulation/functional/simcmds.tcl +pll_100_40_75/simulation/functional/simulate_isim.bat +pll_100_40_75/simulation/functional/simulate_isim.sh +pll_100_40_75/simulation/functional/simulate_mti.bat +pll_100_40_75/simulation/functional/simulate_mti.do +pll_100_40_75/simulation/functional/simulate_mti.sh +pll_100_40_75/simulation/functional/simulate_ncsim.sh +pll_100_40_75/simulation/functional/simulate_vcs.sh +pll_100_40_75/simulation/functional/ucli_commands.key +pll_100_40_75/simulation/functional/vcs_session.tcl +pll_100_40_75/simulation/functional/wave.do +pll_100_40_75/simulation/functional/wave.sv +pll_100_40_75/simulation/pll_100_40_75_tb.v +pll_100_40_75/simulation/timing/pll_100_40_75_tb.v +pll_100_40_75/simulation/timing/sdf_cmd_file +pll_100_40_75/simulation/timing/simcmds.tcl +pll_100_40_75/simulation/timing/simulate_isim.sh +pll_100_40_75/simulation/timing/simulate_mti.bat +pll_100_40_75/simulation/timing/simulate_mti.do +pll_100_40_75/simulation/timing/simulate_mti.sh +pll_100_40_75/simulation/timing/simulate_ncsim.sh +pll_100_40_75/simulation/timing/simulate_vcs.sh +pll_100_40_75/simulation/timing/ucli_commands.key +pll_100_40_75/simulation/timing/vcs_session.tcl +pll_100_40_75/simulation/timing/wave.do +pll_100_40_75.asy +pll_100_40_75.gise +pll_100_40_75.ucf +pll_100_40_75.v +pll_100_40_75.veo +pll_100_40_75.xco +pll_100_40_75.xdc +pll_100_40_75.xise +pll_100_40_75_flist.txt +pll_100_40_75_xmdf.tcl diff --git a/fpga/usrp2/coregen/pll_100_40_75_xmdf.tcl b/fpga/usrp2/coregen/pll_100_40_75_xmdf.tcl new file mode 100755 index 000000000..18eee6e1a --- /dev/null +++ b/fpga/usrp2/coregen/pll_100_40_75_xmdf.tcl @@ -0,0 +1,144 @@ +# The package naming convention is _xmdf +package provide pll_100_40_75_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::pll_100_40_75_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::pll_100_40_75_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name pll_100_40_75 +} +# ::pll_100_40_75_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::pll_100_40_75_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/clk_wiz_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/example_design/pll_100_40_75_exdes.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/doc/clk_wiz_ds709.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/doc/clk_wiz_gsg521.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/example_design/pll_100_40_75_exdes.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/pll_100_40_75_tb.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simcmds.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/wave.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/wave.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.ejp +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module pll_100_40_75 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams -- cgit v1.2.3