From 05d77f772317de5d925301aa11bb9a880656dd05 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Thu, 15 Apr 2010 11:24:24 -0700
Subject: moved usrp1 and usrp2 fpga dirs into fpga subdirectory

---
 fpga/usrp2/control_lib/wb_ram_block.v | 36 +++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 fpga/usrp2/control_lib/wb_ram_block.v

(limited to 'fpga/usrp2/control_lib/wb_ram_block.v')

diff --git a/fpga/usrp2/control_lib/wb_ram_block.v b/fpga/usrp2/control_lib/wb_ram_block.v
new file mode 100644
index 000000000..044d34ca4
--- /dev/null
+++ b/fpga/usrp2/control_lib/wb_ram_block.v
@@ -0,0 +1,36 @@
+
+
+// Since this is a block ram, there are no byte-selects and there is a 1-cycle read latency
+//   These have to be a multiple of 512 lines (2K) long
+
+module wb_ram_block
+  #(parameter AWIDTH=9)
+    (input clk_i,
+     input stb_i,
+     input we_i,
+     input [AWIDTH-1:0] adr_i,
+     input [31:0] dat_i,
+     output reg [31:0] dat_o,
+     output ack_o);
+
+   reg [31:0] distram [0:1<<(AWIDTH-1)];
+
+   always @(posedge clk_i)
+     begin
+	if(stb_i & we_i)
+	  distram[adr_i] <= dat_i;
+	dat_o <= distram[adr_i];
+     end
+
+   reg stb_d1, ack_d1;
+   always @(posedge clk_i)
+     stb_d1 <= stb_i;
+   
+   always @(posedge clk_i)
+     ack_d1 <= ack_o;
+   
+   assign ack_o = stb_i & (we_i | (stb_d1 & ~ack_d1));
+endmodule // wb_ram_block
+
+
+    
-- 
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