From 05d77f772317de5d925301aa11bb9a880656dd05 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Thu, 15 Apr 2010 11:24:24 -0700
Subject: moved usrp1 and usrp2 fpga dirs into fpga subdirectory

---
 fpga/usrp2/control_lib/system_control_tb.v | 57 ++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)
 create mode 100644 fpga/usrp2/control_lib/system_control_tb.v

(limited to 'fpga/usrp2/control_lib/system_control_tb.v')

diff --git a/fpga/usrp2/control_lib/system_control_tb.v b/fpga/usrp2/control_lib/system_control_tb.v
new file mode 100644
index 000000000..a8eff4811
--- /dev/null
+++ b/fpga/usrp2/control_lib/system_control_tb.v
@@ -0,0 +1,57 @@
+
+
+module system_control_tb();
+   
+   reg 	aux_clk, clk_fpga;
+   wire wb_clk, dsp_clk;
+   wire wb_rst, dsp_rst, rl_rst, proc_rst;
+
+   reg 	rl_done, clock_ready;
+   
+   initial aux_clk = 1'b0;
+   always #25 aux_clk = ~aux_clk;
+
+   initial clk_fpga = 1'b0;
+
+   initial clock_ready = 1'b0;
+   initial
+     begin
+	@(negedge proc_rst);
+	#1003 clock_ready <= 1'b1;
+     end
+
+   always #7 clk_fpga = ~clk_fpga;
+      
+   initial begin
+      $dumpfile("system_control_tb.vcd");
+      $dumpvars(0,system_control_tb);
+   end
+
+   initial #10000 $finish;
+
+   initial
+     begin
+	@(negedge rl_rst);
+	rl_done <= 1'b0;
+	#1325 rl_done <= 1'b1;
+     end
+
+   initial
+     begin
+	@(negedge proc_rst);
+	clock_ready <= 1'b0;
+	#327 clock_ready <= 1'b1;
+     end
+     
+   system_control 
+     system_control(.aux_clk_i(aux_clk),.clk_fpga_i(clk_fpga),
+		    .dsp_clk_o(dsp_clk),.wb_clk_o(wb_clk),
+		    .ram_loader_rst_o(rl_rst),
+		    .processor_rst_o(proc_rst),
+		    .wb_rst_o(wb_rst),
+		    .dsp_rst_o(dsp_rst),
+		    .ram_loader_done_i(rl_done),
+		    .clock_ready_i(clock_ready),
+		    .debug_o());
+   
+endmodule // system_control_tb
-- 
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