From fd3e84941de463fa1a7ebab0a69515b4bf2614cd Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Tue, 7 Oct 2014 11:25:20 +0200 Subject: Removed copy of FPGA source files. --- fpga/usrp2/control_lib/clock_control_tb.v | 52 ------------------------------- 1 file changed, 52 deletions(-) delete mode 100644 fpga/usrp2/control_lib/clock_control_tb.v (limited to 'fpga/usrp2/control_lib/clock_control_tb.v') diff --git a/fpga/usrp2/control_lib/clock_control_tb.v b/fpga/usrp2/control_lib/clock_control_tb.v deleted file mode 100644 index 9760efbe3..000000000 --- a/fpga/usrp2/control_lib/clock_control_tb.v +++ /dev/null @@ -1,52 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module clock_control_tb(); - - clock_control clock_control - (.reset(reset), - .aux_clk(aux_clk), - .clk_fpga(clk_fpga), - .clk_en(clk_en), - .clk_sel(clk_sel), - .clk_func(clk_func), - .clk_status(clk_status), - - .sen(sen), - .sclk(sclk), - .sdi(sdi), - .sdo(sdo) - ); - - reg reset, aux_clk; - - wire [1:0] clk_sel, clk_en; - - initial reset = 1'b1; - initial #1000 reset = 1'b0; - - initial aux_clk = 1'b0; - always #10 aux_clk = ~aux_clk; - - initial $dumpfile("clock_control_tb.vcd"); - initial $dumpvars(0,clock_control_tb); - - initial #10000 $finish; - -endmodule // clock_control_tb -- cgit v1.2.3