From 05d77f772317de5d925301aa11bb9a880656dd05 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Thu, 15 Apr 2010 11:24:24 -0700
Subject: moved usrp1 and usrp2 fpga dirs into fpga subdirectory

---
 fpga/usrp2/control_lib/clock_control_tb.v | 35 +++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 fpga/usrp2/control_lib/clock_control_tb.v

(limited to 'fpga/usrp2/control_lib/clock_control_tb.v')

diff --git a/fpga/usrp2/control_lib/clock_control_tb.v b/fpga/usrp2/control_lib/clock_control_tb.v
new file mode 100644
index 000000000..4e705cf23
--- /dev/null
+++ b/fpga/usrp2/control_lib/clock_control_tb.v
@@ -0,0 +1,35 @@
+
+
+module clock_control_tb();
+   
+  clock_control clock_control
+    (.reset(reset),
+     .aux_clk(aux_clk),  
+     .clk_fpga(clk_fpga),
+     .clk_en(clk_en),    
+     .clk_sel(clk_sel),  
+     .clk_func(clk_func), 
+     .clk_status(clk_status),
+     
+     .sen(sen),   
+     .sclk(sclk), 
+     .sdi(sdi),
+     .sdo(sdo)
+     );
+
+   reg reset, aux_clk;
+   
+   wire [1:0] clk_sel, clk_en;
+   
+   initial reset = 1'b1;
+   initial #1000 reset = 1'b0;
+   
+   initial aux_clk = 1'b0;
+   always #10 aux_clk = ~aux_clk;
+   
+   initial $dumpfile("clock_control_tb.vcd");
+   initial $dumpvars(0,clock_control_tb);
+   
+   initial #10000 $finish;
+   
+endmodule // clock_control_tb
-- 
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