From bafa9d95453387814ef25e6b6256ba8db2df612f Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Thu, 23 Jan 2020 16:10:22 -0800 Subject: Merge FPGA repository back into UHD repository MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams Co-authored-by: Andrej Rode Co-authored-by: Ashish Chaudhari Co-authored-by: Ben Hilburn Co-authored-by: Ciro Nishiguchi Co-authored-by: Daniel Jepson Co-authored-by: Derek Kozel Co-authored-by: EJ Kreinar Co-authored-by: Humberto Jimenez Co-authored-by: Ian Buckley Co-authored-by: Jörg Hofrichter Co-authored-by: Jon Kiser Co-authored-by: Josh Blum Co-authored-by: Jonathon Pendlum Co-authored-by: Martin Braun Co-authored-by: Matt Ettus Co-authored-by: Michael West Co-authored-by: Moritz Fischer Co-authored-by: Nick Foster Co-authored-by: Nicolas Cuervo Co-authored-by: Paul Butler Co-authored-by: Paul David Co-authored-by: Ryan Marlow Co-authored-by: Sugandha Gupta Co-authored-by: Sylvain Munaut Co-authored-by: Trung Tran Co-authored-by: Vidush Vishwanath Co-authored-by: Wade Fife --- fpga/usrp2/boot_cpld/boot_cpld.v | 95 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) create mode 100755 fpga/usrp2/boot_cpld/boot_cpld.v (limited to 'fpga/usrp2/boot_cpld/boot_cpld.v') diff --git a/fpga/usrp2/boot_cpld/boot_cpld.v b/fpga/usrp2/boot_cpld/boot_cpld.v new file mode 100755 index 000000000..2ffc6daed --- /dev/null +++ b/fpga/usrp2/boot_cpld/boot_cpld.v @@ -0,0 +1,95 @@ +`timescale 1ns / 1ps +// //////////////////////////////////////////////////////////////////////////////// +// Boot CPLD design, only for u2_rev2 +// //////////////////////////////////////////////////////////////////////////////// + +module boot_cpld + (input CLK_25MHZ, + output CLK_25MHZ_EN, + output [2:0] LED, + output [8:0] DEBUG, + input POR, + + // To SD Card + output SD_nCS, + output SD_Din, + output SD_CLK, + input SD_Dout, + input SD_DAT1, // Unused + input SD_DAT2, // Unused + input SD_prot, // Write Protect + input SD_det, // Card Detect + + // To FPGA Config Interface + input CFG_INIT_B, + output CFG_Din, // Also used in Data interface + output CFG_CCLK, + input CFG_DONE, + output CFG_PROG_B, + + // To FPGA data interface + output CPLD_CLK, + input START, + input MODE, + input DONE, + output detached, + input CPLD_misc // Unused for now + ); + + assign CLK_25MHZ_EN = 1'b1; + + assign LED[0] = ~CFG_DONE; + assign LED[1] = CFG_INIT_B; + assign LED[2] = ~CFG_PROG_B; + + wire en_outs; + wire [3:0] set_sel = 4'd0; + + assign CPLD_CLK = CFG_CCLK; + assign DEBUG[8:0] = { CLK_25MHZ, SD_nCS, SD_CLK, SD_Din, SD_Dout, + START, MODE, DONE, CPLD_misc}; + + // Handle cutover to FPGA control of SD + wire fpga_takeover = ~CPLD_misc; + wire SD_CLK_int, SD_nCS_int, SD_Din_int, CFG_Din_int; + + assign SD_CLK = fpga_takeover ? START : SD_CLK_int; + assign SD_nCS = fpga_takeover ? MODE : SD_nCS_int; + assign SD_Din = fpga_takeover ? DONE : SD_Din_int; + assign CFG_Din = fpga_takeover ? SD_Dout : CFG_Din_int; + + spi_boot #(.width_set_sel_g(4), // How many sets (16) + .width_bit_cnt_g(6), // Block length (12 is faster, 6 is minimum) + .width_img_cnt_g(2), // How many images per set + .num_bits_per_img_g(20), // Image size, 20 = 1MB + .sd_init_g(1), // SD-specific initialization + .mmc_compat_clk_div_g(0),// No MMC support + .width_mmc_clk_div_g(0), // No MMC support + .reset_level_g(0)) // Active low reset + + spi_boot(.clk_i(CLK_25MHZ), + .reset_i(POR), + + // To SD Card + .spi_clk_o(SD_CLK_int), + .spi_cs_n_o(SD_nCS_int), + .spi_data_in_i(SD_Dout), + .spi_data_out_o(SD_Din_int), + .spi_en_outs_o(en_outs), + + // Data Port + .start_i(START), + .mode_i(MODE), // 0->conf mode, 1->data mode + .detached_o(detached), + .dat_done_i(DONE), + .set_sel_i(set_sel), + + // To FPGA + .config_n_o(CFG_PROG_B), + .cfg_init_n_i(CFG_INIT_B), + .cfg_done_i(CFG_DONE), + .cfg_clk_o(CFG_CCLK), + .cfg_dat_o(CFG_Din_int) + ); + +endmodule // boot_cpld -- cgit v1.2.3