From 05d77f772317de5d925301aa11bb9a880656dd05 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 15 Apr 2010 11:24:24 -0700 Subject: moved usrp1 and usrp2 fpga dirs into fpga subdirectory --- fpga/usrp1/sdr_lib/rx_dcoffset.v | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 fpga/usrp1/sdr_lib/rx_dcoffset.v (limited to 'fpga/usrp1/sdr_lib/rx_dcoffset.v') diff --git a/fpga/usrp1/sdr_lib/rx_dcoffset.v b/fpga/usrp1/sdr_lib/rx_dcoffset.v new file mode 100644 index 000000000..3be475ed6 --- /dev/null +++ b/fpga/usrp1/sdr_lib/rx_dcoffset.v @@ -0,0 +1,22 @@ + + +module rx_dcoffset (input clock, input enable, input reset, + input signed [15:0] adc_in, output signed [15:0] adc_out, + input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe); + parameter MYADDR = 0; + + reg signed [31:0] integrator; + wire signed [15:0] scaled_integrator = integrator[31:16] + (integrator[31] & |integrator[15:0]); + assign adc_out = adc_in - scaled_integrator; + + // FIXME do we need signed? + //FIXME What do we do when clipping? + always @(posedge clock) + if(reset) + integrator <= #1 32'd0; + else if(serial_strobe & (MYADDR == serial_addr)) + integrator <= #1 {serial_data[15:0],16'd0}; + else if(enable) + integrator <= #1 integrator + adc_out; + +endmodule // rx_dcoffset -- cgit v1.2.3