From 05d77f772317de5d925301aa11bb9a880656dd05 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 15 Apr 2010 11:24:24 -0700 Subject: moved usrp1 and usrp2 fpga dirs into fpga subdirectory --- fpga/usrp1/megacells/accum32_bb.v | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100755 fpga/usrp1/megacells/accum32_bb.v (limited to 'fpga/usrp1/megacells/accum32_bb.v') diff --git a/fpga/usrp1/megacells/accum32_bb.v b/fpga/usrp1/megacells/accum32_bb.v new file mode 100755 index 000000000..142bde88c --- /dev/null +++ b/fpga/usrp1/megacells/accum32_bb.v @@ -0,0 +1,35 @@ +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module accum32 ( + data, + clock, + clken, + aclr, + result)/* synthesis synthesis_clearbox = 1 */; + + input [31:0] data; + input clock; + input clken; + input aclr; + output [31:0] result; + +endmodule + -- cgit v1.2.3