From 4dc2b7010c0f3e41758b8192636ef7672caae0f7 Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Wed, 9 Jun 2021 10:09:22 -0500 Subject: fpga: tools: Add ip target to simulation makefiles Allow building of just the IP by running "make ip" in simulation directories. --- fpga/docs/usrp3/sim/running_testbenches.md | 1 + 1 file changed, 1 insertion(+) (limited to 'fpga/docs/usrp3/sim') diff --git a/fpga/docs/usrp3/sim/running_testbenches.md b/fpga/docs/usrp3/sim/running_testbenches.md index 2b56af86d..136834bc6 100644 --- a/fpga/docs/usrp3/sim/running_testbenches.md +++ b/fpga/docs/usrp3/sim/running_testbenches.md @@ -15,6 +15,7 @@ all supported simulator targets. Currently, the following targets will work: ipclean: Cleanup all IP intermediate files clean: Cleanup all simulator intermediate files cleanall: Cleanup everything! + ip: Generate the IP required for this simulation xsim: Run the simulation using the Xilinx Vivado Simulator xclean: Cleanup Xilinx Vivado Simulator intermediate files vsim: Run the simulation using ModelSim simulator via Vivado -- cgit v1.2.3