From bafa9d95453387814ef25e6b6256ba8db2df612f Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Thu, 23 Jan 2020 16:10:22 -0800 Subject: Merge FPGA repository back into UHD repository MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams Co-authored-by: Andrej Rode Co-authored-by: Ashish Chaudhari Co-authored-by: Ben Hilburn Co-authored-by: Ciro Nishiguchi Co-authored-by: Daniel Jepson Co-authored-by: Derek Kozel Co-authored-by: EJ Kreinar Co-authored-by: Humberto Jimenez Co-authored-by: Ian Buckley Co-authored-by: Jörg Hofrichter Co-authored-by: Jon Kiser Co-authored-by: Josh Blum Co-authored-by: Jonathon Pendlum Co-authored-by: Martin Braun Co-authored-by: Matt Ettus Co-authored-by: Michael West Co-authored-by: Moritz Fischer Co-authored-by: Nick Foster Co-authored-by: Nicolas Cuervo Co-authored-by: Paul Butler Co-authored-by: Paul David Co-authored-by: Ryan Marlow Co-authored-by: Sugandha Gupta Co-authored-by: Sylvain Munaut Co-authored-by: Trung Tran Co-authored-by: Vidush Vishwanath Co-authored-by: Wade Fife --- fpga/docs/usrp2/build_instructions.md | 55 +++++++++++++++++++++++++++++++ fpga/docs/usrp2/customize_signal_chain.md | 49 +++++++++++++++++++++++++++ 2 files changed, 104 insertions(+) create mode 100644 fpga/docs/usrp2/build_instructions.md create mode 100644 fpga/docs/usrp2/customize_signal_chain.md (limited to 'fpga/docs/usrp2') diff --git a/fpga/docs/usrp2/build_instructions.md b/fpga/docs/usrp2/build_instructions.md new file mode 100644 index 000000000..07c096d45 --- /dev/null +++ b/fpga/docs/usrp2/build_instructions.md @@ -0,0 +1,55 @@ +# Generation 2 USRP Build Documentation + +## Dependencies and Requirements + +### Dependencies + +The USRP FPGA build system requires a UNIX-like environment with the following dependencies + +- [Xilinx ISE 12.2](http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools/v12_2.html) +- [GNU Make](https://www.gnu.org/software/make/) +- (Recommended) [GNU Bash](https://www.gnu.org/software/bash/) + +The N200 will work with the WebPack version of ISE. + +### Requirements + +- [Xilinx ISE Platform Requirements](http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/irn.pdf) + +### What FPGA does my USRP have? + +- USRP N200: Spartan® 3A-DSP 1800 +- USRP N210: Spartan® 3A-DSP 3400 + +## Build Instructions + +- Download and install [Xilinx ISE 12.2](http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools/v12_2.html) + +- To add xtclsh to the PATH and to setup up the Xilinx build environment run + + `source /Xilinx/12.2/ISE_DS/settings64.sh` (64-bit platform) + + `source /Xilinx/12.2/ISE_DS/settings32.sh` (32-bit platform) + +- Navigate to `usrp2/top/{project}` where project is: + + N2x0: For USRP N200 and USRP N210 + +- To build a binary configuration bitstream run `make ` + where the target is specific to each product. To get a list of supported targets run + `make help`. + +- The build output will be specific to the product and will be located in the + `usrp2/top/{project}/build` directory. Run `make help` for more information. + +### N2x0 Targets and Outputs + +#### Supported Targets +- N200R3: Builds the USRP N200 Rev 3 design. +- N200R4: Builds the USRP N200 Rev 4 design. +- N210R3: Builds the USRP N210 Rev 3 design. +- N210R4: Builds the USRP N210 Rev 4 design. + +#### Outputs +- `build-/u2plus.bit` : Configuration bitstream with header +- `build-/u2plus.bin` : Configuration bitstream without header +- `build-/u2plus.syr` : Xilinx system report +- `build-/u2plus.twr` : Xilinx timing report + diff --git a/fpga/docs/usrp2/customize_signal_chain.md b/fpga/docs/usrp2/customize_signal_chain.md new file mode 100644 index 000000000..dfd28b3cc --- /dev/null +++ b/fpga/docs/usrp2/customize_signal_chain.md @@ -0,0 +1,49 @@ +# Customizing the Signal Chain in Generation 2 products + +## Adding DSP logic to Generation 2 products + +As part of the USRP FPGA build-framework, there are several convenient places +for users to insert custom DSP modules into the transmit and receive chains. + +- Before the DDC module +- After the DDC module +- Replace the DDC module +- Before the DUC module +- After the DUC module +- Replace the DUC module +- As an RX packet engine +- As an TX packet engine + +### Customizing the top level makefile + +Each USRP device has a makefile associated with it. This makefile contains all +of the necessary build rules. When making a customized FPGA design, start by +copying the current makefile for your device. Makefiles can be found in +`usrp2/top/{product}/Makefile` + +Edit your new makefile: +- Set BUILD_DIR to a unique directory name +- Set CUSTOM_SRCS for your verilog sources +- Set CUSTOM_DEFS (see section below) + +### Inserting custom modules + +CUSTOM_DEFS is a string of space-separate key-value pairs. Set the CUSTOM_DEFS +variable so the FPGA fabric glue will substitute your custom modules into the +DSP chain. + +Example: + + CUSTOM_DEFS = "TX_ENG0_MODULE=my_tx_engine RX_ENG0_MODULE=my_rx_engine" + +Where `my_tx_engine` and `my_rx_engine` are the names of custom verilog modules. + +The following module definition keys are possible (X is a DSP number): + +- `TX_ENG_MODULE`: Set the module for the transmit chain engine. +- `RX_ENG_MODULE`: Set the module for the receive chain engine. +- `RX_DSP_MODULE`: Set the module for the transmit dsp chain. +- `TX_DSP_MODULE`: Set the module for the receive dsp chain. + +Examples of custom modules can be found in the Verilog files in `usrp2/custom/`. + -- cgit v1.2.3