From 26372c19a9ae32956954b4ed72bddc58f54c9c18 Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Wed, 26 Jan 2022 12:13:59 -0600 Subject: fpga: ci: Increase PR pipeline timeout --- fpga/.ci/x4xx-pr-check.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'fpga/.ci') diff --git a/fpga/.ci/x4xx-pr-check.yml b/fpga/.ci/x4xx-pr-check.yml index 3de9f674d..c1a26edf9 100644 --- a/fpga/.ci/x4xx-pr-check.yml +++ b/fpga/.ci/x4xx-pr-check.yml @@ -36,7 +36,7 @@ jobs: target: X410_XG_100 debug: true # to be able to debug any failed attempts clean: false # for speedup of PR testing - timeout: 360 + timeout: 480 # ------------------------------------------------------------------- # Build X4 FPGA (200 MHz) @@ -46,7 +46,7 @@ jobs: target: X410_X4_200 debug: true # to be able to debug any failed attempts clean: false # for speedup of PR testing - timeout: 360 + timeout: 480 # ------------------------------------------------------------------- # Build C1 FPGA (400 MHz) @@ -56,7 +56,7 @@ jobs: target: X410_C1_400 debug: true # to be able to debug any failed attempts clean: false # for speedup of PR testing - timeout: 360 + timeout: 480 # ------------------------------------------------------------------- # Make CPLD -- cgit v1.2.3