From 232a9a7345f0264602caba0caf2b96dd0856aed6 Mon Sep 17 00:00:00 2001 From: Humberto Jimenez Date: Mon, 21 Feb 2022 16:40:40 -0600 Subject: fpga: ci: Add stages-based pipeline --- fpga/.ci/templates/job-run-testbenches.yml | 40 ++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 fpga/.ci/templates/job-run-testbenches.yml (limited to 'fpga/.ci/templates/job-run-testbenches.yml') diff --git a/fpga/.ci/templates/job-run-testbenches.yml b/fpga/.ci/templates/job-run-testbenches.yml new file mode 100644 index 000000000..6f6ef142b --- /dev/null +++ b/fpga/.ci/templates/job-run-testbenches.yml @@ -0,0 +1,40 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# Description: +# +# This template is used to run all the testbenches using ModelSim. +# + + +jobs: +- job: + displayName: "ModelSim Simulation" + timeoutInMinutes: 360 + pool: + name: Hardware + variables: + - group: sdr-pipeline-vars + steps: + - checkout: self + clean: true + persistCredentials: true + + - checkout: hwtools + clean: true + path: s/hwtools/head + persistCredentials: true + + - bash: | + source $(Build.SourcesDirectory)/uhddev/fpga/.ci/scripts/run_setup.sh ./top/x300 + + echo "---- Run testbenches ----" + pushd ./tools/utils + python3 ./run_testbenches.py --logged --simulator modelsim --excludes=modelsim.excludes -j2 run + popd + workingDirectory: uhddev/fpga/usrp3 + env: + PATCHES_PATH: $(sdr-vivado-patches) + displayName: "Run Testbenches" -- cgit v1.2.3