From d5109ae99e5da24707a8d7a6d57b96f6deabbede Mon Sep 17 00:00:00 2001 From: Ashish Chaudhari Date: Tue, 20 Feb 2018 11:42:56 -0800 Subject: rfnoc,x300: Multiple clocking changes - Moved bus_clk <=> ce_clk crossing to axi_wrapper in FPGA which resulted in a noc_shell compat bump - Change x300 bus_clk frequency to 187.5 MHz --- firmware/usrp3/x300/x300_aurora_bist.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'firmware/usrp3/x300/x300_aurora_bist.py') diff --git a/firmware/usrp3/x300/x300_aurora_bist.py b/firmware/usrp3/x300/x300_aurora_bist.py index 5f7a22a3b..962494b46 100755 --- a/firmware/usrp3/x300/x300_aurora_bist.py +++ b/firmware/usrp3/x300/x300_aurora_bist.py @@ -61,7 +61,7 @@ MAC_CTRL_PHY_RESET = 0x00000200 MAC_CTRL_BIST_RATE_MSK = 0x000001F8 MAC_CTRL_BIST_RATE_OFFSET = 3 -BUS_CLK_RATE = 166.66e6 +BUS_CLK_RATE = 187.50e6 BIST_MAX_TIME_LIMIT = math.floor(pow(2,48)/BUS_CLK_RATE)-1 ######################################################################## -- cgit v1.2.3