From f39c4538a3ca25c79f6b793ee0b6448051dcd751 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Thu, 29 Jul 2010 10:12:45 -0700 Subject: Clock bugs, LED order. Figured out cold-start problem with Matt's help -- the DCM wasn't being reset. This also explains why USRP2 didn't like it when clocks_mimo_config was omitted -- it was sneakily resetting the DCM while enabling/disabling ref outputs. Also re-did USRP2P LED order and genericized the LED settings so LED_D is LED_D for both USRP2 and USRP2P. --- firmware/microblaze/usrp2p/memory_map.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'firmware/microblaze/usrp2p/memory_map.h') diff --git a/firmware/microblaze/usrp2p/memory_map.h b/firmware/microblaze/usrp2p/memory_map.h index fc0094e67..9c5b576d7 100644 --- a/firmware/microblaze/usrp2p/memory_map.h +++ b/firmware/microblaze/usrp2p/memory_map.h @@ -402,6 +402,10 @@ typedef struct { volatile uint32_t led_src; // HW or SW control for LEDs } output_regs_t; +#define CLK_RESET (1<<4) +#define CLK_ENABLE (1<<3) | (1<<2) +#define CLK_SEL (1<<1) | (1<<0) + #define SERDES_ENABLE 8 #define SERDES_PRBSEN 4 #define SERDES_LOOPEN 2 @@ -412,13 +416,13 @@ typedef struct { // crazy order that matches the labels on the case -#define LED_A (1 << 4) -#define LED_B (1 << 1) -#define LED_C (1 << 3) -#define LED_D (1 << 0) -#define LED_E (1 << 2) +#define LED_A (1 << 2) +#define LED_B (1 << 5) +#define LED_E (1 << 3) +#define LED_D (1 << 1) +#define LED_C (1 << 4) // LED_F // controlled by CPLD -#define LED_RJ45 (1 << 5) +#define LED_RJ45 (1 << 0) #define output_regs ((output_regs_t *) MISC_OUTPUT_BASE) -- cgit v1.2.3