From f72ad02f5ec370f45995ecd2b3e8b322e9a7e4dc Mon Sep 17 00:00:00 2001
From: Nick Foster <nick@nerdnetworks.org>
Date: Mon, 26 Jul 2010 15:33:30 -0700
Subject: New branch with firmware dir from USRP2P branch.

---
 firmware/microblaze/usrp2p/memory_map.h | 838 ++++++++++++++++++++++++++++++++
 1 file changed, 838 insertions(+)
 create mode 100644 firmware/microblaze/usrp2p/memory_map.h

(limited to 'firmware/microblaze/usrp2p/memory_map.h')

diff --git a/firmware/microblaze/usrp2p/memory_map.h b/firmware/microblaze/usrp2p/memory_map.h
new file mode 100644
index 000000000..fc0094e67
--- /dev/null
+++ b/firmware/microblaze/usrp2p/memory_map.h
@@ -0,0 +1,838 @@
+/* -*- c -*- */
+/*
+ * Copyright 2007,2008,2009 Free Software Foundation, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Overall Memory Map
+ *   0000-FFFF  64K    RAM space
+ *
+ *   0000-1FFF  8K     Boot RAM
+ *   2000-5FFF  16K    Buffer pool
+ *   6000-7FFF  8K     Peripherals
+ *   8000-FFFF  32K    Main System RAM
+
+
+From u2plus_core.v:
+wb_1master #(.decode_w(8),
+.s0_addr(8'b0000_0000),.s0_mask(8'b1110_0000),  // 0-8K, Boot RAM
+.s1_addr(8'b0100_0000),.s1_mask(8'b1100_0000),  // 16K-32K, Buffer Pool
+.s2_addr(8'b0011_0000),.s2_mask(8'b1111_1111),  // SPI 0x3000
+.s3_addr(8'b0011_0001),.s3_mask(8'b1111_1111),  // I2C 0x3100
+.s4_addr(8'b0011_0010),.s4_mask(8'b1111_1111),  // GPIO 0x3200
+.s5_addr(8'b0011_0011),.s5_mask(8'b1111_1111),  // Readback 0x3300
+.s6_addr(8'b0011_0100),.s6_mask(8'b1111_1111),  // Ethernet MAC 0x3400
+.s7_addr(8'b0010_0000),.s7_mask(8'b1111_0000),  // 8-12K, Settings Bus (only uses 1K) 0x2000-0x2FFF
+.s8_addr(8'b0011_0101),.s8_mask(8'b1111_1111),  // PIC 0x3500
+.s9_addr(8'b0011_0110),.s9_mask(8'b1111_1111),  // Unused 0x3600
+.sa_addr(8'b0011_0111),.sa_mask(8'b1111_1111),  // UART 0x3700
+.sb_addr(8'b0011_1000),.sb_mask(8'b1111_1111),  // ATR 0x3800
+.sc_addr(8'b0011_1001),.sc_mask(8'b1111_1111),  // Unused 0x3900
+.sd_addr(8'b0011_1010),.sd_mask(8'b1111_1111),  // ICAP 0x3A00
+.se_addr(8'b0011_1011),.se_mask(8'b1111_1111),  // SPI Flash 0x3B00
+.sf_addr(8'b1000_0000),.sf_mask(8'b1000_0000),  // 32-64K, Main RAM 0x8000-0xFFFF
+               .dw(dw),.aw(aw),.sw(sw)) wb_1master
+
+ */
+
+
+#ifndef INCLUDED_MEMORY_MAP_H
+#define INCLUDED_MEMORY_MAP_H
+
+#include <stdint.h>
+
+
+#define MASTER_CLK_RATE        100000000		// 100 MHz
+
+
+////////////////////////////////////////////////////////////////
+//
+//         Memory map for embedded wishbone bus
+//
+////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////
+// Boot RAM, Slave 0
+
+#define BOOTRAM_BASE 0x0000
+
+
+////////////////////////////////////////////////////////////////
+// Buffer Pool RAM, Slave 1
+//
+// The buffers themselves are located in Slave 1, Buffer Pool RAM.
+// The status registers are in Slave 5, Buffer Pool Status.
+// The control register is in Slave 7, Settings Bus.
+
+#define BUFFER_POOL_RAM_BASE 0x4000
+
+#define	NBUFFERS                8
+#define BP_NLINES	   0x0200	// number of 32-bit lines in a buffer
+#define BP_LAST_LINE	(BP_NLINES - 1)	// last line in a buffer
+
+#define buffer_pool_ram \
+  ((uint32_t *) BUFFER_POOL_RAM_BASE)
+
+#define buffer_ram(n) (&buffer_pool_ram[(n) * BP_NLINES])
+
+
+/////////////////////////////////////////////////////
+// SPI Core, Slave 2.  See core docs for more info
+#define SPI_BASE 0x3000   // Base address (16-bit) is base peripheral addr
+
+typedef struct {
+  volatile uint32_t	txrx0;
+  volatile uint32_t	txrx1;
+  volatile uint32_t	txrx2;
+  volatile uint32_t	txrx3;
+  volatile uint32_t	ctrl;
+  volatile uint32_t	div;
+  volatile uint32_t	ss;
+} spi_regs_t;
+
+#define spi_regs ((spi_regs_t *) SPI_BASE)
+
+
+// Masks for controlling different peripherals
+#define SPI_SS_AD9510    1
+#define SPI_SS_AD9777    2
+#define SPI_SS_RX_DAC    4
+#define SPI_SS_RX_ADC    8
+#define SPI_SS_RX_DB    16
+#define SPI_SS_TX_DAC   32
+#define SPI_SS_TX_ADC   64
+#define SPI_SS_TX_DB   128
+#define SPI_SS_ADS62P44 256
+
+// Masks for different parts of CTRL reg
+#define SPI_CTRL_ASS      (1<<13)
+#define SPI_CTRL_IE       (1<<12)
+#define SPI_CTRL_LSB      (1<<11)
+#define SPI_CTRL_TXNEG    (1<<10)
+#define SPI_CTRL_RXNEG    (1<< 9)
+#define SPI_CTRL_GO_BSY   (1<< 8)
+#define SPI_CTRL_CHAR_LEN_MASK 0x7F
+
+////////////////////////////////////////////////
+// I2C, Slave 3
+// See Wishbone I2C-Master Core Specification.
+
+#define I2C_BASE 0x3100
+
+typedef struct {
+  volatile uint32_t  prescaler_lo;	// r/w
+  volatile uint32_t  prescaler_hi;	// r/w
+  volatile uint32_t  ctrl;		// r/w
+  volatile uint32_t  data;		// wr = transmit reg; rd = receive reg
+  volatile uint32_t  cmd_status;	// wr = command reg;  rd = status reg
+} i2c_regs_t;
+
+#define i2c_regs ((i2c_regs_t *) I2C_BASE)
+
+#define	I2C_CTRL_EN	(1 << 7)	// core enable
+#define	I2C_CTRL_IE	(1 << 6)	// interrupt enable
+
+//
+// STA, STO, RD, WR, and IACK bits are cleared automatically
+//
+#define	I2C_CMD_START	(1 << 7)	// generate (repeated) start condition
+#define I2C_CMD_STOP	(1 << 6)	// generate stop condition
+#define	I2C_CMD_RD	(1 << 5)	// read from slave
+#define I2C_CMD_WR	(1 << 4)	// write to slave
+#define	I2C_CMD_NACK	(1 << 3)	// when a rcvr, send ACK (ACK=0) or NACK (ACK=1)
+#define I2C_CMD_RSVD_2	(1 << 2)	// reserved
+#define	I2C_CMD_RSVD_1	(1 << 1)	// reserved
+#define I2C_CMD_IACK	(1 << 0)	// set to clear pending interrupt
+
+#define I2C_ST_RXACK	(1 << 7)	// Received acknowledgement from slave (1 = NAK, 0 = ACK)
+#define	I2C_ST_BUSY	(1 << 6)	// 1 after START signal detected; 0 after STOP signal detected
+#define	I2C_ST_AL	(1 << 5)	// Arbitration lost.  1 when core lost arbitration
+#define	I2C_ST_RSVD_4	(1 << 4)	// reserved
+#define	I2C_ST_RSVD_3	(1 << 3)	// reserved
+#define	I2C_ST_RSVD_2	(1 << 2)	// reserved
+#define I2C_ST_TIP	(1 << 1)	// Transfer-in-progress
+#define	I2C_ST_IP	(1 << 0)	// Interrupt pending
+
+
+////////////////////////////////////////////////
+// GPIO, Slave 4
+//
+// These go to the daughterboard i/o pins
+
+#define GPIO_BASE 0x3200
+
+typedef struct {
+  volatile uint32_t	io;	  // tx data in high 16, rx in low 16
+  volatile uint32_t     ddr;      // 32 bits, 1 means output. tx in high 16, rx in low 16
+  volatile uint32_t	tx_sel;   // 16 2-bit fields select which source goes to TX DB
+  volatile uint32_t	rx_sel;   // 16 2-bit fields select which source goes to RX DB
+} gpio_regs_t;
+
+// each 2-bit sel field is layed out this way
+#define GPIO_SEL_SW	   0 // if pin is an output, set by software in the io reg
+#define	GPIO_SEL_ATR	   1 // if pin is an output, set by ATR logic
+#define	GPIO_SEL_DEBUG_0   2 // if pin is an output, debug lines from FPGA fabric
+#define	GPIO_SEL_DEBUG_1   3 // if pin is an output, debug lines from FPGA fabric
+
+#define gpio_base ((gpio_regs_t *) GPIO_BASE)
+
+///////////////////////////////////////////////////
+// Buffer Pool Status, Slave 5
+//
+// The buffers themselves are located in Slave 1, Buffer Pool RAM.
+// The status registers are in Slave 5, Buffer Pool Status.
+// The control register is in Slave 7, Settings Bus.
+
+#define BUFFER_POOL_STATUS_BASE 0x3300
+
+typedef struct {
+  volatile uint32_t last_line[NBUFFERS]; // last line xfer'd in buffer
+  volatile uint32_t status;	         // error and done flags
+  volatile uint32_t hw_config;	         // see below
+  volatile uint32_t dummy[3];
+  volatile uint32_t irqs;
+  volatile uint32_t pri_enc_bp_status;
+  volatile uint32_t cycle_count;
+} buffer_pool_status_t;
+
+#define buffer_pool_status ((buffer_pool_status_t *) BUFFER_POOL_STATUS_BASE)
+
+#define BUTTON_PUSHED ((buffer_pool_status->irqs & PIC_BUTTON) ? 0 : 1)
+
+/*
+ * Buffer n's xfer is done.
+ * Clear this bit by issuing bp_clear_buf(n)
+ */
+#define BPS_DONE(n)     (0x00000001 << (n))
+#define BPS_DONE_0	BPS_DONE(0)
+#define BPS_DONE_1	BPS_DONE(1)
+#define BPS_DONE_2	BPS_DONE(2)
+#define BPS_DONE_3	BPS_DONE(3)
+#define BPS_DONE_4	BPS_DONE(4)
+#define BPS_DONE_5	BPS_DONE(5)
+#define BPS_DONE_6	BPS_DONE(6)
+#define BPS_DONE_7	BPS_DONE(7)
+
+/*
+ * Buffer n's xfer had an error.
+ * Clear this bit by issuing bp_clear_buf(n)
+ */
+#define BPS_ERROR(n)	(0x00000100 << (n))
+#define BPS_ERROR_0	BPS_ERROR(0)
+#define BPS_ERROR_1	BPS_ERROR(1)
+#define BPS_ERROR_2	BPS_ERROR(2)
+#define BPS_ERROR_3	BPS_ERROR(3)
+#define BPS_ERROR_4	BPS_ERROR(4)
+#define BPS_ERROR_5	BPS_ERROR(5)
+#define BPS_ERROR_6	BPS_ERROR(6)
+#define BPS_ERROR_7	BPS_ERROR(7)
+
+/*
+ * Buffer n is idle.  A buffer is idle if it's not
+ * DONE, ERROR, or processing a transaction.  If it's
+ * IDLE, it's safe to start a new transaction.
+ *
+ * Clear this bit by starting a xfer with
+ * bp_send_from_buf or bp_receive_to_buf.
+ */
+#define BPS_IDLE(n)     (0x00010000 << (n))
+#define BPS_IDLE_0	BPS_IDLE(0)
+#define BPS_IDLE_1	BPS_IDLE(1)
+#define BPS_IDLE_2	BPS_IDLE(2)
+#define BPS_IDLE_3	BPS_IDLE(3)
+#define BPS_IDLE_4	BPS_IDLE(4)
+#define BPS_IDLE_5	BPS_IDLE(5)
+#define BPS_IDLE_6	BPS_IDLE(6)
+#define BPS_IDLE_7	BPS_IDLE(7)
+
+/*
+ * Buffer n has a "slow path" packet in it.
+ * This bit is orthogonal to the bits above and indicates that
+ * the FPGA ethernet rx protocol engine has identified this packet
+ * as one requiring firmware intervention.
+ */
+#define BPS_SLOWPATH(n) (0x01000000 << (n))
+#define BPS_SLOWPATH_0	BPS_SLOWPATH(0)
+#define BPS_SLOWPATH_1	BPS_SLOWPATH(1)
+#define BPS_SLOWPATH_2	BPS_SLOWPATH(2)
+#define BPS_SLOWPATH_3	BPS_SLOWPATH(3)
+#define BPS_SLOWPATH_4	BPS_SLOWPATH(4)
+#define BPS_SLOWPATH_5	BPS_SLOWPATH(5)
+#define BPS_SLOWPATH_6	BPS_SLOWPATH(6)
+#define BPS_SLOWPATH_7	BPS_SLOWPATH(7)
+
+
+#define BPS_DONE_ALL	  0x000000ff	// mask of all dones
+#define BPS_ERROR_ALL	  0x0000ff00	// mask of all errors
+#define BPS_IDLE_ALL      0x00ff0000	// mask of all idles
+#define BPS_SLOWPATH_ALL  0xff000000	// mask of all slowpaths
+
+// The hw_config register
+
+#define	HWC_SIMULATION		0x80000000
+#define	HWC_WB_CLK_DIV_MASK	0x0000000f
+
+/*!
+ * \brief return non-zero if we're running under the simulator
+ */
+inline static int
+hwconfig_simulation_p(void)
+{
+  return buffer_pool_status->hw_config & HWC_SIMULATION;
+}
+
+/*!
+ * \brief Return Wishbone Clock divisor.
+ * The processor runs at the Wishbone Clock rate which is MASTER_CLK_RATE / divisor.
+ */
+inline static int
+hwconfig_wishbone_divisor(void)
+{
+  return buffer_pool_status->hw_config & HWC_WB_CLK_DIV_MASK;
+}
+
+///////////////////////////////////////////////////
+// Ethernet Core, Slave 6
+
+#define ETH_BASE 0x3400
+
+#include "eth_mac_regs.h"
+
+#define eth_mac ((eth_mac_regs_t *) ETH_BASE)
+
+////////////////////////////////////////////////////
+// Settings Bus, Slave #7, Not Byte Addressable!
+//
+// Output-only from processor point-of-view.
+// 1KB of address space (== 256 32-bit write-only regs)
+
+
+#define MISC_OUTPUT_BASE        0x2000
+#define	TX_PROTOCOL_ENGINE_BASE 0x2080
+#define	RX_PROTOCOL_ENGINE_BASE 0x20C0
+#define BUFFER_POOL_CTRL_BASE   0x2100
+#define LAST_SETTING_REG        0x23FC	// last valid setting register
+
+#define SR_MISC 0
+#define SR_TX_PROT_ENG 32
+#define SR_RX_PROT_ENG 48
+#define SR_BUFFER_POOL_CTRL 64
+#define SR_UDP_SM 96
+#define SR_TX_DSP 208
+#define SR_TX_CTRL 224
+#define SR_RX_DSP 160
+#define SR_RX_CTRL 176
+#define SR_TIME64 192
+#define SR_SIMTIMER 198
+#define SR_LAST 255
+
+#define	_SR_ADDR(sr)	(MISC_OUTPUT_BASE + (sr) * sizeof(uint32_t))
+
+// --- buffer pool control regs ---
+
+typedef struct {
+  volatile uint32_t ctrl;
+} buffer_pool_ctrl_t;
+
+// buffer pool ports
+
+#define	PORT_SERDES	0	// serial/deserializer
+#define	PORT_DSP	1	// DSP tx or rx pipeline
+#define	PORT_ETH	2	// ethernet tx or rx
+#define	PORT_RAM	3	// RAM tx or rx
+
+// the buffer pool ctrl register fields
+
+#define BPC_BUFFER(n) (((n) & 0xf) << 28)
+#define   BPC_BUFFER_MASK      BPC_BUFFER(~0)
+#define   BPC_BUFFER_0	       BPC_BUFFER(0)
+#define   BPC_BUFFER_1	       BPC_BUFFER(1)
+#define   BPC_BUFFER_2	       BPC_BUFFER(2)
+#define   BPC_BUFFER_3	       BPC_BUFFER(3)
+#define   BPC_BUFFER_4	       BPC_BUFFER(4)
+#define   BPC_BUFFER_5	       BPC_BUFFER(5)
+#define   BPC_BUFFER_6	       BPC_BUFFER(6)
+#define   BPC_BUFFER_7	       BPC_BUFFER(7)
+#define	  BPC_BUFFER_NIL       BPC_BUFFER(0x8)	// disable
+
+#define BPC_PORT(n) (((n) & 0x7) << 25)
+#define   BPC_PORT_MASK        BPC_PORT(~0)
+#define   BPC_PORT_SERDES      BPC_PORT(PORT_SERDES)
+#define   BPC_PORT_DSP	       BPC_PORT(PORT_DSP)
+#define   BPC_PORT_ETH         BPC_PORT(PORT_ETH)
+#define   BPC_PORT_RAM         BPC_PORT(PORT_RAM)
+#define   BPC_PORT_NIL	       BPC_PORT(0x4)   	// disable
+
+#define	BPC_CLR	       	       (1 << 24)  // mutually excl commands
+#define	BPC_READ	       (1 << 23)
+#define BPC_WRITE              (1 << 22)
+
+#define BPC_STEP(step) (((step) & 0xf) << 18)
+#define   BPC_STEP_MASK	       BPC_STEP(~0)
+#define BPC_LAST_LINE(line) (((line) & 0x1ff) << 9)
+#define   BPC_LAST_LINE_MASK   BPC_LAST_LINE(~0)
+#define BPC_FIRST_LINE(line) (((line) & 0x1ff) << 0)
+#define   BPC_FIRST_LINE_MASK  BPC_FIRST_LINE(~0)
+
+#define buffer_pool_ctrl ((buffer_pool_ctrl_t *) BUFFER_POOL_CTRL_BASE)
+
+// --- misc outputs ---
+
+typedef struct {
+  volatile uint32_t	clk_ctrl;
+  volatile uint32_t	serdes_ctrl;
+  volatile uint32_t	adc_ctrl;
+  volatile uint32_t	leds;
+  volatile uint32_t	phy_ctrl;	// LSB is reset line to eth phy
+  volatile uint32_t	debug_mux_ctrl;
+  volatile uint32_t     ram_page;       // FIXME should go somewhere else...
+  volatile uint32_t     flush_icache;   // Flush the icache
+  volatile uint32_t     led_src;        // HW or SW control for LEDs
+} output_regs_t;
+
+#define SERDES_ENABLE 8
+#define SERDES_PRBSEN 4
+#define SERDES_LOOPEN 2
+#define SERDES_RXEN   1
+
+#define	ADC_CTRL_ON	0x0F
+#define	ADC_CTRL_OFF	0x00
+
+// crazy order that matches the labels on the case
+
+#define	LED_A		(1 << 4)
+#define	LED_B		(1 << 1)
+#define	LED_C		(1 << 3)
+#define	LED_D		(1 << 0)
+#define	LED_E		(1 << 2)
+//      LED_F		// controlled by CPLD
+#define	LED_RJ45	(1 << 5)
+
+#define output_regs ((output_regs_t *) MISC_OUTPUT_BASE)
+
+// --- udp tx regs ---
+
+typedef struct {
+  // Bits 19:16 are control info; bits 15:0 are data (see below)
+  // First two words are unused.
+  volatile uint32_t _nope[2];
+  //--- ethernet header - 14 bytes---
+  volatile struct{
+    uint32_t mac_dst_0_1; //word 2
+    uint32_t mac_dst_2_3;
+    uint32_t mac_dst_4_5;
+    uint32_t mac_src_0_1;
+    uint32_t mac_src_2_3;
+    uint32_t mac_src_4_5;
+    uint32_t ether_type; //word 8
+  } eth_hdr;
+  //--- ip header - 20 bytes ---
+  volatile struct{
+    uint32_t ver_ihl_tos; //word 9
+    uint32_t total_length;
+    uint32_t identification;
+    uint32_t flags_frag_off;
+    uint32_t ttl_proto;
+    uint32_t checksum;
+    uint32_t src_addr_high;
+    uint32_t src_addr_low;
+    uint32_t dst_addr_high;
+    uint32_t dst_addr_low; //word 18
+  } ip_hdr;
+  //--- udp header - 8 bytes ---
+  volatile struct{
+    uint32_t src_port; //word 19
+    uint32_t dst_port;
+    uint32_t length;
+    uint32_t checksum; //word 22
+  } udp_hdr;
+  volatile uint32_t _pad[32-23];
+} sr_udp_sm_t;
+
+// control bits (all expect UDP_SM_LAST_WORD are mutually exclusive)
+
+// This is the last word of the header
+#define	UDP_SM_LAST_WORD		(1 << 19)
+
+// Insert IP header checksum here.  Data is the xor of 16'hFFFF and
+// the values written into regs 9-13 and 15-18.
+#define	UDP_SM_INS_IP_HDR_CHKSUM	(1 << 18)
+
+// Insert IP Length here (data ignored)
+#define	UDP_SM_INS_IP_LEN		(1 << 17)
+
+// Insert UDP Length here (data ignore)
+#define	UDP_SM_INS_UDP_LEN		(1 << 16)
+
+#define sr_udp_sm ((sr_udp_sm_t *) _SR_ADDR(SR_UDP_SM))
+
+// --- dsp tx regs ---
+
+#define MIN_CIC_INTERP	1
+#define	MAX_CIC_INTERP  128
+
+typedef struct {
+  volatile uint32_t     num_chan;
+  volatile uint32_t     clear_state;	// clears out state machine, fifos,
+} sr_tx_ctrl_t;
+
+#define sr_tx_ctrl ((sr_tx_ctrl_t *) _SR_ADDR(SR_TX_CTRL))
+
+typedef struct {
+  volatile int32_t	freq;
+  volatile uint32_t	scale_iq;	// {scale_i,scale_q}
+  volatile uint32_t     interp_rate;
+  volatile uint32_t     _padding0;      // padding for the tx_mux
+                                        //   NOT freq, scale, interp
+  /*!
+   * \brief output mux configuration.
+   *
+   * <pre>
+   *     3                   2                   1                       
+   *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   *  +-------------------------------+-------+-------+-------+-------+
+   *  |                                               | DAC1  |  DAC0 |
+   *  +-------------------------------+-------+-------+-------+-------+
+   * 
+   *  There are N DUCs (1 now) with complex inputs and outputs.
+   *  There are two DACs.
+   * 
+   *  Each 4-bit DACx field specifies the source for the DAC
+   *  Each subfield is coded like this: 
+   * 
+   *     3 2 1 0
+   *    +-------+
+   *    |   N   |
+   *    +-------+
+   * 
+   *  N specifies which DUC output is connected to this DAC.
+   * 
+   *   N   which interp output
+   *  ---  -------------------
+   *   0   DUC 0 I
+   *   1   DUC 0 Q
+   *   2   DUC 1 I
+   *   3   DUC 1 Q
+   *   F   All Zeros
+   *   
+   * The default value is 0x10
+   * </pre>
+   */
+  volatile uint32_t	tx_mux;
+
+} dsp_tx_regs_t;
+  
+#define dsp_tx_regs ((dsp_tx_regs_t *) _SR_ADDR(SR_TX_DSP))
+
+// --- VITA RX CTRL regs ---
+typedef struct {
+  // The following 3 are logically a single command register.
+  // They are clocked into the underlying fifo when time_ticks is written.
+  volatile uint32_t	cmd;		// {now, chain, num_samples(30)
+  volatile uint32_t	time_secs;
+  volatile uint32_t	time_ticks;
+
+  volatile uint32_t	clear_overrun;	// write anything to clear overrun
+  volatile uint32_t	vrt_header;	// word 0 of packet.  FPGA fills in packet counter
+  volatile uint32_t	vrt_stream_id;	// word 1 of packet. 
+  volatile uint32_t	vrt_trailer;
+  volatile uint32_t	nsamples_per_pkt;
+  volatile uint32_t     nchannels;      // 1 in basic case, up to 4 for vector sources
+  volatile uint32_t     pad[7];         // Make each structure 16 elements long
+} sr_rx_ctrl_t;
+
+#define sr_rx_ctrl ((sr_rx_ctrl_t *) _SR_ADDR(SR_RX_CTRL))
+
+// --- dsp rx regs ---
+#define	MIN_CIC_DECIM	1
+#define	MAX_CIC_DECIM   128
+
+typedef struct {
+  volatile int32_t	freq;
+  volatile uint32_t	scale_iq;	// {scale_i,scale_q}
+  volatile uint32_t     decim_rate;
+  volatile uint32_t     dcoffset_i;     // Bit 31 high sets fixed offset mode, using lower 14 bits,
+                                        // otherwise it is automatic 
+  volatile uint32_t     dcoffset_q;     // Bit 31 high sets fixed offset mode, using lower 14 bits
+
+  /*!
+   * \brief input mux configuration.
+   *
+   * This determines which ADC (or constant zero) is connected to 
+   * each DDC input.  There are N DDCs (1 now).  Each has two inputs.
+   *
+   * <pre>
+   * Mux value:
+   *
+   *    3                   2                   1                       
+   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   * +-------+-------+-------+-------+-------+-------+-------+-------+
+   * |                                                       |Q0 |I0 |
+   * +-------+-------+-------+-------+-------+-------+-------+-------+
+   *
+   * Each 2-bit I field is either 00 (A/D A), 01 (A/D B) or 1X (const zero)
+   * Each 2-bit Q field is either 00 (A/D A), 01 (A/D B) or 1X (const zero)
+   *
+   * The default value is 0x4
+   * </pre>
+   */
+  volatile uint32_t     rx_mux;        // called adc_mux in dsp_core_rx.v
+
+  /*!
+   * \brief Streaming GPIO configuration
+   *
+   * This determines whether the LSBs of I and Q samples come from the DSP
+   * pipeline or from the io_rx GPIO pins.  To stream GPIO, one must first
+   * set the GPIO data direction register to have io_rx[15] and/or io_rx[14]
+   * configured as inputs.  The GPIO pins will be sampled at the time the
+   * remainder of the DSP sample is strobed into the RX sample FIFO.  There
+   * will be a decimation-dependent fixed time offset between the GPIO
+   * sample stream and the associated RF samples.
+   *
+   *    3                   2                   1                       
+   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   * +-------+-------+-------+-------+-------+-------+-------+-------+
+   * |                           MBZ                             |Q|I|
+   * +-------+-------+-------+-------+-------+-------+-------+-------+
+   *
+   * I         0=LSB comes from DSP pipeline (default)
+   *           1=LSB comes from io_rx[15]
+   * 
+   * Q         0=LSB comes from DSP pipeline (default)
+   *           1=LSB comes from io_rx[14]
+   */
+  volatile uint32_t gpio_stream_enable;
+
+} dsp_rx_regs_t;
+  
+#define dsp_rx_regs ((dsp_rx_regs_t *) _SR_ADDR(SR_RX_DSP))
+
+// ----------------------------------------------------------------
+// VITA49 64 bit time (write only)
+  /*!
+   * \brief Time 64 flags
+   *
+   * <pre>
+   *
+   *    3                   2                   1                       
+   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   * +-----------------------------------------------------------+-+-+
+   * |                                                           |S|P|
+   * +-----------------------------------------------------------+-+-+
+   *
+   * P - PPS edge selection (0=negedge, 1=posedge, default=0)
+   * S - Source (0=sma, 1=mimo, 0=default)
+   *
+   * </pre>
+   */
+typedef struct {
+  volatile uint32_t	secs;	// value to set absolute secs to on next PPS
+  volatile uint32_t	ticks;	// value to set absolute ticks to on next PPS
+  volatile uint32_t flags;  // flags - see chart above
+  volatile uint32_t imm;    // set immediate (0=latch on next pps, 1=latch immediate, default=0)
+} sr_time64_t;
+
+#define sr_time64 ((sr_time64_t *) _SR_ADDR(SR_TIME64))
+
+
+/* 
+ * --- ethernet tx protocol engine regs (write only) ---
+ *
+ * These registers control the transmit portion of the ethernet
+ * protocol engine (out of USRP2).  The protocol engine handles fifo
+ * status and sequence number insertion in outgoing packets, and
+ * automagically generates status packets when required to inform the
+ * host of changes in fifo availability.
+ *
+ * All outgoing packets have their fifo_status field set to the number
+ * of 32-bit lines of fifo available in the ethernet Rx fifo (see
+ * usrp2_eth_packet.h).  Seqno's are set if FIXME, else 0.
+ *
+ * FIXME clean this up once we know how it's supposed to behave.
+ */
+
+typedef struct {
+  volatile uint32_t  flags;	     // not yet fully defined (channel?)
+  volatile uint32_t  mac_dst0123;    // 4 bytes of destination mac addr
+  volatile uint32_t  mac_dst45src01; // 2 bytes of dest mac addr; 2 bytes of src mac addr
+  volatile uint32_t  mac_src2345;    // 4 bytes of destination mac addr
+  volatile uint32_t  seqno;	     // Write to init seqno.  It autoincs on match
+} tx_proto_engine_regs_t;
+
+#define tx_proto_engine ((tx_proto_engine_regs_t *) TX_PROTOCOL_ENGINE_BASE)
+
+/*
+ * --- ethernet rx protocol engine regs (write only) ---
+ *
+ * These registers control the receive portion of the ethernet
+ * protocol engine (into USRP2).  The protocol engine offloads common
+ * packet inspection operations so that firmware has less to do on
+ * "fast path" packets.
+ *
+ * The registers define conditions which must be matched for a packet
+ * to be considered a "fast path" packet.  If a received packet
+ * matches the src and dst mac address, ethertype, flags field, and
+ * expected seqno number it is considered a "fast path" packet, and
+ * the expected seqno is updated.  If the packet fails to satisfy any
+ * of the above conditions it's a "slow path" packet, and the
+ * corresponding SLOWPATH flag will be set buffer_status register.
+ */
+
+typedef struct {
+  volatile uint32_t  flags;	     // not yet fully defined (channel?)
+  volatile uint32_t  mac_dst0123;    // 4 bytes of destination mac addr
+  volatile uint32_t  mac_dst45src01; // 2 bytes of dest mac addr; 2 bytes of src mac addr
+  volatile uint32_t  mac_src2345;    // 4 bytes of destination mac addr
+  volatile uint32_t  ethertype_pad;  // ethertype in high 16-bits
+} rx_proto_engine_regs_t;
+
+#define rx_proto_engine ((rx_proto_engine_regs_t *) RX_PROTOCOL_ENGINE_BASE)
+
+
+
+///////////////////////////////////////////////////
+// Simple Programmable Interrupt Controller, Slave 8
+
+#define PIC_BASE  0x3500
+
+// Interrupt request lines
+// Bit numbers (LSB == 0) that correpond to interrupts into PIC
+
+#define	IRQ_BUFFER	0	// buffer manager
+#define	IRQ_ONETIME	1
+#define	IRQ_SPI		2
+#define	IRQ_I2C		3
+#define	IRQ_PHY		4	// ethernet PHY
+#define	IRQ_UNDERRUN	5
+#define	IRQ_OVERRUN	6
+#define	IRQ_PPS		7	// pulse per second
+#define	IRQ_UART_RX	8
+#define	IRQ_UART_TX	9
+#define	IRQ_SERDES	10
+#define	IRQ_CLKSTATUS	11
+#define IRQ_PERIODIC    12
+#define IRQ_BUTTON	13
+
+#define IRQ_TO_MASK(x) (1 << (x))
+
+#define PIC_BUFFER_INT    IRQ_TO_MASK(IRQ_BUFFER)
+#define PIC_ONETIME_INT   IRQ_TO_MASK(IRQ_ONETIME)
+#define PIC_SPI_INT       IRQ_TO_MASK(IRQ_SPI)
+#define PIC_I2C_INT       IRQ_TO_MASK(IRQ_I2C)
+#define PIC_PHY_INT       IRQ_TO_MASK(IRQ_PHY)
+#define PIC_UNDERRUN_INT  IRQ_TO_MASK(IRQ_UNDERRUN)
+#define PIC_OVERRUN_INT   IRQ_TO_MASK(IRQ_OVERRUN)
+#define PIC_PPS_INT   	  IRQ_TO_MASK(IRQ_PPS)
+#define PIC_UART_RX_INT   IRQ_TO_MASK(IRQ_UART_RX)
+#define PIC_UART_TX_INT   IRQ_TO_MASK(IRQ_UART_TX)
+#define PIC_SERDES        IRQ_TO_MASK(IRQ_SERDES)
+#define PIC_CLKSTATUS     IRQ_TO_MASK(IRQ_CLKSTATUS)
+#define PIC_BUTTON				IRQ_TO_MASK(IRQ_BUTTON)
+
+typedef struct {
+  volatile uint32_t edge_enable; // mask: 1 -> edge triggered, 0 -> level
+  volatile uint32_t polarity;	 // mask: 1 -> rising edge
+  volatile uint32_t mask;	 // mask: 1 -> disabled
+  volatile uint32_t pending;	 // mask: 1 -> pending; write 1's to clear pending ints
+} pic_regs_t;
+
+#define pic_regs ((pic_regs_t *) PIC_BASE)
+
+// ----------------------------------------------------------------
+// WB_CLK_RATE is the time base for this
+typedef struct {
+  volatile uint32_t	onetime;   // Number of wb clk cycles till the onetime interrupt
+  volatile uint32_t	periodic;  // Repeat rate of periodic interrupt
+} sr_simple_timer_t;
+
+#define sr_simple_timer ((sr_simple_timer_t *) _SR_ADDR(SR_SIMTIMER))
+
+///////////////////////////////////////////////////
+// UNUSED, Slave 9
+
+///////////////////////////////////////////////////
+// UART, Slave 10
+
+#define UART_BASE  0x3700
+
+typedef struct {
+  //  All elements are 8 bits except for clkdiv (16), but we use uint32 to make 
+  //    the hardware for decoding easier
+  volatile uint32_t clkdiv;  // Set to 50e6 divided by baud rate (no x16 factor)
+  volatile uint32_t txlevel; // Number of spaces in the FIFO for writes
+  volatile uint32_t rxlevel; // Number of available elements in the FIFO for reads
+  volatile uint32_t txchar;  // Write characters to be sent here
+  volatile uint32_t rxchar;  // Read received characters here
+} uart_regs_t;
+
+#define uart_regs ((uart_regs_t *) UART_BASE)
+
+///////////////////////////////////////////////////
+// ATR Controller, Slave 11
+
+#define ATR_BASE  0x3800
+
+typedef struct {
+  volatile uint32_t	v[16];
+} atr_regs_t;
+
+#define	ATR_IDLE	0x0	// indicies into v
+#define ATR_TX		0x1
+#define	ATR_RX		0x2
+#define	ATR_FULL	0x3
+
+#define atr_regs ((atr_regs_t *) ATR_BASE)
+
+///////////////////////////////////////////////////
+// UNUSED, Slave 12
+
+///////////////////////////////////////////////////
+// ICAP, Slave 13
+
+#define ICAP_BASE 0x3A00
+typedef struct {
+  uint32_t icap; //only the lower 8 bits matter
+} icap_regs_t;
+
+#define icap_regs ((icap_regs_t *) ICAP_BASE)
+
+///////////////////////////////////////////////////
+// SPI Flash interface, Slave 14
+// Control register definitions are the same as SPI, so use SPI_CTRL_ASS, etc.
+// Peripheral mask not needed since bus is dedicated (CE held low)
+
+#define SPIF_BASE 0x3B00
+typedef struct {
+  volatile uint32_t	txrx0;
+  volatile uint32_t	txrx1;
+  volatile uint32_t	txrx2;
+  volatile uint32_t	txrx3;
+  volatile uint32_t	ctrl;
+  volatile uint32_t	div;
+  volatile uint32_t	ss;
+} spif_regs_t;
+
+#define spif_regs ((spif_regs_t *) SPIF_BASE)
+
+////////////////////////////////////////////////////////////////
+// Main RAM, Slave 15
+
+#define RAM_BASE 0x8000
+
+
+
+///////////////////////////////////////////////////
+#endif
+
-- 
cgit v1.2.3


From f39c4538a3ca25c79f6b793ee0b6448051dcd751 Mon Sep 17 00:00:00 2001
From: Nick Foster <nick@nerdnetworks.org>
Date: Thu, 29 Jul 2010 10:12:45 -0700
Subject: Clock bugs, LED order. Figured out cold-start problem with Matt's
 help -- the DCM wasn't being reset. This also explains why USRP2 didn't like
 it when clocks_mimo_config was omitted -- it was sneakily resetting the DCM
 while enabling/disabling ref outputs.

Also re-did USRP2P LED order and genericized the LED settings so LED_D
is LED_D for both USRP2 and USRP2P.
---
 firmware/microblaze/lib/clocks.c        | 23 ++++++++++++++---------
 firmware/microblaze/lib/clocks.h        |  4 ++--
 firmware/microblaze/lib/u2_init.c       |  3 ++-
 firmware/microblaze/usrp2/memory_map.h  |  4 ++++
 firmware/microblaze/usrp2p/ethernet.c   |  4 ++--
 firmware/microblaze/usrp2p/memory_map.h | 16 ++++++++++------
 6 files changed, 34 insertions(+), 20 deletions(-)

(limited to 'firmware/microblaze/usrp2p/memory_map.h')

diff --git a/firmware/microblaze/lib/clocks.c b/firmware/microblaze/lib/clocks.c
index b9bd2e107..2b352a385 100644
--- a/firmware/microblaze/lib/clocks.c
+++ b/firmware/microblaze/lib/clocks.c
@@ -25,7 +25,6 @@
 #include "ad9510.h"
 #include "spi.h"
 #include "u2_init.h"
-#include "nonstdio.h"
 
 //USRP2PLUS clocks:
 //Clock 0: testclk
@@ -46,6 +45,7 @@ clocks_init(void)
   // Set up basic clocking functions in AD9510
   ad9510_write_reg(0x45, 0x01); // CLK2 drives distribution
 
+  //enable the 100MHz clock output to the FPGA for 50MHz CPU clock
   clocks_enable_fpga_clk(true, 1);
 
   spi_wait();
@@ -58,7 +58,14 @@ clocks_init(void)
 //  ad9510_write_reg(0x5A, 0x01); // Update Regs
 
   // Primary clock configuration
-  clocks_mimo_config(MC_WE_DONT_LOCK);
+//  clocks_mimo_config(MC_WE_DONT_LOCK);
+
+
+  //wait for the clock to stabilize
+  while(!clocks_lock_detect());
+
+  //issue a reset to the DCM so it locks up to the new freq
+  output_regs->clk_ctrl |= CLK_RESET;
 
   // Set up other clocks
   //clocks_enable_test_clk(false, 0);
@@ -71,7 +78,7 @@ clocks_init(void)
   //clocks_enable_adc_clk(true, 1);
 }
 
-
+/*
 void
 clocks_mimo_config(int flags)
 {
@@ -99,7 +106,7 @@ clocks_mimo_config(int flags)
   spi_wait();
   
   // Allow for clock switchover
-  
+  // The below masks include 0x10, which issues a reset to the DCM.  
   if (flags & _MC_WE_LOCK){		// WE LOCK
     if (flags & _MC_MIMO_CLK_INPUT) {
       // Turn on ref output and choose the MIMO connector
@@ -121,16 +128,14 @@ clocks_mimo_config(int flags)
 //  else
 //    clocks_enable_clkexp_out(false,0); 
 }
+*/
 
-/*
 bool 
 clocks_lock_detect()
 {
-  if(pic_regs->pending & PIC_CLKSTATUS)
-    return true;
-  return false;
+    return (pic_regs->pending & PIC_CLKSTATUS);
 }
-*/
+
 int inline
 clocks_gen_div(int divisor)
 {
diff --git a/firmware/microblaze/lib/clocks.h b/firmware/microblaze/lib/clocks.h
index 399127595..28d1d542f 100644
--- a/firmware/microblaze/lib/clocks.h
+++ b/firmware/microblaze/lib/clocks.h
@@ -43,12 +43,12 @@ void clocks_init(void);
  * Configure our master clock source, and whether or not we drive a
  * clock onto the mimo connector.  See MC_flags in usrp2_mimo_config.h.
  */
-void clocks_mimo_config(int flags);
+//void clocks_mimo_config(int flags);
 
 /*!
  * \brief Lock Detect -- Return True if our PLL is locked
  */
-//bool clocks_lock_detect();
+bool clocks_lock_detect();
 
 /*!
  * \brief Enable or disable test clock (extra clock signal)
diff --git a/firmware/microblaze/lib/u2_init.c b/firmware/microblaze/lib/u2_init.c
index ff558d673..75bc40859 100644
--- a/firmware/microblaze/lib/u2_init.c
+++ b/firmware/microblaze/lib/u2_init.c
@@ -26,6 +26,7 @@
 #include "mdelay.h"
 #include "clocks.h"
 #include "usrp2/fw_common.h"
+#include "nonstdio.h"
 
 unsigned char u2_hw_rev_major;
 unsigned char u2_hw_rev_minor;
@@ -66,7 +67,7 @@ u2_init(void)
   mdelay(100);
   hal_set_leds(0x1f, 0x1f);
   mdelay(100);
-  hal_set_leds(0x1, 0x1f);  // Leave the first one on
+  hal_set_leds(LED_D, 0x1f);  // Leave one on
 
 #if 0
   // test register readback
diff --git a/firmware/microblaze/usrp2/memory_map.h b/firmware/microblaze/usrp2/memory_map.h
index 4c9ead615..41a2820bc 100644
--- a/firmware/microblaze/usrp2/memory_map.h
+++ b/firmware/microblaze/usrp2/memory_map.h
@@ -375,6 +375,10 @@ typedef struct {
   volatile uint32_t     led_src;        // HW or SW control for LEDs
 } output_regs_t;
 
+#define CLK_RESET  (1<<4)
+#define CLK_ENABLE (1<<3) | (1<<2)
+#define CLK_SEL    (1<<1) | (1<<0)
+
 #define SERDES_ENABLE 8
 #define SERDES_PRBSEN 4
 #define SERDES_LOOPEN 2
diff --git a/firmware/microblaze/usrp2p/ethernet.c b/firmware/microblaze/usrp2p/ethernet.c
index 80c303153..660f28934 100644
--- a/firmware/microblaze/usrp2p/ethernet.c
+++ b/firmware/microblaze/usrp2p/ethernet.c
@@ -70,7 +70,7 @@ ed_link_up(int speed)
   ed_set_mac_speed(speed);
 
 	//turn on link LED for USRP2P
-	hal_set_leds((1 << 0), (1 << 0));
+	hal_set_leds(LED_RJ45, LED_RJ45);
 
 
   if (ed_callback)		// fire link changed callback
@@ -83,7 +83,7 @@ ed_link_down(void)
   // putstr("ed_link_down\n");
 
 	//turn off link LED for USRP2P
-	hal_set_leds(0, (1 << 0));
+	hal_set_leds(0, LED_RJ45);
 
   if (ed_callback)		// fire link changed callback
     (*ed_callback)(0);
diff --git a/firmware/microblaze/usrp2p/memory_map.h b/firmware/microblaze/usrp2p/memory_map.h
index fc0094e67..9c5b576d7 100644
--- a/firmware/microblaze/usrp2p/memory_map.h
+++ b/firmware/microblaze/usrp2p/memory_map.h
@@ -402,6 +402,10 @@ typedef struct {
   volatile uint32_t     led_src;        // HW or SW control for LEDs
 } output_regs_t;
 
+#define CLK_RESET  (1<<4)
+#define CLK_ENABLE (1<<3) | (1<<2)
+#define CLK_SEL    (1<<1) | (1<<0)
+
 #define SERDES_ENABLE 8
 #define SERDES_PRBSEN 4
 #define SERDES_LOOPEN 2
@@ -412,13 +416,13 @@ typedef struct {
 
 // crazy order that matches the labels on the case
 
-#define	LED_A		(1 << 4)
-#define	LED_B		(1 << 1)
-#define	LED_C		(1 << 3)
-#define	LED_D		(1 << 0)
-#define	LED_E		(1 << 2)
+#define	LED_A		(1 << 2)
+#define	LED_B		(1 << 5)
+#define	LED_E		(1 << 3)
+#define	LED_D		(1 << 1)
+#define	LED_C		(1 << 4)
 //      LED_F		// controlled by CPLD
-#define	LED_RJ45	(1 << 5)
+#define	LED_RJ45	(1 << 0)
 
 #define output_regs ((output_regs_t *) MISC_OUTPUT_BASE)
 
-- 
cgit v1.2.3


From dfafbd5f2dbf0758df33d10922eec3c1a37dd32b Mon Sep 17 00:00:00 2001
From: Nick Foster <nick@nerdnetworks.org>
Date: Wed, 11 Aug 2010 14:20:50 -0700
Subject: Branch to make use of quad UART on USRP2P.

---
 firmware/microblaze/lib/hal_io.c        | 14 +++++-----
 firmware/microblaze/lib/hal_uart.c      | 48 ++++++++++++++++++++++++---------
 firmware/microblaze/lib/hal_uart.h      |  8 +++---
 firmware/microblaze/usrp2p/memory_map.h |  5 +++-
 4 files changed, 50 insertions(+), 25 deletions(-)

(limited to 'firmware/microblaze/usrp2p/memory_map.h')

diff --git a/firmware/microblaze/lib/hal_io.c b/firmware/microblaze/lib/hal_io.c
index 58b1e681e..b68067308 100644
--- a/firmware/microblaze/lib/hal_io.c
+++ b/firmware/microblaze/lib/hal_io.c
@@ -102,7 +102,7 @@ hal_finish(void)
 
 // %c
 inline int
-putchar(int ch)
+fputchar(int ch)
 {
   hal_gpio_set_rx((s << 8) | W, 0xff80);
   hal_gpio_set_rx(0, 0xff80);
@@ -124,14 +124,14 @@ hal_finish(void)
 
 // %c
 inline int
-putchar(int ch)
+fputchar(int ch)
 {
   hal_uart_putc(ch);
   return ch;
 }
 
 int
-getchar(void)
+fgetchar(void)
 {
   return hal_uart_getc();
 }
@@ -172,13 +172,13 @@ getchar(void)
 
 // \n
 inline void 
-newline(void)
+fnewline(void)
 {
   putchar('\n');
 }
 
 int
-putstr(const char *s)
+fputstr(const char *s)
 {
   while (*s)
     putchar(*s++);
@@ -187,7 +187,7 @@ putstr(const char *s)
 }
 
 int
-puts(const char *s)
+fputs(const char *s)
 {
   putstr(s);
   putchar('\n');
@@ -195,7 +195,7 @@ puts(const char *s)
 }
 
 char *
-gets(char * const s)
+fgets(char * const s)
 {
 	char *x = s;
 	while((*x=(char)hal_uart_getc()) != '\n') x++;
diff --git a/firmware/microblaze/lib/hal_uart.c b/firmware/microblaze/lib/hal_uart.c
index fe3b7515a..91d67b5e0 100644
--- a/firmware/microblaze/lib/hal_uart.c
+++ b/firmware/microblaze/lib/hal_uart.c
@@ -37,28 +37,30 @@ divisor_table[MAX_WB_DIV+1][NSPEEDS] = {
   { 163,  81,  41,  27, 14,  7 },  // 4:  25 MHz
 };
 
-#define u uart_regs
+//we wrap hal_uart_putc hal_uart_putc_nowait, and hal_uart_getc to accept a UART pointer given by hal_get_uart. we modify hal_io.c to use the new versions.
 
-static char uart_mode = UART_MODE_ONLCR;
+static char uart_mode[4] = {UART_MODE_ONLCR, UART_MODE_ONLCR, UART_MODE_ONLCR, UART_MODE_ONLCR};
 
 void
-hal_uart_set_mode(int mode)
+hal_uart_set_mode(int uart, int mode)
 {
-  uart_mode = mode;
+  uart_mode[uart] = mode;
 }
 
 void
 hal_uart_init(void)
 {
-	hal_uart_set_mode(UART_MODE_ONLCR);
-  u->clkdiv = 217;  // 230400 bps
+  for(int i = 0; i < 4; i++) {
+  	hal_uart_set_mode(i, UART_MODE_ONLCR);
+    u->clkdiv = 217;  // 230400 bps TODO: change to reflect new quad UART
+  }
 }
 
 void
-hal_uart_putc(int ch)
+hal_uart_putc(uart_regs_t *u, int ch)
 {
-  if (ch == '\n')// && (uart_mode == UART_MODE_ONLCR))		//map \n->\r\n if necessary
-    hal_uart_putc('\r');
+  if (ch == '\n')// && (uart_mode[uart] == UART_MODE_ONLCR))		//map \n->\r\n if necessary
+    hal_uart_putc(u, '\r');
 
   while (u->txlevel == 0)	 // wait for fifo to have space
     ;
@@ -67,20 +69,40 @@ hal_uart_putc(int ch)
 }
 
 void
-hal_uart_putc_nowait(int ch)
+hal_uart_putc_nowait(uart_regs_t *u, int ch)
 {
-  if (ch == '\n')// && (uart_mode == UART_MODE_ONLCR))		//map \n->\r\n if necessary
-    hal_uart_putc('\r');
+  if (ch == '\n')// && (uart_mode[uart] == UART_MODE_ONLCR))		//map \n->\r\n if necessary
+    hal_uart_putc(u, '\r');
 
   if(u->txlevel)   // If fifo has space
     u->txchar = ch;
 }
 
 int
-hal_uart_getc(void)
+hal_uart_getc(uart_regs_t *u)
 {
   while ((u->rxlevel) == 0)  // wait for data to be ready
     ;
 
   return u->rxchar;
 }
+
+uart_regs_t *
+hal_get_uart(int number)
+{
+  switch(number) {
+  case 0:
+    return uart_regs_0;
+    break;
+  case 1:
+    return uart_regs_1;
+    break;
+  case 2:
+    return uart_regs_2;
+    break;
+  case 3:
+    return uart_regs_3;
+    break;
+  default:
+    return uart_regs_0; //for safety
+}
diff --git a/firmware/microblaze/lib/hal_uart.h b/firmware/microblaze/lib/hal_uart.h
index dfd73c323..218bd7cb4 100644
--- a/firmware/microblaze/lib/hal_uart.h
+++ b/firmware/microblaze/lib/hal_uart.h
@@ -28,7 +28,7 @@
 /*
  * \brief Set uart mode
  */
-void hal_uart_set_mode(int flags);
+void hal_uart_set_mode(int uart, int flags);
 
 /*!
  * \brief one-time call to init
@@ -62,17 +62,17 @@ void hal_uart_get_config(hal_uart_config_t *c);
 /*!
  * \brief Enqueue \p ch for output over serial port
  */
-void hal_uart_putc(int ch);
+void hal_uart_putc(uart_regs_t *u, int ch);
 
 /*!
  * \brief Enqueue \p ch for output over serial port, silent fail if queue is full
  */
-void hal_uart_putc_nowait(int ch);
+void hal_uart_putc_nowait(uart_regs_t *u, int ch);
 
 /*
  * \brief Blocking read of next char from serial port
  */
-int hal_uart_getc(void);
+int hal_uart_getc(uart_regs_t *u);
 
 
 #endif /* INCLUDED_HAL_UART_H */
diff --git a/firmware/microblaze/usrp2p/memory_map.h b/firmware/microblaze/usrp2p/memory_map.h
index 9c5b576d7..b69cc59bd 100644
--- a/firmware/microblaze/usrp2p/memory_map.h
+++ b/firmware/microblaze/usrp2p/memory_map.h
@@ -781,7 +781,10 @@ typedef struct {
   volatile uint32_t rxchar;  // Read received characters here
 } uart_regs_t;
 
-#define uart_regs ((uart_regs_t *) UART_BASE)
+#define uart_regs_0 ((uart_regs_t *) UART_BASE)
+#define uart_regs_1 ((uart_regs_t *) UART_BASE + 0x0020)
+#define uart_regs_2 ((uart_regs_t *) UART_BASE + 0x0040)
+#define uart_regs_3 ((uart_regs_t *) UART_BASE + 0x0060)
 
 ///////////////////////////////////////////////////
 // ATR Controller, Slave 11
-- 
cgit v1.2.3


From 32c40b5f5956d29e3be1fc3c94a213f8f0d68f42 Mon Sep 17 00:00:00 2001
From: Nick Foster <nick@nerdnetworks.org>
Date: Thu, 12 Aug 2010 10:23:33 -0700
Subject: Working support for multiple UARTs.

Default behavior (printf, gets, etc.) routes to DEFAULT_UART, set in hal_uart.h. Use fputstr() to print to other UARTs. Bring
fgets() from hal_io.c out in hal_io.h if you want to read data from other UARTs.

Still blocking. No interrupt-driven stuff yet.
---
 firmware/microblaze/lib/hal_io.c        | 66 ++++++++++++++++++------
 firmware/microblaze/lib/hal_io.h        |  2 +
 firmware/microblaze/lib/hal_uart.c      | 89 ++++++++++++++++-----------------
 firmware/microblaze/lib/hal_uart.h      | 42 +++++++++-------
 firmware/microblaze/usrp2p/memory_map.h |  6 +--
 5 files changed, 122 insertions(+), 83 deletions(-)

(limited to 'firmware/microblaze/usrp2p/memory_map.h')

diff --git a/firmware/microblaze/lib/hal_io.c b/firmware/microblaze/lib/hal_io.c
index b68067308..8bb5e2af8 100644
--- a/firmware/microblaze/lib/hal_io.c
+++ b/firmware/microblaze/lib/hal_io.c
@@ -18,9 +18,9 @@
 
 // conditionalized on HAL_IO_USES_DBOARD_PINS && HAL_IO_USES_UART
 
-#include "hal_io.h"
 #include "memory_map.h"
 #include "hal_uart.h"
+#include "hal_io.h"
 #include <stdbool.h>
 #include <stdio.h>
 #include <string.h>
@@ -102,7 +102,7 @@ hal_finish(void)
 
 // %c
 inline int
-fputchar(int ch)
+putchar(int ch)
 {
   hal_gpio_set_rx((s << 8) | W, 0xff80);
   hal_gpio_set_rx(0, 0xff80);
@@ -124,16 +124,29 @@ hal_finish(void)
 
 // %c
 inline int
-fputchar(int ch)
+fputchar(hal_uart_name_t u, int ch)
+{
+  hal_uart_putc(u, ch);
+  return ch;
+}
+
+inline int
+putchar(int ch)
 {
-  hal_uart_putc(ch);
+  hal_uart_putc(DEFAULT_UART, ch);
   return ch;
 }
 
 int
-fgetchar(void)
+fgetchar(hal_uart_name_t u)
+{
+  return hal_uart_getc(u);
+}
+
+int
+getchar(void)
 {
-  return hal_uart_getc();
+  return fgetchar(DEFAULT_UART);
 }
 
 #else	// nop all i/o
@@ -172,34 +185,57 @@ getchar(void)
 
 // \n
 inline void 
-fnewline(void)
+fnewline(hal_uart_name_t u)
 {
-  putchar('\n');
+  fputchar(u, '\n');
+}
+
+inline void
+newline(void)
+{
+  fnewline(DEFAULT_UART);
 }
 
 int
-fputstr(const char *s)
+fputstr(hal_uart_name_t u, const char *s)
 {
   while (*s)
-    putchar(*s++);
+    fputchar(u, *s++);
 
   return 0;
 }
 
 int
-fputs(const char *s)
+putstr(const char *s)
+{
+  return fputstr(DEFAULT_UART, s);
+}
+
+int
+fputs(hal_uart_name_t u, const char *s)
 {
-  putstr(s);
-  putchar('\n');
+  fputstr(u, s);
+  fputchar(u, '\n');
   return 0;
 }
 
+int puts(const char *s)
+{
+  return fputs(DEFAULT_UART, s);
+}
+
 char *
-fgets(char * const s)
+fgets(hal_uart_name_t u, char * const s)
 {
 	char *x = s;
-	while((*x=(char)hal_uart_getc()) != '\n') x++;
+	while((*x=(char)hal_uart_getc(u)) != '\n') x++;
 	*x = 0;
 	return s;
 }
 
+char *
+gets(char * const s)
+{
+  return fgets(DEFAULT_UART, s);
+}
+
diff --git a/firmware/microblaze/lib/hal_io.h b/firmware/microblaze/lib/hal_io.h
index c67d96c62..99f8f7fc9 100644
--- a/firmware/microblaze/lib/hal_io.h
+++ b/firmware/microblaze/lib/hal_io.h
@@ -20,10 +20,12 @@
 #define INCLUDED_HAL_IO_H
 
 #include "memory_map.h"
+#include "hal_uart.h"
 
 void hal_io_init(void);
 void hal_finish();
 char *gets(char * const s);
+int fputstr(hal_uart_name_t u, const char *s);
 
 /*
  * ------------------------------------------------------------------------
diff --git a/firmware/microblaze/lib/hal_uart.c b/firmware/microblaze/lib/hal_uart.c
index 91d67b5e0..6717cd5e8 100644
--- a/firmware/microblaze/lib/hal_uart.c
+++ b/firmware/microblaze/lib/hal_uart.c
@@ -16,93 +16,88 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "memory_map.h"
 #include "hal_uart.h"
 #include "hal_io.h"
-#include "memory_map.h"
-
-// First pass, no interrupts
 
-// Replaced with divisors.py which generates best divisor
-//#define CALC_DIVISOR(rate) (WISHBONE_CLK_RATE / ((rate) * 16))
+//just to save you from going insane, note that firmware/FPGA UARTs [0-2] correspond to serial ports [1-3].
+//so in software, we refer to UART_DEBUG as UART0, but it transmits on pin TXD<1>. see the UART assignments in hal_uart.h.
 
 #define NSPEEDS 6
 #define	MAX_WB_DIV 4
 
+//if you're going to recalculate the divisors, it's just uart_clock_rate / baud_rate.
+//uart_clock_rate is 50MHz for USRP2.
 static const uint16_t
-divisor_table[MAX_WB_DIV+1][NSPEEDS] = {
-  {   2,   2,   2,   2,  2,  2},   // 0: can't happen
-  { 651, 326, 163, 109, 54, 27 },  // 1: 100 MHz
-  { 326, 163,  81,  54, 27, 14 },  // 2:  50 MHz
-  { 217, 109,  54,  36, 18,  9 },  // 3:  33.3333 MHz
-  { 163,  81,  41,  27, 14,  7 },  // 4:  25 MHz
+divisor_table[NSPEEDS] = {
+  5208,	//    9600
+  2604,	//   19200
+  1302,	//   38400
+  868,	//   57600
+  434,	//  115200
+  217	//  230400
 };
 
-//we wrap hal_uart_putc hal_uart_putc_nowait, and hal_uart_getc to accept a UART pointer given by hal_get_uart. we modify hal_io.c to use the new versions.
+static char uart_mode[4] = {
+  [UART_DEBUG] = UART_MODE_ONLCR, 
+  [UART_EXP] = UART_MODE_ONLCR, 
+  [UART_GPS] = UART_MODE_ONLCR
+};
 
-static char uart_mode[4] = {UART_MODE_ONLCR, UART_MODE_ONLCR, UART_MODE_ONLCR, UART_MODE_ONLCR};
+static char uart_speeds[4] = {
+  [UART_DEBUG] = US_230400,
+  [UART_EXP] = US_230400,
+  [UART_GPS] = US_230400
+};
 
 void
-hal_uart_set_mode(int uart, int mode)
+hal_uart_set_mode(hal_uart_name_t uart, int mode)
 {
   uart_mode[uart] = mode;
 }
 
+void hal_uart_set_speed(hal_uart_name_t uart, hal_uart_speed_t speed)
+{
+  uart_regs[uart].clkdiv = divisor_table[speed];
+}
+
 void
 hal_uart_init(void)
 {
-  for(int i = 0; i < 4; i++) {
-  	hal_uart_set_mode(i, UART_MODE_ONLCR);
-    u->clkdiv = 217;  // 230400 bps TODO: change to reflect new quad UART
+  for(int i = 0; i < 2; i++) { //uart 3 is unused
+  	hal_uart_set_mode(i, uart_mode[i]);
+    hal_uart_set_speed(i, uart_speeds[i]);
   }
 }
 
 void
-hal_uart_putc(uart_regs_t *u, int ch)
+hal_uart_putc(hal_uart_name_t u, int ch)
 {
-  if (ch == '\n')// && (uart_mode[uart] == UART_MODE_ONLCR))		//map \n->\r\n if necessary
+  if ((ch == '\n') && (uart_mode[u] == UART_MODE_ONLCR))		//map \n->\r\n if necessary
     hal_uart_putc(u, '\r');
 
-  while (u->txlevel == 0)	 // wait for fifo to have space
+  while (uart_regs[u].txlevel == 0)	 // wait for fifo to have space
     ;
 
-  u->txchar = ch;
+  uart_regs[u].txchar = ch;
 }
 
 void
-hal_uart_putc_nowait(uart_regs_t *u, int ch)
+hal_uart_putc_nowait(hal_uart_name_t u, int ch)
 {
-  if (ch == '\n')// && (uart_mode[uart] == UART_MODE_ONLCR))		//map \n->\r\n if necessary
+  if ((ch == '\n') && (uart_mode[u] == UART_MODE_ONLCR))		//map \n->\r\n if necessary
     hal_uart_putc(u, '\r');
 
-  if(u->txlevel)   // If fifo has space
-    u->txchar = ch;
+  if(uart_regs[u].txlevel)   // If fifo has space
+    uart_regs[u].txchar = ch;
 }
 
 int
-hal_uart_getc(uart_regs_t *u)
+hal_uart_getc(hal_uart_name_t u)
 {
-  while ((u->rxlevel) == 0)  // wait for data to be ready
+  while ((uart_regs[u].rxlevel) == 0)  // wait for data to be ready
     ;
 
-  return u->rxchar;
+  return uart_regs[u].rxchar;
 }
 
-uart_regs_t *
-hal_get_uart(int number)
-{
-  switch(number) {
-  case 0:
-    return uart_regs_0;
-    break;
-  case 1:
-    return uart_regs_1;
-    break;
-  case 2:
-    return uart_regs_2;
-    break;
-  case 3:
-    return uart_regs_3;
-    break;
-  default:
-    return uart_regs_0; //for safety
-}
diff --git a/firmware/microblaze/lib/hal_uart.h b/firmware/microblaze/lib/hal_uart.h
index 218bd7cb4..81f4a6777 100644
--- a/firmware/microblaze/lib/hal_uart.h
+++ b/firmware/microblaze/lib/hal_uart.h
@@ -25,29 +25,37 @@
 #define	UART_MODE_RAW		0x0000	// no mapping on input or output
 #define	UART_MODE_ONLCR	0x0001	// map \n to \r\n on output (default)
 
+#define DEFAULT_UART UART_DEBUG //which UART printf, gets, etc. use
+
+typedef enum {
+  US_9600   = 0,
+  US_19200  = 1,
+  US_38400  = 2,
+  US_57600  = 3,
+  US_115200 = 4,
+  US_230400 = 5
+} hal_uart_speed_t;
+
+typedef struct {
+  hal_uart_speed_t	speed;
+} hal_uart_config_t;
+
+typedef enum {
+  UART_DEBUG = 0,
+  UART_EXP   = 1,
+  UART_GPS   = 2
+} hal_uart_name_t;
+
 /*
  * \brief Set uart mode
  */
-void hal_uart_set_mode(int uart, int flags);
+void hal_uart_set_mode(hal_uart_name_t uart, int flags);
 
 /*!
  * \brief one-time call to init
  */
 void hal_uart_init(void);
 
-typedef enum {
-  US_9600,
-  US_19200,
-  US_38400,
-  US_57600,
-  US_115200,
-  US_230400,
-} hal_uart_speed_t;
-
-typedef struct {
-  hal_uart_speed_t	speed;
-} hal_uart_config_t;
-
 /*!
  * \brief Set uart parameters
  *  Default is 115,200 bps, 8N1.
@@ -62,17 +70,17 @@ void hal_uart_get_config(hal_uart_config_t *c);
 /*!
  * \brief Enqueue \p ch for output over serial port
  */
-void hal_uart_putc(uart_regs_t *u, int ch);
+void hal_uart_putc(hal_uart_name_t u, int ch);
 
 /*!
  * \brief Enqueue \p ch for output over serial port, silent fail if queue is full
  */
-void hal_uart_putc_nowait(uart_regs_t *u, int ch);
+void hal_uart_putc_nowait(hal_uart_name_t u, int ch);
 
 /*
  * \brief Blocking read of next char from serial port
  */
-int hal_uart_getc(uart_regs_t *u);
+int hal_uart_getc(hal_uart_name_t u);
 
 
 #endif /* INCLUDED_HAL_UART_H */
diff --git a/firmware/microblaze/usrp2p/memory_map.h b/firmware/microblaze/usrp2p/memory_map.h
index b69cc59bd..addcf67d4 100644
--- a/firmware/microblaze/usrp2p/memory_map.h
+++ b/firmware/microblaze/usrp2p/memory_map.h
@@ -779,12 +779,10 @@ typedef struct {
   volatile uint32_t rxlevel; // Number of available elements in the FIFO for reads
   volatile uint32_t txchar;  // Write characters to be sent here
   volatile uint32_t rxchar;  // Read received characters here
+  volatile uint32_t x[3]; //padding to reach 32B
 } uart_regs_t;
 
-#define uart_regs_0 ((uart_regs_t *) UART_BASE)
-#define uart_regs_1 ((uart_regs_t *) UART_BASE + 0x0020)
-#define uart_regs_2 ((uart_regs_t *) UART_BASE + 0x0040)
-#define uart_regs_3 ((uart_regs_t *) UART_BASE + 0x0060)
+#define uart_regs ((uart_regs_t *) UART_BASE)
 
 ///////////////////////////////////////////////////
 // ATR Controller, Slave 11
-- 
cgit v1.2.3


From 0019bb05437702a6727d3632c6efc6a600bb4aa2 Mon Sep 17 00:00:00 2001
From: Nick Foster <nick@nerdnetworks.org>
Date: Wed, 25 Aug 2010 18:55:09 -0700
Subject: Change to get codec_impl to compile, dur.

Changed memory map to correspond to new tx_policy code.
---
 firmware/microblaze/usrp2p/memory_map.h |  4 ++--
 host/lib/usrp/usrp2/codec_impl.cpp      | 22 +++++++++++-----------
 2 files changed, 13 insertions(+), 13 deletions(-)

(limited to 'firmware/microblaze/usrp2p/memory_map.h')

diff --git a/firmware/microblaze/usrp2p/memory_map.h b/firmware/microblaze/usrp2p/memory_map.h
index addcf67d4..8d0d0c365 100644
--- a/firmware/microblaze/usrp2p/memory_map.h
+++ b/firmware/microblaze/usrp2p/memory_map.h
@@ -417,12 +417,12 @@ typedef struct {
 // crazy order that matches the labels on the case
 
 #define	LED_A		(1 << 2)
-#define	LED_B		(1 << 5)
+#define	LED_B		(1 << 0)
 #define	LED_E		(1 << 3)
 #define	LED_D		(1 << 1)
 #define	LED_C		(1 << 4)
 //      LED_F		// controlled by CPLD
-#define	LED_RJ45	(1 << 0)
+#define	LED_RJ45	(1 << 5)
 
 #define output_regs ((output_regs_t *) MISC_OUTPUT_BASE)
 
diff --git a/host/lib/usrp/usrp2/codec_impl.cpp b/host/lib/usrp/usrp2/codec_impl.cpp
index f7f9ce2d5..db98e50ab 100644
--- a/host/lib/usrp/usrp2/codec_impl.cpp
+++ b/host/lib/usrp/usrp2/codec_impl.cpp
@@ -53,7 +53,8 @@ void usrp2_mboard_impl::codec_init(void){
 /***********************************************************************
  * RX Codec Properties
  **********************************************************************/
-void usrp2_mboard_impl::rx_codec_get(const wax::obj &key, wax::obj &val){
+void usrp2_mboard_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){
+    named_prop_t key = named_prop_t::extract(key_);
 
     //handle the get request conditioned on the key
     switch(key.as<codec_prop_t>()){
@@ -73,23 +74,21 @@ void usrp2_mboard_impl::rx_codec_get(const wax::obj &key, wax::obj &val){
 
     case CODEC_PROP_GAIN_I:
     case CODEC_PROP_GAIN_Q:
-        assert_has(_codec_rx_gains.keys(), name, "codec rx gain name");
-        val = _codec_rx_gains[name];
+        assert_has(_codec_rx_gains.keys(), key.name, "codec rx gain name");
+        val = _codec_rx_gains[key.name];
         return;
 
     case CODEC_PROP_GAIN_RANGE:
-	assert_has(codec_rx_gain_ranges.keys(), name, "codec rx gain range name");
-	val = codec_rx_gain_ranges[name];
-	return;
+      assert_has(codec_rx_gain_ranges.keys(), key.name, "codec rx gain range name");
+      val = codec_rx_gain_ranges[key.name];
+      return;
 
     default: UHD_THROW_PROP_GET_ERROR();
     }
 }
 
 void usrp2_mboard_impl::rx_codec_set(const wax::obj &key_, const wax::obj &val){
-    wax::obj key; std::string name;
-    boost::tie(key, name) = extract_named_prop(key_);
-
+    named_prop_t key = named_prop_t::extract(key_);
     float gain;
 
   switch(key.as<codec_prop_t>()) {
@@ -98,7 +97,7 @@ void usrp2_mboard_impl::rx_codec_set(const wax::obj &key_, const wax::obj &val){
       if(_iface->get_hw_rev() < USRP2P_FIRST_HW_REV) UHD_THROW_PROP_SET_ERROR();//this capability is only found in USRP2P
 
       gain = val.as<float>();
-      this->rx_codec_set_gain(gain, name);
+      this->rx_codec_set_gain(gain, key.name);
       return;
 
     default:
@@ -134,7 +133,8 @@ void usrp2_mboard_impl::rx_codec_set_gain(float gain, const std::string &name){
 /***********************************************************************
  * TX Codec Properties
  **********************************************************************/
-void usrp2_mboard_impl::tx_codec_get(const wax::obj &key, wax::obj &val){
+void usrp2_mboard_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){
+    named_prop_t key = named_prop_t::extract(key_);
 
     //handle the get request conditioned on the key
     switch(key.as<codec_prop_t>()){
-- 
cgit v1.2.3