From f852876884b9c7954419ef1fe85be03ef91bc73a Mon Sep 17 00:00:00 2001 From: matt Date: Thu, 26 Feb 2009 04:42:33 +0000 Subject: timing fix, delays the ethernet flow control by a cycle to get it across the chip. Seems ok in testing. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10523 221aa14e-8319-0410-a670-987f0aec2ac5 --- eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v') diff --git a/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v b/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v index 0fd7c603e..8da2e253c 100644 --- a/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v +++ b/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v @@ -627,7 +627,15 @@ always @ (posedge Clk or posedge Reset) pause_quanta_sub <=0; // FIXME The below probably won't work if the pause request comes when we are in the wrong state - wire clear_xonxoff = (Current_state==StateSendPauseFrame) & (IPLengthCounter==17); + reg clear_xonxoff; + always @(posedge Clk or posedge Reset) + if(Reset) + clear_xonxoff <= 0; + else if((Current_state==StateSendPauseFrame) & (IPLengthCounter==17)) + clear_xonxoff <= 1; + else if(~xon_gen & ~xoff_gen) + clear_xonxoff <= 0; + always @ (posedge Clk or posedge Reset) if (Reset) xoff_gen_complete <=0; -- cgit v1.2.3