From 61f2f0214c5999ea42a368a4fc99f03d8eb28d1e Mon Sep 17 00:00:00 2001
From: jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5>
Date: Mon, 8 Sep 2008 01:00:12 +0000
Subject: Merged r9433:9527 from features/gr-usrp2 into trunk.  Adds usrp2 and
 gr-usrp2 top-level components.  Trunk passes distcheck with mb-gcc installed,
 but currently not without them.  The key issue is that when mb-gcc is not
 installed, the build system skips over the usrp2/firmware directory, and the
 firmware include files don't get put into the dist tarball.  But we can't do
 the usual DIST_SUBDIRS method as the firmware is a subpackage.

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
---
 eth/demo/verilog/RAMB16_S1_S2.v                  | 1535 ++++++++++++++++++++++
 eth/demo/verilog/demo.ucf                        |   52 +
 eth/demo/verilog/demo.v                          |  378 ++++++
 eth/demo/verilog/demo_packet_descriptor_memory.v |  384 ++++++
 eth/demo/verilog/demo_packet_generator.v         |  274 ++++
 eth/demo/verilog/demo_uart.v                     |  235 ++++
 eth/demo/verilog/demo_wishbone_master.v          |  376 ++++++
 eth/demo/verilog/tb_demo.v                       |  348 +++++
 8 files changed, 3582 insertions(+)
 create mode 100644 eth/demo/verilog/RAMB16_S1_S2.v
 create mode 100644 eth/demo/verilog/demo.ucf
 create mode 100644 eth/demo/verilog/demo.v
 create mode 100644 eth/demo/verilog/demo_packet_descriptor_memory.v
 create mode 100644 eth/demo/verilog/demo_packet_generator.v
 create mode 100644 eth/demo/verilog/demo_uart.v
 create mode 100644 eth/demo/verilog/demo_wishbone_master.v
 create mode 100644 eth/demo/verilog/tb_demo.v

(limited to 'eth/demo/verilog')

diff --git a/eth/demo/verilog/RAMB16_S1_S2.v b/eth/demo/verilog/RAMB16_S1_S2.v
new file mode 100644
index 000000000..758760b95
--- /dev/null
+++ b/eth/demo/verilog/RAMB16_S1_S2.v
@@ -0,0 +1,1535 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1_S2.v,v 1.10 2005/03/14 22:54:41 wloo Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2005 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 8.1i (I.13)
+//  \   \         Description : Xilinx Functional Simulation Library Component
+//  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
+// /___/   /\     Filename : RAMB16_S1_S2.v
+// \   \  /  \    Timestamp : Thu Mar 10 16:43:35 PST 2005
+//  \___\/\___\
+//
+// Revision:
+//    03/23/04 - Initial version.
+// End Revision
+
+`ifdef legacy_model
+
+`timescale  1 ps / 1 ps
+
+module RAMB16_S1_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB);
+
+    parameter INIT_A = 1'h0;
+    parameter INIT_B = 2'h0;
+    parameter SRVAL_A = 1'h0;
+    parameter SRVAL_B = 2'h0;
+    parameter WRITE_MODE_A = "WRITE_FIRST";
+    parameter WRITE_MODE_B = "WRITE_FIRST";
+    parameter SIM_COLLISION_CHECK = "ALL";
+    localparam SETUP_ALL = 1000;
+    localparam SETUP_READ_FIRST = 3000;
+
+    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+    output [0:0] DOA;
+    reg [0:0] doa_out;
+    wire doa_out0;
+
+    input [13:0] ADDRA;
+    input [0:0] DIA;
+    input ENA, CLKA, WEA, SSRA;
+
+    output [1:0] DOB;
+    reg [1:0] dob_out;
+    wire dob_out0, dob_out1;
+
+    input [12:0] ADDRB;
+    input [1:0] DIB;
+    input ENB, CLKB, WEB, SSRB;
+
+    reg [18431:0] mem;
+    reg [8:0] count;
+    reg [1:0] wr_mode_a, wr_mode_b;
+
+    reg [5:0] dmi, dbi;
+    reg [5:0] pmi, pbi;
+
+    wire [13:0] addra_int;
+    reg [13:0] addra_reg;
+    wire [0:0] dia_int;
+    wire ena_int, clka_int, wea_int, ssra_int;
+    reg ena_reg, wea_reg, ssra_reg;
+    wire [12:0] addrb_int;
+    reg [12:0] addrb_reg;
+    wire [1:0] dib_int;
+    wire enb_int, clkb_int, web_int, ssrb_int;
+    reg display_flag;
+    reg enb_reg, web_reg, ssrb_reg;
+
+    time time_clka, time_clkb;
+    time time_clka_clkb;
+    time time_clkb_clka;
+
+    reg setup_all_a_b;
+    reg setup_all_b_a;
+    reg setup_zero;
+    reg setup_rf_a_b;
+    reg setup_rf_b_a;
+    reg [1:0] data_collision, data_collision_a_b, data_collision_b_a;
+    reg memory_collision, memory_collision_a_b, memory_collision_b_a;
+    reg address_collision, address_collision_a_b, address_collision_b_a;
+    reg change_clka;
+    reg change_clkb;
+
+    wire [14:0] data_addra_int;
+    wire [14:0] data_addra_reg;
+    wire [14:0] data_addrb_int;
+    wire [14:0] data_addrb_reg;
+    wire [15:0] parity_addra_int;
+    wire [15:0] parity_addra_reg;
+    wire [15:0] parity_addrb_int;
+    wire [15:0] parity_addrb_reg;
+
+    tri0 GSR = glbl.GSR;
+
+    always @(GSR)
+	if (GSR) begin
+	    assign doa_out = INIT_A[0:0];
+	    assign dob_out = INIT_B[1:0];
+	end
+	else begin
+	    deassign doa_out;
+	    deassign dob_out;
+	end
+
+    buf b_doa_out0 (doa_out0, doa_out[0]);
+    buf b_dob_out0 (dob_out0, dob_out[0]);
+    buf b_dob_out1 (dob_out1, dob_out[1]);
+
+    buf b_doa0 (DOA[0], doa_out0);
+    buf b_dob0 (DOB[0], dob_out0);
+    buf b_dob1 (DOB[1], dob_out1);
+
+    buf b_addra_0 (addra_int[0], ADDRA[0]);
+    buf b_addra_1 (addra_int[1], ADDRA[1]);
+    buf b_addra_2 (addra_int[2], ADDRA[2]);
+    buf b_addra_3 (addra_int[3], ADDRA[3]);
+    buf b_addra_4 (addra_int[4], ADDRA[4]);
+    buf b_addra_5 (addra_int[5], ADDRA[5]);
+    buf b_addra_6 (addra_int[6], ADDRA[6]);
+    buf b_addra_7 (addra_int[7], ADDRA[7]);
+    buf b_addra_8 (addra_int[8], ADDRA[8]);
+    buf b_addra_9 (addra_int[9], ADDRA[9]);
+    buf b_addra_10 (addra_int[10], ADDRA[10]);
+    buf b_addra_11 (addra_int[11], ADDRA[11]);
+    buf b_addra_12 (addra_int[12], ADDRA[12]);
+    buf b_addra_13 (addra_int[13], ADDRA[13]);
+    buf b_dia_0 (dia_int[0], DIA[0]);
+    buf b_ena (ena_int, ENA);
+    buf b_clka (clka_int, CLKA);
+    buf b_ssra (ssra_int, SSRA);
+    buf b_wea (wea_int, WEA);
+    buf b_addrb_0 (addrb_int[0], ADDRB[0]);
+    buf b_addrb_1 (addrb_int[1], ADDRB[1]);
+    buf b_addrb_2 (addrb_int[2], ADDRB[2]);
+    buf b_addrb_3 (addrb_int[3], ADDRB[3]);
+    buf b_addrb_4 (addrb_int[4], ADDRB[4]);
+    buf b_addrb_5 (addrb_int[5], ADDRB[5]);
+    buf b_addrb_6 (addrb_int[6], ADDRB[6]);
+    buf b_addrb_7 (addrb_int[7], ADDRB[7]);
+    buf b_addrb_8 (addrb_int[8], ADDRB[8]);
+    buf b_addrb_9 (addrb_int[9], ADDRB[9]);
+    buf b_addrb_10 (addrb_int[10], ADDRB[10]);
+    buf b_addrb_11 (addrb_int[11], ADDRB[11]);
+    buf b_addrb_12 (addrb_int[12], ADDRB[12]);
+    buf b_dib_0 (dib_int[0], DIB[0]);
+    buf b_dib_1 (dib_int[1], DIB[1]);
+    buf b_enb (enb_int, ENB);
+    buf b_clkb (clkb_int, CLKB);
+    buf b_ssrb (ssrb_int, SSRB);
+    buf b_web (web_int, WEB);
+
+    initial begin
+	for (count = 0; count < 256; count = count + 1) begin
+	    mem[count]		  <= INIT_00[count];
+	    mem[256 * 1 + count]  <= INIT_01[count];
+	    mem[256 * 2 + count]  <= INIT_02[count];
+	    mem[256 * 3 + count]  <= INIT_03[count];
+	    mem[256 * 4 + count]  <= INIT_04[count];
+	    mem[256 * 5 + count]  <= INIT_05[count];
+	    mem[256 * 6 + count]  <= INIT_06[count];
+	    mem[256 * 7 + count]  <= INIT_07[count];
+	    mem[256 * 8 + count]  <= INIT_08[count];
+	    mem[256 * 9 + count]  <= INIT_09[count];
+	    mem[256 * 10 + count] <= INIT_0A[count];
+	    mem[256 * 11 + count] <= INIT_0B[count];
+	    mem[256 * 12 + count] <= INIT_0C[count];
+	    mem[256 * 13 + count] <= INIT_0D[count];
+	    mem[256 * 14 + count] <= INIT_0E[count];
+	    mem[256 * 15 + count] <= INIT_0F[count];
+	    mem[256 * 16 + count] <= INIT_10[count];
+	    mem[256 * 17 + count] <= INIT_11[count];
+	    mem[256 * 18 + count] <= INIT_12[count];
+	    mem[256 * 19 + count] <= INIT_13[count];
+	    mem[256 * 20 + count] <= INIT_14[count];
+	    mem[256 * 21 + count] <= INIT_15[count];
+	    mem[256 * 22 + count] <= INIT_16[count];
+	    mem[256 * 23 + count] <= INIT_17[count];
+	    mem[256 * 24 + count] <= INIT_18[count];
+	    mem[256 * 25 + count] <= INIT_19[count];
+	    mem[256 * 26 + count] <= INIT_1A[count];
+	    mem[256 * 27 + count] <= INIT_1B[count];
+	    mem[256 * 28 + count] <= INIT_1C[count];
+	    mem[256 * 29 + count] <= INIT_1D[count];
+	    mem[256 * 30 + count] <= INIT_1E[count];
+	    mem[256 * 31 + count] <= INIT_1F[count];
+	    mem[256 * 32 + count] <= INIT_20[count];
+	    mem[256 * 33 + count] <= INIT_21[count];
+	    mem[256 * 34 + count] <= INIT_22[count];
+	    mem[256 * 35 + count] <= INIT_23[count];
+	    mem[256 * 36 + count] <= INIT_24[count];
+	    mem[256 * 37 + count] <= INIT_25[count];
+	    mem[256 * 38 + count] <= INIT_26[count];
+	    mem[256 * 39 + count] <= INIT_27[count];
+	    mem[256 * 40 + count] <= INIT_28[count];
+	    mem[256 * 41 + count] <= INIT_29[count];
+	    mem[256 * 42 + count] <= INIT_2A[count];
+	    mem[256 * 43 + count] <= INIT_2B[count];
+	    mem[256 * 44 + count] <= INIT_2C[count];
+	    mem[256 * 45 + count] <= INIT_2D[count];
+	    mem[256 * 46 + count] <= INIT_2E[count];
+	    mem[256 * 47 + count] <= INIT_2F[count];
+	    mem[256 * 48 + count] <= INIT_30[count];
+	    mem[256 * 49 + count] <= INIT_31[count];
+	    mem[256 * 50 + count] <= INIT_32[count];
+	    mem[256 * 51 + count] <= INIT_33[count];
+	    mem[256 * 52 + count] <= INIT_34[count];
+	    mem[256 * 53 + count] <= INIT_35[count];
+	    mem[256 * 54 + count] <= INIT_36[count];
+	    mem[256 * 55 + count] <= INIT_37[count];
+	    mem[256 * 56 + count] <= INIT_38[count];
+	    mem[256 * 57 + count] <= INIT_39[count];
+	    mem[256 * 58 + count] <= INIT_3A[count];
+	    mem[256 * 59 + count] <= INIT_3B[count];
+	    mem[256 * 60 + count] <= INIT_3C[count];
+	    mem[256 * 61 + count] <= INIT_3D[count];
+	    mem[256 * 62 + count] <= INIT_3E[count];
+	    mem[256 * 63 + count] <= INIT_3F[count];
+	end
+	address_collision <= 0;
+	address_collision_a_b <= 0;
+	address_collision_b_a <= 0;
+	change_clka <= 0;
+	change_clkb <= 0;
+	data_collision <= 0;
+	data_collision_a_b <= 0;
+	data_collision_b_a <= 0;
+	memory_collision <= 0;
+	memory_collision_a_b <= 0;
+	memory_collision_b_a <= 0;
+	setup_all_a_b <= 0;
+	setup_all_b_a <= 0;
+	setup_zero <= 0;
+	setup_rf_a_b <= 0;
+	setup_rf_b_a <= 0;
+    end
+
+    assign data_addra_int = addra_int * 1;
+    assign data_addra_reg = addra_reg * 1;
+    assign data_addrb_int = addrb_int * 2;
+    assign data_addrb_reg = addrb_reg * 2;
+
+
+    initial begin
+
+	display_flag = 1;
+
+	case (SIM_COLLISION_CHECK)
+
+	    "NONE" : begin
+		         assign setup_all_a_b = 1'b0;
+	                 assign setup_all_b_a = 1'b0;
+	                 assign setup_zero = 1'b0;
+	                 assign setup_rf_a_b = 1'b0;
+	                 assign setup_rf_b_a = 1'b0;
+	                 assign display_flag = 0;
+	             end
+	    "WARNING_ONLY" : begin
+		                 assign data_collision = 2'b00;
+	                         assign data_collision_a_b = 2'b00;
+	                         assign data_collision_b_a = 2'b00;
+	                         assign memory_collision = 1'b0;
+	                         assign memory_collision_a_b = 1'b0;
+	                         assign memory_collision_b_a = 1'b0;
+	                     end
+	    "GENERATE_X_ONLY" : begin
+		                    assign display_flag = 0;
+	                        end
+	    "ALL" : ;
+	    default : begin
+		          $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S1_S2 instance %m is set to %s.  Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK);
+		          $finish;
+	              end
+
+	endcase // case(SIM_COLLISION_CHECK)
+
+    end // initial begin
+
+
+    always @(posedge clka_int) begin
+	time_clka = $time;
+	#0 time_clkb_clka = time_clka - time_clkb;
+	change_clka = ~change_clka;
+    end
+
+    always @(posedge clkb_int) begin
+	time_clkb = $time;
+	#0 time_clka_clkb = time_clkb - time_clka;
+	change_clkb = ~change_clkb;
+    end
+
+    always @(change_clkb) begin
+	if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL))
+	    setup_all_a_b = 1;
+	if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST))
+	    setup_rf_a_b = 1;
+    end
+
+    always @(change_clka) begin
+	if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL))
+	    setup_all_b_a = 1;
+	if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST))
+	    setup_rf_b_a = 1;
+    end
+
+    always @(change_clkb or change_clka) begin
+	if ((time_clkb_clka == 0) && (time_clka_clkb == 0))
+	    setup_zero = 1;
+    end
+
+    always @(posedge setup_zero) begin
+	if ((ena_int == 1) && (wea_int == 1) &&
+	    (enb_int == 1) && (web_int == 1) &&
+	    (data_addra_int[14:1] == data_addrb_int[14:1]))
+	    memory_collision <= 1;
+    end
+
+    always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin
+	if ((ena_reg == 1) && (wea_reg == 1) &&
+	    (enb_int == 1) && (web_int == 1) &&
+	    (data_addra_reg[14:1] == data_addrb_int[14:1]))
+	    memory_collision_a_b <= 1;
+    end
+
+    always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin
+	if ((ena_int == 1) && (wea_int == 1) &&
+	    (enb_reg == 1) && (web_reg == 1) &&
+	    (data_addra_int[14:1] == data_addrb_reg[14:1]))
+	    memory_collision_b_a <= 1;
+    end
+
+    always @(posedge setup_all_a_b) begin
+	if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin
+	if ((ena_reg == 1) && (enb_int == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
+		6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
+		6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
+		6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
+//		6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+		6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
+		6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
+		6'b101011 : begin display_wa_wb; end
+		6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+//		6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+		6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+		6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+//		6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+		6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+		6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+//		6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+		6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+		6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+//		6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+		6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_all_a_b <= 0;
+    end
+
+
+    always @(posedge setup_all_b_a) begin
+	if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin
+	if ((ena_int == 1) && (enb_reg == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
+		6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
+//		6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
+		6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
+//		6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
+		6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
+		6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
+		6'b101011 : begin display_wa_wb; end
+		6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+		6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+		6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+//		6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+		6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+		6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+		6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_all_b_a <= 0;
+    end
+
+
+    always @(posedge setup_zero) begin
+	if (data_addra_int[14:1] == data_addrb_int[14:1]) begin
+	if ((ena_int == 1) && (enb_int == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_int, web_int})
+		6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end
+		6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end
+		6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end
+		6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end
+		6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end
+		6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end
+		6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end
+		6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end
+		6'b101011 : begin display_wa_wb; end
+		6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end
+//		6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end
+		6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end
+		6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end
+//		6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end
+		6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end
+		6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end
+//		6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end
+		6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end
+		6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end
+		6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end
+		6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end
+//		6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end
+//		6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end
+//		6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end
+		6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end
+		6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end
+		6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_zero <= 0;
+    end
+
+    task display_ra_wb;
+    begin
+	if (display_flag)
+        $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int);
+    end
+    endtask
+
+    task display_wa_rb;
+    begin
+	if (display_flag)
+        $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int);
+    end
+    endtask
+
+    task display_wa_wb;
+    begin
+	if (display_flag)
+        $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int);
+    end
+    endtask
+
+
+    always @(posedge setup_rf_a_b) begin
+	if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin
+	if ((ena_reg == 1) && (enb_int == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
+//		6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+		6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
+		6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
+		6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
+//		6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+		6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+//		6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_rf_a_b <= 0;
+    end
+
+
+    always @(posedge setup_rf_b_a) begin
+	if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin
+	if ((ena_int == 1) && (enb_reg == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
+//		6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
+//		6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+//		6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
+//		6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+//		6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
+//		6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+//		6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+		6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+//		6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+//		6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+		6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+//		6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+//		6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+		6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+//		6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+//		6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_rf_b_a <= 0;
+    end
+
+
+    always @(posedge clka_int) begin
+	addra_reg <= addra_int;
+	ena_reg <= ena_int;
+	ssra_reg <= ssra_int;
+	wea_reg <= wea_int;
+    end
+
+    always @(posedge clkb_int) begin
+	addrb_reg <= addrb_int;
+	enb_reg <= enb_int;
+	ssrb_reg <= ssrb_int;
+	web_reg <= web_int;
+    end
+
+    // Data
+    always @(posedge memory_collision) begin
+	for (dmi = 0; dmi < 1; dmi = dmi + 1) begin
+	    mem[data_addra_int + dmi] <= 1'bX;
+	end
+	memory_collision <= 0;
+    end
+
+    always @(posedge memory_collision_a_b) begin
+	for (dmi = 0; dmi < 1; dmi = dmi + 1) begin
+	    mem[data_addra_reg + dmi] <= 1'bX;
+	end
+	memory_collision_a_b <= 0;
+    end
+
+    always @(posedge memory_collision_b_a) begin
+	for (dmi = 0; dmi < 1; dmi = dmi + 1) begin
+	    mem[data_addra_int + dmi] <= 1'bX;
+	end
+	memory_collision_b_a <= 0;
+    end
+
+    always @(posedge data_collision[1]) begin
+	if (ssra_int == 0) begin
+	    doa_out <= 1'bX;
+	end
+	data_collision[1] <= 0;
+    end
+
+    always @(posedge data_collision[0]) begin
+	if (ssrb_int == 0) begin
+	    for (dbi = 0; dbi < 1; dbi = dbi + 1) begin
+		dob_out[data_addra_int[0 : 0] + dbi] <= 1'bX;
+	    end
+	end
+	data_collision[0] <= 0;
+    end
+
+    always @(posedge data_collision_a_b[1]) begin
+	if (ssra_reg == 0) begin
+	    doa_out <= 1'bX;
+	end
+	data_collision_a_b[1] <= 0;
+    end
+
+    always @(posedge data_collision_a_b[0]) begin
+	if (ssrb_int == 0) begin
+	    for (dbi = 0; dbi < 1; dbi = dbi + 1) begin
+		dob_out[data_addra_reg[0 : 0] + dbi] <= 1'bX;
+	    end
+	end
+	data_collision_a_b[0] <= 0;
+    end
+
+    always @(posedge data_collision_b_a[1]) begin
+	if (ssra_int == 0) begin
+	    doa_out <= 1'bX;
+	end
+	data_collision_b_a[1] <= 0;
+    end
+
+    always @(posedge data_collision_b_a[0]) begin
+	if (ssrb_reg == 0) begin
+	    for (dbi = 0; dbi < 1; dbi = dbi + 1) begin
+		dob_out[data_addra_int[0 : 0] + dbi] <= 1'bX;
+	    end
+	end
+	data_collision_b_a[0] <= 0;
+    end
+
+
+    initial begin
+	case (WRITE_MODE_A)
+	    "WRITE_FIRST" : wr_mode_a <= 2'b00;
+	    "READ_FIRST"  : wr_mode_a <= 2'b01;
+	    "NO_CHANGE"   : wr_mode_a <= 2'b10;
+	    default       : begin
+				$display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S1_S2 instance %m is set to %s.  Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
+				$finish;
+			    end
+	endcase
+    end
+
+    initial begin
+	case (WRITE_MODE_B)
+	    "WRITE_FIRST" : wr_mode_b <= 2'b00;
+	    "READ_FIRST"  : wr_mode_b <= 2'b01;
+	    "NO_CHANGE"   : wr_mode_b <= 2'b10;
+	    default       : begin
+				$display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S1_S2 instance %m is set to %s.  Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
+				$finish;
+			    end
+	endcase
+    end
+
+    // Port A
+    always @(posedge clka_int) begin
+	if (ena_int == 1'b1) begin
+	    if (ssra_int == 1'b1) begin
+		doa_out[0] <= SRVAL_A[0];
+	    end
+	    else begin
+		if (wea_int == 1'b1) begin
+		    if (wr_mode_a == 2'b00) begin
+			doa_out <= dia_int;
+		    end
+		    else if (wr_mode_a == 2'b01) begin
+			doa_out[0] <= mem[data_addra_int + 0];
+		    end
+		end
+		else begin
+		    doa_out[0] <= mem[data_addra_int + 0];
+		end
+	    end
+	end
+    end
+
+    always @(posedge clka_int) begin
+	if (ena_int == 1'b1 && wea_int == 1'b1) begin
+	    mem[data_addra_int + 0] <= dia_int[0];
+	end
+    end
+
+    // Port B
+    always @(posedge clkb_int) begin
+	if (enb_int == 1'b1) begin
+	    if (ssrb_int == 1'b1) begin
+		dob_out[0] <= SRVAL_B[0];
+		dob_out[1] <= SRVAL_B[1];
+	    end
+	    else begin
+		if (web_int == 1'b1) begin
+		    if (wr_mode_b == 2'b00) begin
+			dob_out <= dib_int;
+		    end
+		    else if (wr_mode_b == 2'b01) begin
+			dob_out[0] <= mem[data_addrb_int + 0];
+			dob_out[1] <= mem[data_addrb_int + 1];
+		    end
+		end
+		else begin
+		    dob_out[0] <= mem[data_addrb_int + 0];
+		    dob_out[1] <= mem[data_addrb_int + 1];
+		end
+	    end
+	end
+    end
+
+    always @(posedge clkb_int) begin
+	if (enb_int == 1'b1 && web_int == 1'b1) begin
+	    mem[data_addrb_int + 0] <= dib_int[0];
+	    mem[data_addrb_int + 1] <= dib_int[1];
+	end
+    end
+
+    specify
+	(CLKA *> DOA) = (100, 100);
+	(CLKB *> DOB) = (100, 100);
+    endspecify
+
+endmodule
+
+`else
+
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1_S2.v,v 1.10 2005/03/14 22:54:41 wloo Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2005 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 8.1i (I.13)
+//  \   \         Description : Xilinx Timing Simulation Library Component
+//  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
+// /___/   /\     Filename : RAMB16_S1_S2.v
+// \   \  /  \    Timestamp : Thu Mar 10 16:44:01 PST 2005
+//  \___\/\___\
+//
+// Revision:
+//    03/23/04 - Initial version.
+//    03/10/05 - Initialized outputs.
+// End Revision
+
+`timescale 1 ps/1 ps
+
+module RAMB16_S1_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB);
+
+    parameter INIT_A = 1'h0;
+    parameter INIT_B = 2'h0;
+    parameter SRVAL_A = 1'h0;
+    parameter SRVAL_B = 2'h0;
+    parameter WRITE_MODE_A = "WRITE_FIRST";
+    parameter WRITE_MODE_B = "WRITE_FIRST";
+    parameter SIM_COLLISION_CHECK = "ALL";
+    localparam SETUP_ALL = 1000;
+    localparam SETUP_READ_FIRST = 3000;
+
+    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+    output [0:0] DOA;
+    output [1:0] DOB;
+
+    input [13:0] ADDRA;
+    input [0:0] DIA;
+    input ENA, CLKA, WEA, SSRA;
+    input [12:0] ADDRB;
+    input [1:0] DIB;
+    input ENB, CLKB, WEB, SSRB;
+
+    reg [0:0] doa_out = INIT_A[0:0];
+    reg [1:0] dob_out = INIT_B[1:0];
+    
+    reg [1:0] mem [8191:0];
+    
+    reg [8:0] count, countp;
+    reg [1:0] wr_mode_a, wr_mode_b;
+
+    reg [5:0] dmi, dbi;
+    reg [5:0] pmi, pbi;
+
+    wire [13:0] addra_int;
+    reg [13:0] addra_reg;
+    wire [0:0] dia_int;
+    wire ena_int, clka_int, wea_int, ssra_int;
+    reg ena_reg, wea_reg, ssra_reg;
+    wire [12:0] addrb_int;
+    reg [12:0] addrb_reg;
+    wire [1:0] dib_int;
+    wire enb_int, clkb_int, web_int, ssrb_int;
+    reg display_flag, output_flag;
+    reg enb_reg, web_reg, ssrb_reg;
+
+    time time_clka, time_clkb;
+    time time_clka_clkb;
+    time time_clkb_clka;
+
+    reg setup_all_a_b;
+    reg setup_all_b_a;
+    reg setup_zero;
+    reg setup_rf_a_b;
+    reg setup_rf_b_a;
+    reg [1:0] data_collision, data_collision_a_b, data_collision_b_a;
+    reg memory_collision, memory_collision_a_b, memory_collision_b_a;
+    reg change_clka;
+    reg change_clkb;
+
+    wire [14:0] data_addra_int;
+    wire [14:0] data_addra_reg;
+    wire [14:0] data_addrb_int;
+    wire [14:0] data_addrb_reg;
+
+    wire dia_enable = ena_int && wea_int;
+    wire dib_enable = enb_int && web_int;
+
+    tri0 GSR = glbl.GSR;
+    wire gsr_int;
+
+    buf b_gsr (gsr_int, GSR);
+
+    buf b_doa [0:0] (DOA, doa_out);
+    buf b_addra [13:0] (addra_int, ADDRA);
+    buf b_dia [0:0] (dia_int, DIA);
+    buf b_ena (ena_int, ENA);
+    buf b_clka (clka_int, CLKA);
+    buf b_ssra (ssra_int, SSRA);
+    buf b_wea (wea_int, WEA);
+
+    buf b_dob [1:0] (DOB, dob_out);
+    buf b_addrb [12:0] (addrb_int, ADDRB);
+    buf b_dib [1:0] (dib_int, DIB);
+    buf b_enb (enb_int, ENB);
+    buf b_clkb (clkb_int, CLKB);
+    buf b_ssrb (ssrb_int, SSRB);
+    buf b_web (web_int, WEB);
+
+    
+    always @(gsr_int)
+	if (gsr_int) begin
+	    assign {doa_out} = INIT_A;
+	    assign {dob_out} = INIT_B;
+	end
+	else begin
+	    deassign doa_out;
+	    deassign dob_out;
+	end
+
+    
+    initial begin
+
+	for (count = 0; count < 128; count = count + 1) begin
+	    mem[count]          = INIT_00[(count * 2) +: 2];
+	    mem[128 * 1 + count]  = INIT_01[(count * 2) +: 2];
+	    mem[128 * 2 + count]  = INIT_02[(count * 2) +: 2];
+	    mem[128 * 3 + count]  = INIT_03[(count * 2) +: 2];
+	    mem[128 * 4 + count]  = INIT_04[(count * 2) +: 2];
+	    mem[128 * 5 + count]  = INIT_05[(count * 2) +: 2];
+	    mem[128 * 6 + count]  = INIT_06[(count * 2) +: 2];
+	    mem[128 * 7 + count]  = INIT_07[(count * 2) +: 2];
+	    mem[128 * 8 + count]  = INIT_08[(count * 2) +: 2];
+	    mem[128 * 9 + count]  = INIT_09[(count * 2) +: 2];
+	    mem[128 * 10 + count] = INIT_0A[(count * 2) +: 2];
+	    mem[128 * 11 + count] = INIT_0B[(count * 2) +: 2];
+	    mem[128 * 12 + count] = INIT_0C[(count * 2) +: 2];
+	    mem[128 * 13 + count] = INIT_0D[(count * 2) +: 2];
+	    mem[128 * 14 + count] = INIT_0E[(count * 2) +: 2];
+	    mem[128 * 15 + count] = INIT_0F[(count * 2) +: 2];
+	    mem[128 * 16 + count] = INIT_10[(count * 2) +: 2];
+	    mem[128 * 17 + count] = INIT_11[(count * 2) +: 2];
+	    mem[128 * 18 + count] = INIT_12[(count * 2) +: 2];
+	    mem[128 * 19 + count] = INIT_13[(count * 2) +: 2];
+	    mem[128 * 20 + count] = INIT_14[(count * 2) +: 2];
+	    mem[128 * 21 + count] = INIT_15[(count * 2) +: 2];
+	    mem[128 * 22 + count] = INIT_16[(count * 2) +: 2];
+	    mem[128 * 23 + count] = INIT_17[(count * 2) +: 2];
+	    mem[128 * 24 + count] = INIT_18[(count * 2) +: 2];
+	    mem[128 * 25 + count] = INIT_19[(count * 2) +: 2];
+	    mem[128 * 26 + count] = INIT_1A[(count * 2) +: 2];
+	    mem[128 * 27 + count] = INIT_1B[(count * 2) +: 2];
+	    mem[128 * 28 + count] = INIT_1C[(count * 2) +: 2];
+	    mem[128 * 29 + count] = INIT_1D[(count * 2) +: 2];
+	    mem[128 * 30 + count] = INIT_1E[(count * 2) +: 2];
+	    mem[128 * 31 + count] = INIT_1F[(count * 2) +: 2];
+	    mem[128 * 32 + count] = INIT_20[(count * 2) +: 2];
+	    mem[128 * 33 + count] = INIT_21[(count * 2) +: 2];
+	    mem[128 * 34 + count] = INIT_22[(count * 2) +: 2];
+	    mem[128 * 35 + count] = INIT_23[(count * 2) +: 2];
+	    mem[128 * 36 + count] = INIT_24[(count * 2) +: 2];
+	    mem[128 * 37 + count] = INIT_25[(count * 2) +: 2];
+	    mem[128 * 38 + count] = INIT_26[(count * 2) +: 2];
+	    mem[128 * 39 + count] = INIT_27[(count * 2) +: 2];
+	    mem[128 * 40 + count] = INIT_28[(count * 2) +: 2];
+	    mem[128 * 41 + count] = INIT_29[(count * 2) +: 2];
+	    mem[128 * 42 + count] = INIT_2A[(count * 2) +: 2];
+	    mem[128 * 43 + count] = INIT_2B[(count * 2) +: 2];
+	    mem[128 * 44 + count] = INIT_2C[(count * 2) +: 2];
+	    mem[128 * 45 + count] = INIT_2D[(count * 2) +: 2];
+	    mem[128 * 46 + count] = INIT_2E[(count * 2) +: 2];
+	    mem[128 * 47 + count] = INIT_2F[(count * 2) +: 2];
+	    mem[128 * 48 + count] = INIT_30[(count * 2) +: 2];
+	    mem[128 * 49 + count] = INIT_31[(count * 2) +: 2];
+	    mem[128 * 50 + count] = INIT_32[(count * 2) +: 2];
+	    mem[128 * 51 + count] = INIT_33[(count * 2) +: 2];
+	    mem[128 * 52 + count] = INIT_34[(count * 2) +: 2];
+	    mem[128 * 53 + count] = INIT_35[(count * 2) +: 2];
+	    mem[128 * 54 + count] = INIT_36[(count * 2) +: 2];
+	    mem[128 * 55 + count] = INIT_37[(count * 2) +: 2];
+	    mem[128 * 56 + count] = INIT_38[(count * 2) +: 2];
+	    mem[128 * 57 + count] = INIT_39[(count * 2) +: 2];
+	    mem[128 * 58 + count] = INIT_3A[(count * 2) +: 2];
+	    mem[128 * 59 + count] = INIT_3B[(count * 2) +: 2];
+	    mem[128 * 60 + count] = INIT_3C[(count * 2) +: 2];
+	    mem[128 * 61 + count] = INIT_3D[(count * 2) +: 2];
+	    mem[128 * 62 + count] = INIT_3E[(count * 2) +: 2];
+	    mem[128 * 63 + count] = INIT_3F[(count * 2) +: 2];
+	end
+
+	
+	change_clka <= 0;
+	change_clkb <= 0;
+	data_collision <= 0;
+	data_collision_a_b <= 0;
+	data_collision_b_a <= 0;
+	memory_collision <= 0;
+	memory_collision_a_b <= 0;
+	memory_collision_b_a <= 0;
+	setup_all_a_b <= 0;
+	setup_all_b_a <= 0;
+	setup_zero <= 0;
+	setup_rf_a_b <= 0;
+	setup_rf_b_a <= 0;
+    end
+
+    assign data_addra_int = addra_int * 1;
+    assign data_addra_reg = addra_reg * 1;
+    assign data_addrb_int = addrb_int * 2;
+    assign data_addrb_reg = addrb_reg * 2;
+
+
+    initial begin
+
+	display_flag = 1;
+	output_flag = 1;
+	
+	case (SIM_COLLISION_CHECK)
+
+	    "NONE" : begin
+		         output_flag = 0;
+	                 display_flag = 0;
+	             end
+	    "WARNING_ONLY" : output_flag = 0;
+	    "GENERATE_ONLY" : display_flag = 0;
+	    "ALL" : ;
+
+	    default : begin
+		          $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S1_S2 instance %m is set to %s.  Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_ONLY.", SIM_COLLISION_CHECK);
+		          $finish;
+	              end
+
+	endcase // case(SIM_COLLISION_CHECK)
+
+    end // initial begin
+
+    
+    always @(posedge clka_int) begin
+	if ((output_flag || display_flag)) begin
+	    time_clka = $time;
+	    #0 time_clkb_clka = time_clka - time_clkb;
+	    change_clka = ~change_clka;
+	end
+    end
+    
+    always @(posedge clkb_int) begin
+	if ((output_flag || display_flag)) begin
+	    time_clkb = $time;
+	    #0 time_clka_clkb = time_clkb - time_clka;
+	    change_clkb = ~change_clkb;
+	end
+    end
+    
+    always @(change_clkb) begin
+	if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL))
+	    setup_all_a_b = 1;
+	if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST))
+	    setup_rf_a_b = 1;
+    end
+
+    always @(change_clka) begin
+	if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL))
+	    setup_all_b_a = 1;
+	if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST))
+	    setup_rf_b_a = 1;
+    end
+
+    always @(change_clkb or change_clka) begin
+	if ((time_clkb_clka == 0) && (time_clka_clkb == 0))
+	    setup_zero = 1;
+    end
+
+    always @(posedge setup_zero) begin
+	if ((ena_int == 1) && (wea_int == 1) &&
+	    (enb_int == 1) && (web_int == 1) &&
+	    (data_addra_int[14:1] == data_addrb_int[14:1]))
+	    memory_collision <= 1;
+    end
+
+    always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin
+	if ((ena_reg == 1) && (wea_reg == 1) &&
+	    (enb_int == 1) && (web_int == 1) &&
+	    (data_addra_reg[14:1] == data_addrb_int[14:1]))
+	    memory_collision_a_b <= 1;
+    end
+
+    always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin
+	if ((ena_int == 1) && (wea_int == 1) &&
+	    (enb_reg == 1) && (web_reg == 1) &&
+	    (data_addra_int[14:1] == data_addrb_reg[14:1]))
+	    memory_collision_b_a <= 1;
+    end
+
+    always @(posedge setup_all_a_b) begin
+	if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin
+	if ((ena_reg == 1) && (enb_int == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
+		6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
+		6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
+		6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
+//		6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+		6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
+		6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
+		6'b101011 : begin display_wa_wb; end
+		6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+//		6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+		6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+		6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+//		6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+		6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+		6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+//		6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+		6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+		6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+//		6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+		6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_all_a_b <= 0;
+    end
+
+
+    always @(posedge setup_all_b_a) begin
+	if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin
+	if ((ena_int == 1) && (enb_reg == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
+		6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
+//		6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
+		6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
+//		6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
+		6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
+		6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
+		6'b101011 : begin display_wa_wb; end
+		6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+		6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+		6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+//		6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+		6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+		6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+		6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_all_b_a <= 0;
+    end
+
+
+    always @(posedge setup_zero) begin
+	if (data_addra_int[14:1] == data_addrb_int[14:1]) begin
+	if ((ena_int == 1) && (enb_int == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_int, web_int})
+		6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end
+		6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end
+		6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end
+		6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end
+		6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end
+		6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end
+		6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end
+		6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end
+		6'b101011 : begin display_wa_wb; end
+		6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end
+//		6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end
+		6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end
+		6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end
+//		6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end
+		6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end
+		6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end
+//		6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end
+		6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end
+		6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end
+		6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end
+		6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end
+//		6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end
+//		6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end
+//		6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end
+		6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end
+		6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end
+		6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_zero <= 0;
+    end
+
+    task display_ra_wb;
+    begin
+	if (display_flag)
+        $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int);
+    end
+    endtask
+
+    task display_wa_rb;
+    begin
+	if (display_flag)
+        $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int);
+    end
+    endtask
+
+    task display_wa_wb;
+    begin
+	if (display_flag)
+        $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int);
+    end
+    endtask
+
+
+    always @(posedge setup_rf_a_b) begin
+	if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin
+	if ((ena_reg == 1) && (enb_int == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
+//		6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+		6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
+		6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
+		6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
+//		6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+		6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+//		6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_rf_a_b <= 0;
+    end
+
+
+    always @(posedge setup_rf_b_a) begin
+	if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin
+	if ((ena_int == 1) && (enb_reg == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
+//		6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
+//		6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+//		6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
+//		6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+//		6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
+//		6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+//		6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+		6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+//		6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+//		6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+		6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+//		6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+//		6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+		6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+//		6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+//		6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_rf_b_a <= 0;
+    end
+
+
+    always @(posedge clka_int) begin
+	if ((output_flag || display_flag)) begin
+	    addra_reg <= addra_int;
+	    ena_reg <= ena_int;
+	    ssra_reg <= ssra_int;
+	    wea_reg <= wea_int;
+	end
+    end
+    
+    always @(posedge clkb_int) begin
+	if ((output_flag || display_flag)) begin
+	    addrb_reg <= addrb_int;
+	    enb_reg <= enb_int;
+	    ssrb_reg <= ssrb_int;
+	    web_reg <= web_int;
+	end
+    end
+    
+	    
+    // Data
+    always @(posedge memory_collision) begin
+	if ((output_flag || display_flag)) begin
+	    mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1] <= 1'bx;
+	    memory_collision <= 0;
+	end
+	
+    end
+
+    always @(posedge memory_collision_a_b) begin
+	if ((output_flag || display_flag)) begin
+	    mem[addra_reg[13:1]][addra_reg[0:0] * 1 +: 1] <= 1'bx;
+	    memory_collision_a_b <= 0;
+	end
+    end
+    
+    always @(posedge memory_collision_b_a) begin
+	if ((output_flag || display_flag)) begin
+	    mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1] <= 1'bx;
+	    memory_collision_b_a <= 0;
+	end
+    end
+    
+    always @(posedge data_collision[1]) begin
+	if (ssra_int == 0 && output_flag) begin
+	    doa_out <= #100 1'bX;
+	end
+	data_collision[1] <= 0;
+    end
+
+    always @(posedge data_collision[0]) begin
+	if (ssrb_int == 0 && output_flag) begin
+	    dob_out[addra_int[0:0] * 1 +: 1] <= #100 1'bX;
+	end
+	data_collision[0] <= 0;
+    end
+
+    always @(posedge data_collision_a_b[1]) begin
+	if (ssra_reg == 0 && output_flag) begin
+	    doa_out <= #100 1'bX;
+	end
+	data_collision_a_b[1] <= 0;
+    end
+
+    always @(posedge data_collision_a_b[0]) begin
+	if (ssrb_int == 0 && output_flag) begin
+	    dob_out[addra_reg[0:0] * 1 +: 1] <= #100 1'bX;
+	end
+	data_collision_a_b[0] <= 0;
+    end
+
+    always @(posedge data_collision_b_a[1]) begin
+	if (ssra_int == 0 && output_flag) begin
+	    doa_out <= #100 1'bX;
+	end
+	data_collision_b_a[1] <= 0;
+    end
+
+    always @(posedge data_collision_b_a[0]) begin
+	if (ssrb_reg == 0 && output_flag) begin
+	    dob_out[addra_int[0:0] * 1 +: 1] <= #100 1'bX;
+	end
+	data_collision_b_a[0] <= 0;
+    end
+
+
+    initial begin
+	case (WRITE_MODE_A)
+	    "WRITE_FIRST" : wr_mode_a <= 2'b00;
+	    "READ_FIRST"  : wr_mode_a <= 2'b01;
+	    "NO_CHANGE"   : wr_mode_a <= 2'b10;
+	    default       : begin
+				$display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S1_S2 instance %m is set to %s.  Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
+				$finish;
+			    end
+	endcase
+    end
+
+    initial begin
+	case (WRITE_MODE_B)
+	    "WRITE_FIRST" : wr_mode_b <= 2'b00;
+	    "READ_FIRST"  : wr_mode_b <= 2'b01;
+	    "NO_CHANGE"   : wr_mode_b <= 2'b10;
+	    default       : begin
+				$display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S1_S2 instance %m is set to %s.  Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
+				$finish;
+			    end
+	endcase
+    end
+
+
+    // Port A
+    always @(posedge clka_int) begin
+
+	if (ena_int == 1'b1) begin
+
+	    if (ssra_int == 1'b1) begin
+		{doa_out} <= #100 SRVAL_A;
+	    end
+	    else begin
+		if (wea_int == 1'b1) begin
+		    if (wr_mode_a == 2'b00) begin
+			doa_out <= #100 dia_int;
+		    end
+		    else if (wr_mode_a == 2'b01) begin
+
+			doa_out <= #100 mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1];
+
+		    end
+		end
+		else begin
+
+		    doa_out <= #100 mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1];
+		    
+		end
+	    end
+
+	    // memory
+	    if (wea_int == 1'b1) begin
+		mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1] <= dia_int;
+	    end
+	    
+	end
+    end
+
+
+    // Port B
+    always @(posedge clkb_int) begin
+
+	if (enb_int == 1'b1) begin
+
+	    if (ssrb_int == 1'b1) begin
+		{dob_out} <= #100 SRVAL_B;
+	    end
+	    else begin
+		if (web_int == 1'b1) begin
+		    if (wr_mode_b == 2'b00) begin
+			dob_out <= #100 dib_int;
+		    end
+		    else if (wr_mode_b == 2'b01) begin
+			dob_out <= #100 mem[addrb_int];
+		    end
+		end
+		else begin
+		    dob_out <= #100 mem[addrb_int];
+		end
+	    end
+
+	    // memory
+	    if (web_int == 1'b1) begin
+		mem[addrb_int] <= dib_int;
+	    end
+
+	end
+    end
+
+
+endmodule
+
+`endif
diff --git a/eth/demo/verilog/demo.ucf b/eth/demo/verilog/demo.ucf
new file mode 100644
index 000000000..f3562b46b
--- /dev/null
+++ b/eth/demo/verilog/demo.ucf
@@ -0,0 +1,52 @@
+NET "Reset_n"          LOC = "C15"; // PushButton #4
+NET "Clk_100M"         LOC = "B15";
+NET "Clk_125M"         LOC = "A16"; // GMII only
+
+NET "RS232_TXD"        LOC = "A9";
+NET "RS232_RXD"        LOC = "F1";
+
+NET "USB_TXD"          LOC = "D1";
+NET "USB_RXD"          LOC = "A8";
+
+NET "PHY_RESET_n"      LOC = "E25";
+
+NET "PHY_RXC"          LOC = "B13";
+NET "PHY_RXD<0>"       LOC = "D16";
+NET "PHY_RXD<1>"       LOC = "C16";
+NET "PHY_RXD<2>"       LOC = "D15";
+NET "PHY_RXD<3>"       LOC = "D14";
+NET "PHY_RXD<4>"       LOC = "E14";
+NET "PHY_RXD<5>"       LOC = "F14";
+NET "PHY_RXD<6>"       LOC = "F11";
+NET "PHY_RXD<7>"       LOC = "F12";
+NET "PHY_RXDV"         LOC = "F13";
+NET "PHY_RXER"         LOC = "E13";
+
+NET "PHY_GTX_CLK"      LOC = "C26"; // GMII only
+NET "PHY_TXC"          LOC = "A10";
+NET "PHY_TXD<0>"       LOC = "H26";
+NET "PHY_TXD<1>"       LOC = "H24";
+NET "PHY_TXD<2>"       LOC = "G26";
+NET "PHY_TXD<3>"       LOC = "G24";
+NET "PHY_TXD<4>"       LOC = "F26";
+NET "PHY_TXD<5>"       LOC = "F24";
+NET "PHY_TXD<6>"       LOC = "E26";
+NET "PHY_TXD<7>"       LOC = "E24";
+NET "PHY_TXEN"         LOC = "D26";
+NET "PHY_TXER"         LOC = "D24";
+
+NET "PHY_COL"          LOC = "B24";
+NET "PHY_CRS"          LOC = "D25";
+
+NET "PHY_MDC"          LOC = "G25";
+NET "PHY_MDIO"         LOC = "H25";
+
+NET "LED<1>"           LOC = "D13"; // LED #1-4
+NET "LED<2>"           LOC = "D12";
+NET "LED<3>"           LOC = "C11";
+NET "LED<4>"           LOC = "D11";
+
+NET "Clk_100M" PERIOD = 10.000 ; # 100  MHz
+NET "Clk_125M" PERIOD = 8.000  ; # 125  MHz
+NET "PHY_RXC"  PERIOD = 8.000  ; # 125  MHz
+NET "PHY_TXC"  PERIOD = 8.000  ; # 125  MHz
diff --git a/eth/demo/verilog/demo.v b/eth/demo/verilog/demo.v
new file mode 100644
index 000000000..649903c9a
--- /dev/null
+++ b/eth/demo/verilog/demo.v
@@ -0,0 +1,378 @@
+module demo(
+  Reset_n,
+  Clk_100M,
+  Clk_125M, // GMII only
+
+  RS232_TXD,
+  RS232_RXD,
+
+  USB_TXD,
+  USB_RXD,
+
+  //--- 10/100/1000BASE-T Ethernet PHY (MII/GMII)
+  PHY_RESET_n,
+
+  PHY_RXC,
+  PHY_RXD,
+  PHY_RXDV,
+  PHY_RXER,
+
+  PHY_GTX_CLK, // GMII only
+  PHY_TXC,
+  PHY_TXD,
+  PHY_TXEN,
+  PHY_TXER,
+
+  PHY_COL,
+  PHY_CRS,
+
+  PHY_MDC,
+  PHY_MDIO,
+
+  // Misc. I/Os
+  LED,
+  Button
+);
+
+  input        Reset_n;
+  input        Clk_100M;
+  input        Clk_125M; // GMII
+
+  output       RS232_TXD;
+  input        RS232_RXD;
+
+  output       USB_TXD;
+  input        USB_RXD;
+
+  //--- 10/100/1000BASE-T Ethernet PHY (MII/GMII)
+  output       PHY_RESET_n;
+
+  input        PHY_RXC;
+  input [7:0]  PHY_RXD;
+  input        PHY_RXDV;
+  input        PHY_RXER;
+
+  output       PHY_GTX_CLK; // GMII only
+  input        PHY_TXC;
+  output [7:0] PHY_TXD;
+  output       PHY_TXEN;
+  output       PHY_TXER;
+
+  input        PHY_COL;
+  input        PHY_CRS;
+
+  output       PHY_MDC;
+  inout        PHY_MDIO;
+
+  // Misc. I/Os
+  output [1:4] LED;
+
+  input [1:4]  Button;
+
+  //-------------------------------------------------------------------------
+  // Local declarations
+  //-------------------------------------------------------------------------
+
+  // Rename to "standard" core clock name
+  wire Clk = Clk_100M;
+
+  reg [27:0] Counter;
+  always @( negedge Reset_n or posedge Clk )
+    if ( ~Reset_n )
+      Counter <= 0;
+    else
+      Counter <= Counter + 1;
+
+  assign LED[1:4] = Counter[27:24];
+
+  //-------------------------------------------------------------------------
+  // Instantiation of sub-modules
+  //-------------------------------------------------------------------------
+
+  //--- UART ----------------------------------------------------------------
+
+  wire       UART_RXD;
+  wire       UART_TXD;
+  wire       UART_RxValid;
+  wire [7:0] UART_RxData;
+  wire       UART_TxReady;
+  wire       UART_TxValid;
+  wire [7:0] UART_TxData;
+
+  demo_uart demo_uart(
+    .Reset_n( Reset_n ),
+    .Clk    ( Clk     ),
+
+    // Interface to UART PHY
+    .RXD_i( UART_RXD ),
+    .TXD_o( UART_TXD ),
+
+    // Clk is divided by (Prescaler+1) to generate 16x the bitrate
+`ifdef EHDL_SIMULATION
+    .Prescaler_i( 16'd3 ), // Corresponds to VERY FAST - for simulation only!
+`else                      
+    .Prescaler_i( 16'd650 ), // Corresponds to 9600 baud (assuming 100 MHz clock)
+`endif
+                      
+    // Pulsed when RxData is valid
+    .RxValid_o( UART_RxValid ),
+    .RxData_o ( UART_RxData  ),
+
+    // Asserted when ready for a new Tx byte
+    .TxReady_o( UART_TxReady ),
+
+    // Pulsed when TxData is valid
+    .TxValid_i( UART_TxValid ),
+    .TxData_i ( UART_TxData  )
+  );
+
+  // Transmit & receive in parallel on either RS232 or USB/RS232 interface
+//  assign UART_RXD = RS232_RXD & USB_RXD; // RS232 signals are high when inactive
+  assign     UART_RXD = RS232_RXD;
+
+  assign RS232_TXD = UART_TXD;
+  assign USB_TXD   = UART_TXD;
+
+  //--- UART-to-Wishbone Master ---------------------------------------------
+
+  wire        WB_STB_ETH;
+  wire        WB_STB_PDM;
+  wire        WB_STB_PG;
+  wire        WB_CYC;
+  wire [14:0] WB_ADR;
+  wire        WB_WE;
+  wire [15:0] WB_DAT_Wr;
+  wire [15:0] WB_DAT_Rd;
+  wire        WB_ACK;
+
+  demo_wishbone_master demo_wishbone_master(
+    .Reset_n( Reset_n ),
+    .Clk    ( Clk     ),
+
+    //--- UART interface
+
+    // Pulsed when RxData_i is valid
+    .RxValid_i( UART_RxValid ),
+    .RxData_i ( UART_RxData  ),
+
+    // Asserted when ready for a new Tx byte
+    .TxReady_i( UART_TxReady ),
+
+    // Pulsed when TxData_o is valid
+    .TxValid_o( UART_TxValid ),
+    .TxData_o ( UART_TxData  ),
+
+    //--- Wishbone interface
+    .STB_ETH_O( WB_STB_ETH ),
+    .STB_PDM_O( WB_STB_PDM ),
+    .STB_PG_O ( WB_STB_PG  ),
+    .CYC_O    ( WB_CYC     ),
+    .ADR_O    ( WB_ADR     ),
+    .WE_O     ( WB_WE      ), 
+    .DAT_O    ( WB_DAT_Wr  ),
+    .DAT_I    ( WB_DAT_Rd  ),
+    .ACK_I    ( WB_ACK     )
+  );
+
+  //--- Wishbone clients ----------------------------------------------------
+
+  //--- Packet Descriptor Memory --------------------------------------------
+
+  wire [15:0] WB_DAT_Rd_PDM;
+  wire        WB_ACK_PDM;
+
+  wire        PDM_Rd;
+  wire [13:0] PDM_Addr;
+  wire [31:0] PDM_RdData;
+
+  demo_packet_descriptor_memory demo_packet_descriptor_memory(
+    .Reset_n( Reset_n ),
+    .Clk    ( Clk     ),
+
+    //--- Wishbone interface
+    .STB_I( WB_STB_PDM    ),
+    .CYC_I( WB_CYC        ),
+    .ADR_I( WB_ADR        ),
+    .WE_I ( WB_WE         ), 
+    .DAT_I( WB_DAT_Wr     ),
+    .DAT_O( WB_DAT_Rd_PDM ),
+    .ACK_O( WB_ACK_PDM    ),
+
+    //--- Packet Generator interface
+    // RdData_o is always valid exactly one clock after Addr_i changes
+    // and Rd_i is asserted
+    .Rd_i    ( PDM_Rd     ),
+    .Addr_i  ( PDM_Addr   ),
+    .RdData_o( PDM_RdData )
+  );
+
+  //--- Packet Generator ----------------------------------------------------
+
+  wire [15:0] WB_DAT_Rd_PG;
+  wire        WB_ACK_PG;
+
+  wire        Rx_mac_ra;
+  wire        Rx_mac_rd;
+  wire [31:0] Rx_mac_data;
+  wire [1:0]  Rx_mac_BE;
+  wire        Rx_mac_pa;
+  wire        Rx_mac_sop;
+  wire        Rx_mac_err;
+  wire        Rx_mac_eop;
+
+  wire        Tx_mac_wa;
+  wire        Tx_mac_wr;
+  wire [31:0] Tx_mac_data;
+  wire [1:0]  Tx_mac_BE;
+  wire        Tx_mac_sop;
+  wire        Tx_mac_eop;
+
+  demo_packet_generator demo_packet_generator(
+    .Reset_n( Reset_n ),
+    .Clk    ( Clk     ),
+
+    //--- Wishbone interface
+    .STB_I( WB_STB_PG    ),
+    .CYC_I( WB_CYC       ),
+    .ADR_I( WB_ADR[1:0]  ),
+    .WE_I ( WB_WE        ),
+    .DAT_I( WB_DAT_Wr    ),
+    .DAT_O( WB_DAT_Rd_PG ),
+    .ACK_O( WB_ACK_PG    ),
+
+    //--- Packet Descriptor Memory interface
+    // RdData_i is always valid exactly one clock after Addr_o changes
+    // and Rd_o is asserted
+    .Rd_o    ( PDM_Rd     ),
+    .Addr_o  ( PDM_Addr   ),
+    .RdData_i( PDM_RdData ),
+
+    //--- User (packet) interface
+    .Rx_mac_ra  ( Rx_mac_ra   ),
+    .Rx_mac_rd  ( Rx_mac_rd   ),
+    .Rx_mac_data( Rx_mac_data ),
+    .Rx_mac_BE  ( Rx_mac_BE   ),
+    .Rx_mac_pa  ( Rx_mac_pa   ),
+    .Rx_mac_sop ( Rx_mac_sop  ),
+    .Rx_mac_err ( Rx_mac_err  ),
+    .Rx_mac_eop ( Rx_mac_eop  ),
+
+    .Tx_mac_wa  ( Tx_mac_wa   ),
+    .Tx_mac_wr  ( Tx_mac_wr   ),
+    .Tx_mac_data( Tx_mac_data ),
+    .Tx_mac_BE  ( Tx_mac_BE   ),
+    .Tx_mac_sop ( Tx_mac_sop  ),
+    .Tx_mac_eop ( Tx_mac_eop  )
+  );
+
+  //--- Simple Wishbone client ----------------------------------------------
+
+  reg [15:0] Reg1;
+  reg [15:0] Reg2;
+
+  reg        WB_ACK_Reg;
+  reg [15:0] WB_DAT_Reg;
+
+  always @( negedge Reset_n or posedge Clk )
+    if ( ~Reset_n )
+      begin
+        WB_ACK_Reg <= 0;
+        WB_DAT_Reg <= 'b0;
+
+        Reg1 <= 16'h1234;
+        Reg2 <= 16'hABCD;
+      end
+    else
+      begin
+        WB_ACK_Reg <= 0;
+        if ( WB_CYC & ~( WB_STB_ETH | WB_STB_PG | WB_STB_PDM ) )
+          begin
+            WB_ACK_Reg <= 1;
+            if ( WB_WE )
+              begin
+                if ( WB_ADR[0] )
+                  Reg2 <= WB_DAT_Wr;
+                else
+                  Reg1 <= WB_DAT_Wr;
+              end
+            else
+              begin
+                if ( WB_ADR[0] )
+                  WB_DAT_Reg <= Reg2;
+                else
+                  WB_DAT_Reg <= Reg1;
+              end
+          end
+      end
+
+  //--- DUT - Ethernet Core -------------------------------------------------
+
+  wire [15:0] WB_DAT_Rd_ETH;
+  wire        WB_ACK_ETH;
+
+  wire [2:0] Speed;
+
+  MAC_top dut(
+    // System signals
+    .Clk_125M( Clk_125M ),
+    .Clk_user( Clk      ),
+    .Speed   ( Speed    ),
+
+    // Wishbone compliant core host interface
+    .RST_I( ~Reset_n ),
+    .CLK_I( Clk     ),
+    .STB_I( WB_STB_ETH    ),
+    .CYC_I( WB_CYC        ),
+    .ADR_I( WB_ADR[6:0]   ),
+    .WE_I ( WB_WE         ),
+    .DAT_I( WB_DAT_Wr     ),
+    .DAT_O( WB_DAT_Rd_ETH ),
+    .ACK_O( WB_ACK_ETH    ),
+
+    // User (packet) interface
+    .Rx_mac_ra  ( Rx_mac_ra   ),
+    .Rx_mac_rd  ( Rx_mac_rd   ),
+    .Rx_mac_data( Rx_mac_data ),
+    .Rx_mac_BE  ( Rx_mac_BE   ),
+    .Rx_mac_pa  ( Rx_mac_pa   ),
+    .Rx_mac_sop ( Rx_mac_sop  ),
+    .Rx_mac_err ( Rx_mac_err  ),
+    .Rx_mac_eop ( Rx_mac_eop  ),
+
+    .Tx_mac_wa  ( Tx_mac_wa   ),
+    .Tx_mac_wr  ( Tx_mac_wr   ),
+    .Tx_mac_data( Tx_mac_data ),
+    .Tx_mac_BE  ( Tx_mac_BE   ),
+    .Tx_mac_sop ( Tx_mac_sop  ),
+    .Tx_mac_eop ( Tx_mac_eop  ),
+
+    // PHY interface (GMII/MII)
+    .Gtx_clk( PHY_GTX_CLK  ), // Used only in GMII mode
+    .Rx_clk ( PHY_RXC      ),
+    .Tx_clk ( PHY_TXC      ),  // Used only in MII mode
+    .Tx_er  ( PHY_TXER     ),
+    .Tx_en  ( PHY_TXEN     ),
+    .Txd    ( PHY_TXD      ),
+    .Rx_er  ( PHY_RXER     ),
+    .Rx_dv  ( PHY_RXDV     ),
+    .Rxd    ( PHY_RXD      ),
+    .Crs    ( PHY_CRS      ),
+    .Col    ( PHY_COL      ),
+
+    // MDIO interface (to PHY)
+    .Mdio( PHY_MDIO ),
+    .Mdc ( PHY_MDC  )
+  );
+
+  //--- Combination of Wishbone read data and acknowledge -------------------
+
+  assign WB_DAT_Rd = ({16{WB_ACK_Reg}} & WB_DAT_Reg   ) |
+                     ({16{WB_ACK_PDM}} & WB_DAT_Rd_PDM) |
+                     ({16{WB_ACK_PG }} & WB_DAT_Rd_PG ) |
+                     ({16{WB_ACK_ETH}} & WB_DAT_Rd_ETH);
+
+  assign WB_ACK = WB_ACK_Reg | WB_ACK_PDM | WB_ACK_PG | WB_ACK_ETH;
+
+  assign PHY_RESET_n = Reset_n;                 
+
+endmodule
diff --git a/eth/demo/verilog/demo_packet_descriptor_memory.v b/eth/demo/verilog/demo_packet_descriptor_memory.v
new file mode 100644
index 000000000..a5588a7d1
--- /dev/null
+++ b/eth/demo/verilog/demo_packet_descriptor_memory.v
@@ -0,0 +1,384 @@
+module demo_packet_descriptor_memory(
+  Reset_n,
+  Clk,
+
+  //--- Wishbone interface
+  STB_I,
+  CYC_I,
+  ADR_I,
+  WE_I, 
+  DAT_I,
+  DAT_O,
+  ACK_O,
+
+  //--- Packet Generator interface
+  // RdData_o is always valid exactly one clock after Addr_i changes
+  // and Rd_i is asserted
+  Rd_i,
+  Addr_i,
+  RdData_o
+);
+
+  input         Reset_n;
+  input         Clk;
+
+  //--- Wishbone interface
+  input         STB_I;
+  input         CYC_I;
+  input [14:0]  ADR_I;
+  input         WE_I;
+  input [15:0]  DAT_I;
+  output [15:0] DAT_O;
+  output        ACK_O;
+
+  //--- Packet Generator interface
+  // RdData_o is always valid exactly one clock after Addr_i changes
+  // and Rd_i is asserted
+  input         Rd_i;
+  input [13:0]  Addr_i;
+  output [31:0] RdData_o;
+
+  //-------------------------------------------------------------------------
+  // Local declarations
+  //-------------------------------------------------------------------------
+
+  reg ACK_O;
+
+  //-------------------------------------------------------------------------
+
+  wire [15:0] WrDataA = DAT_I;
+  wire [15:0] RdDataA;
+  wire [31:0] RdDataB;
+
+  assign DAT_O = RdDataA;
+  assign RdData_o = RdDataB;
+
+  wire WB_Access = STB_I & CYC_I;
+  wire WB_AccessClock1;
+  reg  WB_AccessClock2;
+
+  assign WB_AccessClock1 = WB_Access & ~WB_AccessClock2;
+
+  always @( negedge Reset_n or posedge Clk )
+    if ( ~Reset_n )
+      begin
+        WB_AccessClock2 <= 0;
+        ACK_O <= 0;
+      end
+    else
+      begin
+        WB_AccessClock2 <= WB_Access;
+        ACK_O <= WB_AccessClock1;
+      end
+
+  //-------------------------------------------------------------------------
+  // Instantiation of sub-modules
+  //-------------------------------------------------------------------------
+
+  //--- Instantiation of Xilinx 16 Kbit Dual Port Memory --------------------
+
+  RAMB16_S1_S2 RAMB16_S1_S2_bit0 (
+    .DOA( RdDataA[0] ),
+    .DOB( { RdDataB[0], RdDataB[16+0] } ),
+
+    .ADDRA( ADR_I[13:0]     ),
+    .DIA  ( WrDataA[0] ),
+    .ENA  ( WB_AccessClock1 ),
+    .CLKA ( Clk             ),
+    .WEA  ( WE_I            ),
+    .SSRA ( 1'b0            ),
+
+    .ADDRB( Addr_i[12:0] ),
+    .DIB  ( 2'b00        ),
+    .ENB  ( Rd_i         ),
+    .CLKB ( Clk          ),
+    .WEB  ( 1'b0         ),
+    .SSRB ( 1'b0         )
+  );
+
+  RAMB16_S1_S2 RAMB16_S1_S2_bit1 (
+    .DOA( RdDataA[1] ),
+    .DOB( { RdDataB[1], RdDataB[16+1] } ),
+
+    .ADDRA( ADR_I[13:0]     ),
+    .DIA  ( WrDataA[1] ),
+    .ENA  ( WB_AccessClock1 ),
+    .CLKA ( Clk             ),
+    .WEA  ( WE_I            ),
+    .SSRA ( 1'b0            ),
+
+    .ADDRB( Addr_i[12:0] ),
+    .DIB  ( 2'b00        ),
+    .ENB  ( Rd_i         ),
+    .CLKB ( Clk          ),
+    .WEB  ( 1'b0         ),
+    .SSRB ( 1'b0         )
+  );
+
+  RAMB16_S1_S2 RAMB16_S1_S2_bit2 (
+    .DOA( RdDataA[2] ),
+    .DOB( { RdDataB[2], RdDataB[16+2] } ),
+
+    .ADDRA( ADR_I[13:0]     ),
+    .DIA  ( WrDataA[2] ),
+    .ENA  ( WB_AccessClock1 ),
+    .CLKA ( Clk             ),
+    .WEA  ( WE_I            ),
+    .SSRA ( 1'b0            ),
+
+    .ADDRB( Addr_i[12:0] ),
+    .DIB  ( 2'b00        ),
+    .ENB  ( Rd_i         ),
+    .CLKB ( Clk          ),
+    .WEB  ( 1'b0         ),
+    .SSRB ( 1'b0         )
+  );
+
+  RAMB16_S1_S2 RAMB16_S1_S2_bit3 (
+    .DOA( RdDataA[3] ),
+    .DOB( { RdDataB[3], RdDataB[16+3] } ),
+
+    .ADDRA( ADR_I[13:0]     ),
+    .DIA  ( WrDataA[3] ),
+    .ENA  ( WB_AccessClock1 ),
+    .CLKA ( Clk             ),
+    .WEA  ( WE_I            ),
+    .SSRA ( 1'b0            ),
+
+    .ADDRB( Addr_i[12:0] ),
+    .DIB  ( 2'b00        ),
+    .ENB  ( Rd_i         ),
+    .CLKB ( Clk          ),
+    .WEB  ( 1'b0         ),
+    .SSRB ( 1'b0         )
+  );
+
+  RAMB16_S1_S2 RAMB16_S1_S2_bit4 (
+    .DOA( RdDataA[4] ),
+    .DOB( { RdDataB[4], RdDataB[16+4] } ),
+
+    .ADDRA( ADR_I[13:0]     ),
+    .DIA  ( WrDataA[4] ),
+    .ENA  ( WB_AccessClock1 ),
+    .CLKA ( Clk             ),
+    .WEA  ( WE_I            ),
+    .SSRA ( 1'b0            ),
+
+    .ADDRB( Addr_i[12:0] ),
+    .DIB  ( 2'b00        ),
+    .ENB  ( Rd_i         ),
+    .CLKB ( Clk          ),
+    .WEB  ( 1'b0         ),
+    .SSRB ( 1'b0         )
+  );
+
+  RAMB16_S1_S2 RAMB16_S1_S2_bit5 (
+    .DOA( RdDataA[5] ),
+    .DOB( { RdDataB[5], RdDataB[16+5] } ),
+
+    .ADDRA( ADR_I[13:0]     ),
+    .DIA  ( WrDataA[5] ),
+    .ENA  ( WB_AccessClock1 ),
+    .CLKA ( Clk             ),
+    .WEA  ( WE_I            ),
+    .SSRA ( 1'b0            ),
+
+    .ADDRB( Addr_i[12:0] ),
+    .DIB  ( 2'b00        ),
+    .ENB  ( Rd_i         ),
+    .CLKB ( Clk          ),
+    .WEB  ( 1'b0         ),
+    .SSRB ( 1'b0         )
+  );
+
+  RAMB16_S1_S2 RAMB16_S1_S2_bit6 (
+    .DOA( RdDataA[6] ),
+    .DOB( { RdDataB[6], RdDataB[16+6] } ),
+
+    .ADDRA( ADR_I[13:0]     ),
+    .DIA  ( WrDataA[6] ),
+    .ENA  ( WB_AccessClock1 ),
+    .CLKA ( Clk             ),
+    .WEA  ( WE_I            ),
+    .SSRA ( 1'b0            ),
+
+    .ADDRB( Addr_i[12:0] ),
+    .DIB  ( 2'b00        ),
+    .ENB  ( Rd_i         ),
+    .CLKB ( Clk          ),
+    .WEB  ( 1'b0         ),
+    .SSRB ( 1'b0         )
+  );
+
+  RAMB16_S1_S2 RAMB16_S1_S2_bit7 (
+    .DOA( RdDataA[7] ),
+    .DOB( { RdDataB[7], RdDataB[16+7] } ),
+
+    .ADDRA( ADR_I[13:0]     ),
+    .DIA  ( WrDataA[7] ),
+    .ENA  ( WB_AccessClock1 ),
+    .CLKA ( Clk             ),
+    .WEA  ( WE_I            ),
+    .SSRA ( 1'b0            ),
+
+    .ADDRB( Addr_i[12:0] ),
+    .DIB  ( 2'b00        ),
+    .ENB  ( Rd_i         ),
+    .CLKB ( Clk          ),
+    .WEB  ( 1'b0         ),
+    .SSRB ( 1'b0         )
+  );
+
+  RAMB16_S1_S2 RAMB16_S1_S2_bit8 (
+    .DOA( RdDataA[8] ),
+    .DOB( { RdDataB[8], RdDataB[16+8] } ),
+
+    .ADDRA( ADR_I[13:0]     ),
+    .DIA  ( WrDataA[8] ),
+    .ENA  ( WB_AccessClock1 ),
+    .CLKA ( Clk             ),
+    .WEA  ( WE_I            ),
+    .SSRA ( 1'b0            ),
+
+    .ADDRB( Addr_i[12:0] ),
+    .DIB  ( 2'b00        ),
+    .ENB  ( Rd_i         ),
+    .CLKB ( Clk          ),
+    .WEB  ( 1'b0         ),
+    .SSRB ( 1'b0         )
+  );
+
+  RAMB16_S1_S2 RAMB16_S1_S2_bit9 (
+    .DOA( RdDataA[9] ),
+    .DOB( { RdDataB[9], RdDataB[16+9] } ),
+
+    .ADDRA( ADR_I[13:0]     ),
+    .DIA  ( WrDataA[9] ),
+    .ENA  ( WB_AccessClock1 ),
+    .CLKA ( Clk             ),
+    .WEA  ( WE_I            ),
+    .SSRA ( 1'b0            ),
+
+    .ADDRB( Addr_i[12:0] ),
+    .DIB  ( 2'b00        ),
+    .ENB  ( Rd_i         ),
+    .CLKB ( Clk          ),
+    .WEB  ( 1'b0         ),
+    .SSRB ( 1'b0         )
+  );
+
+  RAMB16_S1_S2 RAMB16_S1_S2_bit10 (
+    .DOA( RdDataA[10] ),
+    .DOB( { RdDataB[10], RdDataB[16+10] } ),
+
+    .ADDRA( ADR_I[13:0]     ),
+    .DIA  ( WrDataA[10] ),
+    .ENA  ( WB_AccessClock1 ),
+    .CLKA ( Clk             ),
+    .WEA  ( WE_I            ),
+    .SSRA ( 1'b0            ),
+
+    .ADDRB( Addr_i[12:0] ),
+    .DIB  ( 2'b00        ),
+    .ENB  ( Rd_i         ),
+    .CLKB ( Clk          ),
+    .WEB  ( 1'b0         ),
+    .SSRB ( 1'b0         )
+  );
+
+  RAMB16_S1_S2 RAMB16_S1_S2_bit11 (
+    .DOA( RdDataA[11] ),
+    .DOB( { RdDataB[11], RdDataB[16+11] } ),
+
+    .ADDRA( ADR_I[13:0]     ),
+    .DIA  ( WrDataA[11] ),
+    .ENA  ( WB_AccessClock1 ),
+    .CLKA ( Clk             ),
+    .WEA  ( WE_I            ),
+    .SSRA ( 1'b0            ),
+
+    .ADDRB( Addr_i[12:0] ),
+    .DIB  ( 2'b00        ),
+    .ENB  ( Rd_i         ),
+    .CLKB ( Clk          ),
+    .WEB  ( 1'b0         ),
+    .SSRB ( 1'b0         )
+  );
+
+  RAMB16_S1_S2 RAMB16_S1_S2_bit12 (
+    .DOA( RdDataA[12] ),
+    .DOB( { RdDataB[12], RdDataB[16+12] } ),
+
+    .ADDRA( ADR_I[13:0]     ),
+    .DIA  ( WrDataA[12] ),
+    .ENA  ( WB_AccessClock1 ),
+    .CLKA ( Clk             ),
+    .WEA  ( WE_I            ),
+    .SSRA ( 1'b0            ),
+
+    .ADDRB( Addr_i[12:0] ),
+    .DIB  ( 2'b00        ),
+    .ENB  ( Rd_i         ),
+    .CLKB ( Clk          ),
+    .WEB  ( 1'b0         ),
+    .SSRB ( 1'b0         )
+  );
+
+  RAMB16_S1_S2 RAMB16_S1_S2_bit13 (
+    .DOA( RdDataA[13] ),
+    .DOB( { RdDataB[13], RdDataB[16+13] } ),
+
+    .ADDRA( ADR_I[13:0]     ),
+    .DIA  ( WrDataA[13] ),
+    .ENA  ( WB_AccessClock1 ),
+    .CLKA ( Clk             ),
+    .WEA  ( WE_I            ),
+    .SSRA ( 1'b0            ),
+
+    .ADDRB( Addr_i[12:0] ),
+    .DIB  ( 2'b00        ),
+    .ENB  ( Rd_i         ),
+    .CLKB ( Clk          ),
+    .WEB  ( 1'b0         ),
+    .SSRB ( 1'b0         )
+  );
+
+  RAMB16_S1_S2 RAMB16_S1_S2_bit14 (
+    .DOA( RdDataA[14] ),
+    .DOB( { RdDataB[14], RdDataB[16+14] } ),
+
+    .ADDRA( ADR_I[13:0]     ),
+    .DIA  ( WrDataA[14] ),
+    .ENA  ( WB_AccessClock1 ),
+    .CLKA ( Clk             ),
+    .WEA  ( WE_I            ),
+    .SSRA ( 1'b0            ),
+
+    .ADDRB( Addr_i[12:0] ),
+    .DIB  ( 2'b00        ),
+    .ENB  ( Rd_i         ),
+    .CLKB ( Clk          ),
+    .WEB  ( 1'b0         ),
+    .SSRB ( 1'b0         )
+  );
+
+  RAMB16_S1_S2 RAMB16_S1_S2_bit15 (
+    .DOA( RdDataA[15] ),
+    .DOB( { RdDataB[15], RdDataB[16+15] } ),
+
+    .ADDRA( ADR_I[13:0]     ),
+    .DIA  ( WrDataA[15] ),
+    .ENA  ( WB_AccessClock1 ),
+    .CLKA ( Clk             ),
+    .WEA  ( WE_I            ),
+    .SSRA ( 1'b0            ),
+
+    .ADDRB( Addr_i[12:0] ),
+    .DIB  ( 2'b00        ),
+    .ENB  ( Rd_i         ),
+    .CLKB ( Clk          ),
+    .WEB  ( 1'b0         ),
+    .SSRB ( 1'b0         )
+  );
+
+endmodule
diff --git a/eth/demo/verilog/demo_packet_generator.v b/eth/demo/verilog/demo_packet_generator.v
new file mode 100644
index 000000000..22ad52b4c
--- /dev/null
+++ b/eth/demo/verilog/demo_packet_generator.v
@@ -0,0 +1,274 @@
+module demo_packet_generator(
+  Reset_n,
+  Clk,
+
+  //--- Wishbone interface
+  STB_I,
+  CYC_I,
+  ADR_I,
+  WE_I,
+  DAT_I,
+  DAT_O,
+  ACK_O,
+
+  //--- Packet Descriptor Memory interface
+  // RdData_i is always valid exactly one clock after Addr_o changes
+  // and Rd_o is asserted
+  Rd_o,
+  Addr_o,
+  RdData_i,
+
+  //--- User (packet) interface
+  Rx_mac_ra,
+  Rx_mac_rd,
+  Rx_mac_data,
+  Rx_mac_BE,
+  Rx_mac_pa,
+  Rx_mac_sop,
+  Rx_mac_err,
+  Rx_mac_eop,
+
+  Tx_mac_wa,
+  Tx_mac_wr,
+  Tx_mac_data,
+  Tx_mac_BE,
+  Tx_mac_sop,
+  Tx_mac_eop
+);
+
+  input         Reset_n;
+  input         Clk;
+
+  //--- Wishbone interface
+  input         STB_I;
+  input         CYC_I;
+  input [1:0]   ADR_I;
+  input         WE_I;
+  input [15:0]  DAT_I;
+  output [15:0] DAT_O;
+  output        ACK_O;
+
+  //--- Packet Generator interface
+  // RdData_o is always valid exactly one clock after Addr_o changes
+  // and Rd_o is asserted
+  output        Rd_o;
+  output [13:0] Addr_o;
+  input [31:0]  RdData_i;
+
+  //--- User (packet) interface
+  input         Rx_mac_ra;
+  output        Rx_mac_rd;
+  input [31:0]  Rx_mac_data;
+  input [1:0]   Rx_mac_BE;
+  input         Rx_mac_pa;
+  input         Rx_mac_sop;
+  input         Rx_mac_err;
+  input         Rx_mac_eop;
+
+  input         Tx_mac_wa;
+  output        Tx_mac_wr;
+  output [31:0] Tx_mac_data;
+  output [1:0]  Tx_mac_BE;
+  output        Tx_mac_sop;
+  output        Tx_mac_eop;
+
+  //-------------------------------------------------------------------------
+  // Local declarations
+  //-------------------------------------------------------------------------
+
+  reg        ACK_O;
+  reg [15:0] DAT_O;
+
+  reg        Rd_o;
+  reg        Tx_mac_wr;
+  reg [1:0]  Tx_mac_BE;
+  reg        Tx_mac_sop;
+  reg        Tx_mac_eop;
+
+  //--- Wishbone interface --------------------------------------------------
+
+  reg [1:0] PG_CFG;
+  wire      PG_Enable = PG_CFG[0];
+  
+  always @( negedge Reset_n or posedge Clk )
+    if ( ~Reset_n )
+      begin
+        ACK_O <= 0;
+        DAT_O <= 'b0;
+
+        PG_CFG <= 2'h0;
+      end
+    else
+      begin
+        ACK_O <= 0;
+        if ( CYC_I & STB_I )
+          begin
+            ACK_O <= ~ACK_O; // Generate single cycle pulse!
+            if ( WE_I )
+              begin
+                PG_CFG <= DAT_I;
+              end
+            else
+              begin
+                DAT_O[1:0] <= PG_CFG;
+              end
+          end
+      end
+
+  //--- Packet Generator FSM ------------------------------------------------
+
+  parameter  PG_FSM_STATE_IDLE               = 3'h0;
+  parameter  PG_FSM_STATE_LD_DESC_1          = 3'h1;
+  parameter  PG_FSM_STATE_LD_DESC_2          = 3'h2;
+  parameter  PG_FSM_STATE_RD_HEADER          = 3'h3;
+  parameter  PG_FSM_STATE_PAYLOAD_SEQ_NUMBER = 3'h4;
+  parameter  PG_FSM_STATE_PAYLOAD            = 3'h5;
+  parameter  PG_FSM_STATE_DONE               = 3'h6;
+  reg [2:0]  PG_FSM_State;
+
+  reg [9:0] DescHigh; // Selects currente descriptor
+  reg [3:0] DescLow; // Index into a single descriptor (16 entries)
+
+  reg        PDM_CFG1_LAST;
+  reg [3:0]  PDM_CFG1_REPEAT;
+  reg [3:0]  PDM_CFG1_HDRLEN;
+  reg [15:0] PDM_CFG2_PAYLDLEN;
+
+  reg [31:0] Tx_mac_data_reg;
+  reg        WriteHeader;
+  reg [15:0] PayloadRemaining;
+  reg [31:0] PacketSequenceNumber;
+  reg [31:0] Payload;
+  
+  always @( negedge Reset_n or posedge Clk )
+    if ( ~Reset_n )
+      begin
+        PG_FSM_State <= PG_FSM_STATE_IDLE;
+
+        Rd_o <= 0;
+
+        DescHigh <= 10'b0;
+        DescLow  <= 4'b0;
+
+        Tx_mac_wr  <= 0;
+        Tx_mac_sop <= 0;
+        Tx_mac_eop <= 0;
+        Tx_mac_BE  <= 2'b00;
+
+        Tx_mac_data_reg <= 32'b0;
+        WriteHeader <= 0;
+        PayloadRemaining <= 16'd0;
+
+        PacketSequenceNumber <= 32'd0;
+        Payload <= 32'h0;
+
+        { PDM_CFG1_HDRLEN, PDM_CFG1_REPEAT, PDM_CFG1_LAST, PDM_CFG2_PAYLDLEN } <= 'b0;
+      end
+    else
+      begin
+        casez ( PG_FSM_State )
+          PG_FSM_STATE_IDLE:
+            if ( PG_Enable )
+              begin
+                PG_FSM_State <= PG_FSM_STATE_LD_DESC_1;
+                Rd_o <= 1;
+              end
+            else
+              begin
+                DescHigh <= 10'b0;
+                DescLow  <= 4'b0;
+              end
+
+          PG_FSM_STATE_LD_DESC_1:
+            begin
+              PG_FSM_State <= PG_FSM_STATE_LD_DESC_2;
+
+              DescLow <= DescLow + 1;
+            end
+
+          PG_FSM_STATE_LD_DESC_2:
+            begin
+              PG_FSM_State <= PG_FSM_STATE_RD_HEADER;
+
+              { PDM_CFG1_LAST, PDM_CFG1_REPEAT, PDM_CFG1_HDRLEN, PDM_CFG2_PAYLDLEN } <=
+                { RdData_i[31], RdData_i[23:20], RdData_i[19:16], RdData_i[15:0] };
+            end
+
+          PG_FSM_STATE_RD_HEADER:
+            begin
+              Tx_mac_wr <= 0;
+              if ( Tx_mac_wa )
+                begin
+                  // Space in Tx FIFO - write next header word
+                  DescLow <= DescLow + 1;
+                  Tx_mac_wr <= 1;
+                  Tx_mac_sop <= ( DescLow == 1 ); // Assert SOP on first header word
+                  WriteHeader <= 1;
+                  if ( DescLow == PDM_CFG1_HDRLEN )
+                    begin
+                      // The requested number of header words has been read
+                      // - proceed to generate packet payload
+                      PG_FSM_State <= PG_FSM_STATE_PAYLOAD_SEQ_NUMBER;
+                      PayloadRemaining <= PDM_CFG2_PAYLDLEN;
+                    end
+                end
+            end
+
+          PG_FSM_STATE_PAYLOAD_SEQ_NUMBER:
+            begin
+              WriteHeader <= 0;
+              Tx_mac_data_reg <= PacketSequenceNumber;
+              Tx_mac_wr <= 0;
+              Tx_mac_sop <= 0;
+              if ( Tx_mac_wa )
+                begin
+                  Tx_mac_wr <= 1;
+                  PG_FSM_State <= PG_FSM_STATE_PAYLOAD;
+                  Payload <= 32'h01020304;
+                  PayloadRemaining <= PayloadRemaining - 4;
+                end
+            end
+
+          PG_FSM_STATE_PAYLOAD:
+            begin
+              Tx_mac_data_reg <= Payload;
+              Tx_mac_wr <= 0;
+              if ( Tx_mac_wa )
+                begin
+                  Tx_mac_wr <= 1;
+                  Tx_mac_data_reg <= Payload;
+                  Payload[31:24] <= Payload[31:24] + 8'h04;
+                  Payload[23:16] <= Payload[23:16] + 8'h04;
+                  Payload[15: 8] <= Payload[15: 8] + 8'h04;
+                  Payload[ 7: 0] <= Payload[ 7: 0] + 8'h04;
+                  PayloadRemaining <= PayloadRemaining - 4;
+                  if ( PayloadRemaining <= 4 )
+                    begin
+                      PG_FSM_State <= PG_FSM_STATE_DONE;
+
+                      Tx_mac_eop <= 1;
+                      // Indicate how many bytes are valid in this last transfer
+                      Tx_mac_BE <= PayloadRemaining[1:0];
+                    end
+                end
+            end
+
+          PG_FSM_STATE_DONE:
+            begin
+              // TBD: Add support for REPEAT, NEXT & LAST!
+              Tx_mac_wr <= 0;
+              Tx_mac_eop <= 0;
+            end
+        endcase
+      end
+
+  //-------------------------------------------------------------------------
+
+  assign Tx_mac_data = WriteHeader ?
+                       RdData_i : Tx_mac_data_reg;
+
+  assign Addr_o = { DescHigh, DescLow };
+
+  assign Rx_mac_rd = 0;
+
+endmodule
diff --git a/eth/demo/verilog/demo_uart.v b/eth/demo/verilog/demo_uart.v
new file mode 100644
index 000000000..ba4a3c35c
--- /dev/null
+++ b/eth/demo/verilog/demo_uart.v
@@ -0,0 +1,235 @@
+module demo_uart(
+  Reset_n,
+  Clk,
+
+  // Interface to UART PHY (RS232 level converter)
+  RXD_i,
+  TXD_o,
+
+  // Clk is divided by (Prescaler+1) to generate 16x the bitrate
+  Prescaler_i,
+
+  // Pulsed when RxData is valid
+  RxValid_o,
+  RxData_o,
+
+  // Asserted when ready for a new Tx byte
+  TxReady_o,
+
+  // Pulsed when TxData is valid
+  TxValid_i,
+  TxData_i
+);
+
+  input        Reset_n;
+  input        Clk;
+
+  // Interface to UART PHY (RS232 level converter)
+  input        RXD_i;
+  output       TXD_o;
+
+  // Clk is divided by (Prescaler+1) to generate 16x the bitrate
+  input [15:0] Prescaler_i;
+
+  // Pulsed when RxData is valid
+  output       RxValid_o;
+  output [7:0] RxData_o;
+
+  // Asserted when ready for a new Tx byte
+  output       TxReady_o;
+
+  // Pulsed when TxData is valid
+  input        TxValid_i;
+  input [7:0]  TxData_i;
+
+  //-------------------------------------------------------------------------
+  // Local declarations
+  //-------------------------------------------------------------------------
+
+  reg          TXD_o;
+  reg          RxValid_o;
+  reg [7:0]    RxData_o;
+  reg          TxReady_o;
+
+  //-------------------------------------------------------------------------
+  // Instantiation of sub-modules
+  //-------------------------------------------------------------------------
+
+  //--- Prescaler generating 16x bitrate clock ------------------------------
+
+  reg        Clk_16x;
+  reg [15:0] Prescaler;
+
+  always @( negedge Reset_n or posedge Clk )
+    if ( ~Reset_n )
+      begin
+        Prescaler <= 0;
+        Clk_16x <= 0;
+      end
+    else
+      begin
+        if ( Prescaler == Prescaler_i )
+          begin
+            Prescaler <= 0;
+            Clk_16x <= 1;
+          end
+        else
+          begin
+            Prescaler <= Prescaler + 1;
+            Clk_16x <= 0;
+          end
+      end
+
+  //--- Transmitter logic ---------------------------------------------------
+
+  reg [3:0] TxCounter;
+  reg       TxSendBit;
+
+  always @( negedge Reset_n or posedge Clk )
+    if ( ~Reset_n )
+      begin
+        TxCounter <= 0;
+        TxSendBit <= 0;
+      end
+    else
+      begin
+        TxSendBit <= 0;
+        if ( Clk_16x )
+          begin    
+            if ( TxCounter == 15 )
+              begin
+                TxCounter <= 0;
+                TxSendBit <= 1;
+              end
+            else
+              TxCounter <= TxCounter + 1;
+          end
+      end
+
+  reg [7:0] TxData_reg;
+  reg [3:0] TxBitCnt;
+  always @( negedge Reset_n or posedge Clk )
+    if ( ~Reset_n )
+      begin
+        TXD_o      <= 1;
+        TxReady_o  <= 1;
+        TxData_reg <= 0;
+        TxBitCnt   <= 0;
+      end
+    else
+      begin
+        if ( TxReady_o )
+          begin
+            if ( TxValid_i )
+              begin
+                TxReady_o  <= 0;
+                TxData_reg <= TxData_i;
+                TxBitCnt   <= 0;
+              end
+          end
+        else
+          begin
+            if ( TxSendBit )
+              begin
+                // Only do anything on bit boundaries
+                casez ( TxBitCnt )
+                  0: // Tx START bit
+                    TXD_o <= 0;
+                  10: // Tx second STOP bit
+                    // Now we're done
+                    TxReady_o <= 1;
+                  default: // Tx data bit + first stop bit
+                    begin
+                      TXD_o <= TxData_reg[0];
+                      TxData_reg <= { 1'b1, TxData_reg[7:1] };
+                    end
+                endcase
+                
+                TxBitCnt <= TxBitCnt+1;
+              end
+          end
+      end
+
+  //--- Receiver logic ------------------------------------------------------
+
+  reg       RxHunt;
+  reg [3:0] RxCounter;
+  reg       RxSampleBit;
+  reg       RxDone;
+
+  always @( negedge Reset_n or posedge Clk )
+    if ( ~Reset_n )
+      begin
+        RxCounter   <= 0;
+        RxSampleBit <= 0;
+
+        RxHunt <= 1;
+      end
+    else
+      begin
+        RxSampleBit <= 0;
+
+        if ( RxDone )
+          RxHunt <= 1;
+
+        if ( Clk_16x )
+          begin
+            if ( RxHunt )
+              begin
+                if ( RXD_i == 0 )
+                  begin
+                    // Receiving start bit!
+                    RxHunt <= 0;
+                    // Reset 16x bit counter
+                    RxCounter <= 0;
+                  end
+              end
+            else
+              begin
+                RxCounter <= RxCounter + 1;
+                if ( RxCounter == 7 )
+                  // In middle of Rx bit in next cycle
+                  RxSampleBit <= 1;
+              end
+          end
+      end
+
+  reg [3:0] RxBitCount;
+
+  always @( negedge Reset_n or posedge Clk )
+    if ( ~Reset_n )
+      begin
+        RxValid_o <= 0;
+        RxData_o <= 'b0;
+        RxBitCount <= 0;
+        RxDone <= 0;
+      end
+    else
+      begin
+        RxValid_o <= 0;
+        RxDone <= 0;
+
+        if ( RxSampleBit )
+          begin
+            RxBitCount <= RxBitCount + 1;
+
+            casez ( RxBitCount )
+              0: // START bit - just ignore it
+                ;
+              9: // STOP bit - indicate we're ready again
+                begin
+                  RxDone <= 1;
+                  RxBitCount <= 0;
+                end
+              default: // Rx Data bits
+                begin
+                  RxData_o <= { RXD_i, RxData_o[7:1] };
+                  if ( RxBitCount == 8 )
+                    // Last data bit just received
+                    RxValid_o <= 1;
+                end
+            endcase
+          end
+      end
+
+endmodule
diff --git a/eth/demo/verilog/demo_wishbone_master.v b/eth/demo/verilog/demo_wishbone_master.v
new file mode 100644
index 000000000..b3c64fbcf
--- /dev/null
+++ b/eth/demo/verilog/demo_wishbone_master.v
@@ -0,0 +1,376 @@
+module demo_wishbone_master(
+  Reset_n,
+  Clk,
+
+  //--- UART interface
+
+  // Pulsed when RxData_i is valid
+  RxValid_i,
+  RxData_i,
+
+  // Asserted when ready for a new Tx byte
+  TxReady_i,
+
+  // Pulsed when TxData_o is valid
+  TxValid_o,
+  TxData_o,
+
+  //--- Wishbone interface
+  STB_ETH_O,
+  STB_PDM_O,
+  STB_PG_O,
+  CYC_O,
+  ADR_O,
+  WE_O, 
+  DAT_O,
+  DAT_I,
+  ACK_I
+);
+
+  input         Reset_n;
+  input         Clk;
+
+  //--- UART interface
+
+  // Pulsed when RxData_i is valid
+  input         RxValid_i;
+  input [7:0]   RxData_i;
+
+  // Asserted when ready for a new Tx byte
+  input         TxReady_i;
+
+  // Pulsed when TxData_o is valid
+  output        TxValid_o;
+  output [7:0]  TxData_o;
+
+  output        STB_ETH_O;
+  output        STB_PDM_O;
+  output        STB_PG_O;
+  output        CYC_O;
+  output [14:0] ADR_O;
+  output        WE_O;
+  output [15:0] DAT_O;
+  input [15:0]  DAT_I;
+  input         ACK_I;
+
+  //-------------------------------------------------------------------------
+  // Local declarations
+  //-------------------------------------------------------------------------
+
+  reg          TxValid_o;
+  reg [7:0]    TxData_o;
+  reg          STB_ETH_O;
+  reg          STB_PDM_O;
+  reg          STB_PG_O;
+  reg          CYC_O;
+  reg [14:0]   ADR_O;
+  reg          WE_O;
+  reg [15:0]   DAT_O;
+
+  //-------------------------------------------------------------------------
+  // Instantiation of sub-modules
+  //-------------------------------------------------------------------------
+
+  //--- Transmit FSM --------------------------------------------------------
+
+  parameter    TX_STATE_IDLE  = 0;
+  parameter    TX_STATE_INIT  = 1;
+  parameter    TX_STATE_OK    = 2;
+  parameter    TX_STATE_ERROR = 3;
+  parameter    TX_STATE_VALUE = 4;
+  parameter    TX_STATE_LF    = 5;
+
+  reg [2:0]    TxState;
+  reg [3:0]    TxIndex;
+  reg          TxLast;
+
+  wire [15:0]  TxValue16;
+  wire [3:0]   TxHexDigit;
+  wire [7:0]   TxHexChar;
+  reg          TxOK;
+  reg          TxERROR;
+  reg          TxValue;
+
+  always @( negedge Reset_n or posedge Clk )
+    if ( ~Reset_n )
+      begin
+        TxState   <= TX_STATE_INIT;
+        TxIndex   <= 0;
+        TxLast    <= 0;
+
+        TxValid_o <= 0;
+        TxData_o  <= 'b0;
+      end
+    else
+      begin
+        TxValid_o <= 0;
+
+        // Don't do anything in cycle following TxValid_o being pulsed
+        if ( ~TxValid_o )
+          begin
+            casez ( TxState )
+              TX_STATE_INIT:
+                casez ( TxIndex )
+                  0: TxData_o <= "R";
+                  1: TxData_o <= "E";
+                  2: TxData_o <= "A";
+                  3: TxData_o <= "D";
+                  4: TxData_o <= "Y";
+                  default: TxLast <= 1;
+                endcase
+              
+              TX_STATE_OK:
+                casez ( TxIndex )
+                  0: TxData_o <= "O";
+                  1: TxData_o <= "K";
+                  default: TxLast <= 1;
+                endcase
+
+              TX_STATE_ERROR:
+                casez ( TxIndex )
+                  0: TxData_o <= "E";
+                  1: TxData_o <= "R";
+                  2: TxData_o <= "R";
+                  3: TxData_o <= "O";
+                  4: TxData_o <= "R";
+                  default: TxLast <= 1;
+                endcase
+
+              TX_STATE_VALUE:
+                casez ( TxIndex )
+                  0,1,2,3: TxData_o <= TxHexChar;
+                  default: TxLast <= 1;
+                endcase
+
+              TX_STATE_LF:
+                ;
+
+              default:
+                begin
+                  if ( TxOK )
+                    TxState <= TX_STATE_OK;
+                  else if ( TxERROR )
+                    TxState <= TX_STATE_ERROR;
+                  else if ( TxValue )
+                    begin                         
+                      TxState <= TX_STATE_VALUE;
+                      TxIndex <= 0;
+                    end
+                end
+            endcase
+
+            if ( (TxState != TX_STATE_IDLE) & TxReady_i )
+              begin
+                TxValid_o <= 1;
+
+                if ( TxLast )
+                  begin
+                    if ( TxState == TX_STATE_LF )
+                      begin
+                        TxData_o <= 10; // LF
+                        TxState  <= TX_STATE_IDLE;
+                        TxIndex  <= 0;
+                        TxLast   <= 0;
+                      end
+                    else
+                      begin
+                        TxData_o <= 13; // CR
+                        TxState  <= TX_STATE_LF;
+                      end
+                  end
+                else
+                  TxIndex <= TxIndex + 1;
+              end
+          end
+      end
+
+  assign TxHexDigit = (TxIndex==0) ? TxValue16[15:12] :
+                      (TxIndex==1) ? TxValue16[11: 8] :
+                      (TxIndex==2) ? TxValue16[ 7: 4] :
+                                     TxValue16[ 3: 0];
+
+  assign TxHexChar = (TxHexDigit <= 9) ? (TxHexDigit + "0") :
+                                         (TxHexDigit + "A"-'hA);
+
+  //--- Receive FSM ---------------------------------------------------------
+
+  parameter RX_STATE_IDLE           = 0;
+  parameter RX_STATE_VALUE16_FIRST  = 1;
+  parameter RX_STATE_VALUE16        = 2;
+  parameter RX_STATE_COMMENT        = 3;
+  parameter RX_STATE_CMD            = 4;
+
+  reg [2:0] RxState;
+
+  wire IsWhiteSpace = ( RxData_i==" "  ) |
+                      ( RxData_i=="\t" ) |
+                      ( RxData_i==","  ) |
+                      ( RxData_i==10   ) |
+                      ( RxData_i==13   );
+  wire IsHexDigit = (( RxData_i >= "0" ) & ( RxData_i <= "9" )) |
+                    (( RxData_i >= "a" ) & ( RxData_i <= "f" )) |
+                      (( RxData_i >= "A" ) & ( RxData_i <= "F" ));
+  wire [3:0] RxHexValue =
+               (( RxData_i >= "0" ) & ( RxData_i <= "9" )) ? RxData_i[3:0] :
+               (( RxData_i >= "a" ) & ( RxData_i <= "f" )) ? (RxData_i-"a"+'hA) :
+               (( RxData_i >= "A" ) & ( RxData_i <= "F" )) ? (RxData_i-"A"+'hA) : 0;
+
+  reg [15:0] RxValue16;
+  reg        RxWrite;
+  reg        RxWrData;
+
+  reg [15:0] RegAddr;
+  reg [15:0] RegRdData;
+
+  assign     TxValue16 = RegRdData;
+
+  always @( negedge Reset_n or posedge Clk )
+    if ( ~Reset_n )
+      begin
+        RxState   <= RX_STATE_IDLE;
+
+        RxValue16 <= 16'h0;
+        RxWrite   <= 0;
+        RxWrData  <= 0;
+
+        RegAddr   <= 'b0;
+        RegRdData <= 'b0;
+
+        STB_ETH_O <= 0;
+        STB_PDM_O <= 0;
+        STB_PG_O  <= 0;
+        CYC_O     <= 0;
+        ADR_O     <= 0;
+        WE_O      <= 0;
+        DAT_O     <= 0;
+
+        TxOK      <= 0;
+        TxERROR   <= 0;
+        TxValue   <= 0;
+      end
+    else
+      begin
+        TxOK    <= 0;
+        TxERROR <= 0;
+        TxValue <= 0;
+
+        if ( RxState == RX_STATE_CMD )
+          begin
+            STB_ETH_O <= ( RegAddr[15:12] == 4'h0 );
+            STB_PG_O  <= ( RegAddr[15:12] == 4'h1 );
+            STB_PDM_O <= ( RegAddr[15]    == 1'b1 );
+
+            CYC_O <= 1;
+            ADR_O <= RegAddr[14:0];
+            WE_O  <= RxWrite;
+
+            if ( ACK_I )
+              begin
+                // Register transaction is completing!
+                CYC_O     <= 0;
+                STB_ETH_O <= 0;
+                STB_PDM_O <= 0;
+                STB_PG_O  <= 0;
+
+                // Latch data read in case of a read
+                RegRdData <= DAT_I;
+
+                if ( RxWrite )
+                  // Transaction was a register write
+                  TxOK <= 1;
+                else
+                  TxValue <= 1;
+
+                RxState <= RX_STATE_IDLE;
+              end
+          end
+        else if ( (TxState == TX_STATE_IDLE) & RxValid_i )
+          begin
+            // A byte has been received!
+
+            casez ( RxState )
+              RX_STATE_IDLE:
+                if ( (RxData_i == "w") | (RxData_i == "W") )
+                  begin
+                    // Write Register Command: W rrrr dddd
+                    RxState  <= RX_STATE_VALUE16_FIRST;
+                    RxWrite  <= 1;
+                    RxWrData <= 0;
+                  end
+                else if ( (RxData_i == "r") | (RxData_i == "R") )
+                  begin
+                    // Read Register Command: R rrrr
+                    RxState <= RX_STATE_VALUE16_FIRST;
+                    RxWrite <= 0;
+                  end
+                else if ( RxData_i == "/" )
+                  begin
+                    // Comment!
+                    RxState <= RX_STATE_COMMENT;
+                  end
+                else if ( ~IsWhiteSpace )
+                  // Unknown command!
+                  TxERROR <= 1;
+
+              RX_STATE_COMMENT:
+                if ( (RxData_i == 13) | (RxData_i == 10) )
+                  // CR or LF - end of comment
+                  RxState <= RX_STATE_IDLE;
+
+              RX_STATE_VALUE16_FIRST:
+                if ( IsHexDigit )
+                  begin
+                    RxValue16 <= { 12'b0, RxHexValue };
+                    RxState <= RX_STATE_VALUE16;
+                  end
+                else if ( ~IsWhiteSpace )
+                  begin
+                    // Unexpected character!
+                    TxERROR <= 1;
+                    RxState <= RX_STATE_IDLE;
+                  end
+
+              RX_STATE_VALUE16:
+                if ( IsHexDigit )
+                  RxValue16 <= { RxValue16[11:0], RxHexValue };
+                else if ( IsWhiteSpace )
+                  begin
+                    // Done collecting 16-bit value
+                    if ( RxWrite )
+                      begin
+                        // This is a register write
+                        if ( RxWrData )
+                          begin
+                            // Second time around - just received write data
+                            DAT_O   <= RxValue16;
+                            RxState <= RX_STATE_CMD;
+                          end
+                        else
+                          begin
+                            // Just received register address - expecting second argument
+                            RegAddr <= RxValue16;
+                            RxState <= RX_STATE_VALUE16_FIRST;
+                            RxWrData <= 1; // Now receive the write data
+                          end
+                      end
+                    else
+                      begin
+                        // This is a register read
+                        RegAddr <= RxValue16;
+                        RxState <= RX_STATE_CMD;
+                      end
+                  end
+                else
+                  begin
+                    // Unexpected character!
+                    TxERROR <= 1;
+                    RxState <= RX_STATE_IDLE;
+                  end
+
+              default:
+                TxERROR <= 1;
+            endcase
+          end
+      end
+  
+endmodule
diff --git a/eth/demo/verilog/tb_demo.v b/eth/demo/verilog/tb_demo.v
new file mode 100644
index 000000000..c5a8a3f41
--- /dev/null
+++ b/eth/demo/verilog/tb_demo.v
@@ -0,0 +1,348 @@
+`timescale 1ns / 1ns
+
+module tb_demo;
+
+  //-------------------- Instantiate Xilinx glbl module ----------------------
+  // - this is needed to get ModelSim to work because e.g. I/O buffer models
+  //   refer directly to glbl.GTS and similar signals
+
+  wire GSR;
+  wire GTS;
+  xlnx_glbl glbl( .GSR( GSR ), .GTS( GTS ) );
+
+  reg  VLOG_ExitSignal = 0;
+  reg  Done = 0;
+  reg  Error = 0;
+
+  //-------------------------------------------------------------------------
+
+  reg        Reset_n;
+  reg        Clk_100M;
+  reg        Clk_125M;
+
+  wire       RS232_TXD;
+  wire       RS232_RXD;
+
+  wire       USB_TXD;
+  wire       USB_RXD;
+
+  //--- 10/100/1000BASE-T Ethernet PHY (MII/GMII)
+  wire       PHY_RESET_n;
+
+  wire       PHY_RXC;
+  wire [7:0] PHY_RXD;
+  wire       PHY_RXDV;
+  wire       PHY_RXER;
+
+  wire       PHY_GTX_CLK; // GMII only
+  wire       PHY_TXC;
+  wire [7:0] PHY_TXD;
+  wire       PHY_TXEN;
+  wire       PHY_TXER;
+
+  wire       PHY_COL = 0;
+  wire       PHY_CRS = 0;
+
+  wire       PHY_MDC;
+  wire       PHY_MDIO;
+
+  wire [1:4] LED;
+
+  reg [1:4]  Button = 4'b0000;
+
+  //-------------------------------------------------------------------------
+  // Local declarations
+  //-------------------------------------------------------------------------
+
+  //-------------------------------------------------------------------------
+  // Instantiation of sub-modules
+  //-------------------------------------------------------------------------
+
+  //--- DUT
+
+  demo demo(
+    .Reset_n ( Reset_n  ),
+    .Clk_100M( Clk_100M ),
+    .Clk_125M( Clk_125M ),
+
+    .RS232_TXD( RS232_TXD ),
+    .RS232_RXD( RS232_RXD ),
+
+    .USB_TXD( USB_TXD ),
+    .USB_RXD( USB_RXD ),
+
+    //--- 10/100/1000BASE-T Ethernet PHY (MII/GMII)
+    .PHY_RESET_n( PHY_RESET_n ),
+
+    .PHY_RXC ( PHY_RXC  ),
+    .PHY_RXD ( PHY_RXD  ),
+    .PHY_RXDV( PHY_RXDV ),
+    .PHY_RXER( PHY_RXER ),
+
+    .PHY_GTX_CLK( PHY_GTX_CLK ), // GMII only
+    .PHY_TXC    ( PHY_TXC  ),
+    .PHY_TXD    ( PHY_TXD  ),
+    .PHY_TXEN   ( PHY_TXEN ),
+    .PHY_TXER   ( PHY_TXER ),
+
+    .PHY_COL( PHY_COL ),
+    .PHY_CRS( PHY_CRS ),
+
+    .PHY_MDC ( PHY_MDC  ),
+    .PHY_MDIO( PHY_MDIO ),
+
+    // Misc. I/Os
+    .LED   ( LED    ),
+    .Button( Button )
+  );
+
+  //-------------------------------------------------------------------------
+  // MII/GMII Ethernet PHY model
+
+  reg [2:0]  Speed = 3'b000;
+
+  Phy_sim U_Phy_sim(
+    .Gtx_clk( PHY_GTX_CLK ),
+    .Rx_clk ( PHY_RXC  ),
+    .Tx_clk ( PHY_TXC  ),
+    .Tx_er  ( PHY_TXER ),
+    .Tx_en  ( PHY_TXEN ),
+    .Txd    ( PHY_TXD  ),
+    .Rx_er  ( PHY_RXER ),
+    .Rx_dv  ( PHY_RXDV ),
+    .Rxd    ( PHY_RXD  ),
+    .Crs    ( PHY_CRS  ),
+    .Col    ( PHY_COL  ),
+    .Speed  ( Speed    ),
+    .Done   ( Done     )
+  );
+
+  //-------------------------------------------------------------------------
+  // Generate all clocks & reset
+  //-------------------------------------------------------------------------
+
+  // Core master clock (100 MHz)
+  initial 
+    begin
+      #10;
+      while ( !Done )
+        begin
+          #5 Clk_100M = 0;
+          #5 Clk_100M = 1;
+        end
+    end
+
+  // GMII master clock (125 MHz)
+  initial 
+    begin
+      #10;
+      while ( !Done )
+        begin
+          #4 Clk_125M = 0;
+          #4 Clk_125M = 1;
+        end
+    end
+
+  initial
+    begin
+      Reset_n = 0;
+
+      #103;
+      Reset_n = 1;
+    end
+
+  //--- Emulate UART Transmitter --------------------------------------------
+
+  parameter    PRESCALER_16X = 3;
+  integer      Prescaler;
+  integer      TxLen = 0;
+  reg [2:0]    TxState;
+  integer      TxBit;
+  reg [1023:0] TxMsg;
+  reg          TXD;
+  reg          TxDone;
+
+  always @( negedge Reset_n or posedge Clk_100M )
+    if ( ~Reset_n )
+      begin
+        Prescaler <= 0;
+        TxState   = 0;
+        TXD       = 1;
+        TxBit     = 0;
+        TxDone    <= 0;
+      end
+    else
+      begin
+        TxDone <= 0;
+
+        if ( Prescaler == ((PRESCALER_16X + 1)*16 -1) )
+          Prescaler <= 0;
+        else
+          Prescaler <= Prescaler + 1;
+
+        if ( Prescaler==0 )
+          begin
+            casez ( TxState )
+              0: // IDLE
+                begin
+                  if ( TxLen != 0 )
+                    begin // Send start bit!
+                      TxBit = (TxLen-1)*8;
+                      TxLen = TxLen - 1;
+                      TXD = 0;
+                      TxState = 1;
+                    end
+                end
+
+              1: // Send next data bit
+                begin
+                  // Send next data bit
+                  TXD = TxMsg[ TxBit ];
+                  TxBit = TxBit + 1;
+                  if ( (TxBit % 8)==0 )
+                    // Next send two stop bits
+                    TxState = 2;
+                end
+
+              2: // First of two stop bits
+                begin
+                  TXD = 1;
+                  TxState = 3;
+                end
+
+              3: // Second of two stop bits
+                begin
+                  TXD = 1;
+                  TxState = 0;
+                  if ( TxLen == 0 )
+                    // Done with transmission!
+                    TxDone <= 1;
+                end
+            endcase
+          end
+      end
+
+  assign RS232_RXD = TXD;
+  assign USB_RXD = 1;
+
+  //--- Send commands to the DUT --------------------------------------------
+
+  initial
+    begin
+      #10;
+      while ( ~Reset_n ) #10;
+
+      // Wait a couple of clock edges before continuing to allow
+      // internal logic to get out of reset
+      repeat ( 5 )
+        @( posedge Clk_100M );
+
+      // Wait for the "READY" message to complete transmission
+      #60000;
+
+      // Select 100 Mbps
+      Speed = 3'b010;
+      TxMsg = "W 0022 0002 ";
+      TxLen = 12;
+      while ( ~TxDone )
+        @( posedge Clk_100M );
+
+      #50000;
+
+      TxMsg = "W 8000 8003 ";
+      TxLen = 12;
+      while ( ~TxDone )
+        @( posedge Clk_100M );
+
+      #50000;
+
+      TxMsg = "W 8001 0011 ";
+      TxLen = 12;
+      while ( ~TxDone )
+        @( posedge Clk_100M );
+
+      #50000;
+
+      TxMsg = "W 8002 1234 ";
+      TxLen = 12;
+      while ( ~TxDone )
+        @( posedge Clk_100M );
+
+      #50000;
+
+      TxMsg = "W 8003 5678 ";
+      TxLen = 12;
+      while ( ~TxDone )
+        @( posedge Clk_100M );
+
+      #50000;
+
+      TxMsg = "W 8004 9ABC ";
+      TxLen = 12;
+      while ( ~TxDone )
+        @( posedge Clk_100M );
+
+      #50000;
+
+      TxMsg = "W 8005 DEF0 ";
+      TxLen = 12;
+      while ( ~TxDone )
+        @( posedge Clk_100M );
+
+      #50000;
+
+      TxMsg = "W 8006 C5C0 ";
+      TxLen = 12;
+      while ( ~TxDone )
+        @( posedge Clk_100M );
+
+      #50000;
+
+      TxMsg = "W 8007 BABE ";
+      TxLen = 12;
+      while ( ~TxDone )
+        @( posedge Clk_100M );
+
+      #50000;
+
+      TxMsg = "R 8006 ";
+      TxLen = 7;
+      while ( ~TxDone )
+        @( posedge Clk_100M );
+
+      #50000;
+
+      // Enable PG!
+      TxMsg = "W 1000 0001 ";
+      TxLen = 12;
+      while ( ~TxDone )
+        @( posedge Clk_100M );
+
+      #50000;
+
+      // Read back that PG has been enabled!
+      TxMsg = "R 1000 ";
+      TxLen = 7;
+      while ( ~TxDone )
+        @( posedge Clk_100M );
+
+      #50000;
+
+      #50000;
+
+      Done = 1; #10;
+
+      $stop;
+    end
+
+  //--- Directly accesses a register on the internal Wishbone bus, bypassing the UART interface
+
+  task WrReg;
+    input [15:0] Reg;
+    input [15:0] Data;
+
+    begin
+    end
+  endtask
+
+endmodule
-- 
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