From 9e47bbb499484ae92be6c3c9d96f4df0f73ddcd6 Mon Sep 17 00:00:00 2001
From: matt <matt@221aa14e-8319-0410-a670-987f0aec2ac5>
Date: Thu, 4 Dec 2008 06:12:51 +0000
Subject: speed up the diagnostic signals, they were causing timing problems

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10101 221aa14e-8319-0410-a670-987f0aec2ac5
---
 control_lib/longfifo.v  | 46 +++++++++++++++++++++++++++++++++++++---------
 control_lib/shortfifo.v | 32 ++++++++++++++++++++++++++++----
 2 files changed, 65 insertions(+), 13 deletions(-)

(limited to 'control_lib')

diff --git a/control_lib/longfifo.v b/control_lib/longfifo.v
index c73cc76f8..bf3338e0b 100644
--- a/control_lib/longfifo.v
+++ b/control_lib/longfifo.v
@@ -15,8 +15,8 @@ module longfifo
      input clear,
      output full,
      output empty,
-     output [15:0] space,
-     output [15:0] occupied);
+     output reg [15:0] space,
+     output reg [15:0] occupied);
 
    // Read side states
    localparam 	  EMPTY = 0;
@@ -26,12 +26,6 @@ module longfifo
    reg [SIZE-1:0] wr_addr, rd_addr;
    reg [1:0] 	  read_state;
 
-   wire [SIZE-1:0] fullness = wr_addr - rd_addr;  // Approximate, for simulation only
-   assign occupied = {{16-SIZE{1'b0}},fullness};
-
-   wire [SIZE-1:0] free_space = rd_addr - wr_addr - 2;  // Approximate, for SERDES flow control
-   assign space = {{16-SIZE{1'b0}},free_space};
-	  
    reg 	  empty_reg, full_reg;
    always @(posedge clk)
      if(rst)
@@ -43,7 +37,7 @@ module longfifo
 
    ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE))
      ram (.clka(clk),
-	  .ena(1),
+	  .ena(1'b1),
 	  .wea(write),
 	  .addra(wr_addr),
 	  .dia(datain),
@@ -118,5 +112,39 @@ module longfifo
 
    // assign full = ((rd_addr - 1) == wr_addr);
    assign full = full_reg;
+
+   //////////////////////////////////////////////
+   // space and occupied are for diagnostics only
+   // not guaranteed exact
+
+   localparam NUMLINES = (1<<SIZE)-2;
+   always @(posedge clk)
+     if(rst)
+       space <= NUMLINES;
+     else if(clear)
+       space <= NUMLINES;
+     else if(read & ~write)
+       space <= space + 1;
+     else if(write & ~read)
+       space <= space - 1;
+   
+   always @(posedge clk)
+     if(rst)
+       occupied <= 0;
+     else if(clear)
+       occupied <= 0;
+     else if(read & ~write)
+       occupied <= occupied - 1;
+     else if(write & ~read)
+       occupied <= occupied + 1;
+   
+   /*
+   wire [SIZE-1:0] fullness = wr_addr - rd_addr;  // Approximate, for simulation only
+   assign occupied = {{16-SIZE{1'b0}},fullness};
+
+   wire [SIZE-1:0] free_space = rd_addr - wr_addr - 2;  // Approximate, for SERDES flow control
+   assign space = {{16-SIZE{1'b0}},free_space};
+    */  
+
    
 endmodule // longfifo
diff --git a/control_lib/shortfifo.v b/control_lib/shortfifo.v
index 83d2c1980..d8ce1428e 100644
--- a/control_lib/shortfifo.v
+++ b/control_lib/shortfifo.v
@@ -9,8 +9,8 @@ module shortfifo
      input clear,
      output reg full,
      output reg empty,
-     output [4:0] space,
-     output [4:0] occupied);
+     output reg [4:0] space,
+     output reg [4:0] occupied);
    
    reg [3:0] 	  a;
    genvar 	  i;
@@ -57,7 +57,31 @@ module shortfifo
 
    // NOTE will fail if you write into a full fifo or read from an empty one
 
-   assign space = full ? 0 : empty ? 16 : 15-a;
-   assign occupied = empty ? 0 : full ? 16 : a+1;
+   //////////////////////////////////////////////////////////////
+   // space and occupied are used for diagnostics, not 
+   // guaranteed correct
    
+   //assign space = full ? 0 : empty ? 16 : 15-a;
+   //assign occupied = empty ? 0 : full ? 16 : a+1;
+
+   always @(posedge clk)
+     if(rst)
+       space <= 16;
+     else if(clear)
+       space <= 16;
+     else if(read & ~write)
+       space <= space + 1;
+     else if(write & ~read)
+       space <= space - 1;
+   
+   always @(posedge clk)
+     if(rst)
+       occupied <= 0;
+     else if(clear)
+       occupied <= 0;
+     else if(read & ~write)
+       occupied <= occupied - 1;
+     else if(write & ~read)
+       occupied <= occupied + 1;
+      
 endmodule // shortfifo
-- 
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