From 8b377a9d6d0ad281474a8dbff49ea3b093178b28 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 22 Jan 2010 16:00:45 -0800 Subject: moved into subdir --- control_lib/.gitignore | 5 - control_lib/CRC16_D16.v | 89 - control_lib/SYSCTRL.sav | 24 - control_lib/WB_SIM.sav | 47 - control_lib/atr_controller.v | 57 - control_lib/bin2gray.v | 10 - control_lib/bootrom.mem | 26 - control_lib/clock_bootstrap_rom.v | 34 - control_lib/clock_control.v | 115 - control_lib/clock_control_tb.sav | 28 - control_lib/clock_control_tb.v | 35 - control_lib/cmdfile | 18 - control_lib/dcache.v | 165 - control_lib/decoder_3_8.v | 21 - control_lib/dpram32.v | 82 - control_lib/fifo_tb.v | 151 - control_lib/gray2bin.v | 13 - control_lib/gray_send.v | 29 - control_lib/icache.v | 135 - control_lib/longfifo.v | 150 - control_lib/medfifo.v | 49 - control_lib/mux4.v | 16 - control_lib/mux8.v | 21 - control_lib/mux_32_4.v | 13 - control_lib/newfifo/.gitignore | 1 - control_lib/newfifo/buffer_int.v | 168 - control_lib/newfifo/buffer_int_tb.v | 418 --- control_lib/newfifo/buffer_pool.v | 283 -- control_lib/newfifo/buffer_pool_tb.v | 58 - control_lib/newfifo/fifo19_to_fifo36.v | 76 - control_lib/newfifo/fifo19_to_ll8.v | 53 - control_lib/newfifo/fifo36_to_fifo18.v | 40 - control_lib/newfifo/fifo36_to_fifo19.v | 41 - control_lib/newfifo/fifo36_to_ll8.v | 60 - control_lib/newfifo/fifo_2clock.v | 117 - control_lib/newfifo/fifo_2clock_cascade.v | 35 - control_lib/newfifo/fifo_cascade.v | 52 - control_lib/newfifo/fifo_long.v | 148 - control_lib/newfifo/fifo_new_tb.vcd | 5506 ----------------------------- control_lib/newfifo/fifo_short.v | 95 - control_lib/newfifo/fifo_spec.txt | 36 - control_lib/newfifo/fifo_tb.v | 158 - control_lib/newfifo/ll8_shortfifo.v | 13 - control_lib/newfifo/ll8_to_fifo19.v | 73 - control_lib/newfifo/ll8_to_fifo36.v | 97 - control_lib/nsgpio.v | 107 - control_lib/oneshot_2clk.v | 35 - control_lib/pic.v | 183 - control_lib/priority_enc.v | 44 - control_lib/ram_2port.v | 42 - control_lib/ram_harv_cache.v | 75 - control_lib/ram_loader.v | 225 -- control_lib/ram_wb_harvard.v | 86 - control_lib/reset_sync.v | 16 - control_lib/sd_spi.v | 70 - control_lib/sd_spi_tb.v | 40 - control_lib/sd_spi_wb.v | 76 - control_lib/setting_reg.v | 23 - control_lib/settings_bus.v | 49 - control_lib/shortfifo.v | 87 - control_lib/simple_uart.v | 61 - control_lib/simple_uart_rx.v | 64 - control_lib/simple_uart_tx.v | 60 - control_lib/spi.v | 84 - control_lib/srl.v | 21 - control_lib/ss_rcvr.v | 81 - control_lib/system_control.v | 47 - control_lib/system_control_tb.v | 57 - control_lib/traffic_cop.v | 25 - control_lib/wb_1master.v | 464 --- control_lib/wb_bridge_16_32.v | 36 - control_lib/wb_bus_writer.v | 57 - control_lib/wb_output_pins32.v | 49 - control_lib/wb_ram_block.v | 36 - control_lib/wb_ram_dist.v | 33 - control_lib/wb_readback_mux.v | 60 - control_lib/wb_regfile_2clock.v | 107 - control_lib/wb_semaphore.v | 42 - control_lib/wb_sim.v | 79 - 79 files changed, 11482 deletions(-) delete mode 100644 control_lib/.gitignore delete mode 100644 control_lib/CRC16_D16.v delete mode 100644 control_lib/SYSCTRL.sav delete mode 100644 control_lib/WB_SIM.sav delete mode 100644 control_lib/atr_controller.v delete mode 100644 control_lib/bin2gray.v delete mode 100644 control_lib/bootrom.mem delete mode 100644 control_lib/clock_bootstrap_rom.v delete mode 100644 control_lib/clock_control.v delete mode 100644 control_lib/clock_control_tb.sav delete mode 100644 control_lib/clock_control_tb.v delete mode 100644 control_lib/cmdfile delete mode 100644 control_lib/dcache.v delete mode 100644 control_lib/decoder_3_8.v delete mode 100644 control_lib/dpram32.v delete mode 100644 control_lib/fifo_tb.v delete mode 100644 control_lib/gray2bin.v delete mode 100644 control_lib/gray_send.v delete mode 100644 control_lib/icache.v delete mode 100644 control_lib/longfifo.v delete mode 100644 control_lib/medfifo.v delete mode 100644 control_lib/mux4.v delete mode 100644 control_lib/mux8.v delete mode 100644 control_lib/mux_32_4.v delete mode 100644 control_lib/newfifo/.gitignore delete mode 100644 control_lib/newfifo/buffer_int.v delete mode 100644 control_lib/newfifo/buffer_int_tb.v delete mode 100644 control_lib/newfifo/buffer_pool.v delete mode 100644 control_lib/newfifo/buffer_pool_tb.v delete mode 100644 control_lib/newfifo/fifo19_to_fifo36.v delete mode 100644 control_lib/newfifo/fifo19_to_ll8.v delete mode 100644 control_lib/newfifo/fifo36_to_fifo18.v delete mode 100644 control_lib/newfifo/fifo36_to_fifo19.v delete mode 100644 control_lib/newfifo/fifo36_to_ll8.v delete mode 100644 control_lib/newfifo/fifo_2clock.v delete mode 100644 control_lib/newfifo/fifo_2clock_cascade.v delete mode 100644 control_lib/newfifo/fifo_cascade.v delete mode 100644 control_lib/newfifo/fifo_long.v delete mode 100644 control_lib/newfifo/fifo_new_tb.vcd delete mode 100644 control_lib/newfifo/fifo_short.v delete mode 100644 control_lib/newfifo/fifo_spec.txt delete mode 100644 control_lib/newfifo/fifo_tb.v delete mode 100644 control_lib/newfifo/ll8_shortfifo.v delete mode 100644 control_lib/newfifo/ll8_to_fifo19.v delete mode 100644 control_lib/newfifo/ll8_to_fifo36.v delete mode 100644 control_lib/nsgpio.v delete mode 100644 control_lib/oneshot_2clk.v delete mode 100644 control_lib/pic.v delete mode 100644 control_lib/priority_enc.v delete mode 100644 control_lib/ram_2port.v delete mode 100644 control_lib/ram_harv_cache.v delete mode 100644 control_lib/ram_loader.v delete mode 100644 control_lib/ram_wb_harvard.v delete mode 100644 control_lib/reset_sync.v delete mode 100644 control_lib/sd_spi.v delete mode 100644 control_lib/sd_spi_tb.v delete mode 100644 control_lib/sd_spi_wb.v delete mode 100644 control_lib/setting_reg.v delete mode 100644 control_lib/settings_bus.v delete mode 100644 control_lib/shortfifo.v delete mode 100644 control_lib/simple_uart.v delete mode 100644 control_lib/simple_uart_rx.v delete mode 100644 control_lib/simple_uart_tx.v delete mode 100644 control_lib/spi.v delete mode 100644 control_lib/srl.v delete mode 100644 control_lib/ss_rcvr.v delete mode 100644 control_lib/system_control.v delete mode 100644 control_lib/system_control_tb.v delete mode 100644 control_lib/traffic_cop.v delete mode 100644 control_lib/wb_1master.v delete mode 100644 control_lib/wb_bridge_16_32.v delete mode 100644 control_lib/wb_bus_writer.v delete mode 100644 control_lib/wb_output_pins32.v delete mode 100644 control_lib/wb_ram_block.v delete mode 100644 control_lib/wb_ram_dist.v delete mode 100644 control_lib/wb_readback_mux.v delete mode 100644 control_lib/wb_regfile_2clock.v delete mode 100644 control_lib/wb_semaphore.v delete mode 100644 control_lib/wb_sim.v (limited to 'control_lib') diff --git a/control_lib/.gitignore b/control_lib/.gitignore deleted file mode 100644 index 025385cff..000000000 --- a/control_lib/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -/a.out -/*.vcd -/*.lxt -/*.sav -/*.log diff --git a/control_lib/CRC16_D16.v b/control_lib/CRC16_D16.v deleted file mode 100644 index 7e2816af1..000000000 --- a/control_lib/CRC16_D16.v +++ /dev/null @@ -1,89 +0,0 @@ -/////////////////////////////////////////////////////////////////////// -// File: CRC16_D16.v -// Date: Sun Jun 17 06:42:55 2007 -// -// Copyright (C) 1999-2003 Easics NV. -// This source file may be used and distributed without restriction -// provided that this copyright statement is not removed from the file -// and that any derivative work contains the original copyright notice -// and the associated disclaimer. -// -// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS -// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED -// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. -// -// Purpose: Verilog module containing a synthesizable CRC function -// * polynomial: (0 5 12 16) -// * data width: 16 -// -// Info: tools@easics.be -// http://www.easics.com -/////////////////////////////////////////////////////////////////////// - - -module CRC16_D16 - (input [15:0] Data, - input [15:0] CRC, - output [15:0] NewCRC); - - assign NewCRC = nextCRC16_D16(Data,CRC); - - // polynomial: (0 5 12 16) - // data width: 16 - // convention: the first serial data bit is D[15] - function [15:0] nextCRC16_D16; - - input [15:0] Data; - input [15:0] CRC; - - reg [15:0] D; - reg [15:0] C; - reg [15:0] NewCRC; - - begin - - D = Data; - C = CRC; - - NewCRC[0] = D[12] ^ D[11] ^ D[8] ^ D[4] ^ D[0] ^ C[0] ^ C[4] ^ - C[8] ^ C[11] ^ C[12]; - NewCRC[1] = D[13] ^ D[12] ^ D[9] ^ D[5] ^ D[1] ^ C[1] ^ C[5] ^ - C[9] ^ C[12] ^ C[13]; - NewCRC[2] = D[14] ^ D[13] ^ D[10] ^ D[6] ^ D[2] ^ C[2] ^ C[6] ^ - C[10] ^ C[13] ^ C[14]; - NewCRC[3] = D[15] ^ D[14] ^ D[11] ^ D[7] ^ D[3] ^ C[3] ^ C[7] ^ - C[11] ^ C[14] ^ C[15]; - NewCRC[4] = D[15] ^ D[12] ^ D[8] ^ D[4] ^ C[4] ^ C[8] ^ C[12] ^ - C[15]; - NewCRC[5] = D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[8] ^ D[5] ^ D[4] ^ - D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ - C[13]; - NewCRC[6] = D[14] ^ D[13] ^ D[12] ^ D[10] ^ D[9] ^ D[6] ^ D[5] ^ - D[1] ^ C[1] ^ C[5] ^ C[6] ^ C[9] ^ C[10] ^ C[12] ^ - C[13] ^ C[14]; - NewCRC[7] = D[15] ^ D[14] ^ D[13] ^ D[11] ^ D[10] ^ D[7] ^ D[6] ^ - D[2] ^ C[2] ^ C[6] ^ C[7] ^ C[10] ^ C[11] ^ C[13] ^ - C[14] ^ C[15]; - NewCRC[8] = D[15] ^ D[14] ^ D[12] ^ D[11] ^ D[8] ^ D[7] ^ D[3] ^ - C[3] ^ C[7] ^ C[8] ^ C[11] ^ C[12] ^ C[14] ^ C[15]; - NewCRC[9] = D[15] ^ D[13] ^ D[12] ^ D[9] ^ D[8] ^ D[4] ^ C[4] ^ - C[8] ^ C[9] ^ C[12] ^ C[13] ^ C[15]; - NewCRC[10] = D[14] ^ D[13] ^ D[10] ^ D[9] ^ D[5] ^ C[5] ^ C[9] ^ - C[10] ^ C[13] ^ C[14]; - NewCRC[11] = D[15] ^ D[14] ^ D[11] ^ D[10] ^ D[6] ^ C[6] ^ C[10] ^ - C[11] ^ C[14] ^ C[15]; - NewCRC[12] = D[15] ^ D[8] ^ D[7] ^ D[4] ^ D[0] ^ C[0] ^ C[4] ^ C[7] ^ - C[8] ^ C[15]; - NewCRC[13] = D[9] ^ D[8] ^ D[5] ^ D[1] ^ C[1] ^ C[5] ^ C[8] ^ C[9]; - NewCRC[14] = D[10] ^ D[9] ^ D[6] ^ D[2] ^ C[2] ^ C[6] ^ C[9] ^ C[10]; - NewCRC[15] = D[11] ^ D[10] ^ D[7] ^ D[3] ^ C[3] ^ C[7] ^ C[10] ^ - C[11]; - - nextCRC16_D16 = NewCRC; - - end - - endfunction - -endmodule - diff --git a/control_lib/SYSCTRL.sav b/control_lib/SYSCTRL.sav deleted file mode 100644 index 43bfef10e..000000000 --- a/control_lib/SYSCTRL.sav +++ /dev/null @@ -1,24 +0,0 @@ -[size] 1400 971 -[pos] -1 -1 -*-11.026821 2450 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -system_control_tb.aux_clk -@29 -system_control_tb.clk_fpga -@28 -system_control_tb.dsp_clk -system_control_tb.dsp_rst -system_control_tb.proc_rst -system_control_tb.rl_done -system_control_tb.rl_rst -system_control_tb.wb_clk -system_control_tb.wb_rst -system_control_tb.system_control.POR -@22 -system_control_tb.system_control.POR_ctr[3:0] -@28 -system_control_tb.clock_ready -system_control_tb.system_control.half_clk -system_control_tb.system_control.fin_ret_half -system_control_tb.system_control.fin_ret_aux -system_control_tb.system_control.gate_dsp_clk diff --git a/control_lib/WB_SIM.sav b/control_lib/WB_SIM.sav deleted file mode 100644 index 467cd35ef..000000000 --- a/control_lib/WB_SIM.sav +++ /dev/null @@ -1,47 +0,0 @@ -[size] 1400 971 -[pos] -1 -1 -*-6.099828 350 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -wb_sim.wb_rst -wb_sim.wb_clk -@23 -wb_sim.rom_data[47:0] -@22 -wb_sim.rom_addr[15:0] -@28 -wb_sim.start -wb_sim.wb_ack -@22 -wb_sim.wb_adr[15:0] -@28 -wb_sim.wb_cyc -@22 -wb_sim.wb_dat[31:0] -wb_sim.wb_sel[3:0] -@28 -wb_sim.wb_stb -wb_sim.wb_we -@22 -wb_sim.port_output[31:0] -@28 -wb_sim.system_control.POR -wb_sim.system_control.aux_clk -wb_sim.system_control.clk_fpga -@29 -wb_sim.system_control.done -@28 -wb_sim.system_control.dsp_clk -wb_sim.system_control.fin_del1 -wb_sim.system_control.fin_del2 -wb_sim.system_control.fin_del3 -wb_sim.system_control.fin_ret_aux -@29 -wb_sim.system_control.fin_ret_fpga -@28 -wb_sim.system_control.finished -wb_sim.system_control.reset_out -wb_sim.system_control.start -wb_sim.system_control.started -wb_sim.system_control.wb_clk_o -wb_sim.system_control.wb_rst_o -wb_sim.system_control.wb_rst_o_alt diff --git a/control_lib/atr_controller.v b/control_lib/atr_controller.v deleted file mode 100644 index fed2791f9..000000000 --- a/control_lib/atr_controller.v +++ /dev/null @@ -1,57 +0,0 @@ - -// Automatic transmit/receive switching of control pins to daughterboards -// Store everything in registers for now, but could use a RAM for more -// complex state machines in the future - -module atr_controller - (input clk_i, input rst_i, - input [5:0] adr_i, input [3:0] sel_i, input [31:0] dat_i, output reg [31:0] dat_o, - input we_i, input stb_i, input cyc_i, output reg ack_o, - input run_rx, input run_tx, input [31:0] master_time, - output [31:0] ctrl_lines); - - reg [3:0] state; - reg [31:0] atr_ram [0:15]; // DP distributed RAM - - // WB Interface - always @(posedge clk_i) - if(we_i & stb_i & cyc_i) - begin - if(sel_i[3]) - atr_ram[adr_i[5:2]][31:24] <= dat_i[31:24]; - if(sel_i[2]) - atr_ram[adr_i[5:2]][23:16] <= dat_i[23:16]; - if(sel_i[1]) - atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8]; - if(sel_i[0]) - atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0]; - end // if (we_i & stb_i & cyc_i) - - always @(posedge clk_i) - dat_o <= atr_ram[adr_i[5:2]]; - - always @(posedge clk_i) - ack_o <= stb_i & cyc_i & ~ack_o; - - // Control side of DP RAM - assign ctrl_lines = atr_ram[state]; - - // Put a more complex state machine with time delays and multiple states here - // if daughterboard requires more complex sequencing - localparam ATR_IDLE = 4'd0; - localparam ATR_TX = 4'd1; - localparam ATR_RX = 4'd2; - localparam ATR_FULL_DUPLEX = 4'd3; - - always @(posedge clk_i) - if(rst_i) - state <= ATR_IDLE; - else - case ({run_rx,run_tx}) - 2'b00 : state <= ATR_IDLE; - 2'b01 : state <= ATR_TX; - 2'b10 : state <= ATR_RX; - 2'b11 : state <= ATR_FULL_DUPLEX; - endcase // case({run_rx,run_tx}) - -endmodule // atr_controller diff --git a/control_lib/bin2gray.v b/control_lib/bin2gray.v deleted file mode 100644 index 513402163..000000000 --- a/control_lib/bin2gray.v +++ /dev/null @@ -1,10 +0,0 @@ - - -module bin2gray - #(parameter WIDTH=8) - (input [WIDTH-1:0] bin, - output [WIDTH-1:0] gray); - - assign gray = (bin >> 1) ^ bin; - -endmodule // bin2gray diff --git a/control_lib/bootrom.mem b/control_lib/bootrom.mem deleted file mode 100644 index d688b4342..000000000 --- a/control_lib/bootrom.mem +++ /dev/null @@ -1,26 +0,0 @@ -00000C000F03 -101400000000 - // SPI: Set Divider to div by 2 -// Both clk sel choose ext ref (0), both are enabled (1), turn off SERDES, ADCs, turn on leds -1018_0000_0001 // SPI: Choose AD9510 -1010_0000_3418 // SPI: Auto-slave select, interrupt when done, TX_NEG, 24-bit word -1000_0000_0010 // SPI: AD9510 A:0 D:10 Set up AD9510 SPI -1010_0000_3518 // SPI: SEND IT Auto-slave select, interrupt when done, TX_NEG, 24-bit word -ffff_ffff_ffff // terminate -#// First 16 bits are address, last 32 are data -#// First 4 bits of address select which slave -// 6'd01 : addr_data = {13'h45,8'h00}; // CLK2 drives distribution, everything on -// 6'd02 : addr_data = {13'h3D,8'h80}; // Turn on output 1, normal levels -// 6'd03 : addr_data = {13'h4B,8'h80}; // Bypass divider 1 (div by 1) -// 6'd04 : addr_data = {13'h08,8'h47}; // POS PFD, Dig LK Det, Charge Pump normal -// 6'd05 : addr_data = {13'h09,8'h70}; // Max Charge Pump current -// 6'd06 : addr_data = {13'h0A,8'h04}; // Normal operation, Prescalar Div by 2, PLL On -// 6'd07 : addr_data = {13'h0B,8'h00}; // RDIV MSB (6 bits) -// 6'd08 : addr_data = {13'h0C,8'h01}; // RDIV LSB (8 bits), Div by 1 -// 6'd09 : addr_data = {13'h0D,8'h00}; // Everything normal, Dig Lock Det -// 6'd10 : addr_data = {13'h07,8'h00}; // Disable LOR detect - LOR causes failure... -// 6'd11 : addr_data = {13'h04,8'h00}; // A Counter = Don't Care -// 6'd12 : addr_data = {13'h05,8'h00}; // B Counter MSB = 0 -// 6'd13 : addr_data = {13'h06,8'h05}; // B Counter LSB = 5 - // default : addr_data = {13'h5A,8'h01}; // Register Update -// @ 55 // Jump to new address 8'h55 diff --git a/control_lib/clock_bootstrap_rom.v b/control_lib/clock_bootstrap_rom.v deleted file mode 100644 index 46563db65..000000000 --- a/control_lib/clock_bootstrap_rom.v +++ /dev/null @@ -1,34 +0,0 @@ - - -module clock_bootstrap_rom(input [15:0] addr, output [47:0] data); - - reg [47:0] rom [0:15]; - - //initial - // $readmemh("bootrom.mem", rom); - - assign data = rom[addr]; - - initial - begin - // First 16 bits are address, last 32 are data - // First 4 bits of address select which slave - rom[0] = 48'h0000_0C00_0F03; // Both clk sel choose ext ref (0), both are enabled (1), turn off SERDES, ADCs, turn on leds - rom[1] = 48'h1014_0000_0000; // SPI: Set Divider to div by 2 - rom[2] = 48'h1018_0000_0001; // SPI: Choose AD9510 - rom[3] = 48'h1010_0000_3418; // SPI: Auto-slave select, interrupt when done, TX_NEG, 24-bit word - rom[4] = 48'h1000_0000_0010; // SPI: AD9510 A:0 D:10 Set up AD9510 SPI - rom[5] = 48'h1010_0000_3518; // SPI: SEND IT Auto-slave select, interrupt when done, TX_NEG, 24-bit word - rom[6] = 48'hffff_ffff_ffff; // terminate - rom[7] = 48'hffff_ffff_ffff; // terminate - rom[8] = 48'hffff_ffff_ffff; // terminate - rom[9] = 48'hffff_ffff_ffff; // terminate - rom[10] = 48'hffff_ffff_ffff; // terminate - rom[11] = 48'hffff_ffff_ffff; // terminate - rom[12] = 48'hffff_ffff_ffff; // terminate - rom[13] = 48'hffff_ffff_ffff; // terminate - rom[14] = 48'hffff_ffff_ffff; // terminate - rom[15] = 48'hffff_ffff_ffff; // terminate - end // initial begin - -endmodule // clock_bootstrap_rom diff --git a/control_lib/clock_control.v b/control_lib/clock_control.v deleted file mode 100644 index 1bbe6bd75..000000000 --- a/control_lib/clock_control.v +++ /dev/null @@ -1,115 +0,0 @@ - - -// AD9510 Register Map (from datasheet Rev. A) - -/* INSTRUCTION word format (16 bits) - * 15 Read = 1, Write = 0 - * 14:13 W1/W0, Number of bytes 00 - 1, 01 - 2, 10 - 3, 11 - stream - * 12:0 Address - */ - -/* ADDR Contents Value (hex) - * 00 Serial Config Port 10 (def) -- MSB first, SDI/SDO separate - * 04 A Counter - * 05-06 B Counter - * 07-0A PLL Control - * 0B-0C R Divider - * 0D PLL Control - * 34-3A Fine Delay - * 3C-3F LVPECL Outs - * 40-43 LVDS/CMOS Outs - * 45 Clock select, power down - * 48-57 Dividers - * 58 Func and Sync - * 5A Update regs - */ - - -module clock_control - (input reset, - input aux_clk, // 25MHz, for before fpga clock is active - input clk_fpga, // real 100 MHz FPGA clock - output [1:0] clk_en, // controls source of reference clock - output [1:0] clk_sel, // controls source of reference clock - input clk_func, // FIXME needs to be some kind of out SYNC or reset to 9510 - input clk_status, // Monitor PLL or SYNC status - - output sen, // Enable for the AD9510 - output sclk, // FIXME these need to be shared - input sdi, - output sdo - ); - - wire read = 1'b0; // Always write for now - wire [1:0] w = 2'b00; // Always send 1 byte at a time - - assign clk_sel = 2'b00; // Both outputs from External Ref (SMA) - assign clk_en = 2'b11; // Both outputs enabled - - reg [20:0] addr_data; - - reg [5:0] entry; - reg start; - reg [7:0] counter; - reg [23:0] command; - - always @* - case(entry) - 6'd00 : addr_data = {13'h00,8'h10}; // Serial setup - 6'd01 : addr_data = {13'h45,8'h00}; // CLK2 drives distribution, everything on - 6'd02 : addr_data = {13'h3D,8'h80}; // Turn on output 1, normal levels - 6'd03 : addr_data = {13'h4B,8'h80}; // Bypass divider 1 (div by 1) - 6'd04 : addr_data = {13'h08,8'h47}; // POS PFD, Dig LK Det, Charge Pump normal - 6'd05 : addr_data = {13'h09,8'h70}; // Max Charge Pump current - 6'd06 : addr_data = {13'h0A,8'h04}; // Normal operation, Prescalar Div by 2, PLL On - 6'd07 : addr_data = {13'h0B,8'h00}; // RDIV MSB (6 bits) - 6'd08 : addr_data = {13'h0C,8'h01}; // RDIV LSB (8 bits), Div by 1 - 6'd09 : addr_data = {13'h0D,8'h00}; // Everything normal, Dig Lock Det - 6'd10 : addr_data = {13'h07,8'h00}; // Disable LOR detect - LOR causes failure... - 6'd11 : addr_data = {13'h04,8'h00}; // A Counter = Don't Care - 6'd12 : addr_data = {13'h05,8'h00}; // B Counter MSB = 0 - 6'd13 : addr_data = {13'h06,8'h05}; // B Counter LSB = 5 - default : addr_data = {13'h5A,8'h01}; // Register Update - endcase // case(entry) - - wire [5:0] lastentry = 6'd15; - wire done = (counter == 8'd49); - - always @(posedge aux_clk) - if(reset) - begin - entry <= #1 6'd0; - start <= #1 1'b1; - end - else if(start) - start <= #1 1'b0; - else if(done && (entry - // reg [7:0] ram3 [0:(1<<(AWIDTH-2))-1]; - - // Port 1 - always @(posedge clk) - if(en1_i) dat1_o[31:24] <= ram3[adr1_i[AWIDTH-1:2]]; - always @(posedge clk) - if(en1_i) dat1_o[23:16] <= ram2[adr1_i[AWIDTH-1:2]]; - always @(posedge clk) - if(en1_i) dat1_o[15:8] <= ram1[adr1_i[AWIDTH-1:2]]; - always @(posedge clk) - if(en1_i) dat1_o[7:0] <= ram0[adr1_i[AWIDTH-1:2]]; - - always @(posedge clk) - if(we1_i & en1_i & sel1_i[3]) - ram3[adr1_i[AWIDTH-1:2]] <= dat1_i[31:24]; - always @(posedge clk) - if(we1_i & en1_i & sel1_i[2]) - ram2[adr1_i[AWIDTH-1:2]] <= dat1_i[23:16]; - always @(posedge clk) - if(we1_i & en1_i & sel1_i[1]) - ram1[adr1_i[AWIDTH-1:2]] <= dat1_i[15:8]; - always @(posedge clk) - if(we1_i & en1_i & sel1_i[0]) - ram0[adr1_i[AWIDTH-1:2]] <= dat1_i[7:0]; - - // Port 2 - always @(posedge clk) - if(en2_i) dat2_o[31:24] <= ram3[adr2_i[AWIDTH-1:2]]; - always @(posedge clk) - if(en2_i) dat2_o[23:16] <= ram2[adr2_i[AWIDTH-1:2]]; - always @(posedge clk) - if(en2_i) dat2_o[15:8] <= ram1[adr2_i[AWIDTH-1:2]]; - always @(posedge clk) - if(en2_i) dat2_o[7:0] <= ram0[adr2_i[AWIDTH-1:2]]; - - always @(posedge clk) - if(we2_i & en2_i & sel2_i[3]) - ram3[adr2_i[AWIDTH-1:2]] <= dat2_i[31:24]; - always @(posedge clk) - if(we2_i & en2_i & sel2_i[2]) - ram2[adr2_i[AWIDTH-1:2]] <= dat2_i[23:16]; - always @(posedge clk) - if(we2_i & en2_i & sel2_i[1]) - ram1[adr2_i[AWIDTH-1:2]] <= dat2_i[15:8]; - always @(posedge clk) - if(we2_i & en2_i & sel2_i[0]) - ram0[adr2_i[AWIDTH-1:2]] <= dat2_i[7:0]; - -endmodule // dpram32 - - diff --git a/control_lib/fifo_tb.v b/control_lib/fifo_tb.v deleted file mode 100644 index 616fe4ee7..000000000 --- a/control_lib/fifo_tb.v +++ /dev/null @@ -1,151 +0,0 @@ -module fifo_tb(); - - reg clk, rst; - wire short_full, short_empty, long_full, long_empty; - wire casc2_full, casc2_empty; - reg read, write; - - wire [7:0] short_do, long_do; - wire [7:0] casc2_do; - reg [7:0] di; - - reg clear = 0; - - shortfifo #(.WIDTH(8)) shortfifo - (.clk(clk),.rst(rst),.datain(di),.dataout(short_do),.clear(clear), - .read(read),.write(write),.full(short_full),.empty(short_empty)); - - longfifo #(.WIDTH(8), .SIZE(4)) longfifo - (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear), - .read(read),.write(write),.full(long_full),.empty(long_empty)); - - cascadefifo2 #(.WIDTH(8), .SIZE(4)) cascadefifo2 - (.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear), - .read(read),.write(write),.full(casc2_full),.empty(casc2_empty)); - - initial rst = 1; - initial #1000 rst = 0; - initial clk = 0; - always #50 clk = ~clk; - - initial di = 8'hAE; - initial read = 0; - initial write = 0; - - always @(posedge clk) - if(write) - di <= di + 1; - - always @(posedge clk) - begin - if(short_full != long_full) - $display("Error: FULL mismatch"); - if(short_empty != long_empty) - $display("Note: EMPTY mismatch, usually not a problem (longfifo has 2 cycle latency)"); - if(read & (short_do != long_do)) - $display("Error: DATA mismatch"); - end - - initial $dumpfile("fifo_tb.vcd"); - initial $dumpvars(0,fifo_tb); - - initial - begin - @(negedge rst); - @(posedge clk); - repeat (10) - @(posedge clk); - write <= 1; - @(posedge clk); - write <= 0; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - read <= 1; - @(posedge clk); - read <= 0; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - - repeat(10) - begin - write <= 1; - @(posedge clk); - write <= 0; - @(posedge clk); - @(posedge clk); - @(posedge clk); - read <= 1; - @(posedge clk); - read <= 0; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - end // repeat (10) - - write <= 1; - repeat (4) - @(posedge clk); - write <= 0; - @(posedge clk); - read <= 1; - repeat (4) - @(posedge clk); - read <= 0; - @(posedge clk); - - - write <= 1; - repeat (4) - @(posedge clk); - write <= 0; - @(posedge clk); - repeat (4) - begin - read <= 1; - @(posedge clk); - read <= 0; - @(posedge clk); - end - - write <= 1; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - read <= 1; - repeat (5) - @(posedge clk); - write <= 0; - @(posedge clk); - @(posedge clk); - read <= 0; - @(posedge clk); - - write <= 1; - repeat (16) - @(posedge clk); - write <= 0; - @(posedge clk); - - read <= 1; - repeat (16) - @(posedge clk); - read <= 0; - @(posedge clk); - - repeat (10) - @(posedge clk); - $finish; - end -endmodule // longfifo_tb diff --git a/control_lib/gray2bin.v b/control_lib/gray2bin.v deleted file mode 100644 index 5df40bd52..000000000 --- a/control_lib/gray2bin.v +++ /dev/null @@ -1,13 +0,0 @@ - - -module gray2bin - #(parameter WIDTH=8) - (input [WIDTH-1:0] gray, - output reg [WIDTH-1:0] bin); - - integer i; - always @(gray) - for(i = 0;i>i); - -endmodule // gray2bin diff --git a/control_lib/gray_send.v b/control_lib/gray_send.v deleted file mode 100644 index 7fc07d40c..000000000 --- a/control_lib/gray_send.v +++ /dev/null @@ -1,29 +0,0 @@ - - - -module gray_send - #(parameter WIDTH = 8) - (input clk_in, input [WIDTH-1:0] addr_in, - input clk_out, output reg [WIDTH-1:0] addr_out); - - reg [WIDTH-1:0] gray_clkin, gray_clkout, gray_clkout_d1; - wire [WIDTH-1:0] gray, bin; - - bin2gray #(.WIDTH(WIDTH)) b2g (.bin(addr_in), .gray(gray) ); - - always @(posedge clk_in) - gray_clkin <= gray; - - always @(posedge clk_out) - gray_clkout <= gray_clkin; - - always @(posedge clk_out) - gray_clkout_d1 <= gray_clkout; - - gray2bin #(.WIDTH(WIDTH)) g2b (.gray(gray_clkout_d1), .bin(bin) ); - - // FIXME we may not need the next register, but it may help timing - always @(posedge clk_out) - addr_out <= bin; - -endmodule // gray_send diff --git a/control_lib/icache.v b/control_lib/icache.v deleted file mode 100644 index bd21f47cc..000000000 --- a/control_lib/icache.v +++ /dev/null @@ -1,135 +0,0 @@ - -module icache - #(parameter AWIDTH=14, - parameter CWIDTH=6) - - (input wb_clk_i, - input wb_rst_i, - input [AWIDTH-1:0] iwb_adr_i, - input iwb_stb_i, - output [31:0] iwb_dat_o, - output iwb_ack_o, - input [31:0] iram_dat_i, - output [AWIDTH-1:0] iram_adr_o, - output iram_en_o, - input flush); - - localparam TAGWIDTH = AWIDTH-CWIDTH-2; - reg stb_d1, ack_d1, miss_d1; - reg [AWIDTH-1:0] held_addr; - reg [31:0] idata [0:(1< clear $end -$var wire 1 ? clk $end -$var wire 36 @ datain [35:0] $end -$var wire 36 A dataout [35:0] $end -$var wire 1 $ dst_rdy_i $end -$var wire 1 ! dst_rdy_o $end -$var wire 1 B read $end -$var wire 1 C reset $end -$var wire 1 D src_rdy_i $end -$var wire 1 % src_rdy_o $end -$var wire 1 E write $end -$var reg 4 F a [3:0] $end -$var reg 1 G empty $end -$var reg 1 H full $end -$var reg 5 I occupied [4:0] $end -$var reg 5 J space [4:0] $end -$scope begin gen_srl16[0] $end -$scope module srl16e $end -$var wire 1 K A0 $end -$var wire 1 L A1 $end -$var wire 1 M A2 $end -$var wire 1 N A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 O D $end -$var wire 1 P Q $end -$var reg 16 Q data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[1] $end -$scope module srl16e $end -$var wire 1 R A0 $end -$var wire 1 S A1 $end -$var wire 1 T A2 $end -$var wire 1 U A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 V D $end -$var wire 1 W Q $end -$var reg 16 X data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[2] $end -$scope module srl16e $end -$var wire 1 Y A0 $end -$var wire 1 Z A1 $end -$var wire 1 [ A2 $end -$var wire 1 \ A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 ] D $end -$var wire 1 ^ Q $end -$var reg 16 _ data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[3] $end -$scope module srl16e $end -$var wire 1 ` A0 $end -$var wire 1 a A1 $end -$var wire 1 b A2 $end -$var wire 1 c A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 d D $end -$var wire 1 e Q $end -$var reg 16 f data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[4] $end -$scope module srl16e $end -$var wire 1 g A0 $end -$var wire 1 h A1 $end -$var wire 1 i A2 $end -$var wire 1 j A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 k D $end -$var wire 1 l Q $end -$var reg 16 m data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[5] $end -$scope module srl16e $end -$var wire 1 n A0 $end -$var wire 1 o A1 $end -$var wire 1 p A2 $end -$var wire 1 q A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 r D $end -$var wire 1 s Q $end -$var reg 16 t data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[6] $end -$scope module srl16e $end -$var wire 1 u A0 $end -$var wire 1 v A1 $end -$var wire 1 w A2 $end -$var wire 1 x A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 y D $end -$var wire 1 z Q $end -$var reg 16 { data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[7] $end -$scope module srl16e $end -$var wire 1 | A0 $end -$var wire 1 } A1 $end -$var wire 1 ~ A2 $end -$var wire 1 !" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 "" D $end -$var wire 1 #" Q $end -$var reg 16 $" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[8] $end -$scope module srl16e $end -$var wire 1 %" A0 $end -$var wire 1 &" A1 $end -$var wire 1 '" A2 $end -$var wire 1 (" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 )" D $end -$var wire 1 *" Q $end -$var reg 16 +" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[9] $end -$scope module srl16e $end -$var wire 1 ," A0 $end -$var wire 1 -" A1 $end -$var wire 1 ." A2 $end -$var wire 1 /" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 0" D $end -$var wire 1 1" Q $end -$var reg 16 2" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[10] $end -$scope module srl16e $end -$var wire 1 3" A0 $end -$var wire 1 4" A1 $end -$var wire 1 5" A2 $end -$var wire 1 6" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 7" D $end -$var wire 1 8" Q $end -$var reg 16 9" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[11] $end -$scope module srl16e $end -$var wire 1 :" A0 $end -$var wire 1 ;" A1 $end -$var wire 1 <" A2 $end -$var wire 1 =" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 >" D $end -$var wire 1 ?" Q $end -$var reg 16 @" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[12] $end -$scope module srl16e $end -$var wire 1 A" A0 $end -$var wire 1 B" A1 $end -$var wire 1 C" A2 $end -$var wire 1 D" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 E" D $end -$var wire 1 F" Q $end -$var reg 16 G" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[13] $end -$scope module srl16e $end -$var wire 1 H" A0 $end -$var wire 1 I" A1 $end -$var wire 1 J" A2 $end -$var wire 1 K" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 L" D $end -$var wire 1 M" Q $end -$var reg 16 N" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[14] $end -$scope module srl16e $end -$var wire 1 O" A0 $end -$var wire 1 P" A1 $end -$var wire 1 Q" A2 $end -$var wire 1 R" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 S" D $end -$var wire 1 T" Q $end -$var reg 16 U" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[15] $end -$scope module srl16e $end -$var wire 1 V" A0 $end -$var wire 1 W" A1 $end -$var wire 1 X" A2 $end -$var wire 1 Y" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 Z" D $end -$var wire 1 [" Q $end -$var reg 16 \" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[16] $end -$scope module srl16e $end -$var wire 1 ]" A0 $end -$var wire 1 ^" A1 $end -$var wire 1 _" A2 $end -$var wire 1 `" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 a" D $end -$var wire 1 b" Q $end -$var reg 16 c" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[17] $end -$scope module srl16e $end -$var wire 1 d" A0 $end -$var wire 1 e" A1 $end -$var wire 1 f" A2 $end -$var wire 1 g" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 h" D $end -$var wire 1 i" Q $end -$var reg 16 j" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[18] $end -$scope module srl16e $end -$var wire 1 k" A0 $end -$var wire 1 l" A1 $end -$var wire 1 m" A2 $end -$var wire 1 n" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 o" D $end -$var wire 1 p" Q $end -$var reg 16 q" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[19] $end -$scope module srl16e $end -$var wire 1 r" A0 $end -$var wire 1 s" A1 $end -$var wire 1 t" A2 $end -$var wire 1 u" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 v" D $end -$var wire 1 w" Q $end -$var reg 16 x" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[20] $end -$scope module srl16e $end -$var wire 1 y" A0 $end -$var wire 1 z" A1 $end -$var wire 1 {" A2 $end -$var wire 1 |" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 }" D $end -$var wire 1 ~" Q $end -$var reg 16 !# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[21] $end -$scope module srl16e $end -$var wire 1 "# A0 $end -$var wire 1 ## A1 $end -$var wire 1 $# A2 $end -$var wire 1 %# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 &# D $end -$var wire 1 '# Q $end -$var reg 16 (# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[22] $end -$scope module srl16e $end -$var wire 1 )# A0 $end -$var wire 1 *# A1 $end -$var wire 1 +# A2 $end -$var wire 1 ,# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 -# D $end -$var wire 1 .# Q $end -$var reg 16 /# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[23] $end -$scope module srl16e $end -$var wire 1 0# A0 $end -$var wire 1 1# A1 $end -$var wire 1 2# A2 $end -$var wire 1 3# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 4# D $end -$var wire 1 5# Q $end -$var reg 16 6# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[24] $end -$scope module srl16e $end -$var wire 1 7# A0 $end -$var wire 1 8# A1 $end -$var wire 1 9# A2 $end -$var wire 1 :# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 ;# D $end -$var wire 1 <# Q $end -$var reg 16 =# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[25] $end -$scope module srl16e $end -$var wire 1 ># A0 $end -$var wire 1 ?# A1 $end -$var wire 1 @# A2 $end -$var wire 1 A# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 B# D $end -$var wire 1 C# Q $end -$var reg 16 D# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[26] $end -$scope module srl16e $end -$var wire 1 E# A0 $end -$var wire 1 F# A1 $end -$var wire 1 G# A2 $end -$var wire 1 H# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 I# D $end -$var wire 1 J# Q $end -$var reg 16 K# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[27] $end -$scope module srl16e $end -$var wire 1 L# A0 $end -$var wire 1 M# A1 $end -$var wire 1 N# A2 $end -$var wire 1 O# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 P# D $end -$var wire 1 Q# Q $end -$var reg 16 R# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[28] $end -$scope module srl16e $end -$var wire 1 S# A0 $end -$var wire 1 T# A1 $end -$var wire 1 U# A2 $end -$var wire 1 V# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 W# D $end -$var wire 1 X# Q $end -$var reg 16 Y# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[29] $end -$scope module srl16e $end -$var wire 1 Z# A0 $end -$var wire 1 [# A1 $end -$var wire 1 \# A2 $end -$var wire 1 ]# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 ^# D $end -$var wire 1 _# Q $end -$var reg 16 `# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[30] $end -$scope module srl16e $end -$var wire 1 a# A0 $end -$var wire 1 b# A1 $end -$var wire 1 c# A2 $end -$var wire 1 d# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 e# D $end -$var wire 1 f# Q $end -$var reg 16 g# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[31] $end -$scope module srl16e $end -$var wire 1 h# A0 $end -$var wire 1 i# A1 $end -$var wire 1 j# A2 $end -$var wire 1 k# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 l# D $end -$var wire 1 m# Q $end -$var reg 16 n# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[32] $end -$scope module srl16e $end -$var wire 1 o# A0 $end -$var wire 1 p# A1 $end -$var wire 1 q# A2 $end -$var wire 1 r# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 s# D $end -$var wire 1 t# Q $end -$var reg 16 u# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[33] $end -$scope module srl16e $end -$var wire 1 v# A0 $end -$var wire 1 w# A1 $end -$var wire 1 x# A2 $end -$var wire 1 y# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 z# D $end -$var wire 1 {# Q $end -$var reg 16 |# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[34] $end -$scope module srl16e $end -$var wire 1 }# A0 $end -$var wire 1 ~# A1 $end -$var wire 1 !$ A2 $end -$var wire 1 "$ A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 #$ D $end -$var wire 1 $$ Q $end -$var reg 16 %$ data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[35] $end -$scope module srl16e $end -$var wire 1 &$ A0 $end -$var wire 1 '$ A1 $end -$var wire 1 ($ A2 $end -$var wire 1 )$ A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 *$ D $end -$var wire 1 +$ Q $end -$var reg 16 ,$ data [15:0] $end -$upscope $end -$upscope $end -$upscope $end -$scope module fifo36_to_fifo19 $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 -$ f19_dataout [18:0] $end -$var wire 1 ' f19_dst_rdy_i $end -$var wire 1 ( f19_src_rdy_o $end -$var wire 1 .$ f19_xfer $end -$var wire 36 /$ f36_datain [35:0] $end -$var wire 1 $ f36_dst_rdy_o $end -$var wire 1 0$ f36_eof $end -$var wire 1 1$ f36_occ $end -$var wire 1 2$ f36_sof $end -$var wire 1 % f36_src_rdy_i $end -$var wire 1 3$ f36_xfer $end -$var wire 1 4$ half_line $end -$var wire 1 C reset $end -$var reg 1 5$ phase $end -$upscope $end -$scope module fifo19_to_ll8 $end -$var wire 1 6$ advance $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 7$ f19_data [18:0] $end -$var wire 1 ' f19_dst_rdy_o $end -$var wire 1 8$ f19_eof $end -$var wire 1 9$ f19_occ $end -$var wire 1 :$ f19_sof $end -$var wire 1 ( f19_src_rdy_i $end -$var wire 1 ;$ ll_dst_rdy $end -$var wire 1 / ll_dst_rdy_n $end -$var wire 1 <$ ll_eof $end -$var wire 1 0 ll_eof_n $end -$var wire 1 =$ ll_sof $end -$var wire 1 1 ll_sof_n $end -$var wire 1 >$ ll_src_rdy $end -$var wire 1 2 ll_src_rdy_n $end -$var wire 1 C reset $end -$var reg 8 ?$ ll_data [7:0] $end -$var reg 1 @$ state $end -$upscope $end -$scope module ll8_to_fifo19 $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 A$ f19_data [18:0] $end -$var wire 1 * f19_dst_rdy_i $end -$var wire 1 + f19_src_rdy_o $end -$var wire 8 B$ ll_data [7:0] $end -$var wire 1 C$ ll_dst_rdy $end -$var wire 1 / ll_dst_rdy_n $end -$var wire 1 D$ ll_eof $end -$var wire 1 0 ll_eof_n $end -$var wire 1 E$ ll_sof $end -$var wire 1 1 ll_sof_n $end -$var wire 1 F$ ll_src_rdy $end -$var wire 1 2 ll_src_rdy_n $end -$var wire 1 C reset $end -$var wire 1 G$ xfer_out $end -$var reg 8 H$ dat0 [7:0] $end -$var reg 8 I$ dat1 [7:0] $end -$var reg 1 J$ f19_eof $end -$var reg 1 K$ f19_occ $end -$var reg 1 L$ f19_sof $end -$var reg 2 M$ state [1:0] $end -$upscope $end -$scope module fifo19_to_fifo36 $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 N$ f19_datain [18:0] $end -$var wire 1 * f19_dst_rdy_o $end -$var wire 1 O$ f19_eof $end -$var wire 1 P$ f19_occ $end -$var wire 1 Q$ f19_sof $end -$var wire 1 + f19_src_rdy_i $end -$var wire 36 R$ f36_dataout [35:0] $end -$var wire 1 S$ f36_dst_rdy_i $end -$var wire 1 - f36_src_rdy_o $end -$var wire 1 C reset $end -$var wire 1 T$ xfer_out $end -$var reg 16 U$ dat0 [15:0] $end -$var reg 16 V$ dat1 [15:0] $end -$var reg 1 W$ f36_eof $end -$var reg 1 X$ f36_occ $end -$var reg 1 Y$ f36_sof $end -$var reg 2 Z$ state [1:0] $end -$upscope $end -$scope task PutPacketInFIFO36 $end -$var reg 32 [$ data_len [31:0] $end -$var reg 32 \$ data_start [31:0] $end -$upscope $end -$scope task ReadFromFIFO36 $end -$upscope $end -$upscope $end -$enddefinitions $end -#0 -$dumpvars -bx \$ -bx [$ -bx Z$ -xY$ -xX$ -xW$ -bx V$ -bx U$ -0T$ -0S$ -b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx R$ -xQ$ -xP$ -xO$ -bx N$ -bx M$ -xL$ -xK$ -xJ$ -bx I$ -bx H$ -xG$ -xF$ -xE$ -xD$ -xC$ -bx B$ -bx A$ -x@$ -bx ?$ -x>$ -x=$ -x<$ -x;$ -x:$ -x9$ -x8$ -bx 7$ -x6$ -x5$ -x4$ -x3$ -x2$ -x1$ -x0$ -bx /$ -x.$ -bx -$ -b0 ,$ -x+$ -0*$ -x)$ -x($ -x'$ -x&$ -b0 %$ -x$$ -0#$ -x"$ -x!$ -x~# -x}# -b0 |# -x{# -0z# -xy# -xx# -xw# -xv# -b0 u# -xt# -0s# -xr# -xq# -xp# -xo# -b0 n# -xm# -0l# -xk# -xj# -xi# -xh# -b0 g# -xf# -0e# -xd# -xc# -xb# -xa# -b0 `# -x_# -0^# -x]# -x\# -x[# -xZ# -b0 Y# -xX# -0W# -xV# -xU# -xT# -xS# -b0 R# -xQ# -0P# -xO# -xN# -xM# -xL# -b0 K# -xJ# -0I# -xH# -xG# -xF# -xE# -b0 D# -xC# -0B# -xA# -x@# -x?# -x># -b0 =# -x<# -0;# -x:# -x9# -x8# -x7# -b0 6# -x5# -04# -x3# -x2# -x1# -x0# -b0 /# -x.# -0-# -x,# -x+# -x*# -x)# -b0 (# -x'# -0&# -x%# -x$# -x## -x"# -b0 !# -x~" -0}" -x|" -x{" -xz" -xy" -b0 x" -xw" -0v" -xu" -xt" -xs" -xr" -b0 q" -xp" -0o" -xn" -xm" -xl" -xk" -b0 j" -xi" -0h" -xg" -xf" -xe" -xd" -b0 c" -xb" -0a" -x`" -x_" -x^" -x]" -b0 \" -x[" -0Z" -xY" -xX" -xW" -xV" -b0 U" -xT" -0S" -xR" -xQ" -xP" -xO" -b0 N" -xM" -0L" -xK" -xJ" -xI" -xH" -b0 G" -xF" -0E" -xD" -xC" -xB" -xA" -b0 @" -x?" -0>" -x=" -x<" -x;" -x:" -b0 9" -x8" -07" -x6" -x5" -x4" -x3" -b0 2" -x1" -00" -x/" -x." -x-" -x," -b0 +" -x*" -0)" -x(" -x'" -x&" -x%" -b0 $" -x#" -0"" -x!" -x~ -x} -x| -b0 { -xz -0y -xx -xw -xv -xu -b0 t -xs -0r -xq -xp -xo -xn -b0 m -xl -0k -xj -xi -xh -xg -b0 f -xe -0d -xc -xb -xa -x` -b0 _ -x^ -0] -x\ -x[ -xZ -xY -b0 X -xW -0V -xU -xT -xS -xR -b0 Q -xP -0O -xN -xM -xL -xK -bx J -bx I -xH -xG -bx F -0E -0D -1C -xB -bx A -b0 @ -0? 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-#13800000000000000 -04 -0? -#13850000000000000 -1.$ -1' -b11110101 ?$ -b11110101 . -b11110101 B$ -0G$ -1T$ -1@$ -b1 M$ -0+ -b11100101 H$ -b1110010110110100 ) -b1110010110110100 A$ -b1110010110110100 N$ -b10 Z$ -1- -b1010010010110100 V$ -b11100100111101001010010010110100 , -b11100100111101001010010010110100 R$ -14 -1? -#13900000000000000 -04 -0? -#13950000000000000 -0.$ -03$ -0B -0' -0$ -0T$ -1G$ -b10100101 ?$ -b10100101 . -b10100101 B$ -b1010010110110101 & -b1010010110110101 -$ -b1010010110110101 7$ -b0 Z$ -0- -b11110101 I$ -b1110010111110101 ) -b1110010111110101 A$ -b1110010111110101 N$ -b10 M$ -1+ -0@$ -15$ -14 -1? -#14000000000000000 -04 -0? -#14050000000000000 -13$ -1B -1.$ -1$ -1' -b10110101 ?$ -b10110101 . -b10110101 B$ -0G$ -1@$ -b1 M$ -0+ -b10100101 H$ -b1010010111110101 ) -b1010010111110101 A$ -b1010010111110101 N$ -b1 Z$ -b1110010111110101 U$ -b11100101111101011010010010110100 , -b11100101111101011010010010110100 R$ -14 -1? -#14100000000000000 -04 -0? -#14150000000000000 -0.$ -03$ -0B -0' -0$ -1G$ -b11100110 ?$ -b11100110 . -b11100110 B$ -b1110011011110110 & -b1110011011110110 -$ -b1110011011110110 7$ -0K -0P -0R -1W -0Y -0` -0g -0n -0u -0| -0%" -0*" -0," -11" -03" -0:" -0A" -0H" -0O" -0V" -0]" -0b" -0d" -1i" -0k" -0r" -0y" -0"# -0)# -00# -07# -0<# -0># -1C# -b11100110111101101010011010110110 # -b11100110111101101010011010110110 A -b11100110111101101010011010110110 /$ -0E# -0L# -0S# -0Z# -0a# -0h# -0o# -0v# -0}# -0&$ -b10110101 I$ -b1010010110110101 ) -b1010010110110101 A$ -b1010010110110101 N$ -b10 M$ -1+ -0@$ -05$ -b11 I -b1101 J -b10 F -14 -1? -#14200000000000000 -04 -0? -#14250000000000000 -1.$ -1' -b11110110 ?$ -b11110110 . -b11110110 B$ -0G$ -1T$ -1@$ -b1 M$ -0+ -b11100110 H$ -b1110011010110101 ) -b1110011010110101 A$ -b1110011010110101 N$ -b10 Z$ -1- -b1010010110110101 V$ -b11100101111101011010010110110101 , -b11100101111101011010010110110101 R$ -14 -1? -#14300000000000000 -04 -0? -#14350000000000000 -0.$ -03$ -0B -0' -0$ -0T$ -1G$ -b10100110 ?$ -b10100110 . -b10100110 B$ -b1010011010110110 & -b1010011010110110 -$ -b1010011010110110 7$ -b0 Z$ -0- -b11110110 I$ -b1110011011110110 ) -b1110011011110110 A$ -b1110011011110110 N$ -b10 M$ -1+ -0@$ -15$ -14 -1? -#14400000000000000 -04 -0? -#14450000000000000 -13$ -1B -1.$ -1$ -1' -b10110110 ?$ -b10110110 . -b10110110 B$ -0G$ -1@$ -b1 M$ -0+ -b10100110 H$ -b1010011011110110 ) -b1010011011110110 A$ -b1010011011110110 N$ -b1 Z$ -b1110011011110110 U$ -b11100110111101101010010110110101 , -b11100110111101101010010110110101 R$ -14 -1? -#14500000000000000 -04 -0? -#14550000000000000 -0.$ -03$ -0B -0' -0$ -1G$ -b11100111 ?$ -b11100111 . -b11100111 B$ -b1110011111110111 & -b1110011111110111 -$ -b1110011111110111 7$ -1K -1P -0L -1R -0S -1W -1Y -0Z -1^ -1` -0a -0e -1g -0h -1n -0o -1u -0v -1| -0} -1%" -1*" -0&" -1," -0-" -11" -13" -04" -18" -1:" -0;" -0?" -1A" -0B" -1H" -0I" -1O" -0P" -1V" -0W" -1]" -1b" -0^" -1d" -0e" -1i" -1k" -0l" -1p" -1r" -0s" -0w" -1y" -0z" -1"# -0## -1)# -0*# -10# -01# -17# -1<# -08# -1># -0?# -1C# -1E# -0F# -1J# -1L# -0M# -0Q# -1S# -0T# -1Z# -0[# -1a# -0b# -1h# -0i# -1o# -0p# -1v# -0w# -0{# -b11100111111101111010011110110111 # -b11100111111101111010011110110111 A -b11100111111101111010011110110111 /$ -1}# -0~# -1&$ -0'$ -b10110110 I$ -b1010011010110110 ) -b1010011010110110 A$ -b1010011010110110 N$ -b10 M$ -1+ -0@$ -05$ -b10 I -b1110 J -b1 F -14 -1? -#14600000000000000 -04 -0? -#14650000000000000 -1.$ -1' -b11110111 ?$ -b11110111 . -b11110111 B$ -0G$ -1T$ -1@$ -b1 M$ -0+ -b11100111 H$ -b1110011110110110 ) -b1110011110110110 A$ -b1110011110110110 N$ -b10 Z$ -1- -b1010011010110110 V$ -b11100110111101101010011010110110 , -b11100110111101101010011010110110 R$ -14 -1? -#14700000000000000 -04 -0? -#14750000000000000 -0.$ -03$ -0B -0' -0$ -0T$ -1G$ -b10100111 ?$ -b10100111 . -b10100111 B$ -b1010011110110111 & -b1010011110110111 -$ -b1010011110110111 7$ -b0 Z$ -0- -b11110111 I$ -b1110011111110111 ) -b1110011111110111 A$ -b1110011111110111 N$ -b10 M$ -1+ -0@$ -15$ -14 -1? -#14800000000000000 -04 -0? -#14850000000000000 -13$ -1B -1.$ -1$ -1' -b10110111 ?$ -b10110111 . -b10110111 B$ -0G$ -1@$ -b1 M$ -0+ -b10100111 H$ -b1010011111110111 ) -b1010011111110111 A$ -b1010011111110111 N$ -b1 Z$ -b1110011111110111 U$ -b11100111111101111010011010110110 , -b11100111111101111010011010110110 R$ -14 -1? -#14900000000000000 -04 -0? -#14950000000000000 -0.$ -03$ -0B -0' -0$ -10$ -1G$ -b11101000 ?$ -b11101000 . -b11101000 B$ -b1110100011111000 & -b1110100011111000 -$ -b1110100011111000 7$ -0K -0P -0R -0W -0Y -0^ -0` -1e -0g -0n -0u -0| -0%" -0*" -0," -01" -03" -08" -0:" -1?" -0A" -0H" -0O" -0V" -0]" -0b" -0d" -0i" -0k" -0p" -0r" -1w" -0y" -0"# -0)# -00# -07# -0<# -0># -0C# -0E# -0J# -0L# -1Q# -0S# -0Z# -0a# -0h# -0o# -0v# -1{# -b1011101000111110001010100010111000 # -b1011101000111110001010100010111000 A -b1011101000111110001010100010111000 /$ -0}# -0&$ -b10110111 I$ -b1010011110110111 ) -b1010011110110111 A$ -b1010011110110111 N$ -b10 M$ -1+ -0@$ -05$ -b1 I -b1111 J -b0 F -14 -1? -#15000000000000000 -04 -0? -#15050000000000000 -1.$ -1' -b11111000 ?$ -b11111000 . -b11111000 B$ -0G$ -1T$ -1@$ -b1 M$ -0+ -b11101000 H$ -b1110100010110111 ) -b1110100010110111 A$ -b1110100010110111 N$ -b10 Z$ -1- -b1010011110110111 V$ -b11100111111101111010011110110111 , -b11100111111101111010011110110111 R$ -14 -1? -#15100000000000000 -04 -0? -#15150000000000000 -0.$ -03$ -0B -0' -18$ -0$ -0T$ -1G$ -b10101000 ?$ -b10101000 . -b10101000 B$ -b101010100010111000 & -b101010100010111000 -$ -b101010100010111000 7$ -b0 Z$ -0- -b11111000 I$ -b1110100011111000 ) -b1110100011111000 A$ -b1110100011111000 N$ -b10 M$ -1+ -0@$ -15$ -14 -1? -#15200000000000000 -04 -0? -#15250000000000000 -1D$ -13$ -1B -00 -1.$ -1$ -1<$ -1' -b10111000 ?$ -b10111000 . -b10111000 B$ -0G$ -1@$ -b1 M$ -0+ -b10101000 H$ -b1010100011111000 ) -b1010100011111000 A$ -b1010100011111000 N$ -b1 Z$ -b1110100011111000 U$ -b11101000111110001010011110110111 , -b11101000111110001010011110110111 R$ -14 -1? -#15300000000000000 -04 -0? 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-#18100000000000000 -04 -0? -#18150000000000000 -14 -1? -#18200000000000000 -04 -0? -#18250000000000000 -14 -1? -#18300000000000000 -04 -0? -#18350000000000000 -14 -1? -#18400000000000000 -04 -0? -#18450000000000000 -14 -1? -#18500000000000000 -04 -0? -#18550000000000000 -14 -1? -#18600000000000000 -04 -0? -#18650000000000000 -14 -1? -#18700000000000000 -04 -0? -#18750000000000000 -14 -1? -#18800000000000000 -04 -0? -#18850000000000000 -14 -1? -#18900000000000000 -04 -0? -#18950000000000000 -14 -1? -#19000000000000000 -04 -0? -#19050000000000000 -14 -1? -#19100000000000000 -04 -0? -#19150000000000000 -14 -1? -#19200000000000000 -04 -0? -#19250000000000000 -14 -1? -#19300000000000000 -04 -0? -#19350000000000000 -14 -1? -#19400000000000000 -04 -0? -#19450000000000000 -14 -1? -#19500000000000000 -04 -0? -#19550000000000000 -14 -1? -#19600000000000000 -04 -0? -#19650000000000000 -14 -1? -#19700000000000000 -04 -0? -#19750000000000000 -14 -1? -#19800000000000000 -04 -0? -#19850000000000000 -14 -1? -#19900000000000000 -04 -0? -#19950000000000000 -14 -1? -#20000000000000000 -04 -0? diff --git a/control_lib/newfifo/fifo_short.v b/control_lib/newfifo/fifo_short.v deleted file mode 100644 index 53a7603c7..000000000 --- a/control_lib/newfifo/fifo_short.v +++ /dev/null @@ -1,95 +0,0 @@ - -module fifo_short - #(parameter WIDTH=32) - (input clk, input reset, input clear, - input [WIDTH-1:0] datain, - input src_rdy_i, - output dst_rdy_o, - output [WIDTH-1:0] dataout, - output src_rdy_o, - input dst_rdy_i, - - output reg [4:0] space, - output reg [4:0] occupied); - - reg full, empty; - wire write = src_rdy_i & dst_rdy_o; - wire read = dst_rdy_i & src_rdy_o; - - assign dst_rdy_o = ~full; - assign src_rdy_o = ~empty; - - reg [3:0] a; - genvar i; - - generate - for (i=0;i 00 = all 4 bytes - 01 = 1 byte - 10 = 2 bytes - 11 = 3 bytes - -fifo36 --> {OCC[1:0],EOP,SOP,DATA[31:0]} - OCC same as buffer interface - -fifo19 --> {OCC,EOP,SOP,DATA[15:0]} - Doesn't fit well into BRAM, dist RAM ok - OCC = 1 means last word is half full - = 0 means last word is full - -fifo18 --> {EOP,SOP,DATA[15:0]} - No half-word capability? Should we drop sop instead? - -Control Wires - Data into FIFO - SRC_RDY_i Upstream has data for me - DST_RDY_o I have space - Transfer occurs if SRC_RDI_i && DST_RDY_o - -Control Wires - Data out of FIFO - SRC_RDY_o I have data for downstream - DST_RDY_i Downstream has space - Transfer occurs if SRC_RDI_o && DST_RDY_i - diff --git a/control_lib/newfifo/fifo_tb.v b/control_lib/newfifo/fifo_tb.v deleted file mode 100644 index f561df7fa..000000000 --- a/control_lib/newfifo/fifo_tb.v +++ /dev/null @@ -1,158 +0,0 @@ -module fifo_new_tb(); - - reg clk = 0; - reg rst = 1; - reg clear = 0; - initial #1000 rst = 0; - always #50 clk = ~clk; - - reg [31:0] f36_data = 0; - reg [1:0] f36_occ = 0; - reg f36_sof = 0, f36_eof = 0; - - wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data}; - reg src_rdy_f36i = 0; - wire dst_rdy_f36i; - - wire [35:0] f36_out, f36_out2; - wire src_rdy_f36o; - reg dst_rdy_f36o = 0; - - //fifo_cascade #(.WIDTH(36), .SIZE(4)) fifo_cascade36 - //fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36 - - wire i1_sr, i1_dr; - wire i2_sr, i2_dr; - wire i3_sr, i3_dr; - reg i4_dr = 0; - wire i4_sr; - - wire [35:0] i1, i4; - wire [18:0] i2, i3; - - wire [7:0] ll_data; - wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n; - - fifo_short #(.WIDTH(36)) fifo_short1 - (.clk(clk),.reset(rst),.clear(clear), - .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i), - .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) ); - - fifo36_to_fifo19 fifo36_to_fifo19 - (.clk(clk),.reset(rst),.clear(clear), - .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr), - .f19_dataout(i2),.f19_src_rdy_o(i2_sr),.f19_dst_rdy_i(i2_dr) ); - - fifo19_to_ll8 fifo19_to_ll8 - (.clk(clk),.reset(rst),.clear(clear), - .f19_data(i2),.f19_src_rdy_i(i2_sr),.f19_dst_rdy_o(i2_dr), - .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n), - .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n)); - - ll8_to_fifo19 ll8_to_fifo19 - (.clk(clk),.reset(rst),.clear(clear), - .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n), - .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n), - .f19_data(i3),.f19_src_rdy_o(i3_sr),.f19_dst_rdy_i(i3_dr) ); - - fifo19_to_fifo36 fifo19_to_fifo36 - (.clk(clk),.reset(rst),.clear(clear), - .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr), - .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) ); - - task ReadFromFIFO36; - begin - $display("Read from FIFO36"); - #1 i4_dr <= 1; - while(1) - begin - while(~i4_sr) - @(posedge clk); - $display("Read: %h",i4); - @(posedge clk); - end - end - endtask // ReadFromFIFO36 - - reg [15:0] count; - task PutPacketInFIFO36; - input [31:0] data_start; - input [31:0] data_len; - begin - count <= 4; - src_rdy_f36i <= 1; - f36_data <= data_start; - f36_sof <= 1; - f36_eof <= 0; - f36_occ <= 0; - - $display("Put Packet in FIFO36"); - while(~dst_rdy_f36i) - @(posedge clk); - @(posedge clk); - $display("PPI_FIFO36: Entered First Line"); - f36_sof <= 0; - while(count+4 < data_len) - begin - f36_data <= f36_data + 32'h01010101; - count <= count + 4; - while(~dst_rdy_f36i) - @(posedge clk); - @(posedge clk); - $display("PPI_FIFO36: Entered New Line"); - end - f36_data <= f36_data + 32'h01010101; - f36_eof <= 1; - if(count + 4 == data_len) - f36_occ <= 0; - else if(count + 3 == data_len) - f36_occ <= 3; - else if(count + 2 == data_len) - f36_occ <= 2; - else - f36_occ <= 1; - while(~dst_rdy_f36i) - @(posedge clk); - @(posedge clk); - f36_occ <= 0; - f36_eof <= 0; - f36_data <= 0; - src_rdy_f36i <= 0; - $display("PPI_FIFO36: Entered Last Line"); - end - endtask // PutPacketInFIFO36 - - initial $dumpfile("fifo_new_tb.vcd"); - initial $dumpvars(0,fifo_new_tb); - - initial - begin - @(negedge rst); - //#10000; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - ReadFromFIFO36; - end - - initial - begin - @(negedge rst); - @(posedge clk); - @(posedge clk); - PutPacketInFIFO36(32'hA0B0C0D0,12); - @(posedge clk); - @(posedge clk); - #10000; - @(posedge clk); - PutPacketInFIFO36(32'hE0F0A0B0,36); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - end - - initial #20000 $finish; -endmodule // longfifo_tb diff --git a/control_lib/newfifo/ll8_shortfifo.v b/control_lib/newfifo/ll8_shortfifo.v deleted file mode 100644 index 39ada9a4f..000000000 --- a/control_lib/newfifo/ll8_shortfifo.v +++ /dev/null @@ -1,13 +0,0 @@ - - -module ll8_shortfifo - (input clk, input reset, input clear, - input [7:0] datain, input sof_i, input eof_i, input error_i, input src_rdy_i, output dst_rdy_o, - output [7:0] dataout, output sof_o, output eof_o, output error_o, output src_rdy_o, input dst_rdy_i); - - fifo_short #(.WIDTH(11)) fifo_short - (.clk(clk), .reset(reset), .clear(clear), - .datain({error_i,eof_i,sof_i,datain}), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), - .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); - -endmodule // ll8_shortfifo diff --git a/control_lib/newfifo/ll8_to_fifo19.v b/control_lib/newfifo/ll8_to_fifo19.v deleted file mode 100644 index af3b91afb..000000000 --- a/control_lib/newfifo/ll8_to_fifo19.v +++ /dev/null @@ -1,73 +0,0 @@ - -module ll8_to_fifo19 - (input clk, input reset, input clear, - input [7:0] ll_data, - input ll_sof_n, - input ll_eof_n, - input ll_src_rdy_n, - output ll_dst_rdy_n, - - output [18:0] f19_data, - output f19_src_rdy_o, - input f19_dst_rdy_i ); - - localparam XFER_EMPTY = 0; - localparam XFER_HALF = 1; - localparam XFER_HALF_WRITE = 3; - - // Why anybody would use active low in an FPGA is beyond me... - wire ll_sof = ~ll_sof_n; - wire ll_eof = ~ll_eof_n; - wire ll_src_rdy = ~ll_src_rdy_n; - wire ll_dst_rdy; - assign ll_dst_rdy_n = ~ll_dst_rdy; - - wire xfer_out = f19_src_rdy_o & f19_dst_rdy_i; - wire xfer_in = ll_src_rdy & ll_dst_rdy; - - reg hold_sof; - wire f19_sof, f19_eof, f19_occ; - - reg [1:0] state; - reg [7:0] hold_reg; - - always @(posedge clk) - if(ll_src_rdy & (state==XFER_EMPTY)) - hold_reg <= ll_data; - - always @(posedge clk) - if(ll_sof & (state==XFER_EMPTY)) - hold_sof <= 1; - else if(xfer_out) - hold_sof <= 0; - - always @(posedge clk) - if(reset | clear) - state <= XFER_EMPTY; - else - case(state) - XFER_EMPTY : - if(ll_src_rdy) - if(ll_eof) - state <= XFER_HALF_WRITE; - else - state <= XFER_HALF; - XFER_HALF : - if(ll_src_rdy & f19_dst_rdy_i) - state <= XFER_EMPTY; - XFER_HALF_WRITE : - if(f19_dst_rdy_i) - state <= XFER_EMPTY; - endcase // case (state) - - assign ll_dst_rdy = (state==XFER_EMPTY) | ((state==XFER_HALF)&f19_dst_rdy_i); - assign f19_src_rdy_o = (state==XFER_HALF_WRITE) | ((state==XFER_HALF)&ll_src_rdy); - - assign f19_sof = hold_sof | (ll_sof & (state==XFER_HALF)); - assign f19_eof = (state == XFER_HALF_WRITE) | ll_eof; - assign f19_occ = (state == XFER_HALF_WRITE); - - assign f19_data = {f19_occ,f19_eof,f19_sof,hold_reg,ll_data}; - -endmodule // ll8_to_fifo19 - diff --git a/control_lib/newfifo/ll8_to_fifo36.v b/control_lib/newfifo/ll8_to_fifo36.v deleted file mode 100644 index 108daa903..000000000 --- a/control_lib/newfifo/ll8_to_fifo36.v +++ /dev/null @@ -1,97 +0,0 @@ - -module ll8_to_fifo36 - (input clk, input reset, input clear, - input [7:0] ll_data, - input ll_sof_n, - input ll_eof_n, - input ll_src_rdy_n, - output ll_dst_rdy_n, - - output [35:0] f36_data, - output f36_src_rdy_o, - input f36_dst_rdy_i ); - - wire f36_write = f36_src_rdy_o & f36_dst_rdy_i; - - // Why anybody would use active low in an FPGA is beyond me... - wire ll_sof = ~ll_sof_n; - wire ll_eof = ~ll_eof_n; - wire ll_src_rdy = ~ll_src_rdy_n; - wire ll_dst_rdy; - assign ll_dst_rdy_n = ~ll_dst_rdy; - - reg f36_sof, f36_eof; - reg [1:0] f36_occ; - - - reg [2:0] state; - reg [7:0] dat0, dat1, dat2, dat3; - - always @(posedge clk) - if(ll_src_rdy & ((state==0)|f36_write)) - f36_sof <= ll_sof; - - always @(posedge clk) - if(ll_src_rdy & ((state !=4)|f36_write)) - f36_eof <= ll_eof; - - always @(posedge clk) - if(ll_eof) - f36_occ <= state[1:0] + 1; - else - f36_occ <= 0; - - always @(posedge clk) - if(reset) - state <= 0; - else - if(ll_src_rdy) - case(state) - 0 : - if(ll_eof) - state <= 4; - else - state <= 1; - 1 : - if(ll_eof) - state <= 4; - else - state <= 2; - 2 : - if(ll_eof) - state <= 4; - else - state <= 3; - 3 : state <= 4; - 4 : - if(f36_dst_rdy_i) - if(ll_eof) - state <= 4; - else - state <= 1; - endcase // case(state) - else - if(f36_write) - state <= 0; - - always @(posedge clk) - if(ll_src_rdy & (state==3)) - dat3 <= ll_data; - - always @(posedge clk) - if(ll_src_rdy & (state==2)) - dat2 <= ll_data; - - always @(posedge clk) - if(ll_src_rdy & (state==1)) - dat1 <= ll_data; - - always @(posedge clk) - if(ll_src_rdy & ((state==0) | f36_write)) - dat0 <= ll_data; - - assign ll_dst_rdy = f36_dst_rdy_i | (state != 4); - assign f36_data = {f36_occ,f36_eof,f36_sof,dat0,dat1,dat2,dat3}; // FIXME endianess - assign f36_src_rdy_o = (state == 4); - -endmodule // ll8_to_fifo36 diff --git a/control_lib/nsgpio.v b/control_lib/nsgpio.v deleted file mode 100644 index 937ea7020..000000000 --- a/control_lib/nsgpio.v +++ /dev/null @@ -1,107 +0,0 @@ -// Modified from code originally by Richard Herveille, his copyright is below - -///////////////////////////////////////////////////////////////////// -//// //// -//// OpenCores Simple General Purpose IO core //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - - -module nsgpio - (input clk_i, input rst_i, - input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [31:0] dat_i, - output reg [31:0] dat_o, output reg ack_o, - input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1, - inout [31:0] gpio - ); - - reg [63:0] ctrl; - reg [31:0] line; - reg [31:0] lgpio; // LatchedGPIO pins - reg [31:0] ddr; - - wire wb_acc = cyc_i & stb_i; // WISHBONE access - wire wb_wr = wb_acc & we_i; // WISHBONE write access - - always @(posedge clk_i or posedge rst_i) - if (rst_i) - begin - ctrl <= 64'h0; - line <= 0; - end - else if (wb_wr) - case( adr_i[3:2] ) - 2'b00 : - line <= dat_i; - 2'b01 : - ddr[31:0] <= dat_i; - 2'b10 : - ctrl[63:32] <= dat_i; - 2'b11 : - ctrl[31:0] <= dat_i; - endcase // case( adr_i[3:2] ) - - always @(posedge clk_i) - case (adr_i[3:2]) - 2'b00 : - dat_o <= lgpio; - 2'b01 : - dat_o <= ddr; - 2'b10 : - dat_o <= ctrl[63:32]; - 2'b11 : - dat_o <= ctrl[31:0]; - endcase // case(adr_i[3:2]) - - always @(posedge clk_i or posedge rst_i) - if (rst_i) - ack_o <= 1'b0; - else - ack_o <= wb_acc & !ack_o; - - // latch GPIO input pins - always @(posedge clk_i) - lgpio <= gpio; - - // assign GPIO outputs - integer n; - reg [31:0] igpio; // temporary internal signal - - always @(ctrl or line or debug_1 or debug_0 or atr) - for(n=0;n<32;n=n+1) - igpio[n] <= ddr[n] ? (ctrl[2*n+1] ? (ctrl[2*n] ? debug_1[n] : debug_0[n]) : - (ctrl[2*n] ? atr[n] : line[n]) ) - : 1'bz; - - assign gpio = igpio; - -endmodule - diff --git a/control_lib/oneshot_2clk.v b/control_lib/oneshot_2clk.v deleted file mode 100644 index 72f16a4b3..000000000 --- a/control_lib/oneshot_2clk.v +++ /dev/null @@ -1,35 +0,0 @@ - -// Retime a single bit from one clock domain to another -// Guarantees that no matter what the relative clock rates, if the in signal is high for at least -// one clock cycle in the clk_in domain, then the out signal will be high for at least one -// clock cycle in the clk_out domain. If the in signal goes high again before the process is done -// the behavior is undefined. No other guarantees. Designed for passing reset into a new -// clock domain. - -module oneshot_2clk - (input clk_in, - input in, - input clk_out, - output reg out); - - reg del_in = 0; - reg sendit = 0, gotit = 0; - reg sendit_d = 0, gotit_d = 0; - - always @(posedge clk_in) del_in <= in; - - always @(posedge clk_in) - if(in & ~del_in) // we have a positive edge - sendit <= 1; - else if(gotit) - sendit <= 0; - - always @(posedge clk_out) sendit_d <= sendit; - always @(posedge clk_out) out <= sendit_d; - - always @(posedge clk_in) gotit_d <= out; - always @(posedge clk_in) gotit <= gotit_d; - -endmodule // oneshot_2clk - - diff --git a/control_lib/pic.v b/control_lib/pic.v deleted file mode 100644 index 9b9944d4a..000000000 --- a/control_lib/pic.v +++ /dev/null @@ -1,183 +0,0 @@ - -// Heavily modified by M. Ettus, 2009, little original code remains -// Modified by M. Ettus, 2008 for 32 bit width - -///////////////////////////////////////////////////////////////////// -//// //// -//// OpenCores Simple Programmable Interrupt Controller //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// -// -// This is a simple Programmable Interrupt Controller. -// The number of interrupts is depending on the databus size. -// There's one interrupt input per databit (i.e. 16 interrupts for a 16 -// bit databus). -// All attached devices share the same CPU priority level. -// -// -// -// Registers: -// -// 0x00: EdgeEnable Register -// bits 7:0 R/W Edge Enable '1' = edge triggered interrupt source -// '0' = level triggered interrupt source -// 0x01: PolarityRegister -// bits 7:0 R/W Polarity '1' = high level / rising edge -// '0' = low level / falling edge -// 0x02: MaskRegister -// bits 7:0 R/W Mask '1' = interrupt masked (disabled) -// '0' = interrupt not masked (enabled) -// 0x03: PendingRegister -// bits 7:0 R/W Pending '1' = interrupt pending -// '0' = no interrupt pending -// -// A CPU interrupt is generated when an interrupt is pending and its -// MASK bit is cleared. -// -// -// -// HOWTO: -// -// Clearing pending interrupts: -// Writing a '1' to a bit in the interrupt pending register clears the -// interrupt. Make sure to clear the interrupt at the source before -// writing to the interrupt pending register. Otherwise the interrupt -// will be set again. -// -// Priority based interrupts: -// Upon reception of an interrupt, check the interrupt register and -// determine the highest priority interrupt. Mask all interrupts from the -// current level to the lowest level. This negates the interrupt line, and -// makes sure only interrupts with a higher level are triggered. After -// completion of the interrupt service routine, clear the interrupt source, -// the interrupt bit in the pending register, and restore the MASK register -// to it's previous state. -// -// Addapt the core for fewer interrupt sources: -// If less than 8 interrupt sources are required, than the 'is' parameter -// can be set to the amount of required interrupts. Interrupts are mapped -// starting at the LSBs. So only the 'is' LSBs per register are valid. All -// other bits (i.e. the 8-'is' MSBs) are set to zero '0'. -// Codesize is approximately linear to the amount of interrupts. I.e. using -// 4 instead of 8 interrupt sources reduces the size by approx. half. -// - - -module pic - (input clk_i, input rst_i, input cyc_i, input stb_i, - input [2:0] adr_i, - input we_i, - input [31:0] dat_i, - output reg [31:0] dat_o, - output reg ack_o, - output reg int_o, - input [31:0] irq - ); - - reg [31:0] pol, edgen, pending, mask; // register bank - reg [31:0] lirq, dirq; // latched irqs, delayed latched irqs - - // latch interrupt inputs - always @(posedge clk_i) - lirq <= irq; - - // generate delayed latched irqs - always @(posedge clk_i) - dirq <= lirq; - - // generate actual triggers - function trigger; - input edgen, pol, lirq, dirq; - reg edge_irq, level_irq; - begin - edge_irq = pol ? (lirq & ~dirq) : (dirq & ~lirq); - level_irq = pol ? lirq : ~lirq; - trigger = edgen ? edge_irq : level_irq; - end - endfunction - - reg [31:0] irq_event; - integer n; - always @(posedge clk_i) - for(n = 0; n < 32; n = n+1) - irq_event[n] <= trigger(edgen[n], pol[n], lirq[n], dirq[n]); - - // generate wishbone register bank writes - wire wb_acc = cyc_i & stb_i; // WISHBONE access - wire wb_wr = wb_acc & we_i; // WISHBONE write access - - always @(posedge clk_i) - if (rst_i) - begin - pol <= 0; // clear polarity register - edgen <= 0; // clear edge enable register - mask <= 0; // mask all interrupts - end - else if(wb_wr) // wishbone write cycle?? - case (adr_i) // synopsys full_case parallel_case - 3'd0 : edgen <= dat_i; // EDGE-ENABLE register - 3'd1 : pol <= dat_i; // POLARITY register - 3'd2 : mask <= dat_i; // MASK register - 3'd3 : ; // PENDING register is a special case (see below) - 3'd4 : ; // Priority encoded live (pending & ~mask) - endcase - - // pending register is a special case - always @(posedge clk_i) - if (rst_i) - pending <= 0; // clear all pending interrupts - else if ( wb_wr & (adr_i == 3'd3) ) - pending <= (pending & ~dat_i) | irq_event; - else - pending <= pending | irq_event; - - wire [31:0] live_enc; - priority_enc priority_enc ( .in(pending & ~mask), .out(live_enc) ); - - always @(posedge clk_i) - case (adr_i) // synopsys full_case parallel_case - 3'd0 : dat_o <= edgen; - 3'd1 : dat_o <= pol; - 3'd2 : dat_o <= mask; - 3'd3 : dat_o <= pending; - 3'd4 : dat_o <= live_enc; - endcase - - always @(posedge clk_i) - ack_o <= wb_acc & !ack_o; - - always @(posedge clk_i) - if(rst_i) - int_o <= 0; - else - int_o <= |(pending & ~mask); - -endmodule diff --git a/control_lib/priority_enc.v b/control_lib/priority_enc.v deleted file mode 100644 index 916192445..000000000 --- a/control_lib/priority_enc.v +++ /dev/null @@ -1,44 +0,0 @@ - -module priority_enc - (input [31:0] in, - output reg [31:0] out); - - always @* - casex(in) - 32'b1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 31; - 32'b01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 30; - 32'b001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 29; - 32'b0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 28; - 32'b0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 27; - 32'b0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 26; - 32'b0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 25; - 32'b0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 24; - 32'b0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 23; - 32'b0000_0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 22; - 32'b0000_0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 21; - 32'b0000_0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 20; - 32'b0000_0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx : out <= 19; - 32'b0000_0000_0000_01xx_xxxx_xxxx_xxxx_xxxx : out <= 18; - 32'b0000_0000_0000_001x_xxxx_xxxx_xxxx_xxxx : out <= 17; - 32'b0000_0000_0000_0001_xxxx_xxxx_xxxx_xxxx : out <= 16; - 32'b0000_0000_0000_0000_1xxx_xxxx_xxxx_xxxx : out <= 15; - 32'b0000_0000_0000_0000_01xx_xxxx_xxxx_xxxx : out <= 14; - 32'b0000_0000_0000_0000_001x_xxxx_xxxx_xxxx : out <= 13; - 32'b0000_0000_0000_0000_0001_xxxx_xxxx_xxxx : out <= 12; - 32'b0000_0000_0000_0000_0000_1xxx_xxxx_xxxx : out <= 11; - 32'b0000_0000_0000_0000_0000_01xx_xxxx_xxxx : out <= 10; - 32'b0000_0000_0000_0000_0000_001x_xxxx_xxxx : out <= 9; - 32'b0000_0000_0000_0000_0000_0001_xxxx_xxxx : out <= 8; - 32'b0000_0000_0000_0000_0000_0000_1xxx_xxxx : out <= 7; - 32'b0000_0000_0000_0000_0000_0000_01xx_xxxx : out <= 6; - 32'b0000_0000_0000_0000_0000_0000_001x_xxxx : out <= 5; - 32'b0000_0000_0000_0000_0000_0000_0001_xxxx : out <= 4; - 32'b0000_0000_0000_0000_0000_0000_0000_1xxx : out <= 3; - 32'b0000_0000_0000_0000_0000_0000_0000_01xx : out <= 2; - 32'b0000_0000_0000_0000_0000_0000_0000_001x : out <= 1; - 32'b0000_0000_0000_0000_0000_0000_0000_0001 : out <= 0; - 32'b0000_0000_0000_0000_0000_0000_0000_0000 : out <= 32'hFFFF_FFFF; - default : out <= 32'hFFFF_FFFF; - endcase // casex (in) - -endmodule // priority_enc diff --git a/control_lib/ram_2port.v b/control_lib/ram_2port.v deleted file mode 100644 index 6c8332b9c..000000000 --- a/control_lib/ram_2port.v +++ /dev/null @@ -1,42 +0,0 @@ - - -module ram_2port - #(parameter DWIDTH=32, - parameter AWIDTH=9) - (input clka, - input ena, - input wea, - input [AWIDTH-1:0] addra, - input [DWIDTH-1:0] dia, - output reg [DWIDTH-1:0] doa, - - input clkb, - input enb, - input web, - input [AWIDTH-1:0] addrb, - input [DWIDTH-1:0] dib, - output reg [DWIDTH-1:0] dob); - - reg [DWIDTH-1:0] ram [(1<>1)); - wire latch_dat = (clk_ctr == (clk_div - 8'd2)); - wire send_clk_lo = (clk_ctr == (clk_div - 8'd1)); - - wire send_bit = (bit_ready && (bit_ctr != 0)); - assign ready = (bit_ctr == 0); - - always @(posedge clk) - if(rst) - clk_ctr <= 0; - else if(bit_done) - clk_ctr <= 0; - else if(bit_busy) - clk_ctr <= clk_ctr + 1; - else if(send_bit) - clk_ctr <= 1; - - always @(posedge clk) - if(rst) - sd_clk <= 0; - else if(send_clk_hi) - sd_clk <= 1; - else if(send_clk_lo) - sd_clk <= 0; - - always @(posedge clk) - if(rst) - bit_ctr <= 0; - else if(bit_done) - if(bit_ctr == 4'd8) - bit_ctr <= 0; - else - bit_ctr <= bit_ctr + 1; - else if(bit_ready & go) - bit_ctr <= 1; - - reg [7:0] shift_reg; - always @(posedge clk) - if(go) - shift_reg <= send_dat; - else if(latch_dat) - shift_reg <= {shift_reg[6:0],sd_miso}; - - assign sd_mosi = shift_reg[7]; - assign rcv_dat = shift_reg; - -endmodule // sd_spi diff --git a/control_lib/sd_spi_tb.v b/control_lib/sd_spi_tb.v deleted file mode 100644 index e30a5bdf6..000000000 --- a/control_lib/sd_spi_tb.v +++ /dev/null @@ -1,40 +0,0 @@ - - -module sd_spi_tb; - - reg clk = 0; - always #5 clk = ~clk; - reg rst = 1; - initial #32 rst = 0; - - wire sd_clk, sd_mosi, sd_miso; - wire [7:0] clk_div = 12; - wire [7:0] send_dat = 23; - wire [7:0] rcv_dat; - - wire ready; - reg go = 0; - initial - begin - repeat (100) - @(posedge clk); - go <= 1; - @(posedge clk); - go <= 0; - end - - sd_spi dut(.clk(clk),.rst(rst), - .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso), - .clk_div(clk_div),.send_dat(send_dat),.rcv_dat(rcv_dat), - .go(go),.ready(ready) ); - - initial - begin - $dumpfile("sd_spi_tb.vcd"); - $dumpvars(0,sd_spi_tb); - end - - initial - #10000 $finish(); - -endmodule // sd_spi_tb diff --git a/control_lib/sd_spi_wb.v b/control_lib/sd_spi_wb.v deleted file mode 100644 index 7a6258b56..000000000 --- a/control_lib/sd_spi_wb.v +++ /dev/null @@ -1,76 +0,0 @@ - -// Wishbone module for spi communications with an SD Card -// The programming interface is simple -- -// Write the desired clock divider to address 1 (should be 1 or higher) -// Status is in address 0. A 1 indicates the last transaction is done and it is safe to -// send another -// Writing a byte to address 2 sends that byte over SPI. When it is done, -// status (addr 0) goes high again, and the received byte can be read from address 3. - -module sd_spi_wb - (input clk, - input rst, - - // SD Card interface - output sd_clk, - output sd_csn, - output sd_mosi, - input sd_miso, - - input wb_cyc_i, - input wb_stb_i, - input wb_we_i, - input [1:0] wb_adr_i, - input [7:0] wb_dat_i, - output reg [7:0] wb_dat_o, - output reg wb_ack_o); - - localparam ADDR_STATUS = 0; - localparam ADDR_CLKDIV = 1; - localparam ADDR_WRITE = 2; - localparam ADDR_READ = 3; - - wire [7:0] status, rcv_dat; - reg [7:0] clkdiv; - wire ready; - reg ack_d1; - - reg cs_reg; - assign sd_csn = ~cs_reg; // FIXME - - always @(posedge clk) - if(rst) ack_d1 <= 0; - else ack_d1 <= wb_ack_o; - - always @(posedge clk) - if(rst) wb_ack_o <= 0; - else wb_ack_o <= wb_cyc_i & wb_stb_i & ~ack_d1; - - always @(posedge clk) - case(wb_adr_i) - ADDR_STATUS : wb_dat_o <= {7'd0,ready}; - ADDR_CLKDIV : wb_dat_o <= clkdiv; - ADDR_READ : wb_dat_o <= rcv_dat; - default : wb_dat_o <= 0; - endcase // case(wb_adr_i) - - always @(posedge clk) - if(rst) - begin - clkdiv <= 200; - cs_reg <= 0; - end - else if(wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o) - case(wb_adr_i) - ADDR_STATUS : cs_reg <= wb_dat_i; - ADDR_CLKDIV : clkdiv <= wb_dat_i; - endcase // case(wb_adr_i) - - wire go = wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o & (wb_adr_i == ADDR_WRITE); - - sd_spi sd_spi(.clk(clk),.rst(rst), - .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso), - .clk_div(clkdiv),.send_dat(wb_dat_i),.rcv_dat(rcv_dat), - .go(go),.ready(ready) ); - -endmodule // sd_spi_wb diff --git a/control_lib/setting_reg.v b/control_lib/setting_reg.v deleted file mode 100644 index c8aff230f..000000000 --- a/control_lib/setting_reg.v +++ /dev/null @@ -1,23 +0,0 @@ - - -module setting_reg - #(parameter my_addr = 0, parameter at_reset=32'd0) - (input clk, input rst, input strobe, input wire [7:0] addr, - input wire [31:0] in, output reg [31:0] out, output reg changed); - - always @(posedge clk) - if(rst) - begin - out <= at_reset; - changed <= 1'b0; - end - else - if(strobe & (my_addr==addr)) - begin - out <= in; - changed <= 1'b1; - end - else - changed <= 1'b0; - -endmodule // setting_reg diff --git a/control_lib/settings_bus.v b/control_lib/settings_bus.v deleted file mode 100644 index d01a30ab4..000000000 --- a/control_lib/settings_bus.v +++ /dev/null @@ -1,49 +0,0 @@ - -// Grab settings off the wishbone bus, send them out to our simpler bus on the fast clock - -module settings_bus - #(parameter AWIDTH=16, parameter DWIDTH=32) - (input wb_clk, - input wb_rst, - input [AWIDTH-1:0] wb_adr_i, - input [DWIDTH-1:0] wb_dat_i, - input wb_stb_i, - input wb_we_i, - output reg wb_ack_o, - input sys_clk, - output strobe, - output reg [7:0] addr, - output reg [31:0] data); - - reg stb_int, stb_int_d1; - - always @(posedge wb_clk) - if(wb_rst) - begin - stb_int <= 1'b0; - addr <= 8'd0; - data <= 32'd0; - end - else if(wb_we_i & wb_stb_i) - begin - stb_int <= 1'b1; - addr <= wb_adr_i[9:2]; - data <= wb_dat_i; - end - else - stb_int <= 1'b0; - - always @(posedge wb_clk) - if(wb_rst) - wb_ack_o <= 0; - else - wb_ack_o <= wb_stb_i & ~wb_ack_o; - - always @(posedge wb_clk) - stb_int_d1 <= stb_int; - - //assign strobe = stb_int & ~stb_int_d1; - assign strobe = stb_int & wb_ack_o; - -endmodule // settings_bus - diff --git a/control_lib/shortfifo.v b/control_lib/shortfifo.v deleted file mode 100644 index d8ce1428e..000000000 --- a/control_lib/shortfifo.v +++ /dev/null @@ -1,87 +0,0 @@ - -module shortfifo - #(parameter WIDTH=32) - (input clk, input rst, - input [WIDTH-1:0] datain, - output [WIDTH-1:0] dataout, - input read, - input write, - input clear, - output reg full, - output reg empty, - output reg [4:0] space, - output reg [4:0] occupied); - - reg [3:0] a; - genvar i; - - generate - for (i=0;i>1); - wire stop_now = (bit_ctr == 10) && shift_now; - wire go_now = (bit_ctr == 0) && neg_trans; - - always @(posedge clk) - if(rst) - sr <= 0; - else if(shift_now) - sr <= {rx_d2,sr[7:1]}; - - always @(posedge clk) - if(rst) - baud_ctr <= 0; - else - if(go_now) - baud_ctr <= 1; - else if(stop_now) - baud_ctr <= 0; - else if(baud_ctr >= clkdiv) - baud_ctr <= 1; - else if(baud_ctr != 0) - baud_ctr <= baud_ctr + 1; - - always @(posedge clk) - if(rst) - bit_ctr <= 0; - else - if(go_now) - bit_ctr <= 1; - else if(stop_now) - bit_ctr <= 0; - else if(baud_ctr == clkdiv) - bit_ctr <= bit_ctr + 1; - - wire full; - wire write = ~full & rx_d2 & stop_now; - - medfifo #(.WIDTH(8),.DEPTH(DEPTH)) fifo - (.clk(clk),.rst(rst), - .datain(sr),.write(write),.full(full), - .dataout(fifo_out),.read(fifo_read),.empty(fifo_empty), - .clear(0),.space(),.occupied(fifo_level) ); - -endmodule // simple_uart_rx diff --git a/control_lib/simple_uart_tx.v b/control_lib/simple_uart_tx.v deleted file mode 100644 index e11a347ed..000000000 --- a/control_lib/simple_uart_tx.v +++ /dev/null @@ -1,60 +0,0 @@ - -module simple_uart_tx - #(parameter DEPTH=0) - (input clk, input rst, - input [7:0] fifo_in, input fifo_write, output [7:0] fifo_level, output fifo_full, - input [15:0] clkdiv, output baudclk, output reg tx); - - reg [15:0] baud_ctr; - reg [3:0] bit_ctr; - - wire read, empty; - wire [7:0] char_to_send; - - medfifo #(.WIDTH(8),.DEPTH(DEPTH)) fifo - (.clk(clk),.rst(rst), - .datain(fifo_in),.write(fifo_write),.full(fifo_full), - .dataout(char_to_send),.read(read),.empty(empty), - .clear(0),.space(fifo_level),.occupied() ); - - always @(posedge clk) - if(rst) - baud_ctr <= 0; - else if (baud_ctr >= clkdiv) - baud_ctr <= 0; - else - baud_ctr <= baud_ctr + 1; - - always @(posedge clk) - if(rst) - bit_ctr <= 0; - else if(baud_ctr == clkdiv) - if(bit_ctr == 9) - bit_ctr <= 0; - else if(bit_ctr != 0) - bit_ctr <= bit_ctr + 1; - else if(~empty) - bit_ctr <= 1; - - always @(posedge clk) - if(rst) - tx <= 1; - else - case(bit_ctr) - 0 : tx <= 1; - 1 : tx <= 0; - 2 : tx <= char_to_send[0]; - 3 : tx <= char_to_send[1]; - 4 : tx <= char_to_send[2]; - 5 : tx <= char_to_send[3]; - 6 : tx <= char_to_send[4]; - 7 : tx <= char_to_send[5]; - 8 : tx <= char_to_send[6]; - 9 : tx <= char_to_send[7]; - default : tx <= 1; - endcase // case(bit_ctr) - - assign read = (bit_ctr == 9) && (baud_ctr == clkdiv); - assign baudclk = (baud_ctr == 1); // Only for debug purposes - -endmodule // simple_uart_tx diff --git a/control_lib/spi.v b/control_lib/spi.v deleted file mode 100644 index a80c488e9..000000000 --- a/control_lib/spi.v +++ /dev/null @@ -1,84 +0,0 @@ - - -// AD9510 Register Map (from datasheet Rev. A) - -/* INSTRUCTION word format (16 bits) - * 15 Read = 1, Write = 0 - * 14:13 W1/W0, Number of bytes 00 - 1, 01 - 2, 10 - 3, 11 - stream - * 12:0 Address - */ - -/* ADDR Contents Value (hex) - * 00 Serial Config Port 10 (def) -- MSB first, SDI/SDO separate - * 04 A Counter - * 05-06 B Counter - * 07-0A PLL Control - * 0B-0C R Divider - * 0D PLL Control - * 34-3A Fine Delay - * 3C-3F LVPECL Outs - * 40-43 LVDS/CMOS Outs - * 45 Clock select, power down - * 48-57 Dividers - * 58 Func and Sync - * 5A Update regs - */ - - -module spi - (input reset, - input clk, - - // SPI signals - output sen, - output sclk, - input sdi, - output sdo, - - // Interfaces - input read_1, - input write_1, - input [15:0] command_1, - input [15:0] wdata_1, - output [15:0] rdata_1, - output reg done_1, - input msb_first_1, - input [5:0] command_width_1, - input [5:0] data_width_1, - input [7:0] clkdiv_1 - - ); - - reg [15:0] command, wdata, rdata; - reg done; - - always @(posedge clk) - if(reset) - done_1 <= #1 1'b0; - - always @(posedge clk) - if(reset) - begin - counter <= #1 7'd0; - command <= #1 20'd0; - end - else if(start) - begin - counter <= #1 7'd1; - command <= #1 {read,w,addr_data}; - end - else if( |counter && ~done ) - begin - counter <= #1 counter + 7'd1; - if(~counter[0]) - command <= {command[22:0],1'b0}; - end - - wire done = (counter == 8'd49); - - assign sen = (done | counter == 8'd0); // CSB is high when we're not doing anything - assign sclk = ~counter[0]; - assign sdo = command[23]; - - -endmodule // clock_control diff --git a/control_lib/srl.v b/control_lib/srl.v deleted file mode 100644 index fa28c7669..000000000 --- a/control_lib/srl.v +++ /dev/null @@ -1,21 +0,0 @@ - -module srl - #(parameter WIDTH=18) - (input clk, - input write, - input [WIDTH-1:0] in, - input [3:0] addr, - output [WIDTH-1:0] out); - - genvar i; - generate - for (i=0;i 5) - clock_present <= 1; - else - ; - else - if(abs_diff<3) - clock_present <= 0; - else - rd_counter <= rd_counter + 1; - -endmodule // ss_rcvr diff --git a/control_lib/system_control.v b/control_lib/system_control.v deleted file mode 100644 index 5d89f13db..000000000 --- a/control_lib/system_control.v +++ /dev/null @@ -1,47 +0,0 @@ -// System bootup order: -// 0 - Internal POR to reset this block. Maybe control it from CPLD in the future? -// 1 - Everything in reset -// 2 - Take RAM Loader out of reset -// 3 - When RAM Loader done, take processor and wishbone out of reset - -module system_control - (input wb_clk_i, - output reg ram_loader_rst_o, - output reg wb_rst_o, - input ram_loader_done_i - ); - - reg POR = 1'b1; - reg [3:0] POR_ctr; - - initial POR_ctr = 4'd0; - always @(posedge wb_clk_i) - if(POR_ctr == 4'd15) - POR <= 1'b0; - else - POR_ctr <= POR_ctr + 4'd1; - - always @(posedge POR or posedge wb_clk_i) - if(POR) - ram_loader_rst_o <= 1'b1; - else - ram_loader_rst_o <= #1 1'b0; - - // Main system reset - reg delayed_rst; - - always @(posedge POR or posedge wb_clk_i) - if(POR) - begin - wb_rst_o <= 1'b1; - delayed_rst <= 1'b1; - end - else if(ram_loader_done_i) - begin - delayed_rst <= 1'b0; - wb_rst_o <= delayed_rst; - end - -endmodule // system_control - - diff --git a/control_lib/system_control_tb.v b/control_lib/system_control_tb.v deleted file mode 100644 index a8eff4811..000000000 --- a/control_lib/system_control_tb.v +++ /dev/null @@ -1,57 +0,0 @@ - - -module system_control_tb(); - - reg aux_clk, clk_fpga; - wire wb_clk, dsp_clk; - wire wb_rst, dsp_rst, rl_rst, proc_rst; - - reg rl_done, clock_ready; - - initial aux_clk = 1'b0; - always #25 aux_clk = ~aux_clk; - - initial clk_fpga = 1'b0; - - initial clock_ready = 1'b0; - initial - begin - @(negedge proc_rst); - #1003 clock_ready <= 1'b1; - end - - always #7 clk_fpga = ~clk_fpga; - - initial begin - $dumpfile("system_control_tb.vcd"); - $dumpvars(0,system_control_tb); - end - - initial #10000 $finish; - - initial - begin - @(negedge rl_rst); - rl_done <= 1'b0; - #1325 rl_done <= 1'b1; - end - - initial - begin - @(negedge proc_rst); - clock_ready <= 1'b0; - #327 clock_ready <= 1'b1; - end - - system_control - system_control(.aux_clk_i(aux_clk),.clk_fpga_i(clk_fpga), - .dsp_clk_o(dsp_clk),.wb_clk_o(wb_clk), - .ram_loader_rst_o(rl_rst), - .processor_rst_o(proc_rst), - .wb_rst_o(wb_rst), - .dsp_rst_o(dsp_rst), - .ram_loader_done_i(rl_done), - .clock_ready_i(clock_ready), - .debug_o()); - -endmodule // system_control_tb diff --git a/control_lib/traffic_cop.v b/control_lib/traffic_cop.v deleted file mode 100644 index e7579656a..000000000 --- a/control_lib/traffic_cop.v +++ /dev/null @@ -1,25 +0,0 @@ - -module traffic_cop(); - - -endmodule // traffic_cop - - - -/* - - Traffic Cop to control buffer pool - - Inputs - - Commands - - Basic Operations - - Outputs - - - - - - */ diff --git a/control_lib/wb_1master.v b/control_lib/wb_1master.v deleted file mode 100644 index fb313efae..000000000 --- a/control_lib/wb_1master.v +++ /dev/null @@ -1,464 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE Connection Bus Top Level //// -//// //// -//// //// -//// Original Author: Johny Chi //// -//// chisuhua@yahoo.com.cn //// -//// Modified By Matt Ettus, matt@ettus.com //// -//// //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000, 2007 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// Up to 8 slaves share a Wishbone Bus connection to 1 master - - module wb_1master - #(parameter decode_w = 8, // address decode width - parameter s0_addr = 8'h0, // slave 0 address - parameter s0_mask = 8'h0, // slave 0 don't cares - parameter s1_addr = 8'h0, // slave 1 address - parameter s1_mask = 8'h0, // slave 1 don't cares - parameter s2_addr = 8'h0, // slave 2 address - parameter s2_mask = 8'h0, // slave 2 don't cares - parameter s3_addr = 8'h0, // slave 3 address - parameter s3_mask = 8'h0, // slave 3 don't cares - parameter s4_addr = 8'h0, // slave 4 address - parameter s4_mask = 8'h0, // slave 4 don't cares - parameter s5_addr = 8'h0, // slave 5 address - parameter s5_mask = 8'h0, // slave 5 don't cares - parameter s6_addr = 8'h0, // slave 6 address - parameter s6_mask = 8'h0, // slave 6 don't cares - parameter s7_addr = 8'h0, // slave 7 address - parameter s7_mask = 8'h0, // slave 7 don't cares - parameter s8_addr = 8'h0, // slave 8 address - parameter s8_mask = 8'h0, // slave 8 don't cares - parameter s9_addr = 8'h0, // slave 9 address - parameter s9_mask = 8'h0, // slave 9 don't cares - parameter sa_addr = 8'h0, // slave a address - parameter sa_mask = 8'h0, // slave a don't cares - parameter sb_addr = 8'h0, // slave b address - parameter sb_mask = 8'h0, // slave b don't cares - parameter sc_addr = 8'h0, // slave c address - parameter sc_mask = 8'h0, // slave c don't cares - parameter sd_addr = 8'h0, // slave d address - parameter sd_mask = 8'h0, // slave d don't cares - parameter se_addr = 8'h0, // slave e address - parameter se_mask = 8'h0, // slave e don't cares - parameter sf_addr = 8'h0, // slave f address - parameter sf_mask = 8'h0, // slave f don't cares - - parameter dw = 32, // Data bus Width - parameter aw = 32, // Address bus Width - parameter sw = 4) // Number of Select Lines - - (input clk_i, - input rst_i, - - // Master Interface - input [dw-1:0] m0_dat_i, - output [dw-1:0] m0_dat_o, - input [aw-1:0] m0_adr_i, - input [sw-1:0] m0_sel_i, - input m0_we_i, - input m0_cyc_i, - input m0_stb_i, - output m0_ack_o, - output m0_err_o, - output m0_rty_o, - - // Slave Interfaces - input [dw-1:0] s0_dat_i, - output [dw-1:0] s0_dat_o, - output [aw-1:0] s0_adr_o, - output [sw-1:0] s0_sel_o, - output s0_we_o, - output s0_cyc_o, - output s0_stb_o, - input s0_ack_i, - input s0_err_i, - input s0_rty_i, - - input [dw-1:0] s1_dat_i, - output [dw-1:0] s1_dat_o, - output [aw-1:0] s1_adr_o, - output [sw-1:0] s1_sel_o, - output s1_we_o, - output s1_cyc_o, - output s1_stb_o, - input s1_ack_i, - input s1_err_i, - input s1_rty_i, - - input [dw-1:0] s2_dat_i, - output [dw-1:0] s2_dat_o, - output [aw-1:0] s2_adr_o, - output [sw-1:0] s2_sel_o, - output s2_we_o, - output s2_cyc_o, - output s2_stb_o, - input s2_ack_i, - input s2_err_i, - input s2_rty_i, - - input [dw-1:0] s3_dat_i, - output [dw-1:0] s3_dat_o, - output [aw-1:0] s3_adr_o, - output [sw-1:0] s3_sel_o, - output s3_we_o, - output s3_cyc_o, - output s3_stb_o, - input s3_ack_i, - input s3_err_i, - input s3_rty_i, - - input [dw-1:0] s4_dat_i, - output [dw-1:0] s4_dat_o, - output [aw-1:0] s4_adr_o, - output [sw-1:0] s4_sel_o, - output s4_we_o, - output s4_cyc_o, - output s4_stb_o, - input s4_ack_i, - input s4_err_i, - input s4_rty_i, - - input [dw-1:0] s5_dat_i, - output [dw-1:0] s5_dat_o, - output [aw-1:0] s5_adr_o, - output [sw-1:0] s5_sel_o, - output s5_we_o, - output s5_cyc_o, - output s5_stb_o, - input s5_ack_i, - input s5_err_i, - input s5_rty_i, - - input [dw-1:0] s6_dat_i, - output [dw-1:0] s6_dat_o, - output [aw-1:0] s6_adr_o, - output [sw-1:0] s6_sel_o, - output s6_we_o, - output s6_cyc_o, - output s6_stb_o, - input s6_ack_i, - input s6_err_i, - input s6_rty_i, - - input [dw-1:0] s7_dat_i, - output [dw-1:0] s7_dat_o, - output [aw-1:0] s7_adr_o, - output [sw-1:0] s7_sel_o, - output s7_we_o, - output s7_cyc_o, - output s7_stb_o, - input s7_ack_i, - input s7_err_i, - input s7_rty_i, - - input [dw-1:0] s8_dat_i, - output [dw-1:0] s8_dat_o, - output [aw-1:0] s8_adr_o, - output [sw-1:0] s8_sel_o, - output s8_we_o, - output s8_cyc_o, - output s8_stb_o, - input s8_ack_i, - input s8_err_i, - input s8_rty_i, - - input [dw-1:0] s9_dat_i, - output [dw-1:0] s9_dat_o, - output [aw-1:0] s9_adr_o, - output [sw-1:0] s9_sel_o, - output s9_we_o, - output s9_cyc_o, - output s9_stb_o, - input s9_ack_i, - input s9_err_i, - input s9_rty_i, - - input [dw-1:0] sa_dat_i, - output [dw-1:0] sa_dat_o, - output [aw-1:0] sa_adr_o, - output [sw-1:0] sa_sel_o, - output sa_we_o, - output sa_cyc_o, - output sa_stb_o, - input sa_ack_i, - input sa_err_i, - input sa_rty_i, - - input [dw-1:0] sb_dat_i, - output [dw-1:0] sb_dat_o, - output [aw-1:0] sb_adr_o, - output [sw-1:0] sb_sel_o, - output sb_we_o, - output sb_cyc_o, - output sb_stb_o, - input sb_ack_i, - input sb_err_i, - input sb_rty_i, - - input [dw-1:0] sc_dat_i, - output [dw-1:0] sc_dat_o, - output [aw-1:0] sc_adr_o, - output [sw-1:0] sc_sel_o, - output sc_we_o, - output sc_cyc_o, - output sc_stb_o, - input sc_ack_i, - input sc_err_i, - input sc_rty_i, - - input [dw-1:0] sd_dat_i, - output [dw-1:0] sd_dat_o, - output [aw-1:0] sd_adr_o, - output [sw-1:0] sd_sel_o, - output sd_we_o, - output sd_cyc_o, - output sd_stb_o, - input sd_ack_i, - input sd_err_i, - input sd_rty_i, - - input [dw-1:0] se_dat_i, - output [dw-1:0] se_dat_o, - output [aw-1:0] se_adr_o, - output [sw-1:0] se_sel_o, - output se_we_o, - output se_cyc_o, - output se_stb_o, - input se_ack_i, - input se_err_i, - input se_rty_i, - - input [dw-1:0] sf_dat_i, - output [dw-1:0] sf_dat_o, - output [aw-1:0] sf_adr_o, - output [sw-1:0] sf_sel_o, - output sf_we_o, - output sf_cyc_o, - output sf_stb_o, - input sf_ack_i, - input sf_err_i, - input sf_rty_i - ); - - // //////////////////////////////////////////////////////////////// - // - // Local wires - // - - wire [15:0] ssel_dec; - reg [dw-1:0] i_dat_s; // internal share bus , slave data to master - - // Master output Interface - assign m0_dat_o = i_dat_s; - - always @* - case(ssel_dec) - 1 : i_dat_s <= s0_dat_i; - 2 : i_dat_s <= s1_dat_i; - 4 : i_dat_s <= s2_dat_i; - 8 : i_dat_s <= s3_dat_i; - 16 : i_dat_s <= s4_dat_i; - 32 : i_dat_s <= s5_dat_i; - 64 : i_dat_s <= s6_dat_i; - 128 : i_dat_s <= s7_dat_i; - 256 : i_dat_s <= s8_dat_i; - 512 : i_dat_s <= s9_dat_i; - 1024 : i_dat_s <= sa_dat_i; - 2048 : i_dat_s <= sb_dat_i; - 4096 : i_dat_s <= sc_dat_i; - 8192 : i_dat_s <= sd_dat_i; - 16384 : i_dat_s <= se_dat_i; - 32768 : i_dat_s <= sf_dat_i; - default : i_dat_s <= s0_dat_i; - endcase // case(ssel_dec) - - assign {m0_ack_o, m0_err_o, m0_rty_o} - = {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i | - s8_ack_i | s9_ack_i | sa_ack_i | sb_ack_i | sc_ack_i | sd_ack_i | se_ack_i | sf_ack_i , - s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i | - s8_err_i | s9_err_i | sa_err_i | sb_err_i | sc_err_i | sd_err_i | se_err_i | sf_err_i , - s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i | - s8_rty_i | s9_rty_i | sa_rty_i | sb_rty_i | sc_rty_i | sd_rty_i | se_rty_i | sf_rty_i }; - - // Slave output interfaces - assign s0_adr_o = m0_adr_i; - assign s0_sel_o = m0_sel_i; - assign s0_dat_o = m0_dat_i; - assign s0_we_o = m0_we_i; - assign s0_cyc_o = m0_cyc_i; - assign s0_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[0]; - - assign s1_adr_o = m0_adr_i; - assign s1_sel_o = m0_sel_i; - assign s1_dat_o = m0_dat_i; - assign s1_we_o = m0_we_i; - assign s1_cyc_o = m0_cyc_i; - assign s1_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[1]; - - assign s2_adr_o = m0_adr_i; - assign s2_sel_o = m0_sel_i; - assign s2_dat_o = m0_dat_i; - assign s2_we_o = m0_we_i; - assign s2_cyc_o = m0_cyc_i; - assign s2_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[2]; - - assign s3_adr_o = m0_adr_i; - assign s3_sel_o = m0_sel_i; - assign s3_dat_o = m0_dat_i; - assign s3_we_o = m0_we_i; - assign s3_cyc_o = m0_cyc_i; - assign s3_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[3]; - - assign s4_adr_o = m0_adr_i; - assign s4_sel_o = m0_sel_i; - assign s4_dat_o = m0_dat_i; - assign s4_we_o = m0_we_i; - assign s4_cyc_o = m0_cyc_i; - assign s4_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[4]; - - assign s5_adr_o = m0_adr_i; - assign s5_sel_o = m0_sel_i; - assign s5_dat_o = m0_dat_i; - assign s5_we_o = m0_we_i; - assign s5_cyc_o = m0_cyc_i; - assign s5_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[5]; - - assign s6_adr_o = m0_adr_i; - assign s6_sel_o = m0_sel_i; - assign s6_dat_o = m0_dat_i; - assign s6_we_o = m0_we_i; - assign s6_cyc_o = m0_cyc_i; - assign s6_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[6]; - - assign s7_adr_o = m0_adr_i; - assign s7_sel_o = m0_sel_i; - assign s7_dat_o = m0_dat_i; - assign s7_we_o = m0_we_i; - assign s7_cyc_o = m0_cyc_i; - assign s7_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[7]; - - assign s8_adr_o = m0_adr_i; - assign s8_sel_o = m0_sel_i; - assign s8_dat_o = m0_dat_i; - assign s8_we_o = m0_we_i; - assign s8_cyc_o = m0_cyc_i; - assign s8_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[8]; - - assign s9_adr_o = m0_adr_i; - assign s9_sel_o = m0_sel_i; - assign s9_dat_o = m0_dat_i; - assign s9_we_o = m0_we_i; - assign s9_cyc_o = m0_cyc_i; - assign s9_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[9]; - - assign sa_adr_o = m0_adr_i; - assign sa_sel_o = m0_sel_i; - assign sa_dat_o = m0_dat_i; - assign sa_we_o = m0_we_i; - assign sa_cyc_o = m0_cyc_i; - assign sa_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[10]; - - assign sb_adr_o = m0_adr_i; - assign sb_sel_o = m0_sel_i; - assign sb_dat_o = m0_dat_i; - assign sb_we_o = m0_we_i; - assign sb_cyc_o = m0_cyc_i; - assign sb_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[11]; - - assign sc_adr_o = m0_adr_i; - assign sc_sel_o = m0_sel_i; - assign sc_dat_o = m0_dat_i; - assign sc_we_o = m0_we_i; - assign sc_cyc_o = m0_cyc_i; - assign sc_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[12]; - - assign sd_adr_o = m0_adr_i; - assign sd_sel_o = m0_sel_i; - assign sd_dat_o = m0_dat_i; - assign sd_we_o = m0_we_i; - assign sd_cyc_o = m0_cyc_i; - assign sd_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[13]; - - assign se_adr_o = m0_adr_i; - assign se_sel_o = m0_sel_i; - assign se_dat_o = m0_dat_i; - assign se_we_o = m0_we_i; - assign se_cyc_o = m0_cyc_i; - assign se_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[14]; - - assign sf_adr_o = m0_adr_i; - assign sf_sel_o = m0_sel_i; - assign sf_dat_o = m0_dat_i; - assign sf_we_o = m0_we_i; - assign sf_cyc_o = m0_cyc_i; - assign sf_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[15]; - - // Address decode logic - // WARNING -- must make sure these are mutually exclusive! - - - assign ssel_dec[0] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s0_addr) & s0_mask); - assign ssel_dec[1] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s1_addr) & s1_mask); - assign ssel_dec[2] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s2_addr) & s2_mask); - assign ssel_dec[3] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s3_addr) & s3_mask); - assign ssel_dec[4] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s4_addr) & s4_mask); - assign ssel_dec[5] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s5_addr) & s5_mask); - assign ssel_dec[6] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s6_addr) & s6_mask); - assign ssel_dec[7] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s7_addr) & s7_mask); - assign ssel_dec[8] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s8_addr) & s8_mask); - assign ssel_dec[9] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s9_addr) & s9_mask); - assign ssel_dec[10] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sa_addr) & sa_mask); - assign ssel_dec[11] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sb_addr) & sb_mask); - assign ssel_dec[12] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sc_addr) & sc_mask); - assign ssel_dec[13] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sd_addr) & sd_mask); - assign ssel_dec[14] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ se_addr) & se_mask); - assign ssel_dec[15] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sf_addr) & sf_mask); - -/* - assign ssel_dec[0] = (m0_adr_i[aw -1 : aw - decode_w ] == s0_addr); - assign ssel_dec[1] = (m0_adr_i[aw -1 : aw - decode_w ] == s1_addr); - assign ssel_dec[2] = (m0_adr_i[aw -1 : aw - decode_w ] == s2_addr); - assign ssel_dec[3] = (m0_adr_i[aw -1 : aw - decode_w ] == s3_addr); - assign ssel_dec[4] = (m0_adr_i[aw -1 : aw - decode_w ] == s4_addr); - assign ssel_dec[5] = (m0_adr_i[aw -1 : aw - decode_w ] == s5_addr); - assign ssel_dec[6] = (m0_adr_i[aw -1 : aw - decode_w ] == s6_addr); - assign ssel_dec[7] = (m0_adr_i[aw -1 : aw - decode_w ] == s7_addr); - assign ssel_dec[8] = (m0_adr_i[aw -1 : aw - decode_w ] == s8_addr); - assign ssel_dec[9] = (m0_adr_i[aw -1 : aw - decode_w ] == s9_addr); - assign ssel_dec[10] = (m0_adr_i[aw -1 : aw - decode_w ] == sa_addr); - assign ssel_dec[11] = (m0_adr_i[aw -1 : aw - decode_w ] == sb_addr); - assign ssel_dec[12] = (m0_adr_i[aw -1 : aw - decode_w ] == sc_addr); - assign ssel_dec[13] = (m0_adr_i[aw -1 : aw - decode_w ] == sd_addr); - assign ssel_dec[14] = (m0_adr_i[aw -1 : aw - decode_w ] == se_addr); - assign ssel_dec[15] = (m0_adr_i[aw -1 : aw - decode_w ] == sf_addr); - */ -endmodule // wb_1master diff --git a/control_lib/wb_bridge_16_32.v b/control_lib/wb_bridge_16_32.v deleted file mode 100644 index 405e25c3c..000000000 --- a/control_lib/wb_bridge_16_32.v +++ /dev/null @@ -1,36 +0,0 @@ - - -module wb_bridge_16_32 - #(parameter AWIDTH=16) - (input wb_clk, input wb_rst, - input A_cyc_i, input A_stb_i, input A_we_i, input [3:0] A_sel_i, - input [AWIDTH-1:0] A_adr_i, input [31:0] A_dat_i, output [31:0] A_dat_o, output A_ack_o, - output B_cyc_o, output B_stb_o, output B_we_o, output [1:0] B_sel_o, - output [AWIDTH-1:0] B_adr_o, output [15:0] B_dat_o, input [15:0] B_dat_i, input B_ack_i - ); - - reg [15:0] holding; - reg phase; - - assign B_adr_o = {A_adr_i[AWIDTH-1:2],phase,1'b0}; - assign B_cyc_o = A_cyc_i; - assign B_stb_o = A_stb_i; - assign B_we_o = A_we_i; - - assign B_dat_o = ~phase ? A_dat_i[15:0] : A_dat_i[31:16]; - assign B_sel_o = ~phase ? A_sel_i[1:0] : A_sel_i[3:2]; - - assign A_dat_o = {B_dat_i,holding}; - assign A_ack_o = phase & B_ack_i; - - always @(posedge wb_clk) - if(wb_rst) - phase <= 0; - else if(B_ack_i) - phase <= ~phase; - - always @(posedge wb_clk) - if(~phase & B_ack_i) - holding <= B_dat_i; - -endmodule // wb_bridge_16_32 diff --git a/control_lib/wb_bus_writer.v b/control_lib/wb_bus_writer.v deleted file mode 100644 index fc148a0ff..000000000 --- a/control_lib/wb_bus_writer.v +++ /dev/null @@ -1,57 +0,0 @@ - -// wb_bus_writer -// -// WB Bus Master device to send a sequence of single-word transactions -// based on a list in a RAM or ROM (FASM interface) -// ROM data format is {WB_ADDR[15:0],WB_DATA[31:0]} -// continues until it gets an all-1s entry - -module wb_bus_writer (input start, - output done, - output reg [15:0] rom_addr, - input [47:0] rom_data, - // WB Master Interface, don't need wb_dat_i - input wb_clk_i, - input wb_rst_i, - output [31:0] wb_dat_o, - input wb_ack_i, - output [15:0] wb_adr_o, - output wb_cyc_o, - output [3:0] wb_sel_o, - output wb_stb_o, - output wb_we_o - ); - -`define IDLE 0 -`define READ 1 - - reg [3:0] state; - - assign done = (state != `IDLE) && (&rom_data); // Done when we see all 1s - - always @(posedge wb_clk_i) - if(wb_rst_i) - begin - rom_addr <= #1 0; - state <= #1 0; - end - else if(start) - begin - rom_addr <= #1 0; - state <= #1 `READ; - end - else if((state == `READ) && wb_ack_i) - if(done) - state <= #1 `IDLE; - else - rom_addr <= #1 rom_addr + 1; - - assign wb_dat_o = rom_data[31:0]; - assign wb_adr_o = rom_data[47:32]; - assign wb_sel_o = 4'b1111; // All writes are the full 32 bits - - assign wb_cyc_o = !done & (state != `IDLE); - assign wb_stb_o = !done & (state != `IDLE); - assign wb_we_o = !done & (state != `IDLE); - -endmodule // wb_bus_writer diff --git a/control_lib/wb_output_pins32.v b/control_lib/wb_output_pins32.v deleted file mode 100644 index 1517f2066..000000000 --- a/control_lib/wb_output_pins32.v +++ /dev/null @@ -1,49 +0,0 @@ - - -// Simple 32-bit Wishbone compatible slave output port -// with 8-bit granularity, modeled after the one in the spec -// Allows for readback -// Assumes a 32-bit wishbone bus -// Lowest order bits get sel[0] -// - -module wb_output_pins32 - (wb_rst_i, wb_clk_i, wb_dat_i, wb_dat_o, - wb_we_i, wb_sel_i, wb_stb_i, wb_ack_o, wb_cyc_i, - port_output); - - input wb_rst_i; - input wb_clk_i; - input wire [31:0] wb_dat_i; - output wire [31:0] wb_dat_o; - input wb_we_i; - input wire [3:0] wb_sel_i; - input wb_stb_i; - output wb_ack_o; - input wb_cyc_i; - - output wire [31:0] port_output; - - reg [31:0] internal_reg; - - always @(posedge wb_clk_i) - if(wb_rst_i) - internal_reg <= #1 32'b0; - else - begin - if(wb_stb_i & wb_we_i & wb_sel_i[0]) - internal_reg[7:0] <= #1 wb_dat_i[7:0]; - if(wb_stb_i & wb_we_i & wb_sel_i[1]) - internal_reg[15:8] <= #1 wb_dat_i[15:8]; - if(wb_stb_i & wb_we_i & wb_sel_i[2]) - internal_reg[23:16] <= #1 wb_dat_i[23:16]; - if(wb_stb_i & wb_we_i & wb_sel_i[3]) - internal_reg[31:24] <= #1 wb_dat_i[31:24]; - end // else: !if(wb_rst_i) - - assign wb_dat_o = internal_reg; - assign port_output = internal_reg; - assign wb_ack_o = wb_stb_i; - -endmodule // wb_output_pins32 - diff --git a/control_lib/wb_ram_block.v b/control_lib/wb_ram_block.v deleted file mode 100644 index 044d34ca4..000000000 --- a/control_lib/wb_ram_block.v +++ /dev/null @@ -1,36 +0,0 @@ - - -// Since this is a block ram, there are no byte-selects and there is a 1-cycle read latency -// These have to be a multiple of 512 lines (2K) long - -module wb_ram_block - #(parameter AWIDTH=9) - (input clk_i, - input stb_i, - input we_i, - input [AWIDTH-1:0] adr_i, - input [31:0] dat_i, - output reg [31:0] dat_o, - output ack_o); - - reg [31:0] distram [0:1<<(AWIDTH-1)]; - - always @(posedge clk_i) - begin - if(stb_i & we_i) - distram[adr_i] <= dat_i; - dat_o <= distram[adr_i]; - end - - reg stb_d1, ack_d1; - always @(posedge clk_i) - stb_d1 <= stb_i; - - always @(posedge clk_i) - ack_d1 <= ack_o; - - assign ack_o = stb_i & (we_i | (stb_d1 & ~ack_d1)); -endmodule // wb_ram_block - - - diff --git a/control_lib/wb_ram_dist.v b/control_lib/wb_ram_dist.v deleted file mode 100644 index cffc2f423..000000000 --- a/control_lib/wb_ram_dist.v +++ /dev/null @@ -1,33 +0,0 @@ - - -module wb_ram_dist - #(parameter AWIDTH=8) - (input clk_i, - input stb_i, - input we_i, - input [AWIDTH-1:0] adr_i, - input [31:0] dat_i, - input [3:0] sel_i, - output [31:0] dat_o, - output ack_o); - - reg [31:0] distram [0:1<<(AWIDTH-1)]; - - always @(posedge clk_i) - begin - if(stb_i & we_i & sel_i[3]) - distram[adr_i][31:24] <= dat_i[31:24]; - if(stb_i & we_i & sel_i[2]) - distram[adr_i][24:16] <= dat_i[24:16]; - if(stb_i & we_i & sel_i[1]) - distram[adr_i][15:8] <= dat_i[15:8]; - if(stb_i & we_i & sel_i[0]) - distram[adr_i][7:0] <= dat_i[7:0]; - end // always @ (posedge clk_i) - - assign dat_o = distram[adr_i]; - assign ack_o = stb_i; - -endmodule // wb_ram_dist - - diff --git a/control_lib/wb_readback_mux.v b/control_lib/wb_readback_mux.v deleted file mode 100644 index 3922b03e3..000000000 --- a/control_lib/wb_readback_mux.v +++ /dev/null @@ -1,60 +0,0 @@ - - -// Note -- clocks must be synchronous (derived from the same source) -// Assumes alt_clk is running at a multiple of wb_clk - -module wb_readback_mux - (input wb_clk_i, - input wb_rst_i, - input wb_stb_i, - input [15:0] wb_adr_i, - output reg [31:0] wb_dat_o, - output reg wb_ack_o, - - input [31:0] word00, - input [31:0] word01, - input [31:0] word02, - input [31:0] word03, - input [31:0] word04, - input [31:0] word05, - input [31:0] word06, - input [31:0] word07, - input [31:0] word08, - input [31:0] word09, - input [31:0] word10, - input [31:0] word11, - input [31:0] word12, - input [31:0] word13, - input [31:0] word14, - input [31:0] word15 - ); - - always @(posedge wb_clk_i) - if(wb_rst_i) - wb_ack_o <= 0; - else - wb_ack_o <= wb_stb_i & ~wb_ack_o; - - always @(posedge wb_clk_i) - case(wb_adr_i[5:2]) - 0 : wb_dat_o <= word00; - 1 : wb_dat_o <= word01; - 2 : wb_dat_o <= word02; - 3 : wb_dat_o <= word03; - 4 : wb_dat_o <= word04; - 5 : wb_dat_o <= word05; - 6 : wb_dat_o <= word06; - 7 : wb_dat_o <= word07; - 8 : wb_dat_o <= word08; - 9 : wb_dat_o <= word09; - 10: wb_dat_o <= word10; - 11: wb_dat_o <= word11; - 12: wb_dat_o <= word12; - 13: wb_dat_o <= word13; - 14: wb_dat_o <= word14; - 15: wb_dat_o <= word15; - endcase // case(addr_reg[3:0]) - -endmodule // wb_readback_mux - - diff --git a/control_lib/wb_regfile_2clock.v b/control_lib/wb_regfile_2clock.v deleted file mode 100644 index e248e5161..000000000 --- a/control_lib/wb_regfile_2clock.v +++ /dev/null @@ -1,107 +0,0 @@ - -module wb_regfile_2clock - (input wb_clk_i, - input wb_rst_i, - input wb_stb_i, - input wb_we_i, - input [15:0] wb_adr_i, - input [3:0] wb_sel_i, - input [31:0] wb_dat_i, - output [31:0] wb_dat_o, - output wb_ack_o, - input alt_clk, - input alt_rst, - - output reg [31:0] reg00, - output reg [31:0] reg01, - output reg [31:0] reg02, - output reg [31:0] reg03, - output reg [31:0] reg04, - output reg [31:0] reg05, - output reg [31:0] reg06, - output reg [31:0] reg07 - ); - - reg [15:0] addr_reg; - reg [3:0] sel_reg; - reg [31:0] dat_reg; - reg wr_ret1, wr_ret2, we_reg, stb_reg; - - always @(posedge wb_clk_i) - if(wb_rst_i) - begin - addr_reg <= 0; - sel_reg <= 0; - dat_reg <= 0; - end - else if(wb_stb_i & wb_we_i) - begin - addr_reg <= wb_adr_i; - sel_reg <= wb_sel_i; - dat_reg <= wb_dat_i; - end - - always @(posedge wb_clk_i) - if(wb_rst_i) - {we_reg,stb_reg} <= 2'b0; - else - {we_reg,stb_reg} <= {wb_we_i,wb_stb_i}; - - assign wb_ack_o = stb_reg; - - always @(posedge alt_clk) - if(alt_rst) - {wr_ret2, wr_ret1} <= 2'b0; - else - {wr_ret2, wr_ret1} <= {wr_ret1, we_reg & stb_reg}; - - always @(posedge alt_clk) - if(alt_rst) - begin - reg00 <= 0; - reg01 <= 0; - reg02 <= 0; - reg03 <= 0; - reg04 <= 0; - reg05 <= 0; - reg06 <= 0; - reg07 <= 0; - end // if (alt_rst) - else if(wr_ret2) - case(addr_reg[4:2]) - 3'd0: reg00 <= { {sel_reg[3] ? dat_reg[31:24] : reg00[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg00[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg00[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg00[7:0]}}; - 3'd1: reg01 <= { {sel_reg[3] ? dat_reg[31:24] : reg01[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg01[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg01[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg01[7:0]}}; - 3'd2: reg02 <= { {sel_reg[3] ? dat_reg[31:24] : reg02[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg02[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg02[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg02[7:0]}}; - 3'd3: reg03 <= { {sel_reg[3] ? dat_reg[31:24] : reg03[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg03[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg03[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg03[7:0]}}; - 3'd4: reg04 <= { {sel_reg[3] ? dat_reg[31:24] : reg04[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg04[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg04[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg04[7:0]}}; - 3'd5: reg05 <= { {sel_reg[3] ? dat_reg[31:24] : reg05[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg05[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg05[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg05[7:0]}}; - 3'd6: reg06 <= { {sel_reg[3] ? dat_reg[31:24] : reg06[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg06[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg06[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg06[7:0]}}; - 3'd7: reg07 <= { {sel_reg[3] ? dat_reg[31:24] : reg07[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg07[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg07[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg07[7:0]}}; - endcase // case(addr_reg[2:0]) - -endmodule // wb_regfile_2clock - diff --git a/control_lib/wb_semaphore.v b/control_lib/wb_semaphore.v deleted file mode 100644 index a9208e6a1..000000000 --- a/control_lib/wb_semaphore.v +++ /dev/null @@ -1,42 +0,0 @@ - -// up to 8 semaphores - -// After a read operation, the semaphore is always locked -// If it was already locked before the read (meaning someone else holds the lock) -// then a 1 is returned -// If it was not already locked (meaning the reader now holds the lock) -// then a 0 is returned - -// A write operation clears the lock - -module wb_semaphore - #(parameter count=8, DBUS_WIDTH=32) - (input wb_clk_i, - input wb_rst_i, - input [DBUS_WIDTH-1:0] wb_dat_i, - input [2:0] wb_adr_i, - input wb_cyc_i, - input wb_stb_i, - input wb_we_i, - output wb_ack_o, - output [DBUS_WIDTH-1:0] wb_dat_o); - - reg [count-1:0] locked; - - always @(posedge clock) - if(wb_rst_i) - locked <= {count{1'b0}}; - else if(wb_stb_i) - if(wb_we_i) - locked[adr_i] <= 1'b0; - else - locked[adr_i] <= 1'b1; - - assign wb_dat_o[DBUS_WIDTH-1:1] = {(DBUS_WIDTH-1){1'b0}}; - assign wb_dat_o[0] = locked[adr_i]; - assign wb_ack_o = wb_stb_i; - - -endmodule // wb_semaphore - - diff --git a/control_lib/wb_sim.v b/control_lib/wb_sim.v deleted file mode 100644 index b324e1457..000000000 --- a/control_lib/wb_sim.v +++ /dev/null @@ -1,79 +0,0 @@ - - -module wb_sim(); - - wire wb_clk, wb_rst; - wire start; - - reg POR, aux_clk, clk_fpga; - - initial POR = 1'b1; - initial #103 POR = 1'b0; - - initial aux_clk = 1'b0; - always #25 aux_clk = ~aux_clk; - - initial clk_fpga = 1'bx; - initial #3007 clk_fpga = 1'b0; - always #7 clk_fpga = ~clk_fpga; - - initial begin - $dumpfile("wb_sim.vcd"); - $dumpvars(0,wb_sim); - end - - initial #10000 $finish; - - wire [15:0] rom_addr; - wire [47:0] rom_data; - wire [31:0] wb_dat; - wire [15:0] wb_adr; - wire wb_cyc,wb_stb,wb_we,wb_ack; - wire [3:0] wb_sel; - - wire [31:0] port_output; - - - system_control system_control(.dsp_clk(dsp_clk), - .reset_out(reset_out), - .wb_clk_o(wb_clk), - .wb_rst_o(wb_rst), - .wb_rst_o_alt(wb_rst_o_alt), - .start (start), - .aux_clk(aux_clk), - .clk_fpga(clk_fpga), - .POR (POR), - .done (done)); - - clock_bootstrap_rom cbrom(.addr(rom_addr),.data(rom_data)); - - wb_bus_writer bus_writer(.rom_addr (rom_addr[15:0]), - .wb_dat_o (wb_dat[31:0]), - .wb_adr_o (wb_adr[15:0]), - .wb_cyc_o (wb_cyc), - .wb_sel_o (wb_sel[3:0]), - .wb_stb_o (wb_stb), - .wb_we_o (wb_we), - .start (start), - .done (done), - .rom_data (rom_data[47:0]), - .wb_clk_i (wb_clk), - .wb_rst_i (wb_rst), - .wb_ack_i (wb_ack)); - - wb_output_pins32 output_pins(.wb_dat_o(), - .wb_ack_o(wb_ack), - .port_output(port_output[31:0]), - .wb_rst_i(wb_rst), - .wb_clk_i(wb_clk), - .wb_dat_i(wb_dat[31:0]), - .wb_we_i(wb_we), - .wb_sel_i(wb_sel[3:0]), - .wb_stb_i(wb_stb), - .wb_cyc_i(wb_cyc)); - - - - -endmodule // wb_sim - -- cgit v1.2.3