From 91636cbac2b3edfba45321f1050d0b90b34ab696 Mon Sep 17 00:00:00 2001
From: Johnathan Corgan <jcorgan@corganenterprises.com>
Date: Mon, 31 Aug 2009 12:08:30 -0700
Subject: Merged SVN matt/new_eth r10782:11633 into new_eth

* svn diff http://gnuradio.org/svn/branches/developers/matt/new_eth
  -r10782:11633

* Patch applied with no conflicts or fuzz.
---
 control_lib/buffer_int.v                 | 251 ------------------------
 control_lib/buffer_pool.v                | 323 -------------------------------
 control_lib/newfifo/cascadefifo_2clock.v |  27 +++
 control_lib/newfifo/fifo36_to_ll8.v      |   2 +-
 control_lib/newfifo/fifo_2clock.v        |  66 -------
 control_lib/newfifo/fifo_2clock_casc.v   |  31 ---
 control_lib/newfifo/ll8_shortfifo.v      |  13 ++
 control_lib/newfifo/newfifo_2clock.v     |  82 ++++++++
 8 files changed, 123 insertions(+), 672 deletions(-)
 create mode 100644 control_lib/newfifo/cascadefifo_2clock.v
 create mode 100644 control_lib/newfifo/ll8_shortfifo.v
 create mode 100644 control_lib/newfifo/newfifo_2clock.v

(limited to 'control_lib')

diff --git a/control_lib/buffer_int.v b/control_lib/buffer_int.v
index c33f2779d..e69de29bb 100644
--- a/control_lib/buffer_int.v
+++ b/control_lib/buffer_int.v
@@ -1,251 +0,0 @@
-
-// FIFO Interface to the 2K buffer RAMs
-// Read port is read-acknowledge
-// FIXME do we want to be able to interleave reads and writes?
-
-module buffer_int
-  #(parameter BUFF_NUM = 0)
-    (// Control Interface
-     input clk,
-     input rst,
-     input [31:0] ctrl_word,
-     input go,
-     output done,
-     output error,
-     output idle,
-     
-     // Buffer Interface
-     output en_o,
-     output we_o,
-     output reg [8:0] addr_o,
-     output [31:0] dat_to_buf,
-     input [31:0] dat_from_buf,
-     
-     // Write FIFO Interface
-     input [31:0] wr_dat_i,
-     input wr_write_i,
-     input wr_done_i,
-     input wr_error_i,
-     output reg wr_ready_o,
-     output reg wr_full_o,
-     
-     // Read FIFO Interface
-     output [31:0] rd_dat_o,
-     input rd_read_i,
-     input rd_done_i,
-     input rd_error_i,
-     output reg rd_sop_o,
-     output reg rd_eop_o
-     );
-   
-   reg [31:0] ctrl_reg;
-   reg 	      go_reg;
-   
-   always @(posedge clk)
-     go_reg <= go;
-   
-   always @(posedge clk)
-     if(rst)
-       ctrl_reg <= 0;
-     else
-       if(go & (ctrl_word[31:28] == BUFF_NUM))
-	 ctrl_reg <= ctrl_word;
-   
-   wire [8:0] firstline = ctrl_reg[8:0];
-   wire [8:0] lastline = ctrl_reg[17:9];
-   wire [3:0] step = ctrl_reg[21:18];
-   wire       read = ctrl_reg[22];
-   wire       write = ctrl_reg[23];
-   wire       clear = ctrl_reg[24];
-   //wire [2:0] port = ctrl_reg[27:25];  // Ignored in this block
-   //wire [3:0] buff_num = ctrl_reg[31:28];  // Ignored here ?
-   
-   assign     dat_to_buf = wr_dat_i;
-   assign     rd_dat_o = dat_from_buf;
-   
-   localparam IDLE = 3'd0;
-   localparam PRE_READ = 3'd1;
-   localparam READING = 3'd2;
-   localparam WRITING = 3'd3;
-   localparam ERROR = 3'd4;
-   localparam DONE = 3'd5;
-   
-   reg [2:0]  state;
-   
-   always @(posedge clk)
-     if(rst)
-       begin
-	  state <= IDLE;
-	  rd_sop_o <= 0;
-	  rd_eop_o <= 0;
-	  wr_ready_o <= 0;
-	  wr_full_o <= 0;
-       end
-     else
-       if(clear)
-	 begin
-	    state <= IDLE;
-	    rd_sop_o <= 0;
-	    rd_eop_o <= 0;
-	    wr_ready_o <= 0;
-	    wr_full_o <= 0;
-	 end
-       else 
-	 case(state)
-	   IDLE :
-	     if(go_reg & read)
-	       begin
-		  addr_o <= firstline;
-		  state <= PRE_READ;
-	       end
-	     else if(go_reg & write)
-	       begin
-		  addr_o <= firstline;
-		  state <= WRITING;
-		  wr_ready_o <= 1;
-	       end
-	   
-	   PRE_READ :
-	     begin
-		state <= READING;
-		addr_o <= addr_o + 1;
-		rd_sop_o <= 1;
-	     end
-	   
-	   READING :
-	     if(rd_error_i)
-	       state <= ERROR;
-	     else if(rd_done_i)
-	       state <= DONE;
-	     else if(rd_read_i)
-	       begin
-		  rd_sop_o <= 0;
-		  addr_o <= addr_o + 1;
-		  if(addr_o == lastline)
-		    rd_eop_o <= 1;
-		  else
-		    rd_eop_o <= 0;
-		  if(rd_eop_o)
-		    state <= DONE;
-	       end
-	   
-	   WRITING :
-	     begin
-		if(wr_write_i)
-		  addr_o <= addr_o + 1;  // This was the timing problem, so now it doesn't depend on wr_error_i
-		if(wr_error_i)
-		  begin
-		     state <= ERROR;
-		     wr_ready_o <= 0;
-		  end
-		else
-		  begin
-		     if(wr_write_i)
-		       begin
-			  wr_ready_o <= 0;
-			  if(addr_o == (lastline-1))
-			    wr_full_o <= 1;
-			  if(addr_o == lastline)
-			    state <= DONE;
-		       end
-		     if(wr_done_i)
-		       begin
-			  state <= DONE;
-			  wr_ready_o <= 0;
-		       end
-		  end // else: !if(wr_error_i)
-	     end // case: WRITING
-
-	   DONE :
-	     begin
-		rd_eop_o <= 0;
-		rd_sop_o <= 0;
-		wr_ready_o <= 0;
-		wr_full_o <= 0;
-	     end
-	   
-	 endcase // case(state)
-   
-   // FIXME ignores step for now
-
-   assign     we_o = (state == WRITING) && wr_write_i;  // FIXME potential critical path
-                   // IF this is a timing problem, we could always write when in this state
-   assign     en_o = ~((state==READING)& ~rd_read_i);   // FIXME potential critical path
-   
-   assign     done = (state == DONE);
-   assign     error = (state == ERROR);
-   assign     idle = (state == IDLE);
-endmodule // buffer_int
-
-
-
-// These are 2 other ways for doing the WRITING state, both work.  First one is faster, but confusing
-/*
-	     begin
-		// Gen 4 values -- state, wr_ready_o, addr_o, wr_full_o
-		if(~wr_error_i & wr_write_i & (addr_o == (lastline-1)))
-		  wr_full_o <= 1;
-		if(wr_error_i | wr_write_i | wr_done_i)
-		  wr_ready_o <= 0;
-		if(wr_error_i)
-		  state <= ERROR;
-		else if(wr_done_i | (wr_write_i & (addr_o == lastline)))
-		  state <= DONE;
-		// This one was the timing problem...  now we increment addr_o even if there is an error
-		if(wr_write_i)
-		  addr_o <= addr_o + 1;
-	     end // case: WRITING
-*/	   
-		
-/*      begin
-		if(wr_error_i)
-		  begin
-		     state <= ERROR;
-		     wr_ready_o <= 0;
-		  end
-		else
-		  begin
-		     if(wr_write_i)
-		       begin
-			  wr_ready_o <= 0;
-			  addr_o <= addr_o + 1;
-			  if(addr_o == (lastline-1))
-			    wr_full_o <= 1;
-			  if(addr_o == lastline)
-			    state <= DONE;
-		       end
-		     if(wr_done_i)
-		       begin
-			  state <= DONE;
-			  wr_ready_o <= 0;
-		       end
-		  end // else: !if(wr_error_i)
-	     end // case: WRITING
-*/
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Unused old code
-   //assign     rd_empty_o = (state != READING); // && (state != PRE_READ);
-   //assign     rd_empty_o = rd_empty_reg;         // timing fix?
-   //assign     rd_ready_o = (state == READING);
-   //assign     rd_ready_o = ~rd_empty_reg;        // timing fix?
-   
-   //wire       rd_en = (state == PRE_READ) || ((state == READING) && rd_read_i);
-   //wire       wr_en = (state == WRITING) && wr_write_i;  // IF this is a timing problem, we could always enable when in this state
-   //assign     en_o = rd_en | wr_en;   
-   
-   // assign     wr_full_o = (state != WRITING);
-   // assign     wr_ready_o = (state == WRITING);
-   
diff --git a/control_lib/buffer_pool.v b/control_lib/buffer_pool.v
index 969296230..e69de29bb 100644
--- a/control_lib/buffer_pool.v
+++ b/control_lib/buffer_pool.v
@@ -1,323 +0,0 @@
-
-// Buffer pool.  Contains 8 buffers, each 2K (512 by 32).  Each buffer
-// is a dual-ported RAM.  Port A on each of them is indirectly connected 
-// to the wishbone bus by a bridge.  Port B may be connected any one of the
-// 8 (4 rd, 4 wr) FIFO-like streaming interaces, or disconnected.  The wishbone bus
-// provides access to all 8 buffers, and also controls the connections
-// between the ports and the buffers, allocating them as needed.
-
-// wb_adr is 16 bits -- 
-//  bits 13:11 select which buffer
-//  bits 10:2 select line in buffer
-//  bits 1:0 are unused (32-bit access only)
-
-module buffer_pool
-  (input wb_clk_i,
-   input wb_rst_i,
-   input wb_we_i,
-   input wb_stb_i,
-   input [15:0] wb_adr_i,
-   input [31:0] wb_dat_i,   
-   output [31:0] wb_dat_o,
-   output reg wb_ack_o,
-   output wb_err_o,
-   output wb_rty_o,
-   
-   input stream_clk,
-   input stream_rst,
-   
-   input set_stb, input [7:0] set_addr, input [31:0] set_data,
-   output [31:0] status,
-   output sys_int_o,
-
-   output [31:0] s0, output [31:0] s1, output [31:0] s2, output [31:0] s3,
-   output [31:0] s4, output [31:0] s5, output [31:0] s6, output [31:0] s7,
-   
-   // Write Interfaces
-   input [31:0] wr0_dat_i, input wr0_write_i, input wr0_done_i, input wr0_error_i, output wr0_ready_o, output wr0_full_o,
-   input [31:0] wr1_dat_i, input wr1_write_i, input wr1_done_i, input wr1_error_i, output wr1_ready_o, output wr1_full_o,
-   input [31:0] wr2_dat_i, input wr2_write_i, input wr2_done_i, input wr2_error_i, output wr2_ready_o, output wr2_full_o,
-   input [31:0] wr3_dat_i, input wr3_write_i, input wr3_done_i, input wr3_error_i, output wr3_ready_o, output wr3_full_o,
-   
-   // Read Interfaces
-   output [31:0] rd0_dat_o, input rd0_read_i, input rd0_done_i, input rd0_error_i, output rd0_sop_o, output rd0_eop_o,
-   output [31:0] rd1_dat_o, input rd1_read_i, input rd1_done_i, input rd1_error_i, output rd1_sop_o, output rd1_eop_o,
-   output [31:0] rd2_dat_o, input rd2_read_i, input rd2_done_i, input rd2_error_i, output rd2_sop_o, output rd2_eop_o,
-   output [31:0] rd3_dat_o, input rd3_read_i, input rd3_done_i, input rd3_error_i, output rd3_sop_o, output rd3_eop_o
-   );
-
-   wire [7:0] 	 sel_a;
-   
-   wire [2:0] 	 which_buf = wb_adr_i[13:11];   // address 15:14 selects the buffer pool
-   wire [8:0] 	 buf_addra = wb_adr_i[10:2];     // ignore address 1:0, 32-bit access only
-   
-   decoder_3_8 dec(.sel(which_buf),.res(sel_a));
-   
-   genvar 	 i;
-   
-   wire 	 go;
-
-   reg [2:0] 	 port[0:7];	 
-   reg [3:0] 	 read_src[0:3];
-   reg [3:0] 	 write_src[0:3];
-   
-   wire [7:0] 	 done;
-   wire [7:0] 	 error;
-   wire [7:0] 	 idle;
-   
-   wire [31:0] 	 buf_doa[0:7];
-   
-   wire [7:0] 	 buf_enb;
-   wire [7:0] 	 buf_web;
-   wire [8:0] 	 buf_addrb[0:7];
-   wire [31:0] 	 buf_dib[0:7];
-   wire [31:0] 	 buf_dob[0:7];
-   
-   wire [31:0] 	 wr_dat_i[0:7];
-   wire [7:0] 	 wr_write_i;
-   wire [7:0] 	 wr_done_i;
-   wire [7:0] 	 wr_error_i;
-   wire [7:0] 	 wr_ready_o;
-   wire [7:0] 	 wr_full_o;
-   
-   wire [31:0] 	 rd_dat_o[0:7];
-   wire [7:0] 	 rd_read_i;
-   wire [7:0] 	 rd_done_i;
-   wire [7:0] 	 rd_error_i;
-   wire [7:0] 	 rd_sop_o;
-   wire [7:0] 	 rd_eop_o;
-   
-   assign 	 status = {8'd0,idle[7:0],error[7:0],done[7:0]};
-
-   assign 	 s0 = {23'd0,buf_addrb[0]};
-   assign 	 s1 = {23'd0,buf_addrb[1]};
-   assign 	 s2 = {23'd0,buf_addrb[2]};
-   assign 	 s3 = {23'd0,buf_addrb[3]};
-   assign 	 s4 = {23'd0,buf_addrb[4]};
-   assign 	 s5 = {23'd0,buf_addrb[5]};
-   assign 	 s6 = {23'd0,buf_addrb[6]};
-   assign 	 s7 = {23'd0,buf_addrb[7]};
-   
-   wire [31:0] 	 fifo_ctrl;
-   setting_reg #(.my_addr(64)) 
-     sreg(.clk(stream_clk),.rst(stream_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),
-	  .out(fifo_ctrl),.changed(go));
-
-   integer 	 k;
-   always @(posedge stream_clk)
-     if(stream_rst)
-       for(k=0;k<8;k=k+1)
-	 port[k] <= 4;   // disabled
-     else
-       for(k=0;k<8;k=k+1)
-	 if(go & (fifo_ctrl[31:28]==k))
-	   port[k] <= fifo_ctrl[27:25];
-
-   always @(posedge stream_clk)
-     if(stream_rst)
-       for(k=0;k<4;k=k+1)
-	 read_src[k] <= 8;  // disabled
-     else
-       for(k=0;k<4;k=k+1)
-	 if(go & fifo_ctrl[22] & (fifo_ctrl[27:25]==k))
-	   read_src[k] <= fifo_ctrl[31:28];
-   
-   always @(posedge stream_clk)
-     if(stream_rst)
-       for(k=0;k<4;k=k+1)
-	 write_src[k] <= 8;  // disabled
-     else
-       for(k=0;k<4;k=k+1)
-	 if(go & fifo_ctrl[23] & (fifo_ctrl[27:25]==k))
-	   write_src[k] <= fifo_ctrl[31:28];
-   
-   generate
-      for(i=0;i<8;i=i+1)
-	begin : gen_buffer
-	   RAMB16_S36_S36 dpram
-	     (.DOA(buf_doa[i]),.ADDRA(buf_addra),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0),
-	      .ENA(wb_stb_i & sel_a[i]),.SSRA(0),.WEA(wb_we_i),
-	      .DOB(buf_dob[i]),.ADDRB(buf_addrb[i]),.CLKB(stream_clk),.DIB(buf_dib[i]),.DIPB(4'h0),
-	      .ENB(buf_enb[i]),.SSRB(0),.WEB(buf_web[i]) );
-	   
-	   /* ram_2port #(.DWIDTH(32),.AWIDTH(9)) buffer
-	     (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[i]),.wea(wb_we_i),
-	      .addra(buf_addra),.dia(wb_dat_i),.doa(buf_doa[i]),
-	      .clkb(stream_clk),.enb(buf_enb[i]),.web(buf_web[i]),
-	      .addrb(buf_addrb[i]),.dib(buf_dib[i]),.dob(buf_dob[i])); */
-
-	   buffer_int #(.BUFF_NUM(i)) fifo_int
-	     (.clk(stream_clk),.rst(stream_rst),
-	      .ctrl_word(fifo_ctrl),.go(go & (fifo_ctrl[31:28]==i)),
-	      .done(done[i]),.error(error[i]),.idle(idle[i]),
-	      .en_o(buf_enb[i]),
-	      .we_o(buf_web[i]),
-	      .addr_o(buf_addrb[i]),
-	      .dat_to_buf(buf_dib[i]),
-	      .dat_from_buf(buf_dob[i]),
-	      .wr_dat_i(wr_dat_i[i]),
-	      .wr_write_i(wr_write_i[i]),
-	      .wr_done_i(wr_done_i[i]),
-	      .wr_error_i(wr_error_i[i]),
-	      .wr_ready_o(wr_ready_o[i]),
-	      .wr_full_o(wr_full_o[i]),
-	      .rd_dat_o(rd_dat_o[i]),
-	      .rd_read_i(rd_read_i[i]),
-	      .rd_done_i(rd_done_i[i]),
-	      .rd_error_i(rd_error_i[i]),
-	      .rd_sop_o(rd_sop_o[i]),
-	      .rd_eop_o(rd_eop_o[i]) 
-	      );
-
-	   // FIXME -- if it is a problem, maybe we don't need enables on these muxes
-	   mux4 #(.WIDTH(32)) 
-	     mux4_dat_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_dat_i),.i1(wr1_dat_i),
-			 .i2(wr2_dat_i),.i3(wr3_dat_i),.o(wr_dat_i[i]));
-	   mux4 #(.WIDTH(1)) 
-	     mux4_write_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_write_i),.i1(wr1_write_i),
-			   .i2(wr2_write_i),.i3(wr3_write_i),.o(wr_write_i[i]));
-	   mux4 #(.WIDTH(1)) 
-	     mux4_wrdone_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_done_i),.i1(wr1_done_i),
-			    .i2(wr2_done_i),.i3(wr3_done_i),.o(wr_done_i[i]));
-	   mux4 #(.WIDTH(1)) 
-	     mux4_wrerror_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_error_i),.i1(wr1_error_i),
-			     .i2(wr2_error_i),.i3(wr3_error_i),.o(wr_error_i[i]));
-	   mux4 #(.WIDTH(1)) 
-	     mux4_read_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(rd0_read_i),.i1(rd1_read_i),
-			  .i2(rd2_read_i),.i3(rd3_read_i),.o(rd_read_i[i]));
-	   mux4 #(.WIDTH(1)) 
-	     mux4_rddone_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(rd0_done_i),.i1(rd1_done_i),
-			    .i2(rd2_done_i),.i3(rd3_done_i),.o(rd_done_i[i]));
-	   mux4 #(.WIDTH(1)) 
-	     mux4_rderror_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(rd0_error_i),.i1(rd1_error_i),
-			     .i2(rd2_error_i),.i3(rd3_error_i),.o(rd_error_i[i]));
-	end // block: gen_buffer
-   endgenerate
-
-   //----------------------------------------------------------------------
-   // Wishbone Outputs
-
-   // Use the following lines if ram output and mux can be made fast enough
-
-   assign wb_err_o = 1'b0;  // Unused for now
-   assign wb_rty_o = 1'b0;  // Unused for now
-   
-   always @(posedge wb_clk_i)
-     wb_ack_o <= wb_stb_i & ~wb_ack_o;
-   assign wb_dat_o = buf_doa[which_buf];
-
-   // Use this if we can't make the RAM+MUX fast enough
-   // reg [31:0] wb_dat_o_reg;
-   // reg 	      stb_d1;
-
-   // always @(posedge wb_clk_i)
-   //  begin
-   //   wb_dat_o_reg <= buf_doa[which_buf];
-   //   stb_d1 <= wb_stb_i;
-   //   wb_ack_o <= (stb_d1 & ~wb_ack_o) | (wb_we_i & wb_stb_i);
-   //  end
-   //assign     wb_dat_o = wb_dat_o_reg;
-   
-   mux8 #(.WIDTH(1)) 
-     mux8_wr_ready0(.en(~write_src[0][3]),.sel(write_src[0][2:0]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
-		    .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]),
-		    .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),.o(wr0_ready_o));
-
-   mux8 #(.WIDTH(1)) 
-     mux8_wr_full0(.en(~write_src[0][3]),.sel(write_src[0][2:0]), .i0(wr_full_o[0]), .i1(wr_full_o[1]),
-		   .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]),
-		   .i5(wr_full_o[5]), .i6(wr_full_o[6]), .i7(wr_full_o[7]),.o(wr0_full_o));
-   
-   mux8 #(.WIDTH(1)) 
-     mux8_wr_ready1(.en(~write_src[1][3]),.sel(write_src[1][2:0]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
-		    .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]),
-		    .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),.o(wr1_ready_o));
-
-   mux8 #(.WIDTH(1)) 
-     mux8_wr_full1(.en(~write_src[1][3]),.sel(write_src[1][2:0]), .i0(wr_full_o[0]), .i1(wr_full_o[1]),
-		   .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]),
-		   .i5(wr_full_o[5]), .i6(wr_full_o[6]), .i7(wr_full_o[7]),.o(wr1_full_o));
-   
-   mux8 #(.WIDTH(1)) 
-     mux8_wr_ready2(.en(~write_src[2][3]),.sel(write_src[2][2:0]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
-		    .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]),
-		    .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),.o(wr2_ready_o));
-
-   mux8 #(.WIDTH(1)) 
-     mux8_wr_full2(.en(~write_src[2][3]),.sel(write_src[2][2:0]), .i0(wr_full_o[0]), .i1(wr_full_o[1]),
-		   .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]),
-		   .i5(wr_full_o[5]), .i6(wr_full_o[6]), .i7(wr_full_o[7]),.o(wr2_full_o));
-   
-   mux8 #(.WIDTH(1)) 
-     mux8_wr_ready3(.en(~write_src[3][3]),.sel(write_src[3][2:0]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
-		    .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]),
-		    .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),.o(wr3_ready_o));
-   
-   mux8 #(.WIDTH(1)) 
-     mux8_wr_full3(.en(~write_src[3][3]),.sel(write_src[3][2:0]), .i0(wr_full_o[0]), .i1(wr_full_o[1]),
-		   .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]),
-		   .i5(wr_full_o[5]), .i6(wr_full_o[6]), .i7(wr_full_o[7]),.o(wr3_full_o));
-   
-   mux8 #(.WIDTH(1)) 
-     mux8_rd_sop0(.en(~read_src[0][3]),.sel(read_src[0][2:0]), .i0(rd_sop_o[0]), .i1(rd_sop_o[1]),
-		  .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]),
-		  .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), .i7(rd_sop_o[7]),.o(rd0_sop_o));
-   
-   mux8 #(.WIDTH(1)) 
-     mux8_rd_eop0(.en(~read_src[0][3]),.sel(read_src[0][2:0]), .i0(rd_eop_o[0]), .i1(rd_eop_o[1]),
-		  .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]),
-		  .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), .i7(rd_eop_o[7]),.o(rd0_eop_o));
-   
-   mux8 #(.WIDTH(32))
-     mux8_rd_dat_0 (.en(~read_src[0][3]),.sel(read_src[0][2:0]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
-		    .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
-		    .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), .i7(rd_dat_o[7]),.o(rd0_dat_o));
-   
-   mux8 #(.WIDTH(1)) 
-     mux8_rd_sop1(.en(~read_src[1][3]),.sel(read_src[1][2:0]), .i0(rd_sop_o[0]), .i1(rd_sop_o[1]),
-		  .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]),
-		  .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), .i7(rd_sop_o[7]),.o(rd1_sop_o));
-   
-   mux8 #(.WIDTH(1)) 
-     mux8_rd_eop1(.en(~read_src[1][3]),.sel(read_src[1][2:0]), .i0(rd_eop_o[0]), .i1(rd_eop_o[1]),
-		  .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]),
-		  .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), .i7(rd_eop_o[7]),.o(rd1_eop_o));
-   
-   mux8 #(.WIDTH(32))
-     mux8_rd_dat_1 (.en(~read_src[1][3]),.sel(read_src[1][2:0]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
-		    .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
-		    .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), .i7(rd_dat_o[7]),.o(rd1_dat_o));
-   
-   mux8 #(.WIDTH(1)) 
-     mux8_rd_sop2(.en(~read_src[2][3]),.sel(read_src[2][2:0]), .i0(rd_sop_o[0]), .i1(rd_sop_o[1]),
-		  .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]),
-		  .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), .i7(rd_sop_o[7]),.o(rd2_sop_o));
-   
-   mux8 #(.WIDTH(1)) 
-     mux8_rd_eop2(.en(~read_src[2][3]),.sel(read_src[2][2:0]), .i0(rd_eop_o[0]), .i1(rd_eop_o[1]),
-		  .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]),
-		  .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), .i7(rd_eop_o[7]),.o(rd2_eop_o));
-   
-   mux8 #(.WIDTH(32))
-     mux8_rd_dat_2 (.en(~read_src[2][3]),.sel(read_src[2][2:0]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
-		    .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
-		    .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), .i7(rd_dat_o[7]),.o(rd2_dat_o));
-   
-   mux8 #(.WIDTH(1)) 
-     mux8_rd_sop3(.en(~read_src[3][3]),.sel(read_src[3][2:0]), .i0(rd_sop_o[0]), .i1(rd_sop_o[1]),
-		  .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]),
-		  .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), .i7(rd_sop_o[7]),.o(rd3_sop_o));
-   
-   mux8 #(.WIDTH(1)) 
-     mux8_rd_eop3(.en(~read_src[3][3]),.sel(read_src[3][2:0]), .i0(rd_eop_o[0]), .i1(rd_eop_o[1]),
-		  .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]),
-		  .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), .i7(rd_eop_o[7]),.o(rd3_eop_o));
-   
-   mux8 #(.WIDTH(32))
-     mux8_rd_dat_3 (.en(~read_src[3][3]),.sel(read_src[3][2:0]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
-		    .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
-		    .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), .i7(rd_dat_o[7]),.o(rd3_dat_o));
-   
-   assign sys_int_o = (|error) | (|done);
-   
-endmodule // buffer_pool
diff --git a/control_lib/newfifo/cascadefifo_2clock.v b/control_lib/newfifo/cascadefifo_2clock.v
new file mode 100644
index 000000000..2abbbf3b5
--- /dev/null
+++ b/control_lib/newfifo/cascadefifo_2clock.v
@@ -0,0 +1,27 @@
+
+module cascadefifo_2clock
+  #(parameter DWIDTH=32, AWIDTH=9)
+    (input wclk, input [DWIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [AWIDTH-1:0] level_wclk,
+     input rclk, output [DWIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [AWIDTH-1:0] level_rclk,
+     input arst);
+
+   wire [DWIDTH-1:0] data_int1, data_int2;
+   wire src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2;
+   
+   fifo_short #(.WIDTH(DWIDTH)) shortfifo
+     (.clk(wclk), .reset(arst), .clear(0),
+      .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+      .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1) );
+   
+   newfifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock
+     (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .level_wclk(level_wclk),
+      .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .level_rclk(level_rclk),
+      .arst(arst) );
+
+   fifo_short #(.WIDTH(DWIDTH)) shortfifo2
+     (.clk(rclk), .reset(arst), .clear(0),
+      .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
+      .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i) );
+   
+endmodule // fifo_2clock_casc
+
diff --git a/control_lib/newfifo/fifo36_to_ll8.v b/control_lib/newfifo/fifo36_to_ll8.v
index 1befb9e6e..0dee1dfc6 100644
--- a/control_lib/newfifo/fifo36_to_ll8.v
+++ b/control_lib/newfifo/fifo36_to_ll8.v
@@ -1,6 +1,6 @@
 
 module fifo36_to_ll8
-  (input clk, reset,
+  (input clk, input reset, input clear,
    input [35:0] f36_data,
    input f36_src_rdy_i,
    output f36_dst_rdy_o,
diff --git a/control_lib/newfifo/fifo_2clock.v b/control_lib/newfifo/fifo_2clock.v
index 6b1eb607e..e69de29bb 100644
--- a/control_lib/newfifo/fifo_2clock.v
+++ b/control_lib/newfifo/fifo_2clock.v
@@ -1,66 +0,0 @@
-
-module fifo_2clock
-  #(parameter DWIDTH=32, AWIDTH=9)
-    (input wclk, input [DWIDTH-1:0] datain, input write, output full, output reg [AWIDTH-1:0] level_wclk,
-     input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output reg [AWIDTH-1:0] level_rclk,
-     input arst);
-
-   reg [AWIDTH-1:0] wr_addr, rd_addr;
-   wire [AWIDTH-1:0] wr_addr_rclk, rd_addr_wclk;
-   wire [AWIDTH-1:0] next_rd_addr;
-   wire 	    enb_read;
-   
-   // Write side management
-   wire [AWIDTH-1:0] next_wr_addr = wr_addr + 1;
-   always @(posedge wclk or posedge arst)
-     if(arst)
-       wr_addr <= 0;
-     else if(write)
-       wr_addr <= next_wr_addr;
-   assign 	    full = (next_wr_addr == rd_addr_wclk);
-
-   //  RAM for data storage.  Data out is registered, complicating the
-   //     read side logic
-   ram_2port #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) mac_rx_ff_ram
-     (.clka(wclk),.ena(1'b1),.wea(write),.addra(wr_addr),.dia(datain),.doa(),
-      .clkb(rclk),.enb(enb_read),.web(1'b0),.addrb(next_rd_addr),.dib(0),.dob(dataout) );
-
-   // Read side management
-   reg 		    data_valid;
-   assign 	    empty = ~data_valid;
-   assign 	    next_rd_addr = rd_addr + data_valid;
-   assign 	    enb_read = read | ~data_valid;
-
-   always @(posedge rclk or posedge arst)
-     if(arst)
-       rd_addr <= 0;
-     else if(read)
-       rd_addr <= rd_addr + 1;
-
-   always @(posedge rclk or posedge arst)
-     if(arst)
-       data_valid <= 0;
-     else
-       if(read & (next_rd_addr == wr_addr_rclk))
-	 data_valid <= 0;
-       else if(next_rd_addr != wr_addr_rclk)
-	 data_valid <= 1;
-	 
-   // Send pointers across clock domains via gray code
-   gray_send #(.WIDTH(AWIDTH)) send_wr_addr
-     (.clk_in(wclk),.addr_in(wr_addr),
-      .clk_out(rclk),.addr_out(wr_addr_rclk) );
-   
-   gray_send #(.WIDTH(AWIDTH)) send_rd_addr
-     (.clk_in(rclk),.addr_in(rd_addr),
-      .clk_out(wclk),.addr_out(rd_addr_wclk) );
-
-   // Generate fullness info, these are approximate and may be delayed 
-   // and are only for higher-level flow control.  
-   // Only full and empty are guaranteed exact.
-   always @(posedge wclk) 
-     level_wclk <= wr_addr - rd_addr_wclk;
-   always @(posedge rclk) 
-     level_rclk <= wr_addr_rclk - rd_addr;
-   
-endmodule // fifo_2clock
diff --git a/control_lib/newfifo/fifo_2clock_casc.v b/control_lib/newfifo/fifo_2clock_casc.v
index e9b0cfc25..e69de29bb 100644
--- a/control_lib/newfifo/fifo_2clock_casc.v
+++ b/control_lib/newfifo/fifo_2clock_casc.v
@@ -1,31 +0,0 @@
-
-module fifo_2clock_casc
-  #(parameter DWIDTH=32, AWIDTH=9)
-    (input wclk, input [DWIDTH-1:0] datain, input write, output full, output [AWIDTH-1:0] level_wclk,
-     input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output [AWIDTH-1:0] level_rclk,
-     input arst);
-
-   wire    full_int, empty_int, full_int2, empty_int2, transfer, transfer2;
-   wire [DWIDTH-1:0] data_int, data_int2;
-   
-   shortfifo #(.WIDTH(DWIDTH)) shortfifo
-     (.clk(wclk), .rst(arst), .clear(0),
-      .datain(datain), .write(write), .full(full),
-      .dataout(data_int), .read(transfer), .empty(empty_int) );
-
-   assign  transfer = ~full_int & ~empty_int;
-   
-   fifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock
-     (.wclk(wclk), .datain(data_int), .write(transfer), .full(full_int), .level_wclk(level_wclk),
-      .rclk(rclk), .dataout(data_int2), .read(transfer2), .empty(empty_int2), .level_rclk(level_rclk),
-      .arst(arst) );
-
-   assign  transfer2 = ~full_int2 & ~empty_int2;
-
-   shortfifo #(.WIDTH(DWIDTH)) shortfifo2
-     (.clk(rclk), .rst(arst), .clear(0),
-      .datain(data_int2), .write(transfer2), .full(full_int2),
-      .dataout(dataout), .read(read), .empty(empty) );
-   
-endmodule // fifo_2clock_casc
-
diff --git a/control_lib/newfifo/ll8_shortfifo.v b/control_lib/newfifo/ll8_shortfifo.v
new file mode 100644
index 000000000..39ada9a4f
--- /dev/null
+++ b/control_lib/newfifo/ll8_shortfifo.v
@@ -0,0 +1,13 @@
+
+
+module ll8_shortfifo
+  (input clk, input reset, input clear,
+   input [7:0] datain, input sof_i, input eof_i, input error_i, input src_rdy_i, output dst_rdy_o,
+   output [7:0] dataout, output sof_o, output eof_o, output error_o, output src_rdy_o, input dst_rdy_i);
+
+   fifo_short #(.WIDTH(11)) fifo_short
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain({error_i,eof_i,sof_i,datain}), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+      .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
+
+endmodule // ll8_shortfifo
diff --git a/control_lib/newfifo/newfifo_2clock.v b/control_lib/newfifo/newfifo_2clock.v
new file mode 100644
index 000000000..23a6f693c
--- /dev/null
+++ b/control_lib/newfifo/newfifo_2clock.v
@@ -0,0 +1,82 @@
+
+module newfifo_2clock
+  #(parameter DWIDTH=32, AWIDTH=9)
+  (input wclk, input [DWIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output reg [AWIDTH-1:0] level_wclk,
+   input rclk, output [DWIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output reg [AWIDTH-1:0] level_rclk,
+   input arst);
+
+   wire full, empty, write, read;
+
+   assign dst_rdy_o  = ~full;
+   assign src_rdy_o  = ~empty;
+   assign write      = src_rdy_i & dst_rdy_o;
+   assign read 	     = src_rdy_o & dst_rdy_i;
+
+//`define USE_XLNX_FIFO 1
+`ifdef USE_XLNX_FIFO
+   fifo_xlnx_512x36_2clk mac_tx_fifo_2clk
+     (.rst(rst),
+      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(fifo_occupied[8:0]),
+      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count() );   
+`else
+   // ISE sucks, so the following doesn't work properly
+
+   reg [AWIDTH-1:0] wr_addr, rd_addr;
+   wire [AWIDTH-1:0] wr_addr_rclk, rd_addr_wclk;
+   wire [AWIDTH-1:0] next_rd_addr;
+   wire 	    enb_read;
+   
+   // Write side management
+   wire [AWIDTH-1:0] next_wr_addr = wr_addr + 1;
+   always @(posedge wclk or posedge arst)
+     if(arst)
+       wr_addr <= 0;
+     else if(write)
+       wr_addr <= next_wr_addr;
+   assign 	    full = (next_wr_addr == rd_addr_wclk);
+
+   //  RAM for data storage.  Data out is registered, complicating the
+   //     read side logic
+   ram_2port #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) mac_rx_ff_ram
+     (.clka(wclk),.ena(1'b1),.wea(write),.addra(wr_addr),.dia(datain),.doa(),
+      .clkb(rclk),.enb(enb_read),.web(1'b0),.addrb(next_rd_addr),.dib(0),.dob(dataout) );
+
+   // Read side management
+   reg 		    data_valid;
+   assign 	    empty = ~data_valid;
+   assign 	    next_rd_addr = rd_addr + data_valid;
+   assign 	    enb_read = read | ~data_valid;
+
+   always @(posedge rclk or posedge arst)
+     if(arst)
+       rd_addr <= 0;
+     else if(read)
+       rd_addr <= rd_addr + 1;
+
+   always @(posedge rclk or posedge arst)
+     if(arst)
+       data_valid <= 0;
+     else
+       if(read & (next_rd_addr == wr_addr_rclk))
+	 data_valid <= 0;
+       else if(next_rd_addr != wr_addr_rclk)
+	 data_valid <= 1;
+	 
+   // Send pointers across clock domains via gray code
+   gray_send #(.WIDTH(AWIDTH)) send_wr_addr
+     (.clk_in(wclk),.addr_in(wr_addr),
+      .clk_out(rclk),.addr_out(wr_addr_rclk) );
+   
+   gray_send #(.WIDTH(AWIDTH)) send_rd_addr
+     (.clk_in(rclk),.addr_in(rd_addr),
+      .clk_out(wclk),.addr_out(rd_addr_wclk) );
+
+   // Generate fullness info, these are approximate and may be delayed 
+   // and are only for higher-level flow control.  
+   // Only full and empty are guaranteed exact.
+   always @(posedge wclk) 
+     level_wclk <= wr_addr - rd_addr_wclk;
+   always @(posedge rclk) 
+     level_rclk <= wr_addr_rclk - rd_addr;
+`endif
+endmodule // fifo_2clock
-- 
cgit v1.2.3


From 29fa1be3dc307d6d9be0fc3a004213eea50e6071 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Wed, 2 Sep 2009 16:46:06 -0700
Subject: Removed these files completely, they were for the old style of fifos

---
 control_lib/buffer_int.v     |   0
 control_lib/buffer_int_tb.v  | 447 -------------------------------------------
 control_lib/buffer_pool.v    |   0
 control_lib/buffer_pool_tb.v |  50 -----
 4 files changed, 497 deletions(-)
 delete mode 100644 control_lib/buffer_int.v
 delete mode 100644 control_lib/buffer_int_tb.v
 delete mode 100644 control_lib/buffer_pool.v
 delete mode 100644 control_lib/buffer_pool_tb.v

(limited to 'control_lib')

diff --git a/control_lib/buffer_int.v b/control_lib/buffer_int.v
deleted file mode 100644
index e69de29bb..000000000
diff --git a/control_lib/buffer_int_tb.v b/control_lib/buffer_int_tb.v
deleted file mode 100644
index 4fb5c6710..000000000
--- a/control_lib/buffer_int_tb.v
+++ /dev/null
@@ -1,447 +0,0 @@
-
-module buffer_int_tb ();
-
-   reg clk = 0;
-   reg rst = 1;
-
-   initial #100 rst = 0;
-   always #5 clk = ~clk;
-
-   wire en, we;
-   wire [8:0] addr;
-   wire [31:0] fifo2buf, buf2fifo;
-   
-   wire [31:0] rd_dat_o;
-   wire        rd_sop_o, rd_eop_o;
-   reg 	       rd_done_i = 0, rd_error_i = 0, rd_read_i = 0;
-   
-   reg [31:0]  wr_dat_i = 0;
-   reg 	       wr_write_i=0, wr_done_i = 0, wr_error_i = 0;
-   wire        wr_ready_o, wr_full_o;
-   
-   reg 	       clear = 0, write = 0, read = 0;
-   reg [8:0]   firstline = 0, lastline = 0;
-   wire [3:0]  step = 1;
-   wire [31:0] ctrl_word = {4'b0,3'b0,clear,write,read,step,lastline,firstline};
-   reg 	       go = 0;
-   wire        done, error;
-   
-   buffer_int buffer_int
-     (.clk(clk),.rst(rst),
-      .ctrl_word(ctrl_word),.go(go),
-      .done(done),.error(error),
-      
-      // Buffer Interface
-      .en_o(en),.we_o(we),.addr_o(addr),
-      .dat_to_buf(fifo2buf),.dat_from_buf(buf2fifo),
-
-      // Write FIFO Interface
-      .wr_dat_i(wr_dat_i), .wr_write_i(wr_write_i), .wr_done_i(wr_done_i), .wr_error_i(wr_error_i), 
-      .wr_ready_o(wr_ready_o), .wr_full_o(wr_full_o),
-   
-      // Read FIFO Interface
-      .rd_dat_o(rd_dat_o), .rd_read_i(rd_read_i), .rd_done_i(rd_done_i), .rd_error_i(rd_error_i),
-      .rd_sop_o(rd_sop_o), .rd_eop_o(rd_eop_o)
-      );
-   
-   reg 	       ram_en = 0, ram_we = 0;
-   reg [8:0]   ram_addr = 0;
-   reg [31:0]  ram_data = 0;
-   
-   ram_2port #(.DWIDTH(32),.AWIDTH(9)) ram_2port
-     (.clka(clk), .ena(ram_en), .wea(ram_we), .addra(ram_addr), .dia(ram_data), .doa(),
-      .clkb(clk), .enb(en), .web(we), .addrb(addr), .dib(fifo2buf), .dob(buf2fifo) );
-   
-   initial
-     begin
-	@(negedge rst);
-	@(posedge clk);
-	FillRAM;
-
-	ResetBuffer;
-	SetBufferRead(5,10);
-	$display("Testing full read, no wait states.");
-	while(!rd_sop_o)
-	  @(posedge clk);
-	ReadLines(6,0);
-	repeat (10)
-	  @(posedge clk);
-	
-	ResetBuffer;
-	SetBufferRead(5,10);
-	$display("Testing full read, 2 wait states.");
-	while(!rd_sop_o)
-	  @(posedge clk);
-	ReadLines(6,2);
-	repeat (10)
-	  @(posedge clk);
-
-	ResetBuffer;
-	SetBufferRead(5,10);
-	$display("Testing full read, done ON the last.");
-	while(!rd_sop_o)
-	  @(posedge clk);
-	ReadLines(5,2);
-	rd_done_i <= 1;
-	ReadALine;
-	rd_done_i <= 0;
-	repeat (10)
-	  @(posedge clk);
-	
-	ResetBuffer;
-	SetBufferRead(5,10);
-	$display("Testing partial read, 0 wait states, then nothing after last.");
-	while(!rd_sop_o)
-	  @(posedge clk);
-	ReadLines(3,0);
-	repeat (10)
-	  @(posedge clk);
-
-	ResetBuffer;
-	SetBufferRead(5,10);
-	$display("Testing partial read, 0 wait states, then done after last.");
-	while(!rd_sop_o)
-	  @(posedge clk);
-	ReadLines(3,0);
-	rd_done_i <= 1;
-	@(posedge clk);
-	rd_done_i <= 0;
-	repeat (10)
-	  @(posedge clk);
-
-	ResetBuffer;
-	SetBufferRead(5,10);
-	$display("Testing partial read, 0 wait states, then done at same time as last.");
-	while(!rd_sop_o)
-	  @(posedge clk);
-	ReadLines(2,0);
-	rd_done_i <= 1;
-	ReadALine;
-	rd_done_i <= 0;
-	repeat (10)
-	  @(posedge clk);
-
-	ResetBuffer;
-	SetBufferRead(5,10);
-	$display("Testing partial read, 3 wait states, then error at same time as last.");
-	while(!rd_sop_o)
-	  @(posedge clk);
-	ReadLines(2,3);
-	rd_error_i <= 1;
-	ReadALine;
-	rd_error_i <= 0;
-	repeat (10)
-	  @(posedge clk);
-
-	ResetBuffer;
-	SetBufferRead(5,10);
-	$display("Testing Reading too much, 3 wait states.");
-	while(!rd_sop_o)
-	  @(posedge clk);
-	ReadLines(9,3);
-	repeat (10)
-	  @(posedge clk);
-
-	ResetBuffer;
-	SetBufferRead(500,511);
-	$display("Testing full read, to the end of the buffer.");
-	while(!rd_sop_o)
-	  @(posedge clk);
-	ReadLines(12,0);
-	repeat (10)
-	  @(posedge clk);
-	
-	ResetBuffer;
-	SetBufferRead(0,511);
-	$display("Testing full read, start to end of the buffer.");
-	while(!rd_sop_o)
-	  @(posedge clk);
-	ReadLines(512,0);
-	repeat (10)
-	  @(posedge clk);
-	
-	ResetBuffer;
-	SetBufferRead(505,3);
-	$display("Testing full read, wraparound");
-	while(!rd_sop_o)
-	  @(posedge clk);
-	ReadLines(11,0);
-	repeat (10)
-	  @(posedge clk);
-
-	ResetBuffer;
-	SetBufferWrite(10,15);
-	$display("Testing Full Write, no wait states");
-	while(!wr_ready_o)
-	  @(posedge clk);
-	WriteLines(6,0,72);
-	repeat (10)
-	  @(posedge clk);
-	
-	ResetBuffer;
-	SetBufferWrite(18,23);
-	$display("Testing Full Write, 1 wait states");
-	while(!wr_ready_o)
-	  @(posedge clk);
-	WriteLines(6,0,101);
-	repeat (10)
-	  @(posedge clk);
-	
-	ResetBuffer;
-	SetBufferWrite(27,40);
-	$display("Testing Partial Write, 0 wait states");
-	while(!wr_ready_o)
-	  @(posedge clk);
-	WriteLines(6,0,201);
-	repeat (10)
-	  @(posedge clk);
-	
-	ResetBuffer;
-	SetBufferWrite(35,200);
-	$display("Testing Partial Write, 0 wait states, then done");
-	while(!wr_ready_o)
-	  @(posedge clk);
-	WriteLines(6,0,301);
-	wr_done_i <= 1;
-	@(posedge clk);
-	wr_done_i <= 0;
-	repeat (10)
-	  @(posedge clk);
-
-	ResetBuffer;
-	SetBufferWrite(45,200);
-	$display("Testing Partial Write, 0 wait states, then done and write simultaneously");
-	while(!wr_ready_o)
-	  @(posedge clk);
-	WriteLines(6,0,301);
-	wr_done_i <= 1;
-	WriteALine(400);
-	wr_done_i <= 0;
-	repeat (10)
-	  @(posedge clk);
-	
-	ResetBuffer;
-	SetBufferWrite(55,200);
-	$display("Testing Partial Write, 0 wait states, then error");
-	while(!wr_ready_o)
-	  @(posedge clk);
-	WriteLines(6,0,501);
-	wr_error_i <= 1;
-	@(posedge clk);
-	wr_error_i <= 0;
-	repeat (10)
-	  @(posedge clk);
-	
-	ResetBuffer;
-	SetBufferRead(0,82);
-	$display("Testing read after all the writes");
-	while(!rd_sop_o)
-	  @(posedge clk);
-	ReadLines(83,0);
-	repeat (10)
-	  @(posedge clk);
-	
-	ResetBuffer;
-	SetBufferWrite(508,4);
-	$display("Testing wraparound write");
-	while(!wr_ready_o)
-	  @(posedge clk);
-	WriteLines(9,0,601);
-	repeat (10)
-	  @(posedge clk);
-	
-	ResetBuffer;
-	SetBufferRead(506,10);
-	$display("Reading wraparound write");
-	while(!rd_sop_o)
-	  @(posedge clk);
-	ReadLines(17,0);
-	repeat (10)
-	  @(posedge clk);
-	
-	ResetBuffer;
-	SetBufferWrite(0,511);
-	$display("Testing Whole Buffer write");
-	while(!wr_ready_o)
-	  @(posedge clk);
-	WriteLines(512,0,1000);
-	repeat (10)
-	  @(posedge clk);
-	
-	ResetBuffer;
-	SetBufferRead(0,511);
-	$display("Reading Whole Buffer write");
-	while(!rd_sop_o)
-	  @(posedge clk);
-	ReadLines(512,0);
-	repeat (10)
-	  @(posedge clk);
-	
-	ResetBuffer;
-	SetBufferWrite(5,10);
-	$display("Testing Write Too Many");
-	while(!wr_ready_o)
-	  @(posedge clk);
-	WriteLines(12,0,2000);
-	repeat (10)
-	  @(posedge clk);
-	
-	ResetBuffer;
-	SetBufferRead(0,15);
-	$display("Reading back Write Too Many");
-	while(!rd_sop_o)
-	  @(posedge clk);
-	ReadLines(16,0);
-	repeat (10)
-	  @(posedge clk);
-	
-	ResetBuffer;
-	SetBufferWrite(15,20);
-	$display("Testing Write One Less Than Full");
-	while(!wr_ready_o)
-	  @(posedge clk);
-	WriteLines(5,0,2000);
-	repeat (10)
-	  @(posedge clk);
-	
-	ResetBuffer;
-	SetBufferRead(13,22);
-	$display("Reading back Write One Less Than Full");
-	while(!rd_sop_o)
-	  @(posedge clk);
-	ReadLines(10,0);
-	repeat (10)
-	  @(posedge clk);
-	
-	ResetBuffer;
-	repeat(100)
-	  @(posedge clk);
-	$finish;
-     end
-   
-   always @(posedge clk)
-     if(rd_read_i == 1'd1)
-       $display("READ Buffer %d, rd_sop_o %d, rd_eop_o %d", rd_dat_o, rd_sop_o, rd_eop_o);
-
-   always @(posedge clk)
-     if(wr_write_i == 1'd1)
-       $display("WRITE Buffer %d,  wr_ready_o %d, wr_full_o %d", wr_dat_i, wr_ready_o, wr_full_o);
-	   
-   initial begin
-      $dumpfile("buffer_int_tb.vcd");
-      $dumpvars(0,buffer_int_tb);
-   end
-
-   task FillRAM;
-      begin
-	 ram_addr <= 0;
-	 ram_data <= 0;
-	 @(posedge clk);
-	 ram_en <= 1;
-	 ram_we <= 1;
-	 @(posedge clk);
-	 repeat (511)
-	   begin
-	      ram_addr <= ram_addr + 1;
-	      ram_data <= ram_data + 1;
-	      ram_en <= 1;
-	      ram_we <= 1;
-	      @(posedge clk);
-	   end
-	 ram_en <= 0;
-	 ram_we <= 0;
-	 @(posedge clk);
-	 $display("Filled the RAM");
-      end
-   endtask // FillRAM
-
-   task ResetBuffer;
-      begin
-	 clear <= 1; read <= 0; write <= 0;
-	 go <= 1;
-	 @(posedge clk);
-	 go <= 0;
-	 @(posedge clk);
-	 $display("Buffer Reset");
-      end
-   endtask // ClearBuffer
-   
-   task SetBufferWrite;
-      input [8:0] start;
-      input [8:0] stop;
-      begin
-	 clear <= 0; read <= 0; write <= 1;
-	 firstline <= start;
-	 lastline <= stop;
-	 go <= 1;
-	 @(posedge clk);
-	 go <= 0;
-	 @(posedge clk);
-	 $display("Buffer Set for Write");
-      end
-   endtask // SetBufferWrite
-   
-   task SetBufferRead;
-      input [8:0] start;
-      input [8:0] stop;
-      begin
-	 clear <= 0; read <= 1; write <= 0;
-	 firstline <= start;
-	 lastline <= stop;
-	 go <= 1;
-	 @(posedge clk);
-	 go <= 0;
-	 @(posedge clk);
-	 $display("Buffer Set for Read");
-      end
-   endtask // SetBufferRead
-
-   task ReadALine;
-      begin
-	 #1 rd_read_i <= 1;
-	 @(posedge clk);
-	 rd_read_i <= 0;
-      end
-   endtask // ReadALine
-
-   task ReadLines;
-      input [9:0] lines;
-      input [7:0] wait_states;
-      begin
-	 $display("Read Lines: Number %d, Wait States %d",lines,wait_states);
-	 repeat (lines)
-	   begin
-	      ReadALine;
-	      repeat (wait_states)
-		@(posedge clk);
-	   end
-      end
-   endtask // ReadLines
-   
-   task WriteALine;
-      input [31:0] value;
-      begin
-	 #1 wr_write_i <= 1;
-	 wr_dat_i <= value;
-	 @(posedge clk);
-	 wr_write_i <= 0;
-      end
-   endtask // WriteALine
-   
-   task WriteLines;
-      input [9:0] lines;
-      input [7:0] wait_states;
-      input [31:0] value;
-      begin
-	 $display("Write Lines: Number %d, Wait States %d",lines,wait_states);
-	 repeat(lines)
-	   begin
-	      value <= value + 1;
-	      WriteALine(value);
-	      repeat(wait_states)
-		@(posedge clk);
-	   end
-      end
-   endtask // WriteLines
-   
-endmodule // buffer_int_tb
diff --git a/control_lib/buffer_pool.v b/control_lib/buffer_pool.v
deleted file mode 100644
index e69de29bb..000000000
diff --git a/control_lib/buffer_pool_tb.v b/control_lib/buffer_pool_tb.v
deleted file mode 100644
index 16741438e..000000000
--- a/control_lib/buffer_pool_tb.v
+++ /dev/null
@@ -1,50 +0,0 @@
-
-module buffer_pool_tb();
-   
-   wire wb_clk_i;
-   wire wb_rst_i;
-   wire wb_we_i;
-   wire wb_stb_i;
-   wire [15:0] wb_adr_i;
-   wire [31:0] wb_dat_i;   
-   wire [31:0] wb_dat_o;
-   wire wb_ack_o;
-   wire wb_err_o;
-   wire wb_rty_o;
-
-   wire stream_clk, stream_rst;
-
-   wire set_stb;
-   wire [7:0] set_addr;
-   wire [31:0] set_data;
-
-   wire [31:0] wr0_dat_i;
-   buffer_pool dut
-     (.wb_clk_i(wb_clk_i),
-      .wb_rst_i(wb_rst_i),
-      .wb_we_i(wb_we_i),
-      .wb_stb_i(wb_stb_i),
-      .wb_adr_i(wb_adr_i),
-      .wb_dat_i(wb_dat_i),   
-      .wb_dat_o(wb_dat_o),
-      .wb_ack_o(wb_ack_o),
-      .wb_err_o(wb_err_o),
-      .wb_rty_o(wb_rty_o),
-      
-      .stream_clk(stream_clk),
-      .stream_rst(stream_rst),
-      
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      
-      .wr0_dat_i(wr0_dat_i), .wr0_write_i(), .wr0_done_i(), .wr0_error_i(), .wr0_ready_o(), .wr0_full_o(),
-      .wr1_dat_i(), .wr1_write_i(), .wr1_done_i(), .wr1_error_i(), .wr1_ready_o(), .wr1_full_o(),
-      .wr2_dat_i(), .wr2_write_i(), .wr2_done_i(), .wr2_error_i(), .wr2_ready_o(), .wr2_full_o(),
-      .wr3_dat_i(), .wr3_write_i(), .wr3_done_i(), .wr3_error_i(), .wr3_ready_o(), .wr3_full_o(),
-      
-      .rd0_dat_o(), .rd0_read_i(), .rd0_done_i(), .rd0_error_i(), .rd0_ready_o(), .rd0_empty_o(),
-      .rd1_dat_o(), .rd1_read_i(), .rd1_done_i(), .rd1_error_i(), .rd1_ready_o(), .rd1_empty_o(),
-      .rd2_dat_o(), .rd2_read_i(), .rd2_done_i(), .rd2_error_i(), .rd2_ready_o(), .rd2_empty_o(),
-      .rd3_dat_o(), .rd3_read_i(), .rd3_done_i(), .rd3_error_i(), .rd3_ready_o(), .rd3_empty_o()
-      );
-   
-endmodule // buffer_pool_tb
-- 
cgit v1.2.3


From 280e196b60f0a4e8f1915dbd38761e879ccd567e Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Wed, 2 Sep 2009 17:09:16 -0700
Subject: never used, not needed

---
 control_lib/fifo_reader.v  |  28 ------
 control_lib/fifo_writer.v  |  31 -------
 control_lib/giantfifo.v    | 209 ---------------------------------------------
 control_lib/giantfifo_tb.v | 173 -------------------------------------
 4 files changed, 441 deletions(-)
 delete mode 100644 control_lib/fifo_reader.v
 delete mode 100644 control_lib/fifo_writer.v
 delete mode 100644 control_lib/giantfifo.v
 delete mode 100644 control_lib/giantfifo_tb.v

(limited to 'control_lib')

diff --git a/control_lib/fifo_reader.v b/control_lib/fifo_reader.v
deleted file mode 100644
index 49d05b1a6..000000000
--- a/control_lib/fifo_reader.v
+++ /dev/null
@@ -1,28 +0,0 @@
-
-module fifo_reader
-  #(parameter rate=4)
-    (input clk,
-     input [31:0] data_in,
-     output read_o
-     input ready_i,
-     input done_i
-     );
-
-   reg [7:0] state = 0;
-   
-   always @(posedge clk)
-     if(ready)
-       if(state == rate)
-	 state <= 0;
-       else
-	 state <= state + 1;
-     else
-       state <= 0;
-
-   assign    read = (state == rate);
-
-   initial $monitor(data_in);
-   
-endmodule // fifo_reader
-
-   
diff --git a/control_lib/fifo_writer.v b/control_lib/fifo_writer.v
deleted file mode 100644
index 064ad3cb9..000000000
--- a/control_lib/fifo_writer.v
+++ /dev/null
@@ -1,31 +0,0 @@
-
-module fifo_writer
-  #(parameter rate=4)
-    (input clk,
-     output [31:0] data_out,
-     output write_o,
-     input ready_i,
-     input done_i
-     );
-   
-   reg [7:0] state = 0;
-
-
-   // FIXME change this to write
-   always @(posedge clk)
-     if(ready)
-       if(state == rate)
-	 state <= 0;
-       else
-	 state <= state + 1;
-     else
-       state <= 0;
-
-   assign    read = (state == rate);
-
-   initial $monitor(data_in);
-   
-endmodule // fifo_writer
-
-
-   
diff --git a/control_lib/giantfifo.v b/control_lib/giantfifo.v
deleted file mode 100644
index dba330b8a..000000000
--- a/control_lib/giantfifo.v
+++ /dev/null
@@ -1,209 +0,0 @@
-
-
-
-module giantfifo
-  #(parameter WIDTH=36)
-    (input clk, input rst,
-     input [WIDTH-1:0] datain,
-     output [WIDTH-1:0] dataout,
-     input read,
-     input write,
-     input clear,
-     output full,
-     output empty,
-     output [15:0] space,
-     output [15:0] occupied,
-     
-     // External RAM
-     inout [17:0] RAM_D,
-     output reg [18:0] RAM_A,
-     output RAM_CE1n,
-     output RAM_CENn,
-     output reg RAM_CLK,
-     output reg RAM_WEn,
-     output RAM_OEn,
-     output RAM_LDn
-     );
-
-   wire [4:0] path1_occ, path2_space;
-   wire [35:0] path1_dat, path2_dat;
-   
-   shortfifo #(.WIDTH(WIDTH)) sf1
-     (.clk(clk),.rst(rst),.clear(clear),
-      .datain(datain),.write(write),.full(full),
-      .dataout(path1_dat),.read(path1_read),.empty(path1_empty),
-      .space(),.occupied(path1_occ) );
-   wire       path1_almost_empty = (path1_occ == 5'd1);
-   
-   shortfifo #(.WIDTH(WIDTH)) sf2
-     (.clk(clk),.rst(rst),.clear(clear),
-      .datain(path2_dat),.write(path2_write),.full(path2_full),
-      .dataout(dataout),.read(read),.empty(empty),
-      .space(path2_space),.occupied() );
-   wire       path2_almost_full = (path2_space == 5'd1);
-	
-   assign     RAM_CE1n = 1'b0;
-   assign     RAM_CENn = 1'b0;
-   always @(clk)
-     RAM_CLK <= #2 clk;
-   assign     RAM_LDn = 1'b0;
-
-   // State machine
-   wire       write_now, read_now, idle, phase;
-   reg 	      ram_full, ram_empty;
-   
-   reg [17:0] read_ptr, write_ptr;
-   reg [2:0]  zbt_state;
-
-   localparam ZBT_IDLE = 0;
-   localparam ZBT_WRITE_UPPER = 2;
-   localparam ZBT_WRITE_LOWER = 3;
-   localparam ZBT_READ_UPPER = 4;
-   localparam ZBT_READ_LOWER = 5;
-
-   wire       can_write = ~ram_full & ~path1_empty;
-   wire       can_write_chain = can_write & ~path1_almost_empty;
-
-   wire       can_read = ~ram_empty & ~path2_full;
-   wire       can_read_chain = can_read & ~path2_almost_full;
-   
-   assign     phase = zbt_state[0];
-
-   reg [17:0] ram_occupied;
-   wire       ram_almost_empty = (write_ptr == (read_ptr+1'b1));
-   wire       ram_almost_full = ((write_ptr+1'b1) == read_ptr);
-
-   always @(posedge clk)
-     if(rst | clear)
-       begin
-	  zbt_state <= ZBT_IDLE;
-	  write_ptr <= 0;
-	  read_ptr <= 0;
-	  ram_full <= 0;
-	  ram_empty <= 1;
-	  ram_occupied <= 0;
-       end
-     else
-       case(zbt_state)
-	 ZBT_IDLE : 
-	   if(can_read) 
-	     zbt_state <= ZBT_READ_UPPER;
-	   else if(can_write)
-	     zbt_state <= ZBT_WRITE_UPPER;
-	 
-	 ZBT_WRITE_UPPER : 
-	   begin
-	      zbt_state <= ZBT_WRITE_LOWER;
-	      ram_occupied <= ram_occupied + 1;
-	      ram_empty <= 0;
-	      if(ram_occupied == 18'd10)
-		ram_full <= 1;
-	   end
-	 ZBT_WRITE_LOWER : 
-	   begin
-	      write_ptr <= write_ptr + 1;
-	      if(can_read_chain) 
-		zbt_state <= ZBT_READ_UPPER;
-	      else if(can_write_chain)
-		zbt_state <= ZBT_WRITE_UPPER;
-	      else
-		zbt_state <= ZBT_IDLE;
-	   end
-	 ZBT_READ_UPPER : 
-	   begin
-	      zbt_state <= ZBT_READ_LOWER;
-	      ram_occupied <= ram_occupied - 1;
-	      ram_full <= 0;
-	      if(ram_occupied == 18'd1)
-		ram_empty <= 1;
-	   end
-	 ZBT_READ_LOWER :
-	   begin
-	      read_ptr <= read_ptr + 1;
-	      if(can_read_chain) 
-		zbt_state <= ZBT_READ_UPPER;
-	      else if(can_write_chain)
-		zbt_state <= ZBT_WRITE_UPPER;
-	      else
-		zbt_state <= ZBT_IDLE;
-	   end
-	 default :
-	   zbt_state <= ZBT_IDLE;
-       endcase // case(zbt_state)
-
-   // Need to generate RAM_WEn, RAM_OEn, RAM_D, RAM_A;
-   assign path1_read = (zbt_state == ZBT_WRITE_LOWER);
-   reg 	  path2_write, delayed_read_upper, delayed_read_lower, delayed_write;
-
-   always @(posedge clk)
-     if(delayed_read_upper)
-       path2_dat[35:18] <= RAM_D;
-   always @(posedge clk)
-     if(delayed_read_lower)
-       path2_dat[17:0] <= RAM_D;
-
-   always @(posedge clk)
-     if(rst)
-       begin
-	  delayed_read_upper <= 0;
-	  delayed_read_lower <= 0;
-	  path2_write <= 0;
-       end
-     else 
-       begin
-	  delayed_read_upper <= (zbt_state == ZBT_READ_LOWER);
-	  delayed_read_lower <= delayed_read_upper;
-	  path2_write <= delayed_read_lower;
-       end
-   
-   reg [17:0] RAM_D_pre2, RAM_D_pre1, RAM_D_out;
-   
-   always @(posedge clk)
-     RAM_D_pre2 <= phase ? path1_dat[17:0] : path1_dat[35:18];
-
-   always @(posedge clk)  RAM_D_pre1 <= RAM_D_pre2;
-   always @(posedge clk)  RAM_D_out <= RAM_D_pre1;
-   reg 	      wr_del_1, wr_del_2; 	      
-   always @(posedge clk)
-     if(rst)
-       begin
-	  wr_del_1 <= 0;	  
-	  wr_del_2 <= 0;
-	  delayed_write <= 0;
-       end
-     else
-       begin
-	  delayed_write <= wr_del_2;
-	  wr_del_2 <= wr_del_1;
-	  wr_del_1 <= write_now;
-       end
-
-   reg delayed_read, rd_del_1, rd_del_2;
-   always @(posedge clk)
-     if(rst)
-       begin
-	  rd_del_1 <= 0;	  
-	  rd_del_2 <= 0;
-	  delayed_read <= 0;
-       end
-     else
-       begin
-	  delayed_read <= rd_del_2;
-	  rd_del_2 <= rd_del_1;
-	  rd_del_1 <= read_now;
-       end
-	  
-   assign     RAM_D = delayed_write ? RAM_D_out : 18'bzzzzzzzzzzzzzzzzzz;
-   assign     write_now = (zbt_state == ZBT_WRITE_UPPER) || (zbt_state == ZBT_WRITE_LOWER);
-   assign     read_now =  (zbt_state == ZBT_READ_UPPER) || (zbt_state == ZBT_READ_LOWER);
-   
-   always @(posedge clk)
-     RAM_A <= write_now ? {write_ptr,phase} : {read_ptr,phase};
-
-   always @(posedge clk)
-     RAM_WEn <= ~write_now;
-
-   assign     RAM_OEn = ~delayed_read;
-   assign     RAM_OEn = 0;
-   
-endmodule // giantfifo
diff --git a/control_lib/giantfifo_tb.v b/control_lib/giantfifo_tb.v
deleted file mode 100644
index 87ecd97ae..000000000
--- a/control_lib/giantfifo_tb.v
+++ /dev/null
@@ -1,173 +0,0 @@
-module fifo_tb();
-
-   localparam WIDTH = 36;
-   reg clk, rst;
-   wire short_full, short_empty, long_full, long_empty, giant_full, giant_empty;
-   wire casc_full, casc_empty, casc2_full, casc2_empty;
-   reg 	read, write;
-   
-   wire [WIDTH-1:0] short_do, long_do, casc_do, casc2_do, giant_do;
-   reg [WIDTH-1:0]  di;
-
-   reg 	      clear = 0;
-   
-   shortfifo #(.WIDTH(WIDTH)) shortfifo
-     (.clk(clk),.rst(rst),.datain(di),.dataout(short_do),.clear(clear),
-      .read(read),.write(write),.full(short_full),.empty(short_empty));
-   
-   longfifo #(.WIDTH(WIDTH), .SIZE(4)) longfifo
-     (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear),
-      .read(read),.write(write),.full(long_full),.empty(long_empty));
-   
-   cascadefifo #(.WIDTH(WIDTH), .SIZE(4)) cascadefifo
-     (.clk(clk),.rst(rst),.datain(di),.dataout(casc_do),.clear(clear),
-      .read(read),.write(write),.full(casc_full),.empty(casc_empty));
-   
-   cascadefifo2 #(.WIDTH(WIDTH), .SIZE(4)) cascadefifo2
-     (.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear),
-      .read(read),.write(write),.full(casc2_full),.empty(casc2_empty));
-
-   wire [17:0] RAM_D;
-   wire [18:0] RAM_A;
-   wire        RAM_CLK, RAM_WEn, RAM_LDn, RAM_CE1n, RAM_OEn, RAM_CENn;
-   
-   giantfifo #(.WIDTH(WIDTH)) giantfifo
-     (.clk(clk),.rst(rst),.datain(di),.dataout(giant_do),.clear(clear),
-      .read(read),.write(write),.full(giant_full),.empty(giant_empty),
-      .RAM_D(RAM_D),.RAM_A(RAM_A),.RAM_CE1n(RAM_CE1n),.RAM_CENn(RAM_CENn),
-      .RAM_CLK(RAM_CLK),.RAM_WEn(RAM_WEn),.RAM_OEn(RAM_OEn),.RAM_LDn(RAM_LDn)
-      );
-
-   wire        MODE = 1'b0;
-   cy1356 ram_model(.d(RAM_D),.clk(RAM_CLK),.a(RAM_A),
-		    .bws(2'b00),.we_b(RAM_WEn),.adv_lb(RAM_LDn),
-		    .ce1b(RAM_CE1n),.ce2(1'b1),.ce3b(1'b0),
-		    .oeb(RAM_OEn),.cenb(RAM_CENn),.mode(MODE) 
-		    );
-   
-   initial rst = 1;
-   initial #1000 rst = 0;
-   initial clk = 0;
-   always #50 clk = ~clk;
-   
-   initial di = 36'h300AE;
-   initial read = 0;
-   initial write = 0;
-
-   always @(posedge clk)
-     if(write)
-       di <= di + 1;
-   
-   always @(posedge clk)
-     begin
-	if(short_full != long_full)
-	  $display("Error: FULL mismatch");
-	if(short_empty != long_empty)
-	  $display("Note: EMPTY mismatch, usually not a problem (longfifo has 2 cycle latency)");
-	if(read & (short_do != long_do))
-	  $display("Error: DATA mismatch");
-     end
-   
-   initial $dumpfile("giantfifo_tb.vcd");
-   initial $dumpvars(0,fifo_tb);
-
-   initial
-     begin
-	@(negedge rst);
-	@(posedge clk);
-	repeat (10)
-	  @(posedge clk);
-	write <= 1;
-	@(posedge clk);
-	write <= 0;
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	read <= 1;
-	@(posedge clk);
-	read <= 0;
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-
-	repeat(10)
-	  begin
-	     write <= 1;
-	     @(posedge clk);
-	     write <= 0;
-	     @(posedge clk);
-	     @(posedge clk);
-	     @(posedge clk);
-	     read <= 1;
-	     @(posedge clk);
-	     read <= 0;
-	     @(posedge clk);
-	     @(posedge clk);
-	     @(posedge clk);
-	     @(posedge clk);
-	     @(posedge clk);
-	  end // repeat (10)
-	
-	write <= 1;
-	repeat (4)
-	  @(posedge clk);
-	write <= 0;
-	@(posedge clk);
-	read <= 1;
-	repeat (4)
-	  @(posedge clk);
-	read <= 0;
-	@(posedge clk);
-
-
-	write <= 1;
-	repeat (4)
-	  @(posedge clk);
-	write <= 0;
-	@(posedge clk);
-	repeat (4)
-	  begin
-	     read <= 1;
-	     @(posedge clk);
-	     read <= 0;
-	     @(posedge clk);
-	  end
-
-	write <= 1;
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	read <= 1;
-	repeat (5)
-	  @(posedge clk);
-	write <= 0;
-	  @(posedge clk);
-	  @(posedge clk);
-	read <= 0;
-	@(posedge clk);
-
-	write <= 1;
-	repeat (16)
-	  @(posedge clk);
-	write <= 0;
-	@(posedge clk);
-	
-	read <= 1;
-	repeat (16)
-	  @(posedge clk);
-	read <= 0;
-	@(posedge clk);
-		 
-	repeat (10)
-	  @(posedge clk);
-	$finish;
-     end
-endmodule // longfifo_tb
-- 
cgit v1.2.3


From a3ebf209706e424df88a0f5abbb12b80147c922b Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Wed, 2 Sep 2009 17:23:12 -0700
Subject: cascadefifo.v wasn't used, only the double cascade version. 
 fifo_2clock.v and fifo_2clock.v are empty

---
 control_lib/cascadefifo.v              | 50 ----------------------------------
 control_lib/fifo_tb.v                  |  8 ++----
 control_lib/newfifo/fifo_2clock.v      |  0
 control_lib/newfifo/fifo_2clock_casc.v |  0
 4 files changed, 2 insertions(+), 56 deletions(-)
 delete mode 100644 control_lib/cascadefifo.v
 delete mode 100644 control_lib/newfifo/fifo_2clock.v
 delete mode 100644 control_lib/newfifo/fifo_2clock_casc.v

(limited to 'control_lib')

diff --git a/control_lib/cascadefifo.v b/control_lib/cascadefifo.v
deleted file mode 100644
index c1a4ab335..000000000
--- a/control_lib/cascadefifo.v
+++ /dev/null
@@ -1,50 +0,0 @@
-
-
-// This FIFO exists to provide an intermediate point for the data on its
-// long trek from one RAM (in the buffer pool) to another (in the longfifo)
-// The shortfifo is more flexible in its placement since it is based on
-// distributed RAM
-// This one should only be used on transmit side applications.  I.e. tx_mac, tx_dsp, etc.
-//   Spartan 3's have slow routing....
-// If we REALLY need to, we could also do this on the output side, 
-// with for the receive side stuff
-
-module cascadefifo
-  #(parameter WIDTH=32, SIZE=9)
-    (input clk, input rst,
-     input [WIDTH-1:0] datain,
-     output [WIDTH-1:0] dataout,
-     input read,
-     input write,
-     input clear,
-     output full,
-     output empty,
-     output [15:0] space,
-     output [15:0] occupied);
-
-   wire [WIDTH-1:0] data_int;
-   wire 	    empty_int, full_int, transfer;
-   wire [4:0] 	    short_space, short_occupied;
-   wire [15:0] 	    long_space, long_occupied;
-   
-   shortfifo #(.WIDTH(WIDTH)) shortfifo
-     (.clk(clk),.rst(rst),.clear(clear),
-      .datain(datain), .write(write), .full(full),
-      .dataout(data_int), .read(transfer), .empty(empty_int),
-      .space(short_space),.occupied(short_occupied) );
-
-   longfifo #(.WIDTH(WIDTH),.SIZE(SIZE)) longfifo
-     (.clk(clk),.rst(rst),.clear(clear),
-      .datain(data_int), .write(transfer), .full(full_int),
-      .dataout(dataout), .read(read), .empty(empty),
-      .space(long_space),.occupied(long_occupied) );
-
-   assign 	    transfer = ~empty_int & ~full_int; 	    
-
-   assign 	    space = {11'b0,short_space} + long_space;
-   assign 	    occupied = {11'b0,short_occupied} + long_occupied;
-   
-endmodule // cascadefifo
-
-
-
diff --git a/control_lib/fifo_tb.v b/control_lib/fifo_tb.v
index 98fd63f8d..616fe4ee7 100644
--- a/control_lib/fifo_tb.v
+++ b/control_lib/fifo_tb.v
@@ -2,11 +2,11 @@ module fifo_tb();
    
    reg clk, rst;
    wire short_full, short_empty, long_full, long_empty;
-   wire casc_full, casc_empty, casc2_full, casc2_empty;
+   wire casc2_full, casc2_empty;
    reg 	read, write;
    
    wire [7:0] short_do, long_do;
-   wire [7:0] casc_do, casc2_do;
+   wire [7:0] casc2_do;
    reg [7:0]  di;
 
    reg 	      clear = 0;
@@ -19,10 +19,6 @@ module fifo_tb();
      (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear),
       .read(read),.write(write),.full(long_full),.empty(long_empty));
    
-   cascadefifo #(.WIDTH(8), .SIZE(4)) cascadefifo
-     (.clk(clk),.rst(rst),.datain(di),.dataout(casc_do),.clear(clear),
-      .read(read),.write(write),.full(casc_full),.empty(casc_empty));
-   
    cascadefifo2 #(.WIDTH(8), .SIZE(4)) cascadefifo2
      (.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear),
       .read(read),.write(write),.full(casc2_full),.empty(casc2_empty));
diff --git a/control_lib/newfifo/fifo_2clock.v b/control_lib/newfifo/fifo_2clock.v
deleted file mode 100644
index e69de29bb..000000000
diff --git a/control_lib/newfifo/fifo_2clock_casc.v b/control_lib/newfifo/fifo_2clock_casc.v
deleted file mode 100644
index e69de29bb..000000000
-- 
cgit v1.2.3


From fb04ad0eb86ea0cfa65be66c09c8424213c9c932 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Wed, 2 Sep 2009 17:28:57 -0700
Subject: cleaning up the new fifos

---
 control_lib/newfifo/cascadefifo_2clock.v  |  27 ------
 control_lib/newfifo/fifo_2clock.v         |  82 ++++++++++++++++
 control_lib/newfifo/fifo_2clock_cascade.v |  27 ++++++
 control_lib/newfifo/fifo_tb.v             | 155 ------------------------------
 control_lib/newfifo/newfifo_2clock.v      |  82 ----------------
 5 files changed, 109 insertions(+), 264 deletions(-)
 delete mode 100644 control_lib/newfifo/cascadefifo_2clock.v
 create mode 100644 control_lib/newfifo/fifo_2clock.v
 create mode 100644 control_lib/newfifo/fifo_2clock_cascade.v
 delete mode 100644 control_lib/newfifo/fifo_tb.v
 delete mode 100644 control_lib/newfifo/newfifo_2clock.v

(limited to 'control_lib')

diff --git a/control_lib/newfifo/cascadefifo_2clock.v b/control_lib/newfifo/cascadefifo_2clock.v
deleted file mode 100644
index 2abbbf3b5..000000000
--- a/control_lib/newfifo/cascadefifo_2clock.v
+++ /dev/null
@@ -1,27 +0,0 @@
-
-module cascadefifo_2clock
-  #(parameter DWIDTH=32, AWIDTH=9)
-    (input wclk, input [DWIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [AWIDTH-1:0] level_wclk,
-     input rclk, output [DWIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [AWIDTH-1:0] level_rclk,
-     input arst);
-
-   wire [DWIDTH-1:0] data_int1, data_int2;
-   wire src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2;
-   
-   fifo_short #(.WIDTH(DWIDTH)) shortfifo
-     (.clk(wclk), .reset(arst), .clear(0),
-      .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
-      .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1) );
-   
-   newfifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock
-     (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .level_wclk(level_wclk),
-      .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .level_rclk(level_rclk),
-      .arst(arst) );
-
-   fifo_short #(.WIDTH(DWIDTH)) shortfifo2
-     (.clk(rclk), .reset(arst), .clear(0),
-      .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
-      .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i) );
-   
-endmodule // fifo_2clock_casc
-
diff --git a/control_lib/newfifo/fifo_2clock.v b/control_lib/newfifo/fifo_2clock.v
new file mode 100644
index 000000000..23a6f693c
--- /dev/null
+++ b/control_lib/newfifo/fifo_2clock.v
@@ -0,0 +1,82 @@
+
+module newfifo_2clock
+  #(parameter DWIDTH=32, AWIDTH=9)
+  (input wclk, input [DWIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output reg [AWIDTH-1:0] level_wclk,
+   input rclk, output [DWIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output reg [AWIDTH-1:0] level_rclk,
+   input arst);
+
+   wire full, empty, write, read;
+
+   assign dst_rdy_o  = ~full;
+   assign src_rdy_o  = ~empty;
+   assign write      = src_rdy_i & dst_rdy_o;
+   assign read 	     = src_rdy_o & dst_rdy_i;
+
+//`define USE_XLNX_FIFO 1
+`ifdef USE_XLNX_FIFO
+   fifo_xlnx_512x36_2clk mac_tx_fifo_2clk
+     (.rst(rst),
+      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(fifo_occupied[8:0]),
+      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count() );   
+`else
+   // ISE sucks, so the following doesn't work properly
+
+   reg [AWIDTH-1:0] wr_addr, rd_addr;
+   wire [AWIDTH-1:0] wr_addr_rclk, rd_addr_wclk;
+   wire [AWIDTH-1:0] next_rd_addr;
+   wire 	    enb_read;
+   
+   // Write side management
+   wire [AWIDTH-1:0] next_wr_addr = wr_addr + 1;
+   always @(posedge wclk or posedge arst)
+     if(arst)
+       wr_addr <= 0;
+     else if(write)
+       wr_addr <= next_wr_addr;
+   assign 	    full = (next_wr_addr == rd_addr_wclk);
+
+   //  RAM for data storage.  Data out is registered, complicating the
+   //     read side logic
+   ram_2port #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) mac_rx_ff_ram
+     (.clka(wclk),.ena(1'b1),.wea(write),.addra(wr_addr),.dia(datain),.doa(),
+      .clkb(rclk),.enb(enb_read),.web(1'b0),.addrb(next_rd_addr),.dib(0),.dob(dataout) );
+
+   // Read side management
+   reg 		    data_valid;
+   assign 	    empty = ~data_valid;
+   assign 	    next_rd_addr = rd_addr + data_valid;
+   assign 	    enb_read = read | ~data_valid;
+
+   always @(posedge rclk or posedge arst)
+     if(arst)
+       rd_addr <= 0;
+     else if(read)
+       rd_addr <= rd_addr + 1;
+
+   always @(posedge rclk or posedge arst)
+     if(arst)
+       data_valid <= 0;
+     else
+       if(read & (next_rd_addr == wr_addr_rclk))
+	 data_valid <= 0;
+       else if(next_rd_addr != wr_addr_rclk)
+	 data_valid <= 1;
+	 
+   // Send pointers across clock domains via gray code
+   gray_send #(.WIDTH(AWIDTH)) send_wr_addr
+     (.clk_in(wclk),.addr_in(wr_addr),
+      .clk_out(rclk),.addr_out(wr_addr_rclk) );
+   
+   gray_send #(.WIDTH(AWIDTH)) send_rd_addr
+     (.clk_in(rclk),.addr_in(rd_addr),
+      .clk_out(wclk),.addr_out(rd_addr_wclk) );
+
+   // Generate fullness info, these are approximate and may be delayed 
+   // and are only for higher-level flow control.  
+   // Only full and empty are guaranteed exact.
+   always @(posedge wclk) 
+     level_wclk <= wr_addr - rd_addr_wclk;
+   always @(posedge rclk) 
+     level_rclk <= wr_addr_rclk - rd_addr;
+`endif
+endmodule // fifo_2clock
diff --git a/control_lib/newfifo/fifo_2clock_cascade.v b/control_lib/newfifo/fifo_2clock_cascade.v
new file mode 100644
index 000000000..2abbbf3b5
--- /dev/null
+++ b/control_lib/newfifo/fifo_2clock_cascade.v
@@ -0,0 +1,27 @@
+
+module cascadefifo_2clock
+  #(parameter DWIDTH=32, AWIDTH=9)
+    (input wclk, input [DWIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [AWIDTH-1:0] level_wclk,
+     input rclk, output [DWIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [AWIDTH-1:0] level_rclk,
+     input arst);
+
+   wire [DWIDTH-1:0] data_int1, data_int2;
+   wire src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2;
+   
+   fifo_short #(.WIDTH(DWIDTH)) shortfifo
+     (.clk(wclk), .reset(arst), .clear(0),
+      .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+      .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1) );
+   
+   newfifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock
+     (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .level_wclk(level_wclk),
+      .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .level_rclk(level_rclk),
+      .arst(arst) );
+
+   fifo_short #(.WIDTH(DWIDTH)) shortfifo2
+     (.clk(rclk), .reset(arst), .clear(0),
+      .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
+      .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i) );
+   
+endmodule // fifo_2clock_casc
+
diff --git a/control_lib/newfifo/fifo_tb.v b/control_lib/newfifo/fifo_tb.v
deleted file mode 100644
index 98fd63f8d..000000000
--- a/control_lib/newfifo/fifo_tb.v
+++ /dev/null
@@ -1,155 +0,0 @@
-module fifo_tb();
-   
-   reg clk, rst;
-   wire short_full, short_empty, long_full, long_empty;
-   wire casc_full, casc_empty, casc2_full, casc2_empty;
-   reg 	read, write;
-   
-   wire [7:0] short_do, long_do;
-   wire [7:0] casc_do, casc2_do;
-   reg [7:0]  di;
-
-   reg 	      clear = 0;
-   
-   shortfifo #(.WIDTH(8)) shortfifo
-     (.clk(clk),.rst(rst),.datain(di),.dataout(short_do),.clear(clear),
-      .read(read),.write(write),.full(short_full),.empty(short_empty));
-   
-   longfifo #(.WIDTH(8), .SIZE(4)) longfifo
-     (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear),
-      .read(read),.write(write),.full(long_full),.empty(long_empty));
-   
-   cascadefifo #(.WIDTH(8), .SIZE(4)) cascadefifo
-     (.clk(clk),.rst(rst),.datain(di),.dataout(casc_do),.clear(clear),
-      .read(read),.write(write),.full(casc_full),.empty(casc_empty));
-   
-   cascadefifo2 #(.WIDTH(8), .SIZE(4)) cascadefifo2
-     (.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear),
-      .read(read),.write(write),.full(casc2_full),.empty(casc2_empty));
-   
-   initial rst = 1;
-   initial #1000 rst = 0;
-   initial clk = 0;
-   always #50 clk = ~clk;
-   
-   initial di = 8'hAE;
-   initial read = 0;
-   initial write = 0;
-
-   always @(posedge clk)
-     if(write)
-       di <= di + 1;
-   
-   always @(posedge clk)
-     begin
-	if(short_full != long_full)
-	  $display("Error: FULL mismatch");
-	if(short_empty != long_empty)
-	  $display("Note: EMPTY mismatch, usually not a problem (longfifo has 2 cycle latency)");
-	if(read & (short_do != long_do))
-	  $display("Error: DATA mismatch");
-     end
-   
-   initial $dumpfile("fifo_tb.vcd");
-   initial $dumpvars(0,fifo_tb);
-
-   initial
-     begin
-	@(negedge rst);
-	@(posedge clk);
-	repeat (10)
-	  @(posedge clk);
-	write <= 1;
-	@(posedge clk);
-	write <= 0;
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	read <= 1;
-	@(posedge clk);
-	read <= 0;
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-
-	repeat(10)
-	  begin
-	     write <= 1;
-	     @(posedge clk);
-	     write <= 0;
-	     @(posedge clk);
-	     @(posedge clk);
-	     @(posedge clk);
-	     read <= 1;
-	     @(posedge clk);
-	     read <= 0;
-	     @(posedge clk);
-	     @(posedge clk);
-	     @(posedge clk);
-	     @(posedge clk);
-	     @(posedge clk);
-	  end // repeat (10)
-	
-	write <= 1;
-	repeat (4)
-	  @(posedge clk);
-	write <= 0;
-	@(posedge clk);
-	read <= 1;
-	repeat (4)
-	  @(posedge clk);
-	read <= 0;
-	@(posedge clk);
-
-
-	write <= 1;
-	repeat (4)
-	  @(posedge clk);
-	write <= 0;
-	@(posedge clk);
-	repeat (4)
-	  begin
-	     read <= 1;
-	     @(posedge clk);
-	     read <= 0;
-	     @(posedge clk);
-	  end
-
-	write <= 1;
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	read <= 1;
-	repeat (5)
-	  @(posedge clk);
-	write <= 0;
-	  @(posedge clk);
-	  @(posedge clk);
-	read <= 0;
-	@(posedge clk);
-
-	write <= 1;
-	repeat (16)
-	  @(posedge clk);
-	write <= 0;
-	@(posedge clk);
-	
-	read <= 1;
-	repeat (16)
-	  @(posedge clk);
-	read <= 0;
-	@(posedge clk);
-		 
-	repeat (10)
-	  @(posedge clk);
-	$finish;
-     end
-endmodule // longfifo_tb
diff --git a/control_lib/newfifo/newfifo_2clock.v b/control_lib/newfifo/newfifo_2clock.v
deleted file mode 100644
index 23a6f693c..000000000
--- a/control_lib/newfifo/newfifo_2clock.v
+++ /dev/null
@@ -1,82 +0,0 @@
-
-module newfifo_2clock
-  #(parameter DWIDTH=32, AWIDTH=9)
-  (input wclk, input [DWIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output reg [AWIDTH-1:0] level_wclk,
-   input rclk, output [DWIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output reg [AWIDTH-1:0] level_rclk,
-   input arst);
-
-   wire full, empty, write, read;
-
-   assign dst_rdy_o  = ~full;
-   assign src_rdy_o  = ~empty;
-   assign write      = src_rdy_i & dst_rdy_o;
-   assign read 	     = src_rdy_o & dst_rdy_i;
-
-//`define USE_XLNX_FIFO 1
-`ifdef USE_XLNX_FIFO
-   fifo_xlnx_512x36_2clk mac_tx_fifo_2clk
-     (.rst(rst),
-      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(fifo_occupied[8:0]),
-      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count() );   
-`else
-   // ISE sucks, so the following doesn't work properly
-
-   reg [AWIDTH-1:0] wr_addr, rd_addr;
-   wire [AWIDTH-1:0] wr_addr_rclk, rd_addr_wclk;
-   wire [AWIDTH-1:0] next_rd_addr;
-   wire 	    enb_read;
-   
-   // Write side management
-   wire [AWIDTH-1:0] next_wr_addr = wr_addr + 1;
-   always @(posedge wclk or posedge arst)
-     if(arst)
-       wr_addr <= 0;
-     else if(write)
-       wr_addr <= next_wr_addr;
-   assign 	    full = (next_wr_addr == rd_addr_wclk);
-
-   //  RAM for data storage.  Data out is registered, complicating the
-   //     read side logic
-   ram_2port #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) mac_rx_ff_ram
-     (.clka(wclk),.ena(1'b1),.wea(write),.addra(wr_addr),.dia(datain),.doa(),
-      .clkb(rclk),.enb(enb_read),.web(1'b0),.addrb(next_rd_addr),.dib(0),.dob(dataout) );
-
-   // Read side management
-   reg 		    data_valid;
-   assign 	    empty = ~data_valid;
-   assign 	    next_rd_addr = rd_addr + data_valid;
-   assign 	    enb_read = read | ~data_valid;
-
-   always @(posedge rclk or posedge arst)
-     if(arst)
-       rd_addr <= 0;
-     else if(read)
-       rd_addr <= rd_addr + 1;
-
-   always @(posedge rclk or posedge arst)
-     if(arst)
-       data_valid <= 0;
-     else
-       if(read & (next_rd_addr == wr_addr_rclk))
-	 data_valid <= 0;
-       else if(next_rd_addr != wr_addr_rclk)
-	 data_valid <= 1;
-	 
-   // Send pointers across clock domains via gray code
-   gray_send #(.WIDTH(AWIDTH)) send_wr_addr
-     (.clk_in(wclk),.addr_in(wr_addr),
-      .clk_out(rclk),.addr_out(wr_addr_rclk) );
-   
-   gray_send #(.WIDTH(AWIDTH)) send_rd_addr
-     (.clk_in(rclk),.addr_in(rd_addr),
-      .clk_out(wclk),.addr_out(rd_addr_wclk) );
-
-   // Generate fullness info, these are approximate and may be delayed 
-   // and are only for higher-level flow control.  
-   // Only full and empty are guaranteed exact.
-   always @(posedge wclk) 
-     level_wclk <= wr_addr - rd_addr_wclk;
-   always @(posedge rclk) 
-     level_rclk <= wr_addr_rclk - rd_addr;
-`endif
-endmodule // fifo_2clock
-- 
cgit v1.2.3


From 09951ed9ba4758cc7cced26c1f673545284c5cf3 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Wed, 2 Sep 2009 17:56:26 -0700
Subject: major cleanup of 2 clock fifos

---
 control_lib/newfifo/.gitignore            |   1 +
 control_lib/newfifo/fifo_2clock.v         |  32 +++---
 control_lib/newfifo/fifo_2clock_cascade.v |  44 +++++----
 control_lib/newfifo/fifo_new_tb.v         | 158 ------------------------------
 control_lib/newfifo/fifo_tb.v             | 158 ++++++++++++++++++++++++++++++
 5 files changed, 206 insertions(+), 187 deletions(-)
 create mode 100644 control_lib/newfifo/.gitignore
 delete mode 100644 control_lib/newfifo/fifo_new_tb.v
 create mode 100644 control_lib/newfifo/fifo_tb.v

(limited to 'control_lib')

diff --git a/control_lib/newfifo/.gitignore b/control_lib/newfifo/.gitignore
new file mode 100644
index 000000000..cba7efc8e
--- /dev/null
+++ b/control_lib/newfifo/.gitignore
@@ -0,0 +1 @@
+a.out
diff --git a/control_lib/newfifo/fifo_2clock.v b/control_lib/newfifo/fifo_2clock.v
index 23a6f693c..40c479db7 100644
--- a/control_lib/newfifo/fifo_2clock.v
+++ b/control_lib/newfifo/fifo_2clock.v
@@ -1,23 +1,31 @@
 
-module newfifo_2clock
-  #(parameter DWIDTH=32, AWIDTH=9)
-  (input wclk, input [DWIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output reg [AWIDTH-1:0] level_wclk,
-   input rclk, output [DWIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output reg [AWIDTH-1:0] level_rclk,
-   input arst);
+// FIXME ignores the AWIDTH (fifo size) parameter
 
-   wire full, empty, write, read;
+module fifo_2clock
+  #(parameter WIDTH=32, SIZE=9)
+   (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space,
+    input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied,
+    input arst);
+   
+   wire [SIZE-1:0] level_rclk, level_wclk;
+   wire 	   full, empty, write, read;
 
    assign dst_rdy_o  = ~full;
    assign src_rdy_o  = ~empty;
    assign write      = src_rdy_i & dst_rdy_o;
    assign read 	     = src_rdy_o & dst_rdy_i;
-
-//`define USE_XLNX_FIFO 1
-`ifdef USE_XLNX_FIFO
+   
    fifo_xlnx_512x36_2clk mac_tx_fifo_2clk
      (.rst(rst),
-      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(fifo_occupied[8:0]),
-      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count() );   
+      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+
+   assign occupied  = {{(16-SIZE){1'b0}},level_rclk};
+   assign space = ((1<<SIZE)-1)-level_wclk;
+   
+endmodule // fifo_2clock
+
+/*
 `else
    // ISE sucks, so the following doesn't work properly
 
@@ -80,3 +88,5 @@ module newfifo_2clock
      level_rclk <= wr_addr_rclk - rd_addr;
 `endif
 endmodule // fifo_2clock
+
+*/
diff --git a/control_lib/newfifo/fifo_2clock_cascade.v b/control_lib/newfifo/fifo_2clock_cascade.v
index 2abbbf3b5..8d8a47954 100644
--- a/control_lib/newfifo/fifo_2clock_cascade.v
+++ b/control_lib/newfifo/fifo_2clock_cascade.v
@@ -1,27 +1,35 @@
 
-module cascadefifo_2clock
-  #(parameter DWIDTH=32, AWIDTH=9)
-    (input wclk, input [DWIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [AWIDTH-1:0] level_wclk,
-     input rclk, output [DWIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [AWIDTH-1:0] level_rclk,
-     input arst);
-
-   wire [DWIDTH-1:0] data_int1, data_int2;
-   wire src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2;
+module fifo_2clock_cascade
+  #(parameter WIDTH=32, SIZE=9)
+   (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space,
+    input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied,
+    input arst);
+   
+   wire [WIDTH-1:0] data_int1, data_int2;
+   wire 	    src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2;
+   wire [SIZE-1:0]  level_wclk, level_rclk;
+   wire [4:0] 	    s1_space, s1_occupied, s2_space, s2_occupied;
+   wire [15:0] 	    l_space, l_occupied;
    
-   fifo_short #(.WIDTH(DWIDTH)) shortfifo
+   fifo_short #(.WIDTH(WIDTH)) shortfifo
      (.clk(wclk), .reset(arst), .clear(0),
       .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
-      .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1) );
+      .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1),
+      .space(s1_space), .occupied(s1_occupied) );
    
-   newfifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock
-     (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .level_wclk(level_wclk),
-      .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .level_rclk(level_rclk),
+   fifo_2clock #(.DWIDTH(WIDTH),.SIZE(SIZE)) fifo_2clock
+     (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .space(l_space),
+      .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .occupied(l_occupied),
       .arst(arst) );
-
-   fifo_short #(.WIDTH(DWIDTH)) shortfifo2
+   
+   fifo_short #(.WIDTH(WIDTH)) shortfifo2
      (.clk(rclk), .reset(arst), .clear(0),
       .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
-      .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i) );
-   
-endmodule // fifo_2clock_casc
+      .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
+      .space(s2_space), .occupied(s2_occupied));
 
+   // Be conservative -- Only advertise space from input side of fifo, occupied from output side
+   assign 	    space = {11'b0,s1_space} + l_space;
+   assign 	    occupied = {11'b0,s2_occupied} + l_occupied;
+   
+endmodule // fifo_2clock_cascade
diff --git a/control_lib/newfifo/fifo_new_tb.v b/control_lib/newfifo/fifo_new_tb.v
deleted file mode 100644
index f561df7fa..000000000
--- a/control_lib/newfifo/fifo_new_tb.v
+++ /dev/null
@@ -1,158 +0,0 @@
-module fifo_new_tb();
-   
-   reg clk = 0;
-   reg rst = 1;
-   reg clear = 0;
-   initial #1000 rst = 0;
-   always #50 clk = ~clk;
-   
-   reg [31:0] f36_data = 0;
-   reg [1:0] f36_occ = 0;
-   reg f36_sof = 0, f36_eof = 0;
-   
-   wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data};
-   reg src_rdy_f36i  = 0;
-   wire dst_rdy_f36i;
-
-   wire [35:0] f36_out, f36_out2;
-   wire src_rdy_f36o;
-   reg dst_rdy_f36o  = 0;
-   
-   //fifo_cascade #(.WIDTH(36), .SIZE(4)) fifo_cascade36
-   //fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36
-
-   wire i1_sr, i1_dr;
-   wire i2_sr, i2_dr;
-   wire i3_sr, i3_dr;
-   reg i4_dr = 0;
-   wire i4_sr;
-      
-   wire [35:0] i1, i4;
-   wire [18:0] i2, i3;
-   
-   wire [7:0] ll_data;
-   wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n;
-   
-   fifo_short #(.WIDTH(36)) fifo_short1
-     (.clk(clk),.reset(rst),.clear(clear),
-      .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
-      .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) );
-
-   fifo36_to_fifo19 fifo36_to_fifo19
-     (.clk(clk),.reset(rst),.clear(clear),
-      .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr),
-      .f19_dataout(i2),.f19_src_rdy_o(i2_sr),.f19_dst_rdy_i(i2_dr) );
-
-   fifo19_to_ll8 fifo19_to_ll8
-     (.clk(clk),.reset(rst),.clear(clear),
-      .f19_data(i2),.f19_src_rdy_i(i2_sr),.f19_dst_rdy_o(i2_dr),
-      .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
-      .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n));
-
-   ll8_to_fifo19 ll8_to_fifo19
-     (.clk(clk),.reset(rst),.clear(clear),
-      .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
-      .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n),
-      .f19_data(i3),.f19_src_rdy_o(i3_sr),.f19_dst_rdy_i(i3_dr) );
-
-   fifo19_to_fifo36 fifo19_to_fifo36
-     (.clk(clk),.reset(rst),.clear(clear),
-      .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr),
-      .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) );
-     
-   task ReadFromFIFO36;
-      begin
-	 $display("Read from FIFO36");
-	 #1 i4_dr <= 1;
-	 while(1)
-	   begin
-	      while(~i4_sr)
-		@(posedge clk);
-	      $display("Read: %h",i4);
-	      @(posedge clk);
-	   end
-      end
-   endtask // ReadFromFIFO36
-
-   reg [15:0] count;
-   task PutPacketInFIFO36;
-      input [31:0] data_start;
-      input [31:0] data_len;
-      begin
-	 count 	      <= 4;
-	 src_rdy_f36i <= 1;
-	 f36_data     <= data_start;
-	 f36_sof      <= 1;
-	 f36_eof      <= 0;
-	 f36_occ      <= 0;
-	
-	 $display("Put Packet in FIFO36");
-	 while(~dst_rdy_f36i)
-	   @(posedge clk);
-	 @(posedge clk);
-	 $display("PPI_FIFO36: Entered First Line");
-	 f36_sof <= 0;
-	 while(count+4 < data_len)
-	   begin
-	      f36_data <= f36_data + 32'h01010101;
-	      count    <= count + 4;
-	      while(~dst_rdy_f36i)
-		@(posedge clk);
-	      @(posedge clk);
-	      $display("PPI_FIFO36: Entered New Line");
-	   end
-	 f36_data  <= f36_data + 32'h01010101;
-	 f36_eof   <= 1;
-	 if(count + 4 == data_len)
-	   f36_occ <= 0;
-	 else if(count + 3 == data_len)
-	   f36_occ <= 3;
-	 else if(count + 2 == data_len)
-	   f36_occ <= 2;
-	 else
-	   f36_occ <= 1;
-	 while(~dst_rdy_f36i)
-	   @(posedge clk);
-	 @(posedge clk);
-	 f36_occ      <= 0;
-	 f36_eof      <= 0;
-	 f36_data     <= 0;
-	 src_rdy_f36i <= 0;
-	 $display("PPI_FIFO36: Entered Last Line");
-      end
-   endtask // PutPacketInFIFO36
-   
-   initial $dumpfile("fifo_new_tb.vcd");
-   initial $dumpvars(0,fifo_new_tb);
-
-   initial
-     begin
-	@(negedge rst);
-	//#10000;
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	ReadFromFIFO36;
-     end
-   
-   initial
-     begin
-	@(negedge rst);
-	@(posedge clk);
-	@(posedge clk);
-	PutPacketInFIFO36(32'hA0B0C0D0,12);
-	@(posedge clk);
-	@(posedge clk);
-	#10000;
-	@(posedge clk);
-	PutPacketInFIFO36(32'hE0F0A0B0,36);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-     end
-
-   initial #20000 $finish;
-endmodule // longfifo_tb
diff --git a/control_lib/newfifo/fifo_tb.v b/control_lib/newfifo/fifo_tb.v
new file mode 100644
index 000000000..f561df7fa
--- /dev/null
+++ b/control_lib/newfifo/fifo_tb.v
@@ -0,0 +1,158 @@
+module fifo_new_tb();
+   
+   reg clk = 0;
+   reg rst = 1;
+   reg clear = 0;
+   initial #1000 rst = 0;
+   always #50 clk = ~clk;
+   
+   reg [31:0] f36_data = 0;
+   reg [1:0] f36_occ = 0;
+   reg f36_sof = 0, f36_eof = 0;
+   
+   wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data};
+   reg src_rdy_f36i  = 0;
+   wire dst_rdy_f36i;
+
+   wire [35:0] f36_out, f36_out2;
+   wire src_rdy_f36o;
+   reg dst_rdy_f36o  = 0;
+   
+   //fifo_cascade #(.WIDTH(36), .SIZE(4)) fifo_cascade36
+   //fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36
+
+   wire i1_sr, i1_dr;
+   wire i2_sr, i2_dr;
+   wire i3_sr, i3_dr;
+   reg i4_dr = 0;
+   wire i4_sr;
+      
+   wire [35:0] i1, i4;
+   wire [18:0] i2, i3;
+   
+   wire [7:0] ll_data;
+   wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n;
+   
+   fifo_short #(.WIDTH(36)) fifo_short1
+     (.clk(clk),.reset(rst),.clear(clear),
+      .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
+      .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) );
+
+   fifo36_to_fifo19 fifo36_to_fifo19
+     (.clk(clk),.reset(rst),.clear(clear),
+      .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr),
+      .f19_dataout(i2),.f19_src_rdy_o(i2_sr),.f19_dst_rdy_i(i2_dr) );
+
+   fifo19_to_ll8 fifo19_to_ll8
+     (.clk(clk),.reset(rst),.clear(clear),
+      .f19_data(i2),.f19_src_rdy_i(i2_sr),.f19_dst_rdy_o(i2_dr),
+      .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
+      .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n));
+
+   ll8_to_fifo19 ll8_to_fifo19
+     (.clk(clk),.reset(rst),.clear(clear),
+      .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
+      .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n),
+      .f19_data(i3),.f19_src_rdy_o(i3_sr),.f19_dst_rdy_i(i3_dr) );
+
+   fifo19_to_fifo36 fifo19_to_fifo36
+     (.clk(clk),.reset(rst),.clear(clear),
+      .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr),
+      .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) );
+     
+   task ReadFromFIFO36;
+      begin
+	 $display("Read from FIFO36");
+	 #1 i4_dr <= 1;
+	 while(1)
+	   begin
+	      while(~i4_sr)
+		@(posedge clk);
+	      $display("Read: %h",i4);
+	      @(posedge clk);
+	   end
+      end
+   endtask // ReadFromFIFO36
+
+   reg [15:0] count;
+   task PutPacketInFIFO36;
+      input [31:0] data_start;
+      input [31:0] data_len;
+      begin
+	 count 	      <= 4;
+	 src_rdy_f36i <= 1;
+	 f36_data     <= data_start;
+	 f36_sof      <= 1;
+	 f36_eof      <= 0;
+	 f36_occ      <= 0;
+	
+	 $display("Put Packet in FIFO36");
+	 while(~dst_rdy_f36i)
+	   @(posedge clk);
+	 @(posedge clk);
+	 $display("PPI_FIFO36: Entered First Line");
+	 f36_sof <= 0;
+	 while(count+4 < data_len)
+	   begin
+	      f36_data <= f36_data + 32'h01010101;
+	      count    <= count + 4;
+	      while(~dst_rdy_f36i)
+		@(posedge clk);
+	      @(posedge clk);
+	      $display("PPI_FIFO36: Entered New Line");
+	   end
+	 f36_data  <= f36_data + 32'h01010101;
+	 f36_eof   <= 1;
+	 if(count + 4 == data_len)
+	   f36_occ <= 0;
+	 else if(count + 3 == data_len)
+	   f36_occ <= 3;
+	 else if(count + 2 == data_len)
+	   f36_occ <= 2;
+	 else
+	   f36_occ <= 1;
+	 while(~dst_rdy_f36i)
+	   @(posedge clk);
+	 @(posedge clk);
+	 f36_occ      <= 0;
+	 f36_eof      <= 0;
+	 f36_data     <= 0;
+	 src_rdy_f36i <= 0;
+	 $display("PPI_FIFO36: Entered Last Line");
+      end
+   endtask // PutPacketInFIFO36
+   
+   initial $dumpfile("fifo_new_tb.vcd");
+   initial $dumpvars(0,fifo_new_tb);
+
+   initial
+     begin
+	@(negedge rst);
+	//#10000;
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	ReadFromFIFO36;
+     end
+   
+   initial
+     begin
+	@(negedge rst);
+	@(posedge clk);
+	@(posedge clk);
+	PutPacketInFIFO36(32'hA0B0C0D0,12);
+	@(posedge clk);
+	@(posedge clk);
+	#10000;
+	@(posedge clk);
+	PutPacketInFIFO36(32'hE0F0A0B0,36);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+     end
+
+   initial #20000 $finish;
+endmodule // longfifo_tb
-- 
cgit v1.2.3


From c811e886f5dbf61056834b3ef307ace1d5348aae Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Wed, 2 Sep 2009 21:27:18 -0700
Subject: bring the testbench files up to date

---
 control_lib/newfifo/fifo_2clock_cascade.v |   2 +-
 simple_gemac/eth_tasks_f36.v              |  33 ++++----
 simple_gemac/simple_gemac_wrapper.build   |   1 +
 simple_gemac/simple_gemac_wrapper_tb.v    | 131 ++++++++++++++----------------
 4 files changed, 79 insertions(+), 88 deletions(-)
 create mode 100755 simple_gemac/simple_gemac_wrapper.build

(limited to 'control_lib')

diff --git a/control_lib/newfifo/fifo_2clock_cascade.v b/control_lib/newfifo/fifo_2clock_cascade.v
index 8d8a47954..5ce726977 100644
--- a/control_lib/newfifo/fifo_2clock_cascade.v
+++ b/control_lib/newfifo/fifo_2clock_cascade.v
@@ -17,7 +17,7 @@ module fifo_2clock_cascade
       .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1),
       .space(s1_space), .occupied(s1_occupied) );
    
-   fifo_2clock #(.DWIDTH(WIDTH),.SIZE(SIZE)) fifo_2clock
+   fifo_2clock #(.WIDTH(WIDTH),.SIZE(SIZE)) fifo_2clock
      (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .space(l_space),
       .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .occupied(l_occupied),
       .arst(arst) );
diff --git a/simple_gemac/eth_tasks_f36.v b/simple_gemac/eth_tasks_f36.v
index b7fa52c07..efd72778b 100644
--- a/simple_gemac/eth_tasks_f36.v
+++ b/simple_gemac/eth_tasks_f36.v
@@ -5,9 +5,9 @@ task SendFlowCtrl;
    begin
       $display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time);
       pause_time <= fc_len;
-      @(posedge clk);
+      @(posedge eth_clk);
       pause_req <= 1;
-      @(posedge clk);
+      @(posedge eth_clk);
       pause_req <= 0;
       $display("Sent Flow Control");
    end
@@ -20,27 +20,27 @@ task SendPacket_to_fifo36;
    begin
       $display("Sending Packet Len=%d, %d", data_len, $time);
       count   <= 2;
-      tx_f36_dat <= {2'b0, 1'b0, 1'b1, data_start};
+      tx_f36_data <= {2'b0, 1'b0, 1'b1, data_start};
       tx_f36_src_rdy  <= 1;
       #1;
       while(count < data_len)
 	begin
 	   while(~tx_f36_dst_rdy)
-	     @(posedge clk);
-	   @(posedge clk);
-	   tx_f36_dat[31:0] = tx_f36_dat[31:0] + 32'h0101_0101;
+	     @(posedge sys_clk);
+	   @(posedge sys_clk);
+	   tx_f36_data[31:0] = tx_f36_data[31:0] + 32'h0101_0101;
 	   count 	   = count + 4;
-	   tx_f36_dat[32] <= 0;
+	   tx_f36_data[32] <= 0;
 	end
-      tx_f36_dat[3] 	  <= 1;
+      tx_f36_data[33] 	  <= 1;
       while(~tx_f36_dst_rdy)
-	@(posedge clk);
-      @(posedge clk);
+	@(posedge sys_clk);
+      @(posedge sys_clk);
       tx_f36_src_rdy <= 0;
    end
 endtask // SendPacket_to_fifo36
 
-
+/*
 task Waiter;
    input [31:0] wait_length;
    begin
@@ -50,7 +50,9 @@ task Waiter;
       tx_ll_src_rdy2 <= 1;
    end
 endtask // Waiter
+*/
 
+/*
 task SendPacketFromFile_f36;
    input [31:0] data_len;
    input [31:0] wait_length;
@@ -63,9 +65,9 @@ task SendPacketFromFile_f36;
 
       while(~tx_f36_dst_rdy)
 	@(posedge clk);
-      tx_f36_data2 <= pkt_rom[0];
+      tx_f36_data <= pkt_rom[0];
       tx_f36_src_rdy <= 1;
-      tx_ll_eof2     <= 0;
+      tx_f36_eof     <= 0;
       @(posedge clk);
       
       for(i=1;i<data_len-1;i=i+1)
@@ -75,8 +77,8 @@ task SendPacketFromFile_f36;
 	   tx_ll_data2 <= pkt_rom[i];
 	   tx_ll_sof2  <= 0;
 	   @(posedge clk);
-	   if(i==wait_time)
-	     Waiter(wait_length);
+//	   if(i==wait_time)
+//	     Waiter(wait_length);
 	end
       
       while(~tx_ll_dst_rdy2)
@@ -87,3 +89,4 @@ task SendPacketFromFile_f36;
       tx_ll_src_rdy2 <= 0;
    end
 endtask
+*/
diff --git a/simple_gemac/simple_gemac_wrapper.build b/simple_gemac/simple_gemac_wrapper.build
new file mode 100755
index 000000000..30f65ab17
--- /dev/null
+++ b/simple_gemac/simple_gemac_wrapper.build
@@ -0,0 +1 @@
+iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v
diff --git a/simple_gemac/simple_gemac_wrapper_tb.v b/simple_gemac/simple_gemac_wrapper_tb.v
index b51afa5bb..164b50724 100644
--- a/simple_gemac/simple_gemac_wrapper_tb.v
+++ b/simple_gemac/simple_gemac_wrapper_tb.v
@@ -1,18 +1,21 @@
 
 
 module simple_gemac_wrapper_tb;
-`include "eth_tasks.v"
+`include "eth_tasks_f36.v"
      
-   reg clk     = 0;
    reg reset   = 1;
-
    initial #1000 reset = 0;
-   always #50 clk = ~clk;
+   wire wb_rst 	= reset;
+
+   reg eth_clk     = 0;
+   always #50 eth_clk = ~eth_clk;
 
    reg wb_clk 	= 0;
-   wire wb_rst 	= reset;
    always #173 wb_clk = ~wb_clk;
-       
+
+   reg sys_clk 	= 0;
+   always #77 sys_clk = ~ sys_clk;
+   
    wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
    wire [7:0] GMII_RXD, GMII_TXD;
 
@@ -35,55 +38,32 @@ module simple_gemac_wrapper_tb;
    assign GMII_RXD    = GMII_TXD ^ FORCE_DAT_ERR;
 
 
-   wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
-   wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2;
-   reg rx_ll_dst_rdy2 = 1;
-   wire [7:0] rx_ll_data, rx_ll_data2;
-   wire rx_ll_error, rx_ll_error2;
-
    wire [31:0] wb_dat_o;
    reg [31:0]  wb_dat_i;
    reg [7:0]   wb_adr;
    reg 	       wb_stb=0, wb_cyc=0, wb_we=0;
    wire        wb_ack;
+
+   reg [35:0]  tx_f36_data=0;
+   reg 	       tx_f36_src_rdy=0;
+   wire        tx_f36_dst_rdy;
    
    simple_gemac_wrapper simple_gemac_wrapper
-     (.clk125(clk),  .reset(reset),
+     (.clk125(eth_clk),  .reset(reset),
       .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
       .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
       .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
       .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
       .pause_req(pause_req), .pause_time(pause_time),
-      .rx_clk(rx_clk), .rx_ll_data(rx_ll_data), .rx_ll_sof(rx_ll_sof),
-      .rx_ll_eof(rx_ll_eof), .rx_ll_src_rdy(rx_ll_src_rdy), .rx_ll_dst_rdy(rx_ll_dst_rdy),
-      .tx_clk(tx_clk), .tx_ll_data(tx_ll_data), .tx_ll_sof(tx_ll_sof),
-      .tx_ll_eof(tx_ll_eof), .tx_ll_src_rdy(tx_ll_src_rdy), .tx_ll_dst_rdy(tx_ll_dst_rdy),
-      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack),
-      .wb_we(wb_we), .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
-      .mdio(mdio), .mdc(mdc) );
-
-   ll8_shortfifo rx_sfifo
-     (.clk(clk), .reset(reset), .clear(0),
-      .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
-      .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
-      .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
-      .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
-
-   wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
-   reg tx_ll_sof2=0, tx_ll_eof2=0;
-   reg tx_ll_src_rdy2 = 0;
-   wire tx_ll_dst_rdy2;
-   wire [7:0] tx_ll_data;
-   reg [7:0] tx_ll_data2 = 0;
-   wire tx_ll_error;
-   wire tx_ll_error2 = 0;
-
-   ll8_shortfifo tx_sfifo
-     (.clk(clk), .reset(reset), .clear(clear),
-      .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
-      .error_i(tx_ll_error2), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
-      .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
-      .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
+
+      .sys_clk(sys_clk), .rx_f36_data(), .rx_f36_src_rdy(), .rx_f36_dst_rdy(),
+      .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy),
+
+      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we),
+      .wb_adr(), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
+
+      .mdio(), .mdc(),
+      .debug() );
    
    initial $dumpfile("simple_gemac_wrapper_tb.vcd");
    initial $dumpvars(0,simple_gemac_wrapper_tb);
@@ -100,67 +80,74 @@ module simple_gemac_wrapper_tb;
      begin
 	@(negedge reset);
 	repeat (10)
-	  @(posedge clk);
+	  @(posedge wb_clk);
 	WishboneWR(0,6'b111001);
 	WishboneWR(4,16'hF1F2);
 	WishboneWR(8,32'hF3F4_F5F6);
 	WishboneWR(12,16'h0000);
 	WishboneWR(16,32'h0000_0000);
 	
-	@(posedge clk);
+	@(posedge eth_clk);
 	SendFlowCtrl(16'h0007);  // Send flow control
-	@(posedge clk);
+	@(posedge eth_clk);
 	#30000;
-	@(posedge clk);
-	SendFlowCtrl(16'h0009);  // Increas flow control before it expires
+	@(posedge eth_clk);
+	SendFlowCtrl(16'h0009);  // Increase flow control before it expires
 	#10000;
-	@(posedge clk);
+	@(posedge eth_clk);
 	SendFlowCtrl(16'h0000);  // Cancel flow control before it expires
-	@(posedge clk); 
+	@(posedge eth_clk); 
 
-	SendPacket_to_ll8(8'hAA,10);    // This packet gets dropped by the filters
-	repeat (10)
-	  @(posedge clk);
+	repeat (1000)
+	  @(posedge sys_clk);
+	SendPacket_to_fifo36(32'hAABBCCDD,10);    // This packet gets dropped by the filters
+	repeat (1000)
+	  @(posedge sys_clk);
 
- 	SendPacketFromFile_ll8(60,0,0);  // The rest are valid packets
+	SendPacket_to_fifo36(32'hAABBCCDD,100);    // This packet gets dropped by the filters
+	repeat (10)
+	  @(posedge sys_clk);
+/*
+ 	SendPacketFromFile_f36(60,0,0);  // The rest are valid packets
 	repeat (10)
 	  @(posedge clk);
 
- 	SendPacketFromFile_ll8(61,0,0);
+ 	SendPacketFromFile_f36(61,0,0);
 	repeat (10)
 	  @(posedge clk);
-	SendPacketFromFile_ll8(62,0,0);
+	SendPacketFromFile_f36(62,0,0);
 	repeat (10)
 	  @(posedge clk);
-	SendPacketFromFile_ll8(63,0,0);
+	SendPacketFromFile_f36(63,0,0);
 	repeat (1)
 	  @(posedge clk);
-	SendPacketFromFile_ll8(64,0,0);
+	SendPacketFromFile_f36(64,0,0);
 	repeat (10)
 	  @(posedge clk);
-	SendPacketFromFile_ll8(59,0,0);
+	SendPacketFromFile_f36(59,0,0);
 	repeat (1)
 	  @(posedge clk);
-	SendPacketFromFile_ll8(58,0,0);
+	SendPacketFromFile_f36(58,0,0);
 	repeat (1)
 	  @(posedge clk);
-	SendPacketFromFile_ll8(100,0,0);
+	SendPacketFromFile_f36(100,0,0);
 	repeat (1)
 	  @(posedge clk);
-	SendPacketFromFile_ll8(200,150,30);  // waiting 14 empties the fifo, 15 underruns
+	SendPacketFromFile_f36(200,150,30);  // waiting 14 empties the fifo, 15 underruns
 	repeat (1)
 	  @(posedge clk);
-	SendPacketFromFile_ll8(100,0,30);
-	#10000 $finish;
+	SendPacketFromFile_f36(100,0,30);
+ */
+	#100000 $finish;
      end
 
    // Force a CRC error
     initial
      begin
 	#90000;
-	@(posedge clk);
+	@(posedge eth_clk);
 	FORCE_DAT_ERR <= 8'h10;
-	@(posedge clk);
+	@(posedge eth_clk);
 	FORCE_DAT_ERR <= 8'h00;
      end
 
@@ -168,12 +155,12 @@ module simple_gemac_wrapper_tb;
    initial
      begin
 	#116000;
-	@(posedge clk);
+	@(posedge eth_clk);
 	FORCE_ERR <= 1;
-	@(posedge clk);
+	@(posedge eth_clk);
 	FORCE_ERR <= 0;
      end
-
+/*
    // Cause receive fifo to fill, causing an RX overrun
    initial
      begin
@@ -184,7 +171,7 @@ module simple_gemac_wrapper_tb;
 	  @(posedge clk);
 	rx_ll_dst_rdy2 <= 1;
      end
-   
+  */
    // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun
    // Still need to test: CRC errors on Pause Frames, MDIO, wishbone
 
@@ -205,7 +192,7 @@ module simple_gemac_wrapper_tb;
 	 wb_we 	<= 0;
       end
    endtask // WishboneWR
-   
+   /*
    always @(posedge clk)
      if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)
        begin
@@ -215,5 +202,5 @@ module simple_gemac_wrapper_tb;
 	  if(rx_ll_eof2 & ~rx_ll_sof2)
 	    $display("RX-PKT-END %d",$time);
        end
-   
+   */
 endmodule // simple_gemac_wrapper_tb
-- 
cgit v1.2.3


From 5ce99ee61bad4f9c421a873aa2f3144e8e2aebe7 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 3 Sep 2009 14:13:44 -0700
Subject: MAC transmit seems to work now.  The root cause of the problem was
 accidentally using the rx_clk in one stage of the fifos on the tx side.

---
 control_lib/newfifo/fifo_2clock.v      | 33 ++++++++++++++------
 simple_gemac/simple_gemac_wrapper.v    | 31 ++++++++++++-------
 simple_gemac/simple_gemac_wrapper_tb.v | 17 ++++++-----
 top/u2_rev3/Makefile                   | 56 +++++++++++-----------------------
 4 files changed, 70 insertions(+), 67 deletions(-)

(limited to 'control_lib')

diff --git a/control_lib/newfifo/fifo_2clock.v b/control_lib/newfifo/fifo_2clock.v
index 40c479db7..2ada39fb0 100644
--- a/control_lib/newfifo/fifo_2clock.v
+++ b/control_lib/newfifo/fifo_2clock.v
@@ -2,26 +2,39 @@
 // FIXME ignores the AWIDTH (fifo size) parameter
 
 module fifo_2clock
-  #(parameter WIDTH=32, SIZE=9)
+  #(parameter WIDTH=36, SIZE=6)
    (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space,
     input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied,
     input arst);
    
-   wire [SIZE-1:0] level_rclk, level_wclk;
-   wire 	   full, empty, write, read;
+   wire [SIZE:0] level_rclk, level_wclk; // xilinx adds an extra bit if you ask for accurate levels
+   wire 	 full, empty, write, read;
 
    assign dst_rdy_o  = ~full;
    assign src_rdy_o  = ~empty;
    assign write      = src_rdy_i & dst_rdy_o;
    assign read 	     = src_rdy_o & dst_rdy_i;
-   
-   fifo_xlnx_512x36_2clk mac_tx_fifo_2clk
-     (.rst(rst),
-      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
-      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
 
-   assign occupied  = {{(16-SIZE){1'b0}},level_rclk};
-   assign space = ((1<<SIZE)-1)-level_wclk;
+   generate
+      if(SIZE==9)
+	fifo_xlnx_512x36_2clk mac_tx_fifo_2clk
+	      (.rst(rst),
+	       .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+	       .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+      else if(SIZE==11)
+	fifo_xlnx_2Kx36_2clk mac_tx_fifo_2clk
+	      (.rst(rst),
+	       .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+	       .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+      else if(SIZE==6)
+	fifo_xlnx_64x36_2clk mac_tx_fifo_2clk
+		   (.rst(rst),
+		    .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+		    .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+   endgenerate
+   
+   assign occupied  = {{(16-SIZE-1){1'b0}},level_rclk};
+   assign space     = ((1<<SIZE)+1)-level_wclk;
    
 endmodule // fifo_2clock
 
diff --git a/simple_gemac/simple_gemac_wrapper.v b/simple_gemac/simple_gemac_wrapper.v
index 31bc02ebb..b9bc05848 100644
--- a/simple_gemac/simple_gemac_wrapper.v
+++ b/simple_gemac/simple_gemac_wrapper.v
@@ -59,8 +59,12 @@ module simple_gemac_wrapper
 
    // RX FIFO Chain
    wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
-   wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2_n, rx_ll_dst_rdy2;
+
+   wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2;
+   wire rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n;
+
    wire [7:0] rx_ll_data, rx_ll_data2;
+
    wire [35:0] rx_f36_data_int1;
    wire        rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1;
    
@@ -75,19 +79,24 @@ module simple_gemac_wrapper
       .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
       .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
       .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
-      .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(~rx_ll_dst_rdy2_n));
+      .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
 
+   assign rx_ll_dst_rdy2  = ~rx_ll_dst_rdy2_n;
+   assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2;
+   assign rx_ll_sof2_n 	  = ~rx_ll_sof2;
+   assign rx_ll_eof2_n 	  = ~rx_ll_eof2;
+   
    ll8_to_fifo36 ll8_to_fifo36
      (.clk(rx_clk), .reset(rx_reset), .clear(0),
-      .ll_data(rx_ll_data2), .ll_sof_n(~rx_ll_sof2), .ll_eof_n(~rx_ll_eof2),
-      .ll_src_rdy_n(~rx_ll_src_rdy2), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
+      .ll_data(rx_ll_data2), .ll_sof_n(rx_ll_sof2_n), .ll_eof_n(rx_ll_eof2_n),
+      .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
       .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1), .f36_dst_rdy_i(rx_f36_dst_rdy_int1));
 
-   cascadefifo_2clock #(.DWIDTH(36), .AWIDTH(9)) rx_2clk_fifo
+   fifo_2clock_cascade #(.WIDTH(36), .SIZE(6)) rx_2clk_fifo
      (.wclk(rx_clk), .datain(rx_f36_data_int1), 
-      .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .level_wclk(),
+      .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .space(),
       .rclk(sys_clk), .dataout(rx_f36_data), 
-      .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .level_rclk(), .arst(reset));
+      .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .occupied(), .arst(reset));
    
    // TX FIFO Chain
    wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
@@ -97,11 +106,11 @@ module simple_gemac_wrapper
    wire [35:0] tx_f36_data_int1;
    wire        tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1;
 
-   cascadefifo_2clock #(.DWIDTH(36), .AWIDTH(9)) tx_2clk_fifo
+   fifo_2clock #(.WIDTH(36), .SIZE(6)) tx_2clk_fifo
      (.wclk(sys_clk), .datain(tx_f36_data), 
-      .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .level_wclk(),
+      .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(),
       .rclk(tx_clk), .dataout(tx_f36_data_int1), 
-      .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .level_rclk(), .arst(reset));
+      .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), .arst(reset));
    
    fifo36_to_ll8 fifo36_to_ll8
      (.clk(tx_clk), .reset(tx_reset), .clear(clear),
@@ -115,7 +124,7 @@ module simple_gemac_wrapper
    assign tx_ll_dst_rdy2_n  = ~tx_ll_dst_rdy2;
    
    ll8_shortfifo tx_sfifo
-     (.clk(rx_clk), .reset(tx_reset), .clear(clear),
+     (.clk(tx_clk), .reset(tx_reset), .clear(clear),
       .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
       .error_i(0), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
       .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
diff --git a/simple_gemac/simple_gemac_wrapper_tb.v b/simple_gemac/simple_gemac_wrapper_tb.v
index 164b50724..26a471a49 100644
--- a/simple_gemac/simple_gemac_wrapper_tb.v
+++ b/simple_gemac/simple_gemac_wrapper_tb.v
@@ -45,8 +45,11 @@ module simple_gemac_wrapper_tb;
    wire        wb_ack;
 
    reg [35:0]  tx_f36_data=0;
-   reg 	       tx_f36_src_rdy=0;
+   reg 	       tx_f36_src_rdy = 0;
    wire        tx_f36_dst_rdy;
+   wire        rx_f36_data;
+   wire        rx_f36_src_rdy;
+   wire        rx_f36_dst_rdy = 1;
    
    simple_gemac_wrapper simple_gemac_wrapper
      (.clk125(eth_clk),  .reset(reset),
@@ -56,11 +59,11 @@ module simple_gemac_wrapper_tb;
       .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
       .pause_req(pause_req), .pause_time(pause_time),
 
-      .sys_clk(sys_clk), .rx_f36_data(), .rx_f36_src_rdy(), .rx_f36_dst_rdy(),
+      .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
       .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy),
 
       .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we),
-      .wb_adr(), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
+      .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
 
       .mdio(), .mdc(),
       .debug() );
@@ -81,9 +84,9 @@ module simple_gemac_wrapper_tb;
 	@(negedge reset);
 	repeat (10)
 	  @(posedge wb_clk);
-	WishboneWR(0,6'b111001);
-	WishboneWR(4,16'hF1F2);
-	WishboneWR(8,32'hF3F4_F5F6);
+	WishboneWR(0,6'b111101); 
+	WishboneWR(4,16'hA0B0);
+	WishboneWR(8,32'hC0D0_A1B1);
 	WishboneWR(12,16'h0000);
 	WishboneWR(16,32'h0000_0000);
 	
@@ -100,7 +103,7 @@ module simple_gemac_wrapper_tb;
 
 	repeat (1000)
 	  @(posedge sys_clk);
-	SendPacket_to_fifo36(32'hAABBCCDD,10);    // This packet gets dropped by the filters
+	SendPacket_to_fifo36(32'hA0B0C0D0,10);    // This packet gets dropped by the filters
 	repeat (1000)
 	  @(posedge sys_clk);
 
diff --git a/top/u2_rev3/Makefile b/top/u2_rev3/Makefile
index 5d782b610..7847b8c72 100644
--- a/top/u2_rev3/Makefile
+++ b/top/u2_rev3/Makefile
@@ -56,20 +56,12 @@ export SOURCES := \
 control_lib/CRC16_D16.v \
 control_lib/atr_controller.v \
 control_lib/bin2gray.v \
-control_lib/newfifo/buffer_int.v \
-control_lib/newfifo/buffer_pool.v \
-control_lib/cascadefifo2.v \
 control_lib/dcache.v \
 control_lib/decoder_3_8.v \
 control_lib/dpram32.v \
-control_lib/fifo_2clock.v \
-control_lib/fifo_2clock_casc.v \
-control_lib/newfifo/newfifo_2clock.v \
-control_lib/newfifo/cascadefifo_2clock.v \
 control_lib/gray2bin.v \
 control_lib/gray_send.v \
 control_lib/icache.v \
-control_lib/longfifo.v \
 control_lib/mux4.v \
 control_lib/mux8.v \
 control_lib/nsgpio.v \
@@ -78,8 +70,6 @@ control_lib/ram_harv_cache.v \
 control_lib/ram_loader.v \
 control_lib/setting_reg.v \
 control_lib/settings_bus.v \
-control_lib/shortfifo.v \
-control_lib/medfifo.v \
 control_lib/srl.v \
 control_lib/system_control.v \
 control_lib/wb_1master.v \
@@ -101,43 +91,31 @@ simple_gemac/crc.v \
 simple_gemac/delay_line.v \
 simple_gemac/flow_ctrl_tx.v \
 simple_gemac/address_filter.v \
-control_lib/newfifo/ll8_shortfifo.v \
-control_lib/newfifo/ll8_to_fifo36.v \
 simple_gemac/ll8_to_txmac.v \
 simple_gemac/rxmac_to_ll8.v \
+simple_gemac/miim/eth_miim.v \
+simple_gemac/miim/eth_clockgen.v \
+simple_gemac/miim/eth_outputcontrol.v \
+simple_gemac/miim/eth_shiftreg.v \
+control_lib/newfifo/buffer_int.v \
+control_lib/newfifo/buffer_pool.v \
+control_lib/newfifo/fifo_2clock.v \
+control_lib/newfifo/fifo_2clock_cascade.v \
+control_lib/newfifo/ll8_shortfifo.v \
+control_lib/newfifo/ll8_to_fifo36.v \
 control_lib/newfifo/fifo_short.v \
+control_lib/newfifo/fifo_long.v \
+control_lib/newfifo/fifo_cascade.v \
 control_lib/newfifo/fifo36_to_ll8.v \
+control_lib/longfifo.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
 coregen/fifo_xlnx_2Kx36_2clk.v \
 coregen/fifo_xlnx_2Kx36_2clk.xco \
 coregen/fifo_xlnx_512x36_2clk.v \
 coregen/fifo_xlnx_512x36_2clk.xco \
-eth/mac_rxfifo_int.v \
-eth/mac_txfifo_int.v \
-eth/rtl/verilog/Clk_ctrl.v \
-eth/rtl/verilog/MAC_rx.v \
-eth/rtl/verilog/MAC_rx/Broadcast_filter.v \
-eth/rtl/verilog/MAC_rx/CRC_chk.v \
-eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \
-eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \
-eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \
-eth/rtl/verilog/MAC_top.v \
-eth/rtl/verilog/MAC_tx.v \
-eth/rtl/verilog/MAC_tx/CRC_gen.v \
-eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \
-eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \
-eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \
-eth/rtl/verilog/MAC_tx/Random_gen.v \
-eth/rtl/verilog/Phy_int.v \
-eth/rtl/verilog/RMON.v \
-eth/rtl/verilog/RMON/RMON_addr_gen.v \
-eth/rtl/verilog/RMON/RMON_ctrl.v \
-eth/rtl/verilog/Reg_int.v \
-eth/rtl/verilog/eth_miim.v \
-eth/rtl/verilog/flow_ctrl_rx.v \
-eth/rtl/verilog/flow_ctrl_tx.v \
-eth/rtl/verilog/miim/eth_clockgen.v \
-eth/rtl/verilog/miim/eth_outputcontrol.v \
-eth/rtl/verilog/miim/eth_shiftreg.v \
+coregen/fifo_xlnx_64x36_2clk.v \
+coregen/fifo_xlnx_64x36_2clk.xco \
 extram/wb_zbt16_b.v \
 opencores/8b10b/decode_8b10b.v \
 opencores/8b10b/encode_8b10b.v \
-- 
cgit v1.2.3


From 1d26231a1a541eb4015f38409a85ce97a4e98bd7 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Fri, 4 Sep 2009 16:33:00 -0700
Subject: no longer used, replaced by newfifo version

---
 control_lib/fifo_2clock.v | 66 -----------------------------------------------
 1 file changed, 66 deletions(-)
 delete mode 100644 control_lib/fifo_2clock.v

(limited to 'control_lib')

diff --git a/control_lib/fifo_2clock.v b/control_lib/fifo_2clock.v
deleted file mode 100644
index 6b1eb607e..000000000
--- a/control_lib/fifo_2clock.v
+++ /dev/null
@@ -1,66 +0,0 @@
-
-module fifo_2clock
-  #(parameter DWIDTH=32, AWIDTH=9)
-    (input wclk, input [DWIDTH-1:0] datain, input write, output full, output reg [AWIDTH-1:0] level_wclk,
-     input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output reg [AWIDTH-1:0] level_rclk,
-     input arst);
-
-   reg [AWIDTH-1:0] wr_addr, rd_addr;
-   wire [AWIDTH-1:0] wr_addr_rclk, rd_addr_wclk;
-   wire [AWIDTH-1:0] next_rd_addr;
-   wire 	    enb_read;
-   
-   // Write side management
-   wire [AWIDTH-1:0] next_wr_addr = wr_addr + 1;
-   always @(posedge wclk or posedge arst)
-     if(arst)
-       wr_addr <= 0;
-     else if(write)
-       wr_addr <= next_wr_addr;
-   assign 	    full = (next_wr_addr == rd_addr_wclk);
-
-   //  RAM for data storage.  Data out is registered, complicating the
-   //     read side logic
-   ram_2port #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) mac_rx_ff_ram
-     (.clka(wclk),.ena(1'b1),.wea(write),.addra(wr_addr),.dia(datain),.doa(),
-      .clkb(rclk),.enb(enb_read),.web(1'b0),.addrb(next_rd_addr),.dib(0),.dob(dataout) );
-
-   // Read side management
-   reg 		    data_valid;
-   assign 	    empty = ~data_valid;
-   assign 	    next_rd_addr = rd_addr + data_valid;
-   assign 	    enb_read = read | ~data_valid;
-
-   always @(posedge rclk or posedge arst)
-     if(arst)
-       rd_addr <= 0;
-     else if(read)
-       rd_addr <= rd_addr + 1;
-
-   always @(posedge rclk or posedge arst)
-     if(arst)
-       data_valid <= 0;
-     else
-       if(read & (next_rd_addr == wr_addr_rclk))
-	 data_valid <= 0;
-       else if(next_rd_addr != wr_addr_rclk)
-	 data_valid <= 1;
-	 
-   // Send pointers across clock domains via gray code
-   gray_send #(.WIDTH(AWIDTH)) send_wr_addr
-     (.clk_in(wclk),.addr_in(wr_addr),
-      .clk_out(rclk),.addr_out(wr_addr_rclk) );
-   
-   gray_send #(.WIDTH(AWIDTH)) send_rd_addr
-     (.clk_in(rclk),.addr_in(rd_addr),
-      .clk_out(wclk),.addr_out(rd_addr_wclk) );
-
-   // Generate fullness info, these are approximate and may be delayed 
-   // and are only for higher-level flow control.  
-   // Only full and empty are guaranteed exact.
-   always @(posedge wclk) 
-     level_wclk <= wr_addr - rd_addr_wclk;
-   always @(posedge rclk) 
-     level_rclk <= wr_addr_rclk - rd_addr;
-   
-endmodule // fifo_2clock
-- 
cgit v1.2.3


From e50bab11b3cdc30ffebb51f64ffe9f0ef74bdc55 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Fri, 4 Sep 2009 22:14:21 -0700
Subject: remove unused old style fifo

---
 control_lib/fifo_2clock_casc.v | 31 -------------------------------
 1 file changed, 31 deletions(-)
 delete mode 100644 control_lib/fifo_2clock_casc.v

(limited to 'control_lib')

diff --git a/control_lib/fifo_2clock_casc.v b/control_lib/fifo_2clock_casc.v
deleted file mode 100644
index e9b0cfc25..000000000
--- a/control_lib/fifo_2clock_casc.v
+++ /dev/null
@@ -1,31 +0,0 @@
-
-module fifo_2clock_casc
-  #(parameter DWIDTH=32, AWIDTH=9)
-    (input wclk, input [DWIDTH-1:0] datain, input write, output full, output [AWIDTH-1:0] level_wclk,
-     input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output [AWIDTH-1:0] level_rclk,
-     input arst);
-
-   wire    full_int, empty_int, full_int2, empty_int2, transfer, transfer2;
-   wire [DWIDTH-1:0] data_int, data_int2;
-   
-   shortfifo #(.WIDTH(DWIDTH)) shortfifo
-     (.clk(wclk), .rst(arst), .clear(0),
-      .datain(datain), .write(write), .full(full),
-      .dataout(data_int), .read(transfer), .empty(empty_int) );
-
-   assign  transfer = ~full_int & ~empty_int;
-   
-   fifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock
-     (.wclk(wclk), .datain(data_int), .write(transfer), .full(full_int), .level_wclk(level_wclk),
-      .rclk(rclk), .dataout(data_int2), .read(transfer2), .empty(empty_int2), .level_rclk(level_rclk),
-      .arst(arst) );
-
-   assign  transfer2 = ~full_int2 & ~empty_int2;
-
-   shortfifo #(.WIDTH(DWIDTH)) shortfifo2
-     (.clk(rclk), .rst(arst), .clear(0),
-      .datain(data_int2), .write(transfer2), .full(full_int2),
-      .dataout(dataout), .read(read), .empty(empty) );
-   
-endmodule // fifo_2clock_casc
-
-- 
cgit v1.2.3


From 2f3e0eefe01b61f8e5e12d2ceef6990abb8a1ff3 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 10 Sep 2009 21:52:06 -0700
Subject: More xilinx fifos, more clean up of our fifos

---
 control_lib/cascadefifo2.v                         |  56 -------
 control_lib/newfifo/fifo18_to_ll8.v                |  58 -------
 control_lib/newfifo/fifo_2clock.v                  |  42 +++--
 coregen/fifo_xlnx_16x19_2clk.ngc                   |   3 +
 coregen/fifo_xlnx_16x19_2clk.v                     | 169 +++++++++++++++++++++
 coregen/fifo_xlnx_16x19_2clk.veo                   |  53 +++++++
 coregen/fifo_xlnx_16x19_2clk.xco                   |  82 ++++++++++
 ...o_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso |   3 +
 ...x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt | 103 +++++++++++++
 coregen/fifo_xlnx_16x19_2clk_flist.txt             |   8 +
 coregen/fifo_xlnx_16x19_2clk_readme.txt            |  39 +++++
 coregen/fifo_xlnx_16x19_2clk_xmdf.tcl              |  68 +++++++++
 12 files changed, 555 insertions(+), 129 deletions(-)
 delete mode 100644 control_lib/cascadefifo2.v
 delete mode 100644 control_lib/newfifo/fifo18_to_ll8.v
 create mode 100644 coregen/fifo_xlnx_16x19_2clk.ngc
 create mode 100644 coregen/fifo_xlnx_16x19_2clk.v
 create mode 100644 coregen/fifo_xlnx_16x19_2clk.veo
 create mode 100644 coregen/fifo_xlnx_16x19_2clk.xco
 create mode 100644 coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso
 create mode 100644 coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
 create mode 100644 coregen/fifo_xlnx_16x19_2clk_flist.txt
 create mode 100644 coregen/fifo_xlnx_16x19_2clk_readme.txt
 create mode 100644 coregen/fifo_xlnx_16x19_2clk_xmdf.tcl

(limited to 'control_lib')

diff --git a/control_lib/cascadefifo2.v b/control_lib/cascadefifo2.v
deleted file mode 100644
index 984cc46e6..000000000
--- a/control_lib/cascadefifo2.v
+++ /dev/null
@@ -1,56 +0,0 @@
-
-
-// This FIFO exists to provide an intermediate point for the data on its
-// long trek from one RAM (in the buffer pool) to another (in the longfifo)
-// The shortfifo is more flexible in its placement since it is based on
-// distributed RAM
-
-// This one has the shortfifo on both the in and out sides.
-module cascadefifo2
-  #(parameter WIDTH=32, SIZE=9)
-    (input clk, input rst,
-     input [WIDTH-1:0] datain,
-     output [WIDTH-1:0] dataout,
-     input read,
-     input write,
-     input clear,
-     output full,
-     output empty,
-     output [15:0] space,
-     output [15:0] occupied);
-
-   wire [WIDTH-1:0] data_int, data_int2;
-   wire 	    empty_int, full_int, transfer;
-   wire 	    empty_int2, full_int2, transfer2;
-   wire [4:0] 	    s1_space, s1_occupied, s2_space, s2_occupied;
-   wire [15:0] 	    l_space, l_occupied;
-   
-   shortfifo #(.WIDTH(WIDTH)) shortfifo
-     (.clk(clk),.rst(rst),.clear(clear),
-      .datain(datain), .write(write), .full(full),
-      .dataout(data_int), .read(transfer), .empty(empty_int),
-      .space(s1_space),.occupied(s1_occupied) );
-      
-   longfifo #(.WIDTH(WIDTH),.SIZE(SIZE)) longfifo
-     (.clk(clk),.rst(rst),.clear(clear),
-      .datain(data_int), .write(transfer), .full(full_int),
-      .dataout(data_int2), .read(transfer2), .empty(empty_int2),
-      .space(l_space),.occupied(l_occupied) );
-   
-   shortfifo #(.WIDTH(WIDTH)) shortfifo2
-     (.clk(clk),.rst(rst),.clear(clear),
-      .datain(data_int2), .write(transfer2), .full(full_int2),
-      .dataout(dataout), .read(read), .empty(empty),
-      .space(s2_space),.occupied(s2_occupied) );
-   
-   assign 	    transfer = ~empty_int & ~full_int; 	    
-   assign 	    transfer2 = ~empty_int2 & ~full_int2; 	    
-   
-   assign 	    space = {11'b0,s1_space} + {11'b0,s2_space} + l_space;
-   assign 	    occupied = {11'b0,s1_occupied} + {11'b0,s2_occupied} + l_occupied;
-      
-endmodule // cascadefifo2
-
-
-
-
diff --git a/control_lib/newfifo/fifo18_to_ll8.v b/control_lib/newfifo/fifo18_to_ll8.v
deleted file mode 100644
index 4653244ef..000000000
--- a/control_lib/newfifo/fifo18_to_ll8.v
+++ /dev/null
@@ -1,58 +0,0 @@
-
-module fifo18_to_ll8
-  (input clk, input reset, input clear,
-   input [35:0] f18_data,
-   input f18_src_rdy_i,
-   output f18_dst_rdy_o,
-
-   output reg [7:0] ll_data,
-   output ll_sof_n,
-   output ll_eof_n,
-   output ll_src_rdy_n,
-   input ll_dst_rdy_n);
-
-   wire  ll_sof, ll_eof, ll_src_rdy;
-   assign ll_sof_n = ~ll_sof;
-   assign ll_eof_n = ~ll_eof;
-   assign ll_src_rdy_n = ~ll_src_rdy;
-   wire ll_dst_rdy = ~ll_dst_rdy_n;
-
-   wire   f18_sof = f18_data[32];
-   wire   f18_eof = f18_data[33];
-   wire   f18_occ = f18_data[35:34];
-   wire advance, end_early;
-   reg [1:0] state;
-   assign debug    = {29'b0,state};
-
-   always @(posedge clk)
-     if(reset)
-       state 	  <= 0;
-     else
-       if(advance)
-	 if(ll_eof)
-	   state  <= 0;
-	 else
-	   state  <= state + 1;
-
-   always @*
-     case(state)
-       0 : ll_data = f18_data[31:24];
-       1 : ll_data = f18_data[23:16];
-       2 : ll_data = f18_data[15:8];
-       3 : ll_data = f18_data[7:0];
-       default : ll_data = f18_data[31:24];
-       endcase // case (state)
-   
-   assign ll_sof 	 = (state==0) & f18_sof;
-   assign ll_eof 	 = f18_eof & (((state==0)&(f18_occ==1)) |
-			       ((state==1)&(f18_occ==2)) |
-			       ((state==2)&(f18_occ==3)) |
-			       (state==3));
-   
-   assign ll_src_rdy 	 = f18_src_rdy_i;
-
-   assign advance 	 = ll_src_rdy & ll_dst_rdy;
-   assign f18_dst_rdy_o  = advance & ((state==3)|ll_eof);
-   assign debug 	 = state;
-   
-endmodule // ll8_to_fifo36
diff --git a/control_lib/newfifo/fifo_2clock.v b/control_lib/newfifo/fifo_2clock.v
index 2ada39fb0..07ae090f2 100644
--- a/control_lib/newfifo/fifo_2clock.v
+++ b/control_lib/newfifo/fifo_2clock.v
@@ -16,21 +16,33 @@ module fifo_2clock
    assign read 	     = src_rdy_o & dst_rdy_i;
 
    generate
-      if(SIZE==9)
-	fifo_xlnx_512x36_2clk mac_tx_fifo_2clk
-	      (.rst(rst),
-	       .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
-	       .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
-      else if(SIZE==11)
-	fifo_xlnx_2Kx36_2clk mac_tx_fifo_2clk
-	      (.rst(rst),
-	       .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
-	       .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
-      else if(SIZE==6)
-	fifo_xlnx_64x36_2clk mac_tx_fifo_2clk
-		   (.rst(rst),
-		    .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
-		    .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+      if(WIDTH==36)
+	if(SIZE==9)
+	  fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
+	       (.rst(rst),
+		.wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+		.rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+	else if(SIZE==11)
+	  fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk 
+		     (.rst(rst),
+		      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+		      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+	else if(SIZE==6)
+	  fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk 
+		     (.rst(rst),
+		      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+		      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+	else
+	  fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
+	       (.rst(rst),
+		.wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+		.rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+      else if((WIDTH==19)|(WIDTH==18))
+	if(SIZE==4)
+	  fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk
+		     (.rst(rst),
+		      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+		      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
    endgenerate
    
    assign occupied  = {{(16-SIZE-1){1'b0}},level_rclk};
diff --git a/coregen/fifo_xlnx_16x19_2clk.ngc b/coregen/fifo_xlnx_16x19_2clk.ngc
new file mode 100644
index 000000000..b12d34d7c
--- /dev/null
+++ b/coregen/fifo_xlnx_16x19_2clk.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
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\ No newline at end of file
diff --git a/coregen/fifo_xlnx_16x19_2clk.v b/coregen/fifo_xlnx_16x19_2clk.v
new file mode 100644
index 000000000..1d633384b
--- /dev/null
+++ b/coregen/fifo_xlnx_16x19_2clk.v
@@ -0,0 +1,169 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2007 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo_xlnx_16x19_2clk.v when simulating
+// the core, fifo_xlnx_16x19_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo_xlnx_16x19_2clk(
+	din,
+	rd_clk,
+	rd_en,
+	rst,
+	wr_clk,
+	wr_en,
+	dout,
+	empty,
+	full,
+	rd_data_count,
+	wr_data_count);
+
+
+input [18 : 0] din;
+input rd_clk;
+input rd_en;
+input rst;
+input wr_clk;
+input wr_en;
+output [18 : 0] dout;
+output empty;
+output full;
+output [4 : 0] rd_data_count;
+output [4 : 0] wr_data_count;
+
+// synthesis translate_off
+
+      FIFO_GENERATOR_V4_3 #(
+		.C_COMMON_CLOCK(0),
+		.C_COUNT_TYPE(0),
+		.C_DATA_COUNT_WIDTH(5),
+		.C_DEFAULT_VALUE("BlankString"),
+		.C_DIN_WIDTH(19),
+		.C_DOUT_RST_VAL("0"),
+		.C_DOUT_WIDTH(19),
+		.C_ENABLE_RLOCS(0),
+		.C_FAMILY("spartan3"),
+		.C_FULL_FLAGS_RST_VAL(1),
+		.C_HAS_ALMOST_EMPTY(0),
+		.C_HAS_ALMOST_FULL(0),
+		.C_HAS_BACKUP(0),
+		.C_HAS_DATA_COUNT(0),
+		.C_HAS_INT_CLK(0),
+		.C_HAS_MEMINIT_FILE(0),
+		.C_HAS_OVERFLOW(0),
+		.C_HAS_RD_DATA_COUNT(1),
+		.C_HAS_RD_RST(0),
+		.C_HAS_RST(1),
+		.C_HAS_SRST(0),
+		.C_HAS_UNDERFLOW(0),
+		.C_HAS_VALID(0),
+		.C_HAS_WR_ACK(0),
+		.C_HAS_WR_DATA_COUNT(1),
+		.C_HAS_WR_RST(0),
+		.C_IMPLEMENTATION_TYPE(2),
+		.C_INIT_WR_PNTR_VAL(0),
+		.C_MEMORY_TYPE(2),
+		.C_MIF_FILE_NAME("BlankString"),
+		.C_MSGON_VAL(1),
+		.C_OPTIMIZATION_MODE(0),
+		.C_OVERFLOW_LOW(0),
+		.C_PRELOAD_LATENCY(0),
+		.C_PRELOAD_REGS(1),
+		.C_PRIM_FIFO_TYPE("512x36"),
+		.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+		.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+		.C_PROG_EMPTY_TYPE(0),
+		.C_PROG_FULL_THRESH_ASSERT_VAL(15),
+		.C_PROG_FULL_THRESH_NEGATE_VAL(14),
+		.C_PROG_FULL_TYPE(0),
+		.C_RD_DATA_COUNT_WIDTH(5),
+		.C_RD_DEPTH(16),
+		.C_RD_FREQ(1),
+		.C_RD_PNTR_WIDTH(4),
+		.C_UNDERFLOW_LOW(0),
+		.C_USE_DOUT_RST(1),
+		.C_USE_ECC(0),
+		.C_USE_EMBEDDED_REG(0),
+		.C_USE_FIFO16_FLAGS(0),
+		.C_USE_FWFT_DATA_COUNT(1),
+		.C_VALID_LOW(0),
+		.C_WR_ACK_LOW(0),
+		.C_WR_DATA_COUNT_WIDTH(5),
+		.C_WR_DEPTH(16),
+		.C_WR_FREQ(1),
+		.C_WR_PNTR_WIDTH(4),
+		.C_WR_RESPONSE_LATENCY(1))
+	inst (
+		.DIN(din),
+		.RD_CLK(rd_clk),
+		.RD_EN(rd_en),
+		.RST(rst),
+		.WR_CLK(wr_clk),
+		.WR_EN(wr_en),
+		.DOUT(dout),
+		.EMPTY(empty),
+		.FULL(full),
+		.RD_DATA_COUNT(rd_data_count),
+		.WR_DATA_COUNT(wr_data_count),
+		.CLK(),
+		.INT_CLK(),
+		.BACKUP(),
+		.BACKUP_MARKER(),
+		.PROG_EMPTY_THRESH(),
+		.PROG_EMPTY_THRESH_ASSERT(),
+		.PROG_EMPTY_THRESH_NEGATE(),
+		.PROG_FULL_THRESH(),
+		.PROG_FULL_THRESH_ASSERT(),
+		.PROG_FULL_THRESH_NEGATE(),
+		.RD_RST(),
+		.SRST(),
+		.WR_RST(),
+		.ALMOST_EMPTY(),
+		.ALMOST_FULL(),
+		.DATA_COUNT(),
+		.OVERFLOW(),
+		.PROG_EMPTY(),
+		.PROG_FULL(),
+		.VALID(),
+		.UNDERFLOW(),
+		.WR_ACK(),
+		.SBITERR(),
+		.DBITERR());
+
+
+// synthesis translate_on
+
+endmodule
+
diff --git a/coregen/fifo_xlnx_16x19_2clk.veo b/coregen/fifo_xlnx_16x19_2clk.veo
new file mode 100644
index 000000000..2e9af1efa
--- /dev/null
+++ b/coregen/fifo_xlnx_16x19_2clk.veo
@@ -0,0 +1,53 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2007 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_xlnx_16x19_2clk YourInstanceName (
+	.din(din), // Bus [18 : 0] 
+	.rd_clk(rd_clk),
+	.rd_en(rd_en),
+	.rst(rst),
+	.wr_clk(wr_clk),
+	.wr_en(wr_en),
+	.dout(dout), // Bus [18 : 0] 
+	.empty(empty),
+	.full(full),
+	.rd_data_count(rd_data_count), // Bus [4 : 0] 
+	.wr_data_count(wr_data_count)); // Bus [4 : 0] 
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_xlnx_16x19_2clk.v when simulating
+// the core, fifo_xlnx_16x19_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/coregen/fifo_xlnx_16x19_2clk.xco b/coregen/fifo_xlnx_16x19_2clk.xco
new file mode 100644
index 000000000..d0f638026
--- /dev/null
+++ b/coregen/fifo_xlnx_16x19_2clk.xco
@@ -0,0 +1,82 @@
+##############################################################
+#
+# Xilinx Core Generator version K.39
+# Date: Fri Sep 11 04:33:27 2009
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -5
+SET verilogsim = True
+SET vhdlsim = False
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 4.3
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=fifo_xlnx_16x19_2clk
+CSET data_count=false
+CSET data_count_width=5
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET fifo_implementation=Independent_Clocks_Distributed_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=15
+CSET full_threshold_negate_value=14
+CSET input_data_width=19
+CSET input_depth=16
+CSET output_data_width=19
+CSET output_depth=16
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=true
+CSET read_data_count_width=5
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=true
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=true
+CSET write_data_count_width=5
+# END Parameters
+GENERATE
+# CRC: 60b85dda
+
diff --git a/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso b/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso
new file mode 100644
index 000000000..f1a6f7899
--- /dev/null
+++ b/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso
@@ -0,0 +1,3 @@
+blkmemdp_v6_2
+blk_mem_gen_v2_6
+fifo_generator_v4_3
diff --git a/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
new file mode 100644
index 000000000..ef33fff67
--- /dev/null
+++ b/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
@@ -0,0 +1,103 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="lin64" product="ISE" version="10.1.03">
+
+  <!--The data in this file is primarily intended for consumption by Xilinx tools.
+    The structure and the elements are likely to change over the next few releases.
+    This means code written to parse this file will need to be revisited each subsequent release.-->
+
+  <application stringID="Xst" timeStamp="Thu Sep 10 21:33:06 2009">
+    <section stringID="XST_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_RAMS" value="1"></item>
+      <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item>
+      <item dataType="int" stringID="XST_COUNTERS" value="2">
+        <item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="2"/>
+      </item>
+      <item dataType="int" stringID="XST_REGISTERS" value="32">
+        <item dataType="int" stringID="XST_1BIT_REGISTER" value="15"/>
+        <item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_4BIT_REGISTER" value="11"/>
+        <item dataType="int" stringID="XST_5BIT_REGISTER" value="2"/>
+      </item>
+      <item dataType="int" stringID="XST_XORS" value="28">
+        <item dataType="int" stringID="XST_1BIT_XOR2" value="28"/>
+      </item>
+    </section>
+    <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_FSMS" value="1"/>
+      <item dataType="int" stringID="XST_RAMS" value="1"></item>
+      <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item>
+      <item dataType="int" stringID="XST_COUNTERS" value="2">
+        <item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="2"/>
+      </item>
+      <item dataType="int" stringID="XST_REGISTERS" value="107">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="107"/>
+      </item>
+      <item dataType="int" stringID="XST_XORS" value="28">
+        <item dataType="int" stringID="XST_1BIT_XOR2" value="28"/>
+      </item>
+    </section>
+    <section stringID="XST_FINAL_REGISTER_REPORT">
+      <item dataType="int" stringID="XST_REGISTERS" value="126">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="126"/>
+      </item>
+    </section>
+    <section stringID="XST_PARTITION_REPORT">
+      <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
+        <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+      </section>
+    </section>
+    <section stringID="XST_FINAL_REPORT">
+      <section stringID="XST_FINAL_RESULTS">
+        <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="/home/matt/coregen/tmp/_cg/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc"/>
+        <item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
+        <item stringID="XST_OPTIMIZATION_GOAL" value="SPEED"/>
+        <item stringID="XST_KEEP_HIERARCHY" value="no"/>
+      </section>
+      <section stringID="XST_DESIGN_STATISTICS">
+        <item stringID="XST_IOS" value="101"/>
+      </section>
+      <section stringID="XST_CELL_USAGE">
+        <item dataType="int" stringID="XST_BELS" value="66">
+          <item dataType="int" stringID="XST_GND" value="1"/>
+          <item dataType="int" stringID="XST_INV" value="2"/>
+          <item dataType="int" stringID="XST_LUT2" value="18"/>
+          <item dataType="int" stringID="XST_LUT2L" value="1"/>
+          <item dataType="int" stringID="XST_LUT3" value="8"/>
+          <item dataType="int" stringID="XST_LUT4" value="30"/>
+          <item dataType="int" stringID="XST_LUT4D" value="3"/>
+          <item dataType="int" stringID="XST_LUT4L" value="3"/>
+        </item>
+        <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="126">
+          <item dataType="int" stringID="XST_FD" value="4"/>
+          <item dataType="int" stringID="XST_FDC" value="40"/>
+          <item dataType="int" stringID="XST_FDCE" value="62"/>
+          <item dataType="int" stringID="XST_FDP" value="10"/>
+          <item dataType="int" stringID="XST_FDPE" value="5"/>
+        </item>
+        <item dataType="int" stringID="XST_RAMS" value="19">
+          <item dataType="int" stringID="XST_RAM16X1D" value="19"/>
+        </item>
+      </section>
+    </section>
+    <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
+      <item stringID="XST_SELECTED_DEVICE" value="3s2000fg456-5"/>
+      <item AVAILABLE="20480" dataType="int" stringID="XST_NUMBER_OF_SLICES" value="96"/>
+      <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="126"/>
+      <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="103"/>
+      <item dataType="int" stringID="XST_NUMBER_USED_AS_LOGIC" value="65"/>
+      <item dataType="int" stringID="XST_NUMBER_USED_AS_RAMS" value="38"/>
+      <item dataType="int" stringID="XST_NUMBER_OF_IOS" value="101"/>
+      <item AVAILABLE="333" dataType="int" stringID="XST_NUMBER_OF_BONDED_IOBS" value="0"/>
+    </section>
+    <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
+      <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+    </section>
+    <section stringID="XST_ERRORS_STATISTICS">
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="73"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="10"/>
+    </section>
+  </application>
+
+</document>
diff --git a/coregen/fifo_xlnx_16x19_2clk_flist.txt b/coregen/fifo_xlnx_16x19_2clk_flist.txt
new file mode 100644
index 000000000..5e1a6ed35
--- /dev/null
+++ b/coregen/fifo_xlnx_16x19_2clk_flist.txt
@@ -0,0 +1,8 @@
+# Output products list for <fifo_xlnx_16x19_2clk>
+fifo_xlnx_16x19_2clk.ngc
+fifo_xlnx_16x19_2clk.v
+fifo_xlnx_16x19_2clk.veo
+fifo_xlnx_16x19_2clk.xco
+fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+fifo_xlnx_16x19_2clk_flist.txt
+fifo_xlnx_16x19_2clk_xmdf.tcl
diff --git a/coregen/fifo_xlnx_16x19_2clk_readme.txt b/coregen/fifo_xlnx_16x19_2clk_readme.txt
new file mode 100644
index 000000000..1b5976555
--- /dev/null
+++ b/coregen/fifo_xlnx_16x19_2clk_readme.txt
@@ -0,0 +1,39 @@
+The following files were generated for 'fifo_xlnx_16x19_2clk' in directory 
+/home/matt/gnuradio.git/usrp2/fpga/coregen/:
+
+fifo_xlnx_16x19_2clk.ngc:
+   Binary Xilinx implementation netlist file containing the information
+   required to implement the module in a Xilinx (R) FPGA.
+
+fifo_xlnx_16x19_2clk.v:
+   Verilog wrapper file provided to support functional simulation.
+   This file contains simulation model customization data that is
+   passed to a parameterized simulation model for the core.
+
+fifo_xlnx_16x19_2clk.veo:
+   VEO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a Verilog design.
+
+fifo_xlnx_16x19_2clk.xco:
+   CORE Generator input file containing the parameters used to
+   regenerate a core.
+
+fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt:
+   Please see the core data sheet.
+
+fifo_xlnx_16x19_2clk_flist.txt:
+   Text file listing all of the output files produced when a customized
+   core was generated in the CORE Generator.
+
+fifo_xlnx_16x19_2clk_readme.txt:
+   Text file indicating the files generated and how they are used.
+
+fifo_xlnx_16x19_2clk_xmdf.tcl:
+   ISE Project Navigator interface file. ISE uses this file to determine
+   how the files output by CORE Generator for the core can be integrated
+   into your ISE project.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl b/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl
new file mode 100644
index 000000000..8d633e9c2
--- /dev/null
+++ b/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl
@@ -0,0 +1,68 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_xlnx_16x19_2clk_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_xlnx_16x19_2clk_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_xlnx_16x19_2clk_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_16x19_2clk
+}
+# ::fifo_xlnx_16x19_2clk_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_xlnx_16x19_2clk_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_16x19_2clk
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
-- 
cgit v1.2.3


From 037332cb6b8618d79e6eb6b20e2a19160e5ace62 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Wed, 30 Sep 2009 17:35:14 -0700
Subject: Copied wb_1master back from quad radio

more sane config options, should be exactly the same memory map
---
 control_lib/wb_1master.v | 318 ++++++++++++++++++++++++++---------------------
 top/u2_core/u2_core.v    | 143 +++++++++------------
 2 files changed, 238 insertions(+), 223 deletions(-)

(limited to 'control_lib')

diff --git a/control_lib/wb_1master.v b/control_lib/wb_1master.v
index e56ba1fb2..fb313efae 100644
--- a/control_lib/wb_1master.v
+++ b/control_lib/wb_1master.v
@@ -38,26 +38,40 @@
 //   Up to 8 slaves share a Wishbone Bus connection to 1 master
 
   module wb_1master
-    #(parameter	s0_addr_w = 4,			// slave 0 address decode width
-      parameter	s0_addr = 4'h0,			// slave 0 address
-      parameter	s1_addr_w = 4 ,			// slave 1 address decode width
-      parameter	s1_addr = 4'h1,			// slave 1 address 
-      parameter	s215_addr_w = 8 ,		// slave 2 to slave 7 address decode width
-      parameter	s2_addr = 8'h92,		// slave 2 address
-      parameter	s3_addr = 8'h93,		// slave 3 address
-      parameter	s4_addr = 8'h94,		// slave 4 address
-      parameter	s5_addr = 8'h95,		// slave 5 address
-      parameter	s6_addr = 8'h96,		// slave 6 address
-      parameter	s7_addr = 8'h97,		// slave 7 address
-      parameter	s8_addr = 8'h98,		// slave 7 address
-      parameter	s9_addr = 8'h99,		// slave 7 address
-      parameter	s10_addr = 8'h9a,		// slave 7 address
-      parameter	s11_addr = 8'h9b,		// slave 7 address
-      parameter	s12_addr = 8'h9c,		// slave 7 address
-      parameter	s13_addr = 8'h9d,		// slave 7 address
-      parameter	s14_addr = 8'h9e,		// slave 7 address
-      parameter	s15_addr = 8'h9f,		// slave 7 address
-      
+    #(parameter	decode_w = 8,			// address decode width
+      parameter	s0_addr = 8'h0,			// slave 0 address
+      parameter	s0_mask = 8'h0,			// slave 0 don't cares
+      parameter	s1_addr = 8'h0,			// slave 1 address
+      parameter	s1_mask = 8'h0,			// slave 1 don't cares
+      parameter	s2_addr = 8'h0,			// slave 2 address
+      parameter	s2_mask = 8'h0,			// slave 2 don't cares
+      parameter	s3_addr = 8'h0,			// slave 3 address
+      parameter	s3_mask = 8'h0,			// slave 3 don't cares
+      parameter	s4_addr = 8'h0,			// slave 4 address
+      parameter	s4_mask = 8'h0,			// slave 4 don't cares
+      parameter	s5_addr = 8'h0,			// slave 5 address
+      parameter	s5_mask = 8'h0,			// slave 5 don't cares
+      parameter	s6_addr = 8'h0,			// slave 6 address
+      parameter	s6_mask = 8'h0,			// slave 6 don't cares
+      parameter	s7_addr = 8'h0,			// slave 7 address
+      parameter	s7_mask = 8'h0,			// slave 7 don't cares
+      parameter	s8_addr = 8'h0,			// slave 8 address
+      parameter	s8_mask = 8'h0,			// slave 8 don't cares
+      parameter	s9_addr = 8'h0,			// slave 9 address
+      parameter	s9_mask = 8'h0,			// slave 9 don't cares
+      parameter	sa_addr = 8'h0,			// slave a address
+      parameter	sa_mask = 8'h0,			// slave a don't cares
+      parameter	sb_addr = 8'h0,			// slave b address
+      parameter	sb_mask = 8'h0,			// slave b don't cares
+      parameter	sc_addr = 8'h0,			// slave c address
+      parameter	sc_mask = 8'h0,			// slave c don't cares
+      parameter	sd_addr = 8'h0,			// slave d address
+      parameter	sd_mask = 8'h0,			// slave d don't cares
+      parameter	se_addr = 8'h0,			// slave e address
+      parameter	se_mask = 8'h0,			// slave e don't cares
+      parameter	sf_addr = 8'h0,			// slave f address
+      parameter	sf_mask = 8'h0,			// slave f don't cares
+            
       parameter	dw = 32,		// Data bus Width
       parameter	aw = 32,		// Address bus Width
       parameter	sw = 4)                 // Number of Select Lines
@@ -188,71 +202,71 @@
        input 		s9_err_i,
        input 		s9_rty_i,
        
-       input [dw-1:0] 	s10_dat_i,
-       output [dw-1:0] 	s10_dat_o,
-       output [aw-1:0] 	s10_adr_o,
-       output [sw-1:0] 	s10_sel_o,
-       output 		s10_we_o,
-       output 		s10_cyc_o,
-       output 		s10_stb_o,
-       input 		s10_ack_i,
-       input 		s10_err_i,
-       input 		s10_rty_i,
+       input [dw-1:0] 	sa_dat_i,
+       output [dw-1:0] 	sa_dat_o,
+       output [aw-1:0] 	sa_adr_o,
+       output [sw-1:0] 	sa_sel_o,
+       output 		sa_we_o,
+       output 		sa_cyc_o,
+       output 		sa_stb_o,
+       input 		sa_ack_i,
+       input 		sa_err_i,
+       input 		sa_rty_i,
        
-       input [dw-1:0] 	s11_dat_i,
-       output [dw-1:0] 	s11_dat_o,
-       output [aw-1:0] 	s11_adr_o,
-       output [sw-1:0] 	s11_sel_o,
-       output 		s11_we_o,
-       output 		s11_cyc_o,
-       output 		s11_stb_o,
-       input 		s11_ack_i,
-       input 		s11_err_i,
-       input 		s11_rty_i,
+       input [dw-1:0] 	sb_dat_i,
+       output [dw-1:0] 	sb_dat_o,
+       output [aw-1:0] 	sb_adr_o,
+       output [sw-1:0] 	sb_sel_o,
+       output 		sb_we_o,
+       output 		sb_cyc_o,
+       output 		sb_stb_o,
+       input 		sb_ack_i,
+       input 		sb_err_i,
+       input 		sb_rty_i,
        
-       input [dw-1:0] 	s12_dat_i,
-       output [dw-1:0] 	s12_dat_o,
-       output [aw-1:0] 	s12_adr_o,
-       output [sw-1:0] 	s12_sel_o,
-       output 		s12_we_o,
-       output 		s12_cyc_o,
-       output 		s12_stb_o,
-       input 		s12_ack_i,
-       input 		s12_err_i,
-       input 		s12_rty_i,
+       input [dw-1:0] 	sc_dat_i,
+       output [dw-1:0] 	sc_dat_o,
+       output [aw-1:0] 	sc_adr_o,
+       output [sw-1:0] 	sc_sel_o,
+       output 		sc_we_o,
+       output 		sc_cyc_o,
+       output 		sc_stb_o,
+       input 		sc_ack_i,
+       input 		sc_err_i,
+       input 		sc_rty_i,
        
-       input [dw-1:0] 	s13_dat_i,
-       output [dw-1:0] 	s13_dat_o,
-       output [aw-1:0] 	s13_adr_o,
-       output [sw-1:0] 	s13_sel_o,
-       output 		s13_we_o,
-       output 		s13_cyc_o,
-       output 		s13_stb_o,
-       input 		s13_ack_i,
-       input 		s13_err_i,
-       input 		s13_rty_i,
+       input [dw-1:0] 	sd_dat_i,
+       output [dw-1:0] 	sd_dat_o,
+       output [aw-1:0] 	sd_adr_o,
+       output [sw-1:0] 	sd_sel_o,
+       output 		sd_we_o,
+       output 		sd_cyc_o,
+       output 		sd_stb_o,
+       input 		sd_ack_i,
+       input 		sd_err_i,
+       input 		sd_rty_i,
        
-       input [dw-1:0] 	s14_dat_i,
-       output [dw-1:0] 	s14_dat_o,
-       output [aw-1:0] 	s14_adr_o,
-       output [sw-1:0] 	s14_sel_o,
-       output 		s14_we_o,
-       output 		s14_cyc_o,
-       output 		s14_stb_o,
-       input 		s14_ack_i,
-       input 		s14_err_i,
-       input 		s14_rty_i,
+       input [dw-1:0] 	se_dat_i,
+       output [dw-1:0] 	se_dat_o,
+       output [aw-1:0] 	se_adr_o,
+       output [sw-1:0] 	se_sel_o,
+       output 		se_we_o,
+       output 		se_cyc_o,
+       output 		se_stb_o,
+       input 		se_ack_i,
+       input 		se_err_i,
+       input 		se_rty_i,
        
-       input [dw-1:0] 	s15_dat_i,
-       output [dw-1:0] 	s15_dat_o,
-       output [aw-1:0] 	s15_adr_o,
-       output [sw-1:0] 	s15_sel_o,
-       output 		s15_we_o,
-       output 		s15_cyc_o,
-       output 		s15_stb_o,
-       input 		s15_ack_i,
-       input 		s15_err_i,
-       input 		s15_rty_i
+       input [dw-1:0] 	sf_dat_i,
+       output [dw-1:0] 	sf_dat_o,
+       output [aw-1:0] 	sf_adr_o,
+       output [sw-1:0] 	sf_sel_o,
+       output 		sf_we_o,
+       output 		sf_cyc_o,
+       output 		sf_stb_o,
+       input 		sf_ack_i,
+       input 		sf_err_i,
+       input 		sf_rty_i
        );
    
    // ////////////////////////////////////////////////////////////////
@@ -278,22 +292,22 @@
        128 : i_dat_s <= s7_dat_i;
        256 : i_dat_s <= s8_dat_i;
        512 : i_dat_s <= s9_dat_i;
-       1024 : i_dat_s <= s10_dat_i;
-       2048 : i_dat_s <= s11_dat_i;
-       4096 : i_dat_s <= s12_dat_i;
-       8192 : i_dat_s <= s13_dat_i;
-       16384 : i_dat_s <= s14_dat_i;
-       32768 : i_dat_s <= s15_dat_i;
+       1024 : i_dat_s <= sa_dat_i;
+       2048 : i_dat_s <= sb_dat_i;
+       4096 : i_dat_s <= sc_dat_i;
+       8192 : i_dat_s <= sd_dat_i;
+       16384 : i_dat_s <= se_dat_i;
+       32768 : i_dat_s <= sf_dat_i;
        default : i_dat_s <= s0_dat_i;
      endcase // case(ssel_dec)
    
    assign 		{m0_ack_o, m0_err_o, m0_rty_o} 
      =  {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i |
-	 s8_ack_i | s9_ack_i | s10_ack_i | s11_ack_i | s12_ack_i | s13_ack_i | s14_ack_i | s15_ack_i ,
+	 s8_ack_i | s9_ack_i | sa_ack_i | sb_ack_i | sc_ack_i | sd_ack_i | se_ack_i | sf_ack_i ,
 	 s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i |
-	 s8_err_i | s9_err_i | s10_err_i | s11_err_i | s12_err_i | s13_err_i | s14_err_i | s15_err_i ,
+	 s8_err_i | s9_err_i | sa_err_i | sb_err_i | sc_err_i | sd_err_i | se_err_i | sf_err_i ,
 	 s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i |
-	 s8_rty_i | s9_rty_i | s10_rty_i | s11_rty_i | s12_rty_i | s13_rty_i | s14_rty_i | s15_rty_i };
+	 s8_rty_i | s9_rty_i | sa_rty_i | sb_rty_i | sc_rty_i | sd_rty_i | se_rty_i | sf_rty_i };
 
    // Slave output interfaces
    assign 		s0_adr_o = m0_adr_i;
@@ -366,65 +380,85 @@
    assign 		s9_cyc_o = m0_cyc_i;
    assign 		s9_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[9];   
    
-   assign 		s10_adr_o = m0_adr_i;
-   assign 		s10_sel_o = m0_sel_i;
-   assign 		s10_dat_o = m0_dat_i;
-   assign 		s10_we_o = m0_we_i;
-   assign 		s10_cyc_o = m0_cyc_i;
-   assign 		s10_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[10];   
+   assign 		sa_adr_o = m0_adr_i;
+   assign 		sa_sel_o = m0_sel_i;
+   assign 		sa_dat_o = m0_dat_i;
+   assign 		sa_we_o = m0_we_i;
+   assign 		sa_cyc_o = m0_cyc_i;
+   assign 		sa_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[10];   
    
-   assign 		s11_adr_o = m0_adr_i;
-   assign 		s11_sel_o = m0_sel_i;
-   assign 		s11_dat_o = m0_dat_i;
-   assign 		s11_we_o = m0_we_i;
-   assign 		s11_cyc_o = m0_cyc_i;
-   assign 		s11_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[11];   
+   assign 		sb_adr_o = m0_adr_i;
+   assign 		sb_sel_o = m0_sel_i;
+   assign 		sb_dat_o = m0_dat_i;
+   assign 		sb_we_o = m0_we_i;
+   assign 		sb_cyc_o = m0_cyc_i;
+   assign 		sb_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[11];   
    
-   assign 		s12_adr_o = m0_adr_i;
-   assign 		s12_sel_o = m0_sel_i;
-   assign 		s12_dat_o = m0_dat_i;
-   assign 		s12_we_o = m0_we_i;
-   assign 		s12_cyc_o = m0_cyc_i;
-   assign 		s12_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[12];   
+   assign 		sc_adr_o = m0_adr_i;
+   assign 		sc_sel_o = m0_sel_i;
+   assign 		sc_dat_o = m0_dat_i;
+   assign 		sc_we_o = m0_we_i;
+   assign 		sc_cyc_o = m0_cyc_i;
+   assign 		sc_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[12];   
    
-   assign 		s13_adr_o = m0_adr_i;
-   assign 		s13_sel_o = m0_sel_i;
-   assign 		s13_dat_o = m0_dat_i;
-   assign 		s13_we_o = m0_we_i;
-   assign 		s13_cyc_o = m0_cyc_i;
-   assign 		s13_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[13];   
+   assign 		sd_adr_o = m0_adr_i;
+   assign 		sd_sel_o = m0_sel_i;
+   assign 		sd_dat_o = m0_dat_i;
+   assign 		sd_we_o = m0_we_i;
+   assign 		sd_cyc_o = m0_cyc_i;
+   assign 		sd_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[13];   
    
-   assign 		s14_adr_o = m0_adr_i;
-   assign 		s14_sel_o = m0_sel_i;
-   assign 		s14_dat_o = m0_dat_i;
-   assign 		s14_we_o = m0_we_i;
-   assign 		s14_cyc_o = m0_cyc_i;
-   assign 		s14_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[14];   
+   assign 		se_adr_o = m0_adr_i;
+   assign 		se_sel_o = m0_sel_i;
+   assign 		se_dat_o = m0_dat_i;
+   assign 		se_we_o = m0_we_i;
+   assign 		se_cyc_o = m0_cyc_i;
+   assign 		se_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[14];   
    
-   assign 		s15_adr_o = m0_adr_i;
-   assign 		s15_sel_o = m0_sel_i;
-   assign 		s15_dat_o = m0_dat_i;
-   assign 		s15_we_o = m0_we_i;
-   assign 		s15_cyc_o = m0_cyc_i;
-   assign 		s15_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[15];   
+   assign 		sf_adr_o = m0_adr_i;
+   assign 		sf_sel_o = m0_sel_i;
+   assign 		sf_dat_o = m0_dat_i;
+   assign 		sf_we_o = m0_we_i;
+   assign 		sf_cyc_o = m0_cyc_i;
+   assign 		sf_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[15];   
    
    // Address decode logic
    // WARNING -- must make sure these are mutually exclusive!
-   assign 		ssel_dec[0] = (m0_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr);
-   assign 		ssel_dec[1] = (m0_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr);
-   assign 		ssel_dec[2] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s2_addr);
-   assign 		ssel_dec[3] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s3_addr);
-   assign 		ssel_dec[4] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s4_addr);
-   assign 		ssel_dec[5] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s5_addr);
-   assign 		ssel_dec[6] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s6_addr);
-   assign 		ssel_dec[7] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s7_addr);
-   assign 		ssel_dec[8] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s8_addr);
-   assign 		ssel_dec[9] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s9_addr);
-   assign 		ssel_dec[10] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s10_addr);
-   assign 		ssel_dec[11] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s11_addr);
-   assign 		ssel_dec[12] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s12_addr);
-   assign 		ssel_dec[13] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s13_addr);
-   assign 		ssel_dec[14] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s14_addr);
-   assign 		ssel_dec[15] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s15_addr);
-   
+
+
+   assign 		ssel_dec[0] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s0_addr) & s0_mask);
+   assign 		ssel_dec[1] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s1_addr) & s1_mask);
+   assign 		ssel_dec[2] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s2_addr) & s2_mask);
+   assign 		ssel_dec[3] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s3_addr) & s3_mask);
+   assign 		ssel_dec[4] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s4_addr) & s4_mask);
+   assign 		ssel_dec[5] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s5_addr) & s5_mask);
+   assign 		ssel_dec[6] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s6_addr) & s6_mask);
+   assign 		ssel_dec[7] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s7_addr) & s7_mask);
+   assign 		ssel_dec[8] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s8_addr) & s8_mask);
+   assign 		ssel_dec[9] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s9_addr) & s9_mask);
+   assign 		ssel_dec[10] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sa_addr) & sa_mask);
+   assign 		ssel_dec[11] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sb_addr) & sb_mask);
+   assign 		ssel_dec[12] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sc_addr) & sc_mask);
+   assign 		ssel_dec[13] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sd_addr) & sd_mask);
+   assign 		ssel_dec[14] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ se_addr) & se_mask);
+   assign 		ssel_dec[15] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sf_addr) & sf_mask);
+
+/*
+   assign 		ssel_dec[0] = (m0_adr_i[aw -1 : aw - decode_w ] == s0_addr);
+   assign 		ssel_dec[1] = (m0_adr_i[aw -1 : aw - decode_w ] == s1_addr);
+   assign 		ssel_dec[2] = (m0_adr_i[aw -1 : aw - decode_w ] == s2_addr);
+   assign 		ssel_dec[3] = (m0_adr_i[aw -1 : aw - decode_w ] == s3_addr);
+   assign 		ssel_dec[4] = (m0_adr_i[aw -1 : aw - decode_w ] == s4_addr);
+   assign 		ssel_dec[5] = (m0_adr_i[aw -1 : aw - decode_w ] == s5_addr);
+   assign 		ssel_dec[6] = (m0_adr_i[aw -1 : aw - decode_w ] == s6_addr);
+   assign 		ssel_dec[7] = (m0_adr_i[aw -1 : aw - decode_w ] == s7_addr);
+   assign 		ssel_dec[8] = (m0_adr_i[aw -1 : aw - decode_w ] == s8_addr);
+   assign 		ssel_dec[9] = (m0_adr_i[aw -1 : aw - decode_w ] == s9_addr);
+   assign 		ssel_dec[10] = (m0_adr_i[aw -1 : aw - decode_w ] == sa_addr);
+   assign 		ssel_dec[11] = (m0_adr_i[aw -1 : aw - decode_w ] == sb_addr);
+   assign 		ssel_dec[12] = (m0_adr_i[aw -1 : aw - decode_w ] == sc_addr);
+   assign 		ssel_dec[13] = (m0_adr_i[aw -1 : aw - decode_w ] == sd_addr);
+   assign 		ssel_dec[14] = (m0_adr_i[aw -1 : aw - decode_w ] == se_addr);
+   assign 		ssel_dec[15] = (m0_adr_i[aw -1 : aw - decode_w ] == sf_addr);
+ */ 
 endmodule // wb_1master
diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v
index f12b5af4d..5718366d5 100755
--- a/top/u2_core/u2_core.v
+++ b/top/u2_core/u2_core.v
@@ -168,57 +168,68 @@ module u2_core
    wire [dw-1:0] m0_dat_o, m0_dat_i;
    wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i,
 		 s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i,
-		 s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, s11_dat_i, s11_dat_o,
-		 s12_dat_i, s12_dat_o, s13_dat_i, s13_dat_o, s14_dat_i, s14_dat_o;
-   wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr, s13_adr, s14_adr;
-   wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel, s13_sel, s14_sel;
-   wire 	 m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack, s13_ack, s14_ack;
-   wire 	 m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb, s13_stb, s14_stb;
-   wire 	 m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc, s13_cyc, s14_cyc;
-   wire 	 m0_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err, s13_err, s14_err;
-   wire 	 m0_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty, s13_rty, s14_rty;
-   wire 	 m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we,s13_we, s14_we;
-   
-   wb_1master #(.s0_addr_w(1),.s0_addr(1'b0),.s1_addr_w(2),.s1_addr(2'b10),
-		.s215_addr_w(6),.s2_addr(6'b1100_00),.s3_addr(6'b1100_01),.s4_addr(6'b1100_10),
-		.s5_addr(6'b1100_11),.s6_addr(6'b1101_00),.s7_addr(6'b1101_01),.s8_addr(6'b1101_10),
-		.s9_addr(6'b1101_11),.s10_addr(6'b1110_00),.s11_addr(6'b1110_01),.s12_addr(6'b1110_10),
-		.s13_addr(6'b1110_11),.s14_addr(6'b1111_00),.s15_addr(6'b1111_01),
+		 s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o,
+		 sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o;
+   wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr;
+   wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel;
+   wire 	 m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack;
+   wire 	 m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb;
+   wire 	 m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc;
+   wire 	 m0_err, m0_rty;
+   wire 	 m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we;
+   
+   wb_1master #(.decode_w(6),
+		.s0_addr(6'b0000_00),.s0_mask(6'b100000),
+		.s1_addr(6'b1000_00),.s1_mask(6'b110000),
+ 		.s2_addr(6'b1100_00),.s2_mask(6'b111111),
+		.s3_addr(6'b1100_01),.s3_mask(6'b111111),
+		.s4_addr(6'b1100_10),.s4_mask(6'b111111),
+		.s5_addr(6'b1100_11),.s5_mask(6'b111111),
+		.s6_addr(6'b1101_00),.s6_mask(6'b111111),
+		.s7_addr(6'b1101_01),.s7_mask(6'b111111),
+		.s8_addr(6'b1101_10),.s8_mask(6'b111111),
+		.s9_addr(6'b1101_11),.s9_mask(6'b111111),
+		.sa_addr(6'b1110_00),.sa_mask(6'b111111),
+		.sb_addr(6'b1110_01),.sb_mask(6'b111111),
+		.sc_addr(6'b1110_10),.sc_mask(6'b111111),
+		.sd_addr(6'b1110_11),.sd_mask(6'b111111),
+		.se_addr(6'b1111_00),.se_mask(6'b111111),
+		.sf_addr(6'b1111_01),.sf_mask(6'b111111),
 		.dw(dw),.aw(aw),.sw(sw)) wb_1master
      (.clk_i(wb_clk),.rst_i(wb_rst),       
       .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
       .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
       .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o	(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
-      .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty),
+      .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0),
       .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o	(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
-      .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty),
+      .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0),
       .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o	(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
-      .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty),
+      .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0),
       .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o	(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
-      .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty),
+      .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0),
       .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o	(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
-      .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty),
+      .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0),
       .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o	(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
-      .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty),
+      .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0),
       .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o	(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
-      .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty),
+      .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0),
       .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o	(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
-      .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty),
+      .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0),
       .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o	(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
-      .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(s8_err),.s8_rty_i(s8_rty),
+      .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0),
       .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o	(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
-      .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(s9_err),.s9_rty_i(s9_rty),
-      .s10_dat_o(s10_dat_o),.s10_adr_o(s10_adr),.s10_sel_o(s10_sel),.s10_we_o(s10_we),.s10_cyc_o(s10_cyc),.s10_stb_o(s10_stb),
-      .s10_dat_i(s10_dat_i),.s10_ack_i(s10_ack),.s10_err_i(s10_err),.s10_rty_i(s10_rty),
-      .s11_dat_o(s11_dat_o),.s11_adr_o(s11_adr),.s11_sel_o(s11_sel),.s11_we_o(s11_we),.s11_cyc_o(s11_cyc),.s11_stb_o(s11_stb),
-      .s11_dat_i(s11_dat_i),.s11_ack_i(s11_ack),.s11_err_i(s11_err),.s11_rty_i(s11_rty),
-      .s12_dat_o(s12_dat_o),.s12_adr_o(s12_adr),.s12_sel_o(s12_sel),.s12_we_o(s12_we),.s12_cyc_o(s12_cyc),.s12_stb_o(s12_stb),
-      .s12_dat_i(s12_dat_i),.s12_ack_i(s12_ack),.s12_err_i(s12_err),.s12_rty_i(s12_rty),
-      .s13_dat_o(s13_dat_o),.s13_adr_o(s13_adr),.s13_sel_o(s13_sel),.s13_we_o(s13_we),.s13_cyc_o(s13_cyc),.s13_stb_o(s13_stb),
-      .s13_dat_i(s13_dat_i),.s13_ack_i(s13_ack),.s13_err_i(s13_err),.s13_rty_i(s13_rty),
-      .s14_dat_o(s14_dat_o),.s14_adr_o(s14_adr),.s14_sel_o(s14_sel),.s14_we_o(s14_we),.s14_cyc_o(s14_cyc),.s14_stb_o(s14_stb),
-      .s14_dat_i(s14_dat_i),.s14_ack_i(s14_ack),.s14_err_i(s14_err),.s14_rty_i(s14_rty),
-      .s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0)  );
+      .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0),
+      .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb),
+      .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0),
+      .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb),
+      .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0),
+      .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb),
+      .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0),
+      .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb),
+      .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0),
+      .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb),
+      .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0),
+      .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0)  );
    
    //////////////////////////////////////////////////////////////////////////////////////////
    // Reset Controller
@@ -300,9 +311,6 @@ module u2_core
 	     .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
 	     .flush_icache(flush_icache));
    
-   assign 	 s0_err = 1'b0;
-   assign 	 s0_rty = 1'b0;
-
    setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
 					 .in(set_data),.out(),.changed(flush_icache));
 
@@ -322,7 +330,7 @@ module u2_core
    buffer_pool buffer_pool
      (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
       .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),   
-      .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty),
+      .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(),
    
       .stream_clk(dsp_clk), .stream_rst(dsp_rst),
       .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
@@ -355,12 +363,10 @@ module u2_core
    spi_top shared_spi
      (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),
       .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
-      .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(s2_err),.wb_int_o(spi_int),
+      .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int),
       .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
       .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
 
-   assign 	 s2_rty = 1'b0;
-   
    // I2C -- Slave #3
    i2c_master_top #(.ARST_LVL(1)) 
      i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
@@ -371,8 +377,6 @@ module u2_core
 	  .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
 
    assign 	 s3_dat_i[31:8] = 24'd0;
-   assign 	 s3_err = 1'b0;
-   assign 	 s3_rty = 1'b0;
    
    // GPIOs -- Slave #4
    nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
@@ -380,8 +384,6 @@ module u2_core
 		 .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
 		 .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
 		 .gpio( {io_tx,io_rx} ) );
-   assign 	 s4_err = 1'b0;
-   assign 	 s4_rty = 1'b0;
 
    // Buffer Pool Status -- Slave #5
    wb_readback_mux buff_pool_status
@@ -398,9 +400,6 @@ module u2_core
       .word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0)
       );
 
-   assign 	 s5_err = 1'b0;
-   assign 	 s5_rty = 1'b0;
-
    // Slave, #6 Ethernet MAC, see below
    
    // Settings Bus -- Slave #7
@@ -409,8 +408,6 @@ module u2_core
       .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack),
       .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data));
    
-   assign 	 s7_err = 1'b0;
-   assign 	 s7_rty = 1'b0;
    assign 	 s7_dat_i = 32'd0;
 
    // Output control lines
@@ -476,9 +473,6 @@ module u2_core
 	.tx_fifo_occupied(),.tx_fifo_full(),.tx_fifo_empty(),
 	.debug0(debug_mac0),.debug1(debug_mac1) );
 
-   assign 	 s6_err = 1'b0;
-   assign 	 s6_rty = 1'b0;
-
    mac_rxfifo_int mac_rxfifo_int
      (.clk(dsp_clk),.rst(dsp_rst),
       .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),
@@ -506,8 +500,6 @@ module u2_core
      (.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
       .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
       .irq(irq) );
-   assign 	 s8_err = 0;
-   assign 	 s8_rty = 0;
  	 
    // /////////////////////////////////////////////////////////////////////////
    // Master Timer, Slave #9
@@ -518,22 +510,17 @@ module u2_core
       .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]),
       .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack),
       .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) );
-   assign 	 s9_err = 0;
-   assign 	 s9_rty = 0;
 
    // /////////////////////////////////////////////////////////////////////////
    // UART, Slave #10
 
    simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart  // depth of 3 is 128 entries
      (.clk_i(wb_clk),.rst_i(wb_rst),
-      .we_i(s10_we),.stb_i(s10_stb),.cyc_i(s10_cyc),.ack_o(s10_ack),
-      .adr_i(s10_adr[4:2]),.dat_i(s10_dat_o),.dat_o(s10_dat_i),
+      .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack),
+      .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i),
       .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int),
       .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o));
    
-   assign 	 s10_err = 0;
-   assign 	 s10_rty = 0;
-   
    // /////////////////////////////////////////////////////////////////////////
    // ATR Controller, Slave #11
 
@@ -544,11 +531,9 @@ module u2_core
    
    atr_controller atr_controller
      (.clk_i(wb_clk),.rst_i(wb_rst),
-      .adr_i(s11_adr[5:0]),.sel_i(s11_sel),.dat_i(s11_dat_o),.dat_o(s11_dat_i),
-      .we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack),
+      .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i),
+      .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack),
       .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) );
-   assign 	 s11_err = 0;
-   assign 	 s11_rty = 0;
    
    // //////////////////////////////////////////////////////////////////////////
    // Time Sync, Slave #12 
@@ -562,14 +547,12 @@ module u2_core
    wire 	 pps_o;
    time_sync time_sync
      (.wb_clk_i(wb_clk),.rst_i(wb_rst),
-      .cyc_i(s12_cyc),.stb_i(s12_stb),.adr_i(s12_adr[4:2]),
-      .we_i(s12_we),.dat_i(s12_dat_o),.dat_o(s12_dat_i),.ack_o(s12_ack),
+      .cyc_i(sc_cyc),.stb_i(sc_stb),.adr_i(sc_adr[4:2]),
+      .we_i(sc_we),.dat_i(sc_dat_o),.dat_o(sc_dat_i),.ack_o(sc_ack),
       .sys_clk_i(dsp_clk),.master_time_o(master_time),
       .pps_posedge(pps_posedge),.pps_negedge(pps_negedge),
       .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out),
       .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) );
-   assign 	 s12_err = 0;
-   assign 	 s12_rty = 0;
 
    // /////////////////////////////////////////////////////////////////////////
    // SD Card Reader / Writer, Slave #13
@@ -577,11 +560,10 @@ module u2_core
    sd_spi_wb sd_spi_wb
      (.clk(wb_clk),.rst(wb_rst),
       .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
-      .wb_cyc_i(s13_cyc),.wb_stb_i(s13_stb),.wb_we_i(s13_we),
-      .wb_adr_i(s13_adr[3:2]),.wb_dat_i(s13_dat_o),.wb_dat_o(s13_dat_i),
-      .wb_ack_o(s13_ack) );
-   assign 	 s13_err = 0;
-   assign 	 s13_rty = 0;
+      .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we),
+      .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o),.wb_dat_o(sd_dat_i),
+      .wb_ack_o(sd_ack) );
+
    // /////////////////////////////////////////////////////////////////////////
    // DSP
    wire [31:0] 	 sample_rx, sample_tx;
@@ -655,8 +637,8 @@ module u2_core
 
    wb_bridge_16_32 bridge
      (.wb_clk(wb_clk),.wb_rst(wb_rst),
-      .A_cyc_i(s14_cyc),.A_stb_i(s14_stb),.A_we_i(s14_we),.A_sel_i(s14_sel),
-      .A_adr_i(s14_adr),.A_dat_i(s14_dat_o),.A_dat_o(s14_dat_i),.A_ack_o(s14_ack),
+      .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel),
+      .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack),
       .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel),
       .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack));
 
@@ -668,7 +650,6 @@ module u2_core
       .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn),
       .sram_mode(),.sram_zz() );
 
-   assign      s14_err = 0; assign s14_rty = 0;
    assign      RAM_CE1n = 0;
    assign      RAM_D[17:16] = 2'bzz;
    
-- 
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