From 09951ed9ba4758cc7cced26c1f673545284c5cf3 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Wed, 2 Sep 2009 17:56:26 -0700
Subject: major cleanup of 2 clock fifos

---
 control_lib/newfifo/.gitignore            |   1 +
 control_lib/newfifo/fifo_2clock.v         |  32 +++---
 control_lib/newfifo/fifo_2clock_cascade.v |  44 +++++----
 control_lib/newfifo/fifo_new_tb.v         | 158 ------------------------------
 control_lib/newfifo/fifo_tb.v             | 158 ++++++++++++++++++++++++++++++
 5 files changed, 206 insertions(+), 187 deletions(-)
 create mode 100644 control_lib/newfifo/.gitignore
 delete mode 100644 control_lib/newfifo/fifo_new_tb.v
 create mode 100644 control_lib/newfifo/fifo_tb.v

(limited to 'control_lib/newfifo')

diff --git a/control_lib/newfifo/.gitignore b/control_lib/newfifo/.gitignore
new file mode 100644
index 000000000..cba7efc8e
--- /dev/null
+++ b/control_lib/newfifo/.gitignore
@@ -0,0 +1 @@
+a.out
diff --git a/control_lib/newfifo/fifo_2clock.v b/control_lib/newfifo/fifo_2clock.v
index 23a6f693c..40c479db7 100644
--- a/control_lib/newfifo/fifo_2clock.v
+++ b/control_lib/newfifo/fifo_2clock.v
@@ -1,23 +1,31 @@
 
-module newfifo_2clock
-  #(parameter DWIDTH=32, AWIDTH=9)
-  (input wclk, input [DWIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output reg [AWIDTH-1:0] level_wclk,
-   input rclk, output [DWIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output reg [AWIDTH-1:0] level_rclk,
-   input arst);
+// FIXME ignores the AWIDTH (fifo size) parameter
 
-   wire full, empty, write, read;
+module fifo_2clock
+  #(parameter WIDTH=32, SIZE=9)
+   (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space,
+    input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied,
+    input arst);
+   
+   wire [SIZE-1:0] level_rclk, level_wclk;
+   wire 	   full, empty, write, read;
 
    assign dst_rdy_o  = ~full;
    assign src_rdy_o  = ~empty;
    assign write      = src_rdy_i & dst_rdy_o;
    assign read 	     = src_rdy_o & dst_rdy_i;
-
-//`define USE_XLNX_FIFO 1
-`ifdef USE_XLNX_FIFO
+   
    fifo_xlnx_512x36_2clk mac_tx_fifo_2clk
      (.rst(rst),
-      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(fifo_occupied[8:0]),
-      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count() );   
+      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+
+   assign occupied  = {{(16-SIZE){1'b0}},level_rclk};
+   assign space = ((1<<SIZE)-1)-level_wclk;
+   
+endmodule // fifo_2clock
+
+/*
 `else
    // ISE sucks, so the following doesn't work properly
 
@@ -80,3 +88,5 @@ module newfifo_2clock
      level_rclk <= wr_addr_rclk - rd_addr;
 `endif
 endmodule // fifo_2clock
+
+*/
diff --git a/control_lib/newfifo/fifo_2clock_cascade.v b/control_lib/newfifo/fifo_2clock_cascade.v
index 2abbbf3b5..8d8a47954 100644
--- a/control_lib/newfifo/fifo_2clock_cascade.v
+++ b/control_lib/newfifo/fifo_2clock_cascade.v
@@ -1,27 +1,35 @@
 
-module cascadefifo_2clock
-  #(parameter DWIDTH=32, AWIDTH=9)
-    (input wclk, input [DWIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [AWIDTH-1:0] level_wclk,
-     input rclk, output [DWIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [AWIDTH-1:0] level_rclk,
-     input arst);
-
-   wire [DWIDTH-1:0] data_int1, data_int2;
-   wire src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2;
+module fifo_2clock_cascade
+  #(parameter WIDTH=32, SIZE=9)
+   (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space,
+    input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied,
+    input arst);
+   
+   wire [WIDTH-1:0] data_int1, data_int2;
+   wire 	    src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2;
+   wire [SIZE-1:0]  level_wclk, level_rclk;
+   wire [4:0] 	    s1_space, s1_occupied, s2_space, s2_occupied;
+   wire [15:0] 	    l_space, l_occupied;
    
-   fifo_short #(.WIDTH(DWIDTH)) shortfifo
+   fifo_short #(.WIDTH(WIDTH)) shortfifo
      (.clk(wclk), .reset(arst), .clear(0),
       .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
-      .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1) );
+      .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1),
+      .space(s1_space), .occupied(s1_occupied) );
    
-   newfifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock
-     (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .level_wclk(level_wclk),
-      .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .level_rclk(level_rclk),
+   fifo_2clock #(.DWIDTH(WIDTH),.SIZE(SIZE)) fifo_2clock
+     (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .space(l_space),
+      .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .occupied(l_occupied),
       .arst(arst) );
-
-   fifo_short #(.WIDTH(DWIDTH)) shortfifo2
+   
+   fifo_short #(.WIDTH(WIDTH)) shortfifo2
      (.clk(rclk), .reset(arst), .clear(0),
       .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
-      .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i) );
-   
-endmodule // fifo_2clock_casc
+      .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
+      .space(s2_space), .occupied(s2_occupied));
 
+   // Be conservative -- Only advertise space from input side of fifo, occupied from output side
+   assign 	    space = {11'b0,s1_space} + l_space;
+   assign 	    occupied = {11'b0,s2_occupied} + l_occupied;
+   
+endmodule // fifo_2clock_cascade
diff --git a/control_lib/newfifo/fifo_new_tb.v b/control_lib/newfifo/fifo_new_tb.v
deleted file mode 100644
index f561df7fa..000000000
--- a/control_lib/newfifo/fifo_new_tb.v
+++ /dev/null
@@ -1,158 +0,0 @@
-module fifo_new_tb();
-   
-   reg clk = 0;
-   reg rst = 1;
-   reg clear = 0;
-   initial #1000 rst = 0;
-   always #50 clk = ~clk;
-   
-   reg [31:0] f36_data = 0;
-   reg [1:0] f36_occ = 0;
-   reg f36_sof = 0, f36_eof = 0;
-   
-   wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data};
-   reg src_rdy_f36i  = 0;
-   wire dst_rdy_f36i;
-
-   wire [35:0] f36_out, f36_out2;
-   wire src_rdy_f36o;
-   reg dst_rdy_f36o  = 0;
-   
-   //fifo_cascade #(.WIDTH(36), .SIZE(4)) fifo_cascade36
-   //fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36
-
-   wire i1_sr, i1_dr;
-   wire i2_sr, i2_dr;
-   wire i3_sr, i3_dr;
-   reg i4_dr = 0;
-   wire i4_sr;
-      
-   wire [35:0] i1, i4;
-   wire [18:0] i2, i3;
-   
-   wire [7:0] ll_data;
-   wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n;
-   
-   fifo_short #(.WIDTH(36)) fifo_short1
-     (.clk(clk),.reset(rst),.clear(clear),
-      .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
-      .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) );
-
-   fifo36_to_fifo19 fifo36_to_fifo19
-     (.clk(clk),.reset(rst),.clear(clear),
-      .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr),
-      .f19_dataout(i2),.f19_src_rdy_o(i2_sr),.f19_dst_rdy_i(i2_dr) );
-
-   fifo19_to_ll8 fifo19_to_ll8
-     (.clk(clk),.reset(rst),.clear(clear),
-      .f19_data(i2),.f19_src_rdy_i(i2_sr),.f19_dst_rdy_o(i2_dr),
-      .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
-      .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n));
-
-   ll8_to_fifo19 ll8_to_fifo19
-     (.clk(clk),.reset(rst),.clear(clear),
-      .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
-      .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n),
-      .f19_data(i3),.f19_src_rdy_o(i3_sr),.f19_dst_rdy_i(i3_dr) );
-
-   fifo19_to_fifo36 fifo19_to_fifo36
-     (.clk(clk),.reset(rst),.clear(clear),
-      .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr),
-      .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) );
-     
-   task ReadFromFIFO36;
-      begin
-	 $display("Read from FIFO36");
-	 #1 i4_dr <= 1;
-	 while(1)
-	   begin
-	      while(~i4_sr)
-		@(posedge clk);
-	      $display("Read: %h",i4);
-	      @(posedge clk);
-	   end
-      end
-   endtask // ReadFromFIFO36
-
-   reg [15:0] count;
-   task PutPacketInFIFO36;
-      input [31:0] data_start;
-      input [31:0] data_len;
-      begin
-	 count 	      <= 4;
-	 src_rdy_f36i <= 1;
-	 f36_data     <= data_start;
-	 f36_sof      <= 1;
-	 f36_eof      <= 0;
-	 f36_occ      <= 0;
-	
-	 $display("Put Packet in FIFO36");
-	 while(~dst_rdy_f36i)
-	   @(posedge clk);
-	 @(posedge clk);
-	 $display("PPI_FIFO36: Entered First Line");
-	 f36_sof <= 0;
-	 while(count+4 < data_len)
-	   begin
-	      f36_data <= f36_data + 32'h01010101;
-	      count    <= count + 4;
-	      while(~dst_rdy_f36i)
-		@(posedge clk);
-	      @(posedge clk);
-	      $display("PPI_FIFO36: Entered New Line");
-	   end
-	 f36_data  <= f36_data + 32'h01010101;
-	 f36_eof   <= 1;
-	 if(count + 4 == data_len)
-	   f36_occ <= 0;
-	 else if(count + 3 == data_len)
-	   f36_occ <= 3;
-	 else if(count + 2 == data_len)
-	   f36_occ <= 2;
-	 else
-	   f36_occ <= 1;
-	 while(~dst_rdy_f36i)
-	   @(posedge clk);
-	 @(posedge clk);
-	 f36_occ      <= 0;
-	 f36_eof      <= 0;
-	 f36_data     <= 0;
-	 src_rdy_f36i <= 0;
-	 $display("PPI_FIFO36: Entered Last Line");
-      end
-   endtask // PutPacketInFIFO36
-   
-   initial $dumpfile("fifo_new_tb.vcd");
-   initial $dumpvars(0,fifo_new_tb);
-
-   initial
-     begin
-	@(negedge rst);
-	//#10000;
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	ReadFromFIFO36;
-     end
-   
-   initial
-     begin
-	@(negedge rst);
-	@(posedge clk);
-	@(posedge clk);
-	PutPacketInFIFO36(32'hA0B0C0D0,12);
-	@(posedge clk);
-	@(posedge clk);
-	#10000;
-	@(posedge clk);
-	PutPacketInFIFO36(32'hE0F0A0B0,36);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-     end
-
-   initial #20000 $finish;
-endmodule // longfifo_tb
diff --git a/control_lib/newfifo/fifo_tb.v b/control_lib/newfifo/fifo_tb.v
new file mode 100644
index 000000000..f561df7fa
--- /dev/null
+++ b/control_lib/newfifo/fifo_tb.v
@@ -0,0 +1,158 @@
+module fifo_new_tb();
+   
+   reg clk = 0;
+   reg rst = 1;
+   reg clear = 0;
+   initial #1000 rst = 0;
+   always #50 clk = ~clk;
+   
+   reg [31:0] f36_data = 0;
+   reg [1:0] f36_occ = 0;
+   reg f36_sof = 0, f36_eof = 0;
+   
+   wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data};
+   reg src_rdy_f36i  = 0;
+   wire dst_rdy_f36i;
+
+   wire [35:0] f36_out, f36_out2;
+   wire src_rdy_f36o;
+   reg dst_rdy_f36o  = 0;
+   
+   //fifo_cascade #(.WIDTH(36), .SIZE(4)) fifo_cascade36
+   //fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36
+
+   wire i1_sr, i1_dr;
+   wire i2_sr, i2_dr;
+   wire i3_sr, i3_dr;
+   reg i4_dr = 0;
+   wire i4_sr;
+      
+   wire [35:0] i1, i4;
+   wire [18:0] i2, i3;
+   
+   wire [7:0] ll_data;
+   wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n;
+   
+   fifo_short #(.WIDTH(36)) fifo_short1
+     (.clk(clk),.reset(rst),.clear(clear),
+      .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
+      .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) );
+
+   fifo36_to_fifo19 fifo36_to_fifo19
+     (.clk(clk),.reset(rst),.clear(clear),
+      .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr),
+      .f19_dataout(i2),.f19_src_rdy_o(i2_sr),.f19_dst_rdy_i(i2_dr) );
+
+   fifo19_to_ll8 fifo19_to_ll8
+     (.clk(clk),.reset(rst),.clear(clear),
+      .f19_data(i2),.f19_src_rdy_i(i2_sr),.f19_dst_rdy_o(i2_dr),
+      .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
+      .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n));
+
+   ll8_to_fifo19 ll8_to_fifo19
+     (.clk(clk),.reset(rst),.clear(clear),
+      .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
+      .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n),
+      .f19_data(i3),.f19_src_rdy_o(i3_sr),.f19_dst_rdy_i(i3_dr) );
+
+   fifo19_to_fifo36 fifo19_to_fifo36
+     (.clk(clk),.reset(rst),.clear(clear),
+      .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr),
+      .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) );
+     
+   task ReadFromFIFO36;
+      begin
+	 $display("Read from FIFO36");
+	 #1 i4_dr <= 1;
+	 while(1)
+	   begin
+	      while(~i4_sr)
+		@(posedge clk);
+	      $display("Read: %h",i4);
+	      @(posedge clk);
+	   end
+      end
+   endtask // ReadFromFIFO36
+
+   reg [15:0] count;
+   task PutPacketInFIFO36;
+      input [31:0] data_start;
+      input [31:0] data_len;
+      begin
+	 count 	      <= 4;
+	 src_rdy_f36i <= 1;
+	 f36_data     <= data_start;
+	 f36_sof      <= 1;
+	 f36_eof      <= 0;
+	 f36_occ      <= 0;
+	
+	 $display("Put Packet in FIFO36");
+	 while(~dst_rdy_f36i)
+	   @(posedge clk);
+	 @(posedge clk);
+	 $display("PPI_FIFO36: Entered First Line");
+	 f36_sof <= 0;
+	 while(count+4 < data_len)
+	   begin
+	      f36_data <= f36_data + 32'h01010101;
+	      count    <= count + 4;
+	      while(~dst_rdy_f36i)
+		@(posedge clk);
+	      @(posedge clk);
+	      $display("PPI_FIFO36: Entered New Line");
+	   end
+	 f36_data  <= f36_data + 32'h01010101;
+	 f36_eof   <= 1;
+	 if(count + 4 == data_len)
+	   f36_occ <= 0;
+	 else if(count + 3 == data_len)
+	   f36_occ <= 3;
+	 else if(count + 2 == data_len)
+	   f36_occ <= 2;
+	 else
+	   f36_occ <= 1;
+	 while(~dst_rdy_f36i)
+	   @(posedge clk);
+	 @(posedge clk);
+	 f36_occ      <= 0;
+	 f36_eof      <= 0;
+	 f36_data     <= 0;
+	 src_rdy_f36i <= 0;
+	 $display("PPI_FIFO36: Entered Last Line");
+      end
+   endtask // PutPacketInFIFO36
+   
+   initial $dumpfile("fifo_new_tb.vcd");
+   initial $dumpvars(0,fifo_new_tb);
+
+   initial
+     begin
+	@(negedge rst);
+	//#10000;
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	ReadFromFIFO36;
+     end
+   
+   initial
+     begin
+	@(negedge rst);
+	@(posedge clk);
+	@(posedge clk);
+	PutPacketInFIFO36(32'hA0B0C0D0,12);
+	@(posedge clk);
+	@(posedge clk);
+	#10000;
+	@(posedge clk);
+	PutPacketInFIFO36(32'hE0F0A0B0,36);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+     end
+
+   initial #20000 $finish;
+endmodule // longfifo_tb
-- 
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